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https://github.com/ACreTeam/ac-decomp
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Cuyler36
443 lines
18 KiB
C
443 lines
18 KiB
C
#ifndef KS_NES_COMMON_H
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#define KS_NES_COMMON_H
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#include "types.h"
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#include "dolphin/os/OSTime.h"
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#include "libultra/libultra.h"
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#include <dolphin/mtx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define KS_NES_WIDTH 256
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#define KS_NES_HEIGHT 228
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#define KS_NES_SCANLINE_COUNT 240 // 228 visible + 8 pre-render + 8 post-render
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#define KS_NES_SCANLINE_SPRITE_OVERDRAW_COUNT (KS_NES_SCANLINE_COUNT + 32) // 272
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#define KS_NES_CENTER_X (KS_NES_WIDTH / 2)
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#define KS_NES_CENTER_Y (KS_NES_SCANLINE_SPRITE_OVERDRAW_COUNT / 2)
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#define KS_NES_OAM_TABLE_SIZE 64
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#define CHR_TO_I8_BUF_SIZE 0x100000
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#define KS_NES_NESFILE_HEADER_SIZE 0x10
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#define KS_NES_PRGROM_SIZE 0x80000 // 512kb for MMC3
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#define KS_NES_CHRROM_SIZE 0x40000 // 256kb for MMC3
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#define KS_NES_CHRRAM_SIZE 0x2000 // 8kb
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#define KS_NES_BBRAM_SIZE 0x8000 // 32kb, battery backed-up ram
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#define KS_NES_NOISE_DATA_SIZE 0x7F000
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#define KS_NES_DRAW_RESULT_BUF_SIZE 0x1C800
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#define KS_NES_WRAM_SIZE 0x800 // 2kb
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#define KS_NES_PPU_NAMETABLE_RAM_SIZE 0x800 // 2kb
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#define KS_NES_EMU_STACK_SIZE 0x1000 // 4kb for thread stack
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#define KS_NES_BYTES_PER_KB (1024)
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#define KS_NES_TO_KB(b) ((f32)b * (1.0f / (f32)KS_NES_BYTES_PER_KB))
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// NES PPU Control Register ($2000) flags
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#define KS_NES_PPU_CTRL_NAMETABLE_MASK 0x03 // Nametable select (0-3)
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#define KS_NES_PPU_CTRL_NAMETABLE_0 0x00 // Nametable at $2000
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#define KS_NES_PPU_CTRL_NAMETABLE_1 0x01 // Nametable at $2400
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#define KS_NES_PPU_CTRL_NAMETABLE_2 0x02 // Nametable at $2800
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#define KS_NES_PPU_CTRL_NAMETABLE_3 0x03 // Nametable at $2C00
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#define KS_NES_PPU_CTRL_VRAM_INCREMENT 0x04 // VRAM address increment (0=add 1 across, 1=add 32 down)
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#define KS_NES_PPU_CTRL_SPRITE_PATTERN 0x08 // Sprite pattern table for 8x8 sprites (0=$0000, 1=$1000)
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#define KS_NES_PPU_CTRL_BG_PATTERN 0x10 // Background pattern table (0=$0000, 1=$1000)
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#define KS_NES_PPU_CTRL_SPRITE_SIZE 0x20 // Sprite size (0=8x8, 1=8x16)
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#define KS_NES_PPU_CTRL_MASTER_SLAVE 0x40 // PPU master/slave select
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#define KS_NES_PPU_CTRL_NMI_ENABLE 0x80 // Generate NMI at start of vertical blanking
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// Sprite sizes
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#define KS_NES_PPU_CTRL_SPRITE_SIZE_8x8 0x00 // 8x8 sprite size
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#define KS_NES_PPU_CTRL_SPRITE_SIZE_8x16 0x20 // 8x16 sprite size
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// NES PPU Mask Register ($2001) flags
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#define KS_NES_PPU_MASK_GREYSCALE 0x01 // Greyscale mode
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#define KS_NES_PPU_MASK_SHOW_BG_LEFT 0x02 // Show background in leftmost 8 pixels
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#define KS_NES_PPU_MASK_SHOW_SPRITES_LEFT 0x04 // Show sprites in leftmost 8 pixels
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#define KS_NES_PPU_MASK_SHOW_BG 0x08 // Enable background rendering
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#define KS_NES_PPU_MASK_SHOW_SPRITES 0x10 // Enable sprite rendering
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#define KS_NES_PPU_MASK_EMPHASIZE_RED 0x20 // Emphasize red channel
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#define KS_NES_PPU_MASK_EMPHASIZE_GREEN 0x40 // Emphasize green channel
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#define KS_NES_PPU_MASK_EMPHASIZE_BLUE 0x80 // Emphasize blue channel
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// NES PPU Status Register ($2002) flags
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#define KS_NES_PPU_STATUS_FLG_SPRITE_OVERFLOW (1 << 5) // 0x20
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#define KS_NES_PPU_STATUS_FLG_SPRITE_ZERO_HIT (1 << 6) // 0x40
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#define KS_NES_PPU_STATUS_FLG_VBLANK (1 << 7) // 0x80
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// Combined masks used in the codebase
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// All color modification bits (greyscale + RGB emphasis)
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#define KS_NES_PPU_MASK_COLOR_EFFECTS (KS_NES_PPU_MASK_GREYSCALE | KS_NES_PPU_MASK_EMPHASIZE_RED | KS_NES_PPU_MASK_EMPHASIZE_GREEN | KS_NES_PPU_MASK_EMPHASIZE_BLUE) // 0xE1
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// Sprites enabled + leftmost sprites
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#define KS_NES_PPU_MASK_SPRITES_COMBINED (KS_NES_PPU_MASK_SHOW_SPRITES_LEFT | KS_NES_PPU_MASK_SHOW_SPRITES) // 0x14
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// Timer IRQ control register @ 0x4022
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#define KS_NES_FDS_TIMER_CTRL_FLG_IRQ_REPEAT (1 << 0) // 0 = don't repeat, 1 = repeat
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#define KS_NES_FDS_TIMRE_CTRL_FLG_IRQ_ENABLE (1 << 1) // 0 = disabled, 1 = enabled
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// Master IO register @ 0x4023
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#define KS_NES_FDS_MASTER_IO_FLG_ENABLE_DISK_REGS (1 << 0) // enable disk I/O registers
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#define KS_NES_FDS_MASTER_IO_FLG_ENABLE_SOUND_REGS (1 << 1) // enable sound I/O registers
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// FDS Control register @ 0x4025
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#define KS_NES_FDS_CTRL_FLG_TRANSFER_RESET (1 << 0) // 1 = reset transfer timing state
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#define KS_NES_FDS_CTRL_FLG_MOTOR (1 << 1) // 0 = start, 1 = stop
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#define KS_NES_FDS_CTRL_FLG_TRANSFER_MODE (1 << 2) // 0 = write, 1 = read
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#define KS_NES_FDS_CTRL_FLG_NAMETABLE_MODE (1 << 3) // 0 = horizontal (vertical mirroring), 1 = vertical (horizontal mirroring)
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#define KS_NES_FDS_CTRL_FLG_CRC_TRANSFER (1 << 4) // 1 = transfer CRC value
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#define KS_NES_FDS_CTRL_FLG_5 (1 << 5)// unknown, NESDev says it's always 1
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#define KS_NES_FDS_CTRL_FLG_CRC_ENABLE (1 << 6) // 0 = disable/reset, 1 = enable
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#define KS_NES_FDS_CTRL_FLG_INTERRUPT_ENABLE (1 << 7) // 1 = generate IRQ every time byte transfer flag is raised
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// OAM Tile/Index Flags
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#define KS_NES_OAM_TILE_BANK 0x01
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#define KS_NES_OAM_TILE_IDX 0xFE
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// OAM Attribute Flags
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#define KS_NES_OAM_ATTR_PALETTE_MASK 0x03
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#define KS_NES_OAM_ATTR_PRIORITY (1 << 5) // 0x20, 0 = in front of background, 1 = behind background
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#define KS_NES_OAM_ATTR_FLIP_HORIZONTAL (1 << 6) // 0x40, 0 = normal, 1 = flip horizontally
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#define KS_NES_OAM_ATTR_FLIP_VERTICAL (1 << 7) // 0x80, 0 = normal, 1 = flip vertically
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// Misc
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#define KS_NES_SPRITES_PER_SCANLINE 8
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// Mapper definitions
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#define KS_NES_MAPPER_NROM 0
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#define KS_NES_MAPPER_MMC1 1
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#define KS_NES_MAPPER_UxROM 2
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#define KS_NES_MAPPER_CNROM 3
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#define KS_NES_MAPPER_MMC3 4
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#define KS_NES_MAPPER_MMC5 5
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#define KS_NES_MAPPER_MMC2 9
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#define KS_NES_MAPPER_MMC4 10
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#define KS_NES_MAPPER_KONAMI_VRC6A 24
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#define KS_NES_MAPPER_KONAMI_VRC6B 26
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// Emulator flags
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#define KS_NES_FLAG_NINES_OVER_MODE (1 << 13) // 0x2000, enables "nines over" mode which allows drawing more than 8 sprites per scanline
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typedef struct ksNesPPUScanlineState {
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u8* nametable_ptrs[2];
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// Either chr_bank_sprite or chr_bank_bg_mmc3 is used depending on mapper type and CPU cycle
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union {
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u8 chr_bank_sprite[8];
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u32 chr_bank_bg_mmc3[2]; // used in ksNesDrawMakeBGIndTex when the scanline column is >= 9.
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};
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u32 chr_bank_bg[2];
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u8 ppu_ctrl;
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u8 ppumask_flags;
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u8 fine_x_and_next;
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u8 vram_addr_coarse_x;
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u8 vram_addr_y;
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// MMC5-only state
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u8 mmc5_ext_mode;
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u8 chr_bank_ext_upper_sprite;
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u8 chr_bank_ext_upper_bg;
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} ksNesPPUScanlineState; // size == 0x20
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typedef struct ksNesSpriteQuadData {
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u8 y_and_v_pairs[32]; // Pairs of (Y position, texture V coord) for quad segments
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// Each quad segment uses 4 bytes: y_top, v_top, y_bottom, v_bottom
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// Supports up to 8 quad segments per sprite
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} ksNesSpriteQuadData; // size = 0x20
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typedef struct ksNesOAMEntry {
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u8 y_pos;
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u8 tile_index;
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u8 attributes;
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u8 x_pos;
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} ksNesOAMEntry;
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typedef struct ksNesDrawCtx {
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/* 0x0000 */ union {
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u8 sprite_scanline_limit[KS_NES_SCANLINE_COUNT]; // tracks the number of sprites that have been drawn on each scanline
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u8 scanline_y_coords[2 * 256]; // tracks the Y coordinate of the top & bottom of each scanline
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};
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/* 0x0200 */ u8 mmc2_scanline_latch_tiles[KS_NES_SCANLINE_COUNT + 16]; // tracks which tiles should be accessible on each scanline based on MMC2 latch settings
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/* 0x0300 */ u8 sprite_vertex_count[KS_NES_OAM_TABLE_SIZE];
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/* 0x0340 */ ksNesSpriteQuadData sprite_quad_data[KS_NES_OAM_TABLE_SIZE];
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/* 0x0B40 */ ksNesPPUScanlineState ppu_scanline_regs[KS_NES_SCANLINE_COUNT];
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/* 0x2940 */ ksNesOAMEntry OAMTable[KS_NES_OAM_TABLE_SIZE];
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/* 0x2A40 */ u8 post_process_lut[0x800];
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/* 0x3240 */ u8 bg_tile_index_texture[(36 * 256) * 2]; // IA8 texture, holds information about the background tile indices and pattern table data
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/* 0x7840 */ u8 bg_palette_attr_texture[(40 * 256) / 2]; // I4 texture, holds background palette attributes
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/* 0x8E40 */ u8 sprite_indirect_lut[(16 * 4) * 2]; // 4x16 texture IA8, handles indirect tex coords, for mirroring and sized sprites
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/* 0x8EC0 */ u8 sprite_chr_bank_lut[(5 * 4) * 2]; // 8x4 IA8 sprite CHR bank lookup table -- @ BUG - this is setup as a 5x4 IA8 texture, but gets loaded as 8x4.
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/* 0x8EE8 */ Mtx34 draw_mtx;
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} ksNesDrawCtx;
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typedef struct ksNesCommonWorkObj {
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/* 0x0000 */ u8* nesromp;
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/* 0x0004 */ u8* noise_bufp;
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/* 0x0008 */ size_t chr_to_i8_buf_size;
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/* 0x000C */ u8* chr_to_u8_bufp;
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/* 0x0010 */ u8* result_bufp;
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/* 0x0014 */ int _0014;
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/* 0x0018 */ int _0018;
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/* 0x001C */ u8 frames;
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/* 0x001D */ u8 _001D;
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/* 0x001E */ u8 _001E;
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/* 0x001F */ u8 _001F;
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/* 0x0020 */ u32 pads[4];
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/* 0x0030 */ u32 _0030;
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/* 0x0034 */ u32 _0034;
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/* 0x0038 */ u32 _0038;
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/* 0x003C */ u8 _003C[0x0048 - 0x003C];
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/* 0x0048 */ size_t prg_size;
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/* 0x004C */ u8 _004C[0x0060 - 0x004C];
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/* 0x0060 */ ksNesDrawCtx draw_ctx;
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} ksNesCommonWorkObj;
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typedef struct ksNesStateObj {
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/* 0x0000 */ u8 wram[KS_NES_WRAM_SIZE];
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/* 0x0800 */ u8 ppu_nametable_ram[KS_NES_PPU_NAMETABLE_RAM_SIZE];
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/* 0x1000 */ u8 cartridge_nametable_ram[28];
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/* 0x101C */ u8 primary_oam[0x100];
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/* 0x111C */ u8 _pad[4]; // this might not exist and instead the next member might be ATTRIBUTE_ALIGN(16/32)
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/* 0x1120 */ u8 mmc5_extension_ram[0x400];
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// these are all function pointers.
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// leaving these as void pointers until we figure out the function signature.
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/* 0x1520 */ void* store_ppu_func[8]; // ksNesStorePPUFuncTblDefault
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/* 0x1540 */ void* store_io_func[0x28]; // ksNesStoreIOFuncTblDefault
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/* 0x15E0 */ void* store_func[8]; // ksNesStoreFuncTblDefault
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/* 0x1600 */ void* load_func[8]; // ksNesLoadFuncTblDefault
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/* 0x1620 */ void* load_io_func[0x18]; // ksNesLoadIOFuncTblDefault
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/* 0x1680 */ u8* cpu_0000_1fff; // work RAM and its mirrors
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/* 0x1684 */ u8* cpu_2000_3fff; // PPU registers and their mirrors
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/* 0x1688 */ u8* cpu_4000_5fff; // APU registers, I/O registers, and usually unmapped cartridge addresses
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/* 0x168C */ u8* cpu_6000_7fff; // usually battery backed cartridge RAM
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/* 0x1690 */ u8* cpu_8000_9fff; // usually cartridge ROM and mapper registers
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/* 0x1694 */ u8* cpu_a000_bfff; // usually cartridge ROM and mapper registers
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/* 0x1698 */ u8* cpu_c000_dfff; // usually cartridge ROM and mapper registers
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/* 0x169C */ u8* cpu_e000_ffff; // usually cartridge ROM and mapper registers
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/* 0x16A0 */ u8 ppu_internal_state[8];
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/* 0x16A8 */ u8 ppu_register_cache[8];
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/* 0x16B0 */ union {
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u8 raw[4];
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struct {
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u8 disk_status; // 0x00
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u8 data; // 0x01
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u8 drive_status; // 0x02
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u8 expansion_connector; // 0x03 top-most bit is battery status
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} registers;
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} qd_drive;
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/* 0x16B4 */ u32 vblank_frame_counter;
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/* 0x16B8 */ u16 wdm_return_addr; // return address calculated by opcode 42, WDM
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/* 0x16BA */ u16 _16BA;
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/* 0x16BC */ u8 _16BC;
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/* 0x16BD */ u8 qd_irq_acknowledged_flag;
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/* 0x16BE */ u8 _16BE;
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/* 0x16BF */ u8 _16BF;
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/* 0x16C0 */ union {
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u32 full;
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struct {
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u16 upper;
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u16 lower;
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} split;
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} qd_disk_head_position;
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/* 0x16C4 */ u8 _16C4; // 0x4020 ?
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/* 0x16C5 */ u8 _16C5; // 0x4021 ?
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/* 0x16C6 */ u8 fds_timer_control_register; // 0x4022
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/* 0x16C7 */ u8 fds_master_io_enable_register; // 0x4023
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/* 0x16C8 */ u8 _16C8; // 0x4024 ?
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/* 0x16C9 */ u8 fds_control_register; // 0x4025
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/* 0x16CA */ u8 _16CA;
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/* 0x16CB */ u8 _16CB;
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/* 0x16CC */ u8 ppu_palette_ram[4 * 0x20];
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/* 0x174C */ u8 ppu_render_latches[24]; // PPU latches for tile/attribute data
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/* 0x1764 */ u8 mapper;
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/* 0x1765 */ u8 prg_banks; // init to number of 8k PRG banks - 1. might indicate currently selected bank
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/* 0x1766 */ u16 chr_banks; // init to number of 1k CHR banks - 1. might indicate currently selected bank
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/* 0x1768 */ u8 bbram_mode_select;
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/* 0x1769 */ u8 chr_ram_write_enable; // 0 = can't write to chr ram, 1 = can write
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/* 0x176A */ u8 fds_disk_count;
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/* 0x176B */ u8 fds_disk_drive_status; // duplicate of qd_drive.registers.drive_status?
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/* 0x176C */ u8 fds_ready_delay_counter;
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/* 0x176D */ u8 motor_timer;
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// /* 0x176E */ u8 mmc5_registers[0x40]; // MMC5 registers -- also used to store QD info during fast save
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/* 0x176E */ u8 _176E[26];
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/* 0x1788 */ u8 fds_fast_io_lock;
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// MMC1 mapper specific (mapper 01)
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// 0x00 = control
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// 0x01 = chr_bank0, 0x02 = chr_bank1
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// 0x03 = selected_reg_idx
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// 0x04 = 512k_prg_mode_flag
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// 0x05 = load_counter
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// 0x06 = shift_register
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/* 0x1789 */ u8 mmc1_regs[7];
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/* 0x1790 */ u8 mmc3_bank_select_regs[8];
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/* 0x1798 */ u8 _1798;
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/* 0x1799 */ u8 _1799;
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/* 0x179A */ u8 _179A;
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/* 0x179B */ u8 _179B;
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/* 0x179C */ u8 _179C;
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/* 0x179D */ u8 _179D;
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/* 0x179E */ u8 _179E;
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/* 0x179F */ u8 _179F;
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/* 0x17A0 */ u8 _17A0;
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/* 0x17A1 */ u8 _17A1;
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/* 0x17A2 */ u8 _17A2;
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/* 0x17A3 */ u8 _17A3;
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/* 0x17A4 */ u8 _17A4;
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/* 0x17A5 */ u8 _17A5;
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/* 0x17A6 */ u8 _17A6;
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/* 0x17A7 */ u8 _17A7;
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/* 0x17A8 */ u8 _17A8;
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/* 0x17A9 */ u8 _17A9;
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/* 0x17AA */ u8 _17AA;
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/* 0x17AB */ u8 _17AB;
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/* 0x17AC */ u8 _17AC;
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/* 0x17AD */ u8 _17AD;
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/* 0x17AE */ u16 mmc5_scanline_irq_target_val;
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/* 0x17B0 */ u8 mmc5_prg_ram_protect[2];
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/* 0x17B2 */ u8 mmc5_ext_ram_mode;
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/* 0x17B3 */ u8 mmc5_nametable_mapping;
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/* 0x17B4 */ u8 mmc5_apu_pcm_mode_irq; // 0x5010
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/* 0x17B5 */ u8 mmc5_apu_status; // 0x5015 analagous to 0x4015 (regular NES APU status), but only bottom two bits are used for MMC5 pulse channels
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/* 0x17B6 */ u8 mmc5_scanline_irq_status;
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/* 0x17B7 */ u8 mmc5_mul_regs[2]; // 0 = operand 0, 1 = operand 1, 0 = result lo, 1 = result hi
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/* 0x17B9 */ u8 mmc5a_cl3_sl3_data_dir_output_src; // 5207 (read/write)
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/* 0x17BA */ u8 mmc5a_cl3_sl3_status; // 5208 (write only)
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/* 0x17BB */ u8 mmc5a_hardware_timer_irq_upper; // 5209 (read/write)
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/* 0x17BC */// u8 mmc5a_hardware_timer_irq_lower; // 520A (write only)
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/* 0x17BC */ u8 mmc5_mul_operands[2]; // 0 = operand 0, 1 = operand 1
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/* 0x17BE */ u8 _17BE;
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/* 0x17BF */ u8 mmc5_scanline_irq_compare_value;
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/* 0x17C0 */ u8 _17C0;
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/* 0x17C1 */ u8 _17C1;
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/* 0x17C2 */ u8 _17C2;
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/* 0x17C3 */ u8 _17C3;
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/* 0x17C4 */ u8 _17C4;
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/* 0x17C5 */ u8 _17C5;
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/* 0x17C6 */ u8 _17C6;
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/* 0x17C7 */ u8 _17C7;
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/* 0x17C8 */ u8 _17C8;
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/* 0x17C9 */ u8 _17C9;
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/* 0x17CA */ u8 _17CA;
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/* 0x17CB */ u8 _17CB;
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/* 0x17CC */ u8 _17CC;
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/* 0x17CD */ u8 _17CD;
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/* 0x17CE */ u8 _17CE;
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/* 0x17CF */ u8 _17CF;
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/* 0x17D0 */ u8 _17D0;
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/* 0x17D1 */ u8 _17D1;
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/* 0x17D2 */ u8 _17D2;
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/* 0x17D3 */ u8 _17D3;
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/* 0x17D4 */ u8 _17D4;
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/* 0x17D5 */ u8 _17D5;
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/* 0x17D6 */ u8 _17D6;
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/* 0x17D7 */ u8 _17D7;
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/* 0x17D8 */ u8 _17D8;
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/* 0x17D9 */ u8 _17D9;
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/* 0x17DA */ u8 _17DA;
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/* 0x17DB */ u8 _17DB;
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/* 0x17DC */ u8 _17DC;
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/* 0x17DD */ u8 _17DD;
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/* 0x17DE */ u8 _17DE;
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/* 0x17DF */ u8 _17DF;
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/* 0x17E0 */ u8 _17E0;
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/* 0x17E1 */ u8 _17E1;
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/* 0x17E2 */ u8 _17E2;
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/* 0x17E3 */ u8 _17E3;
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/* 0x17E4 */ u8 _17E4;
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/* 0x17E5 */ u8 _17E5;
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/* 0x17E6 */ u8 _17E6;
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/* 0x17E7 */ u8 _17E7;
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/* 0x17E8 */ u8 _17E8;
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/* 0x17E9 */ u8 _17E9;
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/* 0x17EA */ u8 _17EA;
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/* 0x17EB */ u8 _17EB;
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/* 0x17EC */ u8 _17EC;
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/* 0x17ED */ u8 _17ED;
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/* 0x17EE */ u8 _17EE;
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/* 0x17EF */ u8 _17EF;
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/* 0x17F0 */ u8* prgromp; // pointer to the start of PRG ROM?
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/* 0x17F4 */ u8* chrramp; // pointer to the end of PRG ROM?
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/* 0x17F8 */ u8* bbramp; // pointer to battery backed RAM?
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/* 0x17FC */ u8 ppu_chr_banks[8];
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/* 0x1804 */ u8 mapper_chr_bank_ext[12];
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/* 0x1810 */ u8* ppu_nametable_pointers[4];
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/* 0x1820 */ s16 ppu_scanline_counter;
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/* 0x1822 */ s16 cpu_cycles_per_visible_scanline;
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/* 0x1824 */ s16 cpu_cycles_per_vblank_scanline;
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/* 0x1826 */ s16 cpu_cycles_for_nmi;
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/* 0x1828 */ u16 scanline_irq_target_val; // scanline target to initiate iterrupt request
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/* 0x182A */ u16 mapper19_irq_scanline_latch; // latch value used for IRQ timings for Namco 163 mapper
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/* 0x182C */ u8 sprite0_hit_scanline; // scanline which
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/* 0x182D */ u8 mmc3_command_register; // Used exclusive in ksNesStore04_8000 for routing logic
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/* 0x182E */ u8 ppu_scanline_threshold; // used for Tetris 2 + Bombliss & Quinty to correct scrolling behavior
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/* 0x182F */ u8 ppu_fine_x_scroll;
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/* 0x1830 */ u8 ppu_vram_addr_v_hi; // vram address for the current bg tile (v)
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/* 0x1831 */ u8 ppu_vram_addr_v_lo; // fine Y scroll corrected
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/* 0x1832 */ u16 ppu_addr_latch;
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/* 0x1834 */ u8 ppu_vram_addr_t_hi; // vram address for work (t)
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/* 0x1835 */ u8 ppu_vram_addr_t_lo; // fine Y scroll raw
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/* 0x1836 */ u16 _1836; // assumed to be an unused ppu latch value for t?
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/* 0x1838 */ u16 cycle_count;
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/* 0x183A */ u16 _183A; // unused
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/* 0x183C */ u16 mapper_irq_latch;
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/* 0x183E */ u16 _183E; // unused
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/* 0x1840 */ void* mapper_irq_handler;
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/* 0x1844 */ u16 PC;
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|
/* 0x1846 */ struct {
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|
u8 A; // 0x00
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|
u8 X; // 0x01
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|
u8 Y; // 0x02
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|
u8 S; // 0x03
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|
|
u8 flag_z; // 0x04
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|
u8 flag_c; // 0x05
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|
u8 flag_v; // 0x06
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|
u8 flag_n; // 0x07
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|
u8 P; // 0x08
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|
|
u8 _unused_09; // 0x09
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|
|
|
u8 apu_dma_dmc_flags; // 0x0A
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|
u8 dac_value; // 0x0B
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|
|
|
u8 irq_status_flags; // 0x0C
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|
u8 irq_mask_flags; // 0x0D
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|
|
|
u8 controller_strobe; // 0x0E
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|
|
|
u8 apu_frame_counter_mode; // 0x0F
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|
|
|
u8 irq_pending_flag; // 0x10
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|
|
|
u8 mapper_irq_enable; // 0x11
|
|
} cpu_state;
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|
/* 0x1858 */ u32 reset_flags; // this should probably be defined as an enum.
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|
/* 0x185C */ u32 frame_flags; // this should probably be defined as an enum.
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|
/* 0x1860 */ size_t prg_size; // PRG size in bytes
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|
/* 0x1864 */ size_t chr_size; // CHR size in bytes
|
|
/* 0x1868 */ u8* nesromp;
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|
/* 0x186C */ u8* ppu_chr_bank_pointers[24];
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|
/* 0x18CC */ u32 io_shift_registers[7];
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|
/* 0x18E8 */ u8 palette_normal[0x80]; // ksNesPaletteNormal
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|
/* 0x1968 */ u8 _1968[0x108]; // unused? (might be in the draw TU)
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/* 0x1A70 */ u32 frame_counter;
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/* 0x1A74 */ OSTick os_tick;
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|
} ksNesStateObj;
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#ifdef __cplusplus
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|
}
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#endif
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#endif
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