dol2asm OK

This commit is contained in:
Julgodis
2021-03-28 22:49:05 +02:00
parent 3d66902e1a
commit 1e95d29b60
60106 changed files with 4755966 additions and 1107376 deletions
@@ -0,0 +1,18 @@
lbl_802DC638:
/* 802DC638 3C A0 80 3C */ lis r5, __vt__10JSUIosBase@ha
/* 802DC63C 38 05 2D F8 */ addi r0, r5, __vt__10JSUIosBase@l
/* 802DC640 90 03 00 00 */ stw r0, 0(r3)
/* 802DC644 38 C0 00 00 */ li r6, 0
/* 802DC648 98 C3 00 04 */ stb r6, 4(r3)
/* 802DC64C 3C A0 80 3D */ lis r5, __vt__14JSUInputStream@ha
/* 802DC650 38 05 C4 D4 */ addi r0, r5, __vt__14JSUInputStream@l
/* 802DC654 90 03 00 00 */ stw r0, 0(r3)
/* 802DC658 3C A0 80 3D */ lis r5, __vt__20JSURandomInputStream@ha
/* 802DC65C 38 05 C4 B0 */ addi r0, r5, __vt__20JSURandomInputStream@l
/* 802DC660 90 03 00 00 */ stw r0, 0(r3)
/* 802DC664 3C A0 80 3D */ lis r5, __vt__18JSUFileInputStream@ha
/* 802DC668 38 05 C5 18 */ addi r0, r5, __vt__18JSUFileInputStream@l
/* 802DC66C 90 03 00 00 */ stw r0, 0(r3)
/* 802DC670 90 83 00 08 */ stw r4, 8(r3)
/* 802DC674 90 C3 00 0C */ stw r6, 0xc(r3)
/* 802DC678 4E 80 00 20 */ blr
@@ -0,0 +1,13 @@
lbl_802DC82C:
/* 802DC82C 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 802DC830 7C 08 02 A6 */ mflr r0
/* 802DC834 90 01 00 14 */ stw r0, 0x14(r1)
/* 802DC838 80 63 00 08 */ lwz r3, 8(r3)
/* 802DC83C 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC840 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 802DC844 7D 89 03 A6 */ mtctr r12
/* 802DC848 4E 80 04 21 */ bctrl
/* 802DC84C 80 01 00 14 */ lwz r0, 0x14(r1)
/* 802DC850 7C 08 03 A6 */ mtlr r0
/* 802DC854 38 21 00 10 */ addi r1, r1, 0x10
/* 802DC858 4E 80 00 20 */ blr
@@ -0,0 +1,3 @@
lbl_802DC85C:
/* 802DC85C 80 63 00 0C */ lwz r3, 0xc(r3)
/* 802DC860 4E 80 00 20 */ blr
@@ -0,0 +1,57 @@
lbl_802DC67C:
/* 802DC67C 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 802DC680 7C 08 02 A6 */ mflr r0
/* 802DC684 90 01 00 24 */ stw r0, 0x24(r1)
/* 802DC688 39 61 00 20 */ addi r11, r1, 0x20
/* 802DC68C 48 08 5B 4D */ bl _savegpr_28
/* 802DC690 7C 7C 1B 78 */ mr r28, r3
/* 802DC694 7C 9D 23 78 */ mr r29, r4
/* 802DC698 7C BE 2B 78 */ mr r30, r5
/* 802DC69C 3B E0 00 00 */ li r31, 0
/* 802DC6A0 80 63 00 08 */ lwz r3, 8(r3)
/* 802DC6A4 88 03 00 18 */ lbz r0, 0x18(r3)
/* 802DC6A8 28 00 00 00 */ cmplwi r0, 0
/* 802DC6AC 41 82 00 84 */ beq lbl_802DC730
/* 802DC6B0 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC6B4 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 802DC6B8 7D 89 03 A6 */ mtctr r12
/* 802DC6BC 4E 80 04 21 */ bctrl
/* 802DC6C0 80 1C 00 0C */ lwz r0, 0xc(r28)
/* 802DC6C4 7C 00 F2 14 */ add r0, r0, r30
/* 802DC6C8 7C 00 18 40 */ cmplw r0, r3
/* 802DC6CC 40 81 00 20 */ ble lbl_802DC6EC
/* 802DC6D0 80 7C 00 08 */ lwz r3, 8(r28)
/* 802DC6D4 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC6D8 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 802DC6DC 7D 89 03 A6 */ mtctr r12
/* 802DC6E0 4E 80 04 21 */ bctrl
/* 802DC6E4 80 1C 00 0C */ lwz r0, 0xc(r28)
/* 802DC6E8 7F C0 18 50 */ subf r30, r0, r3
lbl_802DC6EC:
/* 802DC6EC 2C 1E 00 00 */ cmpwi r30, 0
/* 802DC6F0 40 81 00 40 */ ble lbl_802DC730
/* 802DC6F4 80 7C 00 08 */ lwz r3, 8(r28)
/* 802DC6F8 7F A4 EB 78 */ mr r4, r29
/* 802DC6FC 7F C5 F3 78 */ mr r5, r30
/* 802DC700 80 DC 00 0C */ lwz r6, 0xc(r28)
/* 802DC704 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC708 81 8C 00 14 */ lwz r12, 0x14(r12)
/* 802DC70C 7D 89 03 A6 */ mtctr r12
/* 802DC710 4E 80 04 21 */ bctrl
/* 802DC714 7C 7F 1B 79 */ or. r31, r3, r3
/* 802DC718 40 80 00 0C */ bge lbl_802DC724
/* 802DC71C 38 60 00 00 */ li r3, 0
/* 802DC720 48 00 00 14 */ b lbl_802DC734
lbl_802DC724:
/* 802DC724 80 1C 00 0C */ lwz r0, 0xc(r28)
/* 802DC728 7C 00 FA 14 */ add r0, r0, r31
/* 802DC72C 90 1C 00 0C */ stw r0, 0xc(r28)
lbl_802DC730:
/* 802DC730 7F E3 FB 78 */ mr r3, r31
lbl_802DC734:
/* 802DC734 39 61 00 20 */ addi r11, r1, 0x20
/* 802DC738 48 08 5A ED */ bl _restgpr_28
/* 802DC73C 80 01 00 24 */ lwz r0, 0x24(r1)
/* 802DC740 7C 08 03 A6 */ mtlr r0
/* 802DC744 38 21 00 20 */ addi r1, r1, 0x20
/* 802DC748 4E 80 00 20 */ blr
@@ -0,0 +1,64 @@
lbl_802DC74C:
/* 802DC74C 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 802DC750 7C 08 02 A6 */ mflr r0
/* 802DC754 90 01 00 24 */ stw r0, 0x24(r1)
/* 802DC758 39 61 00 20 */ addi r11, r1, 0x20
/* 802DC75C 48 08 5A 81 */ bl _savegpr_29
/* 802DC760 7C 7D 1B 78 */ mr r29, r3
/* 802DC764 7C 9E 23 78 */ mr r30, r4
/* 802DC768 83 E3 00 0C */ lwz r31, 0xc(r3)
/* 802DC76C 2C 05 00 01 */ cmpwi r5, 1
/* 802DC770 41 82 00 48 */ beq lbl_802DC7B8
/* 802DC774 40 80 00 10 */ bge lbl_802DC784
/* 802DC778 2C 05 00 00 */ cmpwi r5, 0
/* 802DC77C 40 80 00 14 */ bge lbl_802DC790
/* 802DC780 48 00 00 40 */ b lbl_802DC7C0
lbl_802DC784:
/* 802DC784 2C 05 00 03 */ cmpwi r5, 3
/* 802DC788 40 80 00 38 */ bge lbl_802DC7C0
/* 802DC78C 48 00 00 0C */ b lbl_802DC798
lbl_802DC790:
/* 802DC790 93 DD 00 0C */ stw r30, 0xc(r29)
/* 802DC794 48 00 00 2C */ b lbl_802DC7C0
lbl_802DC798:
/* 802DC798 80 7D 00 08 */ lwz r3, 8(r29)
/* 802DC79C 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC7A0 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 802DC7A4 7D 89 03 A6 */ mtctr r12
/* 802DC7A8 4E 80 04 21 */ bctrl
/* 802DC7AC 7C 1E 18 50 */ subf r0, r30, r3
/* 802DC7B0 90 1D 00 0C */ stw r0, 0xc(r29)
/* 802DC7B4 48 00 00 0C */ b lbl_802DC7C0
lbl_802DC7B8:
/* 802DC7B8 7C 1F F2 14 */ add r0, r31, r30
/* 802DC7BC 90 1D 00 0C */ stw r0, 0xc(r29)
lbl_802DC7C0:
/* 802DC7C0 80 1D 00 0C */ lwz r0, 0xc(r29)
/* 802DC7C4 2C 00 00 00 */ cmpwi r0, 0
/* 802DC7C8 40 80 00 0C */ bge lbl_802DC7D4
/* 802DC7CC 38 00 00 00 */ li r0, 0
/* 802DC7D0 90 1D 00 0C */ stw r0, 0xc(r29)
lbl_802DC7D4:
/* 802DC7D4 80 7D 00 08 */ lwz r3, 8(r29)
/* 802DC7D8 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC7DC 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 802DC7E0 7D 89 03 A6 */ mtctr r12
/* 802DC7E4 4E 80 04 21 */ bctrl
/* 802DC7E8 80 1D 00 0C */ lwz r0, 0xc(r29)
/* 802DC7EC 7C 00 18 00 */ cmpw r0, r3
/* 802DC7F0 40 81 00 1C */ ble lbl_802DC80C
/* 802DC7F4 80 7D 00 08 */ lwz r3, 8(r29)
/* 802DC7F8 81 83 00 00 */ lwz r12, 0(r3)
/* 802DC7FC 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 802DC800 7D 89 03 A6 */ mtctr r12
/* 802DC804 4E 80 04 21 */ bctrl
/* 802DC808 90 7D 00 0C */ stw r3, 0xc(r29)
lbl_802DC80C:
/* 802DC80C 80 1D 00 0C */ lwz r0, 0xc(r29)
/* 802DC810 7C 7F 00 50 */ subf r3, r31, r0
/* 802DC814 39 61 00 20 */ addi r11, r1, 0x20
/* 802DC818 48 08 5A 11 */ bl _restgpr_29
/* 802DC81C 80 01 00 24 */ lwz r0, 0x24(r1)
/* 802DC820 7C 08 03 A6 */ mtlr r0
/* 802DC824 38 21 00 20 */ addi r1, r1, 0x20
/* 802DC828 4E 80 00 20 */ blr