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debugDisplay and Debug_console attemp

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This commit is contained in:
Pheenoh
2021-02-07 17:20:16 -05:00
parent 315ef319fc
commit 34693ded85
70 changed files with 547 additions and 225 deletions
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include/JSystem/JKernel/JKRAram/JKRAram.h
+3
View File
@@ -40,6 +40,7 @@ public:
static void changeGroupIdIfNeed(u8*, int);
static void mainRamToAram(u8*, u32, u32, JKRExpandSwitch, u32, JKRHeap*, int, u32*);
static void aramToMainRam(u32, u8*, u32, JKRExpandSwitch, u32, JKRHeap*, int, u32*);
static void dump(void);
static JKRAram* getManager() { return sAramObject; }
static JKRAramHeap* getAramHeap() { return getManager()->mAramHeap; }
@@ -67,6 +68,8 @@ private:
static JSUList<JKRAMCommand> sAramCommandList;
};
extern JKRAram* sAramObject__7JKRAram; // JKRAram::sAramObject
void JKRDecompressFromAramToMainRam(u32, void*, u32, u32, u32, u32*);
#endif
include/JSystem/JKernel/JKRThread/asm/func_802D1C74.s
+3 -3
View File
@@ -14,7 +14,7 @@
/* 802D1CA8 002CEBE8 3B A3 00 7F */ addi r29, r3, 0x7f
/* 802D1CAC 002CEBEC 41 82 00 34 */ beq lbl_802D1CE0
/* 802D1CB0 002CEBF0 7F 83 E3 78 */ mr r3, r28
/* 802D1CB4 002CEBF4 48 01 59 39 */ bl JUTConsole_NS_clear
/* 802D1CB4 002CEBF4 48 01 59 39 */ bl clear__10JUTConsoleFv
/* 802D1CB8 002CEBF8 7F 83 E3 78 */ mr r3, r28
/* 802D1CBC 002CEBFC 7F 24 CB 78 */ mr r4, r25
/* 802D1CC0 002CEC00 80 AD 8E 34 */ lwz r5, lbl_804513B4-_SDA_BASE_(r13)
@@ -78,11 +78,11 @@ lbl_802D1D60:
/* 802D1D8C 002CECCC EF E0 08 24 */ fdivs f31, f0, f1
/* 802D1D90 002CECD0 C0 02 C5 C0 */ lfs f0, lbl_80455FC0-_SDA2_BASE_(r2)
/* 802D1D94 002CECD4 EC 20 07 F2 */ fmuls f1, f0, f31
/* 802D1D98 002CECD8 48 09 03 15 */ bl func_803620AC
/* 802D1D98 002CECD8 48 09 03 15 */ bl __cvt_fp2unsigned
/* 802D1D9C 002CECDC 7C 79 1B 78 */ mr r25, r3
/* 802D1DA0 002CECE0 C0 02 C5 C4 */ lfs f0, lbl_80455FC4-_SDA2_BASE_(r2)
/* 802D1DA4 002CECE4 EC 20 07 F2 */ fmuls f1, f0, f31
/* 802D1DA8 002CECE8 48 09 03 05 */ bl func_803620AC
/* 802D1DA8 002CECE8 48 09 03 05 */ bl __cvt_fp2unsigned
/* 802D1DAC 002CECEC 38 80 00 0A */ li r4, 0xa
/* 802D1DB0 002CECF0 7C 03 23 96 */ divwu r0, r3, r4
/* 802D1DB4 002CECF4 7C 00 21 D6 */ mullw r0, r0, r4