mirror of
https://github.com/TwilitRealm/dusklight
synced 2026-09-04 09:11:42 -04:00
Work on dvd, si, os and exi (#249)
This commit is contained in:
hatal175
+85
-113
@@ -5,6 +5,9 @@
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#include "dolphin/os/OSCache.h"
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#include "dol2asm.h"
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#include "dolphin/base/PPCArch.h"
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#include "dolphin/db/db.h"
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#include "dolphin/os/OS.h"
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#include "dolphin/os/OSError.h"
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#include "dolphin/os/OSInterrupt.h"
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@@ -12,18 +15,6 @@
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// External References:
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//
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void OSReport();
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void PPCMfmsr();
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void PPCMtmsr();
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void PPCMfhid0();
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void PPCMfl2cr();
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void PPCMtl2cr();
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void PPCHalt();
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void PPCMfhid2();
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void PPCMthid2();
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void OSDumpContext();
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void DBPrintf();
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//
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// Declarations:
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//
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@@ -334,7 +325,7 @@ do_invalidate:
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/* 8033B814-8033B838 336154 0024+00 1/1 0/0 0/0 .text LCStoreBlocks */
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static asm void LCStoreBlocks(register void* destAddr, register void* srcAddr,
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register u32 blockNum) {
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register u32 blockNum){
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// clang-format off
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nofralloc
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@@ -349,8 +340,7 @@ static asm void LCStoreBlocks(register void* destAddr, register void* srcAddr,
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blr
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// clang-format on
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}
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/* 8033B838-8033B8E4 336178 00AC+00 0/0 0/0 3/3 .text LCStoreData */
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} /* 8033B838-8033B8E4 336178 00AC+00 0/0 0/0 3/3 .text LCStoreData */
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u32 LCStoreData(void* destAddr, void* srcAddr, u32 nBytes) {
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u32 blocks = (nBytes + 31) / 32;
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u32 ret = (blocks + 127) / 128;
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@@ -372,7 +362,7 @@ u32 LCStoreData(void* destAddr, void* srcAddr, u32 nBytes) {
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}
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/* 8033B8E4-8033B8F8 336224 0014+00 0/0 0/0 3/3 .text LCQueueWait */
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asm void LCQueueWait(register u32 len){
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asm void LCQueueWait(register u32 len) {
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// clang-format off
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nofralloc
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@@ -386,116 +376,98 @@ asm void LCQueueWait(register u32 len){
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}
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/* ############################################################################################## */
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/* 803CF510-803CF53C 02C630 0029+03 3/3 0/0 0/0 .data @63 */
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SECTION_DATA static char lit_63[] = ">>> L2 INVALIDATE : SHOULD NEVER HAPPEN\n";
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static void L2Disable(void) {
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__sync();
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PPCMtl2cr(PPCMfl2cr() & ~0x80000000);
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__sync();
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}
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/* 8033B8F8-8033B990 336238 0098+00 1/1 0/0 0/0 .text L2GlobalInvalidate */
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#pragma push
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#pragma optimization_level 0
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#pragma optimizewithasm off
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static asm void L2GlobalInvalidate(void) {
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nofralloc
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#include "asm/dolphin/os/OSCache/L2GlobalInvalidate.s"
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void L2GlobalInvalidate(void) {
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L2Disable();
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PPCMtl2cr(PPCMfl2cr() | 0x00200000);
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while (PPCMfl2cr() & 0x00000001u)
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;
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PPCMtl2cr(PPCMfl2cr() & ~0x00200000);
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while (PPCMfl2cr() & 0x00000001u) {
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DBPrintf(">>> L2 INVALIDATE : SHOULD NEVER HAPPEN\n");
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}
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}
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#pragma pop
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/* ############################################################################################## */
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/* 803CF53C-803CF554 02C65C 0018+00 0/1 0/0 0/0 .data @84 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_84[] = "Machine check received\n";
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#pragma pop
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/* 803CF554-803CF570 02C674 001B+01 0/1 0/0 0/0 .data @85 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_85[] = "HID2 = 0x%x SRR1 = 0x%x\n";
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#pragma pop
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/* 803CF570-803CF5A0 02C690 0030+00 0/1 0/0 0/0 .data @86 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_86[] = "Machine check was not DMA/locked cache related\n";
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#pragma pop
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/* 803CF5A0-803CF5DC 02C6C0 003C+00 0/1 0/0 0/0 .data @87 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_87[] = "DMAErrorHandler(): An error occurred while processing DMA.\n";
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#pragma pop
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/* 803CF5DC-803CF614 02C6FC 0037+01 0/1 0/0 0/0 .data @88 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_88[] = "The following errors have been detected and cleared :\n";
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#pragma pop
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/* 803CF614-803CF654 02C734 003F+01 0/1 0/0 0/0 .data @89 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_89[] =
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"\t- Requested a locked cache tag that was already in the cache\n";
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#pragma pop
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/* 803CF654-803CF680 02C774 0029+03 0/1 0/0 0/0 .data @90 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_90[] = "\t- DMA attempted to access normal cache\n";
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#pragma pop
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/* 803CF680-803CF6A0 02C7A0 001D+03 0/1 0/0 0/0 .data @91 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_91[] = "\t- DMA missed in data cache\n";
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#pragma pop
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/* 803CF6A0-803CF6BC 02C7C0 0019+03 0/1 0/0 0/0 .data @92 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_92[] = "\t- DMA queue overflowed\n";
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#pragma pop
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/* 8033B990-8033BAF0 3362D0 0160+00 1/1 0/0 0/0 .text DMAErrorHandler */
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#pragma push
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#pragma optimization_level 0
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#pragma optimizewithasm off
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static asm void DMAErrorHandler(s32 error, OSContext* context) {
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nofralloc
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#include "asm/dolphin/os/OSCache/DMAErrorHandler.s"
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void DMAErrorHandler(u16 error, OSContext* context, ...) {
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u32 hid2 = PPCMfhid2();
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OSReport("Machine check received\n");
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OSReport("HID2 = 0x%x SRR1 = 0x%x\n", hid2, context->srr1);
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if (!(hid2 & (HID2_DCHERR | HID2_DNCERR | HID2_DCMERR | HID2_DQOERR)) ||
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!(context->srr1 & SRR1_DMA_BIT)) {
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OSReport("Machine check was not DMA/locked cache related\n");
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OSDumpContext(context);
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PPCHalt();
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}
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OSReport("DMAErrorHandler(): An error occurred while processing DMA.\n");
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OSReport("The following errors have been detected and cleared :\n");
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if (hid2 & HID2_DCHERR) {
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OSReport("\t- Requested a locked cache tag that was already in the cache\n");
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}
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if (hid2 & HID2_DNCERR) {
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OSReport("\t- DMA attempted to access normal cache\n");
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}
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if (hid2 & HID2_DCMERR) {
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OSReport("\t- DMA missed in data cache\n");
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}
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if (hid2 & HID2_DQOERR) {
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OSReport("\t- DMA queue overflowed\n");
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}
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// write hid2 back to clear the error bits
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PPCMthid2(hid2);
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}
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#pragma pop
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/* ############################################################################################## */
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/* 803CF6BC-803CF6D8 02C7DC 0019+03 0/1 0/0 0/0 .data @104 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_104[] = "L1 i-caches initialized\n";
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#pragma pop
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/* 803CF6D8-803CF6F4 02C7F8 0019+03 0/1 0/0 0/0 .data @105 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_105[] = "L1 d-caches initialized\n";
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#pragma pop
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static void L2Init(void) {
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u32 oldMSR;
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oldMSR = PPCMfmsr();
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__sync();
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PPCMtmsr(MSR_IR | MSR_DR);
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__sync();
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L2Disable();
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L2GlobalInvalidate();
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PPCMtmsr(oldMSR);
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}
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/* 803CF6F4-803CF70C 02C814 0016+02 0/1 0/0 0/0 .data @106 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_106[] = "L2 cache initialized\n";
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#pragma pop
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/* 803CF70C-803CF740 02C82C 002E+06 0/1 0/0 0/0 .data @107 */
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#pragma push
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#pragma force_active on
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SECTION_DATA static char lit_107[] = "Locked cache machine check handler installed\n";
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#pragma pop
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void L2Enable(void) {
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PPCMtl2cr((PPCMfl2cr() | L2CR_L2E) & ~L2CR_L2I);
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}
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/* 8033BAF0-8033BBE4 336430 00F4+00 0/0 2/2 0/0 .text __OSCacheInit */
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#pragma push
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#pragma optimization_level 0
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#pragma optimizewithasm off
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asm void __OSCacheInit(void) {
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nofralloc
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#include "asm/dolphin/os/OSCache/__OSCacheInit.s"
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void __OSCacheInit() {
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if (!(PPCMfhid0() & HID0_ICE)) {
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ICEnable();
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DBPrintf("L1 i-caches initialized\n");
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}
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if (!(PPCMfhid0() & HID0_DCE)) {
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DCEnable();
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DBPrintf("L1 d-caches initialized\n");
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}
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if (!(PPCMfl2cr() & L2CR_L2E)) {
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L2Init();
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L2Enable();
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DBPrintf("L2 cache initialized\n");
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}
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OSSetErrorHandler(OS_ERROR_MACHINE_CHECK, DMAErrorHandler);
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DBPrintf("Locked cache machine check handler installed\n");
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}
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#pragma pop
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