mirror of
https://github.com/TwilitRealm/dusklight
synced 2026-08-10 02:35:17 -04:00
Jonathan Wase
ff2faa9804
* JKRDvdArchive.s split * JKRMemArchive.s split * JKRAramArchive.s split * JKRCompArchive.s split * JKRDecomp.s split * JKRDvdRipper.s split * JKRAramBlock.s split * JKRAramHeap.s split * JKRAramPiece.s split * JKRAramStream.s split * removed unused .s files * JKRDvdAramRipper.s split * JKRAram.s split * cleanup and making vtables easier to debug * fixed merge errors * fixed JKRFileLoader::fetchVolumeName Co-authored-by: Pheenoh <pheenoh@gmail.com>
32 lines
1.5 KiB
ArmAsm
32 lines
1.5 KiB
ArmAsm
/* getTotalFreeSize__11JKRAramHeapFv __ct__11JKRAramHeapFUlUl::getTotalFreeSize(void) */
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/* JKRAramHeap_NS_getTotalFreeSize */
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/* 802D31AC 002D00EC 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 802D31B0 002D00F0 7C 08 02 A6 */ mflr r0
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/* 802D31B4 002D00F4 90 01 00 14 */ stw r0, 0x14(r1)
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/* 802D31B8 002D00F8 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 802D31BC 002D00FC 93 C1 00 08 */ stw r30, 8(r1)
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/* 802D31C0 002D0100 7C 7E 1B 78 */ mr r30, r3
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/* 802D31C4 002D0104 3B E0 00 00 */ li r31, 0
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/* 802D31C8 002D0108 38 7E 00 18 */ addi r3, r30, 0x18
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/* 802D31CC 002D010C 48 06 BE 75 */ bl OSLockMutex
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/* 802D31D0 002D0110 3C 60 80 43 */ lis r3, lbl_8043430C@ha
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/* 802D31D4 002D0114 80 83 43 0C */ lwz r4, lbl_8043430C@l(r3)
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/* 802D31D8 002D0118 48 00 00 14 */ b lbl_802D31EC
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lbl_802D31DC:
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/* 802D31DC 002D011C 80 64 00 00 */ lwz r3, 0(r4)
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/* 802D31E0 002D0120 80 03 00 1C */ lwz r0, 0x1c(r3)
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/* 802D31E4 002D0124 7F FF 02 14 */ add r31, r31, r0
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/* 802D31E8 002D0128 80 84 00 0C */ lwz r4, 0xc(r4)
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lbl_802D31EC:
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/* 802D31EC 002D012C 28 04 00 00 */ cmplwi r4, 0
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/* 802D31F0 002D0130 40 82 FF EC */ bne lbl_802D31DC
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/* 802D31F4 002D0134 38 7E 00 18 */ addi r3, r30, 0x18
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/* 802D31F8 002D0138 48 06 BF 25 */ bl OSUnlockMutex
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/* 802D31FC 002D013C 7F E3 FB 78 */ mr r3, r31
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/* 802D3200 002D0140 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 802D3204 002D0144 83 C1 00 08 */ lwz r30, 8(r1)
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/* 802D3208 002D0148 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 802D320C 002D014C 7C 08 03 A6 */ mtlr r0
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/* 802D3210 002D0150 38 21 00 10 */ addi r1, r1, 0x10
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/* 802D3214 002D0154 4E 80 00 20 */ blr
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