mirror of
https://github.com/TwilitRealm/dusklight
synced 2026-06-07 11:27:26 -04:00
4df8ccc871
* Reorganize files into libs/{dolphin,JSystem,PowerPC_EABI_Support,revolution,TRK_MINNOW_DOLPHIN}
* Update configure.py and project.py for new libs structure
* Refactor `#include <dolphin/x.h>` -> `<x.h>`
* Remove `__REVOLUTION_SDK__` forwards from dolphin
* Fix dolphin/ references in revolution
* Wrap `#include <dolphin.h>` in `!__REVOLUTION_SDK__`
* Always build TRK against dolphin headers
* Resolve revolution SDK header resolution issues
293 lines
3.8 KiB
C
293 lines
3.8 KiB
C
#include <dolphin/dolphin.h>
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#include <dolphin/base/PPCArch.h>
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asm u32 PPCMfmsr() {
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nofralloc
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mfmsr r3
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blr
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}
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asm void PPCMtmsr(__REGISTER u32 newMSR) {
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nofralloc
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mtmsr newMSR
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blr
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}
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asm u32 PPCOrMsr(__REGISTER u32 value) {
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nofralloc
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mfmsr r4
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or value, r4, value
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blr
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}
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asm u32 PPCAndMsr(__REGISTER u32 value) {
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nofralloc
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mfmsr r4
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and value, r4, value
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blr
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}
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asm u32 PPCAndCMsr(__REGISTER u32 value) {
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nofralloc
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mfmsr r4
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andc value, r4, value
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blr
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}
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asm u32 PPCMfhid0() {
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nofralloc
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mfspr r3, HID0
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blr
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}
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asm void PPCMthid0(__REGISTER u32 newHID0) {
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nofralloc
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mtspr HID0, newHID0
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blr
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}
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asm u32 PPCMfhid1() {
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nofralloc
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mfspr r3, HID1
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blr
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}
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asm u32 PPCMfl2cr() {
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nofralloc
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mfspr r3, L2CR
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blr
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}
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asm void PPCMtl2cr(__REGISTER u32 newL2cr) {
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nofralloc
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mtspr L2CR, newL2cr
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blr
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}
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asm void PPCMtdec(__REGISTER u32 newDec) {
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nofralloc
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mtdec newDec
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blr
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}
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asm u32 PPCMfdec() {
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nofralloc
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mfdec r3
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blr
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}
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asm void PPCSync() {
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nofralloc
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sc
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blr
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}
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asm void PPCEieio() {
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nofralloc
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mfmsr r5
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rlwinm r6, r5, 0, 17, 15
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mtmsr r6
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mfspr r3, HID0
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ori r4, r3, 0x8
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mtspr HID0, r4
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isync
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eieio
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isync
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mtspr HID0, r3
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mtmsr r5
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isync
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blr
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}
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asm void PPCHalt() {
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nofralloc
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sync
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loop:
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nop
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li r3, 0
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nop
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b loop
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}
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asm u32 PPCMfmmcr0() {
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nofralloc
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mfspr r3, MMCR0
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blr
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}
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asm void PPCMtmmcr0(__REGISTER u32 newMmcr0) {
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nofralloc
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mtspr MMCR0, newMmcr0
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blr
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}
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asm u32 PPCMfmmcr1() {
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nofralloc
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mfspr r3, MMCR1
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blr
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}
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asm void PPCMtmmcr1(__REGISTER u32 newMmcr1) {
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nofralloc
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mtspr MMCR1, newMmcr1
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blr
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}
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asm u32 PPCMfpmc1() {
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nofralloc
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mfspr r3, PMC1
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blr
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}
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asm void PPCMtpmc1(__REGISTER u32 newPmc1) {
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nofralloc
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mtspr PMC1, newPmc1
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blr
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}
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asm u32 PPCMfpmc2() {
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nofralloc
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mfspr r3, PMC2
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blr
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}
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asm void PPCMtpmc2(__REGISTER u32 newPmc2) {
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nofralloc
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mtspr PMC2, newPmc2
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blr
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}
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asm u32 PPCMfpmc3() {
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nofralloc
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mfspr r3, PMC3
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blr
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}
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asm void PPCMtpmc3(__REGISTER u32 newPmc3) {
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nofralloc
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mtspr PMC3, newPmc3
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blr
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}
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asm u32 PPCMfpmc4() {
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nofralloc
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mfspr r3, PMC4
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blr
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}
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asm void PPCMtpmc4(__REGISTER u32 newPmc4) {
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nofralloc
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mtspr PMC4, newPmc4
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blr
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}
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asm u32 PPCMfsia() {
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nofralloc
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mfspr r3, SIA
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blr
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}
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asm void PPCMtsia(__REGISTER u32 newSia) {
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nofralloc
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mtspr SIA, newSia
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blr
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}
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u32 PPCMffpscr() {
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union FpscrUnion m;
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asm {
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mffs fp31
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stfd fp31, m.f;
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}
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return m.u.fpscr;
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}
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void PPCMtfpscr(__REGISTER u32 newFPSCR) {
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union FpscrUnion m;
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asm {
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li r4, 0
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stw r4, m.u.fpscr_pad;
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stw newFPSCR, m.u.fpscr
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lfd fp31, m.f
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mtfsf 0xff, fp31
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}
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}
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asm u32 PPCMfhid2() {
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nofralloc
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mfspr r3, HID2
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blr
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}
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asm void PPCMthid2(__REGISTER u32 newhid2) {
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nofralloc
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mtspr HID2, newhid2
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blr
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}
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asm u32 PPCMfwpar() {
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nofralloc
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sync
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mfspr r3, WPAR
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blr
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}
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asm void PPCMtwpar(__REGISTER u32 newwpar) {
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nofralloc
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mtspr WPAR, newwpar
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blr
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}
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asm u32 PPCMfdmaU() {
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nofralloc
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mfspr r3, DMA_U
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blr
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}
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asm u32 PPCMfdmaL() {
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nofralloc
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mfspr r3, DMA_L
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blr
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}
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asm void PPCMtdmaU(__REGISTER u32 newdmau) {
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nofralloc
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mtspr DMA_U, newdmau
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blr
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}
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asm void PPCMtdmaL(__REGISTER u32 newdmal) {
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nofralloc
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mtspr DMA_L, newdmal
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blr
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}
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asm u32 PPCMfpvr() {
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nofralloc
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mfspr r3, PVR
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blr
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}
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void PPCEnableSpeculation(void) {
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PPCMthid0(PPCMfhid0() & ~HID0_SPD);
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}
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void PPCDisableSpeculation(void) {
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PPCMthid0(PPCMfhid0() | HID0_SPD);
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}
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asm void PPCSetFpIEEEMode() {
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nofralloc
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mtfsb0 29
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blr
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}
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asm void PPCSetFpNonIEEEMode() {
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nofralloc
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mtfsb1 29
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blr
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}
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