mirror of
https://github.com/TwilitRealm/dusklight
synced 2026-08-20 05:16:24 -04:00
Jonathan Wase
82d5e0f796
* before __register_global_object * JKRThread::sThreadList, JKRHeap::sSystemHeap, etc. * cleanup and started on JKRDvdArchive * before changing JKRCompression * more JKRDvdArchive, abs, and memset * fixed JKRArchive::setExpandSize split * JKRArchive::sCurrentDirID, JKRDvdFile::sDvdList, and matching JKRDvdFile constructors * problems * merge fixes and formatting * updated clang version in clang-format-all to version 10 * Added OSPhysicalToCached and struct for global memory * remove useless __attribute__ * changed from defines and macros to const variable and function * changed FLAG_HAS to FLAG_ON * JKRAram, linking problems * fix JKRAram * remove nonmatching stuff * renamed static data * more static class members * JKRAramStream OK * formatting Co-authored-by: Julgodis <> Co-authored-by: Pheenoh <pheenoh@gmail.com>
46 lines
2.5 KiB
ArmAsm
46 lines
2.5 KiB
ArmAsm
/* firstSrcData__Fv firstSrcData(void) */
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/* firstSrcData */
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/* 802D2C40 002CFB80 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 802D2C44 002CFB84 7C 08 02 A6 */ mflr r0
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/* 802D2C48 002CFB88 90 01 00 14 */ stw r0, 0x14(r1)
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/* 802D2C4C 002CFB8C 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 802D2C50 002CFB90 93 C1 00 08 */ stw r30, 8(r1)
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/* 802D2C54 002CFB94 80 6D 8E 50 */ lwz r3, JKRAram__szpEnd-_SDA_BASE_(r13)
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/* 802D2C58 002CFB98 38 03 FF E7 */ addi r0, r3, -25
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/* 802D2C5C 002CFB9C 90 0D 8E 68 */ stw r0, JKRAram__srcLimit-_SDA_BASE_(r13)
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/* 802D2C60 002CFBA0 80 0D 8E 4C */ lwz r0, JKRAram__szpBuf-_SDA_BASE_(r13)
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/* 802D2C64 002CFBA4 7C 1E 03 78 */ mr r30, r0
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/* 802D2C68 002CFBA8 7C 60 18 50 */ subf r3, r0, r3
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/* 802D2C6C 002CFBAC 80 0D 8E 64 */ lwz r0, JKRAram__transLeft-_SDA_BASE_(r13)
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/* 802D2C70 002CFBB0 7C 00 18 40 */ cmplw r0, r3
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/* 802D2C74 002CFBB4 7C 7F 1B 78 */ mr r31, r3
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/* 802D2C78 002CFBB8 40 80 00 08 */ bge lbl_802D2C80
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/* 802D2C7C 002CFBBC 7C 1F 03 78 */ mr r31, r0
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lbl_802D2C80:
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/* 802D2C80 002CFBC0 38 60 00 01 */ li r3, 1
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/* 802D2C84 002CFBC4 80 8D 8E 6C */ lwz r4, JKRAram__srcAddress-_SDA_BASE_(r13)
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/* 802D2C88 002CFBC8 80 0D 8E 60 */ lwz r0, JKRAram__srcOffset-_SDA_BASE_(r13)
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/* 802D2C8C 002CFBCC 7C 84 02 14 */ add r4, r4, r0
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/* 802D2C90 002CFBD0 7F C5 F3 78 */ mr r5, r30
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/* 802D2C94 002CFBD4 38 1F 00 1F */ addi r0, r31, 0x1f
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/* 802D2C98 002CFBD8 54 06 00 34 */ rlwinm r6, r0, 0, 0, 0x1a
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/* 802D2C9C 002CFBDC 38 E0 00 00 */ li r7, 0
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/* 802D2CA0 002CFBE0 48 00 0B 99 */ bl orderSync__12JKRAramPieceFiUlUlUlP12JKRAramBlock
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/* 802D2CA4 002CFBE4 80 0D 8E 60 */ lwz r0, JKRAram__srcOffset-_SDA_BASE_(r13)
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/* 802D2CA8 002CFBE8 7C 00 FA 14 */ add r0, r0, r31
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/* 802D2CAC 002CFBEC 90 0D 8E 60 */ stw r0, JKRAram__srcOffset-_SDA_BASE_(r13)
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/* 802D2CB0 002CFBF0 80 0D 8E 64 */ lwz r0, JKRAram__transLeft-_SDA_BASE_(r13)
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/* 802D2CB4 002CFBF4 7C 1F 00 51 */ subf. r0, r31, r0
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/* 802D2CB8 002CFBF8 90 0D 8E 64 */ stw r0, JKRAram__transLeft-_SDA_BASE_(r13)
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/* 802D2CBC 002CFBFC 40 82 00 0C */ bne lbl_802D2CC8
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/* 802D2CC0 002CFC00 7C 1E FA 14 */ add r0, r30, r31
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/* 802D2CC4 002CFC04 90 0D 8E 68 */ stw r0, JKRAram__srcLimit-_SDA_BASE_(r13)
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lbl_802D2CC8:
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/* 802D2CC8 002CFC08 7F C3 F3 78 */ mr r3, r30
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/* 802D2CCC 002CFC0C 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 802D2CD0 002CFC10 83 C1 00 08 */ lwz r30, 8(r1)
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/* 802D2CD4 002CFC14 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 802D2CD8 002CFC18 7C 08 03 A6 */ mtlr r0
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/* 802D2CDC 002CFC1C 38 21 00 10 */ addi r1, r1, 0x10
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/* 802D2CE0 002CFC20 4E 80 00 20 */ blr
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