mirror of
https://github.com/TwilitRealm/dusklight
synced 2026-06-28 09:13:10 -04:00
lepelog
0eec99db4d
* split c_math * split c_angle * split c_API_controller_pad * split c_API_graphic * split c_bg_s_chk * c_bg_s_gnd_chk split * more c_bg split * split c_cc_d * delete asm * split c_cc_s * split c_lib * split c_m2d and c_m3d_g_aab * split c_m3d_g_cir * split c_m3d_g_cps * split rest of c_m3d_g * split c_m3d * split c_malloc * split c_request * split c_sxyz * split and partly decompile c_xyz * format * c_angle.h * begin c_angle decomp * c_angle * progress adding stub classes for SComponent * more c_m3d * remove some asm and format * more m3d headers * more c_angle decomp * c_lib headers * add public to classes * fix csXyz member names * c_sxyz partly OK * move Zero csXyz to c_sxyz header * c_API_graphic * delete some unused asm * move math extern data, decompile some functions * delete unused asm * fix duplicated c_angle.h * fix an inlined function name, add more inlined functions for c_angle.h (currently unused) * format Co-authored-by: Pheenoh <pheenoh@gmail.com>
22 lines
1.0 KiB
ArmAsm
22 lines
1.0 KiB
ArmAsm
/* 8026417C 002610BC 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80264180 002610C0 7C 08 02 A6 */ mflr r0
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/* 80264184 002610C4 90 01 00 14 */ stw r0, 0x14(r1)
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/* 80264188 002610C8 7C 66 1B 78 */ mr r6, r3
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/* 8026418C 002610CC 28 04 00 00 */ cmplwi r4, 0
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/* 80264190 002610D0 41 82 00 08 */ beq lbl_80264198
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/* 80264194 002610D4 38 84 00 20 */ addi r4, r4, 0x20
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lbl_80264198:
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/* 80264198 002610D8 7C 83 23 78 */ mr r3, r4
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/* 8026419C 002610DC 38 86 00 20 */ addi r4, r6, 0x20
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/* 802641A0 002610E0 48 00 92 35 */ bl cM3d_Cross_CpsCyl__FRC8cM3dGCpsRC8cM3dGCylP3Vec
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/* 802641A4 002610E4 54 60 06 3F */ clrlwi. r0, r3, 0x18
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/* 802641A8 002610E8 41 82 00 0C */ beq lbl_802641B4
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/* 802641AC 002610EC 38 60 00 01 */ li r3, 1
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/* 802641B0 002610F0 48 00 00 08 */ b lbl_802641B8
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lbl_802641B4:
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/* 802641B4 002610F4 38 60 00 00 */ li r3, 0
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lbl_802641B8:
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/* 802641B8 002610F8 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 802641BC 002610FC 7C 08 03 A6 */ mtlr r0
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/* 802641C0 00261100 38 21 00 10 */ addi r1, r1, 0x10
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/* 802641C4 00261104 4E 80 00 20 */ blr |