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include/PR/R4300.h
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/**************************************************************************
* *
* Copyright (C) 1995, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* $Revision: 1.13 $
* $Date: 1997/02/11 08:15:34 $
* $Source: /disk6/Master/cvsmdev2/PR/include/R4300.h,v $
*
**************************************************************************/
#ifndef __R4300_H__
#define __R4300_H__
#include <PR/ultratypes.h>
/*
* Segment base addresses and sizes
*/
#define KUBASE 0
#define KUSIZE 0x80000000
#define K0BASE 0x80000000
#define K0SIZE 0x20000000
#define K1BASE 0xA0000000
#define K1SIZE 0x20000000
#define K2BASE 0xC0000000
#define K2SIZE 0x20000000
/*
* Exception vectors
*/
#define SIZE_EXCVEC 0x80 /* Size of an exc. vec */
#define UT_VEC K0BASE /* utlbmiss vector */
#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
#define XUT_VEC (K0BASE+0x80) /* extended address tlbmiss */
#define ECC_VEC (K0BASE+0x100) /* Ecc exception vector */
#define E_VEC (K0BASE+0x180) /* Gen. exception vector */
/*
* Address conversion macros
*/
#ifdef _LANGUAGE_ASSEMBLY
#define K0_TO_K1(x) ((x)|0xA0000000) /* kseg0 to kseg1 */
#define K1_TO_K0(x) ((x)&0x9FFFFFFF) /* kseg1 to kseg0 */
#define K0_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg0 to physical */
#define K1_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg1 to physical */
#define KDM_TO_PHYS(x) ((x)&0x1FFFFFFF) /* direct mapped to physical */
#define PHYS_TO_K0(x) ((x)|0x80000000) /* physical to kseg0 */
#define PHYS_TO_K1(x) ((x)|0xA0000000) /* physical to kseg1 */
#else /* _LANGUAGE_C */
#define K0_TO_K1(x) ((u32)(x)|0xA0000000) /* kseg0 to kseg1 */
#define K1_TO_K0(x) ((u32)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */
#define KDM_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* direct mapped to physical */
#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */
#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
#endif /* _LANGUAGE_ASSEMBLY */
/*
* Address predicates
*/
#define IS_KSEG0(x) ((u32)(x) >= K0BASE && (u32)(x) < K1BASE)
#define IS_KSEG1(x) ((u32)(x) >= K1BASE && (u32)(x) < K2BASE)
#define IS_KSEGDM(x) ((u32)(x) >= K0BASE && (u32)(x) < K2BASE)
#define IS_KSEG2(x) ((u32)(x) >= K2BASE && (u32)(x) < KPTE_SHDUBASE)
#define IS_KPTESEG(x) ((u32)(x) >= KPTE_SHDUBASE)
#define IS_KUSEG(x) ((u32)(x) < K0BASE)
/*
* TLB size constants
*/
#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
#define TLBHI_VPN2MASK 0xffffe000
#define TLBHI_VPN2SHIFT 13
#define TLBHI_PIDMASK 0xff
#define TLBHI_PIDSHIFT 0
#define TLBHI_NPID 255 /* 255 to fit in 8 bits */
#define TLBLO_PFNMASK 0x3fffffc0
#define TLBLO_PFNSHIFT 6
#define TLBLO_CACHMASK 0x38 /* cache coherency algorithm */
#define TLBLO_CACHSHIFT 3
#define TLBLO_UNCACHED 0x10 /* not cached */
#define TLBLO_NONCOHRNT 0x18 /* Cacheable non-coherent */
#define TLBLO_EXLWR 0x28 /* Exclusive write */
#define TLBLO_D 0x4 /* writeable */
#define TLBLO_V 0x2 /* valid bit */
#define TLBLO_G 0x1 /* global access bit */
#define TLBINX_PROBE 0x80000000
#define TLBINX_INXMASK 0x3f
#define TLBINX_INXSHIFT 0
#define TLBRAND_RANDMASK 0x3f
#define TLBRAND_RANDSHIFT 0
#define TLBWIRED_WIREDMASK 0x3f
#define TLBCTXT_BASEMASK 0xff800000
#define TLBCTXT_BASESHIFT 23
#define TLBCTXT_BASEBITS 9
#define TLBCTXT_VPNMASK 0x7ffff0
#define TLBCTXT_VPNSHIFT 4
#define TLBPGMASK_4K 0x0
#define TLBPGMASK_16K 0x6000
#define TLBPGMASK_64K 0x1e000
/*
* Status register
*/
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
#define SR_RP 0x08000000 /* Reduced power (quarter speed) */
#define SR_FR 0x04000000 /* MIPS III FP register mode */
#define SR_RE 0x02000000 /* Reverse endian */
#define SR_ITS 0x01000000 /* Instruction trace support */
#define SR_BEV 0x00400000 /* Use boot exception vectors */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_SR 0x00100000 /* Soft reset occured */
#define SR_CH 0x00040000 /* Cache hit for last 'cache' op */
#define SR_CE 0x00020000 /* Create ECC */
#define SR_DE 0x00010000 /* ECC of parity does not cause error */
/*
* Interrupt enable bits
* (NOTE: bits set to 1 enable the corresponding level interrupt)
*/
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
#define SR_IMASK8 0x00000000 /* mask level 8 */
#define SR_IMASK7 0x00008000 /* mask level 7 */
#define SR_IMASK6 0x0000c000 /* mask level 6 */
#define SR_IMASK5 0x0000e000 /* mask level 5 */
#define SR_IMASK4 0x0000f000 /* mask level 4 */
#define SR_IMASK3 0x0000f800 /* mask level 3 */
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
#define SR_IBIT8 0x00008000 /* bit level 8 */
#define SR_IBIT7 0x00004000 /* bit level 7 */
#define SR_IBIT6 0x00002000 /* bit level 6 */
#define SR_IBIT5 0x00001000 /* bit level 5 */
#define SR_IBIT4 0x00000800 /* bit level 4 */
#define SR_IBIT3 0x00000400 /* bit level 3 */
#define SR_IBIT2 0x00000200 /* bit level 2 */
#define SR_IBIT1 0x00000100 /* bit level 1 */
#define SR_IMASKSHIFT 8
#define SR_KX 0x00000080 /* extended-addr TLB vec in kernel */
#define SR_SX 0x00000040 /* xtended-addr TLB vec supervisor */
#define SR_UX 0x00000020 /* xtended-addr TLB vec in user mode */
#define SR_KSU_MASK 0x00000018 /* mode mask */
#define SR_KSU_USR 0x00000010 /* user mode */
#define SR_KSU_SUP 0x00000008 /* supervisor mode */
#define SR_KSU_KER 0x00000000 /* kernel mode */
#define SR_ERL 0x00000004 /* Error level, 1=>cache error */
#define SR_EXL 0x00000002 /* Exception level, 1=>exception */
#define SR_IE 0x00000001 /* interrupt enable, 1=>enable */
/*
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
/* Interrupt pending bits */
#define CAUSE_IP8 0x00008000 /* External level 8 pending - COMPARE */
#define CAUSE_IP7 0x00004000 /* External level 7 pending - INT4 */
#define CAUSE_IP6 0x00002000 /* External level 6 pending - INT3 */
#define CAUSE_IP5 0x00001000 /* External level 5 pending - INT2 */
#define CAUSE_IP4 0x00000800 /* External level 4 pending - INT1 */
#define CAUSE_IP3 0x00000400 /* External level 3 pending - INT0 */
#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
#define CAUSE_IPSHIFT 8
#define CAUSE_EXCMASK 0x0000007C /* Cause code bits */
#define CAUSE_EXCSHIFT 2
/* Cause register exception codes */
#define EXC_CODE(x) ((x)<<2)
/* Hardware exception codes */
#define EXC_INT EXC_CODE(0) /* interrupt */
#define EXC_MOD EXC_CODE(1) /* TLB mod */
#define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */
#define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */
#define EXC_RADE EXC_CODE(4) /* Read Address Error */
#define EXC_WADE EXC_CODE(5) /* Write Address Error */
#define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */
#define EXC_DBE EXC_CODE(7) /* Data Bus Error */
#define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */
#define EXC_BREAK EXC_CODE(9) /* BREAKpoint */
#define EXC_II EXC_CODE(10) /* Illegal Instruction */
#define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */
#define EXC_OV EXC_CODE(12) /* OVerflow */
#define EXC_TRAP EXC_CODE(13) /* Trap exception */
#define EXC_VCEI EXC_CODE(14) /* Virt. Coherency on Inst. fetch */
#define EXC_FPE EXC_CODE(15) /* Floating Point Exception */
#define EXC_WATCH EXC_CODE(23) /* Watchpoint reference */
#define EXC_VCED EXC_CODE(31) /* Virt. Coherency on data read */
/* C0_PRID Defines */
#define C0_IMPMASK 0xff00
#define C0_IMPSHIFT 8
#define C0_REVMASK 0xff
#define C0_MAJREVMASK 0xf0
#define C0_MAJREVSHIFT 4
#define C0_MINREVMASK 0xf
/*
* Coprocessor 0 operations
*/
#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
#define C0_RFE 0x10 /* restore for exception */
/*
* 'cache' instruction definitions
*/
/* Target cache */
#define CACH_PI 0x0 /* specifies primary inst. cache */
#define CACH_PD 0x1 /* primary data cache */
#define CACH_SI 0x2 /* secondary instruction cache */
#define CACH_SD 0x3 /* secondary data cache */
/* Cache operations */
#define C_IINV 0x0 /* index invalidate (inst, 2nd inst) */
#define C_IWBINV 0x0 /* index writeback inval (d, sd) */
#define C_ILT 0x4 /* index load tag (all) */
#define C_IST 0x8 /* index store tag (all) */
#define C_CDX 0xc /* create dirty exclusive (d, sd) */
#define C_HINV 0x10 /* hit invalidate (all) */
#define C_HWBINV 0x14 /* hit writeback inv. (d, sd) */
#define C_FILL 0x14 /* fill (i) */
#define C_HWB 0x18 /* hit writeback (i, d, sd) */
#define C_HSV 0x1c /* hit set virt. (si, sd) */
/*
* Cache size definitions
*/
#define ICACHE_SIZE 0x4000 /* 16K */
#define ICACHE_LINESIZE 32 /* 8 words */
#define ICACHE_LINEMASK (ICACHE_LINESIZE-1)
#define DCACHE_SIZE 0x2000 /* 8K */
#define DCACHE_LINESIZE 16 /* 4 words */
#define DCACHE_LINEMASK (DCACHE_LINESIZE-1)
/*
* C0_CONFIG register definitions
*/
#define CONFIG_CM 0x80000000 /* 1 == Master-Checker enabled */
#define CONFIG_EC 0x70000000 /* System Clock ratio */
#define CONFIG_EC_1_1 0x6 /* System Clock ratio 1 :1 */
#define CONFIG_EC_3_2 0x7 /* System Clock ratio 1.5 :1 */
#define CONFIG_EC_2_1 0x0 /* System Clock ratio 2 :1 */
#define CONFIG_EC_3_1 0x1 /* System Clock ratio 3 :1 */
#define CONFIG_EP 0x0f000000 /* Transmit Data Pattern */
#define CONFIG_SB 0x00c00000 /* Secondary cache block size */
#define CONFIG_SS 0x00200000 /* Split scache: 0 == I&D combined */
#define CONFIG_SW 0x00100000 /* scache port: 0==128, 1==64 */
#define CONFIG_EW 0x000c0000 /* System Port width: 0==64, 1==32 */
#define CONFIG_SC 0x00020000 /* 0 -> 2nd cache present */
#define CONFIG_SM 0x00010000 /* 0 -> Dirty Shared Coherency enabled*/
#define CONFIG_BE 0x00008000 /* Endian-ness: 1 --> BE */
#define CONFIG_EM 0x00004000 /* 1 -> ECC mode, 0 -> parity */
#define CONFIG_EB 0x00002000 /* Block order:1->sequent,0->subblock */
#define CONFIG_IC 0x00000e00 /* Primary Icache size */
#define CONFIG_DC 0x000001c0 /* Primary Dcache size */
#define CONFIG_IB 0x00000020 /* Icache block size */
#define CONFIG_DB 0x00000010 /* Dcache block size */
#define CONFIG_CU 0x00000008 /* Update on Store-conditional */
#define CONFIG_K0 0x00000007 /* K0SEG Coherency algorithm */
#define CONFIG_UNCACHED 0x00000002 /* K0 is uncached */
#define CONFIG_NONCOHRNT 0x00000003
#define CONFIG_COHRNT_EXLWR 0x00000005
#define CONFIG_SB_SHFT 22 /* shift SB to bit position 0 */
#define CONFIG_IC_SHFT 9 /* shift IC to bit position 0 */
#define CONFIG_DC_SHFT 6 /* shift DC to bit position 0 */
#define CONFIG_BE_SHFT 15 /* shift BE to bit position 0 */
/*
* C0_TAGLO definitions for setting/getting cache states and physaddr bits
*/
#define SADDRMASK 0xFFFFE000 /* 31..13 -> scache paddr bits 35..17 */
#define SVINDEXMASK 0x00000380 /* 9..7: prim virt index bits 14..12 */
#define SSTATEMASK 0x00001c00 /* bits 12..10 hold scache line state */
#define SINVALID 0x00000000 /* invalid --> 000 == state 0 */
#define SCLEANEXCL 0x00001000 /* clean exclusive --> 100 == state 4 */
#define SDIRTYEXCL 0x00001400 /* dirty exclusive --> 101 == state 5 */
#define SECC_MASK 0x0000007f /* low 7 bits are ecc for the tag */
#define SADDR_SHIFT 4 /* shift STagLo (31..13) to 35..17 */
#define PADDRMASK 0xFFFFFF00 /* PTagLo31..8->prim paddr bits35..12 */
#define PADDR_SHIFT 4 /* roll bits 35..12 down to 31..8 */
#define PSTATEMASK 0x00C0 /* bits 7..6 hold primary line state */
#define PINVALID 0x0000 /* invalid --> 000 == state 0 */
#define PCLEANEXCL 0x0080 /* clean exclusive --> 10 == state 2 */
#define PDIRTYEXCL 0x00C0 /* dirty exclusive --> 11 == state 3 */
#define PPARITY_MASK 0x0001 /* low bit is parity bit (even). */
/*
* C0_CACHE_ERR definitions.
*/
#define CACHERR_ER 0x80000000 /* 0: inst ref, 1: data ref */
#define CACHERR_EC 0x40000000 /* 0: primary, 1: secondary */
#define CACHERR_ED 0x20000000 /* 1: data error */
#define CACHERR_ET 0x10000000 /* 1: tag error */
#define CACHERR_ES 0x08000000 /* 1: external ref, e.g. snoop*/
#define CACHERR_EE 0x04000000 /* error on SysAD bus */
#define CACHERR_EB 0x02000000 /* complicated, see spec. */
#define CACHERR_EI 0x01000000 /* complicated, see spec. */
#define CACHERR_SIDX_MASK 0x003ffff8 /* secondary cache index */
#define CACHERR_PIDX_MASK 0x00000007 /* primary cache index */
#define CACHERR_PIDX_SHIFT 12 /* bits 2..0 are paddr14..12 */
/* R4000 family supports hardware watchpoints:
* C0_WATCHLO:
* bits 31..3 are bits 31..3 of physaddr to watch
* bit 2: reserved; must be written as 0.
* bit 1: when set causes a watchpoint trap on load accesses to paddr.
* bit 0: when set traps on stores to paddr;
* C0_WATCHHI
* bits 31..4 are reserved and must be written as zeros.
* bits 3..0 are bits 35..32 of the physaddr to watch
*/
#define WATCHLO_WTRAP 0x00000001
#define WATCHLO_RTRAP 0x00000002
#define WATCHLO_ADDRMASK 0xfffffff8
#define WATCHLO_VALIDMASK 0xfffffffb
#define WATCHHI_VALIDMASK 0x0000000f
/*
* Coprocessor 0 registers
*/
#ifdef _LANGUAGE_ASSEMBLY
#define C0_INX $0
#define C0_RAND $1
#define C0_ENTRYLO0 $2
#define C0_ENTRYLO1 $3
#define C0_CONTEXT $4
#define C0_PAGEMASK $5 /* page mask */
#define C0_WIRED $6 /* # wired entries in tlb */
#define C0_BADVADDR $8
#define C0_COUNT $9 /* free-running counter */
#define C0_ENTRYHI $10
#define C0_SR $12
#define C0_CAUSE $13
#define C0_EPC $14
#define C0_PRID $15 /* revision identifier */
#define C0_COMPARE $11 /* counter comparison reg. */
#define C0_CONFIG $16 /* hardware configuration */
#define C0_LLADDR $17 /* load linked address */
#define C0_WATCHLO $18 /* watchpoint */
#define C0_WATCHHI $19 /* watchpoint */
#define C0_ECC $26 /* S-cache ECC and primary parity */
#define C0_CACHE_ERR $27 /* cache error status */
#define C0_TAGLO $28 /* cache operations */
#define C0_TAGHI $29 /* cache operations */
#define C0_ERROR_EPC $30 /* ECC error prg. counter */
# else /* ! _LANGUAGE_ASSEMBLY */
#define C0_INX 0
#define C0_RAND 1
#define C0_ENTRYLO0 2
#define C0_ENTRYLO1 3
#define C0_CONTEXT 4
#define C0_PAGEMASK 5 /* page mask */
#define C0_WIRED 6 /* # wired entries in tlb */
#define C0_BADVADDR 8
#define C0_COUNT 9 /* free-running counter */
#define C0_ENTRYHI 10
#define C0_SR 12
#define C0_CAUSE 13
#define C0_EPC 14
#define C0_PRID 15 /* revision identifier */
#define C0_COMPARE 11 /* counter comparison reg. */
#define C0_CONFIG 16 /* hardware configuration */
#define C0_LLADDR 17 /* load linked address */
#define C0_WATCHLO 18 /* watchpoint */
#define C0_WATCHHI 19 /* watchpoint */
#define C0_ECC 26 /* S-cache ECC and primary parity */
#define C0_CACHE_ERR 27 /* cache error status */
#define C0_TAGLO 28 /* cache operations */
#define C0_TAGHI 29 /* cache operations */
#define C0_ERROR_EPC 30 /* ECC error prg. counter */
#endif /* _LANGUAGE_ASSEMBLY */
/*
* floating-point status register
*/
#define FPCSR_FS 0x01000000 /* flush denorm to zero */
#define FPCSR_C 0x00800000 /* condition bit */
#define FPCSR_CE 0x00020000 /* cause: unimplemented operation */
#define FPCSR_CV 0x00010000 /* cause: invalid operation */
#define FPCSR_CZ 0x00008000 /* cause: division by zero */
#define FPCSR_CO 0x00004000 /* cause: overflow */
#define FPCSR_CU 0x00002000 /* cause: underflow */
#define FPCSR_CI 0x00001000 /* cause: inexact operation */
#define FPCSR_EV 0x00000800 /* enable: invalid operation */
#define FPCSR_EZ 0x00000400 /* enable: division by zero */
#define FPCSR_EO 0x00000200 /* enable: overflow */
#define FPCSR_EU 0x00000100 /* enable: underflow */
#define FPCSR_EI 0x00000080 /* enable: inexact operation */
#define FPCSR_FV 0x00000040 /* flag: invalid operation */
#define FPCSR_FZ 0x00000020 /* flag: division by zero */
#define FPCSR_FO 0x00000010 /* flag: overflow */
#define FPCSR_FU 0x00000008 /* flag: underflow */
#define FPCSR_FI 0x00000004 /* flag: inexact operation */
#define FPCSR_RM_MASK 0x00000003 /* rounding mode mask */
#define FPCSR_RM_RN 0x00000000 /* round to nearest */
#define FPCSR_RM_RZ 0x00000001 /* round to zero */
#define FPCSR_RM_RP 0x00000002 /* round to positive infinity */
#define FPCSR_RM_RM 0x00000003 /* round to negative infinity */
#endif /* __R4300_H */
include/PR/abi.h
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#ifndef _ABI_H_
#define _ABI_H_
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* $Revision: 1.32 $
* $Date: 1997/02/11 08:16:37 $
* $Source: /exdisk2/cvs/N64OS/Master/cvsmdev2/PR/include/abi.h,v $
*
**************************************************************************/
/*
* Header file for the Audio Binary Interface.
* This is included in the Media Binary Interface file
* mbi.h.
*
* This file follows the framework used for graphics.
*
*/
/* Audio commands: */
#define A_SPNOOP 0
#define A_ADPCM 1
#define A_CLEARBUFF 2
#define A_RESAMPLE 5
#define A_SETBUFF 8
#define A_DMEMMOVE 10
#define A_LOADADPCM 11
#define A_MIXER 12
#define A_INTERLEAVE 13
#define A_SETLOOP 15
#ifndef VERSION_SH
#define A_ENVMIXER 3
#define A_LOADBUFF 4
#define A_RESAMPLE 5
#define A_SAVEBUFF 6
#define A_SEGMENT 7
#define A_SETVOL 9
#define A_POLEF 14
#else
#define A_ADDMIXER 4
#define A_RESAMPLE_ZOH 6
#define A_INTERL 17
#define A_ENVSETUP1 18
#define A_ENVMIXER 19
#define A_LOADBUFF 20
#define A_SAVEBUFF 21
#define A_ENVSETUP2 22
#define A_UNK_23 23
#define A_HILOGAIN 24
#define A_UNK_25 25
#define A_DUPLICATE 26
#define A_FILTER 27
#endif
#define ACMD_SIZE 32
/*
* Audio flags
*/
#define A_INIT 0x01
#define A_CONTINUE 0x00
#define A_LOOP 0x02
#define A_OUT 0x02
#define A_LEFT 0x02
#define A_RIGHT 0x00
#define A_VOL 0x04
#define A_RATE 0x00
#define A_AUX 0x08
#define A_NOAUX 0x00
#define A_MAIN 0x00
#define A_MIX 0x10
/*
* BEGIN C-specific section: (typedef's)
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/*
* Data Structures.
*/
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int gain:16;
unsigned int addr;
} Aadpcm;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int gain:16;
unsigned int addr;
} Apolef;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pad1:16;
unsigned int addr;
} Aenvelope;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int dmem:16;
unsigned int pad2:16;
unsigned int count:16;
} Aclearbuff;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int pad2:16;
unsigned int inL:16;
unsigned int inR:16;
} Ainterleave;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:24;
unsigned int addr;
} Aloadbuff;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pad1:16;
unsigned int addr;
} Aenvmixer;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int gain:16;
unsigned int dmemi:16;
unsigned int dmemo:16;
} Amixer;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int dmem2:16;
unsigned int addr;
} Apan;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pitch:16;
unsigned int addr;
} Aresample;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pad1:16;
unsigned int addr;
} Areverb;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:24;
unsigned int addr;
} Asavebuff;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:24;
unsigned int pad2:2;
unsigned int number:4;
unsigned int base:24;
} Asegment;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int dmemin:16;
unsigned int dmemout:16;
unsigned int count:16;
} Asetbuff;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int vol:16;
unsigned int voltgt:16;
unsigned int volrate:16;
} Asetvol;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int dmemin:16;
unsigned int dmemout:16;
unsigned int count:16;
} Admemmove;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int count:16;
unsigned int addr;
} Aloadadpcm;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int pad2:16;
unsigned int addr;
} Asetloop;
/*
* Generic Acmd Packet
*/
typedef struct {
uintptr_t w0;
uintptr_t w1;
} Awords;
typedef union {
Awords words;
#if IS_BIG_ENDIAN && !IS_64_BIT
Aadpcm adpcm;
Apolef polef;
Aclearbuff clearbuff;
Aenvelope envelope;
Ainterleave interleave;
Aloadbuff loadbuff;
Aenvmixer envmixer;
Aresample resample;
Areverb reverb;
Asavebuff savebuff;
Asegment segment;
Asetbuff setbuff;
Asetvol setvol;
Admemmove dmemmove;
Aloadadpcm loadadpcm;
Amixer mixer;
Asetloop setloop;
#endif
long long int force_union_align; /* dummy, force alignment */
} Acmd;
/*
* ADPCM State
*/
typedef short ADPCM_STATE[16];
/*
* Pole filter state
*/
typedef short POLEF_STATE[4];
/*
* Resampler state
*/
typedef short RESAMPLE_STATE[16];
/*
* Resampler constants
*/
#define UNITY_PITCH 0x8000
#define MAX_RATIO 1.99996 /* within .03 cents of +1 octave */
/*
* Enveloper/Mixer state
*/
typedef short ENVMIX_STATE[40];
/*
* Macros to assemble the audio command list
*/
/*
* Info about parameters:
*
* A "count" in the following macros is always measured in bytes.
*
* All volumes/gains are in Q1.15 signed fixed point numbers:
* 0x8000 is the minimum volume (-100%), negating the audio curve.
* 0x0000 is silent.
* 0x7fff is maximum volume (99.997%).
*
* All DRAM addresses refer to segmented addresses. A segment table shall
* first be set up by calling aSegment for each segment. When a DRAM
* address is later used as parameter, the 8 high bits will be an index
* to the segment table and the lower 24 bits are added to the base address
* stored in the segment table for this entry. The result is the physical address.
*
* Transfers to/from DRAM are executed using DMA and hence follow these restrictions:
* All DRAM addresses should be aligned by 8 bytes, or they will be
* rounded down to the nearest multiple of 8 bytes.
* All DRAM lengths should be aligned by 8 bytes, or they will be
* rounded up to the nearest multiple of 8 bytes.
*/
/*
* Decompresses ADPCM data.
* Possible flags: A_INIT and A_LOOP.
*
* First set up internal data in DMEM:
* aLoadADPCM(cmd++, nEntries * 16, physicalAddressOfBook)
* aSetLoop(cmd++, physicalAddressOfLoopState) (if A_LOOP is set)
*
* Then before this command, call:
* aSetBuffer(cmd++, 0, in, out, count)
*
* Note: count will be rounded up to the nearest multiple of 32 bytes.
*
* ADPCM decompression works on a block of 16 (uncompressed) samples.
* The previous 2 samples and 9 bytes of input are decompressed to
* 16 new samples using the code book previously loaded.
*
* Before the algorithm starts, the previous 16 samples are loaded according to flag:
* A_INIT: all zeros
* A_LOOP: the address set by aSetLoop
* no flags: the DRAM address in the s parameter
* These 16 samples are immediately copied to the destination address.
*
* The result of "count" bytes will be written after these 16 initial samples.
* The last 16 samples written to the destination will also be written to
* the state address in DRAM.
*/
#define aADPCMdec(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ADPCM, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (uintptr_t)(s); \
}
#define aADPCM_23(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_UNK_23, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Not used in SM64.
*/
#define aPoleFilter(pkt, f, g, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_POLEF, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Clears DMEM data, where d is address and c is count, by writing zeros.
*
* Note: c is rounded up to the nearest multiple of 16 bytes.
*/
#define aClearBuffer(pkt, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_CLEARBUFF, 24, 8) | _SHIFTL(d, 0, 24); \
_a->words.w1 = (uintptr_t)(c); \
}
/*
* Mixes an envelope with mono sound into 2 or 4 channels.
* Possible flags: A_INIT, A_AUX (indicates that 4 channels should be used).
*
* Before this command, call:
* aSetBuffer(cmd++, 0, inBuf, dryLeft, count)
* aSetBuffer(cmd++, A_AUX, dryRight, wetLeft, wetRight)
*
* The first time (A_INIT is set), volume also needs to be set:
* aSetVolume(cmd++, A_VOL | A_LEFT, initialVolumeLeft, 0, 0)
* aSetVolume(cmd++, A_VOL | A_RIGHT, initialVolumeRight, 0, 0)
* aSetVolume32(cmd++, A_RATE | A_LEFT, targetVolumeLeft, rampLeft)
* aSetVolume32(cmd++, A_RATE | A_RIGHT, targetVolumeRight, rampRight)
* aSetVolume(cmd++, A_AUX, dryVolume, 0, wetVolume)
*
* This command will now mix samples in inBuf into the destination buffers (dry and wet),
* but with the volume increased (or decreased) from initial volumes to target volumes,
* with the specified ramp rate. Once the target volume is reached, the volume stays
* at that level. Before the samples are finally mixed (added) into the destination
* buffers (dry and wet), the volume is changed according to dryVolume and wetVolume.
*
* Note: count will be rounded up to the nearest multiple of 16 bytes.
* Note: the wet channels are used for reverb.
*
*/
#define aEnvMixer(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ENVMIXER, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Interleaves two mono channels into stereo.
*
* First call:
* aSetBuffer(cmd++, 0, 0, output, count)
*
* The count refers to the size of each input. Hence 2 * count bytes will be written out.
* A left sample will be placed before the right sample.
*
* Note: count will be rounded up to the nearest multiple of 16 bytes.
*/
#define aInterleave(pkt, l, r) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_INTERLEAVE, 24, 8); \
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
}
/*
* Loads a buffer from DRAM to DMEM.
*
* First call:
* aSetBuffer(cmd++, 0, in, 0, count)
*
* The in parameter to aSetBuffer is the destination in DMEM and the
* s parameter to this command is the source in DRAM.
*/
#define aLoadBuffer(pkt, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADBUFF, 24, 8); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Mixes audio.
* Possible flags: no flags used, although parameter present.
*
* First call:
* aSetBuffer(cmd++, 0, 0, 0, count)
*
* Input and output addresses are taken from the i and o parameters.
* The volume with which the input is changed is taken from the g parameter.
* After the volume of the input samples have been changed, the result
* is added to the output.
*
* Note: count will be rounded up to the nearest multiple of 32 bytes.
*/
#define aMix(pkt, f, g, i, o) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = _SHIFTL(i,16, 16) | _SHIFTL(o, 0, 16); \
}
// Not present in the audio microcode.
#define aPan(pkt, f, d, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_PAN, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(d, 0, 16)); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Resamples audio.
* Possible flags: A_INIT, A_OUT? (not used in SM64).
*
* First call:
* aSetBuffer(cmd++, 0, in, out, count)
*
* This command resamples the audio using the given frequency ratio (pitch)
* using a filter that uses a window of 4 source samples. This can be used
* either for just resampling audio to be able to be played back at a different
* sample rate, or to change the pitch if the result is played back at
* the same sample rate as the input.
*
* The frequency ratio is given in UQ1.15 fixed point format.
* For no change in frequency, use pitch 0x8000.
* For 1 octave up or downsampling to (roughly) half number of samples, use pitch 0xffff.
* For 1 octave down or upsampling to double as many samples, use pitch 0x4000.
*
* Note: count represents the number of output sample bytes and is rounded up to
* the nearest multiple of 16 bytes.
*
* The state consists of the four following source samples when the algorithm stopped as
* well as a fractional position, and is initialized to all zeros if A_INIT is given.
* Otherwise it is loaded from DRAM at address s.
*
* The algorithm starts by writing the four source samples from the state (or zero)
* to just before the input address given. It then creates one output sample by examining
* the four next source samples and then moving the source position zero or more
* samples forward. The first output sample (when A_INIT is given) is always 0.
*
* When "count" bytes have been written, the following four source samples
* are written to the state in DRAM as well as a fractional position.
*/
#define aResample(pkt, f, p, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE, 24, 8) | _SHIFTL(f, 16, 8) |\
_SHIFTL(p, 0, 16)); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Stores a buffer in DMEM to DRAM.
*
* First call:
* aSetBuffer(cmd++, 0, 0, out, count)
*
* The out parameter to aSetBuffer is the source in DMEM and the
* s parameter to this command is the destination in DRAM.
*/
#define aSaveBuffer(pkt, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SAVEBUFF, 24, 8); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Sets up an entry in the segment table.
*
* The s parameter is a segment index, 0 to 15.
* The b parameter is the base offset.
*/
#define aSegment(pkt, s, b) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SEGMENT, 24, 8); \
_a->words.w1 = _SHIFTL(s, 24, 8) | _SHIFTL(b, 0, 24); \
}
/*
* Sets internal DMEM buffer addresses used for later commands.
* See each command for how to use aSetBuffer.
*/
#define aSetBuffer(pkt, f, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SETBUFF, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(i, 0, 16)); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
}
#define aInterl(pkt, f, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_INTERL, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(i, 0, 16)); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
}
/*
* Sets internal volume parameters.
* See aEnvMixer for more info.
*/
#define aSetVolume(pkt, f, v, t, r) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SETVOL, 24, 8) | _SHIFTL(f, 16, 16) | \
_SHIFTL(v, 0, 16)); \
_a->words.w1 = _SHIFTL(t, 16, 16) | _SHIFTL(r, 0, 16); \
}
/*
* Sets the address to ADPCM loop state.
*
* The a parameter is a DRAM address.
* See aADPCMdec for more info.
*/
#define aSetLoop(pkt, a) \
{ \
Acmd *_a = (Acmd *)pkt; \
_a->words.w0 = _SHIFTL(A_SETLOOP, 24, 8); \
_a->words.w1 = (uintptr_t)(a); \
}
/*
* Copies memory in DMEM.
*
* Copies c bytes from address i to address o.
*
* Note: count is rounded up to the nearest multiple of 16 bytes.
*
* Note: This acts as memcpy where 16 bytes are moved at a time, therefore
* if input and output overlap, output address should be less than input address.
*/
#define aDMEMMove(pkt, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_DMEMMOVE, 24, 8) | _SHIFTL(i, 0, 24); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
}
/*
* Loads ADPCM book from DRAM into DMEM.
*
* This command loads ADPCM table entries from DRAM to DMEM.
*
* The count parameter c should be a multiple of 16 bytes.
* The d parameter is a DRAM address.
*/
#define aLoadADPCM(pkt, c, d) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADADPCM, 24, 8) | _SHIFTL(c, 0, 24); \
_a->words.w1 = (uintptr_t) (d); \
}
// This is a version of aSetVolume which takes a single 32-bit parameter
// instead of two 16-bit ones. According to AziAudio, it is used to set
// ramping values when neither bit 4 nor bit 8 is set in the flags parameter.
// It does not appear in the official abi.h header.
/*
* Sets internal volume parameters.
* See aEnvMixer for more info.
*/
#define aSetVolume32(pkt, f, v, tr) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SETVOL, 24, 8) | _SHIFTL(f, 16, 16) | \
_SHIFTL(v, 0, 16)); \
_a->words.w1 = (uintptr_t)(tr); \
}
#ifdef VERSION_SH
#undef aLoadBuffer
#undef aSaveBuffer
#undef aMix
#undef aEnvMixer
#undef aInterleave
/*
* Mix two tracks by simple clamped addition.
*
* s: DMEM source track 1
* d: DMEM source track 2 and destination
* c: number of bytes to write (rounded down to 16 byte alignment)
*/
#define aAddMixer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ADDMIXER, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(0x7fff, 0, 16)); \
_a->words.w1 = (_SHIFTL(s, 16, 16) | _SHIFTL(d, 0, 16)); \
}
/*
* Loads a buffer from DRAM to DMEM.
*
* s: DRAM source
* d: DMEM destination
* c: number of bytes to copy (rounded down to 16 byte alignment)
*/
#define aLoadBuffer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADBUFF, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(d, 0, 16); \
_a->words.w1 = (uintptr_t)(s); \
}
/*
* Stores a buffer from DMEM to DRAM.
*
* s: DMEM source
* d: DRAM destination
* c: number of bytes to copy (rounded down to 16 byte alignment)
*/
#define aSaveBuffer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SAVEBUFF, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(s, 0, 16); \
_a->words.w1 = (uintptr_t)(d); \
}
/*
* Duplicates 128 bytes of data a number of times.
*
* 128 bytes are read from source DMEM address s.
* Then c identical copies of these bytes are written to DMEM address d.
*/
#define aDuplicate(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_DUPLICATE, 24, 8) | \
_SHIFTL(c, 16, 8) | _SHIFTL(s, 0, 16)); \
_a->words.w1 = (_SHIFTL(d, 16, 16) | _SHIFTL(0x80, 0, 16)); \
}
/*
* Fast resample.
*
* Before this command, call:
* aSetBuffer(cmd++, 0, in, out, count)
*
* This works like the other resample command but just takes the "nearest" sample,
* instead of a function of the four nearest samples.
*/
#define aResampleZoh(pkt, pitch, start_fract) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE_ZOH, 24, 8) | \
_SHIFTL(pitch, 0, 16)); \
_a->words.w1 = _SHIFTL(start_fract, 0, 16); \
}
/*
* Mixes audio.
*
* Input and output addresses are taken from the i and o parameters.
* The volume with which the input is changed is taken from the g parameter.
* After the volume of the input samples have been changed, the result
* is added to the output.
*
* Note: count is first rounded down to the nearest multiple of 16 bytes
* and then rounded up to the nearest multiple of 32 bytes.
*/
#define aMix(pkt, g, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(g, 0, 16)); \
_a->words.w1 = _SHIFTL(i, 16, 16) | _SHIFTL(o, 0, 16); \
}
#define aEnvSetup1(pkt, a, b, c, d) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ENVSETUP1, 24, 8) | \
_SHIFTL(a, 16, 8) | _SHIFTL(b, 0, 16)); \
_a->words.w1 = _SHIFTL(c, 16, 16) | _SHIFTL(d, 0, 16); \
}
#define aEnvSetup2(pkt, volLeft, volRight) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ENVSETUP2, 24, 8); \
_a->words.w1 = _SHIFTL(volLeft, 16, 16) | \
_SHIFTL(volRight, 0, 16); \
}
#define aEnvMixer(pkt, inBuf, nSamples, bit1, bit2, bit3, dryLeft, dryRight, wetLeft, wetRight) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ENVMIXER, 24, 8) | \
_SHIFTL((inBuf) >> 4, 16, 8) | \
_SHIFTL(nSamples, 8, 8)) | \
_SHIFTL(bit1, 2, 1) | _SHIFTL(bit2, 1, 1) | \
_SHIFTL(bit3, 0, 1); \
_a->words.w1 = _SHIFTL((dryLeft) >> 4, 24, 8) | \
_SHIFTL((dryRight) >> 4, 16, 8) | \
_SHIFTL((wetLeft) >> 4, 8, 8) | \
_SHIFTL((wetRight) >> 4, 0, 8); \
}
#define aInterleave(pkt, o, l, r, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_INTERLEAVE, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(o, 0, 16); \
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
}
// countOrBuf meaning depends on flag
#define aFilter(pkt, f, countOrBuf, addr) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_FILTER, 24, 8) | _SHIFTL((f), 16, 8) | \
_SHIFTL((countOrBuf), 0, 16); \
_a->words.w1 = (uintptr_t)(addr); \
}
#define aHilogain(pkt, id, buflen, i) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_HILOGAIN, 24, 8) | \
_SHIFTL((id), 16, 8) | _SHIFTL((buflen), 0, 16); \
_a->words.w1 = _SHIFTL((i), 16, 16); \
}
#define aUnknown25(pkt, f, g, i, o) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_UNK_25, 24, 8) | \
_SHIFTL((f), 16, 8) | _SHIFTL((g), 0, 16)); \
_a->words.w1 = _SHIFTL((i), 16, 16) | _SHIFTL((o), 0, 16); \
}
#endif
#endif /* _LANGUAGE_C */
#endif /* !_ABI_H_ */
include/PR/gbi.h
+4801
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include/PR/gs2dex.h
+392
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@@ -0,0 +1,392 @@
/*---------------------------------------------------------------------
Copyright (C) 1997, Nintendo.
File gs2dex.h
Coded by Yoshitaka Yasumoto. Jul 31, 1997.
Modified by
Comments Header file for S2DEX ucode.
$Id: gs2dex.h,v 1.21 1998/05/28 00:14:49 has Exp $
---------------------------------------------------------------------*/
#ifndef _GS2DEX_H_
#define _GS2DEX_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
/*===========================================================================*
* Macro
*===========================================================================*/
#define GS_CALC_DXT(line) (((1<< G_TX_DXT_FRAC)-1)/(line)+1)
#define GS_PIX2TMEM(pix, siz) ((pix)>>(4-(siz)))
#define GS_PIX2DXT(pix, siz) GS_CALC_DXT(GS_PIX2TMEM((pix), (siz)))
/*===========================================================================*
* Data structures for S2DEX microcode
*===========================================================================*/
/*---------------------------------------------------------------------------*
* Background
*---------------------------------------------------------------------------*/
#define G_BGLT_LOADBLOCK 0x0033
#define G_BGLT_LOADTILE 0xfff4
#define G_BG_FLAG_FLIPS 0x01
#define G_BG_FLAG_FLIPT 0x10
/* Non scalable background plane */
typedef struct {
u16 imageX; /* x-coordinate of upper-left position of texture (u10.5) */
u16 imageW; /* width of the texture (u10.2) */
s16 frameX; /* upper-left position of transferred frame (s10.2) */
u16 frameW; /* width of transferred frame (u10.2) */
u16 imageY; /* y-coordinate of upper-left position of texture (u10.5) */
u16 imageH; /* height of the texture (u10.2) */
s16 frameY; /* upper-left position of transferred frame (s10.2) */
u16 frameH; /* height of transferred frame (u10.2) */
u64 *imagePtr; /* texture source address on DRAM */
u16 imageLoad; /* which to use, LoadBlock or LoadTile */
u8 imageFmt; /* format of texel - G_IM_FMT_* */
u8 imageSiz; /* size of texel - G_IM_SIZ_* */
u16 imagePal; /* pallet number */
u16 imageFlip; /* right & left image inversion (Inverted by G_BG_FLAG_FLIPS) */
/* The following is set in the initialization routine guS2DInitBg(). There is no need for the user to set it. */
u16 tmemW; /* TMEM width and Word size of frame 1 line.
At LoadBlock, GS_PIX2TMEM(imageW/4,imageSiz)
At LoadTile GS_PIX2TMEM(frameW/4,imageSiz)+1 */
u16 tmemH; /* height of TMEM loadable at a time (s13.2) 4 times value
When the normal texture, 512/tmemW*4
When the CI texture, 256/tmemW*4 */
u16 tmemLoadSH; /* SH value
At LoadBlock, tmemSize/2-1
At LoadTile, tmemW*16-1 */
u16 tmemLoadTH; /* TH value or Stride value
At LoadBlock, GS_CALC_DXT(tmemW)
At LoadTile, tmemH-1 */
u16 tmemSizeW; /* skip value of imagePtr for image 1-line
At LoadBlock, tmemW*2
At LoadTile, GS_PIX2TMEM(imageW/4,imageSiz)*2 */
u16 tmemSize; /* skip value of imagePtr for 1-loading
= tmemSizeW*tmemH */
} uObjBg_t; /* 40 bytes */
/* Scalable background plane */
typedef struct {
u16 imageX; /* x-coordinate of upper-left position of texture (u10.5) */
u16 imageW; /* width of texture (u10.2) */
s16 frameX; /* upper-left position of transferred frame (s10.2) */
u16 frameW; /* width of transferred frame (u10.2) */
u16 imageY; /* y-coordinate of upper-left position of texture (u10.5) */
u16 imageH; /* height of texture (u10.2) */
s16 frameY; /* upper-left position of transferred frame (s10.2) */
u16 frameH; /* height of transferred frame (u10.2) */
u64 *imagePtr; /* texture source address on DRAM */
u16 imageLoad; /* Which to use, LoadBlock or LoadTile? */
u8 imageFmt; /* format of texel - G_IM_FMT_* */
u8 imageSiz; /* size of texel - G_IM_SIZ_* */
u16 imagePal; /* pallet number */
u16 imageFlip; /* right & left image inversion (Inverted by G_BG_FLAG_FLIPS) */
u16 scaleW; /* scale value of X-direction (u5.10) */
u16 scaleH; /* scale value of Y-direction (u5.10) */
s32 imageYorig; /* start point of drawing on image (s20.5) */
u8 padding[4];
} uObjScaleBg_t; /* 40 bytes */
typedef union {
uObjBg_t b;
uObjScaleBg_t s;
long long int force_structure_alignment;
} uObjBg;
/*---------------------------------------------------------------------------*
* 2D Objects
*---------------------------------------------------------------------------*/
#define G_OBJ_FLAG_FLIPS 1<<0 /* inversion to S-direction */
#define G_OBJ_FLAG_FLIPT 1<<4 /* nversion to T-direction */
typedef struct {
s16 objX; /* s10.2 OBJ x-coordinate of upper-left end */
u16 scaleW; /* u5.10 Scaling of u5.10 width direction */
u16 imageW; /* u10.5 width of u10.5 texture (length of S-direction) */
u16 paddingX; /* Unused - Always 0 */
s16 objY; /* s10.2 OBJ y-coordinate of s10.2 OBJ upper-left end */
u16 scaleH; /* u5.10 Scaling of u5.10 height direction */
u16 imageH; /* u10.5 height of u10.5 texture (length of T-direction) */
u16 paddingY; /* Unused - Always 0 */
u16 imageStride; /* folding width of texel (In units of 64bit word) */
u16 imageAdrs; /* texture header position in TMEM (In units of 64bit word) */
u8 imageFmt; /* format of texel - G_IM_FMT_* */
u8 imageSiz; /* size of texel - G_IM_SIZ_* */
u8 imagePal; /* pallet number (0-7) */
u8 imageFlags; /* The display flag - G_OBJ_FLAG_FLIP* */
} uObjSprite_t; /* 24 bytes */
typedef union {
uObjSprite_t s;
long long int force_structure_alignment;
} uObjSprite;
/*---------------------------------------------------------------------------*
* 2D Matrix
*---------------------------------------------------------------------------*/
typedef struct {
s32 A, B, C, D; /* s15.16 */
s16 X, Y; /* s10.2 */
u16 BaseScaleX; /* u5.10 */
u16 BaseScaleY; /* u5.10 */
} uObjMtx_t; /* 24 bytes */
typedef union {
uObjMtx_t m;
long long int force_structure_alignment;
} uObjMtx;
typedef struct {
s16 X, Y; /* s10.2 */
u16 BaseScaleX; /* u5.10 */
u16 BaseScaleY; /* u5.10 */
} uObjSubMtx_t; /* 8 bytes */
typedef union {
uObjSubMtx_t m;
long long int force_structure_alignment;
} uObjSubMtx;
/*---------------------------------------------------------------------------*
* Loading into TMEM
*---------------------------------------------------------------------------*/
#define G_OBJLT_TXTRBLOCK 0x00001033
#define G_OBJLT_TXTRTILE 0x00fc1034
#define G_OBJLT_TLUT 0x00000030
#define GS_TB_TSIZE(pix,siz) (GS_PIX2TMEM((pix),(siz))-1)
#define GS_TB_TLINE(pix,siz) (GS_CALC_DXT(GS_PIX2TMEM((pix),(siz))))
typedef struct {
u32 type; /* G_OBJLT_TXTRBLOCK divided into types */
u64 *image; /* texture source address on DRAM */
u16 tmem; /* loaded TMEM word address (8byteWORD) */
u16 tsize; /* Texture size, Specified by macro GS_TB_TSIZE() */
u16 tline; /* width of Texture 1-line, Specified by macro GS_TB_TLINE() */
u16 sid; /* STATE ID Multipled by 4 (Either one of 0, 4, 8 and 12) */
u32 flag; /* STATE flag */
u32 mask; /* STATE mask */
} uObjTxtrBlock_t; /* 24 bytes */
#define GS_TT_TWIDTH(pix,siz) ((GS_PIX2TMEM((pix), (siz))<<2)-1)
#define GS_TT_THEIGHT(pix,siz) (((pix)<<2)-1)
typedef struct {
u32 type; /* G_OBJLT_TXTRTILE divided into types */
u64 *image; /* texture source address on DRAM */
u16 tmem; /* loaded TMEM word address (8byteWORD)*/
u16 twidth; /* width of Texture (Specified by macro GS_TT_TWIDTH()) */
u16 theight; /* height of Texture (Specified by macro GS_TT_THEIGHT()) */
u16 sid; /* STATE ID Multipled by 4 (Either one of 0, 4, 8 and 12) */
u32 flag; /* STATE flag */
u32 mask; /* STATE mask */
} uObjTxtrTile_t; /* 24 bytes */
#define GS_PAL_HEAD(head) ((head)+256)
#define GS_PAL_NUM(num) ((num)-1)
typedef struct {
u32 type; /* G_OBJLT_TLUT divided into types */
u64 *image; /* texture source address on DRAM */
u16 phead; /* pallet number of load header (Between 256 and 511) */
u16 pnum; /* loading pallet number -1 */
u16 zero; /* Assign 0 all the time */
u16 sid; /* STATE ID Multipled by 4 (Either one of 0, 4, 8 and 12)*/
u32 flag; /* STATE flag */
u32 mask; /* STATE mask */
} uObjTxtrTLUT_t; /* 24 bytes */
typedef union {
uObjTxtrBlock_t block;
uObjTxtrTile_t tile;
uObjTxtrTLUT_t tlut;
long long int force_structure_alignment;
} uObjTxtr;
/*---------------------------------------------------------------------------*
* Loading into TMEM & 2D Objects
*---------------------------------------------------------------------------*/
typedef struct {
uObjTxtr txtr;
uObjSprite sprite;
} uObjTxSprite; /* 48 bytes */
/*===========================================================================*
* GBI Commands for S2DEX microcode
*===========================================================================*/
/* GBI Header */
#ifdef F3DEX_GBI_2
#define G_OBJ_RECTANGLE_R 0xda
#define G_OBJ_MOVEMEM 0xdc
#define G_RDPHALF_0 0xe4
#define G_OBJ_RECTANGLE 0x01
#define G_OBJ_SPRITE 0x02
#define G_SELECT_DL 0x04
#define G_OBJ_LOADTXTR 0x05
#define G_OBJ_LDTX_SPRITE 0x06
#define G_OBJ_LDTX_RECT 0x07
#define G_OBJ_LDTX_RECT_R 0x08
#define G_BG_1CYC 0x09
#define G_BG_COPY 0x0a
#define G_OBJ_RENDERMODE 0x0b
#else
#define G_BG_1CYC 0x01
#define G_BG_COPY 0x02
#define G_OBJ_RECTANGLE 0x03
#define G_OBJ_SPRITE 0x04
#define G_OBJ_MOVEMEM 0x05
#define G_SELECT_DL 0xb0
#define G_OBJ_RENDERMODE 0xb1
#define G_OBJ_RECTANGLE_R 0xb2
#define G_OBJ_LOADTXTR 0xc1
#define G_OBJ_LDTX_SPRITE 0xc2
#define G_OBJ_LDTX_RECT 0xc3
#define G_OBJ_LDTX_RECT_R 0xc4
#define G_RDPHALF_0 0xe4
#endif
/*---------------------------------------------------------------------------*
* Background wrapped screen
*---------------------------------------------------------------------------*/
#define gSPBgRectangle(pkt, m, mptr) gDma0p((pkt),(m),(mptr),0)
#define gsSPBgRectangle(m, mptr) gsDma0p( (m),(mptr),0)
#define gSPBgRectCopy(pkt, mptr) gSPBgRectangle((pkt), G_BG_COPY, (mptr))
#define gsSPBgRectCopy(mptr) gsSPBgRectangle( G_BG_COPY, (mptr))
#define gSPBgRect1Cyc(pkt, mptr) gSPBgRectangle((pkt), G_BG_1CYC, (mptr))
#define gsSPBgRect1Cyc(mptr) gsSPBgRectangle( G_BG_1CYC, (mptr))
/*---------------------------------------------------------------------------*
* 2D Objects
*---------------------------------------------------------------------------*/
#define gSPObjSprite(pkt, mptr) gDma0p((pkt),G_OBJ_SPRITE, (mptr),0)
#define gsSPObjSprite(mptr) gsDma0p( G_OBJ_SPRITE, (mptr),0)
#define gSPObjRectangle(pkt, mptr) gDma0p((pkt),G_OBJ_RECTANGLE, (mptr),0)
#define gsSPObjRectangle(mptr) gsDma0p( G_OBJ_RECTANGLE, (mptr),0)
#define gSPObjRectangleR(pkt, mptr) gDma0p((pkt),G_OBJ_RECTANGLE_R,(mptr),0)
#define gsSPObjRectangleR(mptr) gsDma0p( G_OBJ_RECTANGLE_R,(mptr),0)
/*---------------------------------------------------------------------------*
* 2D Matrix
*---------------------------------------------------------------------------*/
#define gSPObjMatrix(pkt, mptr) gDma1p((pkt),G_OBJ_MOVEMEM,(mptr),0,23)
#define gsSPObjMatrix(mptr) gsDma1p( G_OBJ_MOVEMEM,(mptr),0,23)
#define gSPObjSubMatrix(pkt, mptr) gDma1p((pkt),G_OBJ_MOVEMEM,(mptr),2, 7)
#define gsSPObjSubMatrix(mptr) gsDma1p( G_OBJ_MOVEMEM,(mptr),2, 7)
/*---------------------------------------------------------------------------*
* Loading into TMEM
*---------------------------------------------------------------------------*/
#define gSPObjLoadTxtr(pkt, tptr) gDma0p((pkt),G_OBJ_LOADTXTR, (tptr),23)
#define gsSPObjLoadTxtr(tptr) gsDma0p( G_OBJ_LOADTXTR, (tptr),23)
#define gSPObjLoadTxSprite(pkt, tptr) gDma0p((pkt),G_OBJ_LDTX_SPRITE,(tptr),47)
#define gsSPObjLoadTxSprite(tptr) gsDma0p( G_OBJ_LDTX_SPRITE,(tptr),47)
#define gSPObjLoadTxRect(pkt, tptr) gDma0p((pkt),G_OBJ_LDTX_RECT, (tptr),47)
#define gsSPObjLoadTxRect(tptr) gsDma0p( G_OBJ_LDTX_RECT, (tptr),47)
#define gSPObjLoadTxRectR(pkt, tptr) gDma0p((pkt),G_OBJ_LDTX_RECT_R,(tptr),47)
#define gsSPObjLoadTxRectR(tptr) gsDma0p( G_OBJ_LDTX_RECT_R,(tptr),47)
/*---------------------------------------------------------------------------*
* Select Display List
*---------------------------------------------------------------------------*/
#define gSPSelectDL(pkt, mptr, sid, flag, mask) \
{ gDma1p((pkt), G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gDma1p((pkt), G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_PUSH); }
#define gsSPSelectDL(mptr, sid, flag, mask) \
{ gsDma1p(G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gsDma1p(G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_PUSH); }
#define gSPSelectBranchDL(pkt, mptr, sid, flag, mask) \
{ gDma1p((pkt), G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gDma1p((pkt), G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_NOPUSH); }
#define gsSPSelectBranchDL(mptr, sid, flag, mask) \
{ gsDma1p(G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gsDma1p(G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_NOPUSH); }
/*---------------------------------------------------------------------------*
* Set general status
*---------------------------------------------------------------------------*/
#define G_MW_GENSTAT 0x08 /* Note that it is the same value of G_MW_FOG */
#define gSPSetStatus(pkt, sid, val) \
gMoveWd((pkt), G_MW_GENSTAT, (sid), (val))
#define gsSPSetStatus(sid, val) \
gsMoveWd( G_MW_GENSTAT, (sid), (val))
/*---------------------------------------------------------------------------*
* Set Object Render Mode
*---------------------------------------------------------------------------*/
#define G_OBJRM_NOTXCLAMP 0x01
#define G_OBJRM_XLU 0x02 /* Ignored */
#define G_OBJRM_ANTIALIAS 0x04 /* Ignored */
#define G_OBJRM_BILERP 0x08
#define G_OBJRM_SHRINKSIZE_1 0x10
#define G_OBJRM_SHRINKSIZE_2 0x20
#define G_OBJRM_WIDEN 0x40
#define gSPObjRenderMode(pkt, mode) gImmp1((pkt),G_OBJ_RENDERMODE,(mode))
#define gsSPObjRenderMode(mode) gsImmp1( G_OBJ_RENDERMODE,(mode))
/*===========================================================================*
* Render Mode Macro
*===========================================================================*/
#define RM_RA_SPRITE(clk) \
AA_EN | CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define G_RM_SPRITE G_RM_OPA_SURF
#define G_RM_SPRITE2 G_RM_OPA_SURF2
#define G_RM_RA_SPRITE RM_RA_SPRITE(1)
#define G_RM_RA_SPRITE2 RM_RA_SPRITE(2)
#define G_RM_AA_SPRITE G_RM_AA_TEX_TERR
#define G_RM_AA_SPRITE2 G_RM_AA_TEX_TERR2
#define G_RM_XLU_SPRITE G_RM_XLU_SURF
#define G_RM_XLU_SPRITE2 G_RM_XLU_SURF2
#define G_RM_AA_XLU_SPRITE G_RM_AA_XLU_SURF
#define G_RM_AA_XLU_SPRITE2 G_RM_AA_XLU_SURF2
/*===========================================================================*
* External functions
*===========================================================================*/
extern u64 gspS2DEX_fifoTextStart[], gspS2DEX_fifoTextEnd[];
extern u64 gspS2DEX_fifoDataStart[], gspS2DEX_fifoDataEnd[];
extern u64 gspS2DEX_fifo_dTextStart[], gspS2DEX_fifo_dTextEnd[];
extern u64 gspS2DEX_fifo_dDataStart[], gspS2DEX_fifo_dDataEnd[];
extern u64 gspS2DEX2_fifoTextStart[], gspS2DEX2_fifoTextEnd[];
extern u64 gspS2DEX2_fifoDataStart[], gspS2DEX2_fifoDataEnd[];
extern u64 gspS2DEX2_xbusTextStart[], gspS2DEX2_xbusTextEnd[];
extern u64 gspS2DEX2_xbusDataStart[], gspS2DEX2_xbusDataEnd[];
extern void guS2DInitBg(uObjBg *);
#ifdef F3DEX_GBI_2
# define guS2DEmuBgRect1Cyc guS2D2EmuBgRect1Cyc /*Wrapper*/
# define guS2DEmuSetScissor guS2D2EmuSetScissor /*Wrapper*/
extern void guS2D2EmuSetScissor(u32, u32, u32, u32, u8);
extern void guS2D2EmuBgRect1Cyc(Gfx **, uObjBg *);
#else
extern void guS2DEmuSetScissor(u32, u32, u32, u32, u8);
extern void guS2DEmuBgRect1Cyc(Gfx **, uObjBg *);
#endif
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* _GS2DEX_H_ */
/*======== End of gs2dex.h ========*/
include/ultra64/gu.h → include/PR/gu.h
+8
View File
@@ -1,6 +1,9 @@
#ifndef _ULTRA64_GU_H_
#define _ULTRA64_GU_H_
#include <PR/mbi.h>
#include <PR/ultratypes.h>
#define GU_PI 3.1415926
/* Functions */
@@ -18,4 +21,9 @@ void guMtxIdent(Mtx *m);
void guMtxIdentF(float mf[4][4]);
void guMtxL2F(float mf[4][4], Mtx *m);
void guNormalize(float *, float *, float *);
/* Used only in Fast3DEX2 */
void guLookAtReflect (Mtx *m, LookAt *l, float xEye, float yEye, float zEye,
float xAt, float yAt, float zAt,
float xUp, float yUp, float zUp);
#endif
include/PR/libaudio.h
+48
View File
@@ -0,0 +1,48 @@
#ifndef _ULTRA64_LIBAUDIO_H_
#define _ULTRA64_LIBAUDIO_H_
#include "abi.h"
typedef struct
{
u8 *offset;
s32 len;
#ifdef VERSION_SH
s8 magic[2]; // tbl: 0x0204, otherwise: 0x0203
// for ctl (else zeros):
union {
// unused, just for clarification (big endian)
struct {
u8 bank;
u8 ff;
u8 numInstruments;
u8 numDrums;
} as_u8;
// used
struct {
s16 bankAndFf;
s16 numInstrumentsAndDrums;
} as_s16;
} ctl;
#endif
} ALSeqData;
typedef struct
{
#ifndef VERSION_SH
s16 revision;
#endif
s16 seqCount;
#ifdef VERSION_SH
s16 unk2;
u8 *data;
s32 pad[2];
#endif
ALSeqData seqArray[1];
} ALSeqFile;
void alSeqFileNew(ALSeqFile *f, u8 *base);
#endif
include/ultra64/libultra.h → include/PR/libultra.h
+2 -1
View File
@@ -12,6 +12,7 @@
extern u32 osTvType;
extern u32 osRomBase;
extern u32 osResetType;
extern u32 osMemSize;
extern u8 osAppNmiBuffer[64];
extern u64 osClockRate;
#endif /* _LIBULTRA_H */
include/PR/mbi.h
+102
View File
@@ -0,0 +1,102 @@
#ifndef _MBI_H_
#define _MBI_H_
#include "platform_info.h"
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* $Revision: 1.136 $
* $Date: 1999/01/05 13:04:00 $
* $Source: /hosts/gate3/exdisk2/cvs/N64OS/Master/cvsmdev2/PR/include/mbi.h,v $
*
**************************************************************************/
/*
* Header file for the Media Binary Interface
*
* NOTE: This file is included by the RSP microcode, so any C-specific
* constructs must be bracketed by #ifdef _LANGUAGE_C
*
*/
/*
* the SHIFT macros are used to build display list commands, inserting
* bit-fields into a 32-bit word. They take a value, a shift amount,
* and a width.
*
* For the left shift, the lower bits of the value are masked,
* then shifted left.
*
* For the right shift, the value is shifted right, then the lower bits
* are masked.
*
* (NOTE: _SHIFTL(v, 0, 32) won't work, just use an assignment)
*
*/
#define _SHIFTL(v, s, w) \
((unsigned int) (((unsigned int)(v) & ((0x01 << (w)) - 1)) << (s)))
#define _SHIFTR(v, s, w) \
((unsigned int)(((unsigned int)(v) >> (s)) & ((0x01 << (w)) - 1)))
#define _SHIFT _SHIFTL /* old, for compatibility only */
#define G_ON (1)
#define G_OFF (0)
/**************************************************************************
*
* Graphics Binary Interface
*
**************************************************************************/
#include <PR/gbi.h>
/**************************************************************************
*
* Audio Binary Interface
*
**************************************************************************/
#include <PR/abi.h>
/**************************************************************************
*
* Task list
*
**************************************************************************/
#define M_GFXTASK 1
#define M_AUDTASK 2
#define M_VIDTASK 3
#define M_HVQTASK 6
#define M_HVQMTASK 7
/**************************************************************************
*
* Segment macros and definitions
*
**************************************************************************/
#define NUM_SEGMENTS (16)
#define SEGMENT_OFFSET(a) ((unsigned int)(a) & 0x00ffffff)
#define SEGMENT_NUMBER(a) (((unsigned int)(a) << 4) >> 28)
#define SEGMENT_ADDR(num, off) (((num) << 24) + (off))
#ifndef NULL
#define NULL 0
#endif
#endif /* !_MBI_H_ */
include/PR/os_ai.h
+92
View File
@@ -0,0 +1,92 @@
/*====================================================================
* os_ai.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_ai.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:04 $
*---------------------------------------------------------------------*/
#ifndef _OS_AI_H_
#define _OS_AI_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Audio interface (Ai) */
extern u32 osAiGetStatus(void);
extern u32 osAiGetLength(void);
extern s32 osAiSetFrequency(u32);
extern s32 osAiSetNextBuffer(void *, u32);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_AI_H_ */
include/PR/os_cache.h
+96
View File
@@ -0,0 +1,96 @@
/*====================================================================
* os_cache.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_cache.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:04 $
*---------------------------------------------------------------------*/
#ifndef _OS_CACHE_H_
#define _OS_CACHE_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
#define OS_DCACHE_ROUNDUP_ADDR(x) (void *)(((((u32)(x)+0xf)/0x10)*0x10))
#define OS_DCACHE_ROUNDUP_SIZE(x) (u32)(((((u32)(x)+0xf)/0x10)*0x10))
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Cache operations and macros */
extern void osInvalDCache(void *, size_t);
extern void osInvalICache(void *, size_t);
extern void osWritebackDCache(void *, size_t);
extern void osWritebackDCacheAll(void);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_CACHE_H_ */
include/PR/os_cont.h
+207
View File
@@ -0,0 +1,207 @@
/*====================================================================
* os_cont.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_cont.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:05 $
*---------------------------------------------------------------------*/
#ifndef _OS_CONT_H_
#define _OS_CONT_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include "os_message.h"
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
/*
* Structure for controllers
*/
typedef struct {
u16 type; /* Controller Type */
u8 status; /* Controller status */
u8 errnum;
}OSContStatus;
typedef struct {
u16 button;
s8 stick_x; /* -80 <= stick_x <= 80 */
s8 stick_y; /* -80 <= stick_y <= 80 */
u8 errnum;
} OSContPad;
typedef struct {
void *address; /* Ram pad Address: 11 bits */
u8 databuffer[32]; /* address of the data buffer */
u8 addressCrc; /* CRC code for address */
u8 dataCrc; /* CRC code for data */
u8 errnum;
} OSContRamIo;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/*
* Controllers number
*/
#ifndef _HW_VERSION_1
#define MAXCONTROLLERS 4
#else
#define MAXCONTROLLERS 6
#endif
/* controller errors */
#define CONT_NO_RESPONSE_ERROR 0x8
#define CONT_OVERRUN_ERROR 0x4
#ifdef _HW_VERSION_1
#define CONT_FRAME_ERROR 0x2
#define CONT_COLLISION_ERROR 0x1
#endif
/* Controller type */
#define CONT_ABSOLUTE 0x0001
#define CONT_RELATIVE 0x0002
#define CONT_JOYPORT 0x0004
#define CONT_EEPROM 0x8000
#define CONT_EEP16K 0x4000
#define CONT_TYPE_MASK 0x1f07
#define CONT_TYPE_NORMAL 0x0005
#define CONT_TYPE_MOUSE 0x0002
#define CONT_TYPE_VOICE 0x0100
/* Controller status */
#define CONT_CARD_ON 0x01
#define CONT_CARD_PULL 0x02
#define CONT_ADDR_CRC_ER 0x04
#define CONT_EEPROM_BUSY 0x80
/* Buttons */
#define CONT_A 0x8000
#define CONT_B 0x4000
#define CONT_G 0x2000
#define CONT_START 0x1000
#define CONT_UP 0x0800
#define CONT_DOWN 0x0400
#define CONT_LEFT 0x0200
#define CONT_RIGHT 0x0100
#define CONT_L 0x0020
#define CONT_R 0x0010
#define CONT_E 0x0008
#define CONT_D 0x0004
#define CONT_C 0x0002
#define CONT_F 0x0001
/* Nintendo's official button names */
#define A_BUTTON CONT_A
#define B_BUTTON CONT_B
#define L_TRIG CONT_L
#define R_TRIG CONT_R
#define Z_TRIG CONT_G
#define START_BUTTON CONT_START
#define U_JPAD CONT_UP
#define L_JPAD CONT_LEFT
#define R_JPAD CONT_RIGHT
#define D_JPAD CONT_DOWN
#define U_CBUTTONS CONT_E
#define L_CBUTTONS CONT_C
#define R_CBUTTONS CONT_F
#define D_CBUTTONS CONT_D
/* Controller error number */
#define CONT_ERR_NO_CONTROLLER PFS_ERR_NOPACK /* 1 */
#define CONT_ERR_CONTRFAIL CONT_OVERRUN_ERROR /* 4 */
#define CONT_ERR_INVALID PFS_ERR_INVALID /* 5 */
#define CONT_ERR_DEVICE PFS_ERR_DEVICE /* 11 */
#define CONT_ERR_NOT_READY 12
#define CONT_ERR_VOICE_MEMORY 13
#define CONT_ERR_VOICE_WORD 14
#define CONT_ERR_VOICE_NO_RESPONSE 15
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Controller interface */
extern s32 osContInit(OSMesgQueue *, u8 *, OSContStatus *);
extern s32 osContReset(OSMesgQueue *, OSContStatus *);
extern s32 osContStartQuery(OSMesgQueue *);
extern s32 osContStartReadData(OSMesgQueue *);
#ifndef _HW_VERSION_1
extern s32 osContSetCh(u8);
#endif
extern void osContGetQuery(OSContStatus *);
extern void osContGetReadData(OSContPad *);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_CONT_H_ */
include/PR/os_eeprom.h
+107
View File
@@ -0,0 +1,107 @@
/*====================================================================
* os_eeprom.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_eeprom.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:06 $
*---------------------------------------------------------------------*/
#ifndef _OS_EEPROM_H_
#define _OS_EEPROM_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include "os_message.h"
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/* EEPROM TYPE */
#define EEPROM_TYPE_4K 0x01
#define EEPROM_TYPE_16K 0x02
/* definition for EEPROM */
#define EEPROM_MAXBLOCKS 64
#define EEP16K_MAXBLOCKS 256
#define EEPROM_BLOCK_SIZE 8
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* EEPROM interface */
extern s32 osEepromProbe(OSMesgQueue *);
extern s32 osEepromRead(OSMesgQueue *, u8, u8 *);
extern s32 osEepromWrite(OSMesgQueue *, u8, u8 *);
extern s32 osEepromLongRead(OSMesgQueue *, u8, u8 *, int);
extern s32 osEepromLongWrite(OSMesgQueue *, u8, u8 *, int);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_EEPROM_H_ */
include/PR/os_exception.h
+119
View File
@@ -0,0 +1,119 @@
/*====================================================================
* os_exception.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_exception.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:07 $
*---------------------------------------------------------------------*/
#ifndef _OS_EXCEPTION_H_
#define _OS_EXCEPTION_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
typedef u32 OSIntMask;
typedef u32 OSHWIntr;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/* Flags for debugging purpose */
#define OS_FLAG_CPU_BREAK 1 /* Break exception has occurred */
#define OS_FLAG_FAULT 2 /* CPU fault has occurred */
/* Interrupt masks */
#define OS_IM_NONE 0x00000001
#define OS_IM_SW1 0x00000501
#define OS_IM_SW2 0x00000601
#define OS_IM_CART 0x00000c01
#define OS_IM_PRENMI 0x00001401
#define OS_IM_RDBWRITE 0x00002401
#define OS_IM_RDBREAD 0x00004401
#define OS_IM_COUNTER 0x00008401
#define OS_IM_CPU 0x0000ff01
#define OS_IM_SP 0x00010401
#define OS_IM_SI 0x00020401
#define OS_IM_AI 0x00040401
#define OS_IM_VI 0x00080401
#define OS_IM_PI 0x00100401
#define OS_IM_DP 0x00200401
#define OS_IM_ALL 0x003fff01
#define RCP_IMASK 0x003f0000
#define RCP_IMASKSHIFT 16
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Interrupt operations */
extern OSIntMask osGetIntMask(void);
extern OSIntMask osSetIntMask(OSIntMask);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_EXCEPTION_H_ */
include/ultra64/os_internal.h → include/PR/os_internal.h
+4 -1
View File
@@ -1,16 +1,19 @@
#ifndef _ULTRA64_OS_INTERNAL_H_
#define _ULTRA64_OS_INTERNAL_H_
#include "PR/os_message.h"
/* Internal functions used by the operating system */
/* Do not include this header in application code */
/* Variables */
//extern u64 osClockRate;
extern u64 osClockRate;
/* Functions */
/*u32 __osProbeTLB(void *);
u32 __osDisableInt(void);
void __osRestoreInt(u32);*/
OSThread *__osGetCurrFaultedThread(void);
#endif
include/PR/os_libc.h
+10
View File
@@ -0,0 +1,10 @@
#ifndef _OS_LIBC_H_
#define _OS_LIBC_H_
#include "ultratypes.h"
// Old deprecated functions from strings.h, replaced by memcpy/memset.
extern void bcopy(const void *, void *, size_t);
extern void bzero(void *, size_t);
#endif /* !_OS_LIBC_H_ */
include/PR/os_message.h
+164
View File
@@ -0,0 +1,164 @@
/*====================================================================
* os_message.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_message.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:15 $
*---------------------------------------------------------------------*/
#ifndef _OS_MESSAGE_H_
#define _OS_MESSAGE_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include <PR/os_thread.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
typedef u32 OSEvent;
/*
* Structure for message
*/
typedef void * OSMesg;
/*
* Structure for message queue
*/
typedef struct OSMesgQueue_s {
OSThread *mtqueue; /* Queue to store threads blocked
on empty mailboxes (receive) */
OSThread *fullqueue; /* Queue to store threads blocked
on full mailboxes (send) */
s32 validCount; /* Contains number of valid message */
s32 first; /* Points to first valid message */
s32 msgCount; /* Contains total # of messages */
OSMesg *msg; /* Points to message buffer array */
} OSMesgQueue;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/* Events */
#ifdef _FINALROM
#define OS_NUM_EVENTS 15
#else
#define OS_NUM_EVENTS 23
#endif
#define OS_EVENT_SW1 0 /* CPU SW1 interrupt */
#define OS_EVENT_SW2 1 /* CPU SW2 interrupt */
#define OS_EVENT_CART 2 /* Cartridge interrupt: used by rmon */
#define OS_EVENT_COUNTER 3 /* Counter int: used by VI/Timer Mgr */
#define OS_EVENT_SP 4 /* SP task done interrupt */
#define OS_EVENT_SI 5 /* SI (controller) interrupt */
#define OS_EVENT_AI 6 /* AI interrupt */
#define OS_EVENT_VI 7 /* VI interrupt: used by VI/Timer Mgr */
#define OS_EVENT_PI 8 /* PI interrupt: used by PI Manager */
#define OS_EVENT_DP 9 /* DP full sync interrupt */
#define OS_EVENT_CPU_BREAK 10 /* CPU breakpoint: used by rmon */
#define OS_EVENT_SP_BREAK 11 /* SP breakpoint: used by rmon */
#define OS_EVENT_FAULT 12 /* CPU fault event: used by rmon */
#define OS_EVENT_THREADSTATUS 13 /* CPU thread status: used by rmon */
#define OS_EVENT_PRENMI 14 /* Pre NMI interrupt */
#ifndef _FINALROM
#define OS_EVENT_RDB_READ_DONE 15 /* RDB read ok event: used by rmon */
#define OS_EVENT_RDB_LOG_DONE 16 /* read of log data complete */
#define OS_EVENT_RDB_DATA_DONE 17 /* read of hostio data complete */
#define OS_EVENT_RDB_REQ_RAMROM 18 /* host needs ramrom access */
#define OS_EVENT_RDB_FREE_RAMROM 19 /* host is done with ramrom access */
#define OS_EVENT_RDB_DBG_DONE 20
#define OS_EVENT_RDB_FLUSH_PROF 21
#define OS_EVENT_RDB_ACK_PROF 22
#endif
/* Flags to turn blocking on/off when sending/receiving message */
#define OS_MESG_NOBLOCK 0
#define OS_MESG_BLOCK 1
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/* Get count of valid messages in queue */
#define MQ_GET_COUNT(mq) ((mq)->validCount)
/* Figure out if message queue is empty or full */
#define MQ_IS_EMPTY(mq) (MQ_GET_COUNT(mq) == 0)
#define MQ_IS_FULL(mq) (MQ_GET_COUNT(mq) >= (mq)->msgCount)
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Message operations */
extern void osCreateMesgQueue(OSMesgQueue *, OSMesg *, s32);
extern s32 osSendMesg(OSMesgQueue *, OSMesg, s32);
extern s32 osJamMesg(OSMesgQueue *, OSMesg, s32);
extern s32 osRecvMesg(OSMesgQueue *, OSMesg *, s32);
/* Event operations */
extern void osSetEventMesg(OSEvent, OSMesgQueue *, OSMesg);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_MESSAGE_H_ */
include/ultra64/os_misc.h → include/PR/os_misc.h
+2 -2
View File
@@ -1,11 +1,11 @@
#ifndef _ULTRA64_OS_MISC_H_
#define _ULTRA64_OS_MISC_H_
#include <PR/ultratypes.h>
/* Miscellaneous OS functions */
void osInitialize(void);
u32 osGetCount(void);
u32 osVirtualToPhysical(void *);
uintptr_t osVirtualToPhysical(void *);
#endif
include/PR/os_pi.h
+86
View File
@@ -0,0 +1,86 @@
#ifndef _ULTRA64_PI_H_
#define _ULTRA64_PI_H_
#include <ultra64.h>
/* Ultra64 Parallel Interface */
/* Types */
typedef struct {
#if !defined(VERSION_EU)
u32 errStatus;
#endif
void *dramAddr;
void *C2Addr;
u32 sectorSize;
u32 C1ErrNum;
u32 C1ErrSector[4];
} __OSBlockInfo;
typedef struct {
u32 cmdType; // 0
u16 transferMode; // 4
u16 blockNum; // 6
s32 sectorNum; // 8
uintptr_t devAddr; // c
#if defined(VERSION_EU)
u32 errStatus; //error status added moved to blockinfo
#endif
u32 bmCtlShadow; // 10
u32 seqCtlShadow; // 14
__OSBlockInfo block[2]; // 18
} __OSTranxInfo;
typedef struct OSPiHandle_s {
struct OSPiHandle_s *next;
u8 type;
u8 latency;
u8 pageSize;
u8 relDuration;
u8 pulse;
u8 domain;
u32 baseAddress;
u32 speed;
__OSTranxInfo transferInfo;
} OSPiHandle;
typedef struct {
u8 type;
uintptr_t address;
} OSPiInfo;
typedef struct {
u16 type;
u8 pri;
u8 status;
OSMesgQueue *retQueue;
} OSIoMesgHdr;
typedef struct {
/*0x00*/ OSIoMesgHdr hdr;
/*0x08*/ void *dramAddr;
/*0x0C*/ uintptr_t devAddr;
/*0x10*/ size_t size;
OSPiHandle *piHandle; // from the official definition
} OSIoMesg;
/* Definitions */
#define OS_READ 0 // device -> RDRAM
#define OS_WRITE 1 // device <- RDRAM
#define OS_MESG_PRI_NORMAL 0
#define OS_MESG_PRI_HIGH 1
/* Functions */
s32 osPiStartDma(OSIoMesg *mb, s32 priority, s32 direction, uintptr_t devAddr, void *vAddr,
size_t nbytes, OSMesgQueue *mq);
void osCreatePiManager(OSPri pri, OSMesgQueue *cmdQ, OSMesg *cmdBuf, s32 cmdMsgCnt);
OSMesgQueue *osPiGetCmdQueue(void);
s32 osPiWriteIo(uintptr_t devAddr, u32 data);
s32 osPiReadIo(uintptr_t devAddr, u32 *data);
s32 osPiRawStartDma(s32 dir, u32 cart_addr, void *dram_addr, size_t size);
s32 osEPiRawStartDma(OSPiHandle *piHandle, s32 dir, u32 cart_addr, void *dram_addr, size_t size);
#endif
include/PR/os_rdp.h
+92
View File
@@ -0,0 +1,92 @@
/*====================================================================
* os_rdp.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_rdp.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:16 $
*---------------------------------------------------------------------*/
#ifndef _OS_RDP_H_
#define _OS_RDP_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Display processor interface (Dp) */
extern u32 osDpGetStatus(void);
extern void osDpSetStatus(u32);
extern void osDpGetCounters(u32 *);
extern s32 osDpSetNextBuffer(void *, u64);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_RDP_H_ */
include/ultra64/thread.h → include/PR/os_thread.h
+1 -1
View File
@@ -1,6 +1,6 @@
#ifndef _ULTRA64_THREAD_H_
#define _ULTRA64_THREAD_H_
#include "ultratypes.h"
/* Recommended priorities for system threads */
#define OS_PRIORITY_MAX 255
#define OS_PRIORITY_VIMGR 254
include/ultra64/time.h → include/PR/os_time.h
+4 -2
View File
@@ -1,6 +1,8 @@
#ifndef _ULTRA64_TIME_H_
#define _ULTRA64_TIME_H_
#include "message.h"
#include <PR/ultratypes.h>
#include <PR/os_message.h>
/* Types */
@@ -20,6 +22,6 @@ typedef u64 OSTime;
OSTime osGetTime(void);
void osSetTime(OSTime time);
u32 osSetTimer(OSTimer *, OSTime, u64, OSMesgQueue *, OSMesg);
u32 osSetTimer(OSTimer *, OSTime, OSTime, OSMesgQueue *, OSMesg);
#endif
include/PR/os_tlb.h
+107
View File
@@ -0,0 +1,107 @@
/*====================================================================
* os_tlb.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_tlb.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:20 $
*---------------------------------------------------------------------*/
#ifndef _OS_TLB_H_
#define _OS_TLB_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
typedef u32 OSPageMask;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/*
* Page size argument for TLB routines
*/
#define OS_PM_4K 0x0000000
#define OS_PM_16K 0x0006000
#define OS_PM_64K 0x001e000
#define OS_PM_256K 0x007e000
#define OS_PM_1M 0x01fe000
#define OS_PM_4M 0x07fe000
#define OS_PM_16M 0x1ffe000
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* TLB management routines */
extern void osMapTLB(s32, OSPageMask, void *, u32, u32, s32);
extern void osMapTLBRdb(void);
extern void osUnmapTLB(s32);
extern void osUnmapTLBAll(void);
extern void osSetTLBASID(s32);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_TLB_H_ */
include/ultra64/vi.h → include/PR/os_vi.h
+6 -31
View File
@@ -1,6 +1,9 @@
#ifndef _ULTRA64_VI_H_
#define _ULTRA64_VI_H_
#include <PR/ultratypes.h>
#include <PR/os_message.h>
/* Ultra64 Video Interface */
@@ -58,7 +61,7 @@ typedef struct
/* 0x00 */ u16 unk00; //some kind of flags. swap buffer sets to 0x10
/* 0x02 */ u16 retraceCount;
/* 0x04 */ void* buffer;
/* 0x08 */ OSViMode *unk08;
/* 0x08 */ OSViMode *modep;
/* 0x0c */ u32 features;
/* 0x10 */ OSMesgQueue *mq;
/* 0x14 */ OSMesg *msg;
@@ -72,6 +75,7 @@ typedef struct
void osCreateViManager(OSPri pri);
void osViSetMode(OSViMode *mode);
void osViSetEvent(OSMesgQueue *mq, OSMesg msg, u32 retraceCount);
void osViBlack(u8 active);
void osViSetSpecialFeatures(u32 func);
void osViSwapBuffer(void *vaddr);
@@ -107,36 +111,7 @@ void osViSwapBuffer(void *vaddr);
#define OS_VI_PAL_HPN2 26
#define OS_VI_PAL_HPF2 27
#define OS_VI_MPAL_LPN1 28 /* MPAL - mainly Brazil */
#define OS_VI_MPAL_LPF1 29
#define OS_VI_MPAL_LAN1 30
#define OS_VI_MPAL_LAF1 31
#define OS_VI_MPAL_LPN2 32
#define OS_VI_MPAL_LPF2 33
#define OS_VI_MPAL_LAN2 34
#define OS_VI_MPAL_LAF2 35
#define OS_VI_MPAL_HPN1 36
#define OS_VI_MPAL_HPF1 37
#define OS_VI_MPAL_HAN1 38
#define OS_VI_MPAL_HAF1 39
#define OS_VI_MPAL_HPN2 40
#define OS_VI_MPAL_HPF2 41
#define OS_VI_FPAL_LPN1 42 /* FPAL - Full screen PAL */
#define OS_VI_FPAL_LPF1 43
#define OS_VI_FPAL_LAN1 44
#define OS_VI_FPAL_LAF1 45
#define OS_VI_FPAL_LPN2 46
#define OS_VI_FPAL_LPF2 47
#define OS_VI_FPAL_LAN2 48
#define OS_VI_FPAL_LAF2 49
#define OS_VI_FPAL_HPN1 50
#define OS_VI_FPAL_HPF1 51
#define OS_VI_FPAL_HAN1 52
#define OS_VI_FPAL_HAF1 53
#define OS_VI_FPAL_HPN2 54
#define OS_VI_FPAL_HPF2 55
#define OS_VI_MPAL_LAN1 30
extern OSViMode osViModeTable[]; /* Global VI mode table */
include/PR/rcp.h
+881
View File
@@ -0,0 +1,881 @@
#ifndef _RCP_H_
#define _RCP_H_
/**************************************************************************
* *
* Copyright (C) 1995, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* File: rcp.h
*
* This file contains register and bit definitions for RCP memory map.
* $Revision: 1.20 $
* $Date: 1997/07/23 08:35:21 $
* $Source: /disk6/Master/cvsmdev2/PR/include/rcp.h,v $
*
**************************************************************************/
#include <PR/R4300.h>
#include <PR/ultratypes.h>
/**********************************************************************
*
* Here is a quick overview of the RCP memory map:
*
0x0000_0000 .. 0x03ef_ffff RDRAM memory
0x03f0_0000 .. 0x03ff_ffff RDRAM registers
RCP registers (see below)
0x0400_0000 .. 0x040f_ffff SP registers
0x0410_0000 .. 0x041f_ffff DP command registers
0x0420_0000 .. 0x042f_ffff DP span registers
0x0430_0000 .. 0x043f_ffff MI registers
0x0440_0000 .. 0x044f_ffff VI registers
0x0450_0000 .. 0x045f_ffff AI registers
0x0460_0000 .. 0x046f_ffff PI registers
0x0470_0000 .. 0x047f_ffff RI registers
0x0480_0000 .. 0x048f_ffff SI registers
0x0490_0000 .. 0x04ff_ffff unused
0x0500_0000 .. 0x05ff_ffff cartridge domain 2
0x0600_0000 .. 0x07ff_ffff cartridge domain 1
0x0800_0000 .. 0x0fff_ffff cartridge domain 2
0x1000_0000 .. 0x1fbf_ffff cartridge domain 1
0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
0x1fc0_0800 .. 0x1fcf_ffff Reserved
0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
0x8000_0000 .. 0xffff_ffff external SysAD device
The Indy development board use cartridge domain 1:
0x1000_0000 .. 0x10ff_ffff RAMROM
0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
**************************************************************************/
/*************************************************************************
* RDRAM Memory (Assumes that maximum size is 4 MB)
*/
#define RDRAM_0_START 0x00000000
#define RDRAM_0_END 0x001FFFFF
#define RDRAM_1_START 0x00200000
#define RDRAM_1_END 0x003FFFFF
#define RDRAM_START RDRAM_0_START
#define RDRAM_END RDRAM_1_END
/*************************************************************************
* Address predicates
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
#define IS_RDRAM(x) ((unsigned)(x) >= RDRAM_START && \
(unsigned)(x) < RDRAM_END)
#endif
/*************************************************************************
* RDRAM Registers (0x03f0_0000 .. 0x03ff_ffff)
*/
#define RDRAM_BASE_REG 0x03F00000
#define RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00)
#define RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00)
#define RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04)
#define RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08)
#define RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c)
#define RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10)
#define RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14)
#define RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18)
#define RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c)
#define RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20)
#define RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24)
#define RDRAM_0_DEVICE_ID 0
#define RDRAM_1_DEVICE_ID 1
#define RDRAM_RESET_MODE 0
#define RDRAM_ACTIVE_MODE 1
#define RDRAM_STANDBY_MODE 2
#define RDRAM_LENGTH (2*512*2048)
#define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)
#define RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH)
#define RDRAM_0_CONFIG 0x00000
#define RDRAM_1_CONFIG 0x00400
#define RDRAM_GLOBAL_CONFIG 0x80000
/*************************************************************************
* PIF Physical memory map (total size = 2 KB)
*
* Size Description Mode
* 1FC007FF +-------+-----------------+-----+
* | 64 B | JoyChannel RAM | R/W |
* 1FC007C0 +-------+-----------------+-----+
* |1984 B | Boot ROM | * | * = Reserved
* 1FC00000 +-------+-----------------+-----+
*
*/
#define PIF_ROM_START 0x1FC00000
#define PIF_ROM_END 0x1FC007BF
#define PIF_RAM_START 0x1FC007C0
#define PIF_RAM_END 0x1FC007FF
/*************************************************************************
* Controller channel
* Each game controller channel has 4 error bits that are defined in bit 6-7 of
* the Rx and Tx data size area bytes. Programmers need to clear these bits
* when setting the Tx/Rx size area values for a channel
*/
#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
/*************************************************************************
* External device info
*/
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
#define DEVICE_TYPE_SRAM 3 /* SRAM */
/*************************************************************************
* SP Memory
*/
#define SP_DMEM_START 0x04000000 /* read/write */
#define SP_DMEM_END 0x04000FFF
#define SP_IMEM_START 0x04001000 /* read/write */
#define SP_IMEM_END 0x04001FFF
/*************************************************************************
* SP CP0 Registers
*/
#define SP_BASE_REG 0x04040000
/* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */
#define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */
/* SP DRAM DMA address (R/W): [23:0] RDRAM address */
#define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */
/* SP read DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
/* direction: I/DMEM <- RDRAM */
#define SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */
/* SP write DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
/* direction: I/DMEM -> RDRAM */
#define SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */
/* SP status (R/W): [14:0] valid bits; see below for write/read mode */
#define SP_STATUS_REG (SP_BASE_REG+0x10)
/* SP DMA full (R): [0] valid bit; dma full */
#define SP_DMA_FULL_REG (SP_BASE_REG+0x14)
/* SP DMA busy (R): [0] valid bit; dma busy */
#define SP_DMA_BUSY_REG (SP_BASE_REG+0x18)
/* SP semaphore (R/W): Read: [0] semaphore flag (set on read) */
/* Write: [] clear semaphore flag */
#define SP_SEMAPHORE_REG (SP_BASE_REG+0x1C)
/* SP PC (R/W): [11:0] program counter */
#define SP_PC_REG 0x04080000
/* SP MEM address: bit 12 specifies if address is IMEM or DMEM */
#define SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */
#define SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */
/*
* Values to clear/set bit in status reg (SP_STATUS_REG - write)
*/
#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
/*
* Patterns to interpret status reg (SP_STATUS_REG - read)
*/
#define SP_STATUS_HALT 0x001 /* Bit 0: halt */
#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
/*
* Use of SIG bits
*/
#define SP_CLR_YIELD SP_CLR_SIG0
#define SP_SET_YIELD SP_SET_SIG0
#define SP_STATUS_YIELD SP_STATUS_SIG0
#define SP_CLR_YIELDED SP_CLR_SIG1
#define SP_SET_YIELDED SP_SET_SIG1
#define SP_STATUS_YIELDED SP_STATUS_SIG1
#define SP_CLR_TASKDONE SP_CLR_SIG2
#define SP_SET_TASKDONE SP_SET_SIG2
#define SP_STATUS_TASKDONE SP_STATUS_SIG2
#define SP_CLR_RSPSIGNAL SP_CLR_SIG3
#define SP_SET_RSPSIGNAL SP_SET_SIG3
#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
#define SP_CLR_CPUSIGNAL SP_CLR_SIG4
#define SP_SET_CPUSIGNAL SP_SET_SIG4
#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
/* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
#define SP_IBIST_REG 0x04080004
/*
* Patterns to interpret status reg (SP_BIST_REG - write)
*/
#define SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */
#define SP_IBIST_GO 0x02 /* Bit 1: BIST go */
#define SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */
/*
* Patterns to interpret status reg (SP_BIST_REG - read)
*/
/* First 2 bits are same as in write mode:
* Bit 0: BIST check; Bit 1: BIST go
*/
#define SP_IBIST_DONE 0x04 /* Bit 2: BIST done */
#define SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */
/*************************************************************************
* DP Command Registers
*/
#define DPC_BASE_REG 0x04100000
/* DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address */
#define DPC_START_REG (DPC_BASE_REG+0x00)
/* DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address */
#define DPC_END_REG (DPC_BASE_REG+0x04)
/* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
/* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
#define DPC_STATUS_REG (DPC_BASE_REG+0x0C)
/* DP clock counter (R): [23:0] clock counter */
#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
/* DP buffer busy counter (R): [23:0] clock counter */
#define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)
/* DP pipe busy counter (R): [23:0] clock counter */
#define DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18)
/* DP TMEM load counter (R): [23:0] clock counter */
#define DPC_TMEM_REG (DPC_BASE_REG+0x1C)
/*
* Values to clear/set bit in status reg (DPC_STATUS_REG - write)
*/
#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
/*
* Patterns to interpret status reg (DPC_STATUS_REG - read)
*/
#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
/*#define DPC_STATUS_FROZEN 0x008*/ /* Bit 3: frozen */
#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
/*************************************************************************
* DP Span Registers
*/
#define DPS_BASE_REG 0x04200000
/* DP tmem bist (R/W): [10:0] BIST status bits; see below for detail */
#define DPS_TBIST_REG (DPS_BASE_REG+0x00)
/* DP span test mode (R/W): [0] Span buffer test access enable */
#define DPS_TEST_MODE_REG (DPS_BASE_REG+0x04)
/* DP span buffer test address (R/W): [6:0] bits; see below for detail */
#define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08)
/* DP span buffer test data (R/W): [31:0] span buffer data */
#define DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C)
/*
* Patterns to interpret status reg (DPS_TMEM_BIST_REG - write)
*/
#define DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */
#define DPS_TBIST_GO 0x02 /* Bit 1: BIST go */
#define DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */
/*
* Patterns to interpret status reg (DPS_TMEM_BIST_REG - read)
*/
/* First 2 bits are same as in write mode:
* Bit 0: BIST check; Bit 1: BIST go
*/
#define DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */
#define DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */
/*************************************************************************
* MIPS Interface (MI) Registers
*/
#define MI_BASE_REG 0x04300000
/*
* MI init mode (W): [6:0] init length, [7] clear init mode, [8] set init mode
* [9/10] clear/set ebus test mode, [11] clear DP interrupt
* (R): [6:0] init length, [7] init mode, [8] ebus test mode
*/
#define MI_INIT_MODE_REG (MI_BASE_REG+0x00)
#define MI_MODE_REG MI_INIT_MODE_REG
/*
* Values to clear/set bit in mode reg (MI_MODE_REG - write)
*/
#define MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */
#define MI_SET_INIT 0x0100 /* Bit 8: set init mode */
#define MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */
#define MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */
#define MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */
#define MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */
#define MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */
/*
* Patterns to interpret mode reg (MI_MODE_REG - read)
*/
#define MI_MODE_INIT 0x0080 /* Bit 7: init mode */
#define MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */
#define MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */
/* MI version (R): [7:0] io, [15:8] rac, [23:16] rdp, [31:24] rsp */
#define MI_VERSION_REG (MI_BASE_REG+0x04)
#define MI_NOOP_REG MI_VERSION_REG
/* MI interrupt (R): [5:0] valid bits - see below for bit patterns */
#define MI_INTR_REG (MI_BASE_REG+0x08)
/*
* MI interrupt mask (W): [11:0] valid bits - see below for bit patterns
* (R): [5:0] valid bits - see below for bit patterns
*/
#define MI_INTR_MASK_REG (MI_BASE_REG+0x0C)
/*
* The following are values to check for interrupt setting (MI_INTR_REG)
*/
#define MI_INTR_SP 0x01 /* Bit 0: SP intr */
#define MI_INTR_SI 0x02 /* Bit 1: SI intr */
#define MI_INTR_AI 0x04 /* Bit 2: AI intr */
#define MI_INTR_VI 0x08 /* Bit 3: VI intr */
#define MI_INTR_PI 0x10 /* Bit 4: PI intr */
#define MI_INTR_DP 0x20 /* Bit 5: DP intr */
/*
* The following are values to clear/set various interrupt bit mask
* They can be ORed together to manipulate multiple bits
* (MI_INTR_MASK_REG - write)
*/
#define MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */
#define MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */
#define MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */
#define MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */
#define MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */
#define MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */
#define MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */
#define MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */
#define MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */
#define MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */
#define MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */
#define MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */
/*
* The following are values to check for interrupt mask setting
* (MI_INTR_MASK_REG - read)
*/
#define MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */
#define MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */
#define MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */
#define MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */
#define MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */
#define MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */
/*************************************************************************
* Video Interface (VI) Registers
*/
#define VI_BASE_REG 0x04400000
/* VI status/control (R/W): [15-0] valid bits:
* [1:0] = type[1:0] (pixel size)
* 0: blank (no data, no sync)
* 1: reserved
* 2: 5/5/5/3 ("16" bit)
* 3: 8/8/8/8 (32 bit)
* [2] = gamma_dither_enable (normally on, unless "special effect")
* [3] = gamma_enable (normally on, unless MPEG/JPEG)
* [4] = divot_enable (normally on if antialiased, unless decal lines)
* [5] = reserved - always off
* [6] = serrate (always on if interlaced, off if not)
* [7] = reserved - diagnostics only
* [9:8] = anti-alias (aa) mode[1:0]
* 0: aa & resamp (always fetch extra lines)
* 1: aa & resamp (fetch extra lines if needed)
* 2: resamp only (treat as all fully covered)
* 3: neither (replicate pixels, no interpolate)
* [11] = reserved - diagnostics only
* [15:12] = reserved
*
*/
#define VI_STATUS_REG (VI_BASE_REG+0x00)
#define VI_CONTROL_REG VI_STATUS_REG
/* VI origin (R/W): [23:0] frame buffer origin in bytes */
#define VI_ORIGIN_REG (VI_BASE_REG+0x04)
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
/* VI width (R/W): [11:0] frame buffer line width in pixels */
#define VI_WIDTH_REG (VI_BASE_REG+0x08)
#define VI_H_WIDTH_REG VI_WIDTH_REG
/* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
#define VI_INTR_REG (VI_BASE_REG+0x0C)
#define VI_V_INTR_REG VI_INTR_REG
/*
* VI current vertical line (R/W): [9:0] current half line, sampled once per
* line (the lsb of V_CURRENT is constant within a field, and in
* interlaced modes gives the field number - which is constant for non-
* interlaced modes)
* - Any write to this register will clear interrupt line
*/
#define VI_CURRENT_REG (VI_BASE_REG+0x10)
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
/*
* VI video timing (R/W): [ 7: 0] horizontal sync width in pixels,
* [15: 8] color burst width in pixels,
* [19:16] vertical sync width in half lines,
* [29:20] start of color burst in pixels from h-sync
*/
#define VI_BURST_REG (VI_BASE_REG+0x14)
#define VI_TIMING_REG VI_BURST_REG
/* VI vertical sync (R/W): [9:0] number of half-lines per field */
#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
/* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel
* [20:16] a 5-bit leap pattern used for PAL only
* (h_sync_period)
*/
#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
/*
* VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period
* [27:16] identical to h_sync_period
*/
#define VI_LEAP_REG (VI_BASE_REG+0x20)
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
/*
* VI horizontal video (R/W): [ 9: 0] end of active video in screen pixels
* : [25:16] start of active video in screen pixels
*/
#define VI_H_START_REG (VI_BASE_REG+0x24)
#define VI_H_VIDEO_REG VI_H_START_REG
/*
* VI vertical video (R/W): [ 9: 0] end of active video in screen half-lines
* : [25:16] start of active video in screen half-lines
*/
#define VI_V_START_REG (VI_BASE_REG+0x28)
#define VI_V_VIDEO_REG VI_V_START_REG
/*
* VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines
* : [25:16] start of color burst enable in half-lines
*/
#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
/* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format)
* [27:16] horizontal subpixel offset (2.10 format)
*/
#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
/* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format)
* [27:16] vertical subpixel offset (2.10 format)
*/
#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
/*
* Patterns to interpret VI_CONTROL_REG
*/
#define VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */
#define VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */
#define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */
#define VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */
#define VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */
#define VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */
#define VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */
#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */
/*
* Possible video clocks (NTSC or PAL)
*/
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
/*************************************************************************
* Audio Interface (AI) Registers
*
* The address and length registers are double buffered; that is, they
* can be written twice before becoming full.
* The address must be written before the length.
*/
#define AI_BASE_REG 0x04500000
/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
#define AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */
/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
/* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
#define AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */
/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
#define AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */
/*
* AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
* Note that a 1->0 transition in ai_full will set interrupt
* (W): clear audio interrupt
*/
#define AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */
/*
* AI DAC sample period register (W): [13:0] dac rate
* - vid_clock/(dperiod + 1) is the DAC sample rate
* - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
*/
#define AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/
/*
* AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
* - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
* - The abus clock stops if aclockhp is zero
*/
#define AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */
/* Value for control register */
#define AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/
#define AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/
/* Value for status register */
#define AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */
#define AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */
/* DAC rate = video clock / audio frequency
* - DAC rate >= (66 * Bit rate) must be true
*/
#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
#define AI_MIN_DAC_RATE 132
/* Bit rate <= (DAC rate / 66) */
#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
#define AI_MIN_BIT_RATE 2
/*
* Maximum and minimum values for audio frequency based on video clocks
* max frequency = (video clock / min dac rate)
* min frequency = (video clock / max dac rate)
*/
#define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */
#define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */
#define AI_PAL_MAX_FREQ 376000 /* 376 KHz */
#define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */
#define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */
#define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */
/*************************************************************************
* Peripheral Interface (PI) Registers
*/
#define PI_BASE_REG 0x04600000
/* PI DRAM address (R/W): [23:0] starting RDRAM address */
#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
/* PI pbus (cartridge) address (R/W): [31:0] starting AD16 address */
#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
/* PI read length (R/W): [23:0] read data length */
#define PI_RD_LEN_REG (PI_BASE_REG+0x08)
/* PI write length (R/W): [23:0] write data length */
#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
/*
* PI status (R): [0] DMA busy, [1] IO busy, [2], error
* (W): [0] reset controller (and abort current op), [1] clear intr
*/
#define PI_STATUS_REG (PI_BASE_REG+0x10)
/* PI dom1 latency (R/W): [7:0] domain 1 device latency */
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
#define PI_DOM_LAT_OFS 0x00
#define PI_DOM_PWD_OFS 0x04
#define PI_DOM_PGS_OFS 0x08
#define PI_DOM_RLS_OFS 0x0C
/*
* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
* Bit 0: DMA busy - set when DMA is in progress
* Bit 1: IO busy - set when IO is in progress
* Bit 2: Error - set when CPU issues IO request while DMA is busy
*/
#define PI_STATUS_ERROR 0x04
#define PI_STATUS_IO_BUSY 0x02
#define PI_STATUS_DMA_BUSY 0x01
/* PI status register has 2 bits active when written to:
* Bit 0: When set, reset PIC
* Bit 1: When set, clear interrupt flag
* The values of the two bits can be ORed together to both reset PIC and
* clear interrupt at the same time.
*
* Note:
* - The PIC does generate an interrupt at the end of each DMA. CPU
* needs to clear the interrupt flag explicitly (from an interrupt
* handler) by writing into the STATUS register with bit 1 set.
*
* - When a DMA completes, the interrupt flag is set. CPU can issue
* another request even while the interrupt flag is set (as long as
* PIC is idle). However, it is the CPU's responsibility for
* maintaining accurate correspondence between DMA completions and
* interrupts.
*
* - When PIC is reset, if PIC happens to be busy, an interrupt will
* be generated as PIC returns to idle. Otherwise, no interrupt will
* be generated and PIC remains idle.
*/
/*
* Values to clear interrupt/reset PIC (PI_STATUS_REG - write)
*/
#define PI_STATUS_RESET 0x01
#define PI_SET_RESET PI_STATUS_RESET
#define PI_STATUS_CLR_INTR 0x02
#define PI_CLR_INTR PI_STATUS_CLR_INTR
#define PI_DMA_BUFFER_SIZE 128
#define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */
#define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */
#define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */
#define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */
#define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */
/*************************************************************************
* RDRAM Interface (RI) Registers
*/
#define RI_BASE_REG 0x04700000
/* RI mode (R/W): [1:0] operating mode, [2] stop T active, [3] stop R active */
#define RI_MODE_REG (RI_BASE_REG+0x00)
/* RI config (R/W): [5:0] current control input, [6] current control enable */
#define RI_CONFIG_REG (RI_BASE_REG+0x04)
/* RI current load (W): [] any write updates current control register */
#define RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08)
/* RI select (R/W): [2:0] receive select, [2:0] transmit select */
#define RI_SELECT_REG (RI_BASE_REG+0x0C)
/* RI refresh (R/W): [7:0] clean refresh delay, [15:8] dirty refresh delay,
* [16] refresh bank, [17] refresh enable
* [18] refresh optimize
*/
#define RI_REFRESH_REG (RI_BASE_REG+0x10)
#define RI_COUNT_REG RI_REFRESH_REG
/* RI latency (R/W): [3:0] DMA latency/overlap */
#define RI_LATENCY_REG (RI_BASE_REG+0x14)
/* RI error (R): [0] nack error, [1] ack error */
#define RI_RERROR_REG (RI_BASE_REG+0x18)
/* RI error (W): [] any write clears all error bits */
#define RI_WERROR_REG (RI_BASE_REG+0x1C)
/*************************************************************************
* Serial Interface (SI) Registers
*/
#define SI_BASE_REG 0x04800000
/* SI DRAM address (R/W): [23:0] starting RDRAM address */
#define SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */
/* SI address read 64B (W): [] any write causes a 64B DMA write */
#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */
/* Address SI_BASE_REG + (0x08, 0x0c, 0x14) are reserved */
/* SI address write 64B (W): [] any write causes a 64B DMA read */
#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */
/*
* SI status (W): [] any write clears interrupt
* (R): [0] DMA busy, [1] IO read busy, [2] reserved
* [3] DMA error, [12] interrupt
*/
#define SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */
/* SI status register has the following bits active:
* 0: DMA busy - set when DMA is in progress
* 1: IO busy - set when IO access is in progress
* 3: DMA error - set when there are overlapping DMA requests
* 12: Interrupt - Interrupt set
*/
#define SI_STATUS_DMA_BUSY 0x0001
#define SI_STATUS_RD_BUSY 0x0002
#define SI_STATUS_DMA_ERROR 0x0008
#define SI_STATUS_INTERRUPT 0x1000
/*************************************************************************
* Development Board GIO Control Registers
*/
#define GIO_BASE_REG 0x18000000
/* Game to Host Interrupt */
#define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)
/* Game to Host SYNC */
#define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)
/* Host to Game Interrupt */
#define GIO_CART_INTR_REG (GIO_BASE_REG+0x800)
/*************************************************************************
* Common macros
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
#define IO_READ(addr) (*(vu32 *)PHYS_TO_K1(addr))
#define IO_WRITE(addr,data) (*(vu32 *)PHYS_TO_K1(addr)=(u32)(data))
#define RCP_STAT_PRINT \
rmonPrintf("current=%x start=%x end=%x dpstat=%x spstat=%x\n", \
IO_READ(DPC_CURRENT_REG), \
IO_READ(DPC_START_REG), \
IO_READ(DPC_END_REG), \
IO_READ(DPC_STATUS_REG), \
IO_READ(SP_STATUS_REG))
#endif
#endif /* _RCP_H_ */
include/ultra64/sptask.h → include/PR/sptask.h
+3 -1
View File
@@ -8,7 +8,6 @@
#define M_HVQTASK 6
#define M_HVQMTASK 7
//gGfxSPTaskYieldBuffer has to be changed for this too
#if (defined(F3DEX_GBI) || defined(F3DLP_GBI) || defined(F3DEX_GBI_2))
#define OS_YIELD_DATA_SIZE 0xc00
#else
@@ -19,6 +18,9 @@
/* Flags */
#define M_TASK_FLAG0 1
#define M_TASK_FLAG1 2
#ifdef VERSION_SH
#define M_TASK_FLAG2 4
#endif
/* SpStatus */
#define SPSTATUS_CLEAR_HALT 0x00000001
include/ultra64/ucode.h → include/PR/ucode.h
+5 -5
View File
@@ -11,13 +11,13 @@ extern u64 rspF3DBootStart[], rspF3DBootEnd[];
// F3D ucode
extern u64 rspF3DStart[], rspF3DEnd[];
// F3D data ucode
// F3D ucode data
extern u64 rspF3DDataStart[], rspF3DDataEnd[];
// F3D audio ucode
extern u64 rspF3DAudioStart[], rspF3DAudioEnd[];
// aspMain (audio) ucode
extern u64 rspAspMainStart[], rspAspMainEnd[];
// F3D audio data ucode
extern u64 rspF3DAudioDataStart[], rspF3DAudioDataEnd[];
// aspMain ucode data
extern u64 rspAspMainDataStart[], rspAspMainDataEnd[];
#endif
include/ultra64/types.h → include/PR/ultratypes.h
+11 -8
View File
@@ -29,13 +29,16 @@ typedef volatile s64 vs64;
typedef float f32;
typedef double f64;
typedef long int Mtx_t[4][4];
typedef union
{
Mtx_t m;
long long int forc_structure_alignment;
} Mtx;
typedef unsigned long size_t;
#ifdef TARGET_N64
typedef u32 size_t;
typedef s32 ssize_t;
typedef u32 uintptr_t;
typedef s32 intptr_t;
typedef s32 ptrdiff_t;
#else
#include <stddef.h>
#include <stdint.h>
typedef ptrdiff_t ssize_t;
#endif
#endif
include/platform_info.h
+15
View File
@@ -0,0 +1,15 @@
#ifndef PLATFORM_INFO_H
#define PLATFORM_INFO_H
#ifdef TARGET_N64
#define IS_64_BIT 0
#define IS_BIG_ENDIAN 1
#else
#include <stdint.h>
#define IS_64_BIT (UINTPTR_MAX == 0xFFFFFFFFFFFFFFFFU)
#define IS_BIG_ENDIAN (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
#endif
#define DOUBLE_SIZE_ON_64_BIT(size) ((size) * (sizeof(void *) / 4))
#endif // PLATFORM_INFO_H
include/ultra64.h
+26 -22
View File
@@ -3,27 +3,31 @@
#include <math.h>
#include <ultra64/types.h>
#include <ultra64/interrupt.h>
#include <ultra64/os_misc.h>
#include <ultra64/rdp.h>
#include <ultra64/thread.h>
#include <ultra64/time.h>
#include <ultra64/message.h>
#include <ultra64/os_cont.h>
#include <ultra64/tlb.h>
#include <ultra64/sptask.h>
#include <ultra64/ucode.h>
#include <ultra64/cache.h>
#include <ultra64/vi.h>
#include <ultra64/pi.h>
#include <ultra64/os_internal.h>
#include <ultra64/gbi.h>
#include <ultra64/eeprom.h>
#include <ultra64/libc.h>
#include <ultra64/gu.h>
#include <ultra64/os_ai.h>
#include <ultra64/libaudio.h>
#include <ultra64/libultra.h>
#ifndef _LANGUAGE_C
#define _LANGUAGE_C
#endif
#include <PR/ultratypes.h>
#include <PR/os_exception.h>
#include <PR/os_misc.h>
#include <PR/os_rdp.h>
#include <PR/os_thread.h>
#include <PR/os_time.h>
#include <PR/os_message.h>
#include <PR/os_cont.h>
#include <PR/os_tlb.h>
#include <PR/sptask.h>
#include <PR/ucode.h>
#include <PR/os_cache.h>
#include <PR/os_vi.h>
#include <PR/os_pi.h>
#include <PR/os_internal.h>
#include <PR/mbi.h>
#include <PR/os_eeprom.h>
#include <PR/os_libc.h>
#include <PR/gu.h>
#include <PR/os_ai.h>
#include <PR/libaudio.h>
#include <PR/libultra.h>
#endif
include/ultra64/cache.h
-11
View File
@@ -1,11 +0,0 @@
#ifndef _ULTRA64_CACHE_H_
#define _ULTRA64_CACHE_H_
/* Functions */
void osInvalICache(void *vaddr, s32 nbytes);
void osInvalDCache(void *vaddr, s32 nbytes);
void osWritebackDCache(void *vaddr, s32 nbytes);
void osWritebackDCacheAll(void);
#endif
include/ultra64/eeprom.h
-18
View File
@@ -1,18 +0,0 @@
#ifndef _ULTRA64_EEPROM_H_
#define _ULTRA64_EEPROM_H_
typedef struct
{
u16 unk00;
u16 unk01;
} OSEepromUnknownStruct0;
/* Functions */
s32 osEepromLongRead(OSMesgQueue *mq, u8 address, u8 *buffer, int nbytes);
s32 osEepromLongWrite(OSMesgQueue *mq, u8 address, u8 *buffer, int nbytes);
s32 osEepromWrite(OSMesgQueue *mq, u8 address, u8 *buffer);
s32 osEepromRead(OSMesgQueue *mq, u8 address, u8 *buffer);
s32 osEepromProbe(OSMesgQueue *mq);
#endif
include/ultra64/gbi.h
-736
View File
@@ -1,736 +0,0 @@
#ifndef _ULTRA64_GBI_H_
#define _ULTRA64_GBI_H_
/* Types */
/* Vertex (set up for use with colors) */
typedef struct
{
short ob[3]; /* x, y, z */
unsigned short flag;
short tc[2]; /* texture coord */
unsigned char cn[4]; /* color & alpha */
} Vtx_t;
/* Vertex (set up for use with normals) */
typedef struct
{
short ob[3]; /* x, y, z */
unsigned short flag;
short tc[2]; /* texture coord */
signed char n[3]; /* normal */
unsigned char a; /* alpha */
} Vtx_tn;
typedef union
{
Vtx_t v; /* Use this one for colors */
Vtx_tn n; /* Use this one for normals */
long long int force_structure_alignment;
} Vtx;
typedef struct
{
short vscale[4]; /* scale, 2 bits fraction */
short vtrans[4]; /* translate, 2 bits fraction */
} Vp_t;
typedef union
{
Vp_t vp;
long long int force_structure_alignment;
} Vp;
typedef struct
{
unsigned int w0;
unsigned int w1;
} Gwords;
/* TODO: fill in the rest of the members */
typedef union
{
Gwords words;
long long int force_structure_alignment;
} Gfx;
#define _SHIFTL(value, shift, size) \
((unsigned int) (((unsigned int) (value) & ((1 << size) - 1)) << shift))
#define G_ON 1
#define G_OFF 0
#define GPACK_RGBA5551(r, g, b, a) \
((((r) << 8) & 0xF800) | \
(((g) << 3) & 0x07C0) | \
(((b) >> 2) & 0x003E) | \
((a) & 0x0001))
#define GPACK_ZDZ(z, dz) ((z) << 2 | (dz))
#define G_ZBUFFER 0x00000001
#define G_TEXTURE_ENABLE 0x00000002
#define G_SHADE 0x00000004
#define G_SHADING_SMOOTH 0x00000200
#define G_CULL_FRONT 0x00001000
#define G_CULL_BACK 0x00002000
#define G_CULL_BOTH 0x00003000
#define G_FOG 0x00010000
#define G_LIGHTING 0x00020000
#define G_TEXTURE_GEN 0x00040000
#define G_TEXTURE_GEN_LINEAR 0x00080000
#define G_LOD 0x00100000
#define G_CLIPPING 0x00800000
#define G_IM_FMT_RGBA 0
#define G_IM_FMT_YUV 1
#define G_IM_FMT_CI 2
#define G_IM_FMT_IA 3
#define G_IM_FMT_I 4
#define G_IM_SIZ_4b 0
#define G_IM_SIZ_8b 1
#define G_IM_SIZ_16b 2
#define G_IM_SIZ_32b 3
#define G_IM_SIZ_DD 5
#define G_AC_NONE (0 << 0)
#define G_AC_THRESHOLD (1 << 0)
#define G_AC_DITHER (3 << 0)
#define G_ZS_PIXEL (0 << 2)
#define G_ZS_PRIM (1 << 2)
#define G_CD_MAGICSQ (0 << 6)
#define G_CD_BAYER (1 << 6)
#define G_CD_NOISE (2 << 6)
#define G_CK_NONE (0 << 8)
#define G_CK_KEY (1 << 8)
#define G_TC_CONV (0 << 9)
#define G_TC_FILTCONV (5 << 9)
#define G_TC_FILT (6 << 9)
#define G_TF_POINT (0 << 12)
#define G_TF_BILERP (2 << 12)
#define G_TF_AVERAGE (3 << 12)
#define G_TT_NONE (0 << 14)
#define G_TT_RGBA16 (2 << 14)
#define G_TT_IA16 (3 << 14)
#define G_TL_TILE (0 << 16)
#define G_TL_LOD (1 << 16)
#define G_TD_CLAMP (0 << 17)
#define G_TD_SHARPEN (1 << 17)
#define G_TD_DETAIL (2 << 17)
#define G_TP_NONE (0 << 19)
#define G_TP_PERSP (1 << 19)
#define G_CYC_1CYCLE (0 << 20)
#define G_CYC_2CYCLE (1 << 20)
#define G_CYC_COPY (2 << 20)
#define G_CYC_FILL (3 << 20)
#define G_PM_NPRIMITIVE (0 << 23)
#define G_PM_1PRIMITIVE (1 << 23)
#define G_SC_NON_INTERLACE 0
#define G_SC_ODD_INTERLACE 3
#define G_SC_EVEN_INTERLACE 2
#define G_TX_LOADTILE 7
#define G_TX_RENDERTILE 0
#define G_TX_NOMIRROR 0
#define G_TX_WRAP 0
#define G_TX_MIRROR 1
#define G_TX_CLAMP 2
#define G_TX_NOMASK 0
#define G_TX_NOLOD 0
#define G_TX_LDBLK_MAX_TXL 2047
#define G_MV_VIEWPORT 0x80
#define G_MV_LOOKATY 0x82
#define G_MV_LOOKATX 0x84
#define G_MV_L0 0x86
#define G_MV_L1 0x88
#define G_MV_L2 0x8A
#define G_MV_L3 0x8C
#define G_MV_L4 0x8E
#define G_MV_L5 0x90
#define G_MV_L6 0x92
#define G_MV_L7 0x94
#define G_MV_TXTATT 0x96
#define G_MV_MATRIX_1 0x9E
#define G_MV_MATRIX_2 0x98
#define G_MV_MATRIX_3 0x9A
#define G_MV_MATRIX_4 0x9C
#define G_SETOTHERMODE_L 0xB9
#define G_SETOTHERMODE_H 0xBA
#ifndef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
#ifndef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#define gSPMatrix(pkt, m, p) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0x01, 24, 8) \
| _SHIFTL((p), 16, 8) \
| _SHIFTL(sizeof(Mtx), 0, 16); \
_g->words.w1 = (u32)(m); \
}
#define gSPVertex(pkt, v, n, v0) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0x04, 24, 8) \
| _SHIFTL(((n)-1) << 4 | (v0), 16, 8) \
| _SHIFTL(sizeof(Vtx)*(n), 0, 16); \
_g->words.w1 = (u32)(v); \
}
#define gDPLoadSync(pkt) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xE6000000; \
_g->words.w1 = 0x00000000; \
}
#define gDPPipeSync(pkt) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xE7000000; \
_g->words.w1 = 0x00000000; \
}
#define gDPTileSync(pkt) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xE8000000; \
_g->words.w1 = 0x00000000; \
}
#define gDPFullSync(pkt) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xE9000000; \
_g->words.w1 = 0x00000000; \
}
#define gSPDisplayList(pkt, dl) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0x06000000; \
_g->words.w1 = (u32)(dl); \
}
#define gSPBranchList(pkt, dl) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = 0x06010000; \
_g->words.w1 = (u32)(dl); \
}
#define gSPEndDisplayList(pkt) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xB8000000; \
_g->words.w1 = 0x00000000; \
}
#define gDPSetCycleType(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA001402; \
_g->words.w1 = type; \
}
#define gDPPipelineMode(pkt, mode) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA001701; \
_g->words.w1 = mode; \
}
#define gDPSetScissor(pkt, mode, ulx, uly, lrx, lry) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xED, 24, 8) \
| _SHIFTL((int)((float)(ulx)*4.0f), 12, 12) \
| _SHIFTL((int)((float)(uly)*4.0f), 0, 12); \
_g->words.w1 = _SHIFTL((mode), 24, 8) \
| _SHIFTL((int)((float)(lrx)*4.0f), 12, 12) \
| _SHIFTL((int)((float)(lry)*4.0f), 0, 12); \
}
#define gDPSetCombine(pkt, muxs0, muxs1) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xFC, 24, 8) \
| _SHIFTL((muxs0), 0, 24); \
_g->words.w1 = (muxs1); \
}
#define gDPSetTextureLOD(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA001001; \
_g->words.w1 = type; \
}
#define gDPSetTextureLUT(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA000E02; \
_g->words.w1 = type; \
}
#define gDPSetTextureDetail(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA001102; \
_g->words.w1 = type; \
}
#define gDPSetTexturePersp(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA001301; \
_g->words.w1 = type; \
}
#define gDPSetTextureFilter(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA000C02; \
_g->words.w1 = type; \
}
#define gDPSetTextureConvert(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA000903; \
_g->words.w1 = type; \
}
#define gDPSetCombineKey(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA000801; \
_g->words.w1 = type; \
}
#define gDPSetColorDither(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBA000602; \
_g->words.w1 = type; \
}
#define gDPSetFillColor(pkt, color) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xF7000000; \
_g->words.w1 = color; \
}
#define gDPFillRectangle(pkt, ulx, uly, lrx, lry) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xF6, 24, 8) \
| _SHIFTL((lrx), 14, 10) \
| _SHIFTL((lry), 2, 10); \
_g->words.w1 = _SHIFTL(0, 24, 8) \
| _SHIFTL((ulx), 14, 10) \
| _SHIFTL((uly), 2, 10); \
}
#define gDPSetAlphaCompare(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xB9000002; \
_g->words.w1 = type; \
}
#define gDPSetDepthSource(pkt, type) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xB9000201; \
_g->words.w1 = type; \
}
#define gSPSetOtherMode(pkt, cmd, shift, length, data) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = _SHIFTL((cmd), 24, 8) \
| _SHIFTL((shift), 8, 8) \
| _SHIFTL(((length)-1), 0, 8); \
_g->words.w1 = (data); \
}
#define gDPSetRenderMode(pkt, mode1, mode2) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xB900031D; \
_g->words.w1 = (mode1) | (mode2); \
}
#define gSPClearGeometryMode(pkt, mode) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xB6000000; \
_g->words.w1 = mode; \
}
#define gSPSetGeometryMode(pkt, word) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xB7000000; \
_g->words.w1 = word; \
}
#define gSPNumLights(pkt, n) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBC000002; \
_g->words.w1 = (0x80000000 + ((n) + 1) * 0x20); \
}
#define gSPTexture(pkt, sc, tc, level, tile, on) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xBB, 24, 8) \
| _SHIFTL(0, 16, 8) \
| _SHIFTL((level), 11, 3) \
| _SHIFTL((tile), 8, 3) \
| _SHIFTL((on), 0, 8); \
_g->words.w1 = _SHIFTL((sc), 16, 16) \
| _SHIFTL((tc), 0, 16); \
}
#define gDPSetColorImage(pkt, fmt, size, width, image) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xFF, 24, 8) \
| _SHIFTL((fmt), 21, 3) \
| _SHIFTL((size), 19, 2) \
| _SHIFTL((width)-1, 0, 12); \
_g->words.w1 = (image); \
}
#define gDPSetTileSize(pkt, tile, uls, ult, lrs, lrt) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xF2, 24, 8) \
| _SHIFTL(uls, 12, 12) \
| _SHIFTL(ult, 0, 12); \
_g->words.w1 = _SHIFTL(tile, 24, 3) \
| _SHIFTL(lrs, 12, 12) \
| _SHIFTL(lrt, 0, 12); \
}
#define gDPLoadBlock(pkt, tile, uls, ult, lrs, dxt) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xF3, 24, 8) \
| _SHIFTL((uls), 12, 12) \
| _SHIFTL((ult), 0, 12); \
_g->words.w1 = _SHIFTL((tile), 24, 3) \
| _SHIFTL((MIN((lrs),G_TX_LDBLK_MAX_TXL)), 12, 12) \
| _SHIFTL((dxt), 0, 12); \
}
#define gDPSetTile(pkt, fmt, siz, line, tmem, tile, \
palette, cmt, maskt, shiftt, cms, masks, shifts) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xF5, 24, 8) \
| _SHIFTL((fmt), 21, 3) \
| _SHIFTL((siz), 19, 2) \
| _SHIFTL((line), 9, 9) \
| _SHIFTL((tmem), 0, 9); \
_g->words.w1 = _SHIFTL((tile), 24, 3) \
| _SHIFTL((palette), 20, 4) \
| _SHIFTL((cmt), 18, 2) \
| _SHIFTL((maskt), 14, 4) \
| _SHIFTL((shiftt), 10, 4) \
| _SHIFTL((cms), 8, 2) \
| _SHIFTL((masks), 4, 4) \
| _SHIFTL((shifts), 0, 4); \
}
#define gDPSetDepthImage(pkt, image) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xFE, 24, 8); \
_g->words.w1 = (image); \
}
#define G_SETPRIMCOLOR 0xFA
#define gDPSetPrimColor(pkt, m, l, r, g, b, a) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(G_SETPRIMCOLOR, 24, 8) \
| _SHIFTL(m, 8, 8) \
| _SHIFTL(l, 0, 8); \
_g->words.w1 = _SHIFTL(r, 24, 8) \
| _SHIFTL(g, 16, 8) \
| _SHIFTL(b, 8, 8) \
| _SHIFTL(a, 0, 8); \
}
#define gDPSetEnvColor(pkt, r, g, b, a) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xFB, 24, 8); \
_g->words.w1 = _SHIFTL((r), 24, 8) \
| _SHIFTL((g), 16, 8) \
| _SHIFTL((b), 8, 8) \
| _SHIFTL((a), 0, 8); \
}
#define gDPSetTextureImage(pkt, fmt, size, width, img) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xFD, 24, 8) \
| _SHIFTL((fmt), 21, 3) \
| _SHIFTL((size), 19, 2) \
| _SHIFTL((width)-1, 0, 12); \
_g->words.w1 = (u32)(img); \
}
#define gMoveWd(pkt, index, offset, data) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xBC, 24, 8) \
| _SHIFTL((offset), 8, 16) \
| _SHIFTL((index), 0, 8); \
_g->words.w1 = (u32)(data); \
}
/* Matrix Operations */
#define G_MTX_MODELVIEW 0x00
#define G_MTX_PROJECTION 0x01
#define G_MTX_MUL 0x00
#define G_MTX_LOAD 0x02
#define G_MTX_NOPUSH 0x00
#define G_MTX_PUSH 0x04
#define gSPPopMatrix(pkt, n) \
{ \
Gfx *_g = (Gfx *) (pkt); \
_g->words.w0 = 0xBD000000; \
_g->words.w1 = (n); \
}
#define gSPViewport(pkt, v) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0x03, 24, 8) \
| _SHIFTL(G_MV_VIEWPORT, 16, 8) \
| _SHIFTL(sizeof(Vp), 0, 16); \
_g->words.w1 = (u32)(v); \
}
#define gSP1Triangle(pkt, v0, v1, v2, flag) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xBF, 24, 8); \
_g->words.w1 = _SHIFTL((flag), 24, 8) \
| _SHIFTL((v0)*10, 16, 8) \
| _SHIFTL((v1)*10, 8, 8) \
| _SHIFTL((v2)*10, 0, 8); \
}
#if (defined(F3DLP_GBI)||defined(F3DEX_GBI))
/***
*** 2 Triangles
***/
#define gSP2Triangles(pkt, v00, v01, v02, flag0, v10, v11, v12, flag1) \
{ \
Gfx *_g = (Gfx *)(pkt); \
\
_g->words.w0 = (_SHIFTL(G_TRI2, 24, 8)| \
__gsSP1Triangle_w1f(v00, v01, v02, flag0)); \
_g->words.w1 = __gsSP1Triangle_w1f(v10, v11, v12, flag1); \
}
#define gsSP2Triangles(v00, v01, v02, flag0, v10, v11, v12, flag1) \
{ \
(_SHIFTL(G_TRI2, 24, 8)| \
__gsSP1Triangle_w1f(v00, v01, v02, flag0)), \
__gsSP1Triangle_w1f(v10, v11, v12, flag1) \
}
#endif /* F3DEX_GBI/F3DLP_GBI */
#if (defined(TRI4_Ext))
/***
*** 4 Triangles - 2Tri Extension
*** Draws up to four triangles at a time.
*** Expects values from 0-F, corresponding with # points declared by vertex command.
*** Triangles with all points set to 0 are not drawn.
*** Vertex Buffer reduced to 16 due to only being able to address 0-F
***/
#define gSP4Triangles(pkt, v00, v01, v02, v10, v11, v12, \
v20, v21, v22, v30, v31, v32 ) \
{ \
Gfx *_g = (Gfx *)(pkt); \
\
_g->words.w0 = (_SHIFTL(G_TRI2, 24, 8)| \
_SHIFTL((v32),12,4)|_SHIFTL((v22),8,4)|_SHIFTL((v12),4,4)|_SHIFTL((v02),0,4); \
_g->words.w1 = _SHIFTL((v31),28,4)|_SHIFTL((v30),24,4)|_SHIFTL((v21),20,4)|_SHIFTL((v20),16,4) \
_SHIFTL((v11),12,4)|_SHIFTL((v10),8,4)|_SHIFTL((v02),4,4)|_SHIFTL((v00),0,4); \
}
#define gsSP4Triangles(v00, v01, v02, flag0, v10, v11, v12, flag1) \
{ \
(_SHIFTL(G_TRI2, 24, 8)| \
_SHIFTL((v32),12,4)|_SHIFTL((v22),8,4)|_SHIFTL((v12),4,4)|_SHIFTL((v02),0,4)), \
(_SHIFTL((v31),28,4)|_SHIFTL((v30),24,4)|_SHIFTL((v21),20,4)|_SHIFTL((v20),16,4) \
_SHIFTL((v11),12,4)|_SHIFTL((v10),8,4)|_SHIFTL((v02),4,4)|_SHIFTL((v00),0,4)); \
}
#endif /* TRI4_Ext*/
#define gSPTextureRectangle(pkt, xl, yl, xh, yh, tile, s, t, dsdx, dtdy) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xE4, 24, 8) \
| _SHIFTL((xh), 12, 12) \
| _SHIFTL((yh), 0, 12); \
_g->words.w1 = _SHIFTL((tile), 24, 3) \
| _SHIFTL((xl), 12, 12) \
| _SHIFTL((yl), 0, 12); \
} \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xB3, 24, 8); \
_g->words.w1 = _SHIFTL((s), 16, 16) \
| _SHIFTL((t), 0, 16); \
} \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(0xB2, 24, 8); \
_g->words.w1 = _SHIFTL((dsdx), 16, 16) \
| _SHIFTL((dtdy), 0, 16); \
}
/* Lights and Light Operations */
typedef struct {
unsigned char col[3];
char pad1;
unsigned char colc[3];
char pad2;
signed char dir[3];
char pad3;
} Light_t;
typedef struct {
unsigned char col[3];
char pad1;
unsigned char colc[3];
char pad2;
} Ambient_t;
typedef union {
Ambient_t l;
long long int force_structure_alignment[1];
} Ambient;
typedef union {
Light_t l;
long long int force_structure_alignment[2];
} Light;
typedef struct {
Ambient a;
Light l[4];
} Lights4;
typedef struct {
Light l[2];
} LookAt;
typedef struct {
int x1, y1, x2, y2;
} Hilite_t;
typedef union {
Hilite_t h;
long int force_alignmnet[4];
} Hilite;
#define G_MOVEMEM 0x03
/* for gSPNumLights */
// is NUMLIGHTS_0 accurate?
#define NUMLIGHTS_0 1
#define NUMLIGHTS_1 1
#define NUMLIGHTS_2 2
#define NUMLIGHTS_3 3
#define NUMLIGHTS_4 4
#define NUMLIGHTS_5 5
#define NUMLIGHTS_6 6
#define NUMLIGHTS_7 7
/* for gSPLight */
#define LIGHT_1 1
#define LIGHT_2 2
#define LIGHT_3 3
#define LIGHT_4 4
#define LIGHT_5 5
#define LIGHT_6 6
#define LIGHT_7 7
#define LIGHT_8 8
#define gSPLight(pkt, l, n) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(G_MOVEMEM, 24, 8) \
| _SHIFTL(((n)-1)*2+G_MV_L0, 16, 8) \
| _SHIFTL(sizeof(Light), 0, 16); \
_g->words.w1 = (u32)(l); \
}
#define gSPLookAtX(pkt, la) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(G_MOVEMEM, 24, 8) \
| _SHIFTL(G_MV_LOOKATX, 16, 8) \
| _SHIFTL(sizeof(Light), 0, 16); \
_g->words.w1 = (u32)(la); \
}
#define gSPLookAtY(pkt, la) \
{ \
Gfx *_g = (Gfx *)(pkt); \
_g->words.w0 = _SHIFTL(G_MOVEMEM, 24, 8) \
| _SHIFTL(G_MV_LOOKATY, 16, 8) \
| _SHIFTL(sizeof(Light), 0, 16); \
_g->words.w1 = (u32)(la); \
}
#define gSPLookAt(pkt, la) \
{ \
gSPLookAtX((pkt), (la)) \
gSPLookAtY((pkt), (char *)(la)+16) \
}
#endif
include/ultra64/gbi.inc
-332
View File
@@ -1,332 +0,0 @@
/* GNU as assembler macros for F3D GBI */
/* commands with no parameters */
.macro f3d_noparam cmd
.word (\cmd << 24), 0x00000000
.endm
.macro gsImmp1 cmd, param
.word (\cmd << 24), \param
.endm
/* DMA helper */
.macro gsDma1p cmd, segAddr, length, params
.byte \cmd, \params
.hword \length
.word \segAddr
.endm
/* 01: G_MTX */
/* params */
.set G_MTX_MODELVIEW, 0x00
.set G_MTX_PROJECTION, 0x01
.set G_MTX_MUL, 0x00
.set G_MTX_LOAD, 0x02
.set G_MTX_NOPUSH, 0x00
.set G_MTX_PUSH, 0x04
.set G_MTX, 0x01
.macro gsSPMatrix matrix, params
gsDma1p G_MTX, \matrix, 64, \params
.endm
/* 02: reserved */
/* 03: G_MOVEMEM */
.set G_MOVEMEM, 0x03
.set G_MV_L0, 0x86
.macro gsSPLight light, num
gsDma1p G_MOVEMEM, \light, 16, ((\num)-1)*2+G_MV_L0
.endm
/* 04: G_VTX */
.set G_VTX, 0x04
.macro gsSPVertex verts, num, index
gsDma1p G_VTX, \verts, 16*\num, ((\num)-1)<<4|(\index)
.endm
/* 05: reserved */
/* 06: G_DL */
.set G_DL, 0x06
.set G_DL_PUSH, 0x00
.set G_DL_NOPUSH, 0x01
.macro gsSPDisplayList dl
gsDma1p G_DL, \dl, 0, G_DL_PUSH
.endm
.macro gsSPBranchList dl
gsDma1p G_DL, \dl, 0, G_DL_NOPUSH
.endm
/* geometry mode flags */
.set G_ZBUFFER, 0x00000001
.set G_SHADE, 0x00000004
.set G_SHADING_SMOOTH, 0x00000200
.set G_CULL_FRONT, 0x00001000
.set G_CULL_BACK, 0x00002000
.set G_FOG, 0x00010000
.set G_LIGHTING, 0x00020000
.set G_TEXTURE_GEN, 0x00040000
.set G_TEXTURE_GEN_LINEAR, 0x00080000
/* B3: G_RDPHALF_2 */
.set G_RDPHALF_2, 0xB3
/* B4: G_RDPHALF_1 */
.set G_RDPHALF_1, 0xB4
/* B6: G_CLEARGEOMETRYMODE */
.set G_CLEARGEOMETRYMODE, 0xB6
.macro gsSPClearGeometryMode flags
.word G_CLEARGEOMETRYMODE << 24
.word \flags
.endm
/* B7: G_SETGEOMETRYMODE */
.set G_SETGEOMETRYMODE, 0xB7
.macro gsSPSetGeometryMode flags
.word G_SETGEOMETRYMODE << 24
.word \flags
.endm
/* B8: G_ENDDL */
.set G_ENDDL, 0xB8
.macro gsSPEndDisplayList
f3d_noparam G_ENDDL
.endm
/* B9: G_SETOTHERMODE_L */
.set G_SETOTHERMODE_L, 0xB9
/* G_SETOTHERMODE_L sft: shift count */
.set G_MDSFT_ALPHACOMPARE, 0
.set G_MDSFT_ZSRCSEL, 2
.set G_MDSFT_RENDERMODE, 3
.set G_MDSFT_BLENDER, 16
/* BA: G_SETOTHERMODE_H */
.set G_SETOTHERMODE_H, 0xBA
/* G_SETOTHERMODE_H sft: shift count */
.set G_MDSFT_ALPHADITHER, 4
.set G_MDSFT_RGBDITHER, 6
.set G_MDSFT_COMBKEY, 8
.set G_MDSFT_TEXTCONV, 9
.set G_MDSFT_TEXTFILT, 12
.set G_MDSFT_TEXTLUT, 14
.set G_MDSFT_TEXTLOD, 16
.set G_MDSFT_TEXTDETAIL, 17
.set G_MDSFT_TEXTPERSP, 19
.set G_MDSFT_CYCLETYPE, 20
.set G_MDSFT_PIPELINE, 23
.macro gsSPSetOtherMode cmd, sft, len, data
.word ((\cmd & 0xFF) << 24) | ((\sft & 0xFF) << 8) | (\len & 0xFF)
.word \data
.endm
/* BB: G_TEXTURE */
.set G_TEXTURE, 0xBB
.macro gsSPTexture scaleS, scaleT, level, tile, enable
.word (G_TEXTURE << 24) | ((\level & 0x7) << 11) | ((\tile & 0x7) << 8) | \enable
.word ((\scaleS & 0xFFFF) << 16) | (\scaleT & 0xFFFF)
.endm
/* BC: G_MOVEWORD */
.set G_MOVEWORD, 0xBC
.macro gsMoveWd index, offset, data
.word G_MOVEWORD << 24 | ((\index & 0xFFFF) << 8) | (\offset & 0xFF)
.word \data
.endm
/* BF: G_TRI1 */
.set G_TRI1, 0xBF
.macro gsSP1Triangle v0, v1, v2, flag
.word G_TRI1 << 24
.byte \flag, \v0*10, \v1*10, \v2*10
.endm
/* C0: G_NOOP */
.set G_NOOP, 0xC0
.macro gsDPNoOp
f3d_noparam G_NOOP
.endm
/* E6: G_RDPLOADSYNC */
.set G_RDPLOADSYNC, 0xE6
.macro gsDPLoadSync
f3d_noparam G_RDPLOADSYNC
.endm
/* E7: G_RDPPIPESYNC */
.set G_RDPPIPESYNC, 0xE7
.macro gsDPPipeSync
f3d_noparam G_RDPPIPESYNC
.endm
/* E8: G_RDPTILESYNC */
.set G_RDPTILESYNC, 0xE8
.macro gsDPTileSync
f3d_noparam G_RDPTILESYNC
.endm
/* E9: G_RDPFULLSYNC */
.set G_RDPFULLSYNC, 0xE9
.macro gsDPFullSync
f3d_noparam G_RDPFULLSYNC
.endm
/* F0: G_LOADTLUT */
.set G_LOADTLUT, 0xF0
.macro gsDPLoadTLUTCmd tile, count
.word G_LOADTLUT << 24
.word ((\tile & 0x7) << 24) | (\count & 0x3FFF) << 10
.endm
/* F1: unused */
/* F2: G_SETTILESIZE */
.set G_SETTILESIZE, 0xF2
.macro gsDPSetTileSize tile, uls, ult, lrs, lrt
.word (G_SETTILESIZE << 24) | ((\uls & 0x0FFF) << 12) | (\ult & 0x0FFF)
.word ((\tile & 0x7) << 24) | ((\lrs & 0x0FFF) << 12) | (\lrt & 0x0FFF)
.endm
/* F3: G_LOADBLOCK */
.set G_LOADBLOCK, 0xF3
.macro gsDPLoadBlock tile, uls, ult, lrs, dxt
.word (G_LOADBLOCK << 24) | ((\uls & 0x0FFF) << 12) | (\ult & 0x0FFF)
.word ((\tile & 0x7) << 24) | ((\lrs & 0x0FFF) << 12) | (\dxt & 0x0FFF)
.endm
/* F5: G_SETTILE */
.set G_TX_LOADTILE, 0x7
.set G_TX_RENDERTILE, 0x0
/* axis clamp and mirror flags */
.set G_TX_NOMIRROR, 0x0
.set G_TX_WRAP, 0x0
.set G_TX_MIRROR, 0x1
.set G_TX_CLAMP, 0x2
/* mask flags */
.set G_TX_NOMASK, 0x0
/* shift flags */
.set G_TX_NOLOD, 0x0
.set G_SETTILE, 0xF5
.macro gsDPSetTile fmt, siz, line, tmem, tile, palette, cmt, maskt, shiftt, cms, masks, shifts
.word (G_SETTILE << 24) | ((\fmt & 0x7) << 21) | ((\siz & 0x3) << 19) | ((\line & 0x1FF) << 9) | (\tmem & 0x1FF)
.word ((\tile & 0x7) << 24) | ((\palette & 0xF) << 20) | ((\cmt & 0x3) << 18) | ((\maskt & 0xF) << 14) | ((\shiftt & 0xF) << 10) | ((\cms & 0x3) << 8) | ((\masks & 0xF) << 4) | (\shifts & 0xF)
.endm
/* F6: G_FILLRECT */
.set G_FILLRECT, 0xF6
.macro gsDPFillRectangle ulx, uly, lrx, lry
.word (G_FILLRECT << 24) | ((\lrx & 0x3FF) << 14) | ((\lry & 0x3FF) << 2)
.word ((\ulx & 0x3FF) << 14) | ((\uly & 0x3FF) << 2)
.endm
/* F7: G_SETFILLCOLOR */
.set G_SETFILLCOLOR, 0xF7
.macro gsDPSetFillColor fillValue
.word G_SETFILLCOLOR << 24
.word \fillValue
.endm
/* helper for RGBA colors */
.macro sDPRGBColor cmd r, g, b, a
.word \cmd << 24
.byte \r, \g, \b, \a
.endm
/* F8: G_SETFOGCOLOR */
.set G_SETFOGCOLOR, 0xF8
.macro gsDPSetFogColor r, g, b, a
sDPRGBColor G_SETFOGCOLOR, \r, \g, \b, \a
.endm
/* F9: G_SETBLENDCOLOR */
.set G_SETBLENDCOLOR, 0xF9
.macro gsDPSetBlendColor r, g, b, a
sDPRGBColor G_SETBLENDCOLOR, \r, \g, \b, \a
.endm
/* FA: G_SETPRIMCOLOR */
.set G_SETPRIMCOLOR, 0xFA
.macro gsDPSetPrimColor m, l, r, g, b, a
.word (G_SETPRIMCOLOR << 24) | ((\m & 0xFF) << 8) | (\l & 0xFF)
.byte \r, \g, \b, \a
.endm
/* FB: G_SETENVCOLOR */
.set G_SETENVCOLOR, 0xFB
.macro gsDPSetEnvColor r, g, b, a
sDPRGBColor G_SETENVCOLOR, \r, \g, \b, \a
.endm
/* FC: G_SETCOMBINE */
/* color combiner */
.set G_CCMUX_COMBINED, 0
.set G_CCMUX_TEXEL0, 1
.set G_CCMUX_TEXEL1, 2
.set G_CCMUX_PRIMITIVE, 3
.set G_CCMUX_SHADE, 4
.set G_CCMUX_ENVIRONMENT, 5
.set G_CCMUX_CENTER, 6
.set G_CCMUX_SCALE, 6
.set G_CCMUX_COMBINED_ALPHA, 7
.set G_CCMUX_TEXEL0_ALPHA, 8
.set G_CCMUX_TEXEL1_ALPHA, 9
.set G_CCMUX_PRIMITIVE_ALPHA, 10
.set G_CCMUX_SHADE_ALPHA, 11
.set G_CCMUX_ENV_ALPHA, 12
.set G_CCMUX_LOD_FRACTION, 13
.set G_CCMUX_PRIM_LOD_FRAC, 14
.set G_CCMUX_NOISE, 7
.set G_CCMUX_K4, 7
.set G_CCMUX_K5, 15
.set G_CCMUX_1, 6
.set G_CCMUX_0, 31
/* alpha combiner */
.set G_ACMUX_COMBINED, 0
.set G_ACMUX_TEXEL0, 1
.set G_ACMUX_TEXEL1, 2
.set G_ACMUX_PRIMITIVE, 3
.set G_ACMUX_SHADE, 4
.set G_ACMUX_ENVIRONMENT, 5
.set G_ACMUX_LOD_FRACTION, 0
.set G_ACMUX_PRIM_LOD_FRAC, 6
.set G_ACMUX_1, 6
.set G_ACMUX_0, 7
.set G_SETCOMBINE, 0xFC
.macro gsDPSetCombine muxs0, muxs1
.word (G_SETCOMBINE << 24) | (\muxs0 & 0x00FFFFFF)
.word \muxs1
.endm
.macro gsDPSetCombineMode a0, b0, c0, d0, Aa0, Ab0, Ac0, Ad0, a1, b1, c1, d1, Aa1, Ab1, Ac1, Ad1
.word (G_SETCOMBINE << 24) | ((\a0 & 0xF) << 20) | ((\c0 & 0x1F) << 15) | ((\Aa0 & 0x7) << 12) | ((\Ac0 & 0x7) << 9) | ((\a1 & 0xF) << 5) | (\c1 & 0x1F)
.word ((\b0 & 0xF) << 28) | ((\b1 & 0xF) << 24) | ((\Aa1 & 0x7) << 21) | ((\Ac1 & 0x7) << 18) | ((\d0 & 0x7) << 15) | ((\Ab0 & 0x7) << 12) | ((\Ad0 & 0x7) << 9) | ((\d1 & 0x7) << 6) | ((\Ab1 & 0x7) << 3) | (\Ad1 & 0x7)
.endm
/* FD: G_SETTIMG */
/* fmt */
.set G_IM_FMT_RGBA, 0x00
.set G_IM_FMT_YUV, 0x01
.set G_IM_FMT_CI, 0x02
.set G_IM_FMT_IA, 0x03
.set G_IM_FMT_I, 0x04
/* size */
.set G_IM_SIZ_4b, 0x00
.set G_IM_SIZ_8b, 0x01
.set G_IM_SIZ_16b, 0x02
.set G_IM_SIZ_32b, 0x03
.set G_SETTIMG, 0xFD
.macro gsDPSetTextureImage fmt, size, width, segAddr
.word (G_SETTIMG << 24) | ((\fmt & 0x7) << 21) | ((\size & 0x3) << 19) | ((\width-1) & 0x0FFF)
.word \segAddr
.endm
include/ultra64/interrupt.h
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#ifndef _ULTRA64_INTERRUPT_H_
#define _ULTRA64_INTERRUPT_H_
/* Types */
typedef u32 OSIntMask;
/* Functions */
OSIntMask osGetIntMask(void);
OSIntMask osSetIntMask(OSIntMask);
#endif
include/ultra64/libaudio.h
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@@ -1,20 +0,0 @@
#ifndef _ULTRA64_LIBAUDIO_H_
#define _ULTRA64_LIBAUDIO_H_
typedef struct
{
u8 *offset;
s32 len;
} ALSeqData;
typedef struct
{
s16 revision;
s16 seqCount;
ALSeqData seqArray[1];
} ALSeqFile;
void alSeqFileNew(ALSeqFile *f, u8 *base);
#endif
include/ultra64/libc.h
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@@ -1,8 +0,0 @@
#ifndef _ULTRA64_LIBC_H_
#define _ULTRA64_LIBC_H_
int sprintf(char *, const char *, ... );
void bcopy(const void *src, void *dest, size_t size);
void bzero(void *s, size_t size);
#endif
include/ultra64/message.h
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#ifndef _ULTRA64_MESSAGE_H_
#define _ULTRA64_MESSAGE_H_
/* Events */
#define OS_EVENT_SW1 0
#define OS_EVENT_SW2 1
#define OS_EVENT_CART 2
#define OS_EVENT_COUNTER 3
#define OS_EVENT_SP 4
#define OS_EVENT_SI 5
#define OS_EVENT_AI 6
#define OS_EVENT_VI 7
#define OS_EVENT_PI 8
#define OS_EVENT_DP 9
#define OS_EVENT_CPU_BREAK 10
#define OS_EVENT_SP_BREAK 11
#define OS_EVENT_FAULT 12
#define OS_EVENT_THREADSTATUS 13
#define OS_EVENT_PRENMI 14
#define OS_MESG_NOBLOCK 0
#define OS_MESG_BLOCK 1
/* Types */
typedef u32 OSEvent;
typedef void *OSMesg;
typedef struct OSMesgQueue_s
{
OSThread *mtqueue;
OSThread *fullqueue;
s32 validCount;
s32 first;
s32 msgCount;
OSMesg *msg;
} OSMesgQueue;
/* Functions */
void osCreateMesgQueue(OSMesgQueue *mq, OSMesg *msgBuf, s32 count);
s32 osSendMesg(OSMesgQueue *mq, OSMesg msg, s32 flag);
s32 osJamMesg(OSMesgQueue *mq, OSMesg msg, s32 flag);
s32 osRecvMesg(OSMesgQueue *mq, OSMesg *msg, s32 flag);
void osSetEventMesg(OSEvent e, OSMesgQueue *mq, OSMesg msg);
void osViSetEvent(OSMesgQueue *mq, OSMesg msg, u32 retraceCount);
s32 osContStartReadData(OSMesgQueue *mq);
#endif
include/ultra64/os_ai.h
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#ifndef _ULTRA64_AI_H_
#define _ULTRA64_AI_H_
u32 osAiGetLength(void);
s32 osAiSetNextBuffer(void *, u32);
s32 osAiSetFrequency(u32);
#endif
include/ultra64/os_cont.h
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#ifndef _ULTRA64_CONTROLLER_H_
#define _ULTRA64_CONTROLLER_H_
typedef struct
{
/*0x00*/ u16 type; /* Controller Type */
/*0x02*/ u8 status; /* Controller status */
/*0x03*/ u8 errno;
} OSContStatus;
typedef struct {
/*0x00*/ u16 button;
/*0x02*/ s8 stick_x; /* -80 <= stick_x <= 80 */
/*0x03*/ s8 stick_y; /* -80 <= stick_y <= 80 */
/*0x04*/ u8 errno;
} OSContPad;
#define A_BUTTON (1 << 15) // 0x8000
#define B_BUTTON (1 << 14) // 0x4000
#define Z_TRIG (1 << 13) // 0x2000
#define START_BUTTON (1 << 12) // 0x1000
#define U_JPAD (1 << 11) // 0x0800
#define D_JPAD (1 << 10) // 0x0400
#define L_JPAD (1 << 9) // 0x0200
#define R_JPAD (1 << 8) // 0x0100
#define DUMMY_1 (1 << 7) // 0x0080 (unused)
#define DUMMY_2 (1 << 6) // 0x0040 (unused)
#define L_TRIG (1 << 5) // 0x0020
#define R_TRIG (1 << 4) // 0x0010
#define U_CBUTTONS (1 << 3) // 0x0008
#define D_CBUTTONS (1 << 2) // 0x0004
#define L_CBUTTONS (1 << 1) // 0x0002
#define R_CBUTTONS (1 << 0) // 0x0001
s32 osContInit(OSMesgQueue *, u8 *, OSContStatus *);
void osContGetReadData(OSContPad *);
#endif
include/ultra64/pi.h
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#ifndef _ULTRA64_PI_H_
#define _ULTRA64_PI_H_
/* Ultra64 Parallel Interface */
/* Types */
typedef struct
{
u32 errStatus;
void *dramAddr;
void *C2Addr;
u32 sectorSize;
u32 C1ErrNum;
u32 C1ErrSector[4];
} __OSBlockInfo;
typedef struct
{
u32 cmdType;
u16 transferMode;
u16 blockNum;
s32 sectorNum;
u32 devAddr;
u32 bmCtlShadow;
u32 seqCtlShadow;
__OSBlockInfo block[2];
} __OSTranxInfo;
typedef struct OSPiHandle_s
{
struct OSPiHandle_s *next;
u8 type;
u8 latency;
u8 pageSize;
u8 relDuration;
u8 pulse;
u8 domain;
u32 baseAddress;
u32 speed;
__OSTranxInfo transferInfo;
} OSPiHandle;
typedef struct
{
u8 type;
u32 address;
} OSPiInfo;
typedef struct
{
u16 type;
u8 pri;
u8 status;
OSMesgQueue *retQueue;
} OSIoMesgHdr;
typedef struct
{
/*0x00*/ OSIoMesgHdr hdr;
/*0x08*/ void *dramAddr;
/*0x0C*/ u32 devAddr;
/*0x10*/ u32 size;
OSPiHandle *piHandle; //from the official definition
} OSIoMesg;
/* Definitions */
#define OS_READ 0 // device -> RDRAM
#define OS_WRITE 1 // device <- RDRAM
#define OS_MESG_PRI_NORMAL 0
#define OS_MESG_PRI_HIGH 1
/* Functions */
s32 osPiStartDma(OSIoMesg *mb, s32 priority, s32 direction,
u32 devAddr, void *vAddr, u32 nbytes, OSMesgQueue *mq);
void osCreatePiManager(OSPri pri, OSMesgQueue *cmdQ, OSMesg *cmdBuf,
s32 cmdMsgCnt);
OSMesgQueue *osPiGetCmdQueue(void);
s32 osPiWriteIo(u32 devAddr, u32 data);
s32 osPiReadIo(u32 devAddr, u32 *data);
#endif
include/ultra64/rdp.h
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#ifndef _ULTRA64_RDP_H_
#define _ULTRA64_RDP_H_
/* DP Command Registers */
#define DPC_REG_BASE 0xA4100000
#define DPC_START_REG (*(vu32 *)(DPC_REG_BASE + 0x00))
#define DPC_END_REG (*(vu32 *)(DPC_REG_BASE + 0x04))
#define DPC_CURRENT_REG (*(vu32 *)(DPC_REG_BASE + 0x08))
#define DPC_STATUS_REG (*(vu32 *)(DPC_REG_BASE + 0x0C))
#define DPC_CLOCK_REG (*(vu32 *)(DPC_REG_BASE + 0x10))
#define DPC_BUFBUSY_REG (*(vu32 *)(DPC_REG_BASE + 0x14))
#define DPC_PIPEBUSY_REG (*(vu32 *)(DPC_REG_BASE + 0x18))
#define DPC_TMEM_REG (*(vu32 *)(DPC_REG_BASE + 0x1C))
/* DP Span Registers */
#define DPS_REG_BASE 0xA4200000
#define DPS_TBIST_REG (*(vu32 *)(DPS_REG_BASE + 0x00))
#define DPS_TEST_MODE_REG (*(vu32 *)(DPS_REG_BASE + 0x04))
#define DPS_BUFTEST_ADDR_REG (*(vu32 *)(DPS_REG_BASE + 0x08))
#define DPS_BUFTEST_DATA_REG (*(vu32 *)(DPS_REG_BASE + 0x0C))
/* Functions */
u32 osDpGetStatus(void);
void osDpSetStatus(u32 status);
#endif
include/ultra64/tlb.h
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#ifndef _ULTRA64_TLB_H_
#define _ULTRA64_TLB_H_
/* Types */
typedef u32 OSPageMask;
/* OSPageMask Valid Values */
#define OS_PM_4K 0x0000000
#define OS_PM_16K 0x0006000
#define OS_PM_64K 0x001e000
#define OS_PM_256K 0x007e000
#define OS_PM_1M 0x01fe000
#define OS_PM_4M 0x07fe000
#define OS_PM_16M 0x1ffe000
/* Functions */
void osMapTLB(s32 index, OSPageMask pm, void *vaddr, u32 evenpaddr,
u32 oddpaddr, s32 asid);
void osMapTLBRdb(void);
void osUnmapTLB(s32 index);
void osUnmapTLBAll(void);
void osSetTLBASID(s32 asid);
#endif