mirror of
https://github.com/open-goal/jak-project
synced 2026-07-11 15:28:58 -04:00
Make decompiler more successful (#66)
* w/early-return-and-break * more edge cases * all instructions in non asm functions now convert to ir * cleanup * implement rarely used control flow in IR * clang format
This commit is contained in:
water111
@@ -1,3 +1,12 @@
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/*!
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* @file BasicOpBuilder.cpp
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* Convert a basic block into a sequence of IR operations.
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* Build up basic set instructions from GOAL code
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* Recognize common GOAL compiler idioms
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* Recognize branch delay slot use
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* Recognize assembly ops and pass them through as IR_Asm
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*/
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#include "BasicOpBuilder.h"
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#include "decompiler/Function/Function.h"
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#include "decompiler/Function/BasicBlocks.h"
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@@ -5,28 +14,129 @@
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namespace {
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/*!
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* Create a GOAL "set!" form.
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* These will later be compacted into more complicated nested expressions.
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*/
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std::shared_ptr<IR_Set> make_set(IR_Set::Kind kind,
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const std::shared_ptr<IR>& dst,
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const std::shared_ptr<IR>& src) {
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return std::make_shared<IR_Set>(kind, dst, src);
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}
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/*!
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* Create an IR representing a register at a certain point. Idx is the instruction index.
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*/
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std::shared_ptr<IR_Register> make_reg(Register reg, int idx) {
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return std::make_shared<IR_Register>(reg, idx);
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}
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/*!
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* Create an IR representing a symbol. The symbol itself ('thing), not the value.
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*/
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std::shared_ptr<IR_Symbol> make_sym(const std::string& name) {
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return std::make_shared<IR_Symbol>(name);
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}
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/*!
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* Create an IR representing the value of a symbol. Can be read/written.
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*/
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std::shared_ptr<IR_SymbolValue> make_sym_value(const std::string& name) {
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return std::make_shared<IR_SymbolValue>(name);
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}
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/*!
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* Create an integer constant.
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*/
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std::shared_ptr<IR_IntegerConstant> make_int(int64_t x) {
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return std::make_shared<IR_IntegerConstant>(x);
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}
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/*!
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* Create an assembly passthrough in the form op dst, src, src
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*/
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std::shared_ptr<IR> to_asm_reg_reg_reg(const std::string& str, Instruction& instr, int idx) {
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auto result = std::make_shared<IR_AsmOp>(str);
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result->dst = make_reg(instr.get_dst(0).get_reg(), idx);
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result->src0 = make_reg(instr.get_src(0).get_reg(), idx);
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result->src1 = make_reg(instr.get_src(1).get_reg(), idx);
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return result;
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}
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/*!
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* Create an assembly passthrough for op src
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*/
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std::shared_ptr<IR> to_asm_src_reg(const std::string& str, Instruction& instr, int idx) {
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auto result = std::make_shared<IR_AsmOp>(str);
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result->src0 = make_reg(instr.get_src(0).get_reg(), idx);
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return result;
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}
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/*!
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* Create an assembly passthrough for op dst src
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*/
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std::shared_ptr<IR> to_asm_dst_reg_src_reg(const std::string& str, Instruction& instr, int idx) {
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auto result = std::make_shared<IR_AsmOp>(str);
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result->dst = make_reg(instr.get_dst(0).get_reg(), idx);
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result->src0 = make_reg(instr.get_src(0).get_reg(), idx);
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return result;
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}
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/*!
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* Convert an instruction atom to IR.
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*/
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std::shared_ptr<IR> instr_atom_to_ir(const InstructionAtom& ia, int idx) {
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switch (ia.kind) {
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case InstructionAtom::REGISTER:
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return make_reg(ia.get_reg(), idx);
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case InstructionAtom::VU_Q:
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return std::make_shared<IR_AsmReg>(IR_AsmReg::VU_Q);
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case InstructionAtom::VU_ACC:
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return std::make_shared<IR_AsmReg>(IR_AsmReg::VU_ACC);
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case InstructionAtom::IMM:
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return make_int(ia.get_imm());
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default:
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assert(false);
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}
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}
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std::shared_ptr<IR> to_asm_automatic(const std::string& str, Instruction& instr, int idx) {
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auto result = std::make_shared<IR_AsmOp>(str);
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assert(instr.n_dst < 2);
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assert(instr.n_src < 4);
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if (instr.n_dst >= 1) {
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result->dst = instr_atom_to_ir(instr.get_dst(0), idx);
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}
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if (instr.n_src >= 1) {
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result->src0 = instr_atom_to_ir(instr.get_src(0), idx);
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}
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if (instr.n_src >= 2) {
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result->src1 = instr_atom_to_ir(instr.get_src(1), idx);
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}
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if (instr.n_src >= 3) {
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result->src1 = instr_atom_to_ir(instr.get_src(2), idx);
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}
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return result;
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}
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std::shared_ptr<IR> try_subu(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::SUBU, {}, {}, {})) {
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return to_asm_reg_reg_reg("subu", instr, idx);
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_sllv(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::SLLV, {}, {}, make_gpr(Reg::R0))) {
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return to_asm_reg_reg_reg("sllv", instr, idx);
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_or(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::OR, {}, make_gpr(Reg::S7), make_gpr(Reg::R0))) {
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return make_set(IR_Set::REG_64, make_reg(instr.get_dst(0).get_reg(), idx), make_sym("#f"));
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@@ -402,7 +512,7 @@ std::shared_ptr<IR> try_daddu(Instruction& instr, int idx) {
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std::make_shared<IR_IntMath2>(IR_IntMath2::ADD, make_reg(instr.get_src(0).get_reg(), idx),
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make_reg(instr.get_src(1).get_reg(), idx)));
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}
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return nullptr;
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return to_asm_reg_reg_reg("daddu", instr, idx);
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}
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std::shared_ptr<IR> try_dsubu(Instruction& instr, int idx) {
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@@ -459,6 +569,16 @@ std::shared_ptr<IR> try_andi(Instruction& instr, int idx) {
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return nullptr;
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}
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std::shared_ptr<IR> try_xori(Instruction& instr, int idx) {
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if (instr.kind == InstructionKind::XORI) {
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return make_set(
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IR_Set::REG_64, make_reg(instr.get_dst(0).get_reg(), idx),
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std::make_shared<IR_IntMath2>(IR_IntMath2::XOR, make_reg(instr.get_src(0).get_reg(), idx),
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make_int(instr.get_src(1).get_imm())));
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_nor(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::NOR, {}, {}, {}) &&
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!instr.get_src(0).is_reg(make_gpr(Reg::S7)) && instr.get_src(1).is_reg(make_gpr(Reg::R0))) {
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@@ -533,6 +653,17 @@ std::shared_ptr<IR> try_dsrlv(Instruction& instr, int idx) {
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return nullptr;
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}
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std::shared_ptr<IR> try_dsllv(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::DSLLV, {}, {}, {}) &&
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!instr.get_src(0).is_reg(make_gpr(Reg::S7)) && !instr.get_src(1).is_reg(make_gpr(Reg::S7))) {
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return make_set(IR_Set::REG_64, make_reg(instr.get_dst(0).get_reg(), idx),
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std::make_shared<IR_IntMath2>(IR_IntMath2::LEFT_SHIFT,
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make_reg(instr.get_src(0).get_reg(), idx),
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make_reg(instr.get_src(1).get_reg(), idx)));
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_sw(Instruction& instr, int idx) {
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if (instr.kind == InstructionKind::SW && instr.get_src(1).is_sym() &&
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instr.get_src(2).is_reg(make_gpr(Reg::S7))) {
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@@ -647,6 +778,22 @@ std::shared_ptr<IR> try_movs(Instruction& instr, int idx) {
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return nullptr;
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}
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std::shared_ptr<IR> try_movn(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::MOVN, {}, make_gpr(Reg::S7), {})) {
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return make_set(IR_Set::REG_64, make_reg(instr.get_dst(0).get_reg(), idx),
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std::make_shared<IR_CMoveF>(make_reg(instr.get_src(1).get_reg(), idx), false));
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_movz(Instruction& instr, int idx) {
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if (is_gpr_3(instr, InstructionKind::MOVZ, {}, make_gpr(Reg::S7), {})) {
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return make_set(IR_Set::REG_64, make_reg(instr.get_dst(0).get_reg(), idx),
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std::make_shared<IR_CMoveF>(make_reg(instr.get_src(1).get_reg(), idx), true));
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}
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return nullptr;
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}
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// TWO Instructions
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std::shared_ptr<IR> try_div(Instruction& instr, Instruction& next_instr, int idx) {
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if (instr.kind == InstructionKind::DIV && instr.get_src(0).is_reg() &&
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@@ -897,7 +1044,53 @@ std::shared_ptr<IR> try_lui(Instruction& i0, Instruction& i1, int idx) {
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return nullptr;
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}
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std::shared_ptr<IR> try_slt(Instruction& i0, Instruction& i1, int idx) {
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if (is_gpr_3(i0, InstructionKind::SLT, {}, {}, {})) {
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auto temp = i0.get_dst(0).get_reg();
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auto left = i0.get_src(0).get_reg();
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auto right = i0.get_src(1).get_reg();
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if (is_gpr_3(i1, InstructionKind::MOVZ, left, right, temp)) {
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// success!
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auto result =
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make_set(IR_Set::REG_64, make_reg(left, idx),
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std::make_shared<IR_IntMath2>(IR_IntMath2::MIN_SIGNED, make_reg(left, idx),
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make_reg(right, idx)));
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result->clobber = make_reg(temp, idx);
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return result;
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}
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if (is_gpr_3(i1, InstructionKind::MOVN, left, right, temp)) {
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// success!
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auto result =
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make_set(IR_Set::REG_64, make_reg(left, idx),
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std::make_shared<IR_IntMath2>(IR_IntMath2::MAX_SIGNED, make_reg(left, idx),
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make_reg(right, idx)));
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result->clobber = make_reg(temp, idx);
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return result;
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}
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}
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return nullptr;
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}
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// THREE OP
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std::shared_ptr<IR> try_lui(Instruction& i0, Instruction& i1, Instruction& i2, int idx) {
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if (i0.kind == InstructionKind::LUI && i1.kind == InstructionKind::ORI &&
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i0.get_src(0).is_label() && i1.get_src(1).is_label() &&
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is_gpr_3(i2, InstructionKind::ADDU, {}, make_gpr(Reg::FP), {})) {
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assert(i0.get_dst(0).get_reg() == i1.get_src(0).get_reg());
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assert(i0.get_src(0).get_label() == i1.get_src(1).get_label());
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assert(i2.get_dst(0).get_reg() == i2.get_src(1).get_reg());
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assert(i2.get_dst(0).get_reg() == i1.get_dst(0).get_reg());
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auto op = make_set(IR_Set::REG_64, make_reg(i1.get_dst(0).get_reg(), idx),
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std::make_shared<IR_StaticAddress>(i0.get_src(0).get_label()));
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if (i0.get_dst(0).get_reg() != i1.get_dst(0).get_reg()) {
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op->clobber = make_reg(i0.get_dst(0).get_reg(), idx);
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}
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return op;
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_dsubu(Instruction& i0, Instruction& i1, Instruction& i2, int idx) {
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if (i0.kind == InstructionKind::DSUBU && i1.kind == InstructionKind::DADDIU &&
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i2.kind == InstructionKind::MOVN) {
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@@ -1136,6 +1329,21 @@ std::shared_ptr<IR> try_clts(Instruction& i0, Instruction& i1, Instruction& i2,
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return nullptr;
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}
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std::shared_ptr<IR> try_cles(Instruction& i0, Instruction& i1, Instruction& i2, int idx) {
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if (i0.kind == InstructionKind::CLES && i1.kind == InstructionKind::BC1T) {
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return std::make_shared<IR_Branch>(
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Condition(Condition::FLOAT_LEQ, make_reg(i0.get_src(0).get_reg(), idx),
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make_reg(i0.get_src(1).get_reg(), idx), nullptr),
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i1.get_src(0).get_label(), get_branch_delay(i2, idx), false);
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} else if (i0.kind == InstructionKind::CLES && i1.kind == InstructionKind::BC1F) {
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return std::make_shared<IR_Branch>(
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Condition(Condition::FLOAT_GREATER_THAN, make_reg(i0.get_src(0).get_reg(), idx),
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make_reg(i0.get_src(1).get_reg(), idx), nullptr),
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i1.get_src(0).get_label(), get_branch_delay(i2, idx), false);
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}
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return nullptr;
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}
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std::shared_ptr<IR> try_sltu(Instruction& i0, Instruction& i1, Instruction& i2, int idx) {
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if (i0.kind == InstructionKind::SLTU && i1.kind == InstructionKind::BNE) {
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auto clobber_reg = i0.get_dst(0).get_reg();
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@@ -1268,6 +1476,12 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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case InstructionKind::CLTS:
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result = try_clts(i, next, next_next, instr);
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break;
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case InstructionKind::CLES:
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result = try_cles(i, next, next_next, instr);
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break;
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case InstructionKind::LUI:
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result = try_lui(i, next, next_next, instr);
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break;
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default:
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result = nullptr;
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}
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@@ -1317,6 +1531,9 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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case InstructionKind::LUI:
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result = try_lui(i, next, instr);
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break;
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case InstructionKind::SLT:
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result = try_slt(i, next, instr);
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break;
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default:
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result = nullptr;
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}
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@@ -1343,6 +1560,9 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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case InstructionKind::ANDI:
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result = try_andi(i, instr);
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break;
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case InstructionKind::XORI:
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result = try_xori(i, instr);
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break;
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case InstructionKind::NOR:
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result = try_nor(i, instr);
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break;
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@@ -1393,6 +1613,10 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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break;
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case InstructionKind::DSUBU:
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result = try_dsubu(i, instr);
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if (!result) {
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// fails if it uses s7 register.
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result = to_asm_automatic(i.op_name_to_string(), i, instr);
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}
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break;
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case InstructionKind::MULT3:
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result = try_mult3(i, instr);
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@@ -1402,6 +1626,9 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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break;
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case InstructionKind::POR:
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result = try_por(i, instr);
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if (!result) {
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result = to_asm_automatic(i.op_name_to_string(), i, instr);
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}
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break;
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case InstructionKind::LBU:
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result = try_lbu(i, instr);
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@@ -1447,12 +1674,18 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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break;
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case InstructionKind::ADDIU:
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result = try_addiu(i, instr);
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if (!result) {
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result = to_asm_automatic(i.op_name_to_string(), i, instr);
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}
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break;
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case InstructionKind::LUI:
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result = try_lui(i, instr);
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break;
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case InstructionKind::SLL:
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result = try_sll(i, instr);
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if (!result) {
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result = to_asm_automatic(i.op_name_to_string(), i, instr);
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}
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break;
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case InstructionKind::SB:
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result = try_sb(i, instr);
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@@ -1484,6 +1717,168 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
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case InstructionKind::DSRLV:
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result = try_dsrlv(i, instr);
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break;
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case InstructionKind::DSLLV:
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result = try_dsllv(i, instr);
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break;
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case InstructionKind::SUBU:
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result = try_subu(i, instr);
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break;
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case InstructionKind::SLLV:
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result = try_sllv(i, instr);
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break;
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case InstructionKind::MOVN:
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result = try_movn(i, instr);
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if (!result) {
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result = to_asm_automatic(i.op_name_to_string(), i, instr);
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}
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break;
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case InstructionKind::MOVZ:
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result = try_movz(i, instr);
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if (!result) {
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result = to_asm_automatic(i.op_name_to_string(), i, instr);
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}
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break;
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// Everything below here is an "asm passthrough".
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case InstructionKind::JR:
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result = to_asm_src_reg("jr", i, instr);
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break;
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// reg reg
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case InstructionKind::QMFC2:
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result = to_asm_dst_reg_src_reg(i.op_name_to_string(), i, instr);
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break;
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// VU/COP2
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case InstructionKind::VMOVE:
|
||||
case InstructionKind::VFTOI0:
|
||||
case InstructionKind::VFTOI4:
|
||||
case InstructionKind::VFTOI12:
|
||||
case InstructionKind::VITOF0:
|
||||
case InstructionKind::VITOF12:
|
||||
case InstructionKind::VITOF15:
|
||||
case InstructionKind::VABS:
|
||||
case InstructionKind::VADD:
|
||||
case InstructionKind::VSUB:
|
||||
case InstructionKind::VMUL:
|
||||
case InstructionKind::VMINI:
|
||||
case InstructionKind::VMAX:
|
||||
case InstructionKind::VOPMSUB:
|
||||
case InstructionKind::VMADD:
|
||||
case InstructionKind::VMSUB:
|
||||
case InstructionKind::VADD_BC:
|
||||
case InstructionKind::VSUB_BC:
|
||||
case InstructionKind::VMUL_BC:
|
||||
case InstructionKind::VMULA_BC:
|
||||
case InstructionKind::VMADD_BC:
|
||||
case InstructionKind::VADDA_BC:
|
||||
case InstructionKind::VMADDA_BC:
|
||||
case InstructionKind::VMSUBA_BC:
|
||||
case InstructionKind::VMSUB_BC:
|
||||
case InstructionKind::VMINI_BC:
|
||||
case InstructionKind::VMAX_BC:
|
||||
case InstructionKind::VADDQ:
|
||||
case InstructionKind::VSUBQ:
|
||||
case InstructionKind::VMULQ:
|
||||
case InstructionKind::VMSUBQ:
|
||||
case InstructionKind::VMULA:
|
||||
case InstructionKind::VADDA:
|
||||
case InstructionKind::VMADDA:
|
||||
case InstructionKind::VOPMULA:
|
||||
case InstructionKind::VDIV:
|
||||
case InstructionKind::VCLIP:
|
||||
case InstructionKind::VMULAQ:
|
||||
case InstructionKind::VMTIR:
|
||||
case InstructionKind::VIAND:
|
||||
case InstructionKind::VLQI:
|
||||
case InstructionKind::VIADDI:
|
||||
case InstructionKind::VSQI:
|
||||
case InstructionKind::VRGET:
|
||||
case InstructionKind::VSQRT:
|
||||
case InstructionKind::VRSQRT:
|
||||
case InstructionKind::VRXOR:
|
||||
case InstructionKind::VRNEXT:
|
||||
case InstructionKind::VNOP:
|
||||
case InstructionKind::VWAITQ:
|
||||
case InstructionKind::VCALLMS:
|
||||
|
||||
// FPU/COP1
|
||||
case InstructionKind::MULAS:
|
||||
case InstructionKind::MADDAS:
|
||||
case InstructionKind::MADDS:
|
||||
case InstructionKind::ADDAS:
|
||||
|
||||
// Moves / Loads / Stores
|
||||
case InstructionKind::CTC2:
|
||||
case InstructionKind::CFC2:
|
||||
case InstructionKind::SQC2:
|
||||
case InstructionKind::LQC2:
|
||||
case InstructionKind::LDR:
|
||||
case InstructionKind::LDL:
|
||||
case InstructionKind::QMTC2:
|
||||
case InstructionKind::MFC0:
|
||||
case InstructionKind::MTC0:
|
||||
case InstructionKind::SYNCL:
|
||||
case InstructionKind::SYNCP:
|
||||
case InstructionKind::SYSCALL:
|
||||
case InstructionKind::CACHE_DXWBIN:
|
||||
case InstructionKind::MTPC:
|
||||
case InstructionKind::MFPC:
|
||||
|
||||
// random math
|
||||
case InstructionKind::ADDU:
|
||||
case InstructionKind::SRL: // maybe bitfield ops use this?
|
||||
case InstructionKind::SRA:
|
||||
case InstructionKind::SLT:
|
||||
case InstructionKind::SLTI:
|
||||
|
||||
// MMI
|
||||
case InstructionKind::PSLLW:
|
||||
case InstructionKind::PSRAW:
|
||||
case InstructionKind::PSRAH:
|
||||
case InstructionKind::PLZCW:
|
||||
case InstructionKind::PMFHL_UW:
|
||||
case InstructionKind::PMFHL_LW:
|
||||
case InstructionKind::PMFHL_LH:
|
||||
case InstructionKind::PSLLH:
|
||||
case InstructionKind::PSRLH:
|
||||
case InstructionKind::PEXTLW:
|
||||
case InstructionKind::PPACH:
|
||||
case InstructionKind::PSUBW:
|
||||
case InstructionKind::PCGTW:
|
||||
case InstructionKind::PEXTLH:
|
||||
case InstructionKind::PEXTLB:
|
||||
case InstructionKind::PMAXH:
|
||||
case InstructionKind::PPACB:
|
||||
case InstructionKind::PADDW:
|
||||
case InstructionKind::PADDH:
|
||||
case InstructionKind::PMAXW:
|
||||
case InstructionKind::PPACW:
|
||||
case InstructionKind::PCEQW:
|
||||
case InstructionKind::PEXTUW:
|
||||
case InstructionKind::PMINH:
|
||||
case InstructionKind::PEXTUH:
|
||||
case InstructionKind::PEXTUB:
|
||||
case InstructionKind::PCEQB:
|
||||
case InstructionKind::PMINW:
|
||||
case InstructionKind::PABSW:
|
||||
case InstructionKind::PCPYLD:
|
||||
case InstructionKind::PROT3W:
|
||||
case InstructionKind::PAND:
|
||||
case InstructionKind::PMADDH:
|
||||
case InstructionKind::PMULTH:
|
||||
case InstructionKind::PEXEW:
|
||||
case InstructionKind::PCPYUD:
|
||||
case InstructionKind::PNOR:
|
||||
case InstructionKind::PCPYH:
|
||||
case InstructionKind::PINTEH:
|
||||
|
||||
// 128 bit integer
|
||||
// case InstructionKind::LQ:
|
||||
// case InstructionKind::SQ:
|
||||
|
||||
result = to_asm_automatic(i.op_name_to_string(), i, instr);
|
||||
break;
|
||||
default:
|
||||
result = nullptr;
|
||||
}
|
||||
@@ -1496,9 +1891,13 @@ void add_basic_ops_to_block(Function* func, const BasicBlock& block, LinkedObjec
|
||||
// everything failed
|
||||
if (!result) {
|
||||
// temp hack for debug:
|
||||
// printf("Instruction -> BasicOp failed on %s\n", i.to_string(*file).c_str());
|
||||
printf("Instruction -> BasicOp failed on %s\n", i.to_string(*file).c_str());
|
||||
func->add_basic_op(std::make_shared<IR_Failed>(), instr, instr + 1);
|
||||
} else {
|
||||
if (!func->contains_asm_ops && dynamic_cast<IR_AsmOp*>(result.get())) {
|
||||
func->warnings += "Function contains asm op";
|
||||
func->contains_asm_ops = true;
|
||||
}
|
||||
func->add_basic_op(result, instr, instr + length);
|
||||
instr += (length - 1);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user