mirror of
https://github.com/open-goal/jak-project
synced 2026-08-22 07:04:29 -04:00
[decompiler] clean up vector detection and add vector float product detection (#638)
* change * recognize vector float product and update tests
This commit is contained in:
water111
@@ -45,6 +45,10 @@ Register rsp() {
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return make_gpr(Reg::SP);
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}
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Register make_vf(int idx) {
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return Register(Reg::VF, idx);
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}
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/////////////////////////
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// Variable Helpers
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/////////////////////////
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@@ -1393,6 +1397,100 @@ std::unique_ptr<AtomicOp> convert_4(const Instruction& i0,
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// OP 5 Conversions
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//////////////////////
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std::unique_ptr<AtomicOp> convert_vector_plus(const Instruction& i0,
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const Instruction& i1,
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const Instruction& i2,
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const Instruction& i3,
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const Instruction& i4,
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int idx) {
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// vmove.w vf6, vf0
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if (i0.kind != InstructionKind::VMOVE || i0.get_src(0).get_reg() != make_vf(0) ||
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i0.get_dst(0).get_reg() != make_vf(6) || i0.cop2_dest != 1) {
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return nullptr;
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}
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// lqc2 vf4, 0(a1) (src1)
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if (i1.kind != InstructionKind::LQC2 || i1.get_dst(0).get_reg() != make_vf(4) ||
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!i1.get_src(0).is_imm(0)) {
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return nullptr;
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}
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Register src1 = i1.get_src(1).get_reg();
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// lqc2 vf5, 0(a2) (src2)
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if (i2.kind != InstructionKind::LQC2 || i2.get_dst(0).get_reg() != make_vf(5) ||
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!i2.get_src(0).is_imm(0)) {
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return nullptr;
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}
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Register src2 = i2.get_src(1).get_reg();
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// vadd.xyz vf6, vf4, vf5
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if (i3.kind != InstructionKind::VADD || i3.get_dst(0).get_reg() != make_vf(6) ||
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i3.get_src(0).get_reg() != make_vf(4) || i3.get_src(1).get_reg() != make_vf(5) ||
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i3.cop2_dest != 14) {
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return nullptr;
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}
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// sqc2 vf6, 0(a0) (dst)
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if (i4.kind != InstructionKind::SQC2 || i4.get_src(0).get_reg() != make_vf(6) ||
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!i4.get_src(1).is_imm(0)) {
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return nullptr;
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}
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Register dst = i4.get_src(2).get_reg();
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return std::make_unique<SetVarOp>(
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make_dst_var(dst, idx),
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SimpleExpression(SimpleExpression::Kind::VECTOR_PLUS, make_src_atom(dst, idx),
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make_src_atom(src1, idx), make_src_atom(src2, idx)),
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idx);
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}
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std::unique_ptr<AtomicOp> convert_vector_minus(const Instruction& i0,
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const Instruction& i1,
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const Instruction& i2,
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const Instruction& i3,
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const Instruction& i4,
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int idx) {
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// lqc2 vf4, 0(a1) (src1)
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if (i0.kind != InstructionKind::LQC2 || i0.get_dst(0).get_reg() != make_vf(4) ||
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!i0.get_src(0).is_imm(0)) {
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return nullptr;
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}
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Register src1 = i0.get_src(1).get_reg();
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// lqc2 vf5, 0(a2) (src2)
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if (i1.kind != InstructionKind::LQC2 || i1.get_dst(0).get_reg() != make_vf(5) ||
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!i1.get_src(0).is_imm(0)) {
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return nullptr;
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}
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Register src2 = i1.get_src(1).get_reg();
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// vmove.w vf6, vf0
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if (i2.kind != InstructionKind::VMOVE || i2.get_src(0).get_reg() != make_vf(0) ||
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i2.get_dst(0).get_reg() != make_vf(6) || i2.cop2_dest != 1) {
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return nullptr;
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}
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// vadd.xyz vf6, vf4, vf5
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if (i3.kind != InstructionKind::VSUB || i3.get_dst(0).get_reg() != make_vf(6) ||
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i3.get_src(0).get_reg() != make_vf(4) || i3.get_src(1).get_reg() != make_vf(5) ||
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i3.cop2_dest != 14) {
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return nullptr;
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}
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// sqc2 vf6, 0(a0) (dst)
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if (i4.kind != InstructionKind::SQC2 || i4.get_src(0).get_reg() != make_vf(6) ||
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!i4.get_src(1).is_imm(0)) {
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return nullptr;
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}
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Register dst = i4.get_src(2).get_reg();
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return std::make_unique<SetVarOp>(
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make_dst_var(dst, idx),
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SimpleExpression(SimpleExpression::Kind::VECTOR_MINUS, make_src_atom(dst, idx),
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make_src_atom(src1, idx), make_src_atom(src2, idx)),
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idx);
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}
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std::unique_ptr<AtomicOp> convert_5(const Instruction& i0,
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const Instruction& i1,
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const Instruction& i2,
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@@ -1410,6 +1508,86 @@ std::unique_ptr<AtomicOp> convert_5(const Instruction& i0,
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i3.get_src(0).is_reg(s6) && i4.kind == InstructionKind::MFLO1 && i4.get_dst(0).is_reg(s6)) {
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return std::make_unique<SpecialOp>(SpecialOp::Kind::SUSPEND, idx);
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}
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auto as_vector_plus = convert_vector_plus(i0, i1, i2, i3, i4, idx);
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if (as_vector_plus) {
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return as_vector_plus;
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}
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auto as_vector_minus = convert_vector_minus(i0, i1, i2, i3, i4, idx);
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if (as_vector_minus) {
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return as_vector_minus;
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}
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return nullptr;
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}
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std::unique_ptr<AtomicOp> convert_vector_float_product(const Instruction& i0,
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const Instruction& i1,
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const Instruction& i2,
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const Instruction& i3,
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const Instruction& i4,
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const Instruction& i5,
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int idx) {
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// lqc2 vf1, 0(vect_in)
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if (i0.kind != InstructionKind::LQC2 || i0.get_dst(0).get_reg() != make_vf(1) ||
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!i0.get_src(0).is_imm(0)) {
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return nullptr;
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}
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Register vec_src = i0.get_src(1).get_reg();
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// mfc1 gpr_temp, float_in
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if (i1.kind != InstructionKind::MFC1) {
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return nullptr;
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}
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Register gpr_temp = i1.get_dst(0).get_reg();
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Register float_src = i1.get_src(0).get_reg();
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// qmtc2.i vf2, gpr_temp
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if (i2.kind != InstructionKind::QMTC2 || i2.get_dst(0).get_reg() != make_vf(2) ||
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i2.get_src(0).get_reg() != gpr_temp) {
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return nullptr;
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}
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// vaddx.w vf1, vf0, vf0
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if (i3.kind != InstructionKind::VADD_BC || i3.get_dst(0).get_reg() != make_vf(1) ||
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i3.get_src(0).get_reg() != make_vf(0) || i3.get_src(1).get_reg() != make_vf(0) ||
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i3.cop2_bc != 0 || i3.cop2_dest != 1) {
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return nullptr;
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}
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// vmulx.xyz vf1, vf1, vf2
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if (i4.kind != InstructionKind::VMUL_BC || i4.get_dst(0).get_reg() != make_vf(1) ||
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i4.get_src(0).get_reg() != make_vf(1) || i4.get_src(1).get_reg() != make_vf(2) ||
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i4.cop2_dest != 14 || i4.cop2_bc != 0) {
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return nullptr;
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}
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// sqc2 vf1, 0(gE)
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if (i5.kind != InstructionKind::SQC2 || i5.get_src(0).get_reg() != make_vf(1) ||
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!i5.get_src(1).is_imm(0)) {
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return nullptr;
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}
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Register dst = i5.get_src(2).get_reg();
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return std::make_unique<SetVarOp>(
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make_dst_var(dst, idx),
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SimpleExpression(SimpleExpression::Kind::VECTOR_FLOAT_PRODUCT, make_src_atom(dst, idx),
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make_src_atom(vec_src, idx), make_src_atom(float_src, idx)),
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idx);
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}
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std::unique_ptr<AtomicOp> convert_6(const Instruction& i0,
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const Instruction& i1,
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const Instruction& i2,
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const Instruction& i3,
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const Instruction& i4,
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const Instruction& i5,
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int idx) {
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auto as_vector_float_product = convert_vector_float_product(i0, i1, i2, i3, i4, i5, idx);
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if (as_vector_float_product) {
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return as_vector_float_product;
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}
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return nullptr;
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}
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@@ -1445,7 +1623,16 @@ int convert_block_to_atomic_ops(int begin_idx,
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warnings.warn_sq_lq();
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}
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if (n_instr >= 5) {
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if (n_instr >= 6) {
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// try 6 instructions
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op = convert_6(instr[0], instr[1], instr[2], instr[3], instr[4], instr[5], op_idx);
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if (op) {
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converted = true;
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length = 6;
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}
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}
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if (!converted && n_instr >= 5) {
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// try 5 instructions
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op = convert_5(instr[0], instr[1], instr[2], instr[3], instr[4], op_idx);
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if (op) {
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