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[decompiler] support break (#516)

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* support break

* finish implementation of break, decomp method 19 of res
This commit is contained in:
water111
2021-05-23 20:16:34 -04:00
committed by GitHub
parent a96710f0c5
commit d719bf5677
22 changed files with 1132 additions and 126 deletions
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test/decompiler/test_FormExpressionBuildLong.cpp
+506
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@@ -2441,3 +2441,509 @@ TEST_F(FormRegressionTest, ExprStringToInt) {
" )";
test_final_function(func, type, expected);
}
TEST_F(FormRegressionTest, Method19ResTag) {
std::string func =
"sll r0, r0, 0\n"
"L101:\n"
" daddiu sp, sp, -16\n"
" sd fp, 8(sp)\n"
" or fp, t9, r0\n"
" daddiu v1, s7, id\n"
" dsubu v1, a1, v1\n"
" daddiu t0, s7, 8\n"
" movn t0, s7, v1\n"
" bnel s7, t0, L102\n"
" or v1, t0, r0\n"
"\n"
" daddiu v1, s7, aid\n"
" dsubu v1, a1, v1\n"
" daddiu t0, s7, 8\n"
" movn t0, s7, v1\n"
" bnel s7, t0, L102\n"
" or v1, t0, r0\n"
"\n"
" daddiu v1, s7, trans\n"
" dsubu v1, a1, v1\n"
" daddiu t0, s7, 8\n"
" movn t0, s7, v1\n"
" bnel s7, t0, L102\n"
" or v1, t0, r0\n"
"\n"
" daddiu v1, s7, rot\n"
" dsubu v1, a1, v1\n"
" daddiu t0, s7, 8\n"
" movn t0, s7, v1\n"
" bnel s7, t0, L102\n"
" or v1, t0, r0\n"
"\n"
" daddiu v1, s7, nav-mesh\n"
" dsubu v1, a1, v1\n"
" daddiu t0, s7, 8\n"
" movn t0, s7, v1\n"
" bnel s7, t0, L102\n"
" or v1, t0, r0\n"
"\n"
" daddiu v1, s7, process-type\n"
" dsubu v1, a1, v1\n"
" daddiu t0, s7, 8\n"
" movn t0, s7, v1\n"
" bnel s7, t0, L102\n"
" or v1, t0, r0\n"
"\n"
" daddiu v1, s7, task\n"
" dsubu t0, a1, v1\n"
" daddiu v1, s7, 8\n"
" movn v1, s7, t0\n"
"L102:\n"
" beq s7, v1, L103\n"
" or v1, s7, r0\n"
"\n"
" sd r0, 2(r0)\n"
" or v1, r0, r0\n"
"L103:\n"
" beql s7, a0, L104\n"
" daddiu v1, s7, 8\n"
"\n"
" beql a0, r0, L104\n"
" daddiu v1, s7, 8\n"
"\n"
" lw v1, 0(a0)\n"
" slt t0, r0, v1\n"
" daddiu v1, s7, 8\n"
" movn v1, s7, t0\n"
"L104:\n"
" beq s7, v1, L105\n"
" or v1, s7, r0\n"
"\n"
" addiu v0, r0, -1\n"
" beq r0, r0, L129\n"
" sll r0, r0, 0\n"
"\n"
" or v1, r0, r0\n"
"L105:\n"
" addiu v1, r0, -1\n"
" addiu t0, r0, -1\n"
" addiu t1, r0, -1\n"
" ori t2, r0, 65336\n"
" daddu t2, t2, a1\n"
"\n"
" lwu t2, 0(t2)\n"
" daddiu t2, t2, 4\n"
" ld t2, 0(t2)\n"
"\n"
" lw t3, 0(a0)\n"
" daddiu t3, t3, -1\n"
" addiu t4, r0, 0\n"
" beq r0, r0, L109\n"
" sll r0, r0, 0\n"
"\n"
"L106:\n"
" dsubu t5, t3, t4\n"
"\n"
" dsra t5, t5, 1\n"
" daddu t5, t4, t5\n"
" ori t6, r0, 65336\n"
" lwu t7, 24(a0)\n"
" dsll t8, t5, 4\n"
" daddu t7, t7, t8\n"
"\n"
" lq t7, 0(t7)\n"
" dsll32 t7, t7, 0\n"
" dsrl32 t7, t7, 0\n"
" daddu t6, t6, t7\n"
"\n"
" lwu t6, 0(t6)\n"
" daddiu t6, t6, 4\n"
" ld t6, 0(t6)\n"
"\n"
" dsubu t6, t2, t6\n"
" bne t6, r0, L107\n"
" sll r0, r0, 0\n"
"\n"
" or t4, t5, r0\n"
" beq r0, r0, L110\n"
" sll r0, r0, 0\n"
"\n"
" or v1, r0, r0\n"
" beq r0, r0, L109\n"
" sll r0, r0, 0\n"
"\n"
"L107:\n"
" slt t6, t6, r0\n"
" beq t6, r0, L108\n"
" sll r0, r0, 0\n"
"\n"
" daddiu t3, t5, -1\n"
" or t5, t3, r0\n"
" beq r0, r0, L109\n"
" sll r0, r0, 0\n"
"\n"
"L108:\n"
" daddiu t4, t5, 1\n"
" or t5, t4, r0\n"
"L109:\n"
" slt t5, t3, t4\n"
"\n"
" beq t5, r0, L106\n"
" sll r0, r0, 0\n"
"\n"
" or t3, s7, r0\n"
" addiu t4, r0, -1\n"
"L110:\n"
" slt t3, t4, r0\n"
" beq t3, r0, L111\n"
" or t3, s7, r0\n"
"\n"
" or v0, t4, r0\n"
" beq r0, r0, L129\n"
" sll r0, r0, 0\n"
"\n"
" or v1, r0, r0\n"
"L111:\n"
" beq r0, r0, L113\n"
" sll r0, r0, 0\n"
"\n"
"L112:\n"
" daddiu t4, t4, -1\n"
"L113:\n"
" slt t3, r0, t4\n"
" daddiu t5, s7, 8\n"
" movz t5, s7, t3\n"
" beql s7, t5, L114\n"
" or t3, t5, r0\n"
"\n"
" ori t3, r0, 65336\n"
" lwu t5, 24(a0)\n"
" daddiu t6, t4, -1\n"
" dsll t6, t6, 4\n"
" daddu t5, t5, t6\n"
"\n"
" lq t5, 0(t5)\n"
" dsll32 t5, t5, 0\n"
" dsrl32 t5, t5, 0\n"
" daddu t3, t3, t5\n"
"\n"
" lwu t3, 0(t3)\n"
" daddiu t3, t3, 4\n"
" ld t3, 0(t3)\n"
"\n"
" dsubu t5, t2, t3\n"
" daddiu t3, s7, 8\n"
" movn t3, s7, t5\n"
"L114:\n"
" bne s7, t3, L112\n"
" sll r0, r0, 0\n"
"\n"
" or t3, s7, r0\n"
" daddiu t3, s7, base\n"
" bne a2, t3, L115\n"
" or t3, s7, r0\n"
"\n"
" or t0, t4, r0\n"
" or v1, t4, r0\n"
" or a0, s7, r0\n"
" beq r0, r0, L128\n"
" sll r0, r0, 0\n"
"\n"
" or v1, r0, r0\n"
"L115:\n"
" or t3, t4, r0\n"
" dsll t4, t4, 4\n"
" daddu t4, r0, t4\n"
" lwu t5, 24(a0)\n"
" daddu t4, t4, t5\n"
"\n"
" beq r0, r0, L126\n"
" sll r0, r0, 0\n"
"\n"
"L116:\n"
" lq t5, 0(t4)\n"
" dsll32 t5, t5, 0\n"
" dsrl32 t5, t5, 0\n"
" beq a1, t5, L117\n"
" or t5, s7, r0\n"
"\n"
" or t5, s7, r0\n"
" beq r0, r0, L125\n"
" sll r0, r0, 0\n"
"\n"
"L117:\n"
" lq t5, 0(t4)\n"
" dsra32 t5, t5, 0\n"
" mtc1 f0, t5\n"
" mtc1 f1, a3\n"
" c.eq.s f0, f1\n"
" bc1f L118\n"
" or t5, s7, r0\n"
"\n"
" or t0, t3, r0\n"
" or v1, t3, r0\n"
" or a0, s7, r0\n"
" beq r0, r0, L128\n"
" sll r0, r0, 0\n"
"\n"
" or v1, r0, r0\n"
" beq r0, r0, L125\n"
" sll r0, r0, 0\n"
"\n"
"L118:\n"
" mtc1 f0, a3\n"
" lq t5, 0(t4)\n"
" dsra32 t5, t5, 0\n"
" mtc1 f1, t5\n"
" c.lt.s f0, f1\n"
" bc1f L119\n"
" daddiu t5, s7, 8\n"
"\n"
" or t5, s7, r0\n"
"L119:\n"
" beql s7, t5, L120\n"
" or t5, t5, r0\n"
"\n"
" daddiu t5, s7, exact\n"
" dsubu t6, a2, t5\n"
" daddiu t5, s7, 8\n"
" movz t5, s7, t6\n"
"L120:\n"
" beq s7, t5, L122\n"
" or t5, s7, r0\n"
"\n"
" or t0, t3, r0\n"
" or v1, t3, r0\n"
" lq t5, 0(t4)\n"
" dsra32 t5, t5, 0\n"
" mtc1 f0, t5\n"
//" lwc1 f1, L147(fp)\n"
" mtc1 f1, r0\n"
" c.eq.s f0, f1\n"
" bc1f L121\n"
" or t5, s7, r0\n"
"\n"
" or t1, t3, r0\n"
" or t5, t1, r0\n"
"L121:\n"
" beq r0, r0, L125\n"
" sll r0, r0, 0\n"
"\n"
"L122:\n"
" mtc1 f0, a3\n"
" lq t5, 0(t4)\n"
" dsra32 t5, t5, 0\n"
" mtc1 f1, t5\n"
" c.lt.s f0, f1\n"
" bc1f L125\n"
" or t5, s7, r0\n"
"\n"
" dsubu a0, t0, t1\n"
"\n"
" daddiu a1, s7, 8\n"
" movz a1, s7, a0\n"
" beql s7, a1, L123\n"
" or a0, a1, r0\n"
"\n"
" daddiu a0, s7, interp\n"
" dsubu a1, a2, a0\n"
" daddiu a0, s7, 8\n"
" movn a0, s7, a1\n"
"L123:\n"
" beq s7, a0, L124\n"
" or a0, s7, r0\n"
"\n"
" or v1, t3, r0\n"
" or a0, v1, r0\n"
"L124:\n"
" or a0, s7, r0\n"
" beq r0, r0, L128\n"
" sll r0, r0, 0\n"
"\n"
" or v1, r0, r0\n"
"L125:\n"
" daddiu t3, t3, 1\n"
" daddiu t4, t4, 16\n"
"L126:\n"
" lw t5, 0(a0)\n"
" slt t5, t3, t5\n"
" daddiu t6, s7, 8\n"
" movn t6, s7, t5\n"
" bnel s7, t6, L127\n"
" or t5, t6, r0\n"
"\n"
" ori t5, r0, 65336\n"
" lq t6, 0(t4)\n"
" dsll32 t6, t6, 0\n"
" dsrl32 t6, t6, 0\n"
" daddu t5, t5, t6\n"
"\n"
" lwu t5, 0(t5)\n"
" daddiu t5, t5, 4\n"
" ld t5, 0(t5)\n"
"\n"
" sltu t6, t2, t5\n"
" daddiu t5, s7, 8\n"
" movz t5, s7, t6\n"
"L127:\n"
" beq s7, t5, L116\n"
" sll r0, r0, 0\n"
"\n"
" or a0, s7, r0\n"
" or a0, s7, r0\n"
"L128:\n"
//" ld a0, L150(fp)\n"
" or a0, r0, r0\n"
" and a0, a0, t0\n"
" dsll32 v1, v1, 0\n"
" or v0, a0, v1\n"
"\n"
"L129:\n"
" ld fp, 8(sp)\n"
" jr ra\n"
" daddiu sp, sp, 16";
std::string type = "(function res-lump symbol symbol float int)";
std::string expected =
"(begin\n"
" (when\n"
" (or\n"
" (= arg1 'id)\n"
" (= arg1 'aid)\n"
" (= arg1 'trans)\n"
" (= arg1 'rot)\n"
" (= arg1 'nav-mesh)\n"
" (= arg1 'process-type)\n"
" (= arg1 'task)\n"
" )\n"
" (crash!)\n"
" (let ((v1-9 0))\n"
" )\n"
" )\n"
" (if (or (not arg0) (zero? arg0) (<= (-> arg0 length) 0))\n"
" (return -1)\n"
" )\n"
" (let ((v1-14 -1)\n"
" (t0-6 -1)\n"
" )\n"
" (let ((t1-0 -1)\n"
" (t2-4 (-> (the-as (pointer uint64) (-> (symbol->string arg1) data)) 0))\n"
" )\n"
" (let ((t3-1 (+ (-> arg0 length) -1))\n"
" (t4-0 0)\n"
" )\n"
" (while (>= t3-1 t4-0)\n"
" (let* ((t5-2 (+ t4-0 (/ (- t3-1 t4-0) 2)))\n"
" (t6-5\n"
" (-\n"
" t2-4\n"
" (->\n"
" (the-as\n"
" (pointer uint64)\n"
" (-> (symbol->string (-> (-> arg0 tag) t5-2 name)) data)\n"
" )\n"
" 0\n"
" )\n"
" )\n"
" )\n"
" )\n"
" (cond\n"
" ((zero? t6-5)\n"
" (begin\n"
" (set! t4-1 t5-2)\n"
" (goto cfg-32)\n"
" )\n"
" )\n"
" (else\n"
" (if (< (the-as int t6-5) 0)\n"
" (set! t3-1 (+ t5-2 -1))\n"
" (set! t4-0 (+ t5-2 1))\n"
" )\n"
" )\n"
" )\n"
" )\n"
" )\n"
" )\n"
" (set! t4-1 -1)\n"
" (label cfg-32)\n"
" (if (< t4-1 0)\n"
" (return t4-1)\n"
" )\n"
" (while\n"
" (and\n"
" (> t4-1 0)\n"
" (=\n"
" t2-4\n"
" (->\n"
" (the-as\n"
" (pointer uint64)\n"
" (-> (symbol->string (-> (-> arg0 tag) (+ t4-1 -1) name)) data)\n"
" )\n"
" 0\n"
" )\n"
" )\n"
" )\n"
" (+! t4-1 -1)\n"
" )\n"
" (if (= arg2 'base)\n"
" (begin\n"
" (set! t0-6 t4-1)\n"
" (set! v1-14 t4-1)\n"
" (goto cfg-73)\n"
" )\n"
" )\n"
" (let ((t3-13 t4-1)\n"
" (t4-4 (&-> (-> arg0 tag) t4-1))\n"
" )\n"
" (while\n"
" (not\n"
" (or\n"
" (>= t3-13 (-> arg0 length))\n"
" (<\n"
" t2-4\n"
" (->\n"
" (the-as (pointer uint64) (-> (symbol->string (-> t4-4 0 name)) data))\n"
" 0\n"
" )\n"
" )\n"
" )\n"
" )\n"
" (cond\n"
" ((!= arg1 (-> t4-4 0 name))\n"
" )\n"
" ((= (-> t4-4 0 key-frame) arg3)\n"
" (begin\n"
" (set! t0-6 t3-13)\n"
" (set! v1-14 t3-13)\n"
" (goto cfg-73)\n"
" )\n"
" )\n"
" ((and (>= arg3 (-> t4-4 0 key-frame)) (!= arg2 'exact))\n"
" (set! t0-6 t3-13)\n"
" (set! v1-14 t3-13)\n"
" (if (= (-> t4-4 0 key-frame) 0.0)\n"
" (set! t1-0 t3-13)\n"
" )\n"
" )\n"
" ((< arg3 (-> t4-4 0 key-frame))\n"
" (begin\n"
" (if (and (!= t0-6 t1-0) (= arg2 'interp))\n"
" (set! v1-14 t3-13)\n"
" )\n"
" (goto cfg-73)\n"
" )\n"
" )\n"
" )\n"
" (+! t3-13 1)\n"
" (set! t4-4 (&-> t4-4 1))\n"
" )\n"
" )\n"
" )\n"
" (label cfg-73)\n"
" (logior (logand 0 t0-6) (shl v1-14 32))\n"
" )\n"
" )";
test_with_expr(func, type, expected, false, "", {},
"[\n"
" [46, \"t2\", \"(pointer uint64)\"],\n"
" [100, \"t3\", \"(pointer uint64)\"],\n"
" [184, \"t5\", \"(pointer uint64)\"],\n"
" [64, \"t6\", \"(pointer uint64)\"]\n"
" ]");
}