mirror of
https://github.com/open-goal/jak-project
synced 2026-06-11 05:08:53 -04:00
[Decompiler] bitfield support and clean up of DMA (#350)
* get to vif * support basic bitfield access * make bitfields in dma work * clean up dma * fix merge conflict
This commit is contained in:
water111
@@ -325,4 +325,467 @@ TEST_F(FormRegressionTest, IterateProcessTree) {
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" s4-0\n"
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" )";
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test_with_stack_vars(func, type, expected, "[]");
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}
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TEST_F(FormRegressionTest, InspectVifStatBitfield) {
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std::string func =
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"sll r0, r0, 0\n"
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" daddiu sp, sp, -32\n"
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" sd ra, 0(sp)\n"
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" sd fp, 8(sp)\n"
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" or fp, t9, r0\n"
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" sq gp, 16(sp)\n"
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" or gp, a0, r0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L37\n"
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" or a2, gp, r0\n"
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" daddiu a3, s7, vif-stat\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L36\n"
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" dsll32 v1, gp, 30\n"
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" dsrl32 a2, v1, 30\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L35\n"
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" dsll32 v1, gp, 29\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L34\n"
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" dsll32 v1, gp, 25\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L33\n"
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" dsll32 v1, gp, 23\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L32\n"
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" dsll32 v1, gp, 22\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L31\n"
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" dsll32 v1, gp, 21\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L30\n"
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" dsll32 v1, gp, 20\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L29\n"
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" dsll32 v1, gp, 19\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L28\n"
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" dsll32 v1, gp, 18\n"
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" dsrl32 a2, v1, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L27\n"
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" dsll32 v1, gp, 4\n"
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" dsrl32 a2, v1, 28\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" or v0, gp, r0\n"
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" ld ra, 0(sp)\n"
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" ld fp, 8(sp)\n"
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" lq gp, 16(sp)\n"
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" jr ra\n"
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" daddiu sp, sp, 32";
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std::string type = "(function vif-stat vif-stat)";
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std::string expected =
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"(begin\n"
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" (format #t \"[~8x] ~A~%\" arg0 (quote vif-stat))\n"
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" (format #t \"~T ~D~%\" (-> arg0 vps))\n"
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" (format #t \"~T ~D~%\" (-> arg0 vew))\n"
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" (format #t \"~T ~D~%\" (-> arg0 mrk))\n"
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" (format #t \"~T ~D~%\" (-> arg0 vss))\n"
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" (format #t \"~T ~D~%\" (-> arg0 vfs))\n"
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" (format #t \"~T ~D~%\" (-> arg0 vis))\n"
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" (format #t \"~T ~D~%\" (-> arg0 int))\n"
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" (format #t \"~T ~D~%\" (-> arg0 er0))\n"
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" (format #t \"~T ~D~%\" (-> arg0 er1))\n"
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" (format #t \"~T ~D~%\" (-> arg0 fqc))\n"
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" arg0\n"
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" )";
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test_with_expr(func, type, expected, false, "",
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{{"L37", "[~8x] ~A~%"},
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{"L36", "~T ~D~%"},
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{"L35", "~T ~D~%"},
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{"L34", "~T ~D~%"},
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{"L33", "~T ~D~%"},
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{"L32", "~T ~D~%"},
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{"L31", "~T ~D~%"},
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{"L30", "~T ~D~%"},
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{"L29", "~T ~D~%"},
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{"L28", "~T ~D~%"},
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{"L27", "~T ~D~%"}});
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}
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TEST_F(FormRegressionTest, InspectHandleBitfield) {
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std::string func =
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"sll r0, r0, 0\n"
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" daddiu sp, sp, -32\n"
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" sd ra, 0(sp)\n"
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" sd fp, 8(sp)\n"
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" or fp, t9, r0\n"
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" sq gp, 16(sp)\n"
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" or gp, a0, r0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L79\n"
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" or a2, gp, r0\n"
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" daddiu a3, s7, handle\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L32\n"
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" dsll32 v1, gp, 0\n"
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" dsrl32 a2, v1, 0\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L31\n"
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" dsra32 a2, gp, 0\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" or v0, gp, r0\n"
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" ld ra, 0(sp)\n"
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" ld fp, 8(sp)\n"
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" lq gp, 16(sp)\n"
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" jr ra\n"
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" daddiu sp, sp, 32";
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std::string type = "(function handle handle)";
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std::string expected =
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"(begin\n"
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" (format #t \"[~8x] ~A~%\" arg0 (quote handle))\n"
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" (format #t \"~Tprocess: #x~X~%\" (-> arg0 process))\n"
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" (format #t \"~Tpid: ~D~%\" (-> arg0 pid))\n"
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" arg0\n"
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" )";
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test_with_expr(func, type, expected, false, "",
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{{"L79", "[~8x] ~A~%"}, {"L32", "~Tprocess: #x~X~%"}, {"L31", "~Tpid: ~D~%"}});
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}
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TEST_F(FormRegressionTest, InspectDmaTagBitfield) {
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std::string func =
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"sll r0, r0, 0\n"
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" daddiu sp, sp, -32\n"
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" sd ra, 0(sp)\n"
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" sd fp, 8(sp)\n"
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" or fp, t9, r0\n"
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" sq gp, 16(sp)\n"
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" or gp, a0, r0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L65\n"
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" or a2, gp, r0\n"
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" daddiu a3, s7, dma-tag\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L37\n"
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" dsll32 v1, gp, 16\n"
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" dsrl32 a2, v1, 16\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L36\n"
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" dsll32 v1, gp, 4\n"
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" dsrl32 a2, v1, 30\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L35\n"
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" dsll32 v1, gp, 1\n"
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" dsrl32 a2, v1, 29\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L34\n"
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" srl a2, gp, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L33\n"
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" dsll v1, gp, 1\n"
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" dsrl32 a2, v1, 1\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, format(s7)\n"
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" daddiu a0, s7, #t\n"
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" daddiu a1, fp, L32\n"
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" dsrl32 a2, gp, 31\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" or v0, gp, r0\n"
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" ld ra, 0(sp)\n"
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" ld fp, 8(sp)\n"
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" lq gp, 16(sp)\n"
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" jr ra\n"
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" daddiu sp, sp, 32";
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std::string type = "(function dma-tag dma-tag)";
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std::string expected =
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"(begin\n"
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" (format #t \"[~8x] ~A~%\" arg0 (quote dma-tag))\n"
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" (format #t \"~Ta: ~D~%\" (-> arg0 qwc))\n"
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" (format #t \"~Ta: ~D~%\" (-> arg0 pce))\n"
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" (format #t \"~Ta: ~D~%\" (-> arg0 id))\n"
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" (format #t \"~Ta: ~D~%\" (-> arg0 irq))\n"
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" (format #t \"~Ta: ~D~%\" (-> arg0 addr))\n"
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" (format #t \"~Ta: ~D~%\" (-> arg0 spr))\n"
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" arg0\n"
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" )";
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test_with_expr(func, type, expected, false, "",
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{
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{"L65", "[~8x] ~A~%"},
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{"L37", "~Ta: ~D~%"},
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{"L36", "~Ta: ~D~%"},
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{"L35", "~Ta: ~D~%"},
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{"L34", "~Ta: ~D~%"},
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{"L33", "~Ta: ~D~%"},
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{"L32", "~Ta: ~D~%"},
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});
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}
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// Tests nonzero-check on bitfield
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TEST_F(FormRegressionTest, DmaSyncCrash) {
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std::string func =
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"sll r0, r0, 0\n"
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"L46:\n"
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" lui v1, 76\n"
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" ori v1, v1, 19264\n"
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" beq r0, r0, L49\n"
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" sll r0, r0, 0\n"
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"L47:\n"
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" bne v1, r0, L48\n"
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" sll r0, r0, 0\n"
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" sd r0, 2(r0)\n"
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" or a1, r0, r0\n"
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" beq r0, r0, L49\n"
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" sll r0, r0, 0\n"
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"L48:\n"
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" daddiu v1, v1, -1\n"
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" or a1, v1, r0\n"
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"L49:\n"
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" lwu a1, 0(a0)\n"
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" andi a1, a1, 256\n"
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" bne a1, r0, L47\n"
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" sll r0, r0, 0\n"
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" or v1, s7, r0\n"
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" or v0, r0, r0\n"
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" jr ra\n"
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" daddu sp, sp, r0";
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std::string type = "(function dma-bank int)";
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std::string expected =
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"(begin\n"
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" (let ((v1-0 #x4c4b40))\n"
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" (while (nonzero? (-> arg0 chcr str))\n"
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" (cond\n"
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" ((zero? v1-0)\n"
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" (crash!)\n"
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" (let ((a1-0 0))\n"
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" )\n"
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" )\n"
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" (else\n"
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" (+! v1-0 -1)\n"
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" )\n"
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" )\n"
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" )\n"
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" )\n"
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" 0\n"
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" )";
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test_with_expr(func, type, expected);
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}
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TEST_F(FormRegressionTest, DmaSend) {
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std::string func =
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"sll r0, r0, 0\n"
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" daddiu sp, sp, -64\n"
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" sd ra, 0(sp)\n"
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" sq s4, 16(sp)\n"
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" sq s5, 32(sp)\n"
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" sq gp, 48(sp)\n"
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" or gp, a0, r0\n"
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" or s4, a1, r0\n"
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" or s5, a2, r0\n"
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" lw t9, dma-sync(s7)\n"
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" or a0, gp, r0\n"
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" addiu a1, r0, 0\n"
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" addiu a2, r0, 0\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" lw t9, flush-cache(s7)\n"
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" addiu a0, r0, 0\n"
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" jalr ra, t9\n"
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" sll v0, ra, 0\n"
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" sync.l\n"
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" lui v1, 4095\n"
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" ori v1, v1, 65535\n"
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" and v1, v1, s4\n"
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" lui a0, 28672\n"
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" lui a1, 28672\n"
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" and a1, a1, s4\n"
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" bne a1, a0, L44\n"
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" sll r0, r0, 0\n"
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" ori a0, r0, 32768\n"
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" dsll a0, a0, 16\n"
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" beq r0, r0, L45\n"
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" sll r0, r0, 0\n"
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"L44:\n"
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" addiu a0, r0, 0\n"
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"L45:\n"
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" or v1, v1, a0\n"
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" sw v1, 16(gp)\n"
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" sw s5, 32(gp)\n"
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" sync.l\n"
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" addiu v1, r0, 256\n"
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" sw v1, 0(gp)\n"
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" sync.l\n"
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" or v0, r0, r0\n"
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" ld ra, 0(sp)\n"
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" lq gp, 48(sp)\n"
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" lq s5, 32(sp)\n"
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" lq s4, 16(sp)\n"
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" jr ra\n"
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" daddiu sp, sp, 64";
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std::string type = "(function dma-bank uint uint int)";
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std::string expected =
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"(begin\n"
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" (dma-sync (the-as pointer arg0) 0 0)\n"
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" (flush-cache 0)\n"
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" (.sync.l)\n"
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" (set!\n"
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" (-> arg0 madr)\n"
|
||||
" (logior\n"
|
||||
" (logand #xfffffff (the-as int arg1))\n"
|
||||
" (the-as uint (if (= (logand #x70000000 (the-as int arg1)) #x70000000)\n"
|
||||
" (shl #x8000 16)\n" // note: maybe this should be #x80000000? Not sure.
|
||||
" 0\n"
|
||||
" )\n"
|
||||
" )\n"
|
||||
" )\n"
|
||||
" )\n"
|
||||
" (set! (-> arg0 qwc) arg2)\n"
|
||||
" (.sync.l)\n"
|
||||
" (set! (-> arg0 chcr) (new 'static 'dma-chcr :str 1))\n"
|
||||
" (.sync.l)\n"
|
||||
" 0\n"
|
||||
" )";
|
||||
test_with_expr(func, type, expected);
|
||||
}
|
||||
|
||||
TEST_F(FormRegressionTest, DmaInitialize) {
|
||||
std::string func =
|
||||
"sll r0, r0, 0\n"
|
||||
" lui v1, 4096\n"
|
||||
" ori v1, v1, 14336\n"
|
||||
" lwu v1, 32(v1)\n"
|
||||
" addiu a0, r0, -3\n"
|
||||
" and v1, v1, a0\n"
|
||||
" ori v1, v1, 2\n"
|
||||
" lui a0, 4096\n"
|
||||
" ori a0, a0, 14336\n"
|
||||
" sw v1, 32(a0)\n"
|
||||
" lui v1, 4096\n"
|
||||
" ori v1, v1, 15360\n"
|
||||
" lwu v1, 32(v1)\n"
|
||||
" addiu a0, r0, -3\n"
|
||||
" and v1, v1, a0\n"
|
||||
" ori v1, v1, 2\n"
|
||||
" lui a0, 4096\n"
|
||||
" ori a0, a0, 15360\n"
|
||||
" sw v1, 32(a0)\n"
|
||||
" or v0, r0, r0\n"
|
||||
" jr ra\n"
|
||||
" daddu sp, sp, r0";
|
||||
std::string type = "(function int)";
|
||||
std::string expected =
|
||||
"(begin\n"
|
||||
" (set! (-> (the-as vif-bank #x10003800) err me0) 1)\n"
|
||||
" (set! (-> (the-as vif-bank #x10003c00) err me0) 1)\n"
|
||||
" 0\n"
|
||||
" )";
|
||||
test_with_expr(func, type, expected, false, "", {},
|
||||
"[[1, \"v1\", \"vif-bank\"], [8, \"v1\", \"vif-bank\"], [6, \"a0\", "
|
||||
"\"vif-bank\"], [13, \"a0\", \"vif-bank\"]]");
|
||||
}
|
||||
Reference in New Issue
Block a user