Got OpenGOAL building and running natively on Apple Silicon.
This is the rest of the port after the smaller arm64 emitter PRs. I was
told pushing one big PR was okay. This covers goalc, the runtime,
linker, kernel and the GOAL asm.
The new paths have native tests. I also found four more emitter bugs
while running it. They're in scalar sqrt, 128-bit stores, scalar max and
indexed stores above 4 GB.
Spent a while cleaning it up so it's easier to read. 4am gotta sleep lol
Closes#3841
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Co-authored-by: Tyler Wilding <xtvaser@gmail.com>
Some neon tests, plus the fix they needed to run at all.
`ldr q` and `str q` with a register offset had a bad option field so
they don't
decode. The s8 load was ignoring addr2 and reading from the base on its
own. A
few used post indexed forms, which move the address register.
Rest of the avx list to come.
Alters the opcode constants and the lane index maths, so the pext,
vector shift, shuffle, blend and splat helpers now emit the correct
ZIP1/ZIP2, SHL/SSHR/USHR, INS and DUP machine encodings for 128-bit
vector operations.
Adds an Imm5 field helper, which the lane-insert and duplicate encodings
need.
Follows #4384, from the same Apple Silicon work.
Alters the opcode constants in Base, so these helpers now emit the
correct FADD/FMAX/FMIN machine encodings for 4×f32 vector operations.
Found these while getting OpenGOAL running natively on Apple Silicon.
- Adds `capstone` as a disassembling library that could eventually
replace Zydis (for now left that alone)
- Replicates all of the existing x86 tests to ARM64, fixed a bunch of
underlying issues along the way
- There are a very small handful of tests remaining that need to be
enabled / fixed
All that remains (8 instructions) are division, and NEON instructions
that require me to convert the x86 control byte to NEON `TBL` values.
Those handful of instructions can be done later while doing the next
steps (finally something more interesting than just encoding
instructions).
Less than 100 instructions left to implement, with the vast vast
majority being load-and-stores. These will likely be knocked out quickly
but they require a more involved implementation than just simply
translating the instructions (several need multiple instructions, others
may need reserved registers (x16 or x17 are common for this purpose))
This is a good milestone to get something pushed to master.
This PR does the following:
- Designs a mechanism by which arm64 instructions can be encoded and
emitted
- Dispatch our higher-level instruction emitting calls to either x86 or
arm64 instructions depending on what the compiler is set to (defaults to
x86)
- Bare minimum scaffolding to get the arm64 instructions successfully
executing atleast on apple silicon
- Implement enough instructions to get the codetester test suite passing
on arm
Jordan