mirror of
https://github.com/open-goal/jak-project
synced 2026-08-24 07:30:24 -04:00
Tyler Wilding
bfc4c18ada
- Adds `capstone` as a disassembling library that could eventually replace Zydis (for now left that alone) - Replicates all of the existing x86 tests to ARM64, fixed a bunch of underlying issues along the way - There are a very small handful of tests remaining that need to be enabled / fixed
130 lines
3.2 KiB
C
Vendored
Generated
130 lines
3.2 KiB
C
Vendored
Generated
/* Capstone Disassembly Engine */
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/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
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#ifdef CAPSTONE_HAS_ALPHA
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#include <platform.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "../../utils.h"
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#include "../../Mapping.h"
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#include "../../MCInstPrinter.h"
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#include "AlphaLinkage.h"
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#include "AlphaMapping.h"
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static const char *getRegisterName(unsigned RegNo);
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static void printInstruction(MCInst *, uint64_t, SStream *);
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static void printOperand(MCInst *MI, int OpNum, SStream *O);
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static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum,
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SStream *O);
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#define GET_INSTRINFO_ENUM
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#include "AlphaGenInstrInfo.inc"
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#define GET_REGINFO_ENUM
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#include "AlphaGenRegisterInfo.inc"
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static void printOperand(MCInst *MI, int OpNum, SStream *O)
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{
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if (OpNum >= MI->size)
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return;
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Alpha_add_cs_detail(MI, OpNum);
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MCOperand *Op;
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Op = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isReg(Op)) {
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unsigned reg = MCOperand_getReg(Op);
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SStream_concat(O, "%s", getRegisterName(reg));
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} else if (MCOperand_isImm(Op)) {
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int64_t Imm = MCOperand_getImm(Op);
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if (Imm >= 0) {
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if (Imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%" PRIx64, Imm);
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else
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SStream_concat(O, "%" PRIu64, Imm);
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} else {
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if (Imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%" PRIx64, -Imm);
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else
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SStream_concat(O, "-%" PRIu64, -Imm);
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}
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}
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}
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static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum,
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SStream *O)
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{
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MCOperand *Op = MCInst_getOperand(MI, (OpNum));
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uint64_t Imm = MCOperand_getImm(Op);
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uint64_t Target = Address + 4 + (int16_t)(Imm << 2);
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Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, Target);
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printUInt64(O, Target);
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}
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#define PRINT_ALIAS_INSTR
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#include "AlphaGenAsmWriter.inc"
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const char *ALPHA_LLVM_getRegisterName(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return getRegisterName(id);
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#else
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return NULL;
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#endif
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}
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void ALPHA_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info)
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{
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unsigned Opcode = MCInst_getOpcode(MI);
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/*
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* The generated AsmWriter hardcodes "$31" for BR and restricts BSR to
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* Ra=26. Format 27 now decodes Ra as operand[0] and disp21 as
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* operand[1], so we must print them explicitly here.
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*/
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if (Opcode == ALPHA_COND_BRANCH_I) {
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SStream_concat0(O, "call_pal ");
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printOperand(MI, 0, O);
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return;
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}
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/*
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* JMP/JSR/JSRs now decode with format 18 (Ra + Rb + hint14).
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* The generated AsmWriter hardcodes operands for specific canonical
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* forms, so print all three operands explicitly here.
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*/
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if (Opcode == ALPHA_JMP || Opcode == ALPHA_JSR ||
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Opcode == ALPHA_JSRs || Opcode == ALPHA_RETDAG) {
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const char *name = (Opcode == ALPHA_JMP) ? "jmp " :
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(Opcode == ALPHA_RETDAG) ? "ret " :
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"jsr ";
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SStream_concat0(O, name);
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printOperand(MI, 0, O);
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SStream_concat1(O, ',');
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SStream_concat1(O, '(');
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printOperand(MI, 1, O);
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SStream_concat1(O, ')');
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SStream_concat1(O, ',');
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printOperand(MI, 2, O);
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return;
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}
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if (Opcode == ALPHA_BR || Opcode == ALPHA_BSR) {
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SStream_concat0(O, Opcode == ALPHA_BR ? "br " : "bsr ");
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printOperand(MI, 0, O);
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SStream_concat1(O, ',');
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printOperandAddr(MI, MI->address, 1, O);
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return;
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}
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printAliasInstr(MI, MI->address, O);
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printInstruction(MI, MI->address, O);
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}
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#endif |