mirror of
https://github.com/open-goal/jak-project
synced 2026-08-25 15:55:52 -04:00
Tyler Wilding
bfc4c18ada
- Adds `capstone` as a disassembling library that could eventually replace Zydis (for now left that alone) - Replicates all of the existing x86 tests to ARM64, fixed a bunch of underlying issues along the way - There are a very small handful of tests remaining that need to be enabled / fixed
34193 lines
1.9 MiB
Plaintext
Vendored
Generated
34193 lines
1.9 MiB
Plaintext
Vendored
Generated
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#ifdef GET_RISCVMaskedPseudosTable_DECL
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const RISCV_RISCVMaskedPseudoInfo *RISCV_getMaskedPseudoInfo(unsigned MaskedPseudo);
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const RISCV_RISCVMaskedPseudoInfo *RISCV_lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo);
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#endif
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#ifdef GET_RISCVOpcodesList_DECL
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const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByValue(uint8_t Value);
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const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByName(const char * Name);
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#endif
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#ifdef GET_RISCVTuneInfoTable_DECL
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const RISCV_RISCVTuneInfo *RISCV_getRISCVTuneInfo(const char * Name);
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#endif
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#ifdef GET_RISCVVInversePseudosTable_DECL
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const RISCV_PseudoInfo *RISCV_getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW);
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#endif
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#ifdef GET_RISCVVLETable_DECL
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const RISCV_VLEPseudo *RISCV_getVLEPseudo(uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL);
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#endif
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#ifdef GET_RISCVVLSEGTable_DECL
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const RISCV_VLSEGPseudo *RISCV_getVLSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL);
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#endif
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#ifdef GET_RISCVVLXSEGTable_DECL
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const RISCV_VLXSEGPseudo *RISCV_getVLXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL);
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#endif
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#ifdef GET_RISCVVLXTable_DECL
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const RISCV_VLX_VSXPseudo *RISCV_getVLXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL);
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#endif
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#ifdef GET_RISCVVPseudosTable_DECL
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const RISCV_PseudoInfo *RISCV_getPseudoInfo(unsigned Pseudo);
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#endif
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#ifdef GET_RISCVVSETable_DECL
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const RISCV_VSEPseudo *RISCV_getVSEPseudo(uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL);
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#endif
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#ifdef GET_RISCVVSSEGTable_DECL
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const RISCV_VSSEGPseudo *RISCV_getVSSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL);
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#endif
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#ifdef GET_RISCVVSXSEGTable_DECL
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const RISCV_VSXSEGPseudo *RISCV_getVSXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL);
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#endif
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#ifdef GET_RISCVVSXTable_DECL
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const RISCV_VLX_VSXPseudo *RISCV_getVSXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL);
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#endif
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#ifdef GET_SysRegsList_DECL
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const RISCV_SysReg *RISCV_lookupSysRegByEncoding(uint16_t Encoding);
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const RISCV_SysReg *RISCV_lookupSysRegByAltName(const char * AltName);
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const RISCV_SysReg *RISCV_lookupSysRegByDeprecatedName(const char * DeprecatedName);
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const RISCV_SysReg *RISCV_lookupSysRegByName(const char * Name);
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#endif
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#ifdef GET_RISCVMaskedPseudosTable_IMPL
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static const RISCV_RISCVMaskedPseudoInfo RISCVMaskedPseudosTable[] = {
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{ PseudoTHVdotVMAQASU_VV_M1_MASK, PseudoTHVdotVMAQASU_VV_M1, 0x3, false }, // 0
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{ PseudoTHVdotVMAQASU_VV_M2_MASK, PseudoTHVdotVMAQASU_VV_M2, 0x3, false }, // 1
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{ PseudoTHVdotVMAQASU_VV_M4_MASK, PseudoTHVdotVMAQASU_VV_M4, 0x3, false }, // 2
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{ PseudoTHVdotVMAQASU_VV_M8_MASK, PseudoTHVdotVMAQASU_VV_M8, 0x3, false }, // 3
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{ PseudoTHVdotVMAQASU_VV_MF2_MASK, PseudoTHVdotVMAQASU_VV_MF2, 0x3, false }, // 4
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{ PseudoTHVdotVMAQASU_VX_M1_MASK, PseudoTHVdotVMAQASU_VX_M1, 0x3, false }, // 5
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{ PseudoTHVdotVMAQASU_VX_M2_MASK, PseudoTHVdotVMAQASU_VX_M2, 0x3, false }, // 6
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{ PseudoTHVdotVMAQASU_VX_M4_MASK, PseudoTHVdotVMAQASU_VX_M4, 0x3, false }, // 7
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{ PseudoTHVdotVMAQASU_VX_M8_MASK, PseudoTHVdotVMAQASU_VX_M8, 0x3, false }, // 8
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{ PseudoTHVdotVMAQASU_VX_MF2_MASK, PseudoTHVdotVMAQASU_VX_MF2, 0x3, false }, // 9
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{ PseudoTHVdotVMAQAUS_VX_M1_MASK, PseudoTHVdotVMAQAUS_VX_M1, 0x3, false }, // 10
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{ PseudoTHVdotVMAQAUS_VX_M2_MASK, PseudoTHVdotVMAQAUS_VX_M2, 0x3, false }, // 11
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{ PseudoTHVdotVMAQAUS_VX_M4_MASK, PseudoTHVdotVMAQAUS_VX_M4, 0x3, false }, // 12
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{ PseudoTHVdotVMAQAUS_VX_M8_MASK, PseudoTHVdotVMAQAUS_VX_M8, 0x3, false }, // 13
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{ PseudoTHVdotVMAQAUS_VX_MF2_MASK, PseudoTHVdotVMAQAUS_VX_MF2, 0x3, false }, // 14
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{ PseudoTHVdotVMAQAU_VV_M1_MASK, PseudoTHVdotVMAQAU_VV_M1, 0x3, false }, // 15
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{ PseudoTHVdotVMAQAU_VV_M2_MASK, PseudoTHVdotVMAQAU_VV_M2, 0x3, false }, // 16
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{ PseudoTHVdotVMAQAU_VV_M4_MASK, PseudoTHVdotVMAQAU_VV_M4, 0x3, false }, // 17
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{ PseudoTHVdotVMAQAU_VV_M8_MASK, PseudoTHVdotVMAQAU_VV_M8, 0x3, false }, // 18
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{ PseudoTHVdotVMAQAU_VV_MF2_MASK, PseudoTHVdotVMAQAU_VV_MF2, 0x3, false }, // 19
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{ PseudoTHVdotVMAQAU_VX_M1_MASK, PseudoTHVdotVMAQAU_VX_M1, 0x3, false }, // 20
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{ PseudoTHVdotVMAQAU_VX_M2_MASK, PseudoTHVdotVMAQAU_VX_M2, 0x3, false }, // 21
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{ PseudoTHVdotVMAQAU_VX_M4_MASK, PseudoTHVdotVMAQAU_VX_M4, 0x3, false }, // 22
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{ PseudoTHVdotVMAQAU_VX_M8_MASK, PseudoTHVdotVMAQAU_VX_M8, 0x3, false }, // 23
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{ PseudoTHVdotVMAQAU_VX_MF2_MASK, PseudoTHVdotVMAQAU_VX_MF2, 0x3, false }, // 24
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{ PseudoTHVdotVMAQA_VV_M1_MASK, PseudoTHVdotVMAQA_VV_M1, 0x3, false }, // 25
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{ PseudoTHVdotVMAQA_VV_M2_MASK, PseudoTHVdotVMAQA_VV_M2, 0x3, false }, // 26
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{ PseudoTHVdotVMAQA_VV_M4_MASK, PseudoTHVdotVMAQA_VV_M4, 0x3, false }, // 27
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{ PseudoTHVdotVMAQA_VV_M8_MASK, PseudoTHVdotVMAQA_VV_M8, 0x3, false }, // 28
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{ PseudoTHVdotVMAQA_VV_MF2_MASK, PseudoTHVdotVMAQA_VV_MF2, 0x3, false }, // 29
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{ PseudoTHVdotVMAQA_VX_M1_MASK, PseudoTHVdotVMAQA_VX_M1, 0x3, false }, // 30
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{ PseudoTHVdotVMAQA_VX_M2_MASK, PseudoTHVdotVMAQA_VX_M2, 0x3, false }, // 31
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{ PseudoTHVdotVMAQA_VX_M4_MASK, PseudoTHVdotVMAQA_VX_M4, 0x3, false }, // 32
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{ PseudoTHVdotVMAQA_VX_M8_MASK, PseudoTHVdotVMAQA_VX_M8, 0x3, false }, // 33
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{ PseudoTHVdotVMAQA_VX_MF2_MASK, PseudoTHVdotVMAQA_VX_MF2, 0x3, false }, // 34
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{ PseudoVAADDU_VV_M1_MASK, PseudoVAADDU_VV_M1, 0x3, false }, // 35
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{ PseudoVAADDU_VV_M2_MASK, PseudoVAADDU_VV_M2, 0x3, false }, // 36
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{ PseudoVAADDU_VV_M4_MASK, PseudoVAADDU_VV_M4, 0x3, false }, // 37
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{ PseudoVAADDU_VV_M8_MASK, PseudoVAADDU_VV_M8, 0x3, false }, // 38
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{ PseudoVAADDU_VV_MF2_MASK, PseudoVAADDU_VV_MF2, 0x3, false }, // 39
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{ PseudoVAADDU_VV_MF4_MASK, PseudoVAADDU_VV_MF4, 0x3, false }, // 40
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{ PseudoVAADDU_VV_MF8_MASK, PseudoVAADDU_VV_MF8, 0x3, false }, // 41
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{ PseudoVAADDU_VX_M1_MASK, PseudoVAADDU_VX_M1, 0x3, false }, // 42
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{ PseudoVAADDU_VX_M2_MASK, PseudoVAADDU_VX_M2, 0x3, false }, // 43
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{ PseudoVAADDU_VX_M4_MASK, PseudoVAADDU_VX_M4, 0x3, false }, // 44
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{ PseudoVAADDU_VX_M8_MASK, PseudoVAADDU_VX_M8, 0x3, false }, // 45
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{ PseudoVAADDU_VX_MF2_MASK, PseudoVAADDU_VX_MF2, 0x3, false }, // 46
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{ PseudoVAADDU_VX_MF4_MASK, PseudoVAADDU_VX_MF4, 0x3, false }, // 47
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{ PseudoVAADDU_VX_MF8_MASK, PseudoVAADDU_VX_MF8, 0x3, false }, // 48
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{ PseudoVAADD_VV_M1_MASK, PseudoVAADD_VV_M1, 0x3, false }, // 49
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{ PseudoVAADD_VV_M2_MASK, PseudoVAADD_VV_M2, 0x3, false }, // 50
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{ PseudoVAADD_VV_M4_MASK, PseudoVAADD_VV_M4, 0x3, false }, // 51
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{ PseudoVAADD_VV_M8_MASK, PseudoVAADD_VV_M8, 0x3, false }, // 52
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{ PseudoVAADD_VV_MF2_MASK, PseudoVAADD_VV_MF2, 0x3, false }, // 53
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{ PseudoVAADD_VV_MF4_MASK, PseudoVAADD_VV_MF4, 0x3, false }, // 54
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{ PseudoVAADD_VV_MF8_MASK, PseudoVAADD_VV_MF8, 0x3, false }, // 55
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{ PseudoVAADD_VX_M1_MASK, PseudoVAADD_VX_M1, 0x3, false }, // 56
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{ PseudoVAADD_VX_M2_MASK, PseudoVAADD_VX_M2, 0x3, false }, // 57
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{ PseudoVAADD_VX_M4_MASK, PseudoVAADD_VX_M4, 0x3, false }, // 58
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{ PseudoVAADD_VX_M8_MASK, PseudoVAADD_VX_M8, 0x3, false }, // 59
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{ PseudoVAADD_VX_MF2_MASK, PseudoVAADD_VX_MF2, 0x3, false }, // 60
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{ PseudoVAADD_VX_MF4_MASK, PseudoVAADD_VX_MF4, 0x3, false }, // 61
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{ PseudoVAADD_VX_MF8_MASK, PseudoVAADD_VX_MF8, 0x3, false }, // 62
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{ PseudoVADD_VI_M1_MASK, PseudoVADD_VI_M1, 0x3, false }, // 63
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{ PseudoVADD_VI_M2_MASK, PseudoVADD_VI_M2, 0x3, false }, // 64
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{ PseudoVADD_VI_M4_MASK, PseudoVADD_VI_M4, 0x3, false }, // 65
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{ PseudoVADD_VI_M8_MASK, PseudoVADD_VI_M8, 0x3, false }, // 66
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{ PseudoVADD_VI_MF2_MASK, PseudoVADD_VI_MF2, 0x3, false }, // 67
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{ PseudoVADD_VI_MF4_MASK, PseudoVADD_VI_MF4, 0x3, false }, // 68
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{ PseudoVADD_VI_MF8_MASK, PseudoVADD_VI_MF8, 0x3, false }, // 69
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{ PseudoVADD_VV_M1_MASK, PseudoVADD_VV_M1, 0x3, false }, // 70
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{ PseudoVADD_VV_M2_MASK, PseudoVADD_VV_M2, 0x3, false }, // 71
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{ PseudoVADD_VV_M4_MASK, PseudoVADD_VV_M4, 0x3, false }, // 72
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{ PseudoVADD_VV_M8_MASK, PseudoVADD_VV_M8, 0x3, false }, // 73
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{ PseudoVADD_VV_MF2_MASK, PseudoVADD_VV_MF2, 0x3, false }, // 74
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{ PseudoVADD_VV_MF4_MASK, PseudoVADD_VV_MF4, 0x3, false }, // 75
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{ PseudoVADD_VV_MF8_MASK, PseudoVADD_VV_MF8, 0x3, false }, // 76
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{ PseudoVADD_VX_M1_MASK, PseudoVADD_VX_M1, 0x3, false }, // 77
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{ PseudoVADD_VX_M2_MASK, PseudoVADD_VX_M2, 0x3, false }, // 78
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{ PseudoVADD_VX_M4_MASK, PseudoVADD_VX_M4, 0x3, false }, // 79
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{ PseudoVADD_VX_M8_MASK, PseudoVADD_VX_M8, 0x3, false }, // 80
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{ PseudoVADD_VX_MF2_MASK, PseudoVADD_VX_MF2, 0x3, false }, // 81
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{ PseudoVADD_VX_MF4_MASK, PseudoVADD_VX_MF4, 0x3, false }, // 82
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{ PseudoVADD_VX_MF8_MASK, PseudoVADD_VX_MF8, 0x3, false }, // 83
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{ PseudoVANDN_VV_M1_MASK, PseudoVANDN_VV_M1, 0x3, false }, // 84
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{ PseudoVANDN_VV_M2_MASK, PseudoVANDN_VV_M2, 0x3, false }, // 85
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{ PseudoVANDN_VV_M4_MASK, PseudoVANDN_VV_M4, 0x3, false }, // 86
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{ PseudoVANDN_VV_M8_MASK, PseudoVANDN_VV_M8, 0x3, false }, // 87
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{ PseudoVANDN_VV_MF2_MASK, PseudoVANDN_VV_MF2, 0x3, false }, // 88
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{ PseudoVANDN_VV_MF4_MASK, PseudoVANDN_VV_MF4, 0x3, false }, // 89
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{ PseudoVANDN_VV_MF8_MASK, PseudoVANDN_VV_MF8, 0x3, false }, // 90
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{ PseudoVANDN_VX_M1_MASK, PseudoVANDN_VX_M1, 0x3, false }, // 91
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{ PseudoVANDN_VX_M2_MASK, PseudoVANDN_VX_M2, 0x3, false }, // 92
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{ PseudoVANDN_VX_M4_MASK, PseudoVANDN_VX_M4, 0x3, false }, // 93
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{ PseudoVANDN_VX_M8_MASK, PseudoVANDN_VX_M8, 0x3, false }, // 94
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{ PseudoVANDN_VX_MF2_MASK, PseudoVANDN_VX_MF2, 0x3, false }, // 95
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{ PseudoVANDN_VX_MF4_MASK, PseudoVANDN_VX_MF4, 0x3, false }, // 96
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{ PseudoVANDN_VX_MF8_MASK, PseudoVANDN_VX_MF8, 0x3, false }, // 97
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{ PseudoVAND_VI_M1_MASK, PseudoVAND_VI_M1, 0x3, false }, // 98
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{ PseudoVAND_VI_M2_MASK, PseudoVAND_VI_M2, 0x3, false }, // 99
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{ PseudoVAND_VI_M4_MASK, PseudoVAND_VI_M4, 0x3, false }, // 100
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{ PseudoVAND_VI_M8_MASK, PseudoVAND_VI_M8, 0x3, false }, // 101
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{ PseudoVAND_VI_MF2_MASK, PseudoVAND_VI_MF2, 0x3, false }, // 102
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{ PseudoVAND_VI_MF4_MASK, PseudoVAND_VI_MF4, 0x3, false }, // 103
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{ PseudoVAND_VI_MF8_MASK, PseudoVAND_VI_MF8, 0x3, false }, // 104
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{ PseudoVAND_VV_M1_MASK, PseudoVAND_VV_M1, 0x3, false }, // 105
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{ PseudoVAND_VV_M2_MASK, PseudoVAND_VV_M2, 0x3, false }, // 106
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{ PseudoVAND_VV_M4_MASK, PseudoVAND_VV_M4, 0x3, false }, // 107
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{ PseudoVAND_VV_M8_MASK, PseudoVAND_VV_M8, 0x3, false }, // 108
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{ PseudoVAND_VV_MF2_MASK, PseudoVAND_VV_MF2, 0x3, false }, // 109
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{ PseudoVAND_VV_MF4_MASK, PseudoVAND_VV_MF4, 0x3, false }, // 110
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{ PseudoVAND_VV_MF8_MASK, PseudoVAND_VV_MF8, 0x3, false }, // 111
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{ PseudoVAND_VX_M1_MASK, PseudoVAND_VX_M1, 0x3, false }, // 112
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{ PseudoVAND_VX_M2_MASK, PseudoVAND_VX_M2, 0x3, false }, // 113
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{ PseudoVAND_VX_M4_MASK, PseudoVAND_VX_M4, 0x3, false }, // 114
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{ PseudoVAND_VX_M8_MASK, PseudoVAND_VX_M8, 0x3, false }, // 115
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{ PseudoVAND_VX_MF2_MASK, PseudoVAND_VX_MF2, 0x3, false }, // 116
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{ PseudoVAND_VX_MF4_MASK, PseudoVAND_VX_MF4, 0x3, false }, // 117
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{ PseudoVAND_VX_MF8_MASK, PseudoVAND_VX_MF8, 0x3, false }, // 118
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{ PseudoVASUBU_VV_M1_MASK, PseudoVASUBU_VV_M1, 0x3, false }, // 119
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{ PseudoVASUBU_VV_M2_MASK, PseudoVASUBU_VV_M2, 0x3, false }, // 120
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{ PseudoVASUBU_VV_M4_MASK, PseudoVASUBU_VV_M4, 0x3, false }, // 121
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{ PseudoVASUBU_VV_M8_MASK, PseudoVASUBU_VV_M8, 0x3, false }, // 122
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{ PseudoVASUBU_VV_MF2_MASK, PseudoVASUBU_VV_MF2, 0x3, false }, // 123
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{ PseudoVASUBU_VV_MF4_MASK, PseudoVASUBU_VV_MF4, 0x3, false }, // 124
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{ PseudoVASUBU_VV_MF8_MASK, PseudoVASUBU_VV_MF8, 0x3, false }, // 125
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{ PseudoVASUBU_VX_M1_MASK, PseudoVASUBU_VX_M1, 0x3, false }, // 126
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{ PseudoVASUBU_VX_M2_MASK, PseudoVASUBU_VX_M2, 0x3, false }, // 127
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{ PseudoVASUBU_VX_M4_MASK, PseudoVASUBU_VX_M4, 0x3, false }, // 128
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{ PseudoVASUBU_VX_M8_MASK, PseudoVASUBU_VX_M8, 0x3, false }, // 129
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{ PseudoVASUBU_VX_MF2_MASK, PseudoVASUBU_VX_MF2, 0x3, false }, // 130
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{ PseudoVASUBU_VX_MF4_MASK, PseudoVASUBU_VX_MF4, 0x3, false }, // 131
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{ PseudoVASUBU_VX_MF8_MASK, PseudoVASUBU_VX_MF8, 0x3, false }, // 132
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{ PseudoVASUB_VV_M1_MASK, PseudoVASUB_VV_M1, 0x3, false }, // 133
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{ PseudoVASUB_VV_M2_MASK, PseudoVASUB_VV_M2, 0x3, false }, // 134
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{ PseudoVASUB_VV_M4_MASK, PseudoVASUB_VV_M4, 0x3, false }, // 135
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{ PseudoVASUB_VV_M8_MASK, PseudoVASUB_VV_M8, 0x3, false }, // 136
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{ PseudoVASUB_VV_MF2_MASK, PseudoVASUB_VV_MF2, 0x3, false }, // 137
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{ PseudoVASUB_VV_MF4_MASK, PseudoVASUB_VV_MF4, 0x3, false }, // 138
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{ PseudoVASUB_VV_MF8_MASK, PseudoVASUB_VV_MF8, 0x3, false }, // 139
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{ PseudoVASUB_VX_M1_MASK, PseudoVASUB_VX_M1, 0x3, false }, // 140
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{ PseudoVASUB_VX_M2_MASK, PseudoVASUB_VX_M2, 0x3, false }, // 141
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{ PseudoVASUB_VX_M4_MASK, PseudoVASUB_VX_M4, 0x3, false }, // 142
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{ PseudoVASUB_VX_M8_MASK, PseudoVASUB_VX_M8, 0x3, false }, // 143
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{ PseudoVASUB_VX_MF2_MASK, PseudoVASUB_VX_MF2, 0x3, false }, // 144
|
|
{ PseudoVASUB_VX_MF4_MASK, PseudoVASUB_VX_MF4, 0x3, false }, // 145
|
|
{ PseudoVASUB_VX_MF8_MASK, PseudoVASUB_VX_MF8, 0x3, false }, // 146
|
|
{ PseudoVBREV8_V_M1_MASK, PseudoVBREV8_V_M1, 0x2, false }, // 147
|
|
{ PseudoVBREV8_V_M2_MASK, PseudoVBREV8_V_M2, 0x2, false }, // 148
|
|
{ PseudoVBREV8_V_M4_MASK, PseudoVBREV8_V_M4, 0x2, false }, // 149
|
|
{ PseudoVBREV8_V_M8_MASK, PseudoVBREV8_V_M8, 0x2, false }, // 150
|
|
{ PseudoVBREV8_V_MF2_MASK, PseudoVBREV8_V_MF2, 0x2, false }, // 151
|
|
{ PseudoVBREV8_V_MF4_MASK, PseudoVBREV8_V_MF4, 0x2, false }, // 152
|
|
{ PseudoVBREV8_V_MF8_MASK, PseudoVBREV8_V_MF8, 0x2, false }, // 153
|
|
{ PseudoVBREV_V_M1_MASK, PseudoVBREV_V_M1, 0x2, false }, // 154
|
|
{ PseudoVBREV_V_M2_MASK, PseudoVBREV_V_M2, 0x2, false }, // 155
|
|
{ PseudoVBREV_V_M4_MASK, PseudoVBREV_V_M4, 0x2, false }, // 156
|
|
{ PseudoVBREV_V_M8_MASK, PseudoVBREV_V_M8, 0x2, false }, // 157
|
|
{ PseudoVBREV_V_MF2_MASK, PseudoVBREV_V_MF2, 0x2, false }, // 158
|
|
{ PseudoVBREV_V_MF4_MASK, PseudoVBREV_V_MF4, 0x2, false }, // 159
|
|
{ PseudoVBREV_V_MF8_MASK, PseudoVBREV_V_MF8, 0x2, false }, // 160
|
|
{ PseudoVCLMULH_VV_M1_MASK, PseudoVCLMULH_VV_M1, 0x3, false }, // 161
|
|
{ PseudoVCLMULH_VV_M2_MASK, PseudoVCLMULH_VV_M2, 0x3, false }, // 162
|
|
{ PseudoVCLMULH_VV_M4_MASK, PseudoVCLMULH_VV_M4, 0x3, false }, // 163
|
|
{ PseudoVCLMULH_VV_M8_MASK, PseudoVCLMULH_VV_M8, 0x3, false }, // 164
|
|
{ PseudoVCLMULH_VV_MF2_MASK, PseudoVCLMULH_VV_MF2, 0x3, false }, // 165
|
|
{ PseudoVCLMULH_VV_MF4_MASK, PseudoVCLMULH_VV_MF4, 0x3, false }, // 166
|
|
{ PseudoVCLMULH_VV_MF8_MASK, PseudoVCLMULH_VV_MF8, 0x3, false }, // 167
|
|
{ PseudoVCLMULH_VX_M1_MASK, PseudoVCLMULH_VX_M1, 0x3, false }, // 168
|
|
{ PseudoVCLMULH_VX_M2_MASK, PseudoVCLMULH_VX_M2, 0x3, false }, // 169
|
|
{ PseudoVCLMULH_VX_M4_MASK, PseudoVCLMULH_VX_M4, 0x3, false }, // 170
|
|
{ PseudoVCLMULH_VX_M8_MASK, PseudoVCLMULH_VX_M8, 0x3, false }, // 171
|
|
{ PseudoVCLMULH_VX_MF2_MASK, PseudoVCLMULH_VX_MF2, 0x3, false }, // 172
|
|
{ PseudoVCLMULH_VX_MF4_MASK, PseudoVCLMULH_VX_MF4, 0x3, false }, // 173
|
|
{ PseudoVCLMULH_VX_MF8_MASK, PseudoVCLMULH_VX_MF8, 0x3, false }, // 174
|
|
{ PseudoVCLMUL_VV_M1_MASK, PseudoVCLMUL_VV_M1, 0x3, false }, // 175
|
|
{ PseudoVCLMUL_VV_M2_MASK, PseudoVCLMUL_VV_M2, 0x3, false }, // 176
|
|
{ PseudoVCLMUL_VV_M4_MASK, PseudoVCLMUL_VV_M4, 0x3, false }, // 177
|
|
{ PseudoVCLMUL_VV_M8_MASK, PseudoVCLMUL_VV_M8, 0x3, false }, // 178
|
|
{ PseudoVCLMUL_VV_MF2_MASK, PseudoVCLMUL_VV_MF2, 0x3, false }, // 179
|
|
{ PseudoVCLMUL_VV_MF4_MASK, PseudoVCLMUL_VV_MF4, 0x3, false }, // 180
|
|
{ PseudoVCLMUL_VV_MF8_MASK, PseudoVCLMUL_VV_MF8, 0x3, false }, // 181
|
|
{ PseudoVCLMUL_VX_M1_MASK, PseudoVCLMUL_VX_M1, 0x3, false }, // 182
|
|
{ PseudoVCLMUL_VX_M2_MASK, PseudoVCLMUL_VX_M2, 0x3, false }, // 183
|
|
{ PseudoVCLMUL_VX_M4_MASK, PseudoVCLMUL_VX_M4, 0x3, false }, // 184
|
|
{ PseudoVCLMUL_VX_M8_MASK, PseudoVCLMUL_VX_M8, 0x3, false }, // 185
|
|
{ PseudoVCLMUL_VX_MF2_MASK, PseudoVCLMUL_VX_MF2, 0x3, false }, // 186
|
|
{ PseudoVCLMUL_VX_MF4_MASK, PseudoVCLMUL_VX_MF4, 0x3, false }, // 187
|
|
{ PseudoVCLMUL_VX_MF8_MASK, PseudoVCLMUL_VX_MF8, 0x3, false }, // 188
|
|
{ PseudoVCLZ_V_M1_MASK, PseudoVCLZ_V_M1, 0x2, false }, // 189
|
|
{ PseudoVCLZ_V_M2_MASK, PseudoVCLZ_V_M2, 0x2, false }, // 190
|
|
{ PseudoVCLZ_V_M4_MASK, PseudoVCLZ_V_M4, 0x2, false }, // 191
|
|
{ PseudoVCLZ_V_M8_MASK, PseudoVCLZ_V_M8, 0x2, false }, // 192
|
|
{ PseudoVCLZ_V_MF2_MASK, PseudoVCLZ_V_MF2, 0x2, false }, // 193
|
|
{ PseudoVCLZ_V_MF4_MASK, PseudoVCLZ_V_MF4, 0x2, false }, // 194
|
|
{ PseudoVCLZ_V_MF8_MASK, PseudoVCLZ_V_MF8, 0x2, false }, // 195
|
|
{ PseudoVCPOP_V_M1_MASK, PseudoVCPOP_V_M1, 0x2, false }, // 196
|
|
{ PseudoVCPOP_V_M2_MASK, PseudoVCPOP_V_M2, 0x2, false }, // 197
|
|
{ PseudoVCPOP_V_M4_MASK, PseudoVCPOP_V_M4, 0x2, false }, // 198
|
|
{ PseudoVCPOP_V_M8_MASK, PseudoVCPOP_V_M8, 0x2, false }, // 199
|
|
{ PseudoVCPOP_V_MF2_MASK, PseudoVCPOP_V_MF2, 0x2, false }, // 200
|
|
{ PseudoVCPOP_V_MF4_MASK, PseudoVCPOP_V_MF4, 0x2, false }, // 201
|
|
{ PseudoVCPOP_V_MF8_MASK, PseudoVCPOP_V_MF8, 0x2, false }, // 202
|
|
{ PseudoVCTZ_V_M1_MASK, PseudoVCTZ_V_M1, 0x2, false }, // 203
|
|
{ PseudoVCTZ_V_M2_MASK, PseudoVCTZ_V_M2, 0x2, false }, // 204
|
|
{ PseudoVCTZ_V_M4_MASK, PseudoVCTZ_V_M4, 0x2, false }, // 205
|
|
{ PseudoVCTZ_V_M8_MASK, PseudoVCTZ_V_M8, 0x2, false }, // 206
|
|
{ PseudoVCTZ_V_MF2_MASK, PseudoVCTZ_V_MF2, 0x2, false }, // 207
|
|
{ PseudoVCTZ_V_MF4_MASK, PseudoVCTZ_V_MF4, 0x2, false }, // 208
|
|
{ PseudoVCTZ_V_MF8_MASK, PseudoVCTZ_V_MF8, 0x2, false }, // 209
|
|
{ PseudoVDIVU_VV_M1_E16_MASK, PseudoVDIVU_VV_M1_E16, 0x3, false }, // 210
|
|
{ PseudoVDIVU_VV_M1_E32_MASK, PseudoVDIVU_VV_M1_E32, 0x3, false }, // 211
|
|
{ PseudoVDIVU_VV_M1_E64_MASK, PseudoVDIVU_VV_M1_E64, 0x3, false }, // 212
|
|
{ PseudoVDIVU_VV_M1_E8_MASK, PseudoVDIVU_VV_M1_E8, 0x3, false }, // 213
|
|
{ PseudoVDIVU_VV_M2_E16_MASK, PseudoVDIVU_VV_M2_E16, 0x3, false }, // 214
|
|
{ PseudoVDIVU_VV_M2_E32_MASK, PseudoVDIVU_VV_M2_E32, 0x3, false }, // 215
|
|
{ PseudoVDIVU_VV_M2_E64_MASK, PseudoVDIVU_VV_M2_E64, 0x3, false }, // 216
|
|
{ PseudoVDIVU_VV_M2_E8_MASK, PseudoVDIVU_VV_M2_E8, 0x3, false }, // 217
|
|
{ PseudoVDIVU_VV_M4_E16_MASK, PseudoVDIVU_VV_M4_E16, 0x3, false }, // 218
|
|
{ PseudoVDIVU_VV_M4_E32_MASK, PseudoVDIVU_VV_M4_E32, 0x3, false }, // 219
|
|
{ PseudoVDIVU_VV_M4_E64_MASK, PseudoVDIVU_VV_M4_E64, 0x3, false }, // 220
|
|
{ PseudoVDIVU_VV_M4_E8_MASK, PseudoVDIVU_VV_M4_E8, 0x3, false }, // 221
|
|
{ PseudoVDIVU_VV_M8_E16_MASK, PseudoVDIVU_VV_M8_E16, 0x3, false }, // 222
|
|
{ PseudoVDIVU_VV_M8_E32_MASK, PseudoVDIVU_VV_M8_E32, 0x3, false }, // 223
|
|
{ PseudoVDIVU_VV_M8_E64_MASK, PseudoVDIVU_VV_M8_E64, 0x3, false }, // 224
|
|
{ PseudoVDIVU_VV_M8_E8_MASK, PseudoVDIVU_VV_M8_E8, 0x3, false }, // 225
|
|
{ PseudoVDIVU_VV_MF2_E16_MASK, PseudoVDIVU_VV_MF2_E16, 0x3, false }, // 226
|
|
{ PseudoVDIVU_VV_MF2_E32_MASK, PseudoVDIVU_VV_MF2_E32, 0x3, false }, // 227
|
|
{ PseudoVDIVU_VV_MF2_E8_MASK, PseudoVDIVU_VV_MF2_E8, 0x3, false }, // 228
|
|
{ PseudoVDIVU_VV_MF4_E16_MASK, PseudoVDIVU_VV_MF4_E16, 0x3, false }, // 229
|
|
{ PseudoVDIVU_VV_MF4_E8_MASK, PseudoVDIVU_VV_MF4_E8, 0x3, false }, // 230
|
|
{ PseudoVDIVU_VV_MF8_E8_MASK, PseudoVDIVU_VV_MF8_E8, 0x3, false }, // 231
|
|
{ PseudoVDIVU_VX_M1_E16_MASK, PseudoVDIVU_VX_M1_E16, 0x3, false }, // 232
|
|
{ PseudoVDIVU_VX_M1_E32_MASK, PseudoVDIVU_VX_M1_E32, 0x3, false }, // 233
|
|
{ PseudoVDIVU_VX_M1_E64_MASK, PseudoVDIVU_VX_M1_E64, 0x3, false }, // 234
|
|
{ PseudoVDIVU_VX_M1_E8_MASK, PseudoVDIVU_VX_M1_E8, 0x3, false }, // 235
|
|
{ PseudoVDIVU_VX_M2_E16_MASK, PseudoVDIVU_VX_M2_E16, 0x3, false }, // 236
|
|
{ PseudoVDIVU_VX_M2_E32_MASK, PseudoVDIVU_VX_M2_E32, 0x3, false }, // 237
|
|
{ PseudoVDIVU_VX_M2_E64_MASK, PseudoVDIVU_VX_M2_E64, 0x3, false }, // 238
|
|
{ PseudoVDIVU_VX_M2_E8_MASK, PseudoVDIVU_VX_M2_E8, 0x3, false }, // 239
|
|
{ PseudoVDIVU_VX_M4_E16_MASK, PseudoVDIVU_VX_M4_E16, 0x3, false }, // 240
|
|
{ PseudoVDIVU_VX_M4_E32_MASK, PseudoVDIVU_VX_M4_E32, 0x3, false }, // 241
|
|
{ PseudoVDIVU_VX_M4_E64_MASK, PseudoVDIVU_VX_M4_E64, 0x3, false }, // 242
|
|
{ PseudoVDIVU_VX_M4_E8_MASK, PseudoVDIVU_VX_M4_E8, 0x3, false }, // 243
|
|
{ PseudoVDIVU_VX_M8_E16_MASK, PseudoVDIVU_VX_M8_E16, 0x3, false }, // 244
|
|
{ PseudoVDIVU_VX_M8_E32_MASK, PseudoVDIVU_VX_M8_E32, 0x3, false }, // 245
|
|
{ PseudoVDIVU_VX_M8_E64_MASK, PseudoVDIVU_VX_M8_E64, 0x3, false }, // 246
|
|
{ PseudoVDIVU_VX_M8_E8_MASK, PseudoVDIVU_VX_M8_E8, 0x3, false }, // 247
|
|
{ PseudoVDIVU_VX_MF2_E16_MASK, PseudoVDIVU_VX_MF2_E16, 0x3, false }, // 248
|
|
{ PseudoVDIVU_VX_MF2_E32_MASK, PseudoVDIVU_VX_MF2_E32, 0x3, false }, // 249
|
|
{ PseudoVDIVU_VX_MF2_E8_MASK, PseudoVDIVU_VX_MF2_E8, 0x3, false }, // 250
|
|
{ PseudoVDIVU_VX_MF4_E16_MASK, PseudoVDIVU_VX_MF4_E16, 0x3, false }, // 251
|
|
{ PseudoVDIVU_VX_MF4_E8_MASK, PseudoVDIVU_VX_MF4_E8, 0x3, false }, // 252
|
|
{ PseudoVDIVU_VX_MF8_E8_MASK, PseudoVDIVU_VX_MF8_E8, 0x3, false }, // 253
|
|
{ PseudoVDIV_VV_M1_E16_MASK, PseudoVDIV_VV_M1_E16, 0x3, false }, // 254
|
|
{ PseudoVDIV_VV_M1_E32_MASK, PseudoVDIV_VV_M1_E32, 0x3, false }, // 255
|
|
{ PseudoVDIV_VV_M1_E64_MASK, PseudoVDIV_VV_M1_E64, 0x3, false }, // 256
|
|
{ PseudoVDIV_VV_M1_E8_MASK, PseudoVDIV_VV_M1_E8, 0x3, false }, // 257
|
|
{ PseudoVDIV_VV_M2_E16_MASK, PseudoVDIV_VV_M2_E16, 0x3, false }, // 258
|
|
{ PseudoVDIV_VV_M2_E32_MASK, PseudoVDIV_VV_M2_E32, 0x3, false }, // 259
|
|
{ PseudoVDIV_VV_M2_E64_MASK, PseudoVDIV_VV_M2_E64, 0x3, false }, // 260
|
|
{ PseudoVDIV_VV_M2_E8_MASK, PseudoVDIV_VV_M2_E8, 0x3, false }, // 261
|
|
{ PseudoVDIV_VV_M4_E16_MASK, PseudoVDIV_VV_M4_E16, 0x3, false }, // 262
|
|
{ PseudoVDIV_VV_M4_E32_MASK, PseudoVDIV_VV_M4_E32, 0x3, false }, // 263
|
|
{ PseudoVDIV_VV_M4_E64_MASK, PseudoVDIV_VV_M4_E64, 0x3, false }, // 264
|
|
{ PseudoVDIV_VV_M4_E8_MASK, PseudoVDIV_VV_M4_E8, 0x3, false }, // 265
|
|
{ PseudoVDIV_VV_M8_E16_MASK, PseudoVDIV_VV_M8_E16, 0x3, false }, // 266
|
|
{ PseudoVDIV_VV_M8_E32_MASK, PseudoVDIV_VV_M8_E32, 0x3, false }, // 267
|
|
{ PseudoVDIV_VV_M8_E64_MASK, PseudoVDIV_VV_M8_E64, 0x3, false }, // 268
|
|
{ PseudoVDIV_VV_M8_E8_MASK, PseudoVDIV_VV_M8_E8, 0x3, false }, // 269
|
|
{ PseudoVDIV_VV_MF2_E16_MASK, PseudoVDIV_VV_MF2_E16, 0x3, false }, // 270
|
|
{ PseudoVDIV_VV_MF2_E32_MASK, PseudoVDIV_VV_MF2_E32, 0x3, false }, // 271
|
|
{ PseudoVDIV_VV_MF2_E8_MASK, PseudoVDIV_VV_MF2_E8, 0x3, false }, // 272
|
|
{ PseudoVDIV_VV_MF4_E16_MASK, PseudoVDIV_VV_MF4_E16, 0x3, false }, // 273
|
|
{ PseudoVDIV_VV_MF4_E8_MASK, PseudoVDIV_VV_MF4_E8, 0x3, false }, // 274
|
|
{ PseudoVDIV_VV_MF8_E8_MASK, PseudoVDIV_VV_MF8_E8, 0x3, false }, // 275
|
|
{ PseudoVDIV_VX_M1_E16_MASK, PseudoVDIV_VX_M1_E16, 0x3, false }, // 276
|
|
{ PseudoVDIV_VX_M1_E32_MASK, PseudoVDIV_VX_M1_E32, 0x3, false }, // 277
|
|
{ PseudoVDIV_VX_M1_E64_MASK, PseudoVDIV_VX_M1_E64, 0x3, false }, // 278
|
|
{ PseudoVDIV_VX_M1_E8_MASK, PseudoVDIV_VX_M1_E8, 0x3, false }, // 279
|
|
{ PseudoVDIV_VX_M2_E16_MASK, PseudoVDIV_VX_M2_E16, 0x3, false }, // 280
|
|
{ PseudoVDIV_VX_M2_E32_MASK, PseudoVDIV_VX_M2_E32, 0x3, false }, // 281
|
|
{ PseudoVDIV_VX_M2_E64_MASK, PseudoVDIV_VX_M2_E64, 0x3, false }, // 282
|
|
{ PseudoVDIV_VX_M2_E8_MASK, PseudoVDIV_VX_M2_E8, 0x3, false }, // 283
|
|
{ PseudoVDIV_VX_M4_E16_MASK, PseudoVDIV_VX_M4_E16, 0x3, false }, // 284
|
|
{ PseudoVDIV_VX_M4_E32_MASK, PseudoVDIV_VX_M4_E32, 0x3, false }, // 285
|
|
{ PseudoVDIV_VX_M4_E64_MASK, PseudoVDIV_VX_M4_E64, 0x3, false }, // 286
|
|
{ PseudoVDIV_VX_M4_E8_MASK, PseudoVDIV_VX_M4_E8, 0x3, false }, // 287
|
|
{ PseudoVDIV_VX_M8_E16_MASK, PseudoVDIV_VX_M8_E16, 0x3, false }, // 288
|
|
{ PseudoVDIV_VX_M8_E32_MASK, PseudoVDIV_VX_M8_E32, 0x3, false }, // 289
|
|
{ PseudoVDIV_VX_M8_E64_MASK, PseudoVDIV_VX_M8_E64, 0x3, false }, // 290
|
|
{ PseudoVDIV_VX_M8_E8_MASK, PseudoVDIV_VX_M8_E8, 0x3, false }, // 291
|
|
{ PseudoVDIV_VX_MF2_E16_MASK, PseudoVDIV_VX_MF2_E16, 0x3, false }, // 292
|
|
{ PseudoVDIV_VX_MF2_E32_MASK, PseudoVDIV_VX_MF2_E32, 0x3, false }, // 293
|
|
{ PseudoVDIV_VX_MF2_E8_MASK, PseudoVDIV_VX_MF2_E8, 0x3, false }, // 294
|
|
{ PseudoVDIV_VX_MF4_E16_MASK, PseudoVDIV_VX_MF4_E16, 0x3, false }, // 295
|
|
{ PseudoVDIV_VX_MF4_E8_MASK, PseudoVDIV_VX_MF4_E8, 0x3, false }, // 296
|
|
{ PseudoVDIV_VX_MF8_E8_MASK, PseudoVDIV_VX_MF8_E8, 0x3, false }, // 297
|
|
{ PseudoVFADD_VFPR16_M1_MASK, PseudoVFADD_VFPR16_M1, 0x3, false }, // 298
|
|
{ PseudoVFADD_VFPR16_M2_MASK, PseudoVFADD_VFPR16_M2, 0x3, false }, // 299
|
|
{ PseudoVFADD_VFPR16_M4_MASK, PseudoVFADD_VFPR16_M4, 0x3, false }, // 300
|
|
{ PseudoVFADD_VFPR16_M8_MASK, PseudoVFADD_VFPR16_M8, 0x3, false }, // 301
|
|
{ PseudoVFADD_VFPR16_MF2_MASK, PseudoVFADD_VFPR16_MF2, 0x3, false }, // 302
|
|
{ PseudoVFADD_VFPR16_MF4_MASK, PseudoVFADD_VFPR16_MF4, 0x3, false }, // 303
|
|
{ PseudoVFADD_VFPR32_M1_MASK, PseudoVFADD_VFPR32_M1, 0x3, false }, // 304
|
|
{ PseudoVFADD_VFPR32_M2_MASK, PseudoVFADD_VFPR32_M2, 0x3, false }, // 305
|
|
{ PseudoVFADD_VFPR32_M4_MASK, PseudoVFADD_VFPR32_M4, 0x3, false }, // 306
|
|
{ PseudoVFADD_VFPR32_M8_MASK, PseudoVFADD_VFPR32_M8, 0x3, false }, // 307
|
|
{ PseudoVFADD_VFPR32_MF2_MASK, PseudoVFADD_VFPR32_MF2, 0x3, false }, // 308
|
|
{ PseudoVFADD_VFPR64_M1_MASK, PseudoVFADD_VFPR64_M1, 0x3, false }, // 309
|
|
{ PseudoVFADD_VFPR64_M2_MASK, PseudoVFADD_VFPR64_M2, 0x3, false }, // 310
|
|
{ PseudoVFADD_VFPR64_M4_MASK, PseudoVFADD_VFPR64_M4, 0x3, false }, // 311
|
|
{ PseudoVFADD_VFPR64_M8_MASK, PseudoVFADD_VFPR64_M8, 0x3, false }, // 312
|
|
{ PseudoVFADD_VV_M1_MASK, PseudoVFADD_VV_M1, 0x3, false }, // 313
|
|
{ PseudoVFADD_VV_M2_MASK, PseudoVFADD_VV_M2, 0x3, false }, // 314
|
|
{ PseudoVFADD_VV_M4_MASK, PseudoVFADD_VV_M4, 0x3, false }, // 315
|
|
{ PseudoVFADD_VV_M8_MASK, PseudoVFADD_VV_M8, 0x3, false }, // 316
|
|
{ PseudoVFADD_VV_MF2_MASK, PseudoVFADD_VV_MF2, 0x3, false }, // 317
|
|
{ PseudoVFADD_VV_MF4_MASK, PseudoVFADD_VV_MF4, 0x3, false }, // 318
|
|
{ PseudoVFCLASS_V_M1_MASK, PseudoVFCLASS_V_M1, 0x2, false }, // 319
|
|
{ PseudoVFCLASS_V_M2_MASK, PseudoVFCLASS_V_M2, 0x2, false }, // 320
|
|
{ PseudoVFCLASS_V_M4_MASK, PseudoVFCLASS_V_M4, 0x2, false }, // 321
|
|
{ PseudoVFCLASS_V_M8_MASK, PseudoVFCLASS_V_M8, 0x2, false }, // 322
|
|
{ PseudoVFCLASS_V_MF2_MASK, PseudoVFCLASS_V_MF2, 0x2, false }, // 323
|
|
{ PseudoVFCLASS_V_MF4_MASK, PseudoVFCLASS_V_MF4, 0x2, false }, // 324
|
|
{ PseudoVFCVT_F_XU_V_M1_MASK, PseudoVFCVT_F_XU_V_M1, 0x2, false }, // 325
|
|
{ PseudoVFCVT_F_XU_V_M2_MASK, PseudoVFCVT_F_XU_V_M2, 0x2, false }, // 326
|
|
{ PseudoVFCVT_F_XU_V_M4_MASK, PseudoVFCVT_F_XU_V_M4, 0x2, false }, // 327
|
|
{ PseudoVFCVT_F_XU_V_M8_MASK, PseudoVFCVT_F_XU_V_M8, 0x2, false }, // 328
|
|
{ PseudoVFCVT_F_XU_V_MF2_MASK, PseudoVFCVT_F_XU_V_MF2, 0x2, false }, // 329
|
|
{ PseudoVFCVT_F_XU_V_MF4_MASK, PseudoVFCVT_F_XU_V_MF4, 0x2, false }, // 330
|
|
{ PseudoVFCVT_F_X_V_M1_MASK, PseudoVFCVT_F_X_V_M1, 0x2, false }, // 331
|
|
{ PseudoVFCVT_F_X_V_M2_MASK, PseudoVFCVT_F_X_V_M2, 0x2, false }, // 332
|
|
{ PseudoVFCVT_F_X_V_M4_MASK, PseudoVFCVT_F_X_V_M4, 0x2, false }, // 333
|
|
{ PseudoVFCVT_F_X_V_M8_MASK, PseudoVFCVT_F_X_V_M8, 0x2, false }, // 334
|
|
{ PseudoVFCVT_F_X_V_MF2_MASK, PseudoVFCVT_F_X_V_MF2, 0x2, false }, // 335
|
|
{ PseudoVFCVT_F_X_V_MF4_MASK, PseudoVFCVT_F_X_V_MF4, 0x2, false }, // 336
|
|
{ PseudoVFCVT_RM_F_XU_V_M1_MASK, PseudoVFCVT_RM_F_XU_V_M1, 0x2, false }, // 337
|
|
{ PseudoVFCVT_RM_F_XU_V_M2_MASK, PseudoVFCVT_RM_F_XU_V_M2, 0x2, false }, // 338
|
|
{ PseudoVFCVT_RM_F_XU_V_M4_MASK, PseudoVFCVT_RM_F_XU_V_M4, 0x2, false }, // 339
|
|
{ PseudoVFCVT_RM_F_XU_V_M8_MASK, PseudoVFCVT_RM_F_XU_V_M8, 0x2, false }, // 340
|
|
{ PseudoVFCVT_RM_F_XU_V_MF2_MASK, PseudoVFCVT_RM_F_XU_V_MF2, 0x2, false }, // 341
|
|
{ PseudoVFCVT_RM_F_XU_V_MF4_MASK, PseudoVFCVT_RM_F_XU_V_MF4, 0x2, false }, // 342
|
|
{ PseudoVFCVT_RM_F_X_V_M1_MASK, PseudoVFCVT_RM_F_X_V_M1, 0x2, false }, // 343
|
|
{ PseudoVFCVT_RM_F_X_V_M2_MASK, PseudoVFCVT_RM_F_X_V_M2, 0x2, false }, // 344
|
|
{ PseudoVFCVT_RM_F_X_V_M4_MASK, PseudoVFCVT_RM_F_X_V_M4, 0x2, false }, // 345
|
|
{ PseudoVFCVT_RM_F_X_V_M8_MASK, PseudoVFCVT_RM_F_X_V_M8, 0x2, false }, // 346
|
|
{ PseudoVFCVT_RM_F_X_V_MF2_MASK, PseudoVFCVT_RM_F_X_V_MF2, 0x2, false }, // 347
|
|
{ PseudoVFCVT_RM_F_X_V_MF4_MASK, PseudoVFCVT_RM_F_X_V_MF4, 0x2, false }, // 348
|
|
{ PseudoVFCVT_RM_XU_F_V_M1_MASK, PseudoVFCVT_RM_XU_F_V_M1, 0x2, false }, // 349
|
|
{ PseudoVFCVT_RM_XU_F_V_M2_MASK, PseudoVFCVT_RM_XU_F_V_M2, 0x2, false }, // 350
|
|
{ PseudoVFCVT_RM_XU_F_V_M4_MASK, PseudoVFCVT_RM_XU_F_V_M4, 0x2, false }, // 351
|
|
{ PseudoVFCVT_RM_XU_F_V_M8_MASK, PseudoVFCVT_RM_XU_F_V_M8, 0x2, false }, // 352
|
|
{ PseudoVFCVT_RM_XU_F_V_MF2_MASK, PseudoVFCVT_RM_XU_F_V_MF2, 0x2, false }, // 353
|
|
{ PseudoVFCVT_RM_XU_F_V_MF4_MASK, PseudoVFCVT_RM_XU_F_V_MF4, 0x2, false }, // 354
|
|
{ PseudoVFCVT_RM_X_F_V_M1_MASK, PseudoVFCVT_RM_X_F_V_M1, 0x2, false }, // 355
|
|
{ PseudoVFCVT_RM_X_F_V_M2_MASK, PseudoVFCVT_RM_X_F_V_M2, 0x2, false }, // 356
|
|
{ PseudoVFCVT_RM_X_F_V_M4_MASK, PseudoVFCVT_RM_X_F_V_M4, 0x2, false }, // 357
|
|
{ PseudoVFCVT_RM_X_F_V_M8_MASK, PseudoVFCVT_RM_X_F_V_M8, 0x2, false }, // 358
|
|
{ PseudoVFCVT_RM_X_F_V_MF2_MASK, PseudoVFCVT_RM_X_F_V_MF2, 0x2, false }, // 359
|
|
{ PseudoVFCVT_RM_X_F_V_MF4_MASK, PseudoVFCVT_RM_X_F_V_MF4, 0x2, false }, // 360
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M1_MASK, PseudoVFCVT_RTZ_XU_F_V_M1, 0x2, false }, // 361
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M2_MASK, PseudoVFCVT_RTZ_XU_F_V_M2, 0x2, false }, // 362
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M4_MASK, PseudoVFCVT_RTZ_XU_F_V_M4, 0x2, false }, // 363
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M8_MASK, PseudoVFCVT_RTZ_XU_F_V_M8, 0x2, false }, // 364
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFCVT_RTZ_XU_F_V_MF2, 0x2, false }, // 365
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFCVT_RTZ_XU_F_V_MF4, 0x2, false }, // 366
|
|
{ PseudoVFCVT_RTZ_X_F_V_M1_MASK, PseudoVFCVT_RTZ_X_F_V_M1, 0x2, false }, // 367
|
|
{ PseudoVFCVT_RTZ_X_F_V_M2_MASK, PseudoVFCVT_RTZ_X_F_V_M2, 0x2, false }, // 368
|
|
{ PseudoVFCVT_RTZ_X_F_V_M4_MASK, PseudoVFCVT_RTZ_X_F_V_M4, 0x2, false }, // 369
|
|
{ PseudoVFCVT_RTZ_X_F_V_M8_MASK, PseudoVFCVT_RTZ_X_F_V_M8, 0x2, false }, // 370
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF2_MASK, PseudoVFCVT_RTZ_X_F_V_MF2, 0x2, false }, // 371
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF4_MASK, PseudoVFCVT_RTZ_X_F_V_MF4, 0x2, false }, // 372
|
|
{ PseudoVFCVT_XU_F_V_M1_MASK, PseudoVFCVT_XU_F_V_M1, 0x2, false }, // 373
|
|
{ PseudoVFCVT_XU_F_V_M2_MASK, PseudoVFCVT_XU_F_V_M2, 0x2, false }, // 374
|
|
{ PseudoVFCVT_XU_F_V_M4_MASK, PseudoVFCVT_XU_F_V_M4, 0x2, false }, // 375
|
|
{ PseudoVFCVT_XU_F_V_M8_MASK, PseudoVFCVT_XU_F_V_M8, 0x2, false }, // 376
|
|
{ PseudoVFCVT_XU_F_V_MF2_MASK, PseudoVFCVT_XU_F_V_MF2, 0x2, false }, // 377
|
|
{ PseudoVFCVT_XU_F_V_MF4_MASK, PseudoVFCVT_XU_F_V_MF4, 0x2, false }, // 378
|
|
{ PseudoVFCVT_X_F_V_M1_MASK, PseudoVFCVT_X_F_V_M1, 0x2, false }, // 379
|
|
{ PseudoVFCVT_X_F_V_M2_MASK, PseudoVFCVT_X_F_V_M2, 0x2, false }, // 380
|
|
{ PseudoVFCVT_X_F_V_M4_MASK, PseudoVFCVT_X_F_V_M4, 0x2, false }, // 381
|
|
{ PseudoVFCVT_X_F_V_M8_MASK, PseudoVFCVT_X_F_V_M8, 0x2, false }, // 382
|
|
{ PseudoVFCVT_X_F_V_MF2_MASK, PseudoVFCVT_X_F_V_MF2, 0x2, false }, // 383
|
|
{ PseudoVFCVT_X_F_V_MF4_MASK, PseudoVFCVT_X_F_V_MF4, 0x2, false }, // 384
|
|
{ PseudoVFDIV_VFPR16_M1_E16_MASK, PseudoVFDIV_VFPR16_M1_E16, 0x3, false }, // 385
|
|
{ PseudoVFDIV_VFPR16_M2_E16_MASK, PseudoVFDIV_VFPR16_M2_E16, 0x3, false }, // 386
|
|
{ PseudoVFDIV_VFPR16_M4_E16_MASK, PseudoVFDIV_VFPR16_M4_E16, 0x3, false }, // 387
|
|
{ PseudoVFDIV_VFPR16_M8_E16_MASK, PseudoVFDIV_VFPR16_M8_E16, 0x3, false }, // 388
|
|
{ PseudoVFDIV_VFPR16_MF2_E16_MASK, PseudoVFDIV_VFPR16_MF2_E16, 0x3, false }, // 389
|
|
{ PseudoVFDIV_VFPR16_MF4_E16_MASK, PseudoVFDIV_VFPR16_MF4_E16, 0x3, false }, // 390
|
|
{ PseudoVFDIV_VFPR32_M1_E32_MASK, PseudoVFDIV_VFPR32_M1_E32, 0x3, false }, // 391
|
|
{ PseudoVFDIV_VFPR32_M2_E32_MASK, PseudoVFDIV_VFPR32_M2_E32, 0x3, false }, // 392
|
|
{ PseudoVFDIV_VFPR32_M4_E32_MASK, PseudoVFDIV_VFPR32_M4_E32, 0x3, false }, // 393
|
|
{ PseudoVFDIV_VFPR32_M8_E32_MASK, PseudoVFDIV_VFPR32_M8_E32, 0x3, false }, // 394
|
|
{ PseudoVFDIV_VFPR32_MF2_E32_MASK, PseudoVFDIV_VFPR32_MF2_E32, 0x3, false }, // 395
|
|
{ PseudoVFDIV_VFPR64_M1_E64_MASK, PseudoVFDIV_VFPR64_M1_E64, 0x3, false }, // 396
|
|
{ PseudoVFDIV_VFPR64_M2_E64_MASK, PseudoVFDIV_VFPR64_M2_E64, 0x3, false }, // 397
|
|
{ PseudoVFDIV_VFPR64_M4_E64_MASK, PseudoVFDIV_VFPR64_M4_E64, 0x3, false }, // 398
|
|
{ PseudoVFDIV_VFPR64_M8_E64_MASK, PseudoVFDIV_VFPR64_M8_E64, 0x3, false }, // 399
|
|
{ PseudoVFDIV_VV_M1_E16_MASK, PseudoVFDIV_VV_M1_E16, 0x3, false }, // 400
|
|
{ PseudoVFDIV_VV_M1_E32_MASK, PseudoVFDIV_VV_M1_E32, 0x3, false }, // 401
|
|
{ PseudoVFDIV_VV_M1_E64_MASK, PseudoVFDIV_VV_M1_E64, 0x3, false }, // 402
|
|
{ PseudoVFDIV_VV_M2_E16_MASK, PseudoVFDIV_VV_M2_E16, 0x3, false }, // 403
|
|
{ PseudoVFDIV_VV_M2_E32_MASK, PseudoVFDIV_VV_M2_E32, 0x3, false }, // 404
|
|
{ PseudoVFDIV_VV_M2_E64_MASK, PseudoVFDIV_VV_M2_E64, 0x3, false }, // 405
|
|
{ PseudoVFDIV_VV_M4_E16_MASK, PseudoVFDIV_VV_M4_E16, 0x3, false }, // 406
|
|
{ PseudoVFDIV_VV_M4_E32_MASK, PseudoVFDIV_VV_M4_E32, 0x3, false }, // 407
|
|
{ PseudoVFDIV_VV_M4_E64_MASK, PseudoVFDIV_VV_M4_E64, 0x3, false }, // 408
|
|
{ PseudoVFDIV_VV_M8_E16_MASK, PseudoVFDIV_VV_M8_E16, 0x3, false }, // 409
|
|
{ PseudoVFDIV_VV_M8_E32_MASK, PseudoVFDIV_VV_M8_E32, 0x3, false }, // 410
|
|
{ PseudoVFDIV_VV_M8_E64_MASK, PseudoVFDIV_VV_M8_E64, 0x3, false }, // 411
|
|
{ PseudoVFDIV_VV_MF2_E16_MASK, PseudoVFDIV_VV_MF2_E16, 0x3, false }, // 412
|
|
{ PseudoVFDIV_VV_MF2_E32_MASK, PseudoVFDIV_VV_MF2_E32, 0x3, false }, // 413
|
|
{ PseudoVFDIV_VV_MF4_E16_MASK, PseudoVFDIV_VV_MF4_E16, 0x3, false }, // 414
|
|
{ PseudoVFMACC_VFPR16_M1_MASK, PseudoVFMACC_VFPR16_M1, 0x3, false }, // 415
|
|
{ PseudoVFMACC_VFPR16_M2_MASK, PseudoVFMACC_VFPR16_M2, 0x3, false }, // 416
|
|
{ PseudoVFMACC_VFPR16_M4_MASK, PseudoVFMACC_VFPR16_M4, 0x3, false }, // 417
|
|
{ PseudoVFMACC_VFPR16_M8_MASK, PseudoVFMACC_VFPR16_M8, 0x3, false }, // 418
|
|
{ PseudoVFMACC_VFPR16_MF2_MASK, PseudoVFMACC_VFPR16_MF2, 0x3, false }, // 419
|
|
{ PseudoVFMACC_VFPR16_MF4_MASK, PseudoVFMACC_VFPR16_MF4, 0x3, false }, // 420
|
|
{ PseudoVFMACC_VFPR32_M1_MASK, PseudoVFMACC_VFPR32_M1, 0x3, false }, // 421
|
|
{ PseudoVFMACC_VFPR32_M2_MASK, PseudoVFMACC_VFPR32_M2, 0x3, false }, // 422
|
|
{ PseudoVFMACC_VFPR32_M4_MASK, PseudoVFMACC_VFPR32_M4, 0x3, false }, // 423
|
|
{ PseudoVFMACC_VFPR32_M8_MASK, PseudoVFMACC_VFPR32_M8, 0x3, false }, // 424
|
|
{ PseudoVFMACC_VFPR32_MF2_MASK, PseudoVFMACC_VFPR32_MF2, 0x3, false }, // 425
|
|
{ PseudoVFMACC_VFPR64_M1_MASK, PseudoVFMACC_VFPR64_M1, 0x3, false }, // 426
|
|
{ PseudoVFMACC_VFPR64_M2_MASK, PseudoVFMACC_VFPR64_M2, 0x3, false }, // 427
|
|
{ PseudoVFMACC_VFPR64_M4_MASK, PseudoVFMACC_VFPR64_M4, 0x3, false }, // 428
|
|
{ PseudoVFMACC_VFPR64_M8_MASK, PseudoVFMACC_VFPR64_M8, 0x3, false }, // 429
|
|
{ PseudoVFMACC_VV_M1_MASK, PseudoVFMACC_VV_M1, 0x3, false }, // 430
|
|
{ PseudoVFMACC_VV_M2_MASK, PseudoVFMACC_VV_M2, 0x3, false }, // 431
|
|
{ PseudoVFMACC_VV_M4_MASK, PseudoVFMACC_VV_M4, 0x3, false }, // 432
|
|
{ PseudoVFMACC_VV_M8_MASK, PseudoVFMACC_VV_M8, 0x3, false }, // 433
|
|
{ PseudoVFMACC_VV_MF2_MASK, PseudoVFMACC_VV_MF2, 0x3, false }, // 434
|
|
{ PseudoVFMACC_VV_MF4_MASK, PseudoVFMACC_VV_MF4, 0x3, false }, // 435
|
|
{ PseudoVFMADD_VFPR16_M1_MASK, PseudoVFMADD_VFPR16_M1, 0x3, false }, // 436
|
|
{ PseudoVFMADD_VFPR16_M2_MASK, PseudoVFMADD_VFPR16_M2, 0x3, false }, // 437
|
|
{ PseudoVFMADD_VFPR16_M4_MASK, PseudoVFMADD_VFPR16_M4, 0x3, false }, // 438
|
|
{ PseudoVFMADD_VFPR16_M8_MASK, PseudoVFMADD_VFPR16_M8, 0x3, false }, // 439
|
|
{ PseudoVFMADD_VFPR16_MF2_MASK, PseudoVFMADD_VFPR16_MF2, 0x3, false }, // 440
|
|
{ PseudoVFMADD_VFPR16_MF4_MASK, PseudoVFMADD_VFPR16_MF4, 0x3, false }, // 441
|
|
{ PseudoVFMADD_VFPR32_M1_MASK, PseudoVFMADD_VFPR32_M1, 0x3, false }, // 442
|
|
{ PseudoVFMADD_VFPR32_M2_MASK, PseudoVFMADD_VFPR32_M2, 0x3, false }, // 443
|
|
{ PseudoVFMADD_VFPR32_M4_MASK, PseudoVFMADD_VFPR32_M4, 0x3, false }, // 444
|
|
{ PseudoVFMADD_VFPR32_M8_MASK, PseudoVFMADD_VFPR32_M8, 0x3, false }, // 445
|
|
{ PseudoVFMADD_VFPR32_MF2_MASK, PseudoVFMADD_VFPR32_MF2, 0x3, false }, // 446
|
|
{ PseudoVFMADD_VFPR64_M1_MASK, PseudoVFMADD_VFPR64_M1, 0x3, false }, // 447
|
|
{ PseudoVFMADD_VFPR64_M2_MASK, PseudoVFMADD_VFPR64_M2, 0x3, false }, // 448
|
|
{ PseudoVFMADD_VFPR64_M4_MASK, PseudoVFMADD_VFPR64_M4, 0x3, false }, // 449
|
|
{ PseudoVFMADD_VFPR64_M8_MASK, PseudoVFMADD_VFPR64_M8, 0x3, false }, // 450
|
|
{ PseudoVFMADD_VV_M1_MASK, PseudoVFMADD_VV_M1, 0x3, false }, // 451
|
|
{ PseudoVFMADD_VV_M2_MASK, PseudoVFMADD_VV_M2, 0x3, false }, // 452
|
|
{ PseudoVFMADD_VV_M4_MASK, PseudoVFMADD_VV_M4, 0x3, false }, // 453
|
|
{ PseudoVFMADD_VV_M8_MASK, PseudoVFMADD_VV_M8, 0x3, false }, // 454
|
|
{ PseudoVFMADD_VV_MF2_MASK, PseudoVFMADD_VV_MF2, 0x3, false }, // 455
|
|
{ PseudoVFMADD_VV_MF4_MASK, PseudoVFMADD_VV_MF4, 0x3, false }, // 456
|
|
{ PseudoVFMAX_VFPR16_M1_MASK, PseudoVFMAX_VFPR16_M1, 0x3, false }, // 457
|
|
{ PseudoVFMAX_VFPR16_M2_MASK, PseudoVFMAX_VFPR16_M2, 0x3, false }, // 458
|
|
{ PseudoVFMAX_VFPR16_M4_MASK, PseudoVFMAX_VFPR16_M4, 0x3, false }, // 459
|
|
{ PseudoVFMAX_VFPR16_M8_MASK, PseudoVFMAX_VFPR16_M8, 0x3, false }, // 460
|
|
{ PseudoVFMAX_VFPR16_MF2_MASK, PseudoVFMAX_VFPR16_MF2, 0x3, false }, // 461
|
|
{ PseudoVFMAX_VFPR16_MF4_MASK, PseudoVFMAX_VFPR16_MF4, 0x3, false }, // 462
|
|
{ PseudoVFMAX_VFPR32_M1_MASK, PseudoVFMAX_VFPR32_M1, 0x3, false }, // 463
|
|
{ PseudoVFMAX_VFPR32_M2_MASK, PseudoVFMAX_VFPR32_M2, 0x3, false }, // 464
|
|
{ PseudoVFMAX_VFPR32_M4_MASK, PseudoVFMAX_VFPR32_M4, 0x3, false }, // 465
|
|
{ PseudoVFMAX_VFPR32_M8_MASK, PseudoVFMAX_VFPR32_M8, 0x3, false }, // 466
|
|
{ PseudoVFMAX_VFPR32_MF2_MASK, PseudoVFMAX_VFPR32_MF2, 0x3, false }, // 467
|
|
{ PseudoVFMAX_VFPR64_M1_MASK, PseudoVFMAX_VFPR64_M1, 0x3, false }, // 468
|
|
{ PseudoVFMAX_VFPR64_M2_MASK, PseudoVFMAX_VFPR64_M2, 0x3, false }, // 469
|
|
{ PseudoVFMAX_VFPR64_M4_MASK, PseudoVFMAX_VFPR64_M4, 0x3, false }, // 470
|
|
{ PseudoVFMAX_VFPR64_M8_MASK, PseudoVFMAX_VFPR64_M8, 0x3, false }, // 471
|
|
{ PseudoVFMAX_VV_M1_MASK, PseudoVFMAX_VV_M1, 0x3, false }, // 472
|
|
{ PseudoVFMAX_VV_M2_MASK, PseudoVFMAX_VV_M2, 0x3, false }, // 473
|
|
{ PseudoVFMAX_VV_M4_MASK, PseudoVFMAX_VV_M4, 0x3, false }, // 474
|
|
{ PseudoVFMAX_VV_M8_MASK, PseudoVFMAX_VV_M8, 0x3, false }, // 475
|
|
{ PseudoVFMAX_VV_MF2_MASK, PseudoVFMAX_VV_MF2, 0x3, false }, // 476
|
|
{ PseudoVFMAX_VV_MF4_MASK, PseudoVFMAX_VV_MF4, 0x3, false }, // 477
|
|
{ PseudoVFMIN_VFPR16_M1_MASK, PseudoVFMIN_VFPR16_M1, 0x3, false }, // 478
|
|
{ PseudoVFMIN_VFPR16_M2_MASK, PseudoVFMIN_VFPR16_M2, 0x3, false }, // 479
|
|
{ PseudoVFMIN_VFPR16_M4_MASK, PseudoVFMIN_VFPR16_M4, 0x3, false }, // 480
|
|
{ PseudoVFMIN_VFPR16_M8_MASK, PseudoVFMIN_VFPR16_M8, 0x3, false }, // 481
|
|
{ PseudoVFMIN_VFPR16_MF2_MASK, PseudoVFMIN_VFPR16_MF2, 0x3, false }, // 482
|
|
{ PseudoVFMIN_VFPR16_MF4_MASK, PseudoVFMIN_VFPR16_MF4, 0x3, false }, // 483
|
|
{ PseudoVFMIN_VFPR32_M1_MASK, PseudoVFMIN_VFPR32_M1, 0x3, false }, // 484
|
|
{ PseudoVFMIN_VFPR32_M2_MASK, PseudoVFMIN_VFPR32_M2, 0x3, false }, // 485
|
|
{ PseudoVFMIN_VFPR32_M4_MASK, PseudoVFMIN_VFPR32_M4, 0x3, false }, // 486
|
|
{ PseudoVFMIN_VFPR32_M8_MASK, PseudoVFMIN_VFPR32_M8, 0x3, false }, // 487
|
|
{ PseudoVFMIN_VFPR32_MF2_MASK, PseudoVFMIN_VFPR32_MF2, 0x3, false }, // 488
|
|
{ PseudoVFMIN_VFPR64_M1_MASK, PseudoVFMIN_VFPR64_M1, 0x3, false }, // 489
|
|
{ PseudoVFMIN_VFPR64_M2_MASK, PseudoVFMIN_VFPR64_M2, 0x3, false }, // 490
|
|
{ PseudoVFMIN_VFPR64_M4_MASK, PseudoVFMIN_VFPR64_M4, 0x3, false }, // 491
|
|
{ PseudoVFMIN_VFPR64_M8_MASK, PseudoVFMIN_VFPR64_M8, 0x3, false }, // 492
|
|
{ PseudoVFMIN_VV_M1_MASK, PseudoVFMIN_VV_M1, 0x3, false }, // 493
|
|
{ PseudoVFMIN_VV_M2_MASK, PseudoVFMIN_VV_M2, 0x3, false }, // 494
|
|
{ PseudoVFMIN_VV_M4_MASK, PseudoVFMIN_VV_M4, 0x3, false }, // 495
|
|
{ PseudoVFMIN_VV_M8_MASK, PseudoVFMIN_VV_M8, 0x3, false }, // 496
|
|
{ PseudoVFMIN_VV_MF2_MASK, PseudoVFMIN_VV_MF2, 0x3, false }, // 497
|
|
{ PseudoVFMIN_VV_MF4_MASK, PseudoVFMIN_VV_MF4, 0x3, false }, // 498
|
|
{ PseudoVFMSAC_VFPR16_M1_MASK, PseudoVFMSAC_VFPR16_M1, 0x3, false }, // 499
|
|
{ PseudoVFMSAC_VFPR16_M2_MASK, PseudoVFMSAC_VFPR16_M2, 0x3, false }, // 500
|
|
{ PseudoVFMSAC_VFPR16_M4_MASK, PseudoVFMSAC_VFPR16_M4, 0x3, false }, // 501
|
|
{ PseudoVFMSAC_VFPR16_M8_MASK, PseudoVFMSAC_VFPR16_M8, 0x3, false }, // 502
|
|
{ PseudoVFMSAC_VFPR16_MF2_MASK, PseudoVFMSAC_VFPR16_MF2, 0x3, false }, // 503
|
|
{ PseudoVFMSAC_VFPR16_MF4_MASK, PseudoVFMSAC_VFPR16_MF4, 0x3, false }, // 504
|
|
{ PseudoVFMSAC_VFPR32_M1_MASK, PseudoVFMSAC_VFPR32_M1, 0x3, false }, // 505
|
|
{ PseudoVFMSAC_VFPR32_M2_MASK, PseudoVFMSAC_VFPR32_M2, 0x3, false }, // 506
|
|
{ PseudoVFMSAC_VFPR32_M4_MASK, PseudoVFMSAC_VFPR32_M4, 0x3, false }, // 507
|
|
{ PseudoVFMSAC_VFPR32_M8_MASK, PseudoVFMSAC_VFPR32_M8, 0x3, false }, // 508
|
|
{ PseudoVFMSAC_VFPR32_MF2_MASK, PseudoVFMSAC_VFPR32_MF2, 0x3, false }, // 509
|
|
{ PseudoVFMSAC_VFPR64_M1_MASK, PseudoVFMSAC_VFPR64_M1, 0x3, false }, // 510
|
|
{ PseudoVFMSAC_VFPR64_M2_MASK, PseudoVFMSAC_VFPR64_M2, 0x3, false }, // 511
|
|
{ PseudoVFMSAC_VFPR64_M4_MASK, PseudoVFMSAC_VFPR64_M4, 0x3, false }, // 512
|
|
{ PseudoVFMSAC_VFPR64_M8_MASK, PseudoVFMSAC_VFPR64_M8, 0x3, false }, // 513
|
|
{ PseudoVFMSAC_VV_M1_MASK, PseudoVFMSAC_VV_M1, 0x3, false }, // 514
|
|
{ PseudoVFMSAC_VV_M2_MASK, PseudoVFMSAC_VV_M2, 0x3, false }, // 515
|
|
{ PseudoVFMSAC_VV_M4_MASK, PseudoVFMSAC_VV_M4, 0x3, false }, // 516
|
|
{ PseudoVFMSAC_VV_M8_MASK, PseudoVFMSAC_VV_M8, 0x3, false }, // 517
|
|
{ PseudoVFMSAC_VV_MF2_MASK, PseudoVFMSAC_VV_MF2, 0x3, false }, // 518
|
|
{ PseudoVFMSAC_VV_MF4_MASK, PseudoVFMSAC_VV_MF4, 0x3, false }, // 519
|
|
{ PseudoVFMSUB_VFPR16_M1_MASK, PseudoVFMSUB_VFPR16_M1, 0x3, false }, // 520
|
|
{ PseudoVFMSUB_VFPR16_M2_MASK, PseudoVFMSUB_VFPR16_M2, 0x3, false }, // 521
|
|
{ PseudoVFMSUB_VFPR16_M4_MASK, PseudoVFMSUB_VFPR16_M4, 0x3, false }, // 522
|
|
{ PseudoVFMSUB_VFPR16_M8_MASK, PseudoVFMSUB_VFPR16_M8, 0x3, false }, // 523
|
|
{ PseudoVFMSUB_VFPR16_MF2_MASK, PseudoVFMSUB_VFPR16_MF2, 0x3, false }, // 524
|
|
{ PseudoVFMSUB_VFPR16_MF4_MASK, PseudoVFMSUB_VFPR16_MF4, 0x3, false }, // 525
|
|
{ PseudoVFMSUB_VFPR32_M1_MASK, PseudoVFMSUB_VFPR32_M1, 0x3, false }, // 526
|
|
{ PseudoVFMSUB_VFPR32_M2_MASK, PseudoVFMSUB_VFPR32_M2, 0x3, false }, // 527
|
|
{ PseudoVFMSUB_VFPR32_M4_MASK, PseudoVFMSUB_VFPR32_M4, 0x3, false }, // 528
|
|
{ PseudoVFMSUB_VFPR32_M8_MASK, PseudoVFMSUB_VFPR32_M8, 0x3, false }, // 529
|
|
{ PseudoVFMSUB_VFPR32_MF2_MASK, PseudoVFMSUB_VFPR32_MF2, 0x3, false }, // 530
|
|
{ PseudoVFMSUB_VFPR64_M1_MASK, PseudoVFMSUB_VFPR64_M1, 0x3, false }, // 531
|
|
{ PseudoVFMSUB_VFPR64_M2_MASK, PseudoVFMSUB_VFPR64_M2, 0x3, false }, // 532
|
|
{ PseudoVFMSUB_VFPR64_M4_MASK, PseudoVFMSUB_VFPR64_M4, 0x3, false }, // 533
|
|
{ PseudoVFMSUB_VFPR64_M8_MASK, PseudoVFMSUB_VFPR64_M8, 0x3, false }, // 534
|
|
{ PseudoVFMSUB_VV_M1_MASK, PseudoVFMSUB_VV_M1, 0x3, false }, // 535
|
|
{ PseudoVFMSUB_VV_M2_MASK, PseudoVFMSUB_VV_M2, 0x3, false }, // 536
|
|
{ PseudoVFMSUB_VV_M4_MASK, PseudoVFMSUB_VV_M4, 0x3, false }, // 537
|
|
{ PseudoVFMSUB_VV_M8_MASK, PseudoVFMSUB_VV_M8, 0x3, false }, // 538
|
|
{ PseudoVFMSUB_VV_MF2_MASK, PseudoVFMSUB_VV_MF2, 0x3, false }, // 539
|
|
{ PseudoVFMSUB_VV_MF4_MASK, PseudoVFMSUB_VV_MF4, 0x3, false }, // 540
|
|
{ PseudoVFMUL_VFPR16_M1_MASK, PseudoVFMUL_VFPR16_M1, 0x3, false }, // 541
|
|
{ PseudoVFMUL_VFPR16_M2_MASK, PseudoVFMUL_VFPR16_M2, 0x3, false }, // 542
|
|
{ PseudoVFMUL_VFPR16_M4_MASK, PseudoVFMUL_VFPR16_M4, 0x3, false }, // 543
|
|
{ PseudoVFMUL_VFPR16_M8_MASK, PseudoVFMUL_VFPR16_M8, 0x3, false }, // 544
|
|
{ PseudoVFMUL_VFPR16_MF2_MASK, PseudoVFMUL_VFPR16_MF2, 0x3, false }, // 545
|
|
{ PseudoVFMUL_VFPR16_MF4_MASK, PseudoVFMUL_VFPR16_MF4, 0x3, false }, // 546
|
|
{ PseudoVFMUL_VFPR32_M1_MASK, PseudoVFMUL_VFPR32_M1, 0x3, false }, // 547
|
|
{ PseudoVFMUL_VFPR32_M2_MASK, PseudoVFMUL_VFPR32_M2, 0x3, false }, // 548
|
|
{ PseudoVFMUL_VFPR32_M4_MASK, PseudoVFMUL_VFPR32_M4, 0x3, false }, // 549
|
|
{ PseudoVFMUL_VFPR32_M8_MASK, PseudoVFMUL_VFPR32_M8, 0x3, false }, // 550
|
|
{ PseudoVFMUL_VFPR32_MF2_MASK, PseudoVFMUL_VFPR32_MF2, 0x3, false }, // 551
|
|
{ PseudoVFMUL_VFPR64_M1_MASK, PseudoVFMUL_VFPR64_M1, 0x3, false }, // 552
|
|
{ PseudoVFMUL_VFPR64_M2_MASK, PseudoVFMUL_VFPR64_M2, 0x3, false }, // 553
|
|
{ PseudoVFMUL_VFPR64_M4_MASK, PseudoVFMUL_VFPR64_M4, 0x3, false }, // 554
|
|
{ PseudoVFMUL_VFPR64_M8_MASK, PseudoVFMUL_VFPR64_M8, 0x3, false }, // 555
|
|
{ PseudoVFMUL_VV_M1_MASK, PseudoVFMUL_VV_M1, 0x3, false }, // 556
|
|
{ PseudoVFMUL_VV_M2_MASK, PseudoVFMUL_VV_M2, 0x3, false }, // 557
|
|
{ PseudoVFMUL_VV_M4_MASK, PseudoVFMUL_VV_M4, 0x3, false }, // 558
|
|
{ PseudoVFMUL_VV_M8_MASK, PseudoVFMUL_VV_M8, 0x3, false }, // 559
|
|
{ PseudoVFMUL_VV_MF2_MASK, PseudoVFMUL_VV_MF2, 0x3, false }, // 560
|
|
{ PseudoVFMUL_VV_MF4_MASK, PseudoVFMUL_VV_MF4, 0x3, false }, // 561
|
|
{ PseudoVFNCVTBF16_F_F_W_M1_MASK, PseudoVFNCVTBF16_F_F_W_M1, 0x2, false }, // 562
|
|
{ PseudoVFNCVTBF16_F_F_W_M2_MASK, PseudoVFNCVTBF16_F_F_W_M2, 0x2, false }, // 563
|
|
{ PseudoVFNCVTBF16_F_F_W_M4_MASK, PseudoVFNCVTBF16_F_F_W_M4, 0x2, false }, // 564
|
|
{ PseudoVFNCVTBF16_F_F_W_MF2_MASK, PseudoVFNCVTBF16_F_F_W_MF2, 0x2, false }, // 565
|
|
{ PseudoVFNCVTBF16_F_F_W_MF4_MASK, PseudoVFNCVTBF16_F_F_W_MF4, 0x2, false }, // 566
|
|
{ PseudoVFNCVT_F_F_W_M1_MASK, PseudoVFNCVT_F_F_W_M1, 0x2, false }, // 567
|
|
{ PseudoVFNCVT_F_F_W_M2_MASK, PseudoVFNCVT_F_F_W_M2, 0x2, false }, // 568
|
|
{ PseudoVFNCVT_F_F_W_M4_MASK, PseudoVFNCVT_F_F_W_M4, 0x2, false }, // 569
|
|
{ PseudoVFNCVT_F_F_W_MF2_MASK, PseudoVFNCVT_F_F_W_MF2, 0x2, false }, // 570
|
|
{ PseudoVFNCVT_F_F_W_MF4_MASK, PseudoVFNCVT_F_F_W_MF4, 0x2, false }, // 571
|
|
{ PseudoVFNCVT_F_XU_W_M1_MASK, PseudoVFNCVT_F_XU_W_M1, 0x2, false }, // 572
|
|
{ PseudoVFNCVT_F_XU_W_M2_MASK, PseudoVFNCVT_F_XU_W_M2, 0x2, false }, // 573
|
|
{ PseudoVFNCVT_F_XU_W_M4_MASK, PseudoVFNCVT_F_XU_W_M4, 0x2, false }, // 574
|
|
{ PseudoVFNCVT_F_XU_W_MF2_MASK, PseudoVFNCVT_F_XU_W_MF2, 0x2, false }, // 575
|
|
{ PseudoVFNCVT_F_XU_W_MF4_MASK, PseudoVFNCVT_F_XU_W_MF4, 0x2, false }, // 576
|
|
{ PseudoVFNCVT_F_X_W_M1_MASK, PseudoVFNCVT_F_X_W_M1, 0x2, false }, // 577
|
|
{ PseudoVFNCVT_F_X_W_M2_MASK, PseudoVFNCVT_F_X_W_M2, 0x2, false }, // 578
|
|
{ PseudoVFNCVT_F_X_W_M4_MASK, PseudoVFNCVT_F_X_W_M4, 0x2, false }, // 579
|
|
{ PseudoVFNCVT_F_X_W_MF2_MASK, PseudoVFNCVT_F_X_W_MF2, 0x2, false }, // 580
|
|
{ PseudoVFNCVT_F_X_W_MF4_MASK, PseudoVFNCVT_F_X_W_MF4, 0x2, false }, // 581
|
|
{ PseudoVFNCVT_RM_F_XU_W_M1_MASK, PseudoVFNCVT_RM_F_XU_W_M1, 0x2, false }, // 582
|
|
{ PseudoVFNCVT_RM_F_XU_W_M2_MASK, PseudoVFNCVT_RM_F_XU_W_M2, 0x2, false }, // 583
|
|
{ PseudoVFNCVT_RM_F_XU_W_M4_MASK, PseudoVFNCVT_RM_F_XU_W_M4, 0x2, false }, // 584
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF2_MASK, PseudoVFNCVT_RM_F_XU_W_MF2, 0x2, false }, // 585
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF4_MASK, PseudoVFNCVT_RM_F_XU_W_MF4, 0x2, false }, // 586
|
|
{ PseudoVFNCVT_RM_F_X_W_M1_MASK, PseudoVFNCVT_RM_F_X_W_M1, 0x2, false }, // 587
|
|
{ PseudoVFNCVT_RM_F_X_W_M2_MASK, PseudoVFNCVT_RM_F_X_W_M2, 0x2, false }, // 588
|
|
{ PseudoVFNCVT_RM_F_X_W_M4_MASK, PseudoVFNCVT_RM_F_X_W_M4, 0x2, false }, // 589
|
|
{ PseudoVFNCVT_RM_F_X_W_MF2_MASK, PseudoVFNCVT_RM_F_X_W_MF2, 0x2, false }, // 590
|
|
{ PseudoVFNCVT_RM_F_X_W_MF4_MASK, PseudoVFNCVT_RM_F_X_W_MF4, 0x2, false }, // 591
|
|
{ PseudoVFNCVT_RM_XU_F_W_M1_MASK, PseudoVFNCVT_RM_XU_F_W_M1, 0x2, false }, // 592
|
|
{ PseudoVFNCVT_RM_XU_F_W_M2_MASK, PseudoVFNCVT_RM_XU_F_W_M2, 0x2, false }, // 593
|
|
{ PseudoVFNCVT_RM_XU_F_W_M4_MASK, PseudoVFNCVT_RM_XU_F_W_M4, 0x2, false }, // 594
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF2_MASK, PseudoVFNCVT_RM_XU_F_W_MF2, 0x2, false }, // 595
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF4_MASK, PseudoVFNCVT_RM_XU_F_W_MF4, 0x2, false }, // 596
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF8_MASK, PseudoVFNCVT_RM_XU_F_W_MF8, 0x2, false }, // 597
|
|
{ PseudoVFNCVT_RM_X_F_W_M1_MASK, PseudoVFNCVT_RM_X_F_W_M1, 0x2, false }, // 598
|
|
{ PseudoVFNCVT_RM_X_F_W_M2_MASK, PseudoVFNCVT_RM_X_F_W_M2, 0x2, false }, // 599
|
|
{ PseudoVFNCVT_RM_X_F_W_M4_MASK, PseudoVFNCVT_RM_X_F_W_M4, 0x2, false }, // 600
|
|
{ PseudoVFNCVT_RM_X_F_W_MF2_MASK, PseudoVFNCVT_RM_X_F_W_MF2, 0x2, false }, // 601
|
|
{ PseudoVFNCVT_RM_X_F_W_MF4_MASK, PseudoVFNCVT_RM_X_F_W_MF4, 0x2, false }, // 602
|
|
{ PseudoVFNCVT_RM_X_F_W_MF8_MASK, PseudoVFNCVT_RM_X_F_W_MF8, 0x2, false }, // 603
|
|
{ PseudoVFNCVT_ROD_F_F_W_M1_MASK, PseudoVFNCVT_ROD_F_F_W_M1, 0x2, false }, // 604
|
|
{ PseudoVFNCVT_ROD_F_F_W_M2_MASK, PseudoVFNCVT_ROD_F_F_W_M2, 0x2, false }, // 605
|
|
{ PseudoVFNCVT_ROD_F_F_W_M4_MASK, PseudoVFNCVT_ROD_F_F_W_M4, 0x2, false }, // 606
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF2_MASK, PseudoVFNCVT_ROD_F_F_W_MF2, 0x2, false }, // 607
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF4_MASK, PseudoVFNCVT_ROD_F_F_W_MF4, 0x2, false }, // 608
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, PseudoVFNCVT_RTZ_XU_F_W_M1, 0x2, false }, // 609
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, PseudoVFNCVT_RTZ_XU_F_W_M2, 0x2, false }, // 610
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, PseudoVFNCVT_RTZ_XU_F_W_M4, 0x2, false }, // 611
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF2, 0x2, false }, // 612
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF4, 0x2, false }, // 613
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF8, 0x2, false }, // 614
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M1_MASK, PseudoVFNCVT_RTZ_X_F_W_M1, 0x2, false }, // 615
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M2_MASK, PseudoVFNCVT_RTZ_X_F_W_M2, 0x2, false }, // 616
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M4_MASK, PseudoVFNCVT_RTZ_X_F_W_M4, 0x2, false }, // 617
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, PseudoVFNCVT_RTZ_X_F_W_MF2, 0x2, false }, // 618
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, PseudoVFNCVT_RTZ_X_F_W_MF4, 0x2, false }, // 619
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, PseudoVFNCVT_RTZ_X_F_W_MF8, 0x2, false }, // 620
|
|
{ PseudoVFNCVT_XU_F_W_M1_MASK, PseudoVFNCVT_XU_F_W_M1, 0x2, false }, // 621
|
|
{ PseudoVFNCVT_XU_F_W_M2_MASK, PseudoVFNCVT_XU_F_W_M2, 0x2, false }, // 622
|
|
{ PseudoVFNCVT_XU_F_W_M4_MASK, PseudoVFNCVT_XU_F_W_M4, 0x2, false }, // 623
|
|
{ PseudoVFNCVT_XU_F_W_MF2_MASK, PseudoVFNCVT_XU_F_W_MF2, 0x2, false }, // 624
|
|
{ PseudoVFNCVT_XU_F_W_MF4_MASK, PseudoVFNCVT_XU_F_W_MF4, 0x2, false }, // 625
|
|
{ PseudoVFNCVT_XU_F_W_MF8_MASK, PseudoVFNCVT_XU_F_W_MF8, 0x2, false }, // 626
|
|
{ PseudoVFNCVT_X_F_W_M1_MASK, PseudoVFNCVT_X_F_W_M1, 0x2, false }, // 627
|
|
{ PseudoVFNCVT_X_F_W_M2_MASK, PseudoVFNCVT_X_F_W_M2, 0x2, false }, // 628
|
|
{ PseudoVFNCVT_X_F_W_M4_MASK, PseudoVFNCVT_X_F_W_M4, 0x2, false }, // 629
|
|
{ PseudoVFNCVT_X_F_W_MF2_MASK, PseudoVFNCVT_X_F_W_MF2, 0x2, false }, // 630
|
|
{ PseudoVFNCVT_X_F_W_MF4_MASK, PseudoVFNCVT_X_F_W_MF4, 0x2, false }, // 631
|
|
{ PseudoVFNCVT_X_F_W_MF8_MASK, PseudoVFNCVT_X_F_W_MF8, 0x2, false }, // 632
|
|
{ PseudoVFNMACC_VFPR16_M1_MASK, PseudoVFNMACC_VFPR16_M1, 0x3, false }, // 633
|
|
{ PseudoVFNMACC_VFPR16_M2_MASK, PseudoVFNMACC_VFPR16_M2, 0x3, false }, // 634
|
|
{ PseudoVFNMACC_VFPR16_M4_MASK, PseudoVFNMACC_VFPR16_M4, 0x3, false }, // 635
|
|
{ PseudoVFNMACC_VFPR16_M8_MASK, PseudoVFNMACC_VFPR16_M8, 0x3, false }, // 636
|
|
{ PseudoVFNMACC_VFPR16_MF2_MASK, PseudoVFNMACC_VFPR16_MF2, 0x3, false }, // 637
|
|
{ PseudoVFNMACC_VFPR16_MF4_MASK, PseudoVFNMACC_VFPR16_MF4, 0x3, false }, // 638
|
|
{ PseudoVFNMACC_VFPR32_M1_MASK, PseudoVFNMACC_VFPR32_M1, 0x3, false }, // 639
|
|
{ PseudoVFNMACC_VFPR32_M2_MASK, PseudoVFNMACC_VFPR32_M2, 0x3, false }, // 640
|
|
{ PseudoVFNMACC_VFPR32_M4_MASK, PseudoVFNMACC_VFPR32_M4, 0x3, false }, // 641
|
|
{ PseudoVFNMACC_VFPR32_M8_MASK, PseudoVFNMACC_VFPR32_M8, 0x3, false }, // 642
|
|
{ PseudoVFNMACC_VFPR32_MF2_MASK, PseudoVFNMACC_VFPR32_MF2, 0x3, false }, // 643
|
|
{ PseudoVFNMACC_VFPR64_M1_MASK, PseudoVFNMACC_VFPR64_M1, 0x3, false }, // 644
|
|
{ PseudoVFNMACC_VFPR64_M2_MASK, PseudoVFNMACC_VFPR64_M2, 0x3, false }, // 645
|
|
{ PseudoVFNMACC_VFPR64_M4_MASK, PseudoVFNMACC_VFPR64_M4, 0x3, false }, // 646
|
|
{ PseudoVFNMACC_VFPR64_M8_MASK, PseudoVFNMACC_VFPR64_M8, 0x3, false }, // 647
|
|
{ PseudoVFNMACC_VV_M1_MASK, PseudoVFNMACC_VV_M1, 0x3, false }, // 648
|
|
{ PseudoVFNMACC_VV_M2_MASK, PseudoVFNMACC_VV_M2, 0x3, false }, // 649
|
|
{ PseudoVFNMACC_VV_M4_MASK, PseudoVFNMACC_VV_M4, 0x3, false }, // 650
|
|
{ PseudoVFNMACC_VV_M8_MASK, PseudoVFNMACC_VV_M8, 0x3, false }, // 651
|
|
{ PseudoVFNMACC_VV_MF2_MASK, PseudoVFNMACC_VV_MF2, 0x3, false }, // 652
|
|
{ PseudoVFNMACC_VV_MF4_MASK, PseudoVFNMACC_VV_MF4, 0x3, false }, // 653
|
|
{ PseudoVFNMADD_VFPR16_M1_MASK, PseudoVFNMADD_VFPR16_M1, 0x3, false }, // 654
|
|
{ PseudoVFNMADD_VFPR16_M2_MASK, PseudoVFNMADD_VFPR16_M2, 0x3, false }, // 655
|
|
{ PseudoVFNMADD_VFPR16_M4_MASK, PseudoVFNMADD_VFPR16_M4, 0x3, false }, // 656
|
|
{ PseudoVFNMADD_VFPR16_M8_MASK, PseudoVFNMADD_VFPR16_M8, 0x3, false }, // 657
|
|
{ PseudoVFNMADD_VFPR16_MF2_MASK, PseudoVFNMADD_VFPR16_MF2, 0x3, false }, // 658
|
|
{ PseudoVFNMADD_VFPR16_MF4_MASK, PseudoVFNMADD_VFPR16_MF4, 0x3, false }, // 659
|
|
{ PseudoVFNMADD_VFPR32_M1_MASK, PseudoVFNMADD_VFPR32_M1, 0x3, false }, // 660
|
|
{ PseudoVFNMADD_VFPR32_M2_MASK, PseudoVFNMADD_VFPR32_M2, 0x3, false }, // 661
|
|
{ PseudoVFNMADD_VFPR32_M4_MASK, PseudoVFNMADD_VFPR32_M4, 0x3, false }, // 662
|
|
{ PseudoVFNMADD_VFPR32_M8_MASK, PseudoVFNMADD_VFPR32_M8, 0x3, false }, // 663
|
|
{ PseudoVFNMADD_VFPR32_MF2_MASK, PseudoVFNMADD_VFPR32_MF2, 0x3, false }, // 664
|
|
{ PseudoVFNMADD_VFPR64_M1_MASK, PseudoVFNMADD_VFPR64_M1, 0x3, false }, // 665
|
|
{ PseudoVFNMADD_VFPR64_M2_MASK, PseudoVFNMADD_VFPR64_M2, 0x3, false }, // 666
|
|
{ PseudoVFNMADD_VFPR64_M4_MASK, PseudoVFNMADD_VFPR64_M4, 0x3, false }, // 667
|
|
{ PseudoVFNMADD_VFPR64_M8_MASK, PseudoVFNMADD_VFPR64_M8, 0x3, false }, // 668
|
|
{ PseudoVFNMADD_VV_M1_MASK, PseudoVFNMADD_VV_M1, 0x3, false }, // 669
|
|
{ PseudoVFNMADD_VV_M2_MASK, PseudoVFNMADD_VV_M2, 0x3, false }, // 670
|
|
{ PseudoVFNMADD_VV_M4_MASK, PseudoVFNMADD_VV_M4, 0x3, false }, // 671
|
|
{ PseudoVFNMADD_VV_M8_MASK, PseudoVFNMADD_VV_M8, 0x3, false }, // 672
|
|
{ PseudoVFNMADD_VV_MF2_MASK, PseudoVFNMADD_VV_MF2, 0x3, false }, // 673
|
|
{ PseudoVFNMADD_VV_MF4_MASK, PseudoVFNMADD_VV_MF4, 0x3, false }, // 674
|
|
{ PseudoVFNMSAC_VFPR16_M1_MASK, PseudoVFNMSAC_VFPR16_M1, 0x3, false }, // 675
|
|
{ PseudoVFNMSAC_VFPR16_M2_MASK, PseudoVFNMSAC_VFPR16_M2, 0x3, false }, // 676
|
|
{ PseudoVFNMSAC_VFPR16_M4_MASK, PseudoVFNMSAC_VFPR16_M4, 0x3, false }, // 677
|
|
{ PseudoVFNMSAC_VFPR16_M8_MASK, PseudoVFNMSAC_VFPR16_M8, 0x3, false }, // 678
|
|
{ PseudoVFNMSAC_VFPR16_MF2_MASK, PseudoVFNMSAC_VFPR16_MF2, 0x3, false }, // 679
|
|
{ PseudoVFNMSAC_VFPR16_MF4_MASK, PseudoVFNMSAC_VFPR16_MF4, 0x3, false }, // 680
|
|
{ PseudoVFNMSAC_VFPR32_M1_MASK, PseudoVFNMSAC_VFPR32_M1, 0x3, false }, // 681
|
|
{ PseudoVFNMSAC_VFPR32_M2_MASK, PseudoVFNMSAC_VFPR32_M2, 0x3, false }, // 682
|
|
{ PseudoVFNMSAC_VFPR32_M4_MASK, PseudoVFNMSAC_VFPR32_M4, 0x3, false }, // 683
|
|
{ PseudoVFNMSAC_VFPR32_M8_MASK, PseudoVFNMSAC_VFPR32_M8, 0x3, false }, // 684
|
|
{ PseudoVFNMSAC_VFPR32_MF2_MASK, PseudoVFNMSAC_VFPR32_MF2, 0x3, false }, // 685
|
|
{ PseudoVFNMSAC_VFPR64_M1_MASK, PseudoVFNMSAC_VFPR64_M1, 0x3, false }, // 686
|
|
{ PseudoVFNMSAC_VFPR64_M2_MASK, PseudoVFNMSAC_VFPR64_M2, 0x3, false }, // 687
|
|
{ PseudoVFNMSAC_VFPR64_M4_MASK, PseudoVFNMSAC_VFPR64_M4, 0x3, false }, // 688
|
|
{ PseudoVFNMSAC_VFPR64_M8_MASK, PseudoVFNMSAC_VFPR64_M8, 0x3, false }, // 689
|
|
{ PseudoVFNMSAC_VV_M1_MASK, PseudoVFNMSAC_VV_M1, 0x3, false }, // 690
|
|
{ PseudoVFNMSAC_VV_M2_MASK, PseudoVFNMSAC_VV_M2, 0x3, false }, // 691
|
|
{ PseudoVFNMSAC_VV_M4_MASK, PseudoVFNMSAC_VV_M4, 0x3, false }, // 692
|
|
{ PseudoVFNMSAC_VV_M8_MASK, PseudoVFNMSAC_VV_M8, 0x3, false }, // 693
|
|
{ PseudoVFNMSAC_VV_MF2_MASK, PseudoVFNMSAC_VV_MF2, 0x3, false }, // 694
|
|
{ PseudoVFNMSAC_VV_MF4_MASK, PseudoVFNMSAC_VV_MF4, 0x3, false }, // 695
|
|
{ PseudoVFNMSUB_VFPR16_M1_MASK, PseudoVFNMSUB_VFPR16_M1, 0x3, false }, // 696
|
|
{ PseudoVFNMSUB_VFPR16_M2_MASK, PseudoVFNMSUB_VFPR16_M2, 0x3, false }, // 697
|
|
{ PseudoVFNMSUB_VFPR16_M4_MASK, PseudoVFNMSUB_VFPR16_M4, 0x3, false }, // 698
|
|
{ PseudoVFNMSUB_VFPR16_M8_MASK, PseudoVFNMSUB_VFPR16_M8, 0x3, false }, // 699
|
|
{ PseudoVFNMSUB_VFPR16_MF2_MASK, PseudoVFNMSUB_VFPR16_MF2, 0x3, false }, // 700
|
|
{ PseudoVFNMSUB_VFPR16_MF4_MASK, PseudoVFNMSUB_VFPR16_MF4, 0x3, false }, // 701
|
|
{ PseudoVFNMSUB_VFPR32_M1_MASK, PseudoVFNMSUB_VFPR32_M1, 0x3, false }, // 702
|
|
{ PseudoVFNMSUB_VFPR32_M2_MASK, PseudoVFNMSUB_VFPR32_M2, 0x3, false }, // 703
|
|
{ PseudoVFNMSUB_VFPR32_M4_MASK, PseudoVFNMSUB_VFPR32_M4, 0x3, false }, // 704
|
|
{ PseudoVFNMSUB_VFPR32_M8_MASK, PseudoVFNMSUB_VFPR32_M8, 0x3, false }, // 705
|
|
{ PseudoVFNMSUB_VFPR32_MF2_MASK, PseudoVFNMSUB_VFPR32_MF2, 0x3, false }, // 706
|
|
{ PseudoVFNMSUB_VFPR64_M1_MASK, PseudoVFNMSUB_VFPR64_M1, 0x3, false }, // 707
|
|
{ PseudoVFNMSUB_VFPR64_M2_MASK, PseudoVFNMSUB_VFPR64_M2, 0x3, false }, // 708
|
|
{ PseudoVFNMSUB_VFPR64_M4_MASK, PseudoVFNMSUB_VFPR64_M4, 0x3, false }, // 709
|
|
{ PseudoVFNMSUB_VFPR64_M8_MASK, PseudoVFNMSUB_VFPR64_M8, 0x3, false }, // 710
|
|
{ PseudoVFNMSUB_VV_M1_MASK, PseudoVFNMSUB_VV_M1, 0x3, false }, // 711
|
|
{ PseudoVFNMSUB_VV_M2_MASK, PseudoVFNMSUB_VV_M2, 0x3, false }, // 712
|
|
{ PseudoVFNMSUB_VV_M4_MASK, PseudoVFNMSUB_VV_M4, 0x3, false }, // 713
|
|
{ PseudoVFNMSUB_VV_M8_MASK, PseudoVFNMSUB_VV_M8, 0x3, false }, // 714
|
|
{ PseudoVFNMSUB_VV_MF2_MASK, PseudoVFNMSUB_VV_MF2, 0x3, false }, // 715
|
|
{ PseudoVFNMSUB_VV_MF4_MASK, PseudoVFNMSUB_VV_MF4, 0x3, false }, // 716
|
|
{ PseudoVFNRCLIP_XU_F_QF_M1_MASK, PseudoVFNRCLIP_XU_F_QF_M1, 0x3, false }, // 717
|
|
{ PseudoVFNRCLIP_XU_F_QF_M2_MASK, PseudoVFNRCLIP_XU_F_QF_M2, 0x3, false }, // 718
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF2_MASK, PseudoVFNRCLIP_XU_F_QF_MF2, 0x3, false }, // 719
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF4_MASK, PseudoVFNRCLIP_XU_F_QF_MF4, 0x3, false }, // 720
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF8_MASK, PseudoVFNRCLIP_XU_F_QF_MF8, 0x3, false }, // 721
|
|
{ PseudoVFNRCLIP_X_F_QF_M1_MASK, PseudoVFNRCLIP_X_F_QF_M1, 0x3, false }, // 722
|
|
{ PseudoVFNRCLIP_X_F_QF_M2_MASK, PseudoVFNRCLIP_X_F_QF_M2, 0x3, false }, // 723
|
|
{ PseudoVFNRCLIP_X_F_QF_MF2_MASK, PseudoVFNRCLIP_X_F_QF_MF2, 0x3, false }, // 724
|
|
{ PseudoVFNRCLIP_X_F_QF_MF4_MASK, PseudoVFNRCLIP_X_F_QF_MF4, 0x3, false }, // 725
|
|
{ PseudoVFNRCLIP_X_F_QF_MF8_MASK, PseudoVFNRCLIP_X_F_QF_MF8, 0x3, false }, // 726
|
|
{ PseudoVFRDIV_VFPR16_M1_E16_MASK, PseudoVFRDIV_VFPR16_M1_E16, 0x3, false }, // 727
|
|
{ PseudoVFRDIV_VFPR16_M2_E16_MASK, PseudoVFRDIV_VFPR16_M2_E16, 0x3, false }, // 728
|
|
{ PseudoVFRDIV_VFPR16_M4_E16_MASK, PseudoVFRDIV_VFPR16_M4_E16, 0x3, false }, // 729
|
|
{ PseudoVFRDIV_VFPR16_M8_E16_MASK, PseudoVFRDIV_VFPR16_M8_E16, 0x3, false }, // 730
|
|
{ PseudoVFRDIV_VFPR16_MF2_E16_MASK, PseudoVFRDIV_VFPR16_MF2_E16, 0x3, false }, // 731
|
|
{ PseudoVFRDIV_VFPR16_MF4_E16_MASK, PseudoVFRDIV_VFPR16_MF4_E16, 0x3, false }, // 732
|
|
{ PseudoVFRDIV_VFPR32_M1_E32_MASK, PseudoVFRDIV_VFPR32_M1_E32, 0x3, false }, // 733
|
|
{ PseudoVFRDIV_VFPR32_M2_E32_MASK, PseudoVFRDIV_VFPR32_M2_E32, 0x3, false }, // 734
|
|
{ PseudoVFRDIV_VFPR32_M4_E32_MASK, PseudoVFRDIV_VFPR32_M4_E32, 0x3, false }, // 735
|
|
{ PseudoVFRDIV_VFPR32_M8_E32_MASK, PseudoVFRDIV_VFPR32_M8_E32, 0x3, false }, // 736
|
|
{ PseudoVFRDIV_VFPR32_MF2_E32_MASK, PseudoVFRDIV_VFPR32_MF2_E32, 0x3, false }, // 737
|
|
{ PseudoVFRDIV_VFPR64_M1_E64_MASK, PseudoVFRDIV_VFPR64_M1_E64, 0x3, false }, // 738
|
|
{ PseudoVFRDIV_VFPR64_M2_E64_MASK, PseudoVFRDIV_VFPR64_M2_E64, 0x3, false }, // 739
|
|
{ PseudoVFRDIV_VFPR64_M4_E64_MASK, PseudoVFRDIV_VFPR64_M4_E64, 0x3, false }, // 740
|
|
{ PseudoVFRDIV_VFPR64_M8_E64_MASK, PseudoVFRDIV_VFPR64_M8_E64, 0x3, false }, // 741
|
|
{ PseudoVFREC7_V_M1_MASK, PseudoVFREC7_V_M1, 0x2, false }, // 742
|
|
{ PseudoVFREC7_V_M2_MASK, PseudoVFREC7_V_M2, 0x2, false }, // 743
|
|
{ PseudoVFREC7_V_M4_MASK, PseudoVFREC7_V_M4, 0x2, false }, // 744
|
|
{ PseudoVFREC7_V_M8_MASK, PseudoVFREC7_V_M8, 0x2, false }, // 745
|
|
{ PseudoVFREC7_V_MF2_MASK, PseudoVFREC7_V_MF2, 0x2, false }, // 746
|
|
{ PseudoVFREC7_V_MF4_MASK, PseudoVFREC7_V_MF4, 0x2, false }, // 747
|
|
{ PseudoVFREDMAX_VS_M1_E16_MASK, PseudoVFREDMAX_VS_M1_E16, 0x3, true }, // 748
|
|
{ PseudoVFREDMAX_VS_M1_E32_MASK, PseudoVFREDMAX_VS_M1_E32, 0x3, true }, // 749
|
|
{ PseudoVFREDMAX_VS_M1_E64_MASK, PseudoVFREDMAX_VS_M1_E64, 0x3, true }, // 750
|
|
{ PseudoVFREDMAX_VS_M2_E16_MASK, PseudoVFREDMAX_VS_M2_E16, 0x3, true }, // 751
|
|
{ PseudoVFREDMAX_VS_M2_E32_MASK, PseudoVFREDMAX_VS_M2_E32, 0x3, true }, // 752
|
|
{ PseudoVFREDMAX_VS_M2_E64_MASK, PseudoVFREDMAX_VS_M2_E64, 0x3, true }, // 753
|
|
{ PseudoVFREDMAX_VS_M4_E16_MASK, PseudoVFREDMAX_VS_M4_E16, 0x3, true }, // 754
|
|
{ PseudoVFREDMAX_VS_M4_E32_MASK, PseudoVFREDMAX_VS_M4_E32, 0x3, true }, // 755
|
|
{ PseudoVFREDMAX_VS_M4_E64_MASK, PseudoVFREDMAX_VS_M4_E64, 0x3, true }, // 756
|
|
{ PseudoVFREDMAX_VS_M8_E16_MASK, PseudoVFREDMAX_VS_M8_E16, 0x3, true }, // 757
|
|
{ PseudoVFREDMAX_VS_M8_E32_MASK, PseudoVFREDMAX_VS_M8_E32, 0x3, true }, // 758
|
|
{ PseudoVFREDMAX_VS_M8_E64_MASK, PseudoVFREDMAX_VS_M8_E64, 0x3, true }, // 759
|
|
{ PseudoVFREDMAX_VS_MF2_E16_MASK, PseudoVFREDMAX_VS_MF2_E16, 0x3, true }, // 760
|
|
{ PseudoVFREDMAX_VS_MF2_E32_MASK, PseudoVFREDMAX_VS_MF2_E32, 0x3, true }, // 761
|
|
{ PseudoVFREDMAX_VS_MF4_E16_MASK, PseudoVFREDMAX_VS_MF4_E16, 0x3, true }, // 762
|
|
{ PseudoVFREDMIN_VS_M1_E16_MASK, PseudoVFREDMIN_VS_M1_E16, 0x3, true }, // 763
|
|
{ PseudoVFREDMIN_VS_M1_E32_MASK, PseudoVFREDMIN_VS_M1_E32, 0x3, true }, // 764
|
|
{ PseudoVFREDMIN_VS_M1_E64_MASK, PseudoVFREDMIN_VS_M1_E64, 0x3, true }, // 765
|
|
{ PseudoVFREDMIN_VS_M2_E16_MASK, PseudoVFREDMIN_VS_M2_E16, 0x3, true }, // 766
|
|
{ PseudoVFREDMIN_VS_M2_E32_MASK, PseudoVFREDMIN_VS_M2_E32, 0x3, true }, // 767
|
|
{ PseudoVFREDMIN_VS_M2_E64_MASK, PseudoVFREDMIN_VS_M2_E64, 0x3, true }, // 768
|
|
{ PseudoVFREDMIN_VS_M4_E16_MASK, PseudoVFREDMIN_VS_M4_E16, 0x3, true }, // 769
|
|
{ PseudoVFREDMIN_VS_M4_E32_MASK, PseudoVFREDMIN_VS_M4_E32, 0x3, true }, // 770
|
|
{ PseudoVFREDMIN_VS_M4_E64_MASK, PseudoVFREDMIN_VS_M4_E64, 0x3, true }, // 771
|
|
{ PseudoVFREDMIN_VS_M8_E16_MASK, PseudoVFREDMIN_VS_M8_E16, 0x3, true }, // 772
|
|
{ PseudoVFREDMIN_VS_M8_E32_MASK, PseudoVFREDMIN_VS_M8_E32, 0x3, true }, // 773
|
|
{ PseudoVFREDMIN_VS_M8_E64_MASK, PseudoVFREDMIN_VS_M8_E64, 0x3, true }, // 774
|
|
{ PseudoVFREDMIN_VS_MF2_E16_MASK, PseudoVFREDMIN_VS_MF2_E16, 0x3, true }, // 775
|
|
{ PseudoVFREDMIN_VS_MF2_E32_MASK, PseudoVFREDMIN_VS_MF2_E32, 0x3, true }, // 776
|
|
{ PseudoVFREDMIN_VS_MF4_E16_MASK, PseudoVFREDMIN_VS_MF4_E16, 0x3, true }, // 777
|
|
{ PseudoVFREDOSUM_VS_M1_E16_MASK, PseudoVFREDOSUM_VS_M1_E16, 0x3, true }, // 778
|
|
{ PseudoVFREDOSUM_VS_M1_E32_MASK, PseudoVFREDOSUM_VS_M1_E32, 0x3, true }, // 779
|
|
{ PseudoVFREDOSUM_VS_M1_E64_MASK, PseudoVFREDOSUM_VS_M1_E64, 0x3, true }, // 780
|
|
{ PseudoVFREDOSUM_VS_M2_E16_MASK, PseudoVFREDOSUM_VS_M2_E16, 0x3, true }, // 781
|
|
{ PseudoVFREDOSUM_VS_M2_E32_MASK, PseudoVFREDOSUM_VS_M2_E32, 0x3, true }, // 782
|
|
{ PseudoVFREDOSUM_VS_M2_E64_MASK, PseudoVFREDOSUM_VS_M2_E64, 0x3, true }, // 783
|
|
{ PseudoVFREDOSUM_VS_M4_E16_MASK, PseudoVFREDOSUM_VS_M4_E16, 0x3, true }, // 784
|
|
{ PseudoVFREDOSUM_VS_M4_E32_MASK, PseudoVFREDOSUM_VS_M4_E32, 0x3, true }, // 785
|
|
{ PseudoVFREDOSUM_VS_M4_E64_MASK, PseudoVFREDOSUM_VS_M4_E64, 0x3, true }, // 786
|
|
{ PseudoVFREDOSUM_VS_M8_E16_MASK, PseudoVFREDOSUM_VS_M8_E16, 0x3, true }, // 787
|
|
{ PseudoVFREDOSUM_VS_M8_E32_MASK, PseudoVFREDOSUM_VS_M8_E32, 0x3, true }, // 788
|
|
{ PseudoVFREDOSUM_VS_M8_E64_MASK, PseudoVFREDOSUM_VS_M8_E64, 0x3, true }, // 789
|
|
{ PseudoVFREDOSUM_VS_MF2_E16_MASK, PseudoVFREDOSUM_VS_MF2_E16, 0x3, true }, // 790
|
|
{ PseudoVFREDOSUM_VS_MF2_E32_MASK, PseudoVFREDOSUM_VS_MF2_E32, 0x3, true }, // 791
|
|
{ PseudoVFREDOSUM_VS_MF4_E16_MASK, PseudoVFREDOSUM_VS_MF4_E16, 0x3, true }, // 792
|
|
{ PseudoVFREDUSUM_VS_M1_E16_MASK, PseudoVFREDUSUM_VS_M1_E16, 0x3, true }, // 793
|
|
{ PseudoVFREDUSUM_VS_M1_E32_MASK, PseudoVFREDUSUM_VS_M1_E32, 0x3, true }, // 794
|
|
{ PseudoVFREDUSUM_VS_M1_E64_MASK, PseudoVFREDUSUM_VS_M1_E64, 0x3, true }, // 795
|
|
{ PseudoVFREDUSUM_VS_M2_E16_MASK, PseudoVFREDUSUM_VS_M2_E16, 0x3, true }, // 796
|
|
{ PseudoVFREDUSUM_VS_M2_E32_MASK, PseudoVFREDUSUM_VS_M2_E32, 0x3, true }, // 797
|
|
{ PseudoVFREDUSUM_VS_M2_E64_MASK, PseudoVFREDUSUM_VS_M2_E64, 0x3, true }, // 798
|
|
{ PseudoVFREDUSUM_VS_M4_E16_MASK, PseudoVFREDUSUM_VS_M4_E16, 0x3, true }, // 799
|
|
{ PseudoVFREDUSUM_VS_M4_E32_MASK, PseudoVFREDUSUM_VS_M4_E32, 0x3, true }, // 800
|
|
{ PseudoVFREDUSUM_VS_M4_E64_MASK, PseudoVFREDUSUM_VS_M4_E64, 0x3, true }, // 801
|
|
{ PseudoVFREDUSUM_VS_M8_E16_MASK, PseudoVFREDUSUM_VS_M8_E16, 0x3, true }, // 802
|
|
{ PseudoVFREDUSUM_VS_M8_E32_MASK, PseudoVFREDUSUM_VS_M8_E32, 0x3, true }, // 803
|
|
{ PseudoVFREDUSUM_VS_M8_E64_MASK, PseudoVFREDUSUM_VS_M8_E64, 0x3, true }, // 804
|
|
{ PseudoVFREDUSUM_VS_MF2_E16_MASK, PseudoVFREDUSUM_VS_MF2_E16, 0x3, true }, // 805
|
|
{ PseudoVFREDUSUM_VS_MF2_E32_MASK, PseudoVFREDUSUM_VS_MF2_E32, 0x3, true }, // 806
|
|
{ PseudoVFREDUSUM_VS_MF4_E16_MASK, PseudoVFREDUSUM_VS_MF4_E16, 0x3, true }, // 807
|
|
{ PseudoVFRSQRT7_V_M1_MASK, PseudoVFRSQRT7_V_M1, 0x2, false }, // 808
|
|
{ PseudoVFRSQRT7_V_M2_MASK, PseudoVFRSQRT7_V_M2, 0x2, false }, // 809
|
|
{ PseudoVFRSQRT7_V_M4_MASK, PseudoVFRSQRT7_V_M4, 0x2, false }, // 810
|
|
{ PseudoVFRSQRT7_V_M8_MASK, PseudoVFRSQRT7_V_M8, 0x2, false }, // 811
|
|
{ PseudoVFRSQRT7_V_MF2_MASK, PseudoVFRSQRT7_V_MF2, 0x2, false }, // 812
|
|
{ PseudoVFRSQRT7_V_MF4_MASK, PseudoVFRSQRT7_V_MF4, 0x2, false }, // 813
|
|
{ PseudoVFRSUB_VFPR16_M1_MASK, PseudoVFRSUB_VFPR16_M1, 0x3, false }, // 814
|
|
{ PseudoVFRSUB_VFPR16_M2_MASK, PseudoVFRSUB_VFPR16_M2, 0x3, false }, // 815
|
|
{ PseudoVFRSUB_VFPR16_M4_MASK, PseudoVFRSUB_VFPR16_M4, 0x3, false }, // 816
|
|
{ PseudoVFRSUB_VFPR16_M8_MASK, PseudoVFRSUB_VFPR16_M8, 0x3, false }, // 817
|
|
{ PseudoVFRSUB_VFPR16_MF2_MASK, PseudoVFRSUB_VFPR16_MF2, 0x3, false }, // 818
|
|
{ PseudoVFRSUB_VFPR16_MF4_MASK, PseudoVFRSUB_VFPR16_MF4, 0x3, false }, // 819
|
|
{ PseudoVFRSUB_VFPR32_M1_MASK, PseudoVFRSUB_VFPR32_M1, 0x3, false }, // 820
|
|
{ PseudoVFRSUB_VFPR32_M2_MASK, PseudoVFRSUB_VFPR32_M2, 0x3, false }, // 821
|
|
{ PseudoVFRSUB_VFPR32_M4_MASK, PseudoVFRSUB_VFPR32_M4, 0x3, false }, // 822
|
|
{ PseudoVFRSUB_VFPR32_M8_MASK, PseudoVFRSUB_VFPR32_M8, 0x3, false }, // 823
|
|
{ PseudoVFRSUB_VFPR32_MF2_MASK, PseudoVFRSUB_VFPR32_MF2, 0x3, false }, // 824
|
|
{ PseudoVFRSUB_VFPR64_M1_MASK, PseudoVFRSUB_VFPR64_M1, 0x3, false }, // 825
|
|
{ PseudoVFRSUB_VFPR64_M2_MASK, PseudoVFRSUB_VFPR64_M2, 0x3, false }, // 826
|
|
{ PseudoVFRSUB_VFPR64_M4_MASK, PseudoVFRSUB_VFPR64_M4, 0x3, false }, // 827
|
|
{ PseudoVFRSUB_VFPR64_M8_MASK, PseudoVFRSUB_VFPR64_M8, 0x3, false }, // 828
|
|
{ PseudoVFSGNJN_VFPR16_M1_MASK, PseudoVFSGNJN_VFPR16_M1, 0x3, false }, // 829
|
|
{ PseudoVFSGNJN_VFPR16_M2_MASK, PseudoVFSGNJN_VFPR16_M2, 0x3, false }, // 830
|
|
{ PseudoVFSGNJN_VFPR16_M4_MASK, PseudoVFSGNJN_VFPR16_M4, 0x3, false }, // 831
|
|
{ PseudoVFSGNJN_VFPR16_M8_MASK, PseudoVFSGNJN_VFPR16_M8, 0x3, false }, // 832
|
|
{ PseudoVFSGNJN_VFPR16_MF2_MASK, PseudoVFSGNJN_VFPR16_MF2, 0x3, false }, // 833
|
|
{ PseudoVFSGNJN_VFPR16_MF4_MASK, PseudoVFSGNJN_VFPR16_MF4, 0x3, false }, // 834
|
|
{ PseudoVFSGNJN_VFPR32_M1_MASK, PseudoVFSGNJN_VFPR32_M1, 0x3, false }, // 835
|
|
{ PseudoVFSGNJN_VFPR32_M2_MASK, PseudoVFSGNJN_VFPR32_M2, 0x3, false }, // 836
|
|
{ PseudoVFSGNJN_VFPR32_M4_MASK, PseudoVFSGNJN_VFPR32_M4, 0x3, false }, // 837
|
|
{ PseudoVFSGNJN_VFPR32_M8_MASK, PseudoVFSGNJN_VFPR32_M8, 0x3, false }, // 838
|
|
{ PseudoVFSGNJN_VFPR32_MF2_MASK, PseudoVFSGNJN_VFPR32_MF2, 0x3, false }, // 839
|
|
{ PseudoVFSGNJN_VFPR64_M1_MASK, PseudoVFSGNJN_VFPR64_M1, 0x3, false }, // 840
|
|
{ PseudoVFSGNJN_VFPR64_M2_MASK, PseudoVFSGNJN_VFPR64_M2, 0x3, false }, // 841
|
|
{ PseudoVFSGNJN_VFPR64_M4_MASK, PseudoVFSGNJN_VFPR64_M4, 0x3, false }, // 842
|
|
{ PseudoVFSGNJN_VFPR64_M8_MASK, PseudoVFSGNJN_VFPR64_M8, 0x3, false }, // 843
|
|
{ PseudoVFSGNJN_VV_M1_MASK, PseudoVFSGNJN_VV_M1, 0x3, false }, // 844
|
|
{ PseudoVFSGNJN_VV_M2_MASK, PseudoVFSGNJN_VV_M2, 0x3, false }, // 845
|
|
{ PseudoVFSGNJN_VV_M4_MASK, PseudoVFSGNJN_VV_M4, 0x3, false }, // 846
|
|
{ PseudoVFSGNJN_VV_M8_MASK, PseudoVFSGNJN_VV_M8, 0x3, false }, // 847
|
|
{ PseudoVFSGNJN_VV_MF2_MASK, PseudoVFSGNJN_VV_MF2, 0x3, false }, // 848
|
|
{ PseudoVFSGNJN_VV_MF4_MASK, PseudoVFSGNJN_VV_MF4, 0x3, false }, // 849
|
|
{ PseudoVFSGNJX_VFPR16_M1_MASK, PseudoVFSGNJX_VFPR16_M1, 0x3, false }, // 850
|
|
{ PseudoVFSGNJX_VFPR16_M2_MASK, PseudoVFSGNJX_VFPR16_M2, 0x3, false }, // 851
|
|
{ PseudoVFSGNJX_VFPR16_M4_MASK, PseudoVFSGNJX_VFPR16_M4, 0x3, false }, // 852
|
|
{ PseudoVFSGNJX_VFPR16_M8_MASK, PseudoVFSGNJX_VFPR16_M8, 0x3, false }, // 853
|
|
{ PseudoVFSGNJX_VFPR16_MF2_MASK, PseudoVFSGNJX_VFPR16_MF2, 0x3, false }, // 854
|
|
{ PseudoVFSGNJX_VFPR16_MF4_MASK, PseudoVFSGNJX_VFPR16_MF4, 0x3, false }, // 855
|
|
{ PseudoVFSGNJX_VFPR32_M1_MASK, PseudoVFSGNJX_VFPR32_M1, 0x3, false }, // 856
|
|
{ PseudoVFSGNJX_VFPR32_M2_MASK, PseudoVFSGNJX_VFPR32_M2, 0x3, false }, // 857
|
|
{ PseudoVFSGNJX_VFPR32_M4_MASK, PseudoVFSGNJX_VFPR32_M4, 0x3, false }, // 858
|
|
{ PseudoVFSGNJX_VFPR32_M8_MASK, PseudoVFSGNJX_VFPR32_M8, 0x3, false }, // 859
|
|
{ PseudoVFSGNJX_VFPR32_MF2_MASK, PseudoVFSGNJX_VFPR32_MF2, 0x3, false }, // 860
|
|
{ PseudoVFSGNJX_VFPR64_M1_MASK, PseudoVFSGNJX_VFPR64_M1, 0x3, false }, // 861
|
|
{ PseudoVFSGNJX_VFPR64_M2_MASK, PseudoVFSGNJX_VFPR64_M2, 0x3, false }, // 862
|
|
{ PseudoVFSGNJX_VFPR64_M4_MASK, PseudoVFSGNJX_VFPR64_M4, 0x3, false }, // 863
|
|
{ PseudoVFSGNJX_VFPR64_M8_MASK, PseudoVFSGNJX_VFPR64_M8, 0x3, false }, // 864
|
|
{ PseudoVFSGNJX_VV_M1_MASK, PseudoVFSGNJX_VV_M1, 0x3, false }, // 865
|
|
{ PseudoVFSGNJX_VV_M2_MASK, PseudoVFSGNJX_VV_M2, 0x3, false }, // 866
|
|
{ PseudoVFSGNJX_VV_M4_MASK, PseudoVFSGNJX_VV_M4, 0x3, false }, // 867
|
|
{ PseudoVFSGNJX_VV_M8_MASK, PseudoVFSGNJX_VV_M8, 0x3, false }, // 868
|
|
{ PseudoVFSGNJX_VV_MF2_MASK, PseudoVFSGNJX_VV_MF2, 0x3, false }, // 869
|
|
{ PseudoVFSGNJX_VV_MF4_MASK, PseudoVFSGNJX_VV_MF4, 0x3, false }, // 870
|
|
{ PseudoVFSGNJ_VFPR16_M1_MASK, PseudoVFSGNJ_VFPR16_M1, 0x3, false }, // 871
|
|
{ PseudoVFSGNJ_VFPR16_M2_MASK, PseudoVFSGNJ_VFPR16_M2, 0x3, false }, // 872
|
|
{ PseudoVFSGNJ_VFPR16_M4_MASK, PseudoVFSGNJ_VFPR16_M4, 0x3, false }, // 873
|
|
{ PseudoVFSGNJ_VFPR16_M8_MASK, PseudoVFSGNJ_VFPR16_M8, 0x3, false }, // 874
|
|
{ PseudoVFSGNJ_VFPR16_MF2_MASK, PseudoVFSGNJ_VFPR16_MF2, 0x3, false }, // 875
|
|
{ PseudoVFSGNJ_VFPR16_MF4_MASK, PseudoVFSGNJ_VFPR16_MF4, 0x3, false }, // 876
|
|
{ PseudoVFSGNJ_VFPR32_M1_MASK, PseudoVFSGNJ_VFPR32_M1, 0x3, false }, // 877
|
|
{ PseudoVFSGNJ_VFPR32_M2_MASK, PseudoVFSGNJ_VFPR32_M2, 0x3, false }, // 878
|
|
{ PseudoVFSGNJ_VFPR32_M4_MASK, PseudoVFSGNJ_VFPR32_M4, 0x3, false }, // 879
|
|
{ PseudoVFSGNJ_VFPR32_M8_MASK, PseudoVFSGNJ_VFPR32_M8, 0x3, false }, // 880
|
|
{ PseudoVFSGNJ_VFPR32_MF2_MASK, PseudoVFSGNJ_VFPR32_MF2, 0x3, false }, // 881
|
|
{ PseudoVFSGNJ_VFPR64_M1_MASK, PseudoVFSGNJ_VFPR64_M1, 0x3, false }, // 882
|
|
{ PseudoVFSGNJ_VFPR64_M2_MASK, PseudoVFSGNJ_VFPR64_M2, 0x3, false }, // 883
|
|
{ PseudoVFSGNJ_VFPR64_M4_MASK, PseudoVFSGNJ_VFPR64_M4, 0x3, false }, // 884
|
|
{ PseudoVFSGNJ_VFPR64_M8_MASK, PseudoVFSGNJ_VFPR64_M8, 0x3, false }, // 885
|
|
{ PseudoVFSGNJ_VV_M1_MASK, PseudoVFSGNJ_VV_M1, 0x3, false }, // 886
|
|
{ PseudoVFSGNJ_VV_M2_MASK, PseudoVFSGNJ_VV_M2, 0x3, false }, // 887
|
|
{ PseudoVFSGNJ_VV_M4_MASK, PseudoVFSGNJ_VV_M4, 0x3, false }, // 888
|
|
{ PseudoVFSGNJ_VV_M8_MASK, PseudoVFSGNJ_VV_M8, 0x3, false }, // 889
|
|
{ PseudoVFSGNJ_VV_MF2_MASK, PseudoVFSGNJ_VV_MF2, 0x3, false }, // 890
|
|
{ PseudoVFSGNJ_VV_MF4_MASK, PseudoVFSGNJ_VV_MF4, 0x3, false }, // 891
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, PseudoVFSLIDE1DOWN_VFPR16_M1, 0x3, false }, // 892
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, PseudoVFSLIDE1DOWN_VFPR16_M2, 0x3, false }, // 893
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, PseudoVFSLIDE1DOWN_VFPR16_M4, 0x3, false }, // 894
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, PseudoVFSLIDE1DOWN_VFPR16_M8, 0x3, false }, // 895
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF2, 0x3, false }, // 896
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF4, 0x3, false }, // 897
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, PseudoVFSLIDE1DOWN_VFPR32_M1, 0x3, false }, // 898
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, PseudoVFSLIDE1DOWN_VFPR32_M2, 0x3, false }, // 899
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, PseudoVFSLIDE1DOWN_VFPR32_M4, 0x3, false }, // 900
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, PseudoVFSLIDE1DOWN_VFPR32_M8, 0x3, false }, // 901
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR32_MF2, 0x3, false }, // 902
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, PseudoVFSLIDE1DOWN_VFPR64_M1, 0x3, false }, // 903
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, PseudoVFSLIDE1DOWN_VFPR64_M2, 0x3, false }, // 904
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, PseudoVFSLIDE1DOWN_VFPR64_M4, 0x3, false }, // 905
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, PseudoVFSLIDE1DOWN_VFPR64_M8, 0x3, false }, // 906
|
|
{ PseudoVFSLIDE1UP_VFPR16_M1_MASK, PseudoVFSLIDE1UP_VFPR16_M1, 0x3, false }, // 907
|
|
{ PseudoVFSLIDE1UP_VFPR16_M2_MASK, PseudoVFSLIDE1UP_VFPR16_M2, 0x3, false }, // 908
|
|
{ PseudoVFSLIDE1UP_VFPR16_M4_MASK, PseudoVFSLIDE1UP_VFPR16_M4, 0x3, false }, // 909
|
|
{ PseudoVFSLIDE1UP_VFPR16_M8_MASK, PseudoVFSLIDE1UP_VFPR16_M8, 0x3, false }, // 910
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF2_MASK, PseudoVFSLIDE1UP_VFPR16_MF2, 0x3, false }, // 911
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF4_MASK, PseudoVFSLIDE1UP_VFPR16_MF4, 0x3, false }, // 912
|
|
{ PseudoVFSLIDE1UP_VFPR32_M1_MASK, PseudoVFSLIDE1UP_VFPR32_M1, 0x3, false }, // 913
|
|
{ PseudoVFSLIDE1UP_VFPR32_M2_MASK, PseudoVFSLIDE1UP_VFPR32_M2, 0x3, false }, // 914
|
|
{ PseudoVFSLIDE1UP_VFPR32_M4_MASK, PseudoVFSLIDE1UP_VFPR32_M4, 0x3, false }, // 915
|
|
{ PseudoVFSLIDE1UP_VFPR32_M8_MASK, PseudoVFSLIDE1UP_VFPR32_M8, 0x3, false }, // 916
|
|
{ PseudoVFSLIDE1UP_VFPR32_MF2_MASK, PseudoVFSLIDE1UP_VFPR32_MF2, 0x3, false }, // 917
|
|
{ PseudoVFSLIDE1UP_VFPR64_M1_MASK, PseudoVFSLIDE1UP_VFPR64_M1, 0x3, false }, // 918
|
|
{ PseudoVFSLIDE1UP_VFPR64_M2_MASK, PseudoVFSLIDE1UP_VFPR64_M2, 0x3, false }, // 919
|
|
{ PseudoVFSLIDE1UP_VFPR64_M4_MASK, PseudoVFSLIDE1UP_VFPR64_M4, 0x3, false }, // 920
|
|
{ PseudoVFSLIDE1UP_VFPR64_M8_MASK, PseudoVFSLIDE1UP_VFPR64_M8, 0x3, false }, // 921
|
|
{ PseudoVFSQRT_V_M1_E16_MASK, PseudoVFSQRT_V_M1_E16, 0x2, false }, // 922
|
|
{ PseudoVFSQRT_V_M1_E32_MASK, PseudoVFSQRT_V_M1_E32, 0x2, false }, // 923
|
|
{ PseudoVFSQRT_V_M1_E64_MASK, PseudoVFSQRT_V_M1_E64, 0x2, false }, // 924
|
|
{ PseudoVFSQRT_V_M2_E16_MASK, PseudoVFSQRT_V_M2_E16, 0x2, false }, // 925
|
|
{ PseudoVFSQRT_V_M2_E32_MASK, PseudoVFSQRT_V_M2_E32, 0x2, false }, // 926
|
|
{ PseudoVFSQRT_V_M2_E64_MASK, PseudoVFSQRT_V_M2_E64, 0x2, false }, // 927
|
|
{ PseudoVFSQRT_V_M4_E16_MASK, PseudoVFSQRT_V_M4_E16, 0x2, false }, // 928
|
|
{ PseudoVFSQRT_V_M4_E32_MASK, PseudoVFSQRT_V_M4_E32, 0x2, false }, // 929
|
|
{ PseudoVFSQRT_V_M4_E64_MASK, PseudoVFSQRT_V_M4_E64, 0x2, false }, // 930
|
|
{ PseudoVFSQRT_V_M8_E16_MASK, PseudoVFSQRT_V_M8_E16, 0x2, false }, // 931
|
|
{ PseudoVFSQRT_V_M8_E32_MASK, PseudoVFSQRT_V_M8_E32, 0x2, false }, // 932
|
|
{ PseudoVFSQRT_V_M8_E64_MASK, PseudoVFSQRT_V_M8_E64, 0x2, false }, // 933
|
|
{ PseudoVFSQRT_V_MF2_E16_MASK, PseudoVFSQRT_V_MF2_E16, 0x2, false }, // 934
|
|
{ PseudoVFSQRT_V_MF2_E32_MASK, PseudoVFSQRT_V_MF2_E32, 0x2, false }, // 935
|
|
{ PseudoVFSQRT_V_MF4_E16_MASK, PseudoVFSQRT_V_MF4_E16, 0x2, false }, // 936
|
|
{ PseudoVFSUB_VFPR16_M1_MASK, PseudoVFSUB_VFPR16_M1, 0x3, false }, // 937
|
|
{ PseudoVFSUB_VFPR16_M2_MASK, PseudoVFSUB_VFPR16_M2, 0x3, false }, // 938
|
|
{ PseudoVFSUB_VFPR16_M4_MASK, PseudoVFSUB_VFPR16_M4, 0x3, false }, // 939
|
|
{ PseudoVFSUB_VFPR16_M8_MASK, PseudoVFSUB_VFPR16_M8, 0x3, false }, // 940
|
|
{ PseudoVFSUB_VFPR16_MF2_MASK, PseudoVFSUB_VFPR16_MF2, 0x3, false }, // 941
|
|
{ PseudoVFSUB_VFPR16_MF4_MASK, PseudoVFSUB_VFPR16_MF4, 0x3, false }, // 942
|
|
{ PseudoVFSUB_VFPR32_M1_MASK, PseudoVFSUB_VFPR32_M1, 0x3, false }, // 943
|
|
{ PseudoVFSUB_VFPR32_M2_MASK, PseudoVFSUB_VFPR32_M2, 0x3, false }, // 944
|
|
{ PseudoVFSUB_VFPR32_M4_MASK, PseudoVFSUB_VFPR32_M4, 0x3, false }, // 945
|
|
{ PseudoVFSUB_VFPR32_M8_MASK, PseudoVFSUB_VFPR32_M8, 0x3, false }, // 946
|
|
{ PseudoVFSUB_VFPR32_MF2_MASK, PseudoVFSUB_VFPR32_MF2, 0x3, false }, // 947
|
|
{ PseudoVFSUB_VFPR64_M1_MASK, PseudoVFSUB_VFPR64_M1, 0x3, false }, // 948
|
|
{ PseudoVFSUB_VFPR64_M2_MASK, PseudoVFSUB_VFPR64_M2, 0x3, false }, // 949
|
|
{ PseudoVFSUB_VFPR64_M4_MASK, PseudoVFSUB_VFPR64_M4, 0x3, false }, // 950
|
|
{ PseudoVFSUB_VFPR64_M8_MASK, PseudoVFSUB_VFPR64_M8, 0x3, false }, // 951
|
|
{ PseudoVFSUB_VV_M1_MASK, PseudoVFSUB_VV_M1, 0x3, false }, // 952
|
|
{ PseudoVFSUB_VV_M2_MASK, PseudoVFSUB_VV_M2, 0x3, false }, // 953
|
|
{ PseudoVFSUB_VV_M4_MASK, PseudoVFSUB_VV_M4, 0x3, false }, // 954
|
|
{ PseudoVFSUB_VV_M8_MASK, PseudoVFSUB_VV_M8, 0x3, false }, // 955
|
|
{ PseudoVFSUB_VV_MF2_MASK, PseudoVFSUB_VV_MF2, 0x3, false }, // 956
|
|
{ PseudoVFSUB_VV_MF4_MASK, PseudoVFSUB_VV_MF4, 0x3, false }, // 957
|
|
{ PseudoVFWADD_VFPR16_M1_MASK, PseudoVFWADD_VFPR16_M1, 0x3, false }, // 958
|
|
{ PseudoVFWADD_VFPR16_M2_MASK, PseudoVFWADD_VFPR16_M2, 0x3, false }, // 959
|
|
{ PseudoVFWADD_VFPR16_M4_MASK, PseudoVFWADD_VFPR16_M4, 0x3, false }, // 960
|
|
{ PseudoVFWADD_VFPR16_MF2_MASK, PseudoVFWADD_VFPR16_MF2, 0x3, false }, // 961
|
|
{ PseudoVFWADD_VFPR16_MF4_MASK, PseudoVFWADD_VFPR16_MF4, 0x3, false }, // 962
|
|
{ PseudoVFWADD_VFPR32_M1_MASK, PseudoVFWADD_VFPR32_M1, 0x3, false }, // 963
|
|
{ PseudoVFWADD_VFPR32_M2_MASK, PseudoVFWADD_VFPR32_M2, 0x3, false }, // 964
|
|
{ PseudoVFWADD_VFPR32_M4_MASK, PseudoVFWADD_VFPR32_M4, 0x3, false }, // 965
|
|
{ PseudoVFWADD_VFPR32_MF2_MASK, PseudoVFWADD_VFPR32_MF2, 0x3, false }, // 966
|
|
{ PseudoVFWADD_VV_M1_MASK, PseudoVFWADD_VV_M1, 0x3, false }, // 967
|
|
{ PseudoVFWADD_VV_M2_MASK, PseudoVFWADD_VV_M2, 0x3, false }, // 968
|
|
{ PseudoVFWADD_VV_M4_MASK, PseudoVFWADD_VV_M4, 0x3, false }, // 969
|
|
{ PseudoVFWADD_VV_MF2_MASK, PseudoVFWADD_VV_MF2, 0x3, false }, // 970
|
|
{ PseudoVFWADD_VV_MF4_MASK, PseudoVFWADD_VV_MF4, 0x3, false }, // 971
|
|
{ PseudoVFWADD_WFPR16_M1_MASK, PseudoVFWADD_WFPR16_M1, 0x3, false }, // 972
|
|
{ PseudoVFWADD_WFPR16_M2_MASK, PseudoVFWADD_WFPR16_M2, 0x3, false }, // 973
|
|
{ PseudoVFWADD_WFPR16_M4_MASK, PseudoVFWADD_WFPR16_M4, 0x3, false }, // 974
|
|
{ PseudoVFWADD_WFPR16_MF2_MASK, PseudoVFWADD_WFPR16_MF2, 0x3, false }, // 975
|
|
{ PseudoVFWADD_WFPR16_MF4_MASK, PseudoVFWADD_WFPR16_MF4, 0x3, false }, // 976
|
|
{ PseudoVFWADD_WFPR32_M1_MASK, PseudoVFWADD_WFPR32_M1, 0x3, false }, // 977
|
|
{ PseudoVFWADD_WFPR32_M2_MASK, PseudoVFWADD_WFPR32_M2, 0x3, false }, // 978
|
|
{ PseudoVFWADD_WFPR32_M4_MASK, PseudoVFWADD_WFPR32_M4, 0x3, false }, // 979
|
|
{ PseudoVFWADD_WFPR32_MF2_MASK, PseudoVFWADD_WFPR32_MF2, 0x3, false }, // 980
|
|
{ PseudoVFWADD_WV_M1_MASK, PseudoVFWADD_WV_M1, 0x3, false }, // 981
|
|
{ PseudoVFWADD_WV_M2_MASK, PseudoVFWADD_WV_M2, 0x3, false }, // 982
|
|
{ PseudoVFWADD_WV_M4_MASK, PseudoVFWADD_WV_M4, 0x3, false }, // 983
|
|
{ PseudoVFWADD_WV_MF2_MASK, PseudoVFWADD_WV_MF2, 0x3, false }, // 984
|
|
{ PseudoVFWADD_WV_MF4_MASK, PseudoVFWADD_WV_MF4, 0x3, false }, // 985
|
|
{ PseudoVFWCVTBF16_F_F_V_M1_MASK, PseudoVFWCVTBF16_F_F_V_M1, 0x2, false }, // 986
|
|
{ PseudoVFWCVTBF16_F_F_V_M2_MASK, PseudoVFWCVTBF16_F_F_V_M2, 0x2, false }, // 987
|
|
{ PseudoVFWCVTBF16_F_F_V_M4_MASK, PseudoVFWCVTBF16_F_F_V_M4, 0x2, false }, // 988
|
|
{ PseudoVFWCVTBF16_F_F_V_MF2_MASK, PseudoVFWCVTBF16_F_F_V_MF2, 0x2, false }, // 989
|
|
{ PseudoVFWCVTBF16_F_F_V_MF4_MASK, PseudoVFWCVTBF16_F_F_V_MF4, 0x2, false }, // 990
|
|
{ PseudoVFWCVT_F_F_V_M1_MASK, PseudoVFWCVT_F_F_V_M1, 0x2, false }, // 991
|
|
{ PseudoVFWCVT_F_F_V_M2_MASK, PseudoVFWCVT_F_F_V_M2, 0x2, false }, // 992
|
|
{ PseudoVFWCVT_F_F_V_M4_MASK, PseudoVFWCVT_F_F_V_M4, 0x2, false }, // 993
|
|
{ PseudoVFWCVT_F_F_V_MF2_MASK, PseudoVFWCVT_F_F_V_MF2, 0x2, false }, // 994
|
|
{ PseudoVFWCVT_F_F_V_MF4_MASK, PseudoVFWCVT_F_F_V_MF4, 0x2, false }, // 995
|
|
{ PseudoVFWCVT_F_XU_V_M1_MASK, PseudoVFWCVT_F_XU_V_M1, 0x2, false }, // 996
|
|
{ PseudoVFWCVT_F_XU_V_M2_MASK, PseudoVFWCVT_F_XU_V_M2, 0x2, false }, // 997
|
|
{ PseudoVFWCVT_F_XU_V_M4_MASK, PseudoVFWCVT_F_XU_V_M4, 0x2, false }, // 998
|
|
{ PseudoVFWCVT_F_XU_V_MF2_MASK, PseudoVFWCVT_F_XU_V_MF2, 0x2, false }, // 999
|
|
{ PseudoVFWCVT_F_XU_V_MF4_MASK, PseudoVFWCVT_F_XU_V_MF4, 0x2, false }, // 1000
|
|
{ PseudoVFWCVT_F_XU_V_MF8_MASK, PseudoVFWCVT_F_XU_V_MF8, 0x2, false }, // 1001
|
|
{ PseudoVFWCVT_F_X_V_M1_MASK, PseudoVFWCVT_F_X_V_M1, 0x2, false }, // 1002
|
|
{ PseudoVFWCVT_F_X_V_M2_MASK, PseudoVFWCVT_F_X_V_M2, 0x2, false }, // 1003
|
|
{ PseudoVFWCVT_F_X_V_M4_MASK, PseudoVFWCVT_F_X_V_M4, 0x2, false }, // 1004
|
|
{ PseudoVFWCVT_F_X_V_MF2_MASK, PseudoVFWCVT_F_X_V_MF2, 0x2, false }, // 1005
|
|
{ PseudoVFWCVT_F_X_V_MF4_MASK, PseudoVFWCVT_F_X_V_MF4, 0x2, false }, // 1006
|
|
{ PseudoVFWCVT_F_X_V_MF8_MASK, PseudoVFWCVT_F_X_V_MF8, 0x2, false }, // 1007
|
|
{ PseudoVFWCVT_RM_XU_F_V_M1_MASK, PseudoVFWCVT_RM_XU_F_V_M1, 0x2, false }, // 1008
|
|
{ PseudoVFWCVT_RM_XU_F_V_M2_MASK, PseudoVFWCVT_RM_XU_F_V_M2, 0x2, false }, // 1009
|
|
{ PseudoVFWCVT_RM_XU_F_V_M4_MASK, PseudoVFWCVT_RM_XU_F_V_M4, 0x2, false }, // 1010
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF2_MASK, PseudoVFWCVT_RM_XU_F_V_MF2, 0x2, false }, // 1011
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF4_MASK, PseudoVFWCVT_RM_XU_F_V_MF4, 0x2, false }, // 1012
|
|
{ PseudoVFWCVT_RM_X_F_V_M1_MASK, PseudoVFWCVT_RM_X_F_V_M1, 0x2, false }, // 1013
|
|
{ PseudoVFWCVT_RM_X_F_V_M2_MASK, PseudoVFWCVT_RM_X_F_V_M2, 0x2, false }, // 1014
|
|
{ PseudoVFWCVT_RM_X_F_V_M4_MASK, PseudoVFWCVT_RM_X_F_V_M4, 0x2, false }, // 1015
|
|
{ PseudoVFWCVT_RM_X_F_V_MF2_MASK, PseudoVFWCVT_RM_X_F_V_MF2, 0x2, false }, // 1016
|
|
{ PseudoVFWCVT_RM_X_F_V_MF4_MASK, PseudoVFWCVT_RM_X_F_V_MF4, 0x2, false }, // 1017
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, PseudoVFWCVT_RTZ_XU_F_V_M1, 0x2, false }, // 1018
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, PseudoVFWCVT_RTZ_XU_F_V_M2, 0x2, false }, // 1019
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, PseudoVFWCVT_RTZ_XU_F_V_M4, 0x2, false }, // 1020
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF2, 0x2, false }, // 1021
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF4, 0x2, false }, // 1022
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M1_MASK, PseudoVFWCVT_RTZ_X_F_V_M1, 0x2, false }, // 1023
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M2_MASK, PseudoVFWCVT_RTZ_X_F_V_M2, 0x2, false }, // 1024
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M4_MASK, PseudoVFWCVT_RTZ_X_F_V_M4, 0x2, false }, // 1025
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, PseudoVFWCVT_RTZ_X_F_V_MF2, 0x2, false }, // 1026
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, PseudoVFWCVT_RTZ_X_F_V_MF4, 0x2, false }, // 1027
|
|
{ PseudoVFWCVT_XU_F_V_M1_MASK, PseudoVFWCVT_XU_F_V_M1, 0x2, false }, // 1028
|
|
{ PseudoVFWCVT_XU_F_V_M2_MASK, PseudoVFWCVT_XU_F_V_M2, 0x2, false }, // 1029
|
|
{ PseudoVFWCVT_XU_F_V_M4_MASK, PseudoVFWCVT_XU_F_V_M4, 0x2, false }, // 1030
|
|
{ PseudoVFWCVT_XU_F_V_MF2_MASK, PseudoVFWCVT_XU_F_V_MF2, 0x2, false }, // 1031
|
|
{ PseudoVFWCVT_XU_F_V_MF4_MASK, PseudoVFWCVT_XU_F_V_MF4, 0x2, false }, // 1032
|
|
{ PseudoVFWCVT_X_F_V_M1_MASK, PseudoVFWCVT_X_F_V_M1, 0x2, false }, // 1033
|
|
{ PseudoVFWCVT_X_F_V_M2_MASK, PseudoVFWCVT_X_F_V_M2, 0x2, false }, // 1034
|
|
{ PseudoVFWCVT_X_F_V_M4_MASK, PseudoVFWCVT_X_F_V_M4, 0x2, false }, // 1035
|
|
{ PseudoVFWCVT_X_F_V_MF2_MASK, PseudoVFWCVT_X_F_V_MF2, 0x2, false }, // 1036
|
|
{ PseudoVFWCVT_X_F_V_MF4_MASK, PseudoVFWCVT_X_F_V_MF4, 0x2, false }, // 1037
|
|
{ PseudoVFWMACCBF16_VFPR16_M1_MASK, PseudoVFWMACCBF16_VFPR16_M1, 0x3, false }, // 1038
|
|
{ PseudoVFWMACCBF16_VFPR16_M2_MASK, PseudoVFWMACCBF16_VFPR16_M2, 0x3, false }, // 1039
|
|
{ PseudoVFWMACCBF16_VFPR16_M4_MASK, PseudoVFWMACCBF16_VFPR16_M4, 0x3, false }, // 1040
|
|
{ PseudoVFWMACCBF16_VFPR16_MF2_MASK, PseudoVFWMACCBF16_VFPR16_MF2, 0x3, false }, // 1041
|
|
{ PseudoVFWMACCBF16_VFPR16_MF4_MASK, PseudoVFWMACCBF16_VFPR16_MF4, 0x3, false }, // 1042
|
|
{ PseudoVFWMACCBF16_VV_M1_MASK, PseudoVFWMACCBF16_VV_M1, 0x3, false }, // 1043
|
|
{ PseudoVFWMACCBF16_VV_M2_MASK, PseudoVFWMACCBF16_VV_M2, 0x3, false }, // 1044
|
|
{ PseudoVFWMACCBF16_VV_M4_MASK, PseudoVFWMACCBF16_VV_M4, 0x3, false }, // 1045
|
|
{ PseudoVFWMACCBF16_VV_MF2_MASK, PseudoVFWMACCBF16_VV_MF2, 0x3, false }, // 1046
|
|
{ PseudoVFWMACCBF16_VV_MF4_MASK, PseudoVFWMACCBF16_VV_MF4, 0x3, false }, // 1047
|
|
{ PseudoVFWMACC_VFPR16_M1_MASK, PseudoVFWMACC_VFPR16_M1, 0x3, false }, // 1048
|
|
{ PseudoVFWMACC_VFPR16_M2_MASK, PseudoVFWMACC_VFPR16_M2, 0x3, false }, // 1049
|
|
{ PseudoVFWMACC_VFPR16_M4_MASK, PseudoVFWMACC_VFPR16_M4, 0x3, false }, // 1050
|
|
{ PseudoVFWMACC_VFPR16_MF2_MASK, PseudoVFWMACC_VFPR16_MF2, 0x3, false }, // 1051
|
|
{ PseudoVFWMACC_VFPR16_MF4_MASK, PseudoVFWMACC_VFPR16_MF4, 0x3, false }, // 1052
|
|
{ PseudoVFWMACC_VFPR32_M1_MASK, PseudoVFWMACC_VFPR32_M1, 0x3, false }, // 1053
|
|
{ PseudoVFWMACC_VFPR32_M2_MASK, PseudoVFWMACC_VFPR32_M2, 0x3, false }, // 1054
|
|
{ PseudoVFWMACC_VFPR32_M4_MASK, PseudoVFWMACC_VFPR32_M4, 0x3, false }, // 1055
|
|
{ PseudoVFWMACC_VFPR32_MF2_MASK, PseudoVFWMACC_VFPR32_MF2, 0x3, false }, // 1056
|
|
{ PseudoVFWMACC_VV_M1_MASK, PseudoVFWMACC_VV_M1, 0x3, false }, // 1057
|
|
{ PseudoVFWMACC_VV_M2_MASK, PseudoVFWMACC_VV_M2, 0x3, false }, // 1058
|
|
{ PseudoVFWMACC_VV_M4_MASK, PseudoVFWMACC_VV_M4, 0x3, false }, // 1059
|
|
{ PseudoVFWMACC_VV_MF2_MASK, PseudoVFWMACC_VV_MF2, 0x3, false }, // 1060
|
|
{ PseudoVFWMACC_VV_MF4_MASK, PseudoVFWMACC_VV_MF4, 0x3, false }, // 1061
|
|
{ PseudoVFWMSAC_VFPR16_M1_MASK, PseudoVFWMSAC_VFPR16_M1, 0x3, false }, // 1062
|
|
{ PseudoVFWMSAC_VFPR16_M2_MASK, PseudoVFWMSAC_VFPR16_M2, 0x3, false }, // 1063
|
|
{ PseudoVFWMSAC_VFPR16_M4_MASK, PseudoVFWMSAC_VFPR16_M4, 0x3, false }, // 1064
|
|
{ PseudoVFWMSAC_VFPR16_MF2_MASK, PseudoVFWMSAC_VFPR16_MF2, 0x3, false }, // 1065
|
|
{ PseudoVFWMSAC_VFPR16_MF4_MASK, PseudoVFWMSAC_VFPR16_MF4, 0x3, false }, // 1066
|
|
{ PseudoVFWMSAC_VFPR32_M1_MASK, PseudoVFWMSAC_VFPR32_M1, 0x3, false }, // 1067
|
|
{ PseudoVFWMSAC_VFPR32_M2_MASK, PseudoVFWMSAC_VFPR32_M2, 0x3, false }, // 1068
|
|
{ PseudoVFWMSAC_VFPR32_M4_MASK, PseudoVFWMSAC_VFPR32_M4, 0x3, false }, // 1069
|
|
{ PseudoVFWMSAC_VFPR32_MF2_MASK, PseudoVFWMSAC_VFPR32_MF2, 0x3, false }, // 1070
|
|
{ PseudoVFWMSAC_VV_M1_MASK, PseudoVFWMSAC_VV_M1, 0x3, false }, // 1071
|
|
{ PseudoVFWMSAC_VV_M2_MASK, PseudoVFWMSAC_VV_M2, 0x3, false }, // 1072
|
|
{ PseudoVFWMSAC_VV_M4_MASK, PseudoVFWMSAC_VV_M4, 0x3, false }, // 1073
|
|
{ PseudoVFWMSAC_VV_MF2_MASK, PseudoVFWMSAC_VV_MF2, 0x3, false }, // 1074
|
|
{ PseudoVFWMSAC_VV_MF4_MASK, PseudoVFWMSAC_VV_MF4, 0x3, false }, // 1075
|
|
{ PseudoVFWMUL_VFPR16_M1_MASK, PseudoVFWMUL_VFPR16_M1, 0x3, false }, // 1076
|
|
{ PseudoVFWMUL_VFPR16_M2_MASK, PseudoVFWMUL_VFPR16_M2, 0x3, false }, // 1077
|
|
{ PseudoVFWMUL_VFPR16_M4_MASK, PseudoVFWMUL_VFPR16_M4, 0x3, false }, // 1078
|
|
{ PseudoVFWMUL_VFPR16_MF2_MASK, PseudoVFWMUL_VFPR16_MF2, 0x3, false }, // 1079
|
|
{ PseudoVFWMUL_VFPR16_MF4_MASK, PseudoVFWMUL_VFPR16_MF4, 0x3, false }, // 1080
|
|
{ PseudoVFWMUL_VFPR32_M1_MASK, PseudoVFWMUL_VFPR32_M1, 0x3, false }, // 1081
|
|
{ PseudoVFWMUL_VFPR32_M2_MASK, PseudoVFWMUL_VFPR32_M2, 0x3, false }, // 1082
|
|
{ PseudoVFWMUL_VFPR32_M4_MASK, PseudoVFWMUL_VFPR32_M4, 0x3, false }, // 1083
|
|
{ PseudoVFWMUL_VFPR32_MF2_MASK, PseudoVFWMUL_VFPR32_MF2, 0x3, false }, // 1084
|
|
{ PseudoVFWMUL_VV_M1_MASK, PseudoVFWMUL_VV_M1, 0x3, false }, // 1085
|
|
{ PseudoVFWMUL_VV_M2_MASK, PseudoVFWMUL_VV_M2, 0x3, false }, // 1086
|
|
{ PseudoVFWMUL_VV_M4_MASK, PseudoVFWMUL_VV_M4, 0x3, false }, // 1087
|
|
{ PseudoVFWMUL_VV_MF2_MASK, PseudoVFWMUL_VV_MF2, 0x3, false }, // 1088
|
|
{ PseudoVFWMUL_VV_MF4_MASK, PseudoVFWMUL_VV_MF4, 0x3, false }, // 1089
|
|
{ PseudoVFWNMACC_VFPR16_M1_MASK, PseudoVFWNMACC_VFPR16_M1, 0x3, false }, // 1090
|
|
{ PseudoVFWNMACC_VFPR16_M2_MASK, PseudoVFWNMACC_VFPR16_M2, 0x3, false }, // 1091
|
|
{ PseudoVFWNMACC_VFPR16_M4_MASK, PseudoVFWNMACC_VFPR16_M4, 0x3, false }, // 1092
|
|
{ PseudoVFWNMACC_VFPR16_MF2_MASK, PseudoVFWNMACC_VFPR16_MF2, 0x3, false }, // 1093
|
|
{ PseudoVFWNMACC_VFPR16_MF4_MASK, PseudoVFWNMACC_VFPR16_MF4, 0x3, false }, // 1094
|
|
{ PseudoVFWNMACC_VFPR32_M1_MASK, PseudoVFWNMACC_VFPR32_M1, 0x3, false }, // 1095
|
|
{ PseudoVFWNMACC_VFPR32_M2_MASK, PseudoVFWNMACC_VFPR32_M2, 0x3, false }, // 1096
|
|
{ PseudoVFWNMACC_VFPR32_M4_MASK, PseudoVFWNMACC_VFPR32_M4, 0x3, false }, // 1097
|
|
{ PseudoVFWNMACC_VFPR32_MF2_MASK, PseudoVFWNMACC_VFPR32_MF2, 0x3, false }, // 1098
|
|
{ PseudoVFWNMACC_VV_M1_MASK, PseudoVFWNMACC_VV_M1, 0x3, false }, // 1099
|
|
{ PseudoVFWNMACC_VV_M2_MASK, PseudoVFWNMACC_VV_M2, 0x3, false }, // 1100
|
|
{ PseudoVFWNMACC_VV_M4_MASK, PseudoVFWNMACC_VV_M4, 0x3, false }, // 1101
|
|
{ PseudoVFWNMACC_VV_MF2_MASK, PseudoVFWNMACC_VV_MF2, 0x3, false }, // 1102
|
|
{ PseudoVFWNMACC_VV_MF4_MASK, PseudoVFWNMACC_VV_MF4, 0x3, false }, // 1103
|
|
{ PseudoVFWNMSAC_VFPR16_M1_MASK, PseudoVFWNMSAC_VFPR16_M1, 0x3, false }, // 1104
|
|
{ PseudoVFWNMSAC_VFPR16_M2_MASK, PseudoVFWNMSAC_VFPR16_M2, 0x3, false }, // 1105
|
|
{ PseudoVFWNMSAC_VFPR16_M4_MASK, PseudoVFWNMSAC_VFPR16_M4, 0x3, false }, // 1106
|
|
{ PseudoVFWNMSAC_VFPR16_MF2_MASK, PseudoVFWNMSAC_VFPR16_MF2, 0x3, false }, // 1107
|
|
{ PseudoVFWNMSAC_VFPR16_MF4_MASK, PseudoVFWNMSAC_VFPR16_MF4, 0x3, false }, // 1108
|
|
{ PseudoVFWNMSAC_VFPR32_M1_MASK, PseudoVFWNMSAC_VFPR32_M1, 0x3, false }, // 1109
|
|
{ PseudoVFWNMSAC_VFPR32_M2_MASK, PseudoVFWNMSAC_VFPR32_M2, 0x3, false }, // 1110
|
|
{ PseudoVFWNMSAC_VFPR32_M4_MASK, PseudoVFWNMSAC_VFPR32_M4, 0x3, false }, // 1111
|
|
{ PseudoVFWNMSAC_VFPR32_MF2_MASK, PseudoVFWNMSAC_VFPR32_MF2, 0x3, false }, // 1112
|
|
{ PseudoVFWNMSAC_VV_M1_MASK, PseudoVFWNMSAC_VV_M1, 0x3, false }, // 1113
|
|
{ PseudoVFWNMSAC_VV_M2_MASK, PseudoVFWNMSAC_VV_M2, 0x3, false }, // 1114
|
|
{ PseudoVFWNMSAC_VV_M4_MASK, PseudoVFWNMSAC_VV_M4, 0x3, false }, // 1115
|
|
{ PseudoVFWNMSAC_VV_MF2_MASK, PseudoVFWNMSAC_VV_MF2, 0x3, false }, // 1116
|
|
{ PseudoVFWNMSAC_VV_MF4_MASK, PseudoVFWNMSAC_VV_MF4, 0x3, false }, // 1117
|
|
{ PseudoVFWREDOSUM_VS_M1_E16_MASK, PseudoVFWREDOSUM_VS_M1_E16, 0x3, true }, // 1118
|
|
{ PseudoVFWREDOSUM_VS_M1_E32_MASK, PseudoVFWREDOSUM_VS_M1_E32, 0x3, true }, // 1119
|
|
{ PseudoVFWREDOSUM_VS_M2_E16_MASK, PseudoVFWREDOSUM_VS_M2_E16, 0x3, true }, // 1120
|
|
{ PseudoVFWREDOSUM_VS_M2_E32_MASK, PseudoVFWREDOSUM_VS_M2_E32, 0x3, true }, // 1121
|
|
{ PseudoVFWREDOSUM_VS_M4_E16_MASK, PseudoVFWREDOSUM_VS_M4_E16, 0x3, true }, // 1122
|
|
{ PseudoVFWREDOSUM_VS_M4_E32_MASK, PseudoVFWREDOSUM_VS_M4_E32, 0x3, true }, // 1123
|
|
{ PseudoVFWREDOSUM_VS_M8_E16_MASK, PseudoVFWREDOSUM_VS_M8_E16, 0x3, true }, // 1124
|
|
{ PseudoVFWREDOSUM_VS_M8_E32_MASK, PseudoVFWREDOSUM_VS_M8_E32, 0x3, true }, // 1125
|
|
{ PseudoVFWREDOSUM_VS_MF2_E16_MASK, PseudoVFWREDOSUM_VS_MF2_E16, 0x3, true }, // 1126
|
|
{ PseudoVFWREDOSUM_VS_MF2_E32_MASK, PseudoVFWREDOSUM_VS_MF2_E32, 0x3, true }, // 1127
|
|
{ PseudoVFWREDOSUM_VS_MF4_E16_MASK, PseudoVFWREDOSUM_VS_MF4_E16, 0x3, true }, // 1128
|
|
{ PseudoVFWREDUSUM_VS_M1_E16_MASK, PseudoVFWREDUSUM_VS_M1_E16, 0x3, true }, // 1129
|
|
{ PseudoVFWREDUSUM_VS_M1_E32_MASK, PseudoVFWREDUSUM_VS_M1_E32, 0x3, true }, // 1130
|
|
{ PseudoVFWREDUSUM_VS_M2_E16_MASK, PseudoVFWREDUSUM_VS_M2_E16, 0x3, true }, // 1131
|
|
{ PseudoVFWREDUSUM_VS_M2_E32_MASK, PseudoVFWREDUSUM_VS_M2_E32, 0x3, true }, // 1132
|
|
{ PseudoVFWREDUSUM_VS_M4_E16_MASK, PseudoVFWREDUSUM_VS_M4_E16, 0x3, true }, // 1133
|
|
{ PseudoVFWREDUSUM_VS_M4_E32_MASK, PseudoVFWREDUSUM_VS_M4_E32, 0x3, true }, // 1134
|
|
{ PseudoVFWREDUSUM_VS_M8_E16_MASK, PseudoVFWREDUSUM_VS_M8_E16, 0x3, true }, // 1135
|
|
{ PseudoVFWREDUSUM_VS_M8_E32_MASK, PseudoVFWREDUSUM_VS_M8_E32, 0x3, true }, // 1136
|
|
{ PseudoVFWREDUSUM_VS_MF2_E16_MASK, PseudoVFWREDUSUM_VS_MF2_E16, 0x3, true }, // 1137
|
|
{ PseudoVFWREDUSUM_VS_MF2_E32_MASK, PseudoVFWREDUSUM_VS_MF2_E32, 0x3, true }, // 1138
|
|
{ PseudoVFWREDUSUM_VS_MF4_E16_MASK, PseudoVFWREDUSUM_VS_MF4_E16, 0x3, true }, // 1139
|
|
{ PseudoVFWSUB_VFPR16_M1_MASK, PseudoVFWSUB_VFPR16_M1, 0x3, false }, // 1140
|
|
{ PseudoVFWSUB_VFPR16_M2_MASK, PseudoVFWSUB_VFPR16_M2, 0x3, false }, // 1141
|
|
{ PseudoVFWSUB_VFPR16_M4_MASK, PseudoVFWSUB_VFPR16_M4, 0x3, false }, // 1142
|
|
{ PseudoVFWSUB_VFPR16_MF2_MASK, PseudoVFWSUB_VFPR16_MF2, 0x3, false }, // 1143
|
|
{ PseudoVFWSUB_VFPR16_MF4_MASK, PseudoVFWSUB_VFPR16_MF4, 0x3, false }, // 1144
|
|
{ PseudoVFWSUB_VFPR32_M1_MASK, PseudoVFWSUB_VFPR32_M1, 0x3, false }, // 1145
|
|
{ PseudoVFWSUB_VFPR32_M2_MASK, PseudoVFWSUB_VFPR32_M2, 0x3, false }, // 1146
|
|
{ PseudoVFWSUB_VFPR32_M4_MASK, PseudoVFWSUB_VFPR32_M4, 0x3, false }, // 1147
|
|
{ PseudoVFWSUB_VFPR32_MF2_MASK, PseudoVFWSUB_VFPR32_MF2, 0x3, false }, // 1148
|
|
{ PseudoVFWSUB_VV_M1_MASK, PseudoVFWSUB_VV_M1, 0x3, false }, // 1149
|
|
{ PseudoVFWSUB_VV_M2_MASK, PseudoVFWSUB_VV_M2, 0x3, false }, // 1150
|
|
{ PseudoVFWSUB_VV_M4_MASK, PseudoVFWSUB_VV_M4, 0x3, false }, // 1151
|
|
{ PseudoVFWSUB_VV_MF2_MASK, PseudoVFWSUB_VV_MF2, 0x3, false }, // 1152
|
|
{ PseudoVFWSUB_VV_MF4_MASK, PseudoVFWSUB_VV_MF4, 0x3, false }, // 1153
|
|
{ PseudoVFWSUB_WFPR16_M1_MASK, PseudoVFWSUB_WFPR16_M1, 0x3, false }, // 1154
|
|
{ PseudoVFWSUB_WFPR16_M2_MASK, PseudoVFWSUB_WFPR16_M2, 0x3, false }, // 1155
|
|
{ PseudoVFWSUB_WFPR16_M4_MASK, PseudoVFWSUB_WFPR16_M4, 0x3, false }, // 1156
|
|
{ PseudoVFWSUB_WFPR16_MF2_MASK, PseudoVFWSUB_WFPR16_MF2, 0x3, false }, // 1157
|
|
{ PseudoVFWSUB_WFPR16_MF4_MASK, PseudoVFWSUB_WFPR16_MF4, 0x3, false }, // 1158
|
|
{ PseudoVFWSUB_WFPR32_M1_MASK, PseudoVFWSUB_WFPR32_M1, 0x3, false }, // 1159
|
|
{ PseudoVFWSUB_WFPR32_M2_MASK, PseudoVFWSUB_WFPR32_M2, 0x3, false }, // 1160
|
|
{ PseudoVFWSUB_WFPR32_M4_MASK, PseudoVFWSUB_WFPR32_M4, 0x3, false }, // 1161
|
|
{ PseudoVFWSUB_WFPR32_MF2_MASK, PseudoVFWSUB_WFPR32_MF2, 0x3, false }, // 1162
|
|
{ PseudoVFWSUB_WV_M1_MASK, PseudoVFWSUB_WV_M1, 0x3, false }, // 1163
|
|
{ PseudoVFWSUB_WV_M2_MASK, PseudoVFWSUB_WV_M2, 0x3, false }, // 1164
|
|
{ PseudoVFWSUB_WV_M4_MASK, PseudoVFWSUB_WV_M4, 0x3, false }, // 1165
|
|
{ PseudoVFWSUB_WV_MF2_MASK, PseudoVFWSUB_WV_MF2, 0x3, false }, // 1166
|
|
{ PseudoVFWSUB_WV_MF4_MASK, PseudoVFWSUB_WV_MF4, 0x3, false }, // 1167
|
|
{ PseudoVID_V_M1_MASK, PseudoVID_V_M1, 0x1, false }, // 1168
|
|
{ PseudoVID_V_M2_MASK, PseudoVID_V_M2, 0x1, false }, // 1169
|
|
{ PseudoVID_V_M4_MASK, PseudoVID_V_M4, 0x1, false }, // 1170
|
|
{ PseudoVID_V_M8_MASK, PseudoVID_V_M8, 0x1, false }, // 1171
|
|
{ PseudoVID_V_MF2_MASK, PseudoVID_V_MF2, 0x1, false }, // 1172
|
|
{ PseudoVID_V_MF4_MASK, PseudoVID_V_MF4, 0x1, false }, // 1173
|
|
{ PseudoVID_V_MF8_MASK, PseudoVID_V_MF8, 0x1, false }, // 1174
|
|
{ PseudoVIOTA_M_M1_MASK, PseudoVIOTA_M_M1, 0x2, true }, // 1175
|
|
{ PseudoVIOTA_M_M2_MASK, PseudoVIOTA_M_M2, 0x2, true }, // 1176
|
|
{ PseudoVIOTA_M_M4_MASK, PseudoVIOTA_M_M4, 0x2, true }, // 1177
|
|
{ PseudoVIOTA_M_M8_MASK, PseudoVIOTA_M_M8, 0x2, true }, // 1178
|
|
{ PseudoVIOTA_M_MF2_MASK, PseudoVIOTA_M_MF2, 0x2, true }, // 1179
|
|
{ PseudoVIOTA_M_MF4_MASK, PseudoVIOTA_M_MF4, 0x2, true }, // 1180
|
|
{ PseudoVIOTA_M_MF8_MASK, PseudoVIOTA_M_MF8, 0x2, true }, // 1181
|
|
{ PseudoVLE16FF_V_M1_MASK, PseudoVLE16FF_V_M1, 0x2, false }, // 1182
|
|
{ PseudoVLE16FF_V_M2_MASK, PseudoVLE16FF_V_M2, 0x2, false }, // 1183
|
|
{ PseudoVLE16FF_V_M4_MASK, PseudoVLE16FF_V_M4, 0x2, false }, // 1184
|
|
{ PseudoVLE16FF_V_M8_MASK, PseudoVLE16FF_V_M8, 0x2, false }, // 1185
|
|
{ PseudoVLE16FF_V_MF2_MASK, PseudoVLE16FF_V_MF2, 0x2, false }, // 1186
|
|
{ PseudoVLE16FF_V_MF4_MASK, PseudoVLE16FF_V_MF4, 0x2, false }, // 1187
|
|
{ PseudoVLE16_V_M1_MASK, PseudoVLE16_V_M1, 0x2, false }, // 1188
|
|
{ PseudoVLE16_V_M2_MASK, PseudoVLE16_V_M2, 0x2, false }, // 1189
|
|
{ PseudoVLE16_V_M4_MASK, PseudoVLE16_V_M4, 0x2, false }, // 1190
|
|
{ PseudoVLE16_V_M8_MASK, PseudoVLE16_V_M8, 0x2, false }, // 1191
|
|
{ PseudoVLE16_V_MF2_MASK, PseudoVLE16_V_MF2, 0x2, false }, // 1192
|
|
{ PseudoVLE16_V_MF4_MASK, PseudoVLE16_V_MF4, 0x2, false }, // 1193
|
|
{ PseudoVLE32FF_V_M1_MASK, PseudoVLE32FF_V_M1, 0x2, false }, // 1194
|
|
{ PseudoVLE32FF_V_M2_MASK, PseudoVLE32FF_V_M2, 0x2, false }, // 1195
|
|
{ PseudoVLE32FF_V_M4_MASK, PseudoVLE32FF_V_M4, 0x2, false }, // 1196
|
|
{ PseudoVLE32FF_V_M8_MASK, PseudoVLE32FF_V_M8, 0x2, false }, // 1197
|
|
{ PseudoVLE32FF_V_MF2_MASK, PseudoVLE32FF_V_MF2, 0x2, false }, // 1198
|
|
{ PseudoVLE32_V_M1_MASK, PseudoVLE32_V_M1, 0x2, false }, // 1199
|
|
{ PseudoVLE32_V_M2_MASK, PseudoVLE32_V_M2, 0x2, false }, // 1200
|
|
{ PseudoVLE32_V_M4_MASK, PseudoVLE32_V_M4, 0x2, false }, // 1201
|
|
{ PseudoVLE32_V_M8_MASK, PseudoVLE32_V_M8, 0x2, false }, // 1202
|
|
{ PseudoVLE32_V_MF2_MASK, PseudoVLE32_V_MF2, 0x2, false }, // 1203
|
|
{ PseudoVLE64FF_V_M1_MASK, PseudoVLE64FF_V_M1, 0x2, false }, // 1204
|
|
{ PseudoVLE64FF_V_M2_MASK, PseudoVLE64FF_V_M2, 0x2, false }, // 1205
|
|
{ PseudoVLE64FF_V_M4_MASK, PseudoVLE64FF_V_M4, 0x2, false }, // 1206
|
|
{ PseudoVLE64FF_V_M8_MASK, PseudoVLE64FF_V_M8, 0x2, false }, // 1207
|
|
{ PseudoVLE64_V_M1_MASK, PseudoVLE64_V_M1, 0x2, false }, // 1208
|
|
{ PseudoVLE64_V_M2_MASK, PseudoVLE64_V_M2, 0x2, false }, // 1209
|
|
{ PseudoVLE64_V_M4_MASK, PseudoVLE64_V_M4, 0x2, false }, // 1210
|
|
{ PseudoVLE64_V_M8_MASK, PseudoVLE64_V_M8, 0x2, false }, // 1211
|
|
{ PseudoVLE8FF_V_M1_MASK, PseudoVLE8FF_V_M1, 0x2, false }, // 1212
|
|
{ PseudoVLE8FF_V_M2_MASK, PseudoVLE8FF_V_M2, 0x2, false }, // 1213
|
|
{ PseudoVLE8FF_V_M4_MASK, PseudoVLE8FF_V_M4, 0x2, false }, // 1214
|
|
{ PseudoVLE8FF_V_M8_MASK, PseudoVLE8FF_V_M8, 0x2, false }, // 1215
|
|
{ PseudoVLE8FF_V_MF2_MASK, PseudoVLE8FF_V_MF2, 0x2, false }, // 1216
|
|
{ PseudoVLE8FF_V_MF4_MASK, PseudoVLE8FF_V_MF4, 0x2, false }, // 1217
|
|
{ PseudoVLE8FF_V_MF8_MASK, PseudoVLE8FF_V_MF8, 0x2, false }, // 1218
|
|
{ PseudoVLE8_V_M1_MASK, PseudoVLE8_V_M1, 0x2, false }, // 1219
|
|
{ PseudoVLE8_V_M2_MASK, PseudoVLE8_V_M2, 0x2, false }, // 1220
|
|
{ PseudoVLE8_V_M4_MASK, PseudoVLE8_V_M4, 0x2, false }, // 1221
|
|
{ PseudoVLE8_V_M8_MASK, PseudoVLE8_V_M8, 0x2, false }, // 1222
|
|
{ PseudoVLE8_V_MF2_MASK, PseudoVLE8_V_MF2, 0x2, false }, // 1223
|
|
{ PseudoVLE8_V_MF4_MASK, PseudoVLE8_V_MF4, 0x2, false }, // 1224
|
|
{ PseudoVLE8_V_MF8_MASK, PseudoVLE8_V_MF8, 0x2, false }, // 1225
|
|
{ PseudoVLOXEI16_V_M1_M1_MASK, PseudoVLOXEI16_V_M1_M1, 0x3, false }, // 1226
|
|
{ PseudoVLOXEI16_V_M1_M2_MASK, PseudoVLOXEI16_V_M1_M2, 0x3, false }, // 1227
|
|
{ PseudoVLOXEI16_V_M1_M4_MASK, PseudoVLOXEI16_V_M1_M4, 0x3, false }, // 1228
|
|
{ PseudoVLOXEI16_V_M1_MF2_MASK, PseudoVLOXEI16_V_M1_MF2, 0x3, false }, // 1229
|
|
{ PseudoVLOXEI16_V_M2_M1_MASK, PseudoVLOXEI16_V_M2_M1, 0x3, false }, // 1230
|
|
{ PseudoVLOXEI16_V_M2_M2_MASK, PseudoVLOXEI16_V_M2_M2, 0x3, false }, // 1231
|
|
{ PseudoVLOXEI16_V_M2_M4_MASK, PseudoVLOXEI16_V_M2_M4, 0x3, false }, // 1232
|
|
{ PseudoVLOXEI16_V_M2_M8_MASK, PseudoVLOXEI16_V_M2_M8, 0x3, false }, // 1233
|
|
{ PseudoVLOXEI16_V_M4_M2_MASK, PseudoVLOXEI16_V_M4_M2, 0x3, false }, // 1234
|
|
{ PseudoVLOXEI16_V_M4_M4_MASK, PseudoVLOXEI16_V_M4_M4, 0x3, false }, // 1235
|
|
{ PseudoVLOXEI16_V_M4_M8_MASK, PseudoVLOXEI16_V_M4_M8, 0x3, false }, // 1236
|
|
{ PseudoVLOXEI16_V_M8_M4_MASK, PseudoVLOXEI16_V_M8_M4, 0x3, false }, // 1237
|
|
{ PseudoVLOXEI16_V_M8_M8_MASK, PseudoVLOXEI16_V_M8_M8, 0x3, false }, // 1238
|
|
{ PseudoVLOXEI16_V_MF2_M1_MASK, PseudoVLOXEI16_V_MF2_M1, 0x3, false }, // 1239
|
|
{ PseudoVLOXEI16_V_MF2_M2_MASK, PseudoVLOXEI16_V_MF2_M2, 0x3, false }, // 1240
|
|
{ PseudoVLOXEI16_V_MF2_MF2_MASK, PseudoVLOXEI16_V_MF2_MF2, 0x3, false }, // 1241
|
|
{ PseudoVLOXEI16_V_MF2_MF4_MASK, PseudoVLOXEI16_V_MF2_MF4, 0x3, false }, // 1242
|
|
{ PseudoVLOXEI16_V_MF4_M1_MASK, PseudoVLOXEI16_V_MF4_M1, 0x3, false }, // 1243
|
|
{ PseudoVLOXEI16_V_MF4_MF2_MASK, PseudoVLOXEI16_V_MF4_MF2, 0x3, false }, // 1244
|
|
{ PseudoVLOXEI16_V_MF4_MF4_MASK, PseudoVLOXEI16_V_MF4_MF4, 0x3, false }, // 1245
|
|
{ PseudoVLOXEI16_V_MF4_MF8_MASK, PseudoVLOXEI16_V_MF4_MF8, 0x3, false }, // 1246
|
|
{ PseudoVLOXEI32_V_M1_M1_MASK, PseudoVLOXEI32_V_M1_M1, 0x3, false }, // 1247
|
|
{ PseudoVLOXEI32_V_M1_M2_MASK, PseudoVLOXEI32_V_M1_M2, 0x3, false }, // 1248
|
|
{ PseudoVLOXEI32_V_M1_MF2_MASK, PseudoVLOXEI32_V_M1_MF2, 0x3, false }, // 1249
|
|
{ PseudoVLOXEI32_V_M1_MF4_MASK, PseudoVLOXEI32_V_M1_MF4, 0x3, false }, // 1250
|
|
{ PseudoVLOXEI32_V_M2_M1_MASK, PseudoVLOXEI32_V_M2_M1, 0x3, false }, // 1251
|
|
{ PseudoVLOXEI32_V_M2_M2_MASK, PseudoVLOXEI32_V_M2_M2, 0x3, false }, // 1252
|
|
{ PseudoVLOXEI32_V_M2_M4_MASK, PseudoVLOXEI32_V_M2_M4, 0x3, false }, // 1253
|
|
{ PseudoVLOXEI32_V_M2_MF2_MASK, PseudoVLOXEI32_V_M2_MF2, 0x3, false }, // 1254
|
|
{ PseudoVLOXEI32_V_M4_M1_MASK, PseudoVLOXEI32_V_M4_M1, 0x3, false }, // 1255
|
|
{ PseudoVLOXEI32_V_M4_M2_MASK, PseudoVLOXEI32_V_M4_M2, 0x3, false }, // 1256
|
|
{ PseudoVLOXEI32_V_M4_M4_MASK, PseudoVLOXEI32_V_M4_M4, 0x3, false }, // 1257
|
|
{ PseudoVLOXEI32_V_M4_M8_MASK, PseudoVLOXEI32_V_M4_M8, 0x3, false }, // 1258
|
|
{ PseudoVLOXEI32_V_M8_M2_MASK, PseudoVLOXEI32_V_M8_M2, 0x3, false }, // 1259
|
|
{ PseudoVLOXEI32_V_M8_M4_MASK, PseudoVLOXEI32_V_M8_M4, 0x3, false }, // 1260
|
|
{ PseudoVLOXEI32_V_M8_M8_MASK, PseudoVLOXEI32_V_M8_M8, 0x3, false }, // 1261
|
|
{ PseudoVLOXEI32_V_MF2_M1_MASK, PseudoVLOXEI32_V_MF2_M1, 0x3, false }, // 1262
|
|
{ PseudoVLOXEI32_V_MF2_MF2_MASK, PseudoVLOXEI32_V_MF2_MF2, 0x3, false }, // 1263
|
|
{ PseudoVLOXEI32_V_MF2_MF4_MASK, PseudoVLOXEI32_V_MF2_MF4, 0x3, false }, // 1264
|
|
{ PseudoVLOXEI32_V_MF2_MF8_MASK, PseudoVLOXEI32_V_MF2_MF8, 0x3, false }, // 1265
|
|
{ PseudoVLOXEI64_V_M1_M1_MASK, PseudoVLOXEI64_V_M1_M1, 0x3, false }, // 1266
|
|
{ PseudoVLOXEI64_V_M1_MF2_MASK, PseudoVLOXEI64_V_M1_MF2, 0x3, false }, // 1267
|
|
{ PseudoVLOXEI64_V_M1_MF4_MASK, PseudoVLOXEI64_V_M1_MF4, 0x3, false }, // 1268
|
|
{ PseudoVLOXEI64_V_M1_MF8_MASK, PseudoVLOXEI64_V_M1_MF8, 0x3, false }, // 1269
|
|
{ PseudoVLOXEI64_V_M2_M1_MASK, PseudoVLOXEI64_V_M2_M1, 0x3, false }, // 1270
|
|
{ PseudoVLOXEI64_V_M2_M2_MASK, PseudoVLOXEI64_V_M2_M2, 0x3, false }, // 1271
|
|
{ PseudoVLOXEI64_V_M2_MF2_MASK, PseudoVLOXEI64_V_M2_MF2, 0x3, false }, // 1272
|
|
{ PseudoVLOXEI64_V_M2_MF4_MASK, PseudoVLOXEI64_V_M2_MF4, 0x3, false }, // 1273
|
|
{ PseudoVLOXEI64_V_M4_M1_MASK, PseudoVLOXEI64_V_M4_M1, 0x3, false }, // 1274
|
|
{ PseudoVLOXEI64_V_M4_M2_MASK, PseudoVLOXEI64_V_M4_M2, 0x3, false }, // 1275
|
|
{ PseudoVLOXEI64_V_M4_M4_MASK, PseudoVLOXEI64_V_M4_M4, 0x3, false }, // 1276
|
|
{ PseudoVLOXEI64_V_M4_MF2_MASK, PseudoVLOXEI64_V_M4_MF2, 0x3, false }, // 1277
|
|
{ PseudoVLOXEI64_V_M8_M1_MASK, PseudoVLOXEI64_V_M8_M1, 0x3, false }, // 1278
|
|
{ PseudoVLOXEI64_V_M8_M2_MASK, PseudoVLOXEI64_V_M8_M2, 0x3, false }, // 1279
|
|
{ PseudoVLOXEI64_V_M8_M4_MASK, PseudoVLOXEI64_V_M8_M4, 0x3, false }, // 1280
|
|
{ PseudoVLOXEI64_V_M8_M8_MASK, PseudoVLOXEI64_V_M8_M8, 0x3, false }, // 1281
|
|
{ PseudoVLOXEI8_V_M1_M1_MASK, PseudoVLOXEI8_V_M1_M1, 0x3, false }, // 1282
|
|
{ PseudoVLOXEI8_V_M1_M2_MASK, PseudoVLOXEI8_V_M1_M2, 0x3, false }, // 1283
|
|
{ PseudoVLOXEI8_V_M1_M4_MASK, PseudoVLOXEI8_V_M1_M4, 0x3, false }, // 1284
|
|
{ PseudoVLOXEI8_V_M1_M8_MASK, PseudoVLOXEI8_V_M1_M8, 0x3, false }, // 1285
|
|
{ PseudoVLOXEI8_V_M2_M2_MASK, PseudoVLOXEI8_V_M2_M2, 0x3, false }, // 1286
|
|
{ PseudoVLOXEI8_V_M2_M4_MASK, PseudoVLOXEI8_V_M2_M4, 0x3, false }, // 1287
|
|
{ PseudoVLOXEI8_V_M2_M8_MASK, PseudoVLOXEI8_V_M2_M8, 0x3, false }, // 1288
|
|
{ PseudoVLOXEI8_V_M4_M4_MASK, PseudoVLOXEI8_V_M4_M4, 0x3, false }, // 1289
|
|
{ PseudoVLOXEI8_V_M4_M8_MASK, PseudoVLOXEI8_V_M4_M8, 0x3, false }, // 1290
|
|
{ PseudoVLOXEI8_V_M8_M8_MASK, PseudoVLOXEI8_V_M8_M8, 0x3, false }, // 1291
|
|
{ PseudoVLOXEI8_V_MF2_M1_MASK, PseudoVLOXEI8_V_MF2_M1, 0x3, false }, // 1292
|
|
{ PseudoVLOXEI8_V_MF2_M2_MASK, PseudoVLOXEI8_V_MF2_M2, 0x3, false }, // 1293
|
|
{ PseudoVLOXEI8_V_MF2_M4_MASK, PseudoVLOXEI8_V_MF2_M4, 0x3, false }, // 1294
|
|
{ PseudoVLOXEI8_V_MF2_MF2_MASK, PseudoVLOXEI8_V_MF2_MF2, 0x3, false }, // 1295
|
|
{ PseudoVLOXEI8_V_MF4_M1_MASK, PseudoVLOXEI8_V_MF4_M1, 0x3, false }, // 1296
|
|
{ PseudoVLOXEI8_V_MF4_M2_MASK, PseudoVLOXEI8_V_MF4_M2, 0x3, false }, // 1297
|
|
{ PseudoVLOXEI8_V_MF4_MF2_MASK, PseudoVLOXEI8_V_MF4_MF2, 0x3, false }, // 1298
|
|
{ PseudoVLOXEI8_V_MF4_MF4_MASK, PseudoVLOXEI8_V_MF4_MF4, 0x3, false }, // 1299
|
|
{ PseudoVLOXEI8_V_MF8_M1_MASK, PseudoVLOXEI8_V_MF8_M1, 0x3, false }, // 1300
|
|
{ PseudoVLOXEI8_V_MF8_MF2_MASK, PseudoVLOXEI8_V_MF8_MF2, 0x3, false }, // 1301
|
|
{ PseudoVLOXEI8_V_MF8_MF4_MASK, PseudoVLOXEI8_V_MF8_MF4, 0x3, false }, // 1302
|
|
{ PseudoVLOXEI8_V_MF8_MF8_MASK, PseudoVLOXEI8_V_MF8_MF8, 0x3, false }, // 1303
|
|
{ PseudoVLSE16_V_M1_MASK, PseudoVLSE16_V_M1, 0x3, false }, // 1304
|
|
{ PseudoVLSE16_V_M2_MASK, PseudoVLSE16_V_M2, 0x3, false }, // 1305
|
|
{ PseudoVLSE16_V_M4_MASK, PseudoVLSE16_V_M4, 0x3, false }, // 1306
|
|
{ PseudoVLSE16_V_M8_MASK, PseudoVLSE16_V_M8, 0x3, false }, // 1307
|
|
{ PseudoVLSE16_V_MF2_MASK, PseudoVLSE16_V_MF2, 0x3, false }, // 1308
|
|
{ PseudoVLSE16_V_MF4_MASK, PseudoVLSE16_V_MF4, 0x3, false }, // 1309
|
|
{ PseudoVLSE32_V_M1_MASK, PseudoVLSE32_V_M1, 0x3, false }, // 1310
|
|
{ PseudoVLSE32_V_M2_MASK, PseudoVLSE32_V_M2, 0x3, false }, // 1311
|
|
{ PseudoVLSE32_V_M4_MASK, PseudoVLSE32_V_M4, 0x3, false }, // 1312
|
|
{ PseudoVLSE32_V_M8_MASK, PseudoVLSE32_V_M8, 0x3, false }, // 1313
|
|
{ PseudoVLSE32_V_MF2_MASK, PseudoVLSE32_V_MF2, 0x3, false }, // 1314
|
|
{ PseudoVLSE64_V_M1_MASK, PseudoVLSE64_V_M1, 0x3, false }, // 1315
|
|
{ PseudoVLSE64_V_M2_MASK, PseudoVLSE64_V_M2, 0x3, false }, // 1316
|
|
{ PseudoVLSE64_V_M4_MASK, PseudoVLSE64_V_M4, 0x3, false }, // 1317
|
|
{ PseudoVLSE64_V_M8_MASK, PseudoVLSE64_V_M8, 0x3, false }, // 1318
|
|
{ PseudoVLSE8_V_M1_MASK, PseudoVLSE8_V_M1, 0x3, false }, // 1319
|
|
{ PseudoVLSE8_V_M2_MASK, PseudoVLSE8_V_M2, 0x3, false }, // 1320
|
|
{ PseudoVLSE8_V_M4_MASK, PseudoVLSE8_V_M4, 0x3, false }, // 1321
|
|
{ PseudoVLSE8_V_M8_MASK, PseudoVLSE8_V_M8, 0x3, false }, // 1322
|
|
{ PseudoVLSE8_V_MF2_MASK, PseudoVLSE8_V_MF2, 0x3, false }, // 1323
|
|
{ PseudoVLSE8_V_MF4_MASK, PseudoVLSE8_V_MF4, 0x3, false }, // 1324
|
|
{ PseudoVLSE8_V_MF8_MASK, PseudoVLSE8_V_MF8, 0x3, false }, // 1325
|
|
{ PseudoVLUXEI16_V_M1_M1_MASK, PseudoVLUXEI16_V_M1_M1, 0x3, false }, // 1326
|
|
{ PseudoVLUXEI16_V_M1_M2_MASK, PseudoVLUXEI16_V_M1_M2, 0x3, false }, // 1327
|
|
{ PseudoVLUXEI16_V_M1_M4_MASK, PseudoVLUXEI16_V_M1_M4, 0x3, false }, // 1328
|
|
{ PseudoVLUXEI16_V_M1_MF2_MASK, PseudoVLUXEI16_V_M1_MF2, 0x3, false }, // 1329
|
|
{ PseudoVLUXEI16_V_M2_M1_MASK, PseudoVLUXEI16_V_M2_M1, 0x3, false }, // 1330
|
|
{ PseudoVLUXEI16_V_M2_M2_MASK, PseudoVLUXEI16_V_M2_M2, 0x3, false }, // 1331
|
|
{ PseudoVLUXEI16_V_M2_M4_MASK, PseudoVLUXEI16_V_M2_M4, 0x3, false }, // 1332
|
|
{ PseudoVLUXEI16_V_M2_M8_MASK, PseudoVLUXEI16_V_M2_M8, 0x3, false }, // 1333
|
|
{ PseudoVLUXEI16_V_M4_M2_MASK, PseudoVLUXEI16_V_M4_M2, 0x3, false }, // 1334
|
|
{ PseudoVLUXEI16_V_M4_M4_MASK, PseudoVLUXEI16_V_M4_M4, 0x3, false }, // 1335
|
|
{ PseudoVLUXEI16_V_M4_M8_MASK, PseudoVLUXEI16_V_M4_M8, 0x3, false }, // 1336
|
|
{ PseudoVLUXEI16_V_M8_M4_MASK, PseudoVLUXEI16_V_M8_M4, 0x3, false }, // 1337
|
|
{ PseudoVLUXEI16_V_M8_M8_MASK, PseudoVLUXEI16_V_M8_M8, 0x3, false }, // 1338
|
|
{ PseudoVLUXEI16_V_MF2_M1_MASK, PseudoVLUXEI16_V_MF2_M1, 0x3, false }, // 1339
|
|
{ PseudoVLUXEI16_V_MF2_M2_MASK, PseudoVLUXEI16_V_MF2_M2, 0x3, false }, // 1340
|
|
{ PseudoVLUXEI16_V_MF2_MF2_MASK, PseudoVLUXEI16_V_MF2_MF2, 0x3, false }, // 1341
|
|
{ PseudoVLUXEI16_V_MF2_MF4_MASK, PseudoVLUXEI16_V_MF2_MF4, 0x3, false }, // 1342
|
|
{ PseudoVLUXEI16_V_MF4_M1_MASK, PseudoVLUXEI16_V_MF4_M1, 0x3, false }, // 1343
|
|
{ PseudoVLUXEI16_V_MF4_MF2_MASK, PseudoVLUXEI16_V_MF4_MF2, 0x3, false }, // 1344
|
|
{ PseudoVLUXEI16_V_MF4_MF4_MASK, PseudoVLUXEI16_V_MF4_MF4, 0x3, false }, // 1345
|
|
{ PseudoVLUXEI16_V_MF4_MF8_MASK, PseudoVLUXEI16_V_MF4_MF8, 0x3, false }, // 1346
|
|
{ PseudoVLUXEI32_V_M1_M1_MASK, PseudoVLUXEI32_V_M1_M1, 0x3, false }, // 1347
|
|
{ PseudoVLUXEI32_V_M1_M2_MASK, PseudoVLUXEI32_V_M1_M2, 0x3, false }, // 1348
|
|
{ PseudoVLUXEI32_V_M1_MF2_MASK, PseudoVLUXEI32_V_M1_MF2, 0x3, false }, // 1349
|
|
{ PseudoVLUXEI32_V_M1_MF4_MASK, PseudoVLUXEI32_V_M1_MF4, 0x3, false }, // 1350
|
|
{ PseudoVLUXEI32_V_M2_M1_MASK, PseudoVLUXEI32_V_M2_M1, 0x3, false }, // 1351
|
|
{ PseudoVLUXEI32_V_M2_M2_MASK, PseudoVLUXEI32_V_M2_M2, 0x3, false }, // 1352
|
|
{ PseudoVLUXEI32_V_M2_M4_MASK, PseudoVLUXEI32_V_M2_M4, 0x3, false }, // 1353
|
|
{ PseudoVLUXEI32_V_M2_MF2_MASK, PseudoVLUXEI32_V_M2_MF2, 0x3, false }, // 1354
|
|
{ PseudoVLUXEI32_V_M4_M1_MASK, PseudoVLUXEI32_V_M4_M1, 0x3, false }, // 1355
|
|
{ PseudoVLUXEI32_V_M4_M2_MASK, PseudoVLUXEI32_V_M4_M2, 0x3, false }, // 1356
|
|
{ PseudoVLUXEI32_V_M4_M4_MASK, PseudoVLUXEI32_V_M4_M4, 0x3, false }, // 1357
|
|
{ PseudoVLUXEI32_V_M4_M8_MASK, PseudoVLUXEI32_V_M4_M8, 0x3, false }, // 1358
|
|
{ PseudoVLUXEI32_V_M8_M2_MASK, PseudoVLUXEI32_V_M8_M2, 0x3, false }, // 1359
|
|
{ PseudoVLUXEI32_V_M8_M4_MASK, PseudoVLUXEI32_V_M8_M4, 0x3, false }, // 1360
|
|
{ PseudoVLUXEI32_V_M8_M8_MASK, PseudoVLUXEI32_V_M8_M8, 0x3, false }, // 1361
|
|
{ PseudoVLUXEI32_V_MF2_M1_MASK, PseudoVLUXEI32_V_MF2_M1, 0x3, false }, // 1362
|
|
{ PseudoVLUXEI32_V_MF2_MF2_MASK, PseudoVLUXEI32_V_MF2_MF2, 0x3, false }, // 1363
|
|
{ PseudoVLUXEI32_V_MF2_MF4_MASK, PseudoVLUXEI32_V_MF2_MF4, 0x3, false }, // 1364
|
|
{ PseudoVLUXEI32_V_MF2_MF8_MASK, PseudoVLUXEI32_V_MF2_MF8, 0x3, false }, // 1365
|
|
{ PseudoVLUXEI64_V_M1_M1_MASK, PseudoVLUXEI64_V_M1_M1, 0x3, false }, // 1366
|
|
{ PseudoVLUXEI64_V_M1_MF2_MASK, PseudoVLUXEI64_V_M1_MF2, 0x3, false }, // 1367
|
|
{ PseudoVLUXEI64_V_M1_MF4_MASK, PseudoVLUXEI64_V_M1_MF4, 0x3, false }, // 1368
|
|
{ PseudoVLUXEI64_V_M1_MF8_MASK, PseudoVLUXEI64_V_M1_MF8, 0x3, false }, // 1369
|
|
{ PseudoVLUXEI64_V_M2_M1_MASK, PseudoVLUXEI64_V_M2_M1, 0x3, false }, // 1370
|
|
{ PseudoVLUXEI64_V_M2_M2_MASK, PseudoVLUXEI64_V_M2_M2, 0x3, false }, // 1371
|
|
{ PseudoVLUXEI64_V_M2_MF2_MASK, PseudoVLUXEI64_V_M2_MF2, 0x3, false }, // 1372
|
|
{ PseudoVLUXEI64_V_M2_MF4_MASK, PseudoVLUXEI64_V_M2_MF4, 0x3, false }, // 1373
|
|
{ PseudoVLUXEI64_V_M4_M1_MASK, PseudoVLUXEI64_V_M4_M1, 0x3, false }, // 1374
|
|
{ PseudoVLUXEI64_V_M4_M2_MASK, PseudoVLUXEI64_V_M4_M2, 0x3, false }, // 1375
|
|
{ PseudoVLUXEI64_V_M4_M4_MASK, PseudoVLUXEI64_V_M4_M4, 0x3, false }, // 1376
|
|
{ PseudoVLUXEI64_V_M4_MF2_MASK, PseudoVLUXEI64_V_M4_MF2, 0x3, false }, // 1377
|
|
{ PseudoVLUXEI64_V_M8_M1_MASK, PseudoVLUXEI64_V_M8_M1, 0x3, false }, // 1378
|
|
{ PseudoVLUXEI64_V_M8_M2_MASK, PseudoVLUXEI64_V_M8_M2, 0x3, false }, // 1379
|
|
{ PseudoVLUXEI64_V_M8_M4_MASK, PseudoVLUXEI64_V_M8_M4, 0x3, false }, // 1380
|
|
{ PseudoVLUXEI64_V_M8_M8_MASK, PseudoVLUXEI64_V_M8_M8, 0x3, false }, // 1381
|
|
{ PseudoVLUXEI8_V_M1_M1_MASK, PseudoVLUXEI8_V_M1_M1, 0x3, false }, // 1382
|
|
{ PseudoVLUXEI8_V_M1_M2_MASK, PseudoVLUXEI8_V_M1_M2, 0x3, false }, // 1383
|
|
{ PseudoVLUXEI8_V_M1_M4_MASK, PseudoVLUXEI8_V_M1_M4, 0x3, false }, // 1384
|
|
{ PseudoVLUXEI8_V_M1_M8_MASK, PseudoVLUXEI8_V_M1_M8, 0x3, false }, // 1385
|
|
{ PseudoVLUXEI8_V_M2_M2_MASK, PseudoVLUXEI8_V_M2_M2, 0x3, false }, // 1386
|
|
{ PseudoVLUXEI8_V_M2_M4_MASK, PseudoVLUXEI8_V_M2_M4, 0x3, false }, // 1387
|
|
{ PseudoVLUXEI8_V_M2_M8_MASK, PseudoVLUXEI8_V_M2_M8, 0x3, false }, // 1388
|
|
{ PseudoVLUXEI8_V_M4_M4_MASK, PseudoVLUXEI8_V_M4_M4, 0x3, false }, // 1389
|
|
{ PseudoVLUXEI8_V_M4_M8_MASK, PseudoVLUXEI8_V_M4_M8, 0x3, false }, // 1390
|
|
{ PseudoVLUXEI8_V_M8_M8_MASK, PseudoVLUXEI8_V_M8_M8, 0x3, false }, // 1391
|
|
{ PseudoVLUXEI8_V_MF2_M1_MASK, PseudoVLUXEI8_V_MF2_M1, 0x3, false }, // 1392
|
|
{ PseudoVLUXEI8_V_MF2_M2_MASK, PseudoVLUXEI8_V_MF2_M2, 0x3, false }, // 1393
|
|
{ PseudoVLUXEI8_V_MF2_M4_MASK, PseudoVLUXEI8_V_MF2_M4, 0x3, false }, // 1394
|
|
{ PseudoVLUXEI8_V_MF2_MF2_MASK, PseudoVLUXEI8_V_MF2_MF2, 0x3, false }, // 1395
|
|
{ PseudoVLUXEI8_V_MF4_M1_MASK, PseudoVLUXEI8_V_MF4_M1, 0x3, false }, // 1396
|
|
{ PseudoVLUXEI8_V_MF4_M2_MASK, PseudoVLUXEI8_V_MF4_M2, 0x3, false }, // 1397
|
|
{ PseudoVLUXEI8_V_MF4_MF2_MASK, PseudoVLUXEI8_V_MF4_MF2, 0x3, false }, // 1398
|
|
{ PseudoVLUXEI8_V_MF4_MF4_MASK, PseudoVLUXEI8_V_MF4_MF4, 0x3, false }, // 1399
|
|
{ PseudoVLUXEI8_V_MF8_M1_MASK, PseudoVLUXEI8_V_MF8_M1, 0x3, false }, // 1400
|
|
{ PseudoVLUXEI8_V_MF8_MF2_MASK, PseudoVLUXEI8_V_MF8_MF2, 0x3, false }, // 1401
|
|
{ PseudoVLUXEI8_V_MF8_MF4_MASK, PseudoVLUXEI8_V_MF8_MF4, 0x3, false }, // 1402
|
|
{ PseudoVLUXEI8_V_MF8_MF8_MASK, PseudoVLUXEI8_V_MF8_MF8, 0x3, false }, // 1403
|
|
{ PseudoVMACC_VV_M1_MASK, PseudoVMACC_VV_M1, 0x3, false }, // 1404
|
|
{ PseudoVMACC_VV_M2_MASK, PseudoVMACC_VV_M2, 0x3, false }, // 1405
|
|
{ PseudoVMACC_VV_M4_MASK, PseudoVMACC_VV_M4, 0x3, false }, // 1406
|
|
{ PseudoVMACC_VV_M8_MASK, PseudoVMACC_VV_M8, 0x3, false }, // 1407
|
|
{ PseudoVMACC_VV_MF2_MASK, PseudoVMACC_VV_MF2, 0x3, false }, // 1408
|
|
{ PseudoVMACC_VV_MF4_MASK, PseudoVMACC_VV_MF4, 0x3, false }, // 1409
|
|
{ PseudoVMACC_VV_MF8_MASK, PseudoVMACC_VV_MF8, 0x3, false }, // 1410
|
|
{ PseudoVMACC_VX_M1_MASK, PseudoVMACC_VX_M1, 0x3, false }, // 1411
|
|
{ PseudoVMACC_VX_M2_MASK, PseudoVMACC_VX_M2, 0x3, false }, // 1412
|
|
{ PseudoVMACC_VX_M4_MASK, PseudoVMACC_VX_M4, 0x3, false }, // 1413
|
|
{ PseudoVMACC_VX_M8_MASK, PseudoVMACC_VX_M8, 0x3, false }, // 1414
|
|
{ PseudoVMACC_VX_MF2_MASK, PseudoVMACC_VX_MF2, 0x3, false }, // 1415
|
|
{ PseudoVMACC_VX_MF4_MASK, PseudoVMACC_VX_MF4, 0x3, false }, // 1416
|
|
{ PseudoVMACC_VX_MF8_MASK, PseudoVMACC_VX_MF8, 0x3, false }, // 1417
|
|
{ PseudoVMADD_VV_M1_MASK, PseudoVMADD_VV_M1, 0x3, false }, // 1418
|
|
{ PseudoVMADD_VV_M2_MASK, PseudoVMADD_VV_M2, 0x3, false }, // 1419
|
|
{ PseudoVMADD_VV_M4_MASK, PseudoVMADD_VV_M4, 0x3, false }, // 1420
|
|
{ PseudoVMADD_VV_M8_MASK, PseudoVMADD_VV_M8, 0x3, false }, // 1421
|
|
{ PseudoVMADD_VV_MF2_MASK, PseudoVMADD_VV_MF2, 0x3, false }, // 1422
|
|
{ PseudoVMADD_VV_MF4_MASK, PseudoVMADD_VV_MF4, 0x3, false }, // 1423
|
|
{ PseudoVMADD_VV_MF8_MASK, PseudoVMADD_VV_MF8, 0x3, false }, // 1424
|
|
{ PseudoVMADD_VX_M1_MASK, PseudoVMADD_VX_M1, 0x3, false }, // 1425
|
|
{ PseudoVMADD_VX_M2_MASK, PseudoVMADD_VX_M2, 0x3, false }, // 1426
|
|
{ PseudoVMADD_VX_M4_MASK, PseudoVMADD_VX_M4, 0x3, false }, // 1427
|
|
{ PseudoVMADD_VX_M8_MASK, PseudoVMADD_VX_M8, 0x3, false }, // 1428
|
|
{ PseudoVMADD_VX_MF2_MASK, PseudoVMADD_VX_MF2, 0x3, false }, // 1429
|
|
{ PseudoVMADD_VX_MF4_MASK, PseudoVMADD_VX_MF4, 0x3, false }, // 1430
|
|
{ PseudoVMADD_VX_MF8_MASK, PseudoVMADD_VX_MF8, 0x3, false }, // 1431
|
|
{ PseudoVMAXU_VV_M1_MASK, PseudoVMAXU_VV_M1, 0x3, false }, // 1432
|
|
{ PseudoVMAXU_VV_M2_MASK, PseudoVMAXU_VV_M2, 0x3, false }, // 1433
|
|
{ PseudoVMAXU_VV_M4_MASK, PseudoVMAXU_VV_M4, 0x3, false }, // 1434
|
|
{ PseudoVMAXU_VV_M8_MASK, PseudoVMAXU_VV_M8, 0x3, false }, // 1435
|
|
{ PseudoVMAXU_VV_MF2_MASK, PseudoVMAXU_VV_MF2, 0x3, false }, // 1436
|
|
{ PseudoVMAXU_VV_MF4_MASK, PseudoVMAXU_VV_MF4, 0x3, false }, // 1437
|
|
{ PseudoVMAXU_VV_MF8_MASK, PseudoVMAXU_VV_MF8, 0x3, false }, // 1438
|
|
{ PseudoVMAXU_VX_M1_MASK, PseudoVMAXU_VX_M1, 0x3, false }, // 1439
|
|
{ PseudoVMAXU_VX_M2_MASK, PseudoVMAXU_VX_M2, 0x3, false }, // 1440
|
|
{ PseudoVMAXU_VX_M4_MASK, PseudoVMAXU_VX_M4, 0x3, false }, // 1441
|
|
{ PseudoVMAXU_VX_M8_MASK, PseudoVMAXU_VX_M8, 0x3, false }, // 1442
|
|
{ PseudoVMAXU_VX_MF2_MASK, PseudoVMAXU_VX_MF2, 0x3, false }, // 1443
|
|
{ PseudoVMAXU_VX_MF4_MASK, PseudoVMAXU_VX_MF4, 0x3, false }, // 1444
|
|
{ PseudoVMAXU_VX_MF8_MASK, PseudoVMAXU_VX_MF8, 0x3, false }, // 1445
|
|
{ PseudoVMAX_VV_M1_MASK, PseudoVMAX_VV_M1, 0x3, false }, // 1446
|
|
{ PseudoVMAX_VV_M2_MASK, PseudoVMAX_VV_M2, 0x3, false }, // 1447
|
|
{ PseudoVMAX_VV_M4_MASK, PseudoVMAX_VV_M4, 0x3, false }, // 1448
|
|
{ PseudoVMAX_VV_M8_MASK, PseudoVMAX_VV_M8, 0x3, false }, // 1449
|
|
{ PseudoVMAX_VV_MF2_MASK, PseudoVMAX_VV_MF2, 0x3, false }, // 1450
|
|
{ PseudoVMAX_VV_MF4_MASK, PseudoVMAX_VV_MF4, 0x3, false }, // 1451
|
|
{ PseudoVMAX_VV_MF8_MASK, PseudoVMAX_VV_MF8, 0x3, false }, // 1452
|
|
{ PseudoVMAX_VX_M1_MASK, PseudoVMAX_VX_M1, 0x3, false }, // 1453
|
|
{ PseudoVMAX_VX_M2_MASK, PseudoVMAX_VX_M2, 0x3, false }, // 1454
|
|
{ PseudoVMAX_VX_M4_MASK, PseudoVMAX_VX_M4, 0x3, false }, // 1455
|
|
{ PseudoVMAX_VX_M8_MASK, PseudoVMAX_VX_M8, 0x3, false }, // 1456
|
|
{ PseudoVMAX_VX_MF2_MASK, PseudoVMAX_VX_MF2, 0x3, false }, // 1457
|
|
{ PseudoVMAX_VX_MF4_MASK, PseudoVMAX_VX_MF4, 0x3, false }, // 1458
|
|
{ PseudoVMAX_VX_MF8_MASK, PseudoVMAX_VX_MF8, 0x3, false }, // 1459
|
|
{ PseudoVMFEQ_VFPR16_M1_MASK, PseudoVMFEQ_VFPR16_M1, 0x3, false }, // 1460
|
|
{ PseudoVMFEQ_VFPR16_M2_MASK, PseudoVMFEQ_VFPR16_M2, 0x3, false }, // 1461
|
|
{ PseudoVMFEQ_VFPR16_M4_MASK, PseudoVMFEQ_VFPR16_M4, 0x3, false }, // 1462
|
|
{ PseudoVMFEQ_VFPR16_M8_MASK, PseudoVMFEQ_VFPR16_M8, 0x3, false }, // 1463
|
|
{ PseudoVMFEQ_VFPR16_MF2_MASK, PseudoVMFEQ_VFPR16_MF2, 0x3, false }, // 1464
|
|
{ PseudoVMFEQ_VFPR16_MF4_MASK, PseudoVMFEQ_VFPR16_MF4, 0x3, false }, // 1465
|
|
{ PseudoVMFEQ_VFPR32_M1_MASK, PseudoVMFEQ_VFPR32_M1, 0x3, false }, // 1466
|
|
{ PseudoVMFEQ_VFPR32_M2_MASK, PseudoVMFEQ_VFPR32_M2, 0x3, false }, // 1467
|
|
{ PseudoVMFEQ_VFPR32_M4_MASK, PseudoVMFEQ_VFPR32_M4, 0x3, false }, // 1468
|
|
{ PseudoVMFEQ_VFPR32_M8_MASK, PseudoVMFEQ_VFPR32_M8, 0x3, false }, // 1469
|
|
{ PseudoVMFEQ_VFPR32_MF2_MASK, PseudoVMFEQ_VFPR32_MF2, 0x3, false }, // 1470
|
|
{ PseudoVMFEQ_VFPR64_M1_MASK, PseudoVMFEQ_VFPR64_M1, 0x3, false }, // 1471
|
|
{ PseudoVMFEQ_VFPR64_M2_MASK, PseudoVMFEQ_VFPR64_M2, 0x3, false }, // 1472
|
|
{ PseudoVMFEQ_VFPR64_M4_MASK, PseudoVMFEQ_VFPR64_M4, 0x3, false }, // 1473
|
|
{ PseudoVMFEQ_VFPR64_M8_MASK, PseudoVMFEQ_VFPR64_M8, 0x3, false }, // 1474
|
|
{ PseudoVMFEQ_VV_M1_MASK, PseudoVMFEQ_VV_M1, 0x3, false }, // 1475
|
|
{ PseudoVMFEQ_VV_M2_MASK, PseudoVMFEQ_VV_M2, 0x3, false }, // 1476
|
|
{ PseudoVMFEQ_VV_M4_MASK, PseudoVMFEQ_VV_M4, 0x3, false }, // 1477
|
|
{ PseudoVMFEQ_VV_M8_MASK, PseudoVMFEQ_VV_M8, 0x3, false }, // 1478
|
|
{ PseudoVMFEQ_VV_MF2_MASK, PseudoVMFEQ_VV_MF2, 0x3, false }, // 1479
|
|
{ PseudoVMFEQ_VV_MF4_MASK, PseudoVMFEQ_VV_MF4, 0x3, false }, // 1480
|
|
{ PseudoVMFGE_VFPR16_M1_MASK, PseudoVMFGE_VFPR16_M1, 0x3, false }, // 1481
|
|
{ PseudoVMFGE_VFPR16_M2_MASK, PseudoVMFGE_VFPR16_M2, 0x3, false }, // 1482
|
|
{ PseudoVMFGE_VFPR16_M4_MASK, PseudoVMFGE_VFPR16_M4, 0x3, false }, // 1483
|
|
{ PseudoVMFGE_VFPR16_M8_MASK, PseudoVMFGE_VFPR16_M8, 0x3, false }, // 1484
|
|
{ PseudoVMFGE_VFPR16_MF2_MASK, PseudoVMFGE_VFPR16_MF2, 0x3, false }, // 1485
|
|
{ PseudoVMFGE_VFPR16_MF4_MASK, PseudoVMFGE_VFPR16_MF4, 0x3, false }, // 1486
|
|
{ PseudoVMFGE_VFPR32_M1_MASK, PseudoVMFGE_VFPR32_M1, 0x3, false }, // 1487
|
|
{ PseudoVMFGE_VFPR32_M2_MASK, PseudoVMFGE_VFPR32_M2, 0x3, false }, // 1488
|
|
{ PseudoVMFGE_VFPR32_M4_MASK, PseudoVMFGE_VFPR32_M4, 0x3, false }, // 1489
|
|
{ PseudoVMFGE_VFPR32_M8_MASK, PseudoVMFGE_VFPR32_M8, 0x3, false }, // 1490
|
|
{ PseudoVMFGE_VFPR32_MF2_MASK, PseudoVMFGE_VFPR32_MF2, 0x3, false }, // 1491
|
|
{ PseudoVMFGE_VFPR64_M1_MASK, PseudoVMFGE_VFPR64_M1, 0x3, false }, // 1492
|
|
{ PseudoVMFGE_VFPR64_M2_MASK, PseudoVMFGE_VFPR64_M2, 0x3, false }, // 1493
|
|
{ PseudoVMFGE_VFPR64_M4_MASK, PseudoVMFGE_VFPR64_M4, 0x3, false }, // 1494
|
|
{ PseudoVMFGE_VFPR64_M8_MASK, PseudoVMFGE_VFPR64_M8, 0x3, false }, // 1495
|
|
{ PseudoVMFGT_VFPR16_M1_MASK, PseudoVMFGT_VFPR16_M1, 0x3, false }, // 1496
|
|
{ PseudoVMFGT_VFPR16_M2_MASK, PseudoVMFGT_VFPR16_M2, 0x3, false }, // 1497
|
|
{ PseudoVMFGT_VFPR16_M4_MASK, PseudoVMFGT_VFPR16_M4, 0x3, false }, // 1498
|
|
{ PseudoVMFGT_VFPR16_M8_MASK, PseudoVMFGT_VFPR16_M8, 0x3, false }, // 1499
|
|
{ PseudoVMFGT_VFPR16_MF2_MASK, PseudoVMFGT_VFPR16_MF2, 0x3, false }, // 1500
|
|
{ PseudoVMFGT_VFPR16_MF4_MASK, PseudoVMFGT_VFPR16_MF4, 0x3, false }, // 1501
|
|
{ PseudoVMFGT_VFPR32_M1_MASK, PseudoVMFGT_VFPR32_M1, 0x3, false }, // 1502
|
|
{ PseudoVMFGT_VFPR32_M2_MASK, PseudoVMFGT_VFPR32_M2, 0x3, false }, // 1503
|
|
{ PseudoVMFGT_VFPR32_M4_MASK, PseudoVMFGT_VFPR32_M4, 0x3, false }, // 1504
|
|
{ PseudoVMFGT_VFPR32_M8_MASK, PseudoVMFGT_VFPR32_M8, 0x3, false }, // 1505
|
|
{ PseudoVMFGT_VFPR32_MF2_MASK, PseudoVMFGT_VFPR32_MF2, 0x3, false }, // 1506
|
|
{ PseudoVMFGT_VFPR64_M1_MASK, PseudoVMFGT_VFPR64_M1, 0x3, false }, // 1507
|
|
{ PseudoVMFGT_VFPR64_M2_MASK, PseudoVMFGT_VFPR64_M2, 0x3, false }, // 1508
|
|
{ PseudoVMFGT_VFPR64_M4_MASK, PseudoVMFGT_VFPR64_M4, 0x3, false }, // 1509
|
|
{ PseudoVMFGT_VFPR64_M8_MASK, PseudoVMFGT_VFPR64_M8, 0x3, false }, // 1510
|
|
{ PseudoVMFLE_VFPR16_M1_MASK, PseudoVMFLE_VFPR16_M1, 0x3, false }, // 1511
|
|
{ PseudoVMFLE_VFPR16_M2_MASK, PseudoVMFLE_VFPR16_M2, 0x3, false }, // 1512
|
|
{ PseudoVMFLE_VFPR16_M4_MASK, PseudoVMFLE_VFPR16_M4, 0x3, false }, // 1513
|
|
{ PseudoVMFLE_VFPR16_M8_MASK, PseudoVMFLE_VFPR16_M8, 0x3, false }, // 1514
|
|
{ PseudoVMFLE_VFPR16_MF2_MASK, PseudoVMFLE_VFPR16_MF2, 0x3, false }, // 1515
|
|
{ PseudoVMFLE_VFPR16_MF4_MASK, PseudoVMFLE_VFPR16_MF4, 0x3, false }, // 1516
|
|
{ PseudoVMFLE_VFPR32_M1_MASK, PseudoVMFLE_VFPR32_M1, 0x3, false }, // 1517
|
|
{ PseudoVMFLE_VFPR32_M2_MASK, PseudoVMFLE_VFPR32_M2, 0x3, false }, // 1518
|
|
{ PseudoVMFLE_VFPR32_M4_MASK, PseudoVMFLE_VFPR32_M4, 0x3, false }, // 1519
|
|
{ PseudoVMFLE_VFPR32_M8_MASK, PseudoVMFLE_VFPR32_M8, 0x3, false }, // 1520
|
|
{ PseudoVMFLE_VFPR32_MF2_MASK, PseudoVMFLE_VFPR32_MF2, 0x3, false }, // 1521
|
|
{ PseudoVMFLE_VFPR64_M1_MASK, PseudoVMFLE_VFPR64_M1, 0x3, false }, // 1522
|
|
{ PseudoVMFLE_VFPR64_M2_MASK, PseudoVMFLE_VFPR64_M2, 0x3, false }, // 1523
|
|
{ PseudoVMFLE_VFPR64_M4_MASK, PseudoVMFLE_VFPR64_M4, 0x3, false }, // 1524
|
|
{ PseudoVMFLE_VFPR64_M8_MASK, PseudoVMFLE_VFPR64_M8, 0x3, false }, // 1525
|
|
{ PseudoVMFLE_VV_M1_MASK, PseudoVMFLE_VV_M1, 0x3, false }, // 1526
|
|
{ PseudoVMFLE_VV_M2_MASK, PseudoVMFLE_VV_M2, 0x3, false }, // 1527
|
|
{ PseudoVMFLE_VV_M4_MASK, PseudoVMFLE_VV_M4, 0x3, false }, // 1528
|
|
{ PseudoVMFLE_VV_M8_MASK, PseudoVMFLE_VV_M8, 0x3, false }, // 1529
|
|
{ PseudoVMFLE_VV_MF2_MASK, PseudoVMFLE_VV_MF2, 0x3, false }, // 1530
|
|
{ PseudoVMFLE_VV_MF4_MASK, PseudoVMFLE_VV_MF4, 0x3, false }, // 1531
|
|
{ PseudoVMFLT_VFPR16_M1_MASK, PseudoVMFLT_VFPR16_M1, 0x3, false }, // 1532
|
|
{ PseudoVMFLT_VFPR16_M2_MASK, PseudoVMFLT_VFPR16_M2, 0x3, false }, // 1533
|
|
{ PseudoVMFLT_VFPR16_M4_MASK, PseudoVMFLT_VFPR16_M4, 0x3, false }, // 1534
|
|
{ PseudoVMFLT_VFPR16_M8_MASK, PseudoVMFLT_VFPR16_M8, 0x3, false }, // 1535
|
|
{ PseudoVMFLT_VFPR16_MF2_MASK, PseudoVMFLT_VFPR16_MF2, 0x3, false }, // 1536
|
|
{ PseudoVMFLT_VFPR16_MF4_MASK, PseudoVMFLT_VFPR16_MF4, 0x3, false }, // 1537
|
|
{ PseudoVMFLT_VFPR32_M1_MASK, PseudoVMFLT_VFPR32_M1, 0x3, false }, // 1538
|
|
{ PseudoVMFLT_VFPR32_M2_MASK, PseudoVMFLT_VFPR32_M2, 0x3, false }, // 1539
|
|
{ PseudoVMFLT_VFPR32_M4_MASK, PseudoVMFLT_VFPR32_M4, 0x3, false }, // 1540
|
|
{ PseudoVMFLT_VFPR32_M8_MASK, PseudoVMFLT_VFPR32_M8, 0x3, false }, // 1541
|
|
{ PseudoVMFLT_VFPR32_MF2_MASK, PseudoVMFLT_VFPR32_MF2, 0x3, false }, // 1542
|
|
{ PseudoVMFLT_VFPR64_M1_MASK, PseudoVMFLT_VFPR64_M1, 0x3, false }, // 1543
|
|
{ PseudoVMFLT_VFPR64_M2_MASK, PseudoVMFLT_VFPR64_M2, 0x3, false }, // 1544
|
|
{ PseudoVMFLT_VFPR64_M4_MASK, PseudoVMFLT_VFPR64_M4, 0x3, false }, // 1545
|
|
{ PseudoVMFLT_VFPR64_M8_MASK, PseudoVMFLT_VFPR64_M8, 0x3, false }, // 1546
|
|
{ PseudoVMFLT_VV_M1_MASK, PseudoVMFLT_VV_M1, 0x3, false }, // 1547
|
|
{ PseudoVMFLT_VV_M2_MASK, PseudoVMFLT_VV_M2, 0x3, false }, // 1548
|
|
{ PseudoVMFLT_VV_M4_MASK, PseudoVMFLT_VV_M4, 0x3, false }, // 1549
|
|
{ PseudoVMFLT_VV_M8_MASK, PseudoVMFLT_VV_M8, 0x3, false }, // 1550
|
|
{ PseudoVMFLT_VV_MF2_MASK, PseudoVMFLT_VV_MF2, 0x3, false }, // 1551
|
|
{ PseudoVMFLT_VV_MF4_MASK, PseudoVMFLT_VV_MF4, 0x3, false }, // 1552
|
|
{ PseudoVMFNE_VFPR16_M1_MASK, PseudoVMFNE_VFPR16_M1, 0x3, false }, // 1553
|
|
{ PseudoVMFNE_VFPR16_M2_MASK, PseudoVMFNE_VFPR16_M2, 0x3, false }, // 1554
|
|
{ PseudoVMFNE_VFPR16_M4_MASK, PseudoVMFNE_VFPR16_M4, 0x3, false }, // 1555
|
|
{ PseudoVMFNE_VFPR16_M8_MASK, PseudoVMFNE_VFPR16_M8, 0x3, false }, // 1556
|
|
{ PseudoVMFNE_VFPR16_MF2_MASK, PseudoVMFNE_VFPR16_MF2, 0x3, false }, // 1557
|
|
{ PseudoVMFNE_VFPR16_MF4_MASK, PseudoVMFNE_VFPR16_MF4, 0x3, false }, // 1558
|
|
{ PseudoVMFNE_VFPR32_M1_MASK, PseudoVMFNE_VFPR32_M1, 0x3, false }, // 1559
|
|
{ PseudoVMFNE_VFPR32_M2_MASK, PseudoVMFNE_VFPR32_M2, 0x3, false }, // 1560
|
|
{ PseudoVMFNE_VFPR32_M4_MASK, PseudoVMFNE_VFPR32_M4, 0x3, false }, // 1561
|
|
{ PseudoVMFNE_VFPR32_M8_MASK, PseudoVMFNE_VFPR32_M8, 0x3, false }, // 1562
|
|
{ PseudoVMFNE_VFPR32_MF2_MASK, PseudoVMFNE_VFPR32_MF2, 0x3, false }, // 1563
|
|
{ PseudoVMFNE_VFPR64_M1_MASK, PseudoVMFNE_VFPR64_M1, 0x3, false }, // 1564
|
|
{ PseudoVMFNE_VFPR64_M2_MASK, PseudoVMFNE_VFPR64_M2, 0x3, false }, // 1565
|
|
{ PseudoVMFNE_VFPR64_M4_MASK, PseudoVMFNE_VFPR64_M4, 0x3, false }, // 1566
|
|
{ PseudoVMFNE_VFPR64_M8_MASK, PseudoVMFNE_VFPR64_M8, 0x3, false }, // 1567
|
|
{ PseudoVMFNE_VV_M1_MASK, PseudoVMFNE_VV_M1, 0x3, false }, // 1568
|
|
{ PseudoVMFNE_VV_M2_MASK, PseudoVMFNE_VV_M2, 0x3, false }, // 1569
|
|
{ PseudoVMFNE_VV_M4_MASK, PseudoVMFNE_VV_M4, 0x3, false }, // 1570
|
|
{ PseudoVMFNE_VV_M8_MASK, PseudoVMFNE_VV_M8, 0x3, false }, // 1571
|
|
{ PseudoVMFNE_VV_MF2_MASK, PseudoVMFNE_VV_MF2, 0x3, false }, // 1572
|
|
{ PseudoVMFNE_VV_MF4_MASK, PseudoVMFNE_VV_MF4, 0x3, false }, // 1573
|
|
{ PseudoVMINU_VV_M1_MASK, PseudoVMINU_VV_M1, 0x3, false }, // 1574
|
|
{ PseudoVMINU_VV_M2_MASK, PseudoVMINU_VV_M2, 0x3, false }, // 1575
|
|
{ PseudoVMINU_VV_M4_MASK, PseudoVMINU_VV_M4, 0x3, false }, // 1576
|
|
{ PseudoVMINU_VV_M8_MASK, PseudoVMINU_VV_M8, 0x3, false }, // 1577
|
|
{ PseudoVMINU_VV_MF2_MASK, PseudoVMINU_VV_MF2, 0x3, false }, // 1578
|
|
{ PseudoVMINU_VV_MF4_MASK, PseudoVMINU_VV_MF4, 0x3, false }, // 1579
|
|
{ PseudoVMINU_VV_MF8_MASK, PseudoVMINU_VV_MF8, 0x3, false }, // 1580
|
|
{ PseudoVMINU_VX_M1_MASK, PseudoVMINU_VX_M1, 0x3, false }, // 1581
|
|
{ PseudoVMINU_VX_M2_MASK, PseudoVMINU_VX_M2, 0x3, false }, // 1582
|
|
{ PseudoVMINU_VX_M4_MASK, PseudoVMINU_VX_M4, 0x3, false }, // 1583
|
|
{ PseudoVMINU_VX_M8_MASK, PseudoVMINU_VX_M8, 0x3, false }, // 1584
|
|
{ PseudoVMINU_VX_MF2_MASK, PseudoVMINU_VX_MF2, 0x3, false }, // 1585
|
|
{ PseudoVMINU_VX_MF4_MASK, PseudoVMINU_VX_MF4, 0x3, false }, // 1586
|
|
{ PseudoVMINU_VX_MF8_MASK, PseudoVMINU_VX_MF8, 0x3, false }, // 1587
|
|
{ PseudoVMIN_VV_M1_MASK, PseudoVMIN_VV_M1, 0x3, false }, // 1588
|
|
{ PseudoVMIN_VV_M2_MASK, PseudoVMIN_VV_M2, 0x3, false }, // 1589
|
|
{ PseudoVMIN_VV_M4_MASK, PseudoVMIN_VV_M4, 0x3, false }, // 1590
|
|
{ PseudoVMIN_VV_M8_MASK, PseudoVMIN_VV_M8, 0x3, false }, // 1591
|
|
{ PseudoVMIN_VV_MF2_MASK, PseudoVMIN_VV_MF2, 0x3, false }, // 1592
|
|
{ PseudoVMIN_VV_MF4_MASK, PseudoVMIN_VV_MF4, 0x3, false }, // 1593
|
|
{ PseudoVMIN_VV_MF8_MASK, PseudoVMIN_VV_MF8, 0x3, false }, // 1594
|
|
{ PseudoVMIN_VX_M1_MASK, PseudoVMIN_VX_M1, 0x3, false }, // 1595
|
|
{ PseudoVMIN_VX_M2_MASK, PseudoVMIN_VX_M2, 0x3, false }, // 1596
|
|
{ PseudoVMIN_VX_M4_MASK, PseudoVMIN_VX_M4, 0x3, false }, // 1597
|
|
{ PseudoVMIN_VX_M8_MASK, PseudoVMIN_VX_M8, 0x3, false }, // 1598
|
|
{ PseudoVMIN_VX_MF2_MASK, PseudoVMIN_VX_MF2, 0x3, false }, // 1599
|
|
{ PseudoVMIN_VX_MF4_MASK, PseudoVMIN_VX_MF4, 0x3, false }, // 1600
|
|
{ PseudoVMIN_VX_MF8_MASK, PseudoVMIN_VX_MF8, 0x3, false }, // 1601
|
|
{ PseudoVMSEQ_VI_M1_MASK, PseudoVMSEQ_VI_M1, 0x3, false }, // 1602
|
|
{ PseudoVMSEQ_VI_M2_MASK, PseudoVMSEQ_VI_M2, 0x3, false }, // 1603
|
|
{ PseudoVMSEQ_VI_M4_MASK, PseudoVMSEQ_VI_M4, 0x3, false }, // 1604
|
|
{ PseudoVMSEQ_VI_M8_MASK, PseudoVMSEQ_VI_M8, 0x3, false }, // 1605
|
|
{ PseudoVMSEQ_VI_MF2_MASK, PseudoVMSEQ_VI_MF2, 0x3, false }, // 1606
|
|
{ PseudoVMSEQ_VI_MF4_MASK, PseudoVMSEQ_VI_MF4, 0x3, false }, // 1607
|
|
{ PseudoVMSEQ_VI_MF8_MASK, PseudoVMSEQ_VI_MF8, 0x3, false }, // 1608
|
|
{ PseudoVMSEQ_VV_M1_MASK, PseudoVMSEQ_VV_M1, 0x3, false }, // 1609
|
|
{ PseudoVMSEQ_VV_M2_MASK, PseudoVMSEQ_VV_M2, 0x3, false }, // 1610
|
|
{ PseudoVMSEQ_VV_M4_MASK, PseudoVMSEQ_VV_M4, 0x3, false }, // 1611
|
|
{ PseudoVMSEQ_VV_M8_MASK, PseudoVMSEQ_VV_M8, 0x3, false }, // 1612
|
|
{ PseudoVMSEQ_VV_MF2_MASK, PseudoVMSEQ_VV_MF2, 0x3, false }, // 1613
|
|
{ PseudoVMSEQ_VV_MF4_MASK, PseudoVMSEQ_VV_MF4, 0x3, false }, // 1614
|
|
{ PseudoVMSEQ_VV_MF8_MASK, PseudoVMSEQ_VV_MF8, 0x3, false }, // 1615
|
|
{ PseudoVMSEQ_VX_M1_MASK, PseudoVMSEQ_VX_M1, 0x3, false }, // 1616
|
|
{ PseudoVMSEQ_VX_M2_MASK, PseudoVMSEQ_VX_M2, 0x3, false }, // 1617
|
|
{ PseudoVMSEQ_VX_M4_MASK, PseudoVMSEQ_VX_M4, 0x3, false }, // 1618
|
|
{ PseudoVMSEQ_VX_M8_MASK, PseudoVMSEQ_VX_M8, 0x3, false }, // 1619
|
|
{ PseudoVMSEQ_VX_MF2_MASK, PseudoVMSEQ_VX_MF2, 0x3, false }, // 1620
|
|
{ PseudoVMSEQ_VX_MF4_MASK, PseudoVMSEQ_VX_MF4, 0x3, false }, // 1621
|
|
{ PseudoVMSEQ_VX_MF8_MASK, PseudoVMSEQ_VX_MF8, 0x3, false }, // 1622
|
|
{ PseudoVMSGTU_VI_M1_MASK, PseudoVMSGTU_VI_M1, 0x3, false }, // 1623
|
|
{ PseudoVMSGTU_VI_M2_MASK, PseudoVMSGTU_VI_M2, 0x3, false }, // 1624
|
|
{ PseudoVMSGTU_VI_M4_MASK, PseudoVMSGTU_VI_M4, 0x3, false }, // 1625
|
|
{ PseudoVMSGTU_VI_M8_MASK, PseudoVMSGTU_VI_M8, 0x3, false }, // 1626
|
|
{ PseudoVMSGTU_VI_MF2_MASK, PseudoVMSGTU_VI_MF2, 0x3, false }, // 1627
|
|
{ PseudoVMSGTU_VI_MF4_MASK, PseudoVMSGTU_VI_MF4, 0x3, false }, // 1628
|
|
{ PseudoVMSGTU_VI_MF8_MASK, PseudoVMSGTU_VI_MF8, 0x3, false }, // 1629
|
|
{ PseudoVMSGTU_VX_M1_MASK, PseudoVMSGTU_VX_M1, 0x3, false }, // 1630
|
|
{ PseudoVMSGTU_VX_M2_MASK, PseudoVMSGTU_VX_M2, 0x3, false }, // 1631
|
|
{ PseudoVMSGTU_VX_M4_MASK, PseudoVMSGTU_VX_M4, 0x3, false }, // 1632
|
|
{ PseudoVMSGTU_VX_M8_MASK, PseudoVMSGTU_VX_M8, 0x3, false }, // 1633
|
|
{ PseudoVMSGTU_VX_MF2_MASK, PseudoVMSGTU_VX_MF2, 0x3, false }, // 1634
|
|
{ PseudoVMSGTU_VX_MF4_MASK, PseudoVMSGTU_VX_MF4, 0x3, false }, // 1635
|
|
{ PseudoVMSGTU_VX_MF8_MASK, PseudoVMSGTU_VX_MF8, 0x3, false }, // 1636
|
|
{ PseudoVMSGT_VI_M1_MASK, PseudoVMSGT_VI_M1, 0x3, false }, // 1637
|
|
{ PseudoVMSGT_VI_M2_MASK, PseudoVMSGT_VI_M2, 0x3, false }, // 1638
|
|
{ PseudoVMSGT_VI_M4_MASK, PseudoVMSGT_VI_M4, 0x3, false }, // 1639
|
|
{ PseudoVMSGT_VI_M8_MASK, PseudoVMSGT_VI_M8, 0x3, false }, // 1640
|
|
{ PseudoVMSGT_VI_MF2_MASK, PseudoVMSGT_VI_MF2, 0x3, false }, // 1641
|
|
{ PseudoVMSGT_VI_MF4_MASK, PseudoVMSGT_VI_MF4, 0x3, false }, // 1642
|
|
{ PseudoVMSGT_VI_MF8_MASK, PseudoVMSGT_VI_MF8, 0x3, false }, // 1643
|
|
{ PseudoVMSGT_VX_M1_MASK, PseudoVMSGT_VX_M1, 0x3, false }, // 1644
|
|
{ PseudoVMSGT_VX_M2_MASK, PseudoVMSGT_VX_M2, 0x3, false }, // 1645
|
|
{ PseudoVMSGT_VX_M4_MASK, PseudoVMSGT_VX_M4, 0x3, false }, // 1646
|
|
{ PseudoVMSGT_VX_M8_MASK, PseudoVMSGT_VX_M8, 0x3, false }, // 1647
|
|
{ PseudoVMSGT_VX_MF2_MASK, PseudoVMSGT_VX_MF2, 0x3, false }, // 1648
|
|
{ PseudoVMSGT_VX_MF4_MASK, PseudoVMSGT_VX_MF4, 0x3, false }, // 1649
|
|
{ PseudoVMSGT_VX_MF8_MASK, PseudoVMSGT_VX_MF8, 0x3, false }, // 1650
|
|
{ PseudoVMSLEU_VI_M1_MASK, PseudoVMSLEU_VI_M1, 0x3, false }, // 1651
|
|
{ PseudoVMSLEU_VI_M2_MASK, PseudoVMSLEU_VI_M2, 0x3, false }, // 1652
|
|
{ PseudoVMSLEU_VI_M4_MASK, PseudoVMSLEU_VI_M4, 0x3, false }, // 1653
|
|
{ PseudoVMSLEU_VI_M8_MASK, PseudoVMSLEU_VI_M8, 0x3, false }, // 1654
|
|
{ PseudoVMSLEU_VI_MF2_MASK, PseudoVMSLEU_VI_MF2, 0x3, false }, // 1655
|
|
{ PseudoVMSLEU_VI_MF4_MASK, PseudoVMSLEU_VI_MF4, 0x3, false }, // 1656
|
|
{ PseudoVMSLEU_VI_MF8_MASK, PseudoVMSLEU_VI_MF8, 0x3, false }, // 1657
|
|
{ PseudoVMSLEU_VV_M1_MASK, PseudoVMSLEU_VV_M1, 0x3, false }, // 1658
|
|
{ PseudoVMSLEU_VV_M2_MASK, PseudoVMSLEU_VV_M2, 0x3, false }, // 1659
|
|
{ PseudoVMSLEU_VV_M4_MASK, PseudoVMSLEU_VV_M4, 0x3, false }, // 1660
|
|
{ PseudoVMSLEU_VV_M8_MASK, PseudoVMSLEU_VV_M8, 0x3, false }, // 1661
|
|
{ PseudoVMSLEU_VV_MF2_MASK, PseudoVMSLEU_VV_MF2, 0x3, false }, // 1662
|
|
{ PseudoVMSLEU_VV_MF4_MASK, PseudoVMSLEU_VV_MF4, 0x3, false }, // 1663
|
|
{ PseudoVMSLEU_VV_MF8_MASK, PseudoVMSLEU_VV_MF8, 0x3, false }, // 1664
|
|
{ PseudoVMSLEU_VX_M1_MASK, PseudoVMSLEU_VX_M1, 0x3, false }, // 1665
|
|
{ PseudoVMSLEU_VX_M2_MASK, PseudoVMSLEU_VX_M2, 0x3, false }, // 1666
|
|
{ PseudoVMSLEU_VX_M4_MASK, PseudoVMSLEU_VX_M4, 0x3, false }, // 1667
|
|
{ PseudoVMSLEU_VX_M8_MASK, PseudoVMSLEU_VX_M8, 0x3, false }, // 1668
|
|
{ PseudoVMSLEU_VX_MF2_MASK, PseudoVMSLEU_VX_MF2, 0x3, false }, // 1669
|
|
{ PseudoVMSLEU_VX_MF4_MASK, PseudoVMSLEU_VX_MF4, 0x3, false }, // 1670
|
|
{ PseudoVMSLEU_VX_MF8_MASK, PseudoVMSLEU_VX_MF8, 0x3, false }, // 1671
|
|
{ PseudoVMSLE_VI_M1_MASK, PseudoVMSLE_VI_M1, 0x3, false }, // 1672
|
|
{ PseudoVMSLE_VI_M2_MASK, PseudoVMSLE_VI_M2, 0x3, false }, // 1673
|
|
{ PseudoVMSLE_VI_M4_MASK, PseudoVMSLE_VI_M4, 0x3, false }, // 1674
|
|
{ PseudoVMSLE_VI_M8_MASK, PseudoVMSLE_VI_M8, 0x3, false }, // 1675
|
|
{ PseudoVMSLE_VI_MF2_MASK, PseudoVMSLE_VI_MF2, 0x3, false }, // 1676
|
|
{ PseudoVMSLE_VI_MF4_MASK, PseudoVMSLE_VI_MF4, 0x3, false }, // 1677
|
|
{ PseudoVMSLE_VI_MF8_MASK, PseudoVMSLE_VI_MF8, 0x3, false }, // 1678
|
|
{ PseudoVMSLE_VV_M1_MASK, PseudoVMSLE_VV_M1, 0x3, false }, // 1679
|
|
{ PseudoVMSLE_VV_M2_MASK, PseudoVMSLE_VV_M2, 0x3, false }, // 1680
|
|
{ PseudoVMSLE_VV_M4_MASK, PseudoVMSLE_VV_M4, 0x3, false }, // 1681
|
|
{ PseudoVMSLE_VV_M8_MASK, PseudoVMSLE_VV_M8, 0x3, false }, // 1682
|
|
{ PseudoVMSLE_VV_MF2_MASK, PseudoVMSLE_VV_MF2, 0x3, false }, // 1683
|
|
{ PseudoVMSLE_VV_MF4_MASK, PseudoVMSLE_VV_MF4, 0x3, false }, // 1684
|
|
{ PseudoVMSLE_VV_MF8_MASK, PseudoVMSLE_VV_MF8, 0x3, false }, // 1685
|
|
{ PseudoVMSLE_VX_M1_MASK, PseudoVMSLE_VX_M1, 0x3, false }, // 1686
|
|
{ PseudoVMSLE_VX_M2_MASK, PseudoVMSLE_VX_M2, 0x3, false }, // 1687
|
|
{ PseudoVMSLE_VX_M4_MASK, PseudoVMSLE_VX_M4, 0x3, false }, // 1688
|
|
{ PseudoVMSLE_VX_M8_MASK, PseudoVMSLE_VX_M8, 0x3, false }, // 1689
|
|
{ PseudoVMSLE_VX_MF2_MASK, PseudoVMSLE_VX_MF2, 0x3, false }, // 1690
|
|
{ PseudoVMSLE_VX_MF4_MASK, PseudoVMSLE_VX_MF4, 0x3, false }, // 1691
|
|
{ PseudoVMSLE_VX_MF8_MASK, PseudoVMSLE_VX_MF8, 0x3, false }, // 1692
|
|
{ PseudoVMSLTU_VV_M1_MASK, PseudoVMSLTU_VV_M1, 0x3, false }, // 1693
|
|
{ PseudoVMSLTU_VV_M2_MASK, PseudoVMSLTU_VV_M2, 0x3, false }, // 1694
|
|
{ PseudoVMSLTU_VV_M4_MASK, PseudoVMSLTU_VV_M4, 0x3, false }, // 1695
|
|
{ PseudoVMSLTU_VV_M8_MASK, PseudoVMSLTU_VV_M8, 0x3, false }, // 1696
|
|
{ PseudoVMSLTU_VV_MF2_MASK, PseudoVMSLTU_VV_MF2, 0x3, false }, // 1697
|
|
{ PseudoVMSLTU_VV_MF4_MASK, PseudoVMSLTU_VV_MF4, 0x3, false }, // 1698
|
|
{ PseudoVMSLTU_VV_MF8_MASK, PseudoVMSLTU_VV_MF8, 0x3, false }, // 1699
|
|
{ PseudoVMSLTU_VX_M1_MASK, PseudoVMSLTU_VX_M1, 0x3, false }, // 1700
|
|
{ PseudoVMSLTU_VX_M2_MASK, PseudoVMSLTU_VX_M2, 0x3, false }, // 1701
|
|
{ PseudoVMSLTU_VX_M4_MASK, PseudoVMSLTU_VX_M4, 0x3, false }, // 1702
|
|
{ PseudoVMSLTU_VX_M8_MASK, PseudoVMSLTU_VX_M8, 0x3, false }, // 1703
|
|
{ PseudoVMSLTU_VX_MF2_MASK, PseudoVMSLTU_VX_MF2, 0x3, false }, // 1704
|
|
{ PseudoVMSLTU_VX_MF4_MASK, PseudoVMSLTU_VX_MF4, 0x3, false }, // 1705
|
|
{ PseudoVMSLTU_VX_MF8_MASK, PseudoVMSLTU_VX_MF8, 0x3, false }, // 1706
|
|
{ PseudoVMSLT_VV_M1_MASK, PseudoVMSLT_VV_M1, 0x3, false }, // 1707
|
|
{ PseudoVMSLT_VV_M2_MASK, PseudoVMSLT_VV_M2, 0x3, false }, // 1708
|
|
{ PseudoVMSLT_VV_M4_MASK, PseudoVMSLT_VV_M4, 0x3, false }, // 1709
|
|
{ PseudoVMSLT_VV_M8_MASK, PseudoVMSLT_VV_M8, 0x3, false }, // 1710
|
|
{ PseudoVMSLT_VV_MF2_MASK, PseudoVMSLT_VV_MF2, 0x3, false }, // 1711
|
|
{ PseudoVMSLT_VV_MF4_MASK, PseudoVMSLT_VV_MF4, 0x3, false }, // 1712
|
|
{ PseudoVMSLT_VV_MF8_MASK, PseudoVMSLT_VV_MF8, 0x3, false }, // 1713
|
|
{ PseudoVMSLT_VX_M1_MASK, PseudoVMSLT_VX_M1, 0x3, false }, // 1714
|
|
{ PseudoVMSLT_VX_M2_MASK, PseudoVMSLT_VX_M2, 0x3, false }, // 1715
|
|
{ PseudoVMSLT_VX_M4_MASK, PseudoVMSLT_VX_M4, 0x3, false }, // 1716
|
|
{ PseudoVMSLT_VX_M8_MASK, PseudoVMSLT_VX_M8, 0x3, false }, // 1717
|
|
{ PseudoVMSLT_VX_MF2_MASK, PseudoVMSLT_VX_MF2, 0x3, false }, // 1718
|
|
{ PseudoVMSLT_VX_MF4_MASK, PseudoVMSLT_VX_MF4, 0x3, false }, // 1719
|
|
{ PseudoVMSLT_VX_MF8_MASK, PseudoVMSLT_VX_MF8, 0x3, false }, // 1720
|
|
{ PseudoVMSNE_VI_M1_MASK, PseudoVMSNE_VI_M1, 0x3, false }, // 1721
|
|
{ PseudoVMSNE_VI_M2_MASK, PseudoVMSNE_VI_M2, 0x3, false }, // 1722
|
|
{ PseudoVMSNE_VI_M4_MASK, PseudoVMSNE_VI_M4, 0x3, false }, // 1723
|
|
{ PseudoVMSNE_VI_M8_MASK, PseudoVMSNE_VI_M8, 0x3, false }, // 1724
|
|
{ PseudoVMSNE_VI_MF2_MASK, PseudoVMSNE_VI_MF2, 0x3, false }, // 1725
|
|
{ PseudoVMSNE_VI_MF4_MASK, PseudoVMSNE_VI_MF4, 0x3, false }, // 1726
|
|
{ PseudoVMSNE_VI_MF8_MASK, PseudoVMSNE_VI_MF8, 0x3, false }, // 1727
|
|
{ PseudoVMSNE_VV_M1_MASK, PseudoVMSNE_VV_M1, 0x3, false }, // 1728
|
|
{ PseudoVMSNE_VV_M2_MASK, PseudoVMSNE_VV_M2, 0x3, false }, // 1729
|
|
{ PseudoVMSNE_VV_M4_MASK, PseudoVMSNE_VV_M4, 0x3, false }, // 1730
|
|
{ PseudoVMSNE_VV_M8_MASK, PseudoVMSNE_VV_M8, 0x3, false }, // 1731
|
|
{ PseudoVMSNE_VV_MF2_MASK, PseudoVMSNE_VV_MF2, 0x3, false }, // 1732
|
|
{ PseudoVMSNE_VV_MF4_MASK, PseudoVMSNE_VV_MF4, 0x3, false }, // 1733
|
|
{ PseudoVMSNE_VV_MF8_MASK, PseudoVMSNE_VV_MF8, 0x3, false }, // 1734
|
|
{ PseudoVMSNE_VX_M1_MASK, PseudoVMSNE_VX_M1, 0x3, false }, // 1735
|
|
{ PseudoVMSNE_VX_M2_MASK, PseudoVMSNE_VX_M2, 0x3, false }, // 1736
|
|
{ PseudoVMSNE_VX_M4_MASK, PseudoVMSNE_VX_M4, 0x3, false }, // 1737
|
|
{ PseudoVMSNE_VX_M8_MASK, PseudoVMSNE_VX_M8, 0x3, false }, // 1738
|
|
{ PseudoVMSNE_VX_MF2_MASK, PseudoVMSNE_VX_MF2, 0x3, false }, // 1739
|
|
{ PseudoVMSNE_VX_MF4_MASK, PseudoVMSNE_VX_MF4, 0x3, false }, // 1740
|
|
{ PseudoVMSNE_VX_MF8_MASK, PseudoVMSNE_VX_MF8, 0x3, false }, // 1741
|
|
{ PseudoVMULHSU_VV_M1_MASK, PseudoVMULHSU_VV_M1, 0x3, false }, // 1742
|
|
{ PseudoVMULHSU_VV_M2_MASK, PseudoVMULHSU_VV_M2, 0x3, false }, // 1743
|
|
{ PseudoVMULHSU_VV_M4_MASK, PseudoVMULHSU_VV_M4, 0x3, false }, // 1744
|
|
{ PseudoVMULHSU_VV_M8_MASK, PseudoVMULHSU_VV_M8, 0x3, false }, // 1745
|
|
{ PseudoVMULHSU_VV_MF2_MASK, PseudoVMULHSU_VV_MF2, 0x3, false }, // 1746
|
|
{ PseudoVMULHSU_VV_MF4_MASK, PseudoVMULHSU_VV_MF4, 0x3, false }, // 1747
|
|
{ PseudoVMULHSU_VV_MF8_MASK, PseudoVMULHSU_VV_MF8, 0x3, false }, // 1748
|
|
{ PseudoVMULHSU_VX_M1_MASK, PseudoVMULHSU_VX_M1, 0x3, false }, // 1749
|
|
{ PseudoVMULHSU_VX_M2_MASK, PseudoVMULHSU_VX_M2, 0x3, false }, // 1750
|
|
{ PseudoVMULHSU_VX_M4_MASK, PseudoVMULHSU_VX_M4, 0x3, false }, // 1751
|
|
{ PseudoVMULHSU_VX_M8_MASK, PseudoVMULHSU_VX_M8, 0x3, false }, // 1752
|
|
{ PseudoVMULHSU_VX_MF2_MASK, PseudoVMULHSU_VX_MF2, 0x3, false }, // 1753
|
|
{ PseudoVMULHSU_VX_MF4_MASK, PseudoVMULHSU_VX_MF4, 0x3, false }, // 1754
|
|
{ PseudoVMULHSU_VX_MF8_MASK, PseudoVMULHSU_VX_MF8, 0x3, false }, // 1755
|
|
{ PseudoVMULHU_VV_M1_MASK, PseudoVMULHU_VV_M1, 0x3, false }, // 1756
|
|
{ PseudoVMULHU_VV_M2_MASK, PseudoVMULHU_VV_M2, 0x3, false }, // 1757
|
|
{ PseudoVMULHU_VV_M4_MASK, PseudoVMULHU_VV_M4, 0x3, false }, // 1758
|
|
{ PseudoVMULHU_VV_M8_MASK, PseudoVMULHU_VV_M8, 0x3, false }, // 1759
|
|
{ PseudoVMULHU_VV_MF2_MASK, PseudoVMULHU_VV_MF2, 0x3, false }, // 1760
|
|
{ PseudoVMULHU_VV_MF4_MASK, PseudoVMULHU_VV_MF4, 0x3, false }, // 1761
|
|
{ PseudoVMULHU_VV_MF8_MASK, PseudoVMULHU_VV_MF8, 0x3, false }, // 1762
|
|
{ PseudoVMULHU_VX_M1_MASK, PseudoVMULHU_VX_M1, 0x3, false }, // 1763
|
|
{ PseudoVMULHU_VX_M2_MASK, PseudoVMULHU_VX_M2, 0x3, false }, // 1764
|
|
{ PseudoVMULHU_VX_M4_MASK, PseudoVMULHU_VX_M4, 0x3, false }, // 1765
|
|
{ PseudoVMULHU_VX_M8_MASK, PseudoVMULHU_VX_M8, 0x3, false }, // 1766
|
|
{ PseudoVMULHU_VX_MF2_MASK, PseudoVMULHU_VX_MF2, 0x3, false }, // 1767
|
|
{ PseudoVMULHU_VX_MF4_MASK, PseudoVMULHU_VX_MF4, 0x3, false }, // 1768
|
|
{ PseudoVMULHU_VX_MF8_MASK, PseudoVMULHU_VX_MF8, 0x3, false }, // 1769
|
|
{ PseudoVMULH_VV_M1_MASK, PseudoVMULH_VV_M1, 0x3, false }, // 1770
|
|
{ PseudoVMULH_VV_M2_MASK, PseudoVMULH_VV_M2, 0x3, false }, // 1771
|
|
{ PseudoVMULH_VV_M4_MASK, PseudoVMULH_VV_M4, 0x3, false }, // 1772
|
|
{ PseudoVMULH_VV_M8_MASK, PseudoVMULH_VV_M8, 0x3, false }, // 1773
|
|
{ PseudoVMULH_VV_MF2_MASK, PseudoVMULH_VV_MF2, 0x3, false }, // 1774
|
|
{ PseudoVMULH_VV_MF4_MASK, PseudoVMULH_VV_MF4, 0x3, false }, // 1775
|
|
{ PseudoVMULH_VV_MF8_MASK, PseudoVMULH_VV_MF8, 0x3, false }, // 1776
|
|
{ PseudoVMULH_VX_M1_MASK, PseudoVMULH_VX_M1, 0x3, false }, // 1777
|
|
{ PseudoVMULH_VX_M2_MASK, PseudoVMULH_VX_M2, 0x3, false }, // 1778
|
|
{ PseudoVMULH_VX_M4_MASK, PseudoVMULH_VX_M4, 0x3, false }, // 1779
|
|
{ PseudoVMULH_VX_M8_MASK, PseudoVMULH_VX_M8, 0x3, false }, // 1780
|
|
{ PseudoVMULH_VX_MF2_MASK, PseudoVMULH_VX_MF2, 0x3, false }, // 1781
|
|
{ PseudoVMULH_VX_MF4_MASK, PseudoVMULH_VX_MF4, 0x3, false }, // 1782
|
|
{ PseudoVMULH_VX_MF8_MASK, PseudoVMULH_VX_MF8, 0x3, false }, // 1783
|
|
{ PseudoVMUL_VV_M1_MASK, PseudoVMUL_VV_M1, 0x3, false }, // 1784
|
|
{ PseudoVMUL_VV_M2_MASK, PseudoVMUL_VV_M2, 0x3, false }, // 1785
|
|
{ PseudoVMUL_VV_M4_MASK, PseudoVMUL_VV_M4, 0x3, false }, // 1786
|
|
{ PseudoVMUL_VV_M8_MASK, PseudoVMUL_VV_M8, 0x3, false }, // 1787
|
|
{ PseudoVMUL_VV_MF2_MASK, PseudoVMUL_VV_MF2, 0x3, false }, // 1788
|
|
{ PseudoVMUL_VV_MF4_MASK, PseudoVMUL_VV_MF4, 0x3, false }, // 1789
|
|
{ PseudoVMUL_VV_MF8_MASK, PseudoVMUL_VV_MF8, 0x3, false }, // 1790
|
|
{ PseudoVMUL_VX_M1_MASK, PseudoVMUL_VX_M1, 0x3, false }, // 1791
|
|
{ PseudoVMUL_VX_M2_MASK, PseudoVMUL_VX_M2, 0x3, false }, // 1792
|
|
{ PseudoVMUL_VX_M4_MASK, PseudoVMUL_VX_M4, 0x3, false }, // 1793
|
|
{ PseudoVMUL_VX_M8_MASK, PseudoVMUL_VX_M8, 0x3, false }, // 1794
|
|
{ PseudoVMUL_VX_MF2_MASK, PseudoVMUL_VX_MF2, 0x3, false }, // 1795
|
|
{ PseudoVMUL_VX_MF4_MASK, PseudoVMUL_VX_MF4, 0x3, false }, // 1796
|
|
{ PseudoVMUL_VX_MF8_MASK, PseudoVMUL_VX_MF8, 0x3, false }, // 1797
|
|
{ PseudoVNCLIPU_WI_M1_MASK, PseudoVNCLIPU_WI_M1, 0x3, false }, // 1798
|
|
{ PseudoVNCLIPU_WI_M2_MASK, PseudoVNCLIPU_WI_M2, 0x3, false }, // 1799
|
|
{ PseudoVNCLIPU_WI_M4_MASK, PseudoVNCLIPU_WI_M4, 0x3, false }, // 1800
|
|
{ PseudoVNCLIPU_WI_MF2_MASK, PseudoVNCLIPU_WI_MF2, 0x3, false }, // 1801
|
|
{ PseudoVNCLIPU_WI_MF4_MASK, PseudoVNCLIPU_WI_MF4, 0x3, false }, // 1802
|
|
{ PseudoVNCLIPU_WI_MF8_MASK, PseudoVNCLIPU_WI_MF8, 0x3, false }, // 1803
|
|
{ PseudoVNCLIPU_WV_M1_MASK, PseudoVNCLIPU_WV_M1, 0x3, false }, // 1804
|
|
{ PseudoVNCLIPU_WV_M2_MASK, PseudoVNCLIPU_WV_M2, 0x3, false }, // 1805
|
|
{ PseudoVNCLIPU_WV_M4_MASK, PseudoVNCLIPU_WV_M4, 0x3, false }, // 1806
|
|
{ PseudoVNCLIPU_WV_MF2_MASK, PseudoVNCLIPU_WV_MF2, 0x3, false }, // 1807
|
|
{ PseudoVNCLIPU_WV_MF4_MASK, PseudoVNCLIPU_WV_MF4, 0x3, false }, // 1808
|
|
{ PseudoVNCLIPU_WV_MF8_MASK, PseudoVNCLIPU_WV_MF8, 0x3, false }, // 1809
|
|
{ PseudoVNCLIPU_WX_M1_MASK, PseudoVNCLIPU_WX_M1, 0x3, false }, // 1810
|
|
{ PseudoVNCLIPU_WX_M2_MASK, PseudoVNCLIPU_WX_M2, 0x3, false }, // 1811
|
|
{ PseudoVNCLIPU_WX_M4_MASK, PseudoVNCLIPU_WX_M4, 0x3, false }, // 1812
|
|
{ PseudoVNCLIPU_WX_MF2_MASK, PseudoVNCLIPU_WX_MF2, 0x3, false }, // 1813
|
|
{ PseudoVNCLIPU_WX_MF4_MASK, PseudoVNCLIPU_WX_MF4, 0x3, false }, // 1814
|
|
{ PseudoVNCLIPU_WX_MF8_MASK, PseudoVNCLIPU_WX_MF8, 0x3, false }, // 1815
|
|
{ PseudoVNCLIP_WI_M1_MASK, PseudoVNCLIP_WI_M1, 0x3, false }, // 1816
|
|
{ PseudoVNCLIP_WI_M2_MASK, PseudoVNCLIP_WI_M2, 0x3, false }, // 1817
|
|
{ PseudoVNCLIP_WI_M4_MASK, PseudoVNCLIP_WI_M4, 0x3, false }, // 1818
|
|
{ PseudoVNCLIP_WI_MF2_MASK, PseudoVNCLIP_WI_MF2, 0x3, false }, // 1819
|
|
{ PseudoVNCLIP_WI_MF4_MASK, PseudoVNCLIP_WI_MF4, 0x3, false }, // 1820
|
|
{ PseudoVNCLIP_WI_MF8_MASK, PseudoVNCLIP_WI_MF8, 0x3, false }, // 1821
|
|
{ PseudoVNCLIP_WV_M1_MASK, PseudoVNCLIP_WV_M1, 0x3, false }, // 1822
|
|
{ PseudoVNCLIP_WV_M2_MASK, PseudoVNCLIP_WV_M2, 0x3, false }, // 1823
|
|
{ PseudoVNCLIP_WV_M4_MASK, PseudoVNCLIP_WV_M4, 0x3, false }, // 1824
|
|
{ PseudoVNCLIP_WV_MF2_MASK, PseudoVNCLIP_WV_MF2, 0x3, false }, // 1825
|
|
{ PseudoVNCLIP_WV_MF4_MASK, PseudoVNCLIP_WV_MF4, 0x3, false }, // 1826
|
|
{ PseudoVNCLIP_WV_MF8_MASK, PseudoVNCLIP_WV_MF8, 0x3, false }, // 1827
|
|
{ PseudoVNCLIP_WX_M1_MASK, PseudoVNCLIP_WX_M1, 0x3, false }, // 1828
|
|
{ PseudoVNCLIP_WX_M2_MASK, PseudoVNCLIP_WX_M2, 0x3, false }, // 1829
|
|
{ PseudoVNCLIP_WX_M4_MASK, PseudoVNCLIP_WX_M4, 0x3, false }, // 1830
|
|
{ PseudoVNCLIP_WX_MF2_MASK, PseudoVNCLIP_WX_MF2, 0x3, false }, // 1831
|
|
{ PseudoVNCLIP_WX_MF4_MASK, PseudoVNCLIP_WX_MF4, 0x3, false }, // 1832
|
|
{ PseudoVNCLIP_WX_MF8_MASK, PseudoVNCLIP_WX_MF8, 0x3, false }, // 1833
|
|
{ PseudoVNMSAC_VV_M1_MASK, PseudoVNMSAC_VV_M1, 0x3, false }, // 1834
|
|
{ PseudoVNMSAC_VV_M2_MASK, PseudoVNMSAC_VV_M2, 0x3, false }, // 1835
|
|
{ PseudoVNMSAC_VV_M4_MASK, PseudoVNMSAC_VV_M4, 0x3, false }, // 1836
|
|
{ PseudoVNMSAC_VV_M8_MASK, PseudoVNMSAC_VV_M8, 0x3, false }, // 1837
|
|
{ PseudoVNMSAC_VV_MF2_MASK, PseudoVNMSAC_VV_MF2, 0x3, false }, // 1838
|
|
{ PseudoVNMSAC_VV_MF4_MASK, PseudoVNMSAC_VV_MF4, 0x3, false }, // 1839
|
|
{ PseudoVNMSAC_VV_MF8_MASK, PseudoVNMSAC_VV_MF8, 0x3, false }, // 1840
|
|
{ PseudoVNMSAC_VX_M1_MASK, PseudoVNMSAC_VX_M1, 0x3, false }, // 1841
|
|
{ PseudoVNMSAC_VX_M2_MASK, PseudoVNMSAC_VX_M2, 0x3, false }, // 1842
|
|
{ PseudoVNMSAC_VX_M4_MASK, PseudoVNMSAC_VX_M4, 0x3, false }, // 1843
|
|
{ PseudoVNMSAC_VX_M8_MASK, PseudoVNMSAC_VX_M8, 0x3, false }, // 1844
|
|
{ PseudoVNMSAC_VX_MF2_MASK, PseudoVNMSAC_VX_MF2, 0x3, false }, // 1845
|
|
{ PseudoVNMSAC_VX_MF4_MASK, PseudoVNMSAC_VX_MF4, 0x3, false }, // 1846
|
|
{ PseudoVNMSAC_VX_MF8_MASK, PseudoVNMSAC_VX_MF8, 0x3, false }, // 1847
|
|
{ PseudoVNMSUB_VV_M1_MASK, PseudoVNMSUB_VV_M1, 0x3, false }, // 1848
|
|
{ PseudoVNMSUB_VV_M2_MASK, PseudoVNMSUB_VV_M2, 0x3, false }, // 1849
|
|
{ PseudoVNMSUB_VV_M4_MASK, PseudoVNMSUB_VV_M4, 0x3, false }, // 1850
|
|
{ PseudoVNMSUB_VV_M8_MASK, PseudoVNMSUB_VV_M8, 0x3, false }, // 1851
|
|
{ PseudoVNMSUB_VV_MF2_MASK, PseudoVNMSUB_VV_MF2, 0x3, false }, // 1852
|
|
{ PseudoVNMSUB_VV_MF4_MASK, PseudoVNMSUB_VV_MF4, 0x3, false }, // 1853
|
|
{ PseudoVNMSUB_VV_MF8_MASK, PseudoVNMSUB_VV_MF8, 0x3, false }, // 1854
|
|
{ PseudoVNMSUB_VX_M1_MASK, PseudoVNMSUB_VX_M1, 0x3, false }, // 1855
|
|
{ PseudoVNMSUB_VX_M2_MASK, PseudoVNMSUB_VX_M2, 0x3, false }, // 1856
|
|
{ PseudoVNMSUB_VX_M4_MASK, PseudoVNMSUB_VX_M4, 0x3, false }, // 1857
|
|
{ PseudoVNMSUB_VX_M8_MASK, PseudoVNMSUB_VX_M8, 0x3, false }, // 1858
|
|
{ PseudoVNMSUB_VX_MF2_MASK, PseudoVNMSUB_VX_MF2, 0x3, false }, // 1859
|
|
{ PseudoVNMSUB_VX_MF4_MASK, PseudoVNMSUB_VX_MF4, 0x3, false }, // 1860
|
|
{ PseudoVNMSUB_VX_MF8_MASK, PseudoVNMSUB_VX_MF8, 0x3, false }, // 1861
|
|
{ PseudoVNSRA_WI_M1_MASK, PseudoVNSRA_WI_M1, 0x3, false }, // 1862
|
|
{ PseudoVNSRA_WI_M2_MASK, PseudoVNSRA_WI_M2, 0x3, false }, // 1863
|
|
{ PseudoVNSRA_WI_M4_MASK, PseudoVNSRA_WI_M4, 0x3, false }, // 1864
|
|
{ PseudoVNSRA_WI_MF2_MASK, PseudoVNSRA_WI_MF2, 0x3, false }, // 1865
|
|
{ PseudoVNSRA_WI_MF4_MASK, PseudoVNSRA_WI_MF4, 0x3, false }, // 1866
|
|
{ PseudoVNSRA_WI_MF8_MASK, PseudoVNSRA_WI_MF8, 0x3, false }, // 1867
|
|
{ PseudoVNSRA_WV_M1_MASK, PseudoVNSRA_WV_M1, 0x3, false }, // 1868
|
|
{ PseudoVNSRA_WV_M2_MASK, PseudoVNSRA_WV_M2, 0x3, false }, // 1869
|
|
{ PseudoVNSRA_WV_M4_MASK, PseudoVNSRA_WV_M4, 0x3, false }, // 1870
|
|
{ PseudoVNSRA_WV_MF2_MASK, PseudoVNSRA_WV_MF2, 0x3, false }, // 1871
|
|
{ PseudoVNSRA_WV_MF4_MASK, PseudoVNSRA_WV_MF4, 0x3, false }, // 1872
|
|
{ PseudoVNSRA_WV_MF8_MASK, PseudoVNSRA_WV_MF8, 0x3, false }, // 1873
|
|
{ PseudoVNSRA_WX_M1_MASK, PseudoVNSRA_WX_M1, 0x3, false }, // 1874
|
|
{ PseudoVNSRA_WX_M2_MASK, PseudoVNSRA_WX_M2, 0x3, false }, // 1875
|
|
{ PseudoVNSRA_WX_M4_MASK, PseudoVNSRA_WX_M4, 0x3, false }, // 1876
|
|
{ PseudoVNSRA_WX_MF2_MASK, PseudoVNSRA_WX_MF2, 0x3, false }, // 1877
|
|
{ PseudoVNSRA_WX_MF4_MASK, PseudoVNSRA_WX_MF4, 0x3, false }, // 1878
|
|
{ PseudoVNSRA_WX_MF8_MASK, PseudoVNSRA_WX_MF8, 0x3, false }, // 1879
|
|
{ PseudoVNSRL_WI_M1_MASK, PseudoVNSRL_WI_M1, 0x3, false }, // 1880
|
|
{ PseudoVNSRL_WI_M2_MASK, PseudoVNSRL_WI_M2, 0x3, false }, // 1881
|
|
{ PseudoVNSRL_WI_M4_MASK, PseudoVNSRL_WI_M4, 0x3, false }, // 1882
|
|
{ PseudoVNSRL_WI_MF2_MASK, PseudoVNSRL_WI_MF2, 0x3, false }, // 1883
|
|
{ PseudoVNSRL_WI_MF4_MASK, PseudoVNSRL_WI_MF4, 0x3, false }, // 1884
|
|
{ PseudoVNSRL_WI_MF8_MASK, PseudoVNSRL_WI_MF8, 0x3, false }, // 1885
|
|
{ PseudoVNSRL_WV_M1_MASK, PseudoVNSRL_WV_M1, 0x3, false }, // 1886
|
|
{ PseudoVNSRL_WV_M2_MASK, PseudoVNSRL_WV_M2, 0x3, false }, // 1887
|
|
{ PseudoVNSRL_WV_M4_MASK, PseudoVNSRL_WV_M4, 0x3, false }, // 1888
|
|
{ PseudoVNSRL_WV_MF2_MASK, PseudoVNSRL_WV_MF2, 0x3, false }, // 1889
|
|
{ PseudoVNSRL_WV_MF4_MASK, PseudoVNSRL_WV_MF4, 0x3, false }, // 1890
|
|
{ PseudoVNSRL_WV_MF8_MASK, PseudoVNSRL_WV_MF8, 0x3, false }, // 1891
|
|
{ PseudoVNSRL_WX_M1_MASK, PseudoVNSRL_WX_M1, 0x3, false }, // 1892
|
|
{ PseudoVNSRL_WX_M2_MASK, PseudoVNSRL_WX_M2, 0x3, false }, // 1893
|
|
{ PseudoVNSRL_WX_M4_MASK, PseudoVNSRL_WX_M4, 0x3, false }, // 1894
|
|
{ PseudoVNSRL_WX_MF2_MASK, PseudoVNSRL_WX_MF2, 0x3, false }, // 1895
|
|
{ PseudoVNSRL_WX_MF4_MASK, PseudoVNSRL_WX_MF4, 0x3, false }, // 1896
|
|
{ PseudoVNSRL_WX_MF8_MASK, PseudoVNSRL_WX_MF8, 0x3, false }, // 1897
|
|
{ PseudoVOR_VI_M1_MASK, PseudoVOR_VI_M1, 0x3, false }, // 1898
|
|
{ PseudoVOR_VI_M2_MASK, PseudoVOR_VI_M2, 0x3, false }, // 1899
|
|
{ PseudoVOR_VI_M4_MASK, PseudoVOR_VI_M4, 0x3, false }, // 1900
|
|
{ PseudoVOR_VI_M8_MASK, PseudoVOR_VI_M8, 0x3, false }, // 1901
|
|
{ PseudoVOR_VI_MF2_MASK, PseudoVOR_VI_MF2, 0x3, false }, // 1902
|
|
{ PseudoVOR_VI_MF4_MASK, PseudoVOR_VI_MF4, 0x3, false }, // 1903
|
|
{ PseudoVOR_VI_MF8_MASK, PseudoVOR_VI_MF8, 0x3, false }, // 1904
|
|
{ PseudoVOR_VV_M1_MASK, PseudoVOR_VV_M1, 0x3, false }, // 1905
|
|
{ PseudoVOR_VV_M2_MASK, PseudoVOR_VV_M2, 0x3, false }, // 1906
|
|
{ PseudoVOR_VV_M4_MASK, PseudoVOR_VV_M4, 0x3, false }, // 1907
|
|
{ PseudoVOR_VV_M8_MASK, PseudoVOR_VV_M8, 0x3, false }, // 1908
|
|
{ PseudoVOR_VV_MF2_MASK, PseudoVOR_VV_MF2, 0x3, false }, // 1909
|
|
{ PseudoVOR_VV_MF4_MASK, PseudoVOR_VV_MF4, 0x3, false }, // 1910
|
|
{ PseudoVOR_VV_MF8_MASK, PseudoVOR_VV_MF8, 0x3, false }, // 1911
|
|
{ PseudoVOR_VX_M1_MASK, PseudoVOR_VX_M1, 0x3, false }, // 1912
|
|
{ PseudoVOR_VX_M2_MASK, PseudoVOR_VX_M2, 0x3, false }, // 1913
|
|
{ PseudoVOR_VX_M4_MASK, PseudoVOR_VX_M4, 0x3, false }, // 1914
|
|
{ PseudoVOR_VX_M8_MASK, PseudoVOR_VX_M8, 0x3, false }, // 1915
|
|
{ PseudoVOR_VX_MF2_MASK, PseudoVOR_VX_MF2, 0x3, false }, // 1916
|
|
{ PseudoVOR_VX_MF4_MASK, PseudoVOR_VX_MF4, 0x3, false }, // 1917
|
|
{ PseudoVOR_VX_MF8_MASK, PseudoVOR_VX_MF8, 0x3, false }, // 1918
|
|
{ PseudoVREDAND_VS_M1_E16_MASK, PseudoVREDAND_VS_M1_E16, 0x3, true }, // 1919
|
|
{ PseudoVREDAND_VS_M1_E32_MASK, PseudoVREDAND_VS_M1_E32, 0x3, true }, // 1920
|
|
{ PseudoVREDAND_VS_M1_E64_MASK, PseudoVREDAND_VS_M1_E64, 0x3, true }, // 1921
|
|
{ PseudoVREDAND_VS_M1_E8_MASK, PseudoVREDAND_VS_M1_E8, 0x3, true }, // 1922
|
|
{ PseudoVREDAND_VS_M2_E16_MASK, PseudoVREDAND_VS_M2_E16, 0x3, true }, // 1923
|
|
{ PseudoVREDAND_VS_M2_E32_MASK, PseudoVREDAND_VS_M2_E32, 0x3, true }, // 1924
|
|
{ PseudoVREDAND_VS_M2_E64_MASK, PseudoVREDAND_VS_M2_E64, 0x3, true }, // 1925
|
|
{ PseudoVREDAND_VS_M2_E8_MASK, PseudoVREDAND_VS_M2_E8, 0x3, true }, // 1926
|
|
{ PseudoVREDAND_VS_M4_E16_MASK, PseudoVREDAND_VS_M4_E16, 0x3, true }, // 1927
|
|
{ PseudoVREDAND_VS_M4_E32_MASK, PseudoVREDAND_VS_M4_E32, 0x3, true }, // 1928
|
|
{ PseudoVREDAND_VS_M4_E64_MASK, PseudoVREDAND_VS_M4_E64, 0x3, true }, // 1929
|
|
{ PseudoVREDAND_VS_M4_E8_MASK, PseudoVREDAND_VS_M4_E8, 0x3, true }, // 1930
|
|
{ PseudoVREDAND_VS_M8_E16_MASK, PseudoVREDAND_VS_M8_E16, 0x3, true }, // 1931
|
|
{ PseudoVREDAND_VS_M8_E32_MASK, PseudoVREDAND_VS_M8_E32, 0x3, true }, // 1932
|
|
{ PseudoVREDAND_VS_M8_E64_MASK, PseudoVREDAND_VS_M8_E64, 0x3, true }, // 1933
|
|
{ PseudoVREDAND_VS_M8_E8_MASK, PseudoVREDAND_VS_M8_E8, 0x3, true }, // 1934
|
|
{ PseudoVREDAND_VS_MF2_E16_MASK, PseudoVREDAND_VS_MF2_E16, 0x3, true }, // 1935
|
|
{ PseudoVREDAND_VS_MF2_E32_MASK, PseudoVREDAND_VS_MF2_E32, 0x3, true }, // 1936
|
|
{ PseudoVREDAND_VS_MF2_E8_MASK, PseudoVREDAND_VS_MF2_E8, 0x3, true }, // 1937
|
|
{ PseudoVREDAND_VS_MF4_E16_MASK, PseudoVREDAND_VS_MF4_E16, 0x3, true }, // 1938
|
|
{ PseudoVREDAND_VS_MF4_E8_MASK, PseudoVREDAND_VS_MF4_E8, 0x3, true }, // 1939
|
|
{ PseudoVREDAND_VS_MF8_E8_MASK, PseudoVREDAND_VS_MF8_E8, 0x3, true }, // 1940
|
|
{ PseudoVREDMAXU_VS_M1_E16_MASK, PseudoVREDMAXU_VS_M1_E16, 0x3, true }, // 1941
|
|
{ PseudoVREDMAXU_VS_M1_E32_MASK, PseudoVREDMAXU_VS_M1_E32, 0x3, true }, // 1942
|
|
{ PseudoVREDMAXU_VS_M1_E64_MASK, PseudoVREDMAXU_VS_M1_E64, 0x3, true }, // 1943
|
|
{ PseudoVREDMAXU_VS_M1_E8_MASK, PseudoVREDMAXU_VS_M1_E8, 0x3, true }, // 1944
|
|
{ PseudoVREDMAXU_VS_M2_E16_MASK, PseudoVREDMAXU_VS_M2_E16, 0x3, true }, // 1945
|
|
{ PseudoVREDMAXU_VS_M2_E32_MASK, PseudoVREDMAXU_VS_M2_E32, 0x3, true }, // 1946
|
|
{ PseudoVREDMAXU_VS_M2_E64_MASK, PseudoVREDMAXU_VS_M2_E64, 0x3, true }, // 1947
|
|
{ PseudoVREDMAXU_VS_M2_E8_MASK, PseudoVREDMAXU_VS_M2_E8, 0x3, true }, // 1948
|
|
{ PseudoVREDMAXU_VS_M4_E16_MASK, PseudoVREDMAXU_VS_M4_E16, 0x3, true }, // 1949
|
|
{ PseudoVREDMAXU_VS_M4_E32_MASK, PseudoVREDMAXU_VS_M4_E32, 0x3, true }, // 1950
|
|
{ PseudoVREDMAXU_VS_M4_E64_MASK, PseudoVREDMAXU_VS_M4_E64, 0x3, true }, // 1951
|
|
{ PseudoVREDMAXU_VS_M4_E8_MASK, PseudoVREDMAXU_VS_M4_E8, 0x3, true }, // 1952
|
|
{ PseudoVREDMAXU_VS_M8_E16_MASK, PseudoVREDMAXU_VS_M8_E16, 0x3, true }, // 1953
|
|
{ PseudoVREDMAXU_VS_M8_E32_MASK, PseudoVREDMAXU_VS_M8_E32, 0x3, true }, // 1954
|
|
{ PseudoVREDMAXU_VS_M8_E64_MASK, PseudoVREDMAXU_VS_M8_E64, 0x3, true }, // 1955
|
|
{ PseudoVREDMAXU_VS_M8_E8_MASK, PseudoVREDMAXU_VS_M8_E8, 0x3, true }, // 1956
|
|
{ PseudoVREDMAXU_VS_MF2_E16_MASK, PseudoVREDMAXU_VS_MF2_E16, 0x3, true }, // 1957
|
|
{ PseudoVREDMAXU_VS_MF2_E32_MASK, PseudoVREDMAXU_VS_MF2_E32, 0x3, true }, // 1958
|
|
{ PseudoVREDMAXU_VS_MF2_E8_MASK, PseudoVREDMAXU_VS_MF2_E8, 0x3, true }, // 1959
|
|
{ PseudoVREDMAXU_VS_MF4_E16_MASK, PseudoVREDMAXU_VS_MF4_E16, 0x3, true }, // 1960
|
|
{ PseudoVREDMAXU_VS_MF4_E8_MASK, PseudoVREDMAXU_VS_MF4_E8, 0x3, true }, // 1961
|
|
{ PseudoVREDMAXU_VS_MF8_E8_MASK, PseudoVREDMAXU_VS_MF8_E8, 0x3, true }, // 1962
|
|
{ PseudoVREDMAX_VS_M1_E16_MASK, PseudoVREDMAX_VS_M1_E16, 0x3, true }, // 1963
|
|
{ PseudoVREDMAX_VS_M1_E32_MASK, PseudoVREDMAX_VS_M1_E32, 0x3, true }, // 1964
|
|
{ PseudoVREDMAX_VS_M1_E64_MASK, PseudoVREDMAX_VS_M1_E64, 0x3, true }, // 1965
|
|
{ PseudoVREDMAX_VS_M1_E8_MASK, PseudoVREDMAX_VS_M1_E8, 0x3, true }, // 1966
|
|
{ PseudoVREDMAX_VS_M2_E16_MASK, PseudoVREDMAX_VS_M2_E16, 0x3, true }, // 1967
|
|
{ PseudoVREDMAX_VS_M2_E32_MASK, PseudoVREDMAX_VS_M2_E32, 0x3, true }, // 1968
|
|
{ PseudoVREDMAX_VS_M2_E64_MASK, PseudoVREDMAX_VS_M2_E64, 0x3, true }, // 1969
|
|
{ PseudoVREDMAX_VS_M2_E8_MASK, PseudoVREDMAX_VS_M2_E8, 0x3, true }, // 1970
|
|
{ PseudoVREDMAX_VS_M4_E16_MASK, PseudoVREDMAX_VS_M4_E16, 0x3, true }, // 1971
|
|
{ PseudoVREDMAX_VS_M4_E32_MASK, PseudoVREDMAX_VS_M4_E32, 0x3, true }, // 1972
|
|
{ PseudoVREDMAX_VS_M4_E64_MASK, PseudoVREDMAX_VS_M4_E64, 0x3, true }, // 1973
|
|
{ PseudoVREDMAX_VS_M4_E8_MASK, PseudoVREDMAX_VS_M4_E8, 0x3, true }, // 1974
|
|
{ PseudoVREDMAX_VS_M8_E16_MASK, PseudoVREDMAX_VS_M8_E16, 0x3, true }, // 1975
|
|
{ PseudoVREDMAX_VS_M8_E32_MASK, PseudoVREDMAX_VS_M8_E32, 0x3, true }, // 1976
|
|
{ PseudoVREDMAX_VS_M8_E64_MASK, PseudoVREDMAX_VS_M8_E64, 0x3, true }, // 1977
|
|
{ PseudoVREDMAX_VS_M8_E8_MASK, PseudoVREDMAX_VS_M8_E8, 0x3, true }, // 1978
|
|
{ PseudoVREDMAX_VS_MF2_E16_MASK, PseudoVREDMAX_VS_MF2_E16, 0x3, true }, // 1979
|
|
{ PseudoVREDMAX_VS_MF2_E32_MASK, PseudoVREDMAX_VS_MF2_E32, 0x3, true }, // 1980
|
|
{ PseudoVREDMAX_VS_MF2_E8_MASK, PseudoVREDMAX_VS_MF2_E8, 0x3, true }, // 1981
|
|
{ PseudoVREDMAX_VS_MF4_E16_MASK, PseudoVREDMAX_VS_MF4_E16, 0x3, true }, // 1982
|
|
{ PseudoVREDMAX_VS_MF4_E8_MASK, PseudoVREDMAX_VS_MF4_E8, 0x3, true }, // 1983
|
|
{ PseudoVREDMAX_VS_MF8_E8_MASK, PseudoVREDMAX_VS_MF8_E8, 0x3, true }, // 1984
|
|
{ PseudoVREDMINU_VS_M1_E16_MASK, PseudoVREDMINU_VS_M1_E16, 0x3, true }, // 1985
|
|
{ PseudoVREDMINU_VS_M1_E32_MASK, PseudoVREDMINU_VS_M1_E32, 0x3, true }, // 1986
|
|
{ PseudoVREDMINU_VS_M1_E64_MASK, PseudoVREDMINU_VS_M1_E64, 0x3, true }, // 1987
|
|
{ PseudoVREDMINU_VS_M1_E8_MASK, PseudoVREDMINU_VS_M1_E8, 0x3, true }, // 1988
|
|
{ PseudoVREDMINU_VS_M2_E16_MASK, PseudoVREDMINU_VS_M2_E16, 0x3, true }, // 1989
|
|
{ PseudoVREDMINU_VS_M2_E32_MASK, PseudoVREDMINU_VS_M2_E32, 0x3, true }, // 1990
|
|
{ PseudoVREDMINU_VS_M2_E64_MASK, PseudoVREDMINU_VS_M2_E64, 0x3, true }, // 1991
|
|
{ PseudoVREDMINU_VS_M2_E8_MASK, PseudoVREDMINU_VS_M2_E8, 0x3, true }, // 1992
|
|
{ PseudoVREDMINU_VS_M4_E16_MASK, PseudoVREDMINU_VS_M4_E16, 0x3, true }, // 1993
|
|
{ PseudoVREDMINU_VS_M4_E32_MASK, PseudoVREDMINU_VS_M4_E32, 0x3, true }, // 1994
|
|
{ PseudoVREDMINU_VS_M4_E64_MASK, PseudoVREDMINU_VS_M4_E64, 0x3, true }, // 1995
|
|
{ PseudoVREDMINU_VS_M4_E8_MASK, PseudoVREDMINU_VS_M4_E8, 0x3, true }, // 1996
|
|
{ PseudoVREDMINU_VS_M8_E16_MASK, PseudoVREDMINU_VS_M8_E16, 0x3, true }, // 1997
|
|
{ PseudoVREDMINU_VS_M8_E32_MASK, PseudoVREDMINU_VS_M8_E32, 0x3, true }, // 1998
|
|
{ PseudoVREDMINU_VS_M8_E64_MASK, PseudoVREDMINU_VS_M8_E64, 0x3, true }, // 1999
|
|
{ PseudoVREDMINU_VS_M8_E8_MASK, PseudoVREDMINU_VS_M8_E8, 0x3, true }, // 2000
|
|
{ PseudoVREDMINU_VS_MF2_E16_MASK, PseudoVREDMINU_VS_MF2_E16, 0x3, true }, // 2001
|
|
{ PseudoVREDMINU_VS_MF2_E32_MASK, PseudoVREDMINU_VS_MF2_E32, 0x3, true }, // 2002
|
|
{ PseudoVREDMINU_VS_MF2_E8_MASK, PseudoVREDMINU_VS_MF2_E8, 0x3, true }, // 2003
|
|
{ PseudoVREDMINU_VS_MF4_E16_MASK, PseudoVREDMINU_VS_MF4_E16, 0x3, true }, // 2004
|
|
{ PseudoVREDMINU_VS_MF4_E8_MASK, PseudoVREDMINU_VS_MF4_E8, 0x3, true }, // 2005
|
|
{ PseudoVREDMINU_VS_MF8_E8_MASK, PseudoVREDMINU_VS_MF8_E8, 0x3, true }, // 2006
|
|
{ PseudoVREDMIN_VS_M1_E16_MASK, PseudoVREDMIN_VS_M1_E16, 0x3, true }, // 2007
|
|
{ PseudoVREDMIN_VS_M1_E32_MASK, PseudoVREDMIN_VS_M1_E32, 0x3, true }, // 2008
|
|
{ PseudoVREDMIN_VS_M1_E64_MASK, PseudoVREDMIN_VS_M1_E64, 0x3, true }, // 2009
|
|
{ PseudoVREDMIN_VS_M1_E8_MASK, PseudoVREDMIN_VS_M1_E8, 0x3, true }, // 2010
|
|
{ PseudoVREDMIN_VS_M2_E16_MASK, PseudoVREDMIN_VS_M2_E16, 0x3, true }, // 2011
|
|
{ PseudoVREDMIN_VS_M2_E32_MASK, PseudoVREDMIN_VS_M2_E32, 0x3, true }, // 2012
|
|
{ PseudoVREDMIN_VS_M2_E64_MASK, PseudoVREDMIN_VS_M2_E64, 0x3, true }, // 2013
|
|
{ PseudoVREDMIN_VS_M2_E8_MASK, PseudoVREDMIN_VS_M2_E8, 0x3, true }, // 2014
|
|
{ PseudoVREDMIN_VS_M4_E16_MASK, PseudoVREDMIN_VS_M4_E16, 0x3, true }, // 2015
|
|
{ PseudoVREDMIN_VS_M4_E32_MASK, PseudoVREDMIN_VS_M4_E32, 0x3, true }, // 2016
|
|
{ PseudoVREDMIN_VS_M4_E64_MASK, PseudoVREDMIN_VS_M4_E64, 0x3, true }, // 2017
|
|
{ PseudoVREDMIN_VS_M4_E8_MASK, PseudoVREDMIN_VS_M4_E8, 0x3, true }, // 2018
|
|
{ PseudoVREDMIN_VS_M8_E16_MASK, PseudoVREDMIN_VS_M8_E16, 0x3, true }, // 2019
|
|
{ PseudoVREDMIN_VS_M8_E32_MASK, PseudoVREDMIN_VS_M8_E32, 0x3, true }, // 2020
|
|
{ PseudoVREDMIN_VS_M8_E64_MASK, PseudoVREDMIN_VS_M8_E64, 0x3, true }, // 2021
|
|
{ PseudoVREDMIN_VS_M8_E8_MASK, PseudoVREDMIN_VS_M8_E8, 0x3, true }, // 2022
|
|
{ PseudoVREDMIN_VS_MF2_E16_MASK, PseudoVREDMIN_VS_MF2_E16, 0x3, true }, // 2023
|
|
{ PseudoVREDMIN_VS_MF2_E32_MASK, PseudoVREDMIN_VS_MF2_E32, 0x3, true }, // 2024
|
|
{ PseudoVREDMIN_VS_MF2_E8_MASK, PseudoVREDMIN_VS_MF2_E8, 0x3, true }, // 2025
|
|
{ PseudoVREDMIN_VS_MF4_E16_MASK, PseudoVREDMIN_VS_MF4_E16, 0x3, true }, // 2026
|
|
{ PseudoVREDMIN_VS_MF4_E8_MASK, PseudoVREDMIN_VS_MF4_E8, 0x3, true }, // 2027
|
|
{ PseudoVREDMIN_VS_MF8_E8_MASK, PseudoVREDMIN_VS_MF8_E8, 0x3, true }, // 2028
|
|
{ PseudoVREDOR_VS_M1_E16_MASK, PseudoVREDOR_VS_M1_E16, 0x3, true }, // 2029
|
|
{ PseudoVREDOR_VS_M1_E32_MASK, PseudoVREDOR_VS_M1_E32, 0x3, true }, // 2030
|
|
{ PseudoVREDOR_VS_M1_E64_MASK, PseudoVREDOR_VS_M1_E64, 0x3, true }, // 2031
|
|
{ PseudoVREDOR_VS_M1_E8_MASK, PseudoVREDOR_VS_M1_E8, 0x3, true }, // 2032
|
|
{ PseudoVREDOR_VS_M2_E16_MASK, PseudoVREDOR_VS_M2_E16, 0x3, true }, // 2033
|
|
{ PseudoVREDOR_VS_M2_E32_MASK, PseudoVREDOR_VS_M2_E32, 0x3, true }, // 2034
|
|
{ PseudoVREDOR_VS_M2_E64_MASK, PseudoVREDOR_VS_M2_E64, 0x3, true }, // 2035
|
|
{ PseudoVREDOR_VS_M2_E8_MASK, PseudoVREDOR_VS_M2_E8, 0x3, true }, // 2036
|
|
{ PseudoVREDOR_VS_M4_E16_MASK, PseudoVREDOR_VS_M4_E16, 0x3, true }, // 2037
|
|
{ PseudoVREDOR_VS_M4_E32_MASK, PseudoVREDOR_VS_M4_E32, 0x3, true }, // 2038
|
|
{ PseudoVREDOR_VS_M4_E64_MASK, PseudoVREDOR_VS_M4_E64, 0x3, true }, // 2039
|
|
{ PseudoVREDOR_VS_M4_E8_MASK, PseudoVREDOR_VS_M4_E8, 0x3, true }, // 2040
|
|
{ PseudoVREDOR_VS_M8_E16_MASK, PseudoVREDOR_VS_M8_E16, 0x3, true }, // 2041
|
|
{ PseudoVREDOR_VS_M8_E32_MASK, PseudoVREDOR_VS_M8_E32, 0x3, true }, // 2042
|
|
{ PseudoVREDOR_VS_M8_E64_MASK, PseudoVREDOR_VS_M8_E64, 0x3, true }, // 2043
|
|
{ PseudoVREDOR_VS_M8_E8_MASK, PseudoVREDOR_VS_M8_E8, 0x3, true }, // 2044
|
|
{ PseudoVREDOR_VS_MF2_E16_MASK, PseudoVREDOR_VS_MF2_E16, 0x3, true }, // 2045
|
|
{ PseudoVREDOR_VS_MF2_E32_MASK, PseudoVREDOR_VS_MF2_E32, 0x3, true }, // 2046
|
|
{ PseudoVREDOR_VS_MF2_E8_MASK, PseudoVREDOR_VS_MF2_E8, 0x3, true }, // 2047
|
|
{ PseudoVREDOR_VS_MF4_E16_MASK, PseudoVREDOR_VS_MF4_E16, 0x3, true }, // 2048
|
|
{ PseudoVREDOR_VS_MF4_E8_MASK, PseudoVREDOR_VS_MF4_E8, 0x3, true }, // 2049
|
|
{ PseudoVREDOR_VS_MF8_E8_MASK, PseudoVREDOR_VS_MF8_E8, 0x3, true }, // 2050
|
|
{ PseudoVREDSUM_VS_M1_E16_MASK, PseudoVREDSUM_VS_M1_E16, 0x3, true }, // 2051
|
|
{ PseudoVREDSUM_VS_M1_E32_MASK, PseudoVREDSUM_VS_M1_E32, 0x3, true }, // 2052
|
|
{ PseudoVREDSUM_VS_M1_E64_MASK, PseudoVREDSUM_VS_M1_E64, 0x3, true }, // 2053
|
|
{ PseudoVREDSUM_VS_M1_E8_MASK, PseudoVREDSUM_VS_M1_E8, 0x3, true }, // 2054
|
|
{ PseudoVREDSUM_VS_M2_E16_MASK, PseudoVREDSUM_VS_M2_E16, 0x3, true }, // 2055
|
|
{ PseudoVREDSUM_VS_M2_E32_MASK, PseudoVREDSUM_VS_M2_E32, 0x3, true }, // 2056
|
|
{ PseudoVREDSUM_VS_M2_E64_MASK, PseudoVREDSUM_VS_M2_E64, 0x3, true }, // 2057
|
|
{ PseudoVREDSUM_VS_M2_E8_MASK, PseudoVREDSUM_VS_M2_E8, 0x3, true }, // 2058
|
|
{ PseudoVREDSUM_VS_M4_E16_MASK, PseudoVREDSUM_VS_M4_E16, 0x3, true }, // 2059
|
|
{ PseudoVREDSUM_VS_M4_E32_MASK, PseudoVREDSUM_VS_M4_E32, 0x3, true }, // 2060
|
|
{ PseudoVREDSUM_VS_M4_E64_MASK, PseudoVREDSUM_VS_M4_E64, 0x3, true }, // 2061
|
|
{ PseudoVREDSUM_VS_M4_E8_MASK, PseudoVREDSUM_VS_M4_E8, 0x3, true }, // 2062
|
|
{ PseudoVREDSUM_VS_M8_E16_MASK, PseudoVREDSUM_VS_M8_E16, 0x3, true }, // 2063
|
|
{ PseudoVREDSUM_VS_M8_E32_MASK, PseudoVREDSUM_VS_M8_E32, 0x3, true }, // 2064
|
|
{ PseudoVREDSUM_VS_M8_E64_MASK, PseudoVREDSUM_VS_M8_E64, 0x3, true }, // 2065
|
|
{ PseudoVREDSUM_VS_M8_E8_MASK, PseudoVREDSUM_VS_M8_E8, 0x3, true }, // 2066
|
|
{ PseudoVREDSUM_VS_MF2_E16_MASK, PseudoVREDSUM_VS_MF2_E16, 0x3, true }, // 2067
|
|
{ PseudoVREDSUM_VS_MF2_E32_MASK, PseudoVREDSUM_VS_MF2_E32, 0x3, true }, // 2068
|
|
{ PseudoVREDSUM_VS_MF2_E8_MASK, PseudoVREDSUM_VS_MF2_E8, 0x3, true }, // 2069
|
|
{ PseudoVREDSUM_VS_MF4_E16_MASK, PseudoVREDSUM_VS_MF4_E16, 0x3, true }, // 2070
|
|
{ PseudoVREDSUM_VS_MF4_E8_MASK, PseudoVREDSUM_VS_MF4_E8, 0x3, true }, // 2071
|
|
{ PseudoVREDSUM_VS_MF8_E8_MASK, PseudoVREDSUM_VS_MF8_E8, 0x3, true }, // 2072
|
|
{ PseudoVREDXOR_VS_M1_E16_MASK, PseudoVREDXOR_VS_M1_E16, 0x3, true }, // 2073
|
|
{ PseudoVREDXOR_VS_M1_E32_MASK, PseudoVREDXOR_VS_M1_E32, 0x3, true }, // 2074
|
|
{ PseudoVREDXOR_VS_M1_E64_MASK, PseudoVREDXOR_VS_M1_E64, 0x3, true }, // 2075
|
|
{ PseudoVREDXOR_VS_M1_E8_MASK, PseudoVREDXOR_VS_M1_E8, 0x3, true }, // 2076
|
|
{ PseudoVREDXOR_VS_M2_E16_MASK, PseudoVREDXOR_VS_M2_E16, 0x3, true }, // 2077
|
|
{ PseudoVREDXOR_VS_M2_E32_MASK, PseudoVREDXOR_VS_M2_E32, 0x3, true }, // 2078
|
|
{ PseudoVREDXOR_VS_M2_E64_MASK, PseudoVREDXOR_VS_M2_E64, 0x3, true }, // 2079
|
|
{ PseudoVREDXOR_VS_M2_E8_MASK, PseudoVREDXOR_VS_M2_E8, 0x3, true }, // 2080
|
|
{ PseudoVREDXOR_VS_M4_E16_MASK, PseudoVREDXOR_VS_M4_E16, 0x3, true }, // 2081
|
|
{ PseudoVREDXOR_VS_M4_E32_MASK, PseudoVREDXOR_VS_M4_E32, 0x3, true }, // 2082
|
|
{ PseudoVREDXOR_VS_M4_E64_MASK, PseudoVREDXOR_VS_M4_E64, 0x3, true }, // 2083
|
|
{ PseudoVREDXOR_VS_M4_E8_MASK, PseudoVREDXOR_VS_M4_E8, 0x3, true }, // 2084
|
|
{ PseudoVREDXOR_VS_M8_E16_MASK, PseudoVREDXOR_VS_M8_E16, 0x3, true }, // 2085
|
|
{ PseudoVREDXOR_VS_M8_E32_MASK, PseudoVREDXOR_VS_M8_E32, 0x3, true }, // 2086
|
|
{ PseudoVREDXOR_VS_M8_E64_MASK, PseudoVREDXOR_VS_M8_E64, 0x3, true }, // 2087
|
|
{ PseudoVREDXOR_VS_M8_E8_MASK, PseudoVREDXOR_VS_M8_E8, 0x3, true }, // 2088
|
|
{ PseudoVREDXOR_VS_MF2_E16_MASK, PseudoVREDXOR_VS_MF2_E16, 0x3, true }, // 2089
|
|
{ PseudoVREDXOR_VS_MF2_E32_MASK, PseudoVREDXOR_VS_MF2_E32, 0x3, true }, // 2090
|
|
{ PseudoVREDXOR_VS_MF2_E8_MASK, PseudoVREDXOR_VS_MF2_E8, 0x3, true }, // 2091
|
|
{ PseudoVREDXOR_VS_MF4_E16_MASK, PseudoVREDXOR_VS_MF4_E16, 0x3, true }, // 2092
|
|
{ PseudoVREDXOR_VS_MF4_E8_MASK, PseudoVREDXOR_VS_MF4_E8, 0x3, true }, // 2093
|
|
{ PseudoVREDXOR_VS_MF8_E8_MASK, PseudoVREDXOR_VS_MF8_E8, 0x3, true }, // 2094
|
|
{ PseudoVREMU_VV_M1_E16_MASK, PseudoVREMU_VV_M1_E16, 0x3, false }, // 2095
|
|
{ PseudoVREMU_VV_M1_E32_MASK, PseudoVREMU_VV_M1_E32, 0x3, false }, // 2096
|
|
{ PseudoVREMU_VV_M1_E64_MASK, PseudoVREMU_VV_M1_E64, 0x3, false }, // 2097
|
|
{ PseudoVREMU_VV_M1_E8_MASK, PseudoVREMU_VV_M1_E8, 0x3, false }, // 2098
|
|
{ PseudoVREMU_VV_M2_E16_MASK, PseudoVREMU_VV_M2_E16, 0x3, false }, // 2099
|
|
{ PseudoVREMU_VV_M2_E32_MASK, PseudoVREMU_VV_M2_E32, 0x3, false }, // 2100
|
|
{ PseudoVREMU_VV_M2_E64_MASK, PseudoVREMU_VV_M2_E64, 0x3, false }, // 2101
|
|
{ PseudoVREMU_VV_M2_E8_MASK, PseudoVREMU_VV_M2_E8, 0x3, false }, // 2102
|
|
{ PseudoVREMU_VV_M4_E16_MASK, PseudoVREMU_VV_M4_E16, 0x3, false }, // 2103
|
|
{ PseudoVREMU_VV_M4_E32_MASK, PseudoVREMU_VV_M4_E32, 0x3, false }, // 2104
|
|
{ PseudoVREMU_VV_M4_E64_MASK, PseudoVREMU_VV_M4_E64, 0x3, false }, // 2105
|
|
{ PseudoVREMU_VV_M4_E8_MASK, PseudoVREMU_VV_M4_E8, 0x3, false }, // 2106
|
|
{ PseudoVREMU_VV_M8_E16_MASK, PseudoVREMU_VV_M8_E16, 0x3, false }, // 2107
|
|
{ PseudoVREMU_VV_M8_E32_MASK, PseudoVREMU_VV_M8_E32, 0x3, false }, // 2108
|
|
{ PseudoVREMU_VV_M8_E64_MASK, PseudoVREMU_VV_M8_E64, 0x3, false }, // 2109
|
|
{ PseudoVREMU_VV_M8_E8_MASK, PseudoVREMU_VV_M8_E8, 0x3, false }, // 2110
|
|
{ PseudoVREMU_VV_MF2_E16_MASK, PseudoVREMU_VV_MF2_E16, 0x3, false }, // 2111
|
|
{ PseudoVREMU_VV_MF2_E32_MASK, PseudoVREMU_VV_MF2_E32, 0x3, false }, // 2112
|
|
{ PseudoVREMU_VV_MF2_E8_MASK, PseudoVREMU_VV_MF2_E8, 0x3, false }, // 2113
|
|
{ PseudoVREMU_VV_MF4_E16_MASK, PseudoVREMU_VV_MF4_E16, 0x3, false }, // 2114
|
|
{ PseudoVREMU_VV_MF4_E8_MASK, PseudoVREMU_VV_MF4_E8, 0x3, false }, // 2115
|
|
{ PseudoVREMU_VV_MF8_E8_MASK, PseudoVREMU_VV_MF8_E8, 0x3, false }, // 2116
|
|
{ PseudoVREMU_VX_M1_E16_MASK, PseudoVREMU_VX_M1_E16, 0x3, false }, // 2117
|
|
{ PseudoVREMU_VX_M1_E32_MASK, PseudoVREMU_VX_M1_E32, 0x3, false }, // 2118
|
|
{ PseudoVREMU_VX_M1_E64_MASK, PseudoVREMU_VX_M1_E64, 0x3, false }, // 2119
|
|
{ PseudoVREMU_VX_M1_E8_MASK, PseudoVREMU_VX_M1_E8, 0x3, false }, // 2120
|
|
{ PseudoVREMU_VX_M2_E16_MASK, PseudoVREMU_VX_M2_E16, 0x3, false }, // 2121
|
|
{ PseudoVREMU_VX_M2_E32_MASK, PseudoVREMU_VX_M2_E32, 0x3, false }, // 2122
|
|
{ PseudoVREMU_VX_M2_E64_MASK, PseudoVREMU_VX_M2_E64, 0x3, false }, // 2123
|
|
{ PseudoVREMU_VX_M2_E8_MASK, PseudoVREMU_VX_M2_E8, 0x3, false }, // 2124
|
|
{ PseudoVREMU_VX_M4_E16_MASK, PseudoVREMU_VX_M4_E16, 0x3, false }, // 2125
|
|
{ PseudoVREMU_VX_M4_E32_MASK, PseudoVREMU_VX_M4_E32, 0x3, false }, // 2126
|
|
{ PseudoVREMU_VX_M4_E64_MASK, PseudoVREMU_VX_M4_E64, 0x3, false }, // 2127
|
|
{ PseudoVREMU_VX_M4_E8_MASK, PseudoVREMU_VX_M4_E8, 0x3, false }, // 2128
|
|
{ PseudoVREMU_VX_M8_E16_MASK, PseudoVREMU_VX_M8_E16, 0x3, false }, // 2129
|
|
{ PseudoVREMU_VX_M8_E32_MASK, PseudoVREMU_VX_M8_E32, 0x3, false }, // 2130
|
|
{ PseudoVREMU_VX_M8_E64_MASK, PseudoVREMU_VX_M8_E64, 0x3, false }, // 2131
|
|
{ PseudoVREMU_VX_M8_E8_MASK, PseudoVREMU_VX_M8_E8, 0x3, false }, // 2132
|
|
{ PseudoVREMU_VX_MF2_E16_MASK, PseudoVREMU_VX_MF2_E16, 0x3, false }, // 2133
|
|
{ PseudoVREMU_VX_MF2_E32_MASK, PseudoVREMU_VX_MF2_E32, 0x3, false }, // 2134
|
|
{ PseudoVREMU_VX_MF2_E8_MASK, PseudoVREMU_VX_MF2_E8, 0x3, false }, // 2135
|
|
{ PseudoVREMU_VX_MF4_E16_MASK, PseudoVREMU_VX_MF4_E16, 0x3, false }, // 2136
|
|
{ PseudoVREMU_VX_MF4_E8_MASK, PseudoVREMU_VX_MF4_E8, 0x3, false }, // 2137
|
|
{ PseudoVREMU_VX_MF8_E8_MASK, PseudoVREMU_VX_MF8_E8, 0x3, false }, // 2138
|
|
{ PseudoVREM_VV_M1_E16_MASK, PseudoVREM_VV_M1_E16, 0x3, false }, // 2139
|
|
{ PseudoVREM_VV_M1_E32_MASK, PseudoVREM_VV_M1_E32, 0x3, false }, // 2140
|
|
{ PseudoVREM_VV_M1_E64_MASK, PseudoVREM_VV_M1_E64, 0x3, false }, // 2141
|
|
{ PseudoVREM_VV_M1_E8_MASK, PseudoVREM_VV_M1_E8, 0x3, false }, // 2142
|
|
{ PseudoVREM_VV_M2_E16_MASK, PseudoVREM_VV_M2_E16, 0x3, false }, // 2143
|
|
{ PseudoVREM_VV_M2_E32_MASK, PseudoVREM_VV_M2_E32, 0x3, false }, // 2144
|
|
{ PseudoVREM_VV_M2_E64_MASK, PseudoVREM_VV_M2_E64, 0x3, false }, // 2145
|
|
{ PseudoVREM_VV_M2_E8_MASK, PseudoVREM_VV_M2_E8, 0x3, false }, // 2146
|
|
{ PseudoVREM_VV_M4_E16_MASK, PseudoVREM_VV_M4_E16, 0x3, false }, // 2147
|
|
{ PseudoVREM_VV_M4_E32_MASK, PseudoVREM_VV_M4_E32, 0x3, false }, // 2148
|
|
{ PseudoVREM_VV_M4_E64_MASK, PseudoVREM_VV_M4_E64, 0x3, false }, // 2149
|
|
{ PseudoVREM_VV_M4_E8_MASK, PseudoVREM_VV_M4_E8, 0x3, false }, // 2150
|
|
{ PseudoVREM_VV_M8_E16_MASK, PseudoVREM_VV_M8_E16, 0x3, false }, // 2151
|
|
{ PseudoVREM_VV_M8_E32_MASK, PseudoVREM_VV_M8_E32, 0x3, false }, // 2152
|
|
{ PseudoVREM_VV_M8_E64_MASK, PseudoVREM_VV_M8_E64, 0x3, false }, // 2153
|
|
{ PseudoVREM_VV_M8_E8_MASK, PseudoVREM_VV_M8_E8, 0x3, false }, // 2154
|
|
{ PseudoVREM_VV_MF2_E16_MASK, PseudoVREM_VV_MF2_E16, 0x3, false }, // 2155
|
|
{ PseudoVREM_VV_MF2_E32_MASK, PseudoVREM_VV_MF2_E32, 0x3, false }, // 2156
|
|
{ PseudoVREM_VV_MF2_E8_MASK, PseudoVREM_VV_MF2_E8, 0x3, false }, // 2157
|
|
{ PseudoVREM_VV_MF4_E16_MASK, PseudoVREM_VV_MF4_E16, 0x3, false }, // 2158
|
|
{ PseudoVREM_VV_MF4_E8_MASK, PseudoVREM_VV_MF4_E8, 0x3, false }, // 2159
|
|
{ PseudoVREM_VV_MF8_E8_MASK, PseudoVREM_VV_MF8_E8, 0x3, false }, // 2160
|
|
{ PseudoVREM_VX_M1_E16_MASK, PseudoVREM_VX_M1_E16, 0x3, false }, // 2161
|
|
{ PseudoVREM_VX_M1_E32_MASK, PseudoVREM_VX_M1_E32, 0x3, false }, // 2162
|
|
{ PseudoVREM_VX_M1_E64_MASK, PseudoVREM_VX_M1_E64, 0x3, false }, // 2163
|
|
{ PseudoVREM_VX_M1_E8_MASK, PseudoVREM_VX_M1_E8, 0x3, false }, // 2164
|
|
{ PseudoVREM_VX_M2_E16_MASK, PseudoVREM_VX_M2_E16, 0x3, false }, // 2165
|
|
{ PseudoVREM_VX_M2_E32_MASK, PseudoVREM_VX_M2_E32, 0x3, false }, // 2166
|
|
{ PseudoVREM_VX_M2_E64_MASK, PseudoVREM_VX_M2_E64, 0x3, false }, // 2167
|
|
{ PseudoVREM_VX_M2_E8_MASK, PseudoVREM_VX_M2_E8, 0x3, false }, // 2168
|
|
{ PseudoVREM_VX_M4_E16_MASK, PseudoVREM_VX_M4_E16, 0x3, false }, // 2169
|
|
{ PseudoVREM_VX_M4_E32_MASK, PseudoVREM_VX_M4_E32, 0x3, false }, // 2170
|
|
{ PseudoVREM_VX_M4_E64_MASK, PseudoVREM_VX_M4_E64, 0x3, false }, // 2171
|
|
{ PseudoVREM_VX_M4_E8_MASK, PseudoVREM_VX_M4_E8, 0x3, false }, // 2172
|
|
{ PseudoVREM_VX_M8_E16_MASK, PseudoVREM_VX_M8_E16, 0x3, false }, // 2173
|
|
{ PseudoVREM_VX_M8_E32_MASK, PseudoVREM_VX_M8_E32, 0x3, false }, // 2174
|
|
{ PseudoVREM_VX_M8_E64_MASK, PseudoVREM_VX_M8_E64, 0x3, false }, // 2175
|
|
{ PseudoVREM_VX_M8_E8_MASK, PseudoVREM_VX_M8_E8, 0x3, false }, // 2176
|
|
{ PseudoVREM_VX_MF2_E16_MASK, PseudoVREM_VX_MF2_E16, 0x3, false }, // 2177
|
|
{ PseudoVREM_VX_MF2_E32_MASK, PseudoVREM_VX_MF2_E32, 0x3, false }, // 2178
|
|
{ PseudoVREM_VX_MF2_E8_MASK, PseudoVREM_VX_MF2_E8, 0x3, false }, // 2179
|
|
{ PseudoVREM_VX_MF4_E16_MASK, PseudoVREM_VX_MF4_E16, 0x3, false }, // 2180
|
|
{ PseudoVREM_VX_MF4_E8_MASK, PseudoVREM_VX_MF4_E8, 0x3, false }, // 2181
|
|
{ PseudoVREM_VX_MF8_E8_MASK, PseudoVREM_VX_MF8_E8, 0x3, false }, // 2182
|
|
{ PseudoVREV8_V_M1_MASK, PseudoVREV8_V_M1, 0x2, false }, // 2183
|
|
{ PseudoVREV8_V_M2_MASK, PseudoVREV8_V_M2, 0x2, false }, // 2184
|
|
{ PseudoVREV8_V_M4_MASK, PseudoVREV8_V_M4, 0x2, false }, // 2185
|
|
{ PseudoVREV8_V_M8_MASK, PseudoVREV8_V_M8, 0x2, false }, // 2186
|
|
{ PseudoVREV8_V_MF2_MASK, PseudoVREV8_V_MF2, 0x2, false }, // 2187
|
|
{ PseudoVREV8_V_MF4_MASK, PseudoVREV8_V_MF4, 0x2, false }, // 2188
|
|
{ PseudoVREV8_V_MF8_MASK, PseudoVREV8_V_MF8, 0x2, false }, // 2189
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, PseudoVRGATHEREI16_VV_M1_E16_M1, 0x3, false }, // 2190
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, PseudoVRGATHEREI16_VV_M1_E16_M2, 0x3, false }, // 2191
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF2, 0x3, false }, // 2192
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF4, 0x3, false }, // 2193
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, PseudoVRGATHEREI16_VV_M1_E32_M1, 0x3, false }, // 2194
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, PseudoVRGATHEREI16_VV_M1_E32_M2, 0x3, false }, // 2195
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF2, 0x3, false }, // 2196
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF4, 0x3, false }, // 2197
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, PseudoVRGATHEREI16_VV_M1_E64_M1, 0x3, false }, // 2198
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, PseudoVRGATHEREI16_VV_M1_E64_M2, 0x3, false }, // 2199
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF2, 0x3, false }, // 2200
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF4, 0x3, false }, // 2201
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, PseudoVRGATHEREI16_VV_M1_E8_M1, 0x3, false }, // 2202
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, PseudoVRGATHEREI16_VV_M1_E8_M2, 0x3, false }, // 2203
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF2, 0x3, false }, // 2204
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF4, 0x3, false }, // 2205
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, PseudoVRGATHEREI16_VV_M2_E16_M1, 0x3, false }, // 2206
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, PseudoVRGATHEREI16_VV_M2_E16_M2, 0x3, false }, // 2207
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, PseudoVRGATHEREI16_VV_M2_E16_M4, 0x3, false }, // 2208
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E16_MF2, 0x3, false }, // 2209
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, PseudoVRGATHEREI16_VV_M2_E32_M1, 0x3, false }, // 2210
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, PseudoVRGATHEREI16_VV_M2_E32_M2, 0x3, false }, // 2211
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, PseudoVRGATHEREI16_VV_M2_E32_M4, 0x3, false }, // 2212
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E32_MF2, 0x3, false }, // 2213
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, PseudoVRGATHEREI16_VV_M2_E64_M1, 0x3, false }, // 2214
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, PseudoVRGATHEREI16_VV_M2_E64_M2, 0x3, false }, // 2215
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, PseudoVRGATHEREI16_VV_M2_E64_M4, 0x3, false }, // 2216
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E64_MF2, 0x3, false }, // 2217
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, PseudoVRGATHEREI16_VV_M2_E8_M1, 0x3, false }, // 2218
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, PseudoVRGATHEREI16_VV_M2_E8_M2, 0x3, false }, // 2219
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, PseudoVRGATHEREI16_VV_M2_E8_M4, 0x3, false }, // 2220
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E8_MF2, 0x3, false }, // 2221
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, PseudoVRGATHEREI16_VV_M4_E16_M1, 0x3, false }, // 2222
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, PseudoVRGATHEREI16_VV_M4_E16_M2, 0x3, false }, // 2223
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, PseudoVRGATHEREI16_VV_M4_E16_M4, 0x3, false }, // 2224
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, PseudoVRGATHEREI16_VV_M4_E16_M8, 0x3, false }, // 2225
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, PseudoVRGATHEREI16_VV_M4_E32_M1, 0x3, false }, // 2226
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, PseudoVRGATHEREI16_VV_M4_E32_M2, 0x3, false }, // 2227
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, PseudoVRGATHEREI16_VV_M4_E32_M4, 0x3, false }, // 2228
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, PseudoVRGATHEREI16_VV_M4_E32_M8, 0x3, false }, // 2229
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, PseudoVRGATHEREI16_VV_M4_E64_M1, 0x3, false }, // 2230
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, PseudoVRGATHEREI16_VV_M4_E64_M2, 0x3, false }, // 2231
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, PseudoVRGATHEREI16_VV_M4_E64_M4, 0x3, false }, // 2232
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, PseudoVRGATHEREI16_VV_M4_E64_M8, 0x3, false }, // 2233
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, PseudoVRGATHEREI16_VV_M4_E8_M1, 0x3, false }, // 2234
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, PseudoVRGATHEREI16_VV_M4_E8_M2, 0x3, false }, // 2235
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, PseudoVRGATHEREI16_VV_M4_E8_M4, 0x3, false }, // 2236
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, PseudoVRGATHEREI16_VV_M4_E8_M8, 0x3, false }, // 2237
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, PseudoVRGATHEREI16_VV_M8_E16_M2, 0x3, false }, // 2238
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, PseudoVRGATHEREI16_VV_M8_E16_M4, 0x3, false }, // 2239
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, PseudoVRGATHEREI16_VV_M8_E16_M8, 0x3, false }, // 2240
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, PseudoVRGATHEREI16_VV_M8_E32_M2, 0x3, false }, // 2241
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, PseudoVRGATHEREI16_VV_M8_E32_M4, 0x3, false }, // 2242
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, PseudoVRGATHEREI16_VV_M8_E32_M8, 0x3, false }, // 2243
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, PseudoVRGATHEREI16_VV_M8_E64_M2, 0x3, false }, // 2244
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, PseudoVRGATHEREI16_VV_M8_E64_M4, 0x3, false }, // 2245
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, PseudoVRGATHEREI16_VV_M8_E64_M8, 0x3, false }, // 2246
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, PseudoVRGATHEREI16_VV_M8_E8_M2, 0x3, false }, // 2247
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, PseudoVRGATHEREI16_VV_M8_E8_M4, 0x3, false }, // 2248
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, PseudoVRGATHEREI16_VV_M8_E8_M8, 0x3, false }, // 2249
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E16_M1, 0x3, false }, // 2250
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF2, 0x3, false }, // 2251
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF4, 0x3, false }, // 2252
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF8, 0x3, false }, // 2253
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E32_M1, 0x3, false }, // 2254
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF2, 0x3, false }, // 2255
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF4, 0x3, false }, // 2256
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF8, 0x3, false }, // 2257
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E8_M1, 0x3, false }, // 2258
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF2, 0x3, false }, // 2259
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF4, 0x3, false }, // 2260
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF8, 0x3, false }, // 2261
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF2, 0x3, false }, // 2262
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF4, 0x3, false }, // 2263
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF8, 0x3, false }, // 2264
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF2, 0x3, false }, // 2265
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF4, 0x3, false }, // 2266
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF8, 0x3, false }, // 2267
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF4, 0x3, false }, // 2268
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF8, 0x3, false }, // 2269
|
|
{ PseudoVRGATHER_VI_M1_MASK, PseudoVRGATHER_VI_M1, 0x3, false }, // 2270
|
|
{ PseudoVRGATHER_VI_M2_MASK, PseudoVRGATHER_VI_M2, 0x3, false }, // 2271
|
|
{ PseudoVRGATHER_VI_M4_MASK, PseudoVRGATHER_VI_M4, 0x3, false }, // 2272
|
|
{ PseudoVRGATHER_VI_M8_MASK, PseudoVRGATHER_VI_M8, 0x3, false }, // 2273
|
|
{ PseudoVRGATHER_VI_MF2_MASK, PseudoVRGATHER_VI_MF2, 0x3, false }, // 2274
|
|
{ PseudoVRGATHER_VI_MF4_MASK, PseudoVRGATHER_VI_MF4, 0x3, false }, // 2275
|
|
{ PseudoVRGATHER_VI_MF8_MASK, PseudoVRGATHER_VI_MF8, 0x3, false }, // 2276
|
|
{ PseudoVRGATHER_VV_M1_E16_MASK, PseudoVRGATHER_VV_M1_E16, 0x3, false }, // 2277
|
|
{ PseudoVRGATHER_VV_M1_E32_MASK, PseudoVRGATHER_VV_M1_E32, 0x3, false }, // 2278
|
|
{ PseudoVRGATHER_VV_M1_E64_MASK, PseudoVRGATHER_VV_M1_E64, 0x3, false }, // 2279
|
|
{ PseudoVRGATHER_VV_M1_E8_MASK, PseudoVRGATHER_VV_M1_E8, 0x3, false }, // 2280
|
|
{ PseudoVRGATHER_VV_M2_E16_MASK, PseudoVRGATHER_VV_M2_E16, 0x3, false }, // 2281
|
|
{ PseudoVRGATHER_VV_M2_E32_MASK, PseudoVRGATHER_VV_M2_E32, 0x3, false }, // 2282
|
|
{ PseudoVRGATHER_VV_M2_E64_MASK, PseudoVRGATHER_VV_M2_E64, 0x3, false }, // 2283
|
|
{ PseudoVRGATHER_VV_M2_E8_MASK, PseudoVRGATHER_VV_M2_E8, 0x3, false }, // 2284
|
|
{ PseudoVRGATHER_VV_M4_E16_MASK, PseudoVRGATHER_VV_M4_E16, 0x3, false }, // 2285
|
|
{ PseudoVRGATHER_VV_M4_E32_MASK, PseudoVRGATHER_VV_M4_E32, 0x3, false }, // 2286
|
|
{ PseudoVRGATHER_VV_M4_E64_MASK, PseudoVRGATHER_VV_M4_E64, 0x3, false }, // 2287
|
|
{ PseudoVRGATHER_VV_M4_E8_MASK, PseudoVRGATHER_VV_M4_E8, 0x3, false }, // 2288
|
|
{ PseudoVRGATHER_VV_M8_E16_MASK, PseudoVRGATHER_VV_M8_E16, 0x3, false }, // 2289
|
|
{ PseudoVRGATHER_VV_M8_E32_MASK, PseudoVRGATHER_VV_M8_E32, 0x3, false }, // 2290
|
|
{ PseudoVRGATHER_VV_M8_E64_MASK, PseudoVRGATHER_VV_M8_E64, 0x3, false }, // 2291
|
|
{ PseudoVRGATHER_VV_M8_E8_MASK, PseudoVRGATHER_VV_M8_E8, 0x3, false }, // 2292
|
|
{ PseudoVRGATHER_VV_MF2_E16_MASK, PseudoVRGATHER_VV_MF2_E16, 0x3, false }, // 2293
|
|
{ PseudoVRGATHER_VV_MF2_E32_MASK, PseudoVRGATHER_VV_MF2_E32, 0x3, false }, // 2294
|
|
{ PseudoVRGATHER_VV_MF2_E8_MASK, PseudoVRGATHER_VV_MF2_E8, 0x3, false }, // 2295
|
|
{ PseudoVRGATHER_VV_MF4_E16_MASK, PseudoVRGATHER_VV_MF4_E16, 0x3, false }, // 2296
|
|
{ PseudoVRGATHER_VV_MF4_E8_MASK, PseudoVRGATHER_VV_MF4_E8, 0x3, false }, // 2297
|
|
{ PseudoVRGATHER_VV_MF8_E8_MASK, PseudoVRGATHER_VV_MF8_E8, 0x3, false }, // 2298
|
|
{ PseudoVRGATHER_VX_M1_MASK, PseudoVRGATHER_VX_M1, 0x3, false }, // 2299
|
|
{ PseudoVRGATHER_VX_M2_MASK, PseudoVRGATHER_VX_M2, 0x3, false }, // 2300
|
|
{ PseudoVRGATHER_VX_M4_MASK, PseudoVRGATHER_VX_M4, 0x3, false }, // 2301
|
|
{ PseudoVRGATHER_VX_M8_MASK, PseudoVRGATHER_VX_M8, 0x3, false }, // 2302
|
|
{ PseudoVRGATHER_VX_MF2_MASK, PseudoVRGATHER_VX_MF2, 0x3, false }, // 2303
|
|
{ PseudoVRGATHER_VX_MF4_MASK, PseudoVRGATHER_VX_MF4, 0x3, false }, // 2304
|
|
{ PseudoVRGATHER_VX_MF8_MASK, PseudoVRGATHER_VX_MF8, 0x3, false }, // 2305
|
|
{ PseudoVROL_VV_M1_MASK, PseudoVROL_VV_M1, 0x3, false }, // 2306
|
|
{ PseudoVROL_VV_M2_MASK, PseudoVROL_VV_M2, 0x3, false }, // 2307
|
|
{ PseudoVROL_VV_M4_MASK, PseudoVROL_VV_M4, 0x3, false }, // 2308
|
|
{ PseudoVROL_VV_M8_MASK, PseudoVROL_VV_M8, 0x3, false }, // 2309
|
|
{ PseudoVROL_VV_MF2_MASK, PseudoVROL_VV_MF2, 0x3, false }, // 2310
|
|
{ PseudoVROL_VV_MF4_MASK, PseudoVROL_VV_MF4, 0x3, false }, // 2311
|
|
{ PseudoVROL_VV_MF8_MASK, PseudoVROL_VV_MF8, 0x3, false }, // 2312
|
|
{ PseudoVROL_VX_M1_MASK, PseudoVROL_VX_M1, 0x3, false }, // 2313
|
|
{ PseudoVROL_VX_M2_MASK, PseudoVROL_VX_M2, 0x3, false }, // 2314
|
|
{ PseudoVROL_VX_M4_MASK, PseudoVROL_VX_M4, 0x3, false }, // 2315
|
|
{ PseudoVROL_VX_M8_MASK, PseudoVROL_VX_M8, 0x3, false }, // 2316
|
|
{ PseudoVROL_VX_MF2_MASK, PseudoVROL_VX_MF2, 0x3, false }, // 2317
|
|
{ PseudoVROL_VX_MF4_MASK, PseudoVROL_VX_MF4, 0x3, false }, // 2318
|
|
{ PseudoVROL_VX_MF8_MASK, PseudoVROL_VX_MF8, 0x3, false }, // 2319
|
|
{ PseudoVROR_VI_M1_MASK, PseudoVROR_VI_M1, 0x3, false }, // 2320
|
|
{ PseudoVROR_VI_M2_MASK, PseudoVROR_VI_M2, 0x3, false }, // 2321
|
|
{ PseudoVROR_VI_M4_MASK, PseudoVROR_VI_M4, 0x3, false }, // 2322
|
|
{ PseudoVROR_VI_M8_MASK, PseudoVROR_VI_M8, 0x3, false }, // 2323
|
|
{ PseudoVROR_VI_MF2_MASK, PseudoVROR_VI_MF2, 0x3, false }, // 2324
|
|
{ PseudoVROR_VI_MF4_MASK, PseudoVROR_VI_MF4, 0x3, false }, // 2325
|
|
{ PseudoVROR_VI_MF8_MASK, PseudoVROR_VI_MF8, 0x3, false }, // 2326
|
|
{ PseudoVROR_VV_M1_MASK, PseudoVROR_VV_M1, 0x3, false }, // 2327
|
|
{ PseudoVROR_VV_M2_MASK, PseudoVROR_VV_M2, 0x3, false }, // 2328
|
|
{ PseudoVROR_VV_M4_MASK, PseudoVROR_VV_M4, 0x3, false }, // 2329
|
|
{ PseudoVROR_VV_M8_MASK, PseudoVROR_VV_M8, 0x3, false }, // 2330
|
|
{ PseudoVROR_VV_MF2_MASK, PseudoVROR_VV_MF2, 0x3, false }, // 2331
|
|
{ PseudoVROR_VV_MF4_MASK, PseudoVROR_VV_MF4, 0x3, false }, // 2332
|
|
{ PseudoVROR_VV_MF8_MASK, PseudoVROR_VV_MF8, 0x3, false }, // 2333
|
|
{ PseudoVROR_VX_M1_MASK, PseudoVROR_VX_M1, 0x3, false }, // 2334
|
|
{ PseudoVROR_VX_M2_MASK, PseudoVROR_VX_M2, 0x3, false }, // 2335
|
|
{ PseudoVROR_VX_M4_MASK, PseudoVROR_VX_M4, 0x3, false }, // 2336
|
|
{ PseudoVROR_VX_M8_MASK, PseudoVROR_VX_M8, 0x3, false }, // 2337
|
|
{ PseudoVROR_VX_MF2_MASK, PseudoVROR_VX_MF2, 0x3, false }, // 2338
|
|
{ PseudoVROR_VX_MF4_MASK, PseudoVROR_VX_MF4, 0x3, false }, // 2339
|
|
{ PseudoVROR_VX_MF8_MASK, PseudoVROR_VX_MF8, 0x3, false }, // 2340
|
|
{ PseudoVRSUB_VI_M1_MASK, PseudoVRSUB_VI_M1, 0x3, false }, // 2341
|
|
{ PseudoVRSUB_VI_M2_MASK, PseudoVRSUB_VI_M2, 0x3, false }, // 2342
|
|
{ PseudoVRSUB_VI_M4_MASK, PseudoVRSUB_VI_M4, 0x3, false }, // 2343
|
|
{ PseudoVRSUB_VI_M8_MASK, PseudoVRSUB_VI_M8, 0x3, false }, // 2344
|
|
{ PseudoVRSUB_VI_MF2_MASK, PseudoVRSUB_VI_MF2, 0x3, false }, // 2345
|
|
{ PseudoVRSUB_VI_MF4_MASK, PseudoVRSUB_VI_MF4, 0x3, false }, // 2346
|
|
{ PseudoVRSUB_VI_MF8_MASK, PseudoVRSUB_VI_MF8, 0x3, false }, // 2347
|
|
{ PseudoVRSUB_VX_M1_MASK, PseudoVRSUB_VX_M1, 0x3, false }, // 2348
|
|
{ PseudoVRSUB_VX_M2_MASK, PseudoVRSUB_VX_M2, 0x3, false }, // 2349
|
|
{ PseudoVRSUB_VX_M4_MASK, PseudoVRSUB_VX_M4, 0x3, false }, // 2350
|
|
{ PseudoVRSUB_VX_M8_MASK, PseudoVRSUB_VX_M8, 0x3, false }, // 2351
|
|
{ PseudoVRSUB_VX_MF2_MASK, PseudoVRSUB_VX_MF2, 0x3, false }, // 2352
|
|
{ PseudoVRSUB_VX_MF4_MASK, PseudoVRSUB_VX_MF4, 0x3, false }, // 2353
|
|
{ PseudoVRSUB_VX_MF8_MASK, PseudoVRSUB_VX_MF8, 0x3, false }, // 2354
|
|
{ PseudoVSADDU_VI_M1_MASK, PseudoVSADDU_VI_M1, 0x3, false }, // 2355
|
|
{ PseudoVSADDU_VI_M2_MASK, PseudoVSADDU_VI_M2, 0x3, false }, // 2356
|
|
{ PseudoVSADDU_VI_M4_MASK, PseudoVSADDU_VI_M4, 0x3, false }, // 2357
|
|
{ PseudoVSADDU_VI_M8_MASK, PseudoVSADDU_VI_M8, 0x3, false }, // 2358
|
|
{ PseudoVSADDU_VI_MF2_MASK, PseudoVSADDU_VI_MF2, 0x3, false }, // 2359
|
|
{ PseudoVSADDU_VI_MF4_MASK, PseudoVSADDU_VI_MF4, 0x3, false }, // 2360
|
|
{ PseudoVSADDU_VI_MF8_MASK, PseudoVSADDU_VI_MF8, 0x3, false }, // 2361
|
|
{ PseudoVSADDU_VV_M1_MASK, PseudoVSADDU_VV_M1, 0x3, false }, // 2362
|
|
{ PseudoVSADDU_VV_M2_MASK, PseudoVSADDU_VV_M2, 0x3, false }, // 2363
|
|
{ PseudoVSADDU_VV_M4_MASK, PseudoVSADDU_VV_M4, 0x3, false }, // 2364
|
|
{ PseudoVSADDU_VV_M8_MASK, PseudoVSADDU_VV_M8, 0x3, false }, // 2365
|
|
{ PseudoVSADDU_VV_MF2_MASK, PseudoVSADDU_VV_MF2, 0x3, false }, // 2366
|
|
{ PseudoVSADDU_VV_MF4_MASK, PseudoVSADDU_VV_MF4, 0x3, false }, // 2367
|
|
{ PseudoVSADDU_VV_MF8_MASK, PseudoVSADDU_VV_MF8, 0x3, false }, // 2368
|
|
{ PseudoVSADDU_VX_M1_MASK, PseudoVSADDU_VX_M1, 0x3, false }, // 2369
|
|
{ PseudoVSADDU_VX_M2_MASK, PseudoVSADDU_VX_M2, 0x3, false }, // 2370
|
|
{ PseudoVSADDU_VX_M4_MASK, PseudoVSADDU_VX_M4, 0x3, false }, // 2371
|
|
{ PseudoVSADDU_VX_M8_MASK, PseudoVSADDU_VX_M8, 0x3, false }, // 2372
|
|
{ PseudoVSADDU_VX_MF2_MASK, PseudoVSADDU_VX_MF2, 0x3, false }, // 2373
|
|
{ PseudoVSADDU_VX_MF4_MASK, PseudoVSADDU_VX_MF4, 0x3, false }, // 2374
|
|
{ PseudoVSADDU_VX_MF8_MASK, PseudoVSADDU_VX_MF8, 0x3, false }, // 2375
|
|
{ PseudoVSADD_VI_M1_MASK, PseudoVSADD_VI_M1, 0x3, false }, // 2376
|
|
{ PseudoVSADD_VI_M2_MASK, PseudoVSADD_VI_M2, 0x3, false }, // 2377
|
|
{ PseudoVSADD_VI_M4_MASK, PseudoVSADD_VI_M4, 0x3, false }, // 2378
|
|
{ PseudoVSADD_VI_M8_MASK, PseudoVSADD_VI_M8, 0x3, false }, // 2379
|
|
{ PseudoVSADD_VI_MF2_MASK, PseudoVSADD_VI_MF2, 0x3, false }, // 2380
|
|
{ PseudoVSADD_VI_MF4_MASK, PseudoVSADD_VI_MF4, 0x3, false }, // 2381
|
|
{ PseudoVSADD_VI_MF8_MASK, PseudoVSADD_VI_MF8, 0x3, false }, // 2382
|
|
{ PseudoVSADD_VV_M1_MASK, PseudoVSADD_VV_M1, 0x3, false }, // 2383
|
|
{ PseudoVSADD_VV_M2_MASK, PseudoVSADD_VV_M2, 0x3, false }, // 2384
|
|
{ PseudoVSADD_VV_M4_MASK, PseudoVSADD_VV_M4, 0x3, false }, // 2385
|
|
{ PseudoVSADD_VV_M8_MASK, PseudoVSADD_VV_M8, 0x3, false }, // 2386
|
|
{ PseudoVSADD_VV_MF2_MASK, PseudoVSADD_VV_MF2, 0x3, false }, // 2387
|
|
{ PseudoVSADD_VV_MF4_MASK, PseudoVSADD_VV_MF4, 0x3, false }, // 2388
|
|
{ PseudoVSADD_VV_MF8_MASK, PseudoVSADD_VV_MF8, 0x3, false }, // 2389
|
|
{ PseudoVSADD_VX_M1_MASK, PseudoVSADD_VX_M1, 0x3, false }, // 2390
|
|
{ PseudoVSADD_VX_M2_MASK, PseudoVSADD_VX_M2, 0x3, false }, // 2391
|
|
{ PseudoVSADD_VX_M4_MASK, PseudoVSADD_VX_M4, 0x3, false }, // 2392
|
|
{ PseudoVSADD_VX_M8_MASK, PseudoVSADD_VX_M8, 0x3, false }, // 2393
|
|
{ PseudoVSADD_VX_MF2_MASK, PseudoVSADD_VX_MF2, 0x3, false }, // 2394
|
|
{ PseudoVSADD_VX_MF4_MASK, PseudoVSADD_VX_MF4, 0x3, false }, // 2395
|
|
{ PseudoVSADD_VX_MF8_MASK, PseudoVSADD_VX_MF8, 0x3, false }, // 2396
|
|
{ PseudoVSEXT_VF2_M1_MASK, PseudoVSEXT_VF2_M1, 0x2, false }, // 2397
|
|
{ PseudoVSEXT_VF2_M2_MASK, PseudoVSEXT_VF2_M2, 0x2, false }, // 2398
|
|
{ PseudoVSEXT_VF2_M4_MASK, PseudoVSEXT_VF2_M4, 0x2, false }, // 2399
|
|
{ PseudoVSEXT_VF2_M8_MASK, PseudoVSEXT_VF2_M8, 0x2, false }, // 2400
|
|
{ PseudoVSEXT_VF2_MF2_MASK, PseudoVSEXT_VF2_MF2, 0x2, false }, // 2401
|
|
{ PseudoVSEXT_VF2_MF4_MASK, PseudoVSEXT_VF2_MF4, 0x2, false }, // 2402
|
|
{ PseudoVSEXT_VF4_M1_MASK, PseudoVSEXT_VF4_M1, 0x2, false }, // 2403
|
|
{ PseudoVSEXT_VF4_M2_MASK, PseudoVSEXT_VF4_M2, 0x2, false }, // 2404
|
|
{ PseudoVSEXT_VF4_M4_MASK, PseudoVSEXT_VF4_M4, 0x2, false }, // 2405
|
|
{ PseudoVSEXT_VF4_M8_MASK, PseudoVSEXT_VF4_M8, 0x2, false }, // 2406
|
|
{ PseudoVSEXT_VF4_MF2_MASK, PseudoVSEXT_VF4_MF2, 0x2, false }, // 2407
|
|
{ PseudoVSEXT_VF8_M1_MASK, PseudoVSEXT_VF8_M1, 0x2, false }, // 2408
|
|
{ PseudoVSEXT_VF8_M2_MASK, PseudoVSEXT_VF8_M2, 0x2, false }, // 2409
|
|
{ PseudoVSEXT_VF8_M4_MASK, PseudoVSEXT_VF8_M4, 0x2, false }, // 2410
|
|
{ PseudoVSEXT_VF8_M8_MASK, PseudoVSEXT_VF8_M8, 0x2, false }, // 2411
|
|
{ PseudoVSLIDE1DOWN_VX_M1_MASK, PseudoVSLIDE1DOWN_VX_M1, 0x3, false }, // 2412
|
|
{ PseudoVSLIDE1DOWN_VX_M2_MASK, PseudoVSLIDE1DOWN_VX_M2, 0x3, false }, // 2413
|
|
{ PseudoVSLIDE1DOWN_VX_M4_MASK, PseudoVSLIDE1DOWN_VX_M4, 0x3, false }, // 2414
|
|
{ PseudoVSLIDE1DOWN_VX_M8_MASK, PseudoVSLIDE1DOWN_VX_M8, 0x3, false }, // 2415
|
|
{ PseudoVSLIDE1DOWN_VX_MF2_MASK, PseudoVSLIDE1DOWN_VX_MF2, 0x3, false }, // 2416
|
|
{ PseudoVSLIDE1DOWN_VX_MF4_MASK, PseudoVSLIDE1DOWN_VX_MF4, 0x3, false }, // 2417
|
|
{ PseudoVSLIDE1DOWN_VX_MF8_MASK, PseudoVSLIDE1DOWN_VX_MF8, 0x3, false }, // 2418
|
|
{ PseudoVSLIDE1UP_VX_M1_MASK, PseudoVSLIDE1UP_VX_M1, 0x3, false }, // 2419
|
|
{ PseudoVSLIDE1UP_VX_M2_MASK, PseudoVSLIDE1UP_VX_M2, 0x3, false }, // 2420
|
|
{ PseudoVSLIDE1UP_VX_M4_MASK, PseudoVSLIDE1UP_VX_M4, 0x3, false }, // 2421
|
|
{ PseudoVSLIDE1UP_VX_M8_MASK, PseudoVSLIDE1UP_VX_M8, 0x3, false }, // 2422
|
|
{ PseudoVSLIDE1UP_VX_MF2_MASK, PseudoVSLIDE1UP_VX_MF2, 0x3, false }, // 2423
|
|
{ PseudoVSLIDE1UP_VX_MF4_MASK, PseudoVSLIDE1UP_VX_MF4, 0x3, false }, // 2424
|
|
{ PseudoVSLIDE1UP_VX_MF8_MASK, PseudoVSLIDE1UP_VX_MF8, 0x3, false }, // 2425
|
|
{ PseudoVSLIDEDOWN_VI_M1_MASK, PseudoVSLIDEDOWN_VI_M1, 0x3, false }, // 2426
|
|
{ PseudoVSLIDEDOWN_VI_M2_MASK, PseudoVSLIDEDOWN_VI_M2, 0x3, false }, // 2427
|
|
{ PseudoVSLIDEDOWN_VI_M4_MASK, PseudoVSLIDEDOWN_VI_M4, 0x3, false }, // 2428
|
|
{ PseudoVSLIDEDOWN_VI_M8_MASK, PseudoVSLIDEDOWN_VI_M8, 0x3, false }, // 2429
|
|
{ PseudoVSLIDEDOWN_VI_MF2_MASK, PseudoVSLIDEDOWN_VI_MF2, 0x3, false }, // 2430
|
|
{ PseudoVSLIDEDOWN_VI_MF4_MASK, PseudoVSLIDEDOWN_VI_MF4, 0x3, false }, // 2431
|
|
{ PseudoVSLIDEDOWN_VI_MF8_MASK, PseudoVSLIDEDOWN_VI_MF8, 0x3, false }, // 2432
|
|
{ PseudoVSLIDEDOWN_VX_M1_MASK, PseudoVSLIDEDOWN_VX_M1, 0x3, false }, // 2433
|
|
{ PseudoVSLIDEDOWN_VX_M2_MASK, PseudoVSLIDEDOWN_VX_M2, 0x3, false }, // 2434
|
|
{ PseudoVSLIDEDOWN_VX_M4_MASK, PseudoVSLIDEDOWN_VX_M4, 0x3, false }, // 2435
|
|
{ PseudoVSLIDEDOWN_VX_M8_MASK, PseudoVSLIDEDOWN_VX_M8, 0x3, false }, // 2436
|
|
{ PseudoVSLIDEDOWN_VX_MF2_MASK, PseudoVSLIDEDOWN_VX_MF2, 0x3, false }, // 2437
|
|
{ PseudoVSLIDEDOWN_VX_MF4_MASK, PseudoVSLIDEDOWN_VX_MF4, 0x3, false }, // 2438
|
|
{ PseudoVSLIDEDOWN_VX_MF8_MASK, PseudoVSLIDEDOWN_VX_MF8, 0x3, false }, // 2439
|
|
{ PseudoVSLIDEUP_VI_M1_MASK, PseudoVSLIDEUP_VI_M1, 0x3, false }, // 2440
|
|
{ PseudoVSLIDEUP_VI_M2_MASK, PseudoVSLIDEUP_VI_M2, 0x3, false }, // 2441
|
|
{ PseudoVSLIDEUP_VI_M4_MASK, PseudoVSLIDEUP_VI_M4, 0x3, false }, // 2442
|
|
{ PseudoVSLIDEUP_VI_M8_MASK, PseudoVSLIDEUP_VI_M8, 0x3, false }, // 2443
|
|
{ PseudoVSLIDEUP_VI_MF2_MASK, PseudoVSLIDEUP_VI_MF2, 0x3, false }, // 2444
|
|
{ PseudoVSLIDEUP_VI_MF4_MASK, PseudoVSLIDEUP_VI_MF4, 0x3, false }, // 2445
|
|
{ PseudoVSLIDEUP_VI_MF8_MASK, PseudoVSLIDEUP_VI_MF8, 0x3, false }, // 2446
|
|
{ PseudoVSLIDEUP_VX_M1_MASK, PseudoVSLIDEUP_VX_M1, 0x3, false }, // 2447
|
|
{ PseudoVSLIDEUP_VX_M2_MASK, PseudoVSLIDEUP_VX_M2, 0x3, false }, // 2448
|
|
{ PseudoVSLIDEUP_VX_M4_MASK, PseudoVSLIDEUP_VX_M4, 0x3, false }, // 2449
|
|
{ PseudoVSLIDEUP_VX_M8_MASK, PseudoVSLIDEUP_VX_M8, 0x3, false }, // 2450
|
|
{ PseudoVSLIDEUP_VX_MF2_MASK, PseudoVSLIDEUP_VX_MF2, 0x3, false }, // 2451
|
|
{ PseudoVSLIDEUP_VX_MF4_MASK, PseudoVSLIDEUP_VX_MF4, 0x3, false }, // 2452
|
|
{ PseudoVSLIDEUP_VX_MF8_MASK, PseudoVSLIDEUP_VX_MF8, 0x3, false }, // 2453
|
|
{ PseudoVSLL_VI_M1_MASK, PseudoVSLL_VI_M1, 0x3, false }, // 2454
|
|
{ PseudoVSLL_VI_M2_MASK, PseudoVSLL_VI_M2, 0x3, false }, // 2455
|
|
{ PseudoVSLL_VI_M4_MASK, PseudoVSLL_VI_M4, 0x3, false }, // 2456
|
|
{ PseudoVSLL_VI_M8_MASK, PseudoVSLL_VI_M8, 0x3, false }, // 2457
|
|
{ PseudoVSLL_VI_MF2_MASK, PseudoVSLL_VI_MF2, 0x3, false }, // 2458
|
|
{ PseudoVSLL_VI_MF4_MASK, PseudoVSLL_VI_MF4, 0x3, false }, // 2459
|
|
{ PseudoVSLL_VI_MF8_MASK, PseudoVSLL_VI_MF8, 0x3, false }, // 2460
|
|
{ PseudoVSLL_VV_M1_MASK, PseudoVSLL_VV_M1, 0x3, false }, // 2461
|
|
{ PseudoVSLL_VV_M2_MASK, PseudoVSLL_VV_M2, 0x3, false }, // 2462
|
|
{ PseudoVSLL_VV_M4_MASK, PseudoVSLL_VV_M4, 0x3, false }, // 2463
|
|
{ PseudoVSLL_VV_M8_MASK, PseudoVSLL_VV_M8, 0x3, false }, // 2464
|
|
{ PseudoVSLL_VV_MF2_MASK, PseudoVSLL_VV_MF2, 0x3, false }, // 2465
|
|
{ PseudoVSLL_VV_MF4_MASK, PseudoVSLL_VV_MF4, 0x3, false }, // 2466
|
|
{ PseudoVSLL_VV_MF8_MASK, PseudoVSLL_VV_MF8, 0x3, false }, // 2467
|
|
{ PseudoVSLL_VX_M1_MASK, PseudoVSLL_VX_M1, 0x3, false }, // 2468
|
|
{ PseudoVSLL_VX_M2_MASK, PseudoVSLL_VX_M2, 0x3, false }, // 2469
|
|
{ PseudoVSLL_VX_M4_MASK, PseudoVSLL_VX_M4, 0x3, false }, // 2470
|
|
{ PseudoVSLL_VX_M8_MASK, PseudoVSLL_VX_M8, 0x3, false }, // 2471
|
|
{ PseudoVSLL_VX_MF2_MASK, PseudoVSLL_VX_MF2, 0x3, false }, // 2472
|
|
{ PseudoVSLL_VX_MF4_MASK, PseudoVSLL_VX_MF4, 0x3, false }, // 2473
|
|
{ PseudoVSLL_VX_MF8_MASK, PseudoVSLL_VX_MF8, 0x3, false }, // 2474
|
|
{ PseudoVSMUL_VV_M1_MASK, PseudoVSMUL_VV_M1, 0x3, false }, // 2475
|
|
{ PseudoVSMUL_VV_M2_MASK, PseudoVSMUL_VV_M2, 0x3, false }, // 2476
|
|
{ PseudoVSMUL_VV_M4_MASK, PseudoVSMUL_VV_M4, 0x3, false }, // 2477
|
|
{ PseudoVSMUL_VV_M8_MASK, PseudoVSMUL_VV_M8, 0x3, false }, // 2478
|
|
{ PseudoVSMUL_VV_MF2_MASK, PseudoVSMUL_VV_MF2, 0x3, false }, // 2479
|
|
{ PseudoVSMUL_VV_MF4_MASK, PseudoVSMUL_VV_MF4, 0x3, false }, // 2480
|
|
{ PseudoVSMUL_VV_MF8_MASK, PseudoVSMUL_VV_MF8, 0x3, false }, // 2481
|
|
{ PseudoVSMUL_VX_M1_MASK, PseudoVSMUL_VX_M1, 0x3, false }, // 2482
|
|
{ PseudoVSMUL_VX_M2_MASK, PseudoVSMUL_VX_M2, 0x3, false }, // 2483
|
|
{ PseudoVSMUL_VX_M4_MASK, PseudoVSMUL_VX_M4, 0x3, false }, // 2484
|
|
{ PseudoVSMUL_VX_M8_MASK, PseudoVSMUL_VX_M8, 0x3, false }, // 2485
|
|
{ PseudoVSMUL_VX_MF2_MASK, PseudoVSMUL_VX_MF2, 0x3, false }, // 2486
|
|
{ PseudoVSMUL_VX_MF4_MASK, PseudoVSMUL_VX_MF4, 0x3, false }, // 2487
|
|
{ PseudoVSMUL_VX_MF8_MASK, PseudoVSMUL_VX_MF8, 0x3, false }, // 2488
|
|
{ PseudoVSRA_VI_M1_MASK, PseudoVSRA_VI_M1, 0x3, false }, // 2489
|
|
{ PseudoVSRA_VI_M2_MASK, PseudoVSRA_VI_M2, 0x3, false }, // 2490
|
|
{ PseudoVSRA_VI_M4_MASK, PseudoVSRA_VI_M4, 0x3, false }, // 2491
|
|
{ PseudoVSRA_VI_M8_MASK, PseudoVSRA_VI_M8, 0x3, false }, // 2492
|
|
{ PseudoVSRA_VI_MF2_MASK, PseudoVSRA_VI_MF2, 0x3, false }, // 2493
|
|
{ PseudoVSRA_VI_MF4_MASK, PseudoVSRA_VI_MF4, 0x3, false }, // 2494
|
|
{ PseudoVSRA_VI_MF8_MASK, PseudoVSRA_VI_MF8, 0x3, false }, // 2495
|
|
{ PseudoVSRA_VV_M1_MASK, PseudoVSRA_VV_M1, 0x3, false }, // 2496
|
|
{ PseudoVSRA_VV_M2_MASK, PseudoVSRA_VV_M2, 0x3, false }, // 2497
|
|
{ PseudoVSRA_VV_M4_MASK, PseudoVSRA_VV_M4, 0x3, false }, // 2498
|
|
{ PseudoVSRA_VV_M8_MASK, PseudoVSRA_VV_M8, 0x3, false }, // 2499
|
|
{ PseudoVSRA_VV_MF2_MASK, PseudoVSRA_VV_MF2, 0x3, false }, // 2500
|
|
{ PseudoVSRA_VV_MF4_MASK, PseudoVSRA_VV_MF4, 0x3, false }, // 2501
|
|
{ PseudoVSRA_VV_MF8_MASK, PseudoVSRA_VV_MF8, 0x3, false }, // 2502
|
|
{ PseudoVSRA_VX_M1_MASK, PseudoVSRA_VX_M1, 0x3, false }, // 2503
|
|
{ PseudoVSRA_VX_M2_MASK, PseudoVSRA_VX_M2, 0x3, false }, // 2504
|
|
{ PseudoVSRA_VX_M4_MASK, PseudoVSRA_VX_M4, 0x3, false }, // 2505
|
|
{ PseudoVSRA_VX_M8_MASK, PseudoVSRA_VX_M8, 0x3, false }, // 2506
|
|
{ PseudoVSRA_VX_MF2_MASK, PseudoVSRA_VX_MF2, 0x3, false }, // 2507
|
|
{ PseudoVSRA_VX_MF4_MASK, PseudoVSRA_VX_MF4, 0x3, false }, // 2508
|
|
{ PseudoVSRA_VX_MF8_MASK, PseudoVSRA_VX_MF8, 0x3, false }, // 2509
|
|
{ PseudoVSRL_VI_M1_MASK, PseudoVSRL_VI_M1, 0x3, false }, // 2510
|
|
{ PseudoVSRL_VI_M2_MASK, PseudoVSRL_VI_M2, 0x3, false }, // 2511
|
|
{ PseudoVSRL_VI_M4_MASK, PseudoVSRL_VI_M4, 0x3, false }, // 2512
|
|
{ PseudoVSRL_VI_M8_MASK, PseudoVSRL_VI_M8, 0x3, false }, // 2513
|
|
{ PseudoVSRL_VI_MF2_MASK, PseudoVSRL_VI_MF2, 0x3, false }, // 2514
|
|
{ PseudoVSRL_VI_MF4_MASK, PseudoVSRL_VI_MF4, 0x3, false }, // 2515
|
|
{ PseudoVSRL_VI_MF8_MASK, PseudoVSRL_VI_MF8, 0x3, false }, // 2516
|
|
{ PseudoVSRL_VV_M1_MASK, PseudoVSRL_VV_M1, 0x3, false }, // 2517
|
|
{ PseudoVSRL_VV_M2_MASK, PseudoVSRL_VV_M2, 0x3, false }, // 2518
|
|
{ PseudoVSRL_VV_M4_MASK, PseudoVSRL_VV_M4, 0x3, false }, // 2519
|
|
{ PseudoVSRL_VV_M8_MASK, PseudoVSRL_VV_M8, 0x3, false }, // 2520
|
|
{ PseudoVSRL_VV_MF2_MASK, PseudoVSRL_VV_MF2, 0x3, false }, // 2521
|
|
{ PseudoVSRL_VV_MF4_MASK, PseudoVSRL_VV_MF4, 0x3, false }, // 2522
|
|
{ PseudoVSRL_VV_MF8_MASK, PseudoVSRL_VV_MF8, 0x3, false }, // 2523
|
|
{ PseudoVSRL_VX_M1_MASK, PseudoVSRL_VX_M1, 0x3, false }, // 2524
|
|
{ PseudoVSRL_VX_M2_MASK, PseudoVSRL_VX_M2, 0x3, false }, // 2525
|
|
{ PseudoVSRL_VX_M4_MASK, PseudoVSRL_VX_M4, 0x3, false }, // 2526
|
|
{ PseudoVSRL_VX_M8_MASK, PseudoVSRL_VX_M8, 0x3, false }, // 2527
|
|
{ PseudoVSRL_VX_MF2_MASK, PseudoVSRL_VX_MF2, 0x3, false }, // 2528
|
|
{ PseudoVSRL_VX_MF4_MASK, PseudoVSRL_VX_MF4, 0x3, false }, // 2529
|
|
{ PseudoVSRL_VX_MF8_MASK, PseudoVSRL_VX_MF8, 0x3, false }, // 2530
|
|
{ PseudoVSSRA_VI_M1_MASK, PseudoVSSRA_VI_M1, 0x3, false }, // 2531
|
|
{ PseudoVSSRA_VI_M2_MASK, PseudoVSSRA_VI_M2, 0x3, false }, // 2532
|
|
{ PseudoVSSRA_VI_M4_MASK, PseudoVSSRA_VI_M4, 0x3, false }, // 2533
|
|
{ PseudoVSSRA_VI_M8_MASK, PseudoVSSRA_VI_M8, 0x3, false }, // 2534
|
|
{ PseudoVSSRA_VI_MF2_MASK, PseudoVSSRA_VI_MF2, 0x3, false }, // 2535
|
|
{ PseudoVSSRA_VI_MF4_MASK, PseudoVSSRA_VI_MF4, 0x3, false }, // 2536
|
|
{ PseudoVSSRA_VI_MF8_MASK, PseudoVSSRA_VI_MF8, 0x3, false }, // 2537
|
|
{ PseudoVSSRA_VV_M1_MASK, PseudoVSSRA_VV_M1, 0x3, false }, // 2538
|
|
{ PseudoVSSRA_VV_M2_MASK, PseudoVSSRA_VV_M2, 0x3, false }, // 2539
|
|
{ PseudoVSSRA_VV_M4_MASK, PseudoVSSRA_VV_M4, 0x3, false }, // 2540
|
|
{ PseudoVSSRA_VV_M8_MASK, PseudoVSSRA_VV_M8, 0x3, false }, // 2541
|
|
{ PseudoVSSRA_VV_MF2_MASK, PseudoVSSRA_VV_MF2, 0x3, false }, // 2542
|
|
{ PseudoVSSRA_VV_MF4_MASK, PseudoVSSRA_VV_MF4, 0x3, false }, // 2543
|
|
{ PseudoVSSRA_VV_MF8_MASK, PseudoVSSRA_VV_MF8, 0x3, false }, // 2544
|
|
{ PseudoVSSRA_VX_M1_MASK, PseudoVSSRA_VX_M1, 0x3, false }, // 2545
|
|
{ PseudoVSSRA_VX_M2_MASK, PseudoVSSRA_VX_M2, 0x3, false }, // 2546
|
|
{ PseudoVSSRA_VX_M4_MASK, PseudoVSSRA_VX_M4, 0x3, false }, // 2547
|
|
{ PseudoVSSRA_VX_M8_MASK, PseudoVSSRA_VX_M8, 0x3, false }, // 2548
|
|
{ PseudoVSSRA_VX_MF2_MASK, PseudoVSSRA_VX_MF2, 0x3, false }, // 2549
|
|
{ PseudoVSSRA_VX_MF4_MASK, PseudoVSSRA_VX_MF4, 0x3, false }, // 2550
|
|
{ PseudoVSSRA_VX_MF8_MASK, PseudoVSSRA_VX_MF8, 0x3, false }, // 2551
|
|
{ PseudoVSSRL_VI_M1_MASK, PseudoVSSRL_VI_M1, 0x3, false }, // 2552
|
|
{ PseudoVSSRL_VI_M2_MASK, PseudoVSSRL_VI_M2, 0x3, false }, // 2553
|
|
{ PseudoVSSRL_VI_M4_MASK, PseudoVSSRL_VI_M4, 0x3, false }, // 2554
|
|
{ PseudoVSSRL_VI_M8_MASK, PseudoVSSRL_VI_M8, 0x3, false }, // 2555
|
|
{ PseudoVSSRL_VI_MF2_MASK, PseudoVSSRL_VI_MF2, 0x3, false }, // 2556
|
|
{ PseudoVSSRL_VI_MF4_MASK, PseudoVSSRL_VI_MF4, 0x3, false }, // 2557
|
|
{ PseudoVSSRL_VI_MF8_MASK, PseudoVSSRL_VI_MF8, 0x3, false }, // 2558
|
|
{ PseudoVSSRL_VV_M1_MASK, PseudoVSSRL_VV_M1, 0x3, false }, // 2559
|
|
{ PseudoVSSRL_VV_M2_MASK, PseudoVSSRL_VV_M2, 0x3, false }, // 2560
|
|
{ PseudoVSSRL_VV_M4_MASK, PseudoVSSRL_VV_M4, 0x3, false }, // 2561
|
|
{ PseudoVSSRL_VV_M8_MASK, PseudoVSSRL_VV_M8, 0x3, false }, // 2562
|
|
{ PseudoVSSRL_VV_MF2_MASK, PseudoVSSRL_VV_MF2, 0x3, false }, // 2563
|
|
{ PseudoVSSRL_VV_MF4_MASK, PseudoVSSRL_VV_MF4, 0x3, false }, // 2564
|
|
{ PseudoVSSRL_VV_MF8_MASK, PseudoVSSRL_VV_MF8, 0x3, false }, // 2565
|
|
{ PseudoVSSRL_VX_M1_MASK, PseudoVSSRL_VX_M1, 0x3, false }, // 2566
|
|
{ PseudoVSSRL_VX_M2_MASK, PseudoVSSRL_VX_M2, 0x3, false }, // 2567
|
|
{ PseudoVSSRL_VX_M4_MASK, PseudoVSSRL_VX_M4, 0x3, false }, // 2568
|
|
{ PseudoVSSRL_VX_M8_MASK, PseudoVSSRL_VX_M8, 0x3, false }, // 2569
|
|
{ PseudoVSSRL_VX_MF2_MASK, PseudoVSSRL_VX_MF2, 0x3, false }, // 2570
|
|
{ PseudoVSSRL_VX_MF4_MASK, PseudoVSSRL_VX_MF4, 0x3, false }, // 2571
|
|
{ PseudoVSSRL_VX_MF8_MASK, PseudoVSSRL_VX_MF8, 0x3, false }, // 2572
|
|
{ PseudoVSSUBU_VV_M1_MASK, PseudoVSSUBU_VV_M1, 0x3, false }, // 2573
|
|
{ PseudoVSSUBU_VV_M2_MASK, PseudoVSSUBU_VV_M2, 0x3, false }, // 2574
|
|
{ PseudoVSSUBU_VV_M4_MASK, PseudoVSSUBU_VV_M4, 0x3, false }, // 2575
|
|
{ PseudoVSSUBU_VV_M8_MASK, PseudoVSSUBU_VV_M8, 0x3, false }, // 2576
|
|
{ PseudoVSSUBU_VV_MF2_MASK, PseudoVSSUBU_VV_MF2, 0x3, false }, // 2577
|
|
{ PseudoVSSUBU_VV_MF4_MASK, PseudoVSSUBU_VV_MF4, 0x3, false }, // 2578
|
|
{ PseudoVSSUBU_VV_MF8_MASK, PseudoVSSUBU_VV_MF8, 0x3, false }, // 2579
|
|
{ PseudoVSSUBU_VX_M1_MASK, PseudoVSSUBU_VX_M1, 0x3, false }, // 2580
|
|
{ PseudoVSSUBU_VX_M2_MASK, PseudoVSSUBU_VX_M2, 0x3, false }, // 2581
|
|
{ PseudoVSSUBU_VX_M4_MASK, PseudoVSSUBU_VX_M4, 0x3, false }, // 2582
|
|
{ PseudoVSSUBU_VX_M8_MASK, PseudoVSSUBU_VX_M8, 0x3, false }, // 2583
|
|
{ PseudoVSSUBU_VX_MF2_MASK, PseudoVSSUBU_VX_MF2, 0x3, false }, // 2584
|
|
{ PseudoVSSUBU_VX_MF4_MASK, PseudoVSSUBU_VX_MF4, 0x3, false }, // 2585
|
|
{ PseudoVSSUBU_VX_MF8_MASK, PseudoVSSUBU_VX_MF8, 0x3, false }, // 2586
|
|
{ PseudoVSSUB_VV_M1_MASK, PseudoVSSUB_VV_M1, 0x3, false }, // 2587
|
|
{ PseudoVSSUB_VV_M2_MASK, PseudoVSSUB_VV_M2, 0x3, false }, // 2588
|
|
{ PseudoVSSUB_VV_M4_MASK, PseudoVSSUB_VV_M4, 0x3, false }, // 2589
|
|
{ PseudoVSSUB_VV_M8_MASK, PseudoVSSUB_VV_M8, 0x3, false }, // 2590
|
|
{ PseudoVSSUB_VV_MF2_MASK, PseudoVSSUB_VV_MF2, 0x3, false }, // 2591
|
|
{ PseudoVSSUB_VV_MF4_MASK, PseudoVSSUB_VV_MF4, 0x3, false }, // 2592
|
|
{ PseudoVSSUB_VV_MF8_MASK, PseudoVSSUB_VV_MF8, 0x3, false }, // 2593
|
|
{ PseudoVSSUB_VX_M1_MASK, PseudoVSSUB_VX_M1, 0x3, false }, // 2594
|
|
{ PseudoVSSUB_VX_M2_MASK, PseudoVSSUB_VX_M2, 0x3, false }, // 2595
|
|
{ PseudoVSSUB_VX_M4_MASK, PseudoVSSUB_VX_M4, 0x3, false }, // 2596
|
|
{ PseudoVSSUB_VX_M8_MASK, PseudoVSSUB_VX_M8, 0x3, false }, // 2597
|
|
{ PseudoVSSUB_VX_MF2_MASK, PseudoVSSUB_VX_MF2, 0x3, false }, // 2598
|
|
{ PseudoVSSUB_VX_MF4_MASK, PseudoVSSUB_VX_MF4, 0x3, false }, // 2599
|
|
{ PseudoVSSUB_VX_MF8_MASK, PseudoVSSUB_VX_MF8, 0x3, false }, // 2600
|
|
{ PseudoVSUB_VV_M1_MASK, PseudoVSUB_VV_M1, 0x3, false }, // 2601
|
|
{ PseudoVSUB_VV_M2_MASK, PseudoVSUB_VV_M2, 0x3, false }, // 2602
|
|
{ PseudoVSUB_VV_M4_MASK, PseudoVSUB_VV_M4, 0x3, false }, // 2603
|
|
{ PseudoVSUB_VV_M8_MASK, PseudoVSUB_VV_M8, 0x3, false }, // 2604
|
|
{ PseudoVSUB_VV_MF2_MASK, PseudoVSUB_VV_MF2, 0x3, false }, // 2605
|
|
{ PseudoVSUB_VV_MF4_MASK, PseudoVSUB_VV_MF4, 0x3, false }, // 2606
|
|
{ PseudoVSUB_VV_MF8_MASK, PseudoVSUB_VV_MF8, 0x3, false }, // 2607
|
|
{ PseudoVSUB_VX_M1_MASK, PseudoVSUB_VX_M1, 0x3, false }, // 2608
|
|
{ PseudoVSUB_VX_M2_MASK, PseudoVSUB_VX_M2, 0x3, false }, // 2609
|
|
{ PseudoVSUB_VX_M4_MASK, PseudoVSUB_VX_M4, 0x3, false }, // 2610
|
|
{ PseudoVSUB_VX_M8_MASK, PseudoVSUB_VX_M8, 0x3, false }, // 2611
|
|
{ PseudoVSUB_VX_MF2_MASK, PseudoVSUB_VX_MF2, 0x3, false }, // 2612
|
|
{ PseudoVSUB_VX_MF4_MASK, PseudoVSUB_VX_MF4, 0x3, false }, // 2613
|
|
{ PseudoVSUB_VX_MF8_MASK, PseudoVSUB_VX_MF8, 0x3, false }, // 2614
|
|
{ PseudoVWADDU_VV_M1_MASK, PseudoVWADDU_VV_M1, 0x3, false }, // 2615
|
|
{ PseudoVWADDU_VV_M2_MASK, PseudoVWADDU_VV_M2, 0x3, false }, // 2616
|
|
{ PseudoVWADDU_VV_M4_MASK, PseudoVWADDU_VV_M4, 0x3, false }, // 2617
|
|
{ PseudoVWADDU_VV_MF2_MASK, PseudoVWADDU_VV_MF2, 0x3, false }, // 2618
|
|
{ PseudoVWADDU_VV_MF4_MASK, PseudoVWADDU_VV_MF4, 0x3, false }, // 2619
|
|
{ PseudoVWADDU_VV_MF8_MASK, PseudoVWADDU_VV_MF8, 0x3, false }, // 2620
|
|
{ PseudoVWADDU_VX_M1_MASK, PseudoVWADDU_VX_M1, 0x3, false }, // 2621
|
|
{ PseudoVWADDU_VX_M2_MASK, PseudoVWADDU_VX_M2, 0x3, false }, // 2622
|
|
{ PseudoVWADDU_VX_M4_MASK, PseudoVWADDU_VX_M4, 0x3, false }, // 2623
|
|
{ PseudoVWADDU_VX_MF2_MASK, PseudoVWADDU_VX_MF2, 0x3, false }, // 2624
|
|
{ PseudoVWADDU_VX_MF4_MASK, PseudoVWADDU_VX_MF4, 0x3, false }, // 2625
|
|
{ PseudoVWADDU_VX_MF8_MASK, PseudoVWADDU_VX_MF8, 0x3, false }, // 2626
|
|
{ PseudoVWADDU_WV_M1_MASK, PseudoVWADDU_WV_M1, 0x3, false }, // 2627
|
|
{ PseudoVWADDU_WV_M2_MASK, PseudoVWADDU_WV_M2, 0x3, false }, // 2628
|
|
{ PseudoVWADDU_WV_M4_MASK, PseudoVWADDU_WV_M4, 0x3, false }, // 2629
|
|
{ PseudoVWADDU_WV_MF2_MASK, PseudoVWADDU_WV_MF2, 0x3, false }, // 2630
|
|
{ PseudoVWADDU_WV_MF4_MASK, PseudoVWADDU_WV_MF4, 0x3, false }, // 2631
|
|
{ PseudoVWADDU_WV_MF8_MASK, PseudoVWADDU_WV_MF8, 0x3, false }, // 2632
|
|
{ PseudoVWADDU_WX_M1_MASK, PseudoVWADDU_WX_M1, 0x3, false }, // 2633
|
|
{ PseudoVWADDU_WX_M2_MASK, PseudoVWADDU_WX_M2, 0x3, false }, // 2634
|
|
{ PseudoVWADDU_WX_M4_MASK, PseudoVWADDU_WX_M4, 0x3, false }, // 2635
|
|
{ PseudoVWADDU_WX_MF2_MASK, PseudoVWADDU_WX_MF2, 0x3, false }, // 2636
|
|
{ PseudoVWADDU_WX_MF4_MASK, PseudoVWADDU_WX_MF4, 0x3, false }, // 2637
|
|
{ PseudoVWADDU_WX_MF8_MASK, PseudoVWADDU_WX_MF8, 0x3, false }, // 2638
|
|
{ PseudoVWADD_VV_M1_MASK, PseudoVWADD_VV_M1, 0x3, false }, // 2639
|
|
{ PseudoVWADD_VV_M2_MASK, PseudoVWADD_VV_M2, 0x3, false }, // 2640
|
|
{ PseudoVWADD_VV_M4_MASK, PseudoVWADD_VV_M4, 0x3, false }, // 2641
|
|
{ PseudoVWADD_VV_MF2_MASK, PseudoVWADD_VV_MF2, 0x3, false }, // 2642
|
|
{ PseudoVWADD_VV_MF4_MASK, PseudoVWADD_VV_MF4, 0x3, false }, // 2643
|
|
{ PseudoVWADD_VV_MF8_MASK, PseudoVWADD_VV_MF8, 0x3, false }, // 2644
|
|
{ PseudoVWADD_VX_M1_MASK, PseudoVWADD_VX_M1, 0x3, false }, // 2645
|
|
{ PseudoVWADD_VX_M2_MASK, PseudoVWADD_VX_M2, 0x3, false }, // 2646
|
|
{ PseudoVWADD_VX_M4_MASK, PseudoVWADD_VX_M4, 0x3, false }, // 2647
|
|
{ PseudoVWADD_VX_MF2_MASK, PseudoVWADD_VX_MF2, 0x3, false }, // 2648
|
|
{ PseudoVWADD_VX_MF4_MASK, PseudoVWADD_VX_MF4, 0x3, false }, // 2649
|
|
{ PseudoVWADD_VX_MF8_MASK, PseudoVWADD_VX_MF8, 0x3, false }, // 2650
|
|
{ PseudoVWADD_WV_M1_MASK, PseudoVWADD_WV_M1, 0x3, false }, // 2651
|
|
{ PseudoVWADD_WV_M2_MASK, PseudoVWADD_WV_M2, 0x3, false }, // 2652
|
|
{ PseudoVWADD_WV_M4_MASK, PseudoVWADD_WV_M4, 0x3, false }, // 2653
|
|
{ PseudoVWADD_WV_MF2_MASK, PseudoVWADD_WV_MF2, 0x3, false }, // 2654
|
|
{ PseudoVWADD_WV_MF4_MASK, PseudoVWADD_WV_MF4, 0x3, false }, // 2655
|
|
{ PseudoVWADD_WV_MF8_MASK, PseudoVWADD_WV_MF8, 0x3, false }, // 2656
|
|
{ PseudoVWADD_WX_M1_MASK, PseudoVWADD_WX_M1, 0x3, false }, // 2657
|
|
{ PseudoVWADD_WX_M2_MASK, PseudoVWADD_WX_M2, 0x3, false }, // 2658
|
|
{ PseudoVWADD_WX_M4_MASK, PseudoVWADD_WX_M4, 0x3, false }, // 2659
|
|
{ PseudoVWADD_WX_MF2_MASK, PseudoVWADD_WX_MF2, 0x3, false }, // 2660
|
|
{ PseudoVWADD_WX_MF4_MASK, PseudoVWADD_WX_MF4, 0x3, false }, // 2661
|
|
{ PseudoVWADD_WX_MF8_MASK, PseudoVWADD_WX_MF8, 0x3, false }, // 2662
|
|
{ PseudoVWMACCSU_VV_M1_MASK, PseudoVWMACCSU_VV_M1, 0x3, false }, // 2663
|
|
{ PseudoVWMACCSU_VV_M2_MASK, PseudoVWMACCSU_VV_M2, 0x3, false }, // 2664
|
|
{ PseudoVWMACCSU_VV_M4_MASK, PseudoVWMACCSU_VV_M4, 0x3, false }, // 2665
|
|
{ PseudoVWMACCSU_VV_MF2_MASK, PseudoVWMACCSU_VV_MF2, 0x3, false }, // 2666
|
|
{ PseudoVWMACCSU_VV_MF4_MASK, PseudoVWMACCSU_VV_MF4, 0x3, false }, // 2667
|
|
{ PseudoVWMACCSU_VV_MF8_MASK, PseudoVWMACCSU_VV_MF8, 0x3, false }, // 2668
|
|
{ PseudoVWMACCSU_VX_M1_MASK, PseudoVWMACCSU_VX_M1, 0x3, false }, // 2669
|
|
{ PseudoVWMACCSU_VX_M2_MASK, PseudoVWMACCSU_VX_M2, 0x3, false }, // 2670
|
|
{ PseudoVWMACCSU_VX_M4_MASK, PseudoVWMACCSU_VX_M4, 0x3, false }, // 2671
|
|
{ PseudoVWMACCSU_VX_MF2_MASK, PseudoVWMACCSU_VX_MF2, 0x3, false }, // 2672
|
|
{ PseudoVWMACCSU_VX_MF4_MASK, PseudoVWMACCSU_VX_MF4, 0x3, false }, // 2673
|
|
{ PseudoVWMACCSU_VX_MF8_MASK, PseudoVWMACCSU_VX_MF8, 0x3, false }, // 2674
|
|
{ PseudoVWMACCUS_VX_M1_MASK, PseudoVWMACCUS_VX_M1, 0x3, false }, // 2675
|
|
{ PseudoVWMACCUS_VX_M2_MASK, PseudoVWMACCUS_VX_M2, 0x3, false }, // 2676
|
|
{ PseudoVWMACCUS_VX_M4_MASK, PseudoVWMACCUS_VX_M4, 0x3, false }, // 2677
|
|
{ PseudoVWMACCUS_VX_MF2_MASK, PseudoVWMACCUS_VX_MF2, 0x3, false }, // 2678
|
|
{ PseudoVWMACCUS_VX_MF4_MASK, PseudoVWMACCUS_VX_MF4, 0x3, false }, // 2679
|
|
{ PseudoVWMACCUS_VX_MF8_MASK, PseudoVWMACCUS_VX_MF8, 0x3, false }, // 2680
|
|
{ PseudoVWMACCU_VV_M1_MASK, PseudoVWMACCU_VV_M1, 0x3, false }, // 2681
|
|
{ PseudoVWMACCU_VV_M2_MASK, PseudoVWMACCU_VV_M2, 0x3, false }, // 2682
|
|
{ PseudoVWMACCU_VV_M4_MASK, PseudoVWMACCU_VV_M4, 0x3, false }, // 2683
|
|
{ PseudoVWMACCU_VV_MF2_MASK, PseudoVWMACCU_VV_MF2, 0x3, false }, // 2684
|
|
{ PseudoVWMACCU_VV_MF4_MASK, PseudoVWMACCU_VV_MF4, 0x3, false }, // 2685
|
|
{ PseudoVWMACCU_VV_MF8_MASK, PseudoVWMACCU_VV_MF8, 0x3, false }, // 2686
|
|
{ PseudoVWMACCU_VX_M1_MASK, PseudoVWMACCU_VX_M1, 0x3, false }, // 2687
|
|
{ PseudoVWMACCU_VX_M2_MASK, PseudoVWMACCU_VX_M2, 0x3, false }, // 2688
|
|
{ PseudoVWMACCU_VX_M4_MASK, PseudoVWMACCU_VX_M4, 0x3, false }, // 2689
|
|
{ PseudoVWMACCU_VX_MF2_MASK, PseudoVWMACCU_VX_MF2, 0x3, false }, // 2690
|
|
{ PseudoVWMACCU_VX_MF4_MASK, PseudoVWMACCU_VX_MF4, 0x3, false }, // 2691
|
|
{ PseudoVWMACCU_VX_MF8_MASK, PseudoVWMACCU_VX_MF8, 0x3, false }, // 2692
|
|
{ PseudoVWMACC_VV_M1_MASK, PseudoVWMACC_VV_M1, 0x3, false }, // 2693
|
|
{ PseudoVWMACC_VV_M2_MASK, PseudoVWMACC_VV_M2, 0x3, false }, // 2694
|
|
{ PseudoVWMACC_VV_M4_MASK, PseudoVWMACC_VV_M4, 0x3, false }, // 2695
|
|
{ PseudoVWMACC_VV_MF2_MASK, PseudoVWMACC_VV_MF2, 0x3, false }, // 2696
|
|
{ PseudoVWMACC_VV_MF4_MASK, PseudoVWMACC_VV_MF4, 0x3, false }, // 2697
|
|
{ PseudoVWMACC_VV_MF8_MASK, PseudoVWMACC_VV_MF8, 0x3, false }, // 2698
|
|
{ PseudoVWMACC_VX_M1_MASK, PseudoVWMACC_VX_M1, 0x3, false }, // 2699
|
|
{ PseudoVWMACC_VX_M2_MASK, PseudoVWMACC_VX_M2, 0x3, false }, // 2700
|
|
{ PseudoVWMACC_VX_M4_MASK, PseudoVWMACC_VX_M4, 0x3, false }, // 2701
|
|
{ PseudoVWMACC_VX_MF2_MASK, PseudoVWMACC_VX_MF2, 0x3, false }, // 2702
|
|
{ PseudoVWMACC_VX_MF4_MASK, PseudoVWMACC_VX_MF4, 0x3, false }, // 2703
|
|
{ PseudoVWMACC_VX_MF8_MASK, PseudoVWMACC_VX_MF8, 0x3, false }, // 2704
|
|
{ PseudoVWMULSU_VV_M1_MASK, PseudoVWMULSU_VV_M1, 0x3, false }, // 2705
|
|
{ PseudoVWMULSU_VV_M2_MASK, PseudoVWMULSU_VV_M2, 0x3, false }, // 2706
|
|
{ PseudoVWMULSU_VV_M4_MASK, PseudoVWMULSU_VV_M4, 0x3, false }, // 2707
|
|
{ PseudoVWMULSU_VV_MF2_MASK, PseudoVWMULSU_VV_MF2, 0x3, false }, // 2708
|
|
{ PseudoVWMULSU_VV_MF4_MASK, PseudoVWMULSU_VV_MF4, 0x3, false }, // 2709
|
|
{ PseudoVWMULSU_VV_MF8_MASK, PseudoVWMULSU_VV_MF8, 0x3, false }, // 2710
|
|
{ PseudoVWMULSU_VX_M1_MASK, PseudoVWMULSU_VX_M1, 0x3, false }, // 2711
|
|
{ PseudoVWMULSU_VX_M2_MASK, PseudoVWMULSU_VX_M2, 0x3, false }, // 2712
|
|
{ PseudoVWMULSU_VX_M4_MASK, PseudoVWMULSU_VX_M4, 0x3, false }, // 2713
|
|
{ PseudoVWMULSU_VX_MF2_MASK, PseudoVWMULSU_VX_MF2, 0x3, false }, // 2714
|
|
{ PseudoVWMULSU_VX_MF4_MASK, PseudoVWMULSU_VX_MF4, 0x3, false }, // 2715
|
|
{ PseudoVWMULSU_VX_MF8_MASK, PseudoVWMULSU_VX_MF8, 0x3, false }, // 2716
|
|
{ PseudoVWMULU_VV_M1_MASK, PseudoVWMULU_VV_M1, 0x3, false }, // 2717
|
|
{ PseudoVWMULU_VV_M2_MASK, PseudoVWMULU_VV_M2, 0x3, false }, // 2718
|
|
{ PseudoVWMULU_VV_M4_MASK, PseudoVWMULU_VV_M4, 0x3, false }, // 2719
|
|
{ PseudoVWMULU_VV_MF2_MASK, PseudoVWMULU_VV_MF2, 0x3, false }, // 2720
|
|
{ PseudoVWMULU_VV_MF4_MASK, PseudoVWMULU_VV_MF4, 0x3, false }, // 2721
|
|
{ PseudoVWMULU_VV_MF8_MASK, PseudoVWMULU_VV_MF8, 0x3, false }, // 2722
|
|
{ PseudoVWMULU_VX_M1_MASK, PseudoVWMULU_VX_M1, 0x3, false }, // 2723
|
|
{ PseudoVWMULU_VX_M2_MASK, PseudoVWMULU_VX_M2, 0x3, false }, // 2724
|
|
{ PseudoVWMULU_VX_M4_MASK, PseudoVWMULU_VX_M4, 0x3, false }, // 2725
|
|
{ PseudoVWMULU_VX_MF2_MASK, PseudoVWMULU_VX_MF2, 0x3, false }, // 2726
|
|
{ PseudoVWMULU_VX_MF4_MASK, PseudoVWMULU_VX_MF4, 0x3, false }, // 2727
|
|
{ PseudoVWMULU_VX_MF8_MASK, PseudoVWMULU_VX_MF8, 0x3, false }, // 2728
|
|
{ PseudoVWMUL_VV_M1_MASK, PseudoVWMUL_VV_M1, 0x3, false }, // 2729
|
|
{ PseudoVWMUL_VV_M2_MASK, PseudoVWMUL_VV_M2, 0x3, false }, // 2730
|
|
{ PseudoVWMUL_VV_M4_MASK, PseudoVWMUL_VV_M4, 0x3, false }, // 2731
|
|
{ PseudoVWMUL_VV_MF2_MASK, PseudoVWMUL_VV_MF2, 0x3, false }, // 2732
|
|
{ PseudoVWMUL_VV_MF4_MASK, PseudoVWMUL_VV_MF4, 0x3, false }, // 2733
|
|
{ PseudoVWMUL_VV_MF8_MASK, PseudoVWMUL_VV_MF8, 0x3, false }, // 2734
|
|
{ PseudoVWMUL_VX_M1_MASK, PseudoVWMUL_VX_M1, 0x3, false }, // 2735
|
|
{ PseudoVWMUL_VX_M2_MASK, PseudoVWMUL_VX_M2, 0x3, false }, // 2736
|
|
{ PseudoVWMUL_VX_M4_MASK, PseudoVWMUL_VX_M4, 0x3, false }, // 2737
|
|
{ PseudoVWMUL_VX_MF2_MASK, PseudoVWMUL_VX_MF2, 0x3, false }, // 2738
|
|
{ PseudoVWMUL_VX_MF4_MASK, PseudoVWMUL_VX_MF4, 0x3, false }, // 2739
|
|
{ PseudoVWMUL_VX_MF8_MASK, PseudoVWMUL_VX_MF8, 0x3, false }, // 2740
|
|
{ PseudoVWREDSUMU_VS_M1_E16_MASK, PseudoVWREDSUMU_VS_M1_E16, 0x3, true }, // 2741
|
|
{ PseudoVWREDSUMU_VS_M1_E32_MASK, PseudoVWREDSUMU_VS_M1_E32, 0x3, true }, // 2742
|
|
{ PseudoVWREDSUMU_VS_M1_E8_MASK, PseudoVWREDSUMU_VS_M1_E8, 0x3, true }, // 2743
|
|
{ PseudoVWREDSUMU_VS_M2_E16_MASK, PseudoVWREDSUMU_VS_M2_E16, 0x3, true }, // 2744
|
|
{ PseudoVWREDSUMU_VS_M2_E32_MASK, PseudoVWREDSUMU_VS_M2_E32, 0x3, true }, // 2745
|
|
{ PseudoVWREDSUMU_VS_M2_E8_MASK, PseudoVWREDSUMU_VS_M2_E8, 0x3, true }, // 2746
|
|
{ PseudoVWREDSUMU_VS_M4_E16_MASK, PseudoVWREDSUMU_VS_M4_E16, 0x3, true }, // 2747
|
|
{ PseudoVWREDSUMU_VS_M4_E32_MASK, PseudoVWREDSUMU_VS_M4_E32, 0x3, true }, // 2748
|
|
{ PseudoVWREDSUMU_VS_M4_E8_MASK, PseudoVWREDSUMU_VS_M4_E8, 0x3, true }, // 2749
|
|
{ PseudoVWREDSUMU_VS_M8_E16_MASK, PseudoVWREDSUMU_VS_M8_E16, 0x3, true }, // 2750
|
|
{ PseudoVWREDSUMU_VS_M8_E32_MASK, PseudoVWREDSUMU_VS_M8_E32, 0x3, true }, // 2751
|
|
{ PseudoVWREDSUMU_VS_M8_E8_MASK, PseudoVWREDSUMU_VS_M8_E8, 0x3, true }, // 2752
|
|
{ PseudoVWREDSUMU_VS_MF2_E16_MASK, PseudoVWREDSUMU_VS_MF2_E16, 0x3, true }, // 2753
|
|
{ PseudoVWREDSUMU_VS_MF2_E32_MASK, PseudoVWREDSUMU_VS_MF2_E32, 0x3, true }, // 2754
|
|
{ PseudoVWREDSUMU_VS_MF2_E8_MASK, PseudoVWREDSUMU_VS_MF2_E8, 0x3, true }, // 2755
|
|
{ PseudoVWREDSUMU_VS_MF4_E16_MASK, PseudoVWREDSUMU_VS_MF4_E16, 0x3, true }, // 2756
|
|
{ PseudoVWREDSUMU_VS_MF4_E8_MASK, PseudoVWREDSUMU_VS_MF4_E8, 0x3, true }, // 2757
|
|
{ PseudoVWREDSUMU_VS_MF8_E8_MASK, PseudoVWREDSUMU_VS_MF8_E8, 0x3, true }, // 2758
|
|
{ PseudoVWREDSUM_VS_M1_E16_MASK, PseudoVWREDSUM_VS_M1_E16, 0x3, true }, // 2759
|
|
{ PseudoVWREDSUM_VS_M1_E32_MASK, PseudoVWREDSUM_VS_M1_E32, 0x3, true }, // 2760
|
|
{ PseudoVWREDSUM_VS_M1_E8_MASK, PseudoVWREDSUM_VS_M1_E8, 0x3, true }, // 2761
|
|
{ PseudoVWREDSUM_VS_M2_E16_MASK, PseudoVWREDSUM_VS_M2_E16, 0x3, true }, // 2762
|
|
{ PseudoVWREDSUM_VS_M2_E32_MASK, PseudoVWREDSUM_VS_M2_E32, 0x3, true }, // 2763
|
|
{ PseudoVWREDSUM_VS_M2_E8_MASK, PseudoVWREDSUM_VS_M2_E8, 0x3, true }, // 2764
|
|
{ PseudoVWREDSUM_VS_M4_E16_MASK, PseudoVWREDSUM_VS_M4_E16, 0x3, true }, // 2765
|
|
{ PseudoVWREDSUM_VS_M4_E32_MASK, PseudoVWREDSUM_VS_M4_E32, 0x3, true }, // 2766
|
|
{ PseudoVWREDSUM_VS_M4_E8_MASK, PseudoVWREDSUM_VS_M4_E8, 0x3, true }, // 2767
|
|
{ PseudoVWREDSUM_VS_M8_E16_MASK, PseudoVWREDSUM_VS_M8_E16, 0x3, true }, // 2768
|
|
{ PseudoVWREDSUM_VS_M8_E32_MASK, PseudoVWREDSUM_VS_M8_E32, 0x3, true }, // 2769
|
|
{ PseudoVWREDSUM_VS_M8_E8_MASK, PseudoVWREDSUM_VS_M8_E8, 0x3, true }, // 2770
|
|
{ PseudoVWREDSUM_VS_MF2_E16_MASK, PseudoVWREDSUM_VS_MF2_E16, 0x3, true }, // 2771
|
|
{ PseudoVWREDSUM_VS_MF2_E32_MASK, PseudoVWREDSUM_VS_MF2_E32, 0x3, true }, // 2772
|
|
{ PseudoVWREDSUM_VS_MF2_E8_MASK, PseudoVWREDSUM_VS_MF2_E8, 0x3, true }, // 2773
|
|
{ PseudoVWREDSUM_VS_MF4_E16_MASK, PseudoVWREDSUM_VS_MF4_E16, 0x3, true }, // 2774
|
|
{ PseudoVWREDSUM_VS_MF4_E8_MASK, PseudoVWREDSUM_VS_MF4_E8, 0x3, true }, // 2775
|
|
{ PseudoVWREDSUM_VS_MF8_E8_MASK, PseudoVWREDSUM_VS_MF8_E8, 0x3, true }, // 2776
|
|
{ PseudoVWSLL_VI_M1_MASK, PseudoVWSLL_VI_M1, 0x3, false }, // 2777
|
|
{ PseudoVWSLL_VI_M2_MASK, PseudoVWSLL_VI_M2, 0x3, false }, // 2778
|
|
{ PseudoVWSLL_VI_M4_MASK, PseudoVWSLL_VI_M4, 0x3, false }, // 2779
|
|
{ PseudoVWSLL_VI_MF2_MASK, PseudoVWSLL_VI_MF2, 0x3, false }, // 2780
|
|
{ PseudoVWSLL_VI_MF4_MASK, PseudoVWSLL_VI_MF4, 0x3, false }, // 2781
|
|
{ PseudoVWSLL_VI_MF8_MASK, PseudoVWSLL_VI_MF8, 0x3, false }, // 2782
|
|
{ PseudoVWSLL_VV_M1_MASK, PseudoVWSLL_VV_M1, 0x3, false }, // 2783
|
|
{ PseudoVWSLL_VV_M2_MASK, PseudoVWSLL_VV_M2, 0x3, false }, // 2784
|
|
{ PseudoVWSLL_VV_M4_MASK, PseudoVWSLL_VV_M4, 0x3, false }, // 2785
|
|
{ PseudoVWSLL_VV_MF2_MASK, PseudoVWSLL_VV_MF2, 0x3, false }, // 2786
|
|
{ PseudoVWSLL_VV_MF4_MASK, PseudoVWSLL_VV_MF4, 0x3, false }, // 2787
|
|
{ PseudoVWSLL_VV_MF8_MASK, PseudoVWSLL_VV_MF8, 0x3, false }, // 2788
|
|
{ PseudoVWSLL_VX_M1_MASK, PseudoVWSLL_VX_M1, 0x3, false }, // 2789
|
|
{ PseudoVWSLL_VX_M2_MASK, PseudoVWSLL_VX_M2, 0x3, false }, // 2790
|
|
{ PseudoVWSLL_VX_M4_MASK, PseudoVWSLL_VX_M4, 0x3, false }, // 2791
|
|
{ PseudoVWSLL_VX_MF2_MASK, PseudoVWSLL_VX_MF2, 0x3, false }, // 2792
|
|
{ PseudoVWSLL_VX_MF4_MASK, PseudoVWSLL_VX_MF4, 0x3, false }, // 2793
|
|
{ PseudoVWSLL_VX_MF8_MASK, PseudoVWSLL_VX_MF8, 0x3, false }, // 2794
|
|
{ PseudoVWSUBU_VV_M1_MASK, PseudoVWSUBU_VV_M1, 0x3, false }, // 2795
|
|
{ PseudoVWSUBU_VV_M2_MASK, PseudoVWSUBU_VV_M2, 0x3, false }, // 2796
|
|
{ PseudoVWSUBU_VV_M4_MASK, PseudoVWSUBU_VV_M4, 0x3, false }, // 2797
|
|
{ PseudoVWSUBU_VV_MF2_MASK, PseudoVWSUBU_VV_MF2, 0x3, false }, // 2798
|
|
{ PseudoVWSUBU_VV_MF4_MASK, PseudoVWSUBU_VV_MF4, 0x3, false }, // 2799
|
|
{ PseudoVWSUBU_VV_MF8_MASK, PseudoVWSUBU_VV_MF8, 0x3, false }, // 2800
|
|
{ PseudoVWSUBU_VX_M1_MASK, PseudoVWSUBU_VX_M1, 0x3, false }, // 2801
|
|
{ PseudoVWSUBU_VX_M2_MASK, PseudoVWSUBU_VX_M2, 0x3, false }, // 2802
|
|
{ PseudoVWSUBU_VX_M4_MASK, PseudoVWSUBU_VX_M4, 0x3, false }, // 2803
|
|
{ PseudoVWSUBU_VX_MF2_MASK, PseudoVWSUBU_VX_MF2, 0x3, false }, // 2804
|
|
{ PseudoVWSUBU_VX_MF4_MASK, PseudoVWSUBU_VX_MF4, 0x3, false }, // 2805
|
|
{ PseudoVWSUBU_VX_MF8_MASK, PseudoVWSUBU_VX_MF8, 0x3, false }, // 2806
|
|
{ PseudoVWSUBU_WV_M1_MASK, PseudoVWSUBU_WV_M1, 0x3, false }, // 2807
|
|
{ PseudoVWSUBU_WV_M2_MASK, PseudoVWSUBU_WV_M2, 0x3, false }, // 2808
|
|
{ PseudoVWSUBU_WV_M4_MASK, PseudoVWSUBU_WV_M4, 0x3, false }, // 2809
|
|
{ PseudoVWSUBU_WV_MF2_MASK, PseudoVWSUBU_WV_MF2, 0x3, false }, // 2810
|
|
{ PseudoVWSUBU_WV_MF4_MASK, PseudoVWSUBU_WV_MF4, 0x3, false }, // 2811
|
|
{ PseudoVWSUBU_WV_MF8_MASK, PseudoVWSUBU_WV_MF8, 0x3, false }, // 2812
|
|
{ PseudoVWSUBU_WX_M1_MASK, PseudoVWSUBU_WX_M1, 0x3, false }, // 2813
|
|
{ PseudoVWSUBU_WX_M2_MASK, PseudoVWSUBU_WX_M2, 0x3, false }, // 2814
|
|
{ PseudoVWSUBU_WX_M4_MASK, PseudoVWSUBU_WX_M4, 0x3, false }, // 2815
|
|
{ PseudoVWSUBU_WX_MF2_MASK, PseudoVWSUBU_WX_MF2, 0x3, false }, // 2816
|
|
{ PseudoVWSUBU_WX_MF4_MASK, PseudoVWSUBU_WX_MF4, 0x3, false }, // 2817
|
|
{ PseudoVWSUBU_WX_MF8_MASK, PseudoVWSUBU_WX_MF8, 0x3, false }, // 2818
|
|
{ PseudoVWSUB_VV_M1_MASK, PseudoVWSUB_VV_M1, 0x3, false }, // 2819
|
|
{ PseudoVWSUB_VV_M2_MASK, PseudoVWSUB_VV_M2, 0x3, false }, // 2820
|
|
{ PseudoVWSUB_VV_M4_MASK, PseudoVWSUB_VV_M4, 0x3, false }, // 2821
|
|
{ PseudoVWSUB_VV_MF2_MASK, PseudoVWSUB_VV_MF2, 0x3, false }, // 2822
|
|
{ PseudoVWSUB_VV_MF4_MASK, PseudoVWSUB_VV_MF4, 0x3, false }, // 2823
|
|
{ PseudoVWSUB_VV_MF8_MASK, PseudoVWSUB_VV_MF8, 0x3, false }, // 2824
|
|
{ PseudoVWSUB_VX_M1_MASK, PseudoVWSUB_VX_M1, 0x3, false }, // 2825
|
|
{ PseudoVWSUB_VX_M2_MASK, PseudoVWSUB_VX_M2, 0x3, false }, // 2826
|
|
{ PseudoVWSUB_VX_M4_MASK, PseudoVWSUB_VX_M4, 0x3, false }, // 2827
|
|
{ PseudoVWSUB_VX_MF2_MASK, PseudoVWSUB_VX_MF2, 0x3, false }, // 2828
|
|
{ PseudoVWSUB_VX_MF4_MASK, PseudoVWSUB_VX_MF4, 0x3, false }, // 2829
|
|
{ PseudoVWSUB_VX_MF8_MASK, PseudoVWSUB_VX_MF8, 0x3, false }, // 2830
|
|
{ PseudoVWSUB_WV_M1_MASK, PseudoVWSUB_WV_M1, 0x3, false }, // 2831
|
|
{ PseudoVWSUB_WV_M2_MASK, PseudoVWSUB_WV_M2, 0x3, false }, // 2832
|
|
{ PseudoVWSUB_WV_M4_MASK, PseudoVWSUB_WV_M4, 0x3, false }, // 2833
|
|
{ PseudoVWSUB_WV_MF2_MASK, PseudoVWSUB_WV_MF2, 0x3, false }, // 2834
|
|
{ PseudoVWSUB_WV_MF4_MASK, PseudoVWSUB_WV_MF4, 0x3, false }, // 2835
|
|
{ PseudoVWSUB_WV_MF8_MASK, PseudoVWSUB_WV_MF8, 0x3, false }, // 2836
|
|
{ PseudoVWSUB_WX_M1_MASK, PseudoVWSUB_WX_M1, 0x3, false }, // 2837
|
|
{ PseudoVWSUB_WX_M2_MASK, PseudoVWSUB_WX_M2, 0x3, false }, // 2838
|
|
{ PseudoVWSUB_WX_M4_MASK, PseudoVWSUB_WX_M4, 0x3, false }, // 2839
|
|
{ PseudoVWSUB_WX_MF2_MASK, PseudoVWSUB_WX_MF2, 0x3, false }, // 2840
|
|
{ PseudoVWSUB_WX_MF4_MASK, PseudoVWSUB_WX_MF4, 0x3, false }, // 2841
|
|
{ PseudoVWSUB_WX_MF8_MASK, PseudoVWSUB_WX_MF8, 0x3, false }, // 2842
|
|
{ PseudoVXOR_VI_M1_MASK, PseudoVXOR_VI_M1, 0x3, false }, // 2843
|
|
{ PseudoVXOR_VI_M2_MASK, PseudoVXOR_VI_M2, 0x3, false }, // 2844
|
|
{ PseudoVXOR_VI_M4_MASK, PseudoVXOR_VI_M4, 0x3, false }, // 2845
|
|
{ PseudoVXOR_VI_M8_MASK, PseudoVXOR_VI_M8, 0x3, false }, // 2846
|
|
{ PseudoVXOR_VI_MF2_MASK, PseudoVXOR_VI_MF2, 0x3, false }, // 2847
|
|
{ PseudoVXOR_VI_MF4_MASK, PseudoVXOR_VI_MF4, 0x3, false }, // 2848
|
|
{ PseudoVXOR_VI_MF8_MASK, PseudoVXOR_VI_MF8, 0x3, false }, // 2849
|
|
{ PseudoVXOR_VV_M1_MASK, PseudoVXOR_VV_M1, 0x3, false }, // 2850
|
|
{ PseudoVXOR_VV_M2_MASK, PseudoVXOR_VV_M2, 0x3, false }, // 2851
|
|
{ PseudoVXOR_VV_M4_MASK, PseudoVXOR_VV_M4, 0x3, false }, // 2852
|
|
{ PseudoVXOR_VV_M8_MASK, PseudoVXOR_VV_M8, 0x3, false }, // 2853
|
|
{ PseudoVXOR_VV_MF2_MASK, PseudoVXOR_VV_MF2, 0x3, false }, // 2854
|
|
{ PseudoVXOR_VV_MF4_MASK, PseudoVXOR_VV_MF4, 0x3, false }, // 2855
|
|
{ PseudoVXOR_VV_MF8_MASK, PseudoVXOR_VV_MF8, 0x3, false }, // 2856
|
|
{ PseudoVXOR_VX_M1_MASK, PseudoVXOR_VX_M1, 0x3, false }, // 2857
|
|
{ PseudoVXOR_VX_M2_MASK, PseudoVXOR_VX_M2, 0x3, false }, // 2858
|
|
{ PseudoVXOR_VX_M4_MASK, PseudoVXOR_VX_M4, 0x3, false }, // 2859
|
|
{ PseudoVXOR_VX_M8_MASK, PseudoVXOR_VX_M8, 0x3, false }, // 2860
|
|
{ PseudoVXOR_VX_MF2_MASK, PseudoVXOR_VX_MF2, 0x3, false }, // 2861
|
|
{ PseudoVXOR_VX_MF4_MASK, PseudoVXOR_VX_MF4, 0x3, false }, // 2862
|
|
{ PseudoVXOR_VX_MF8_MASK, PseudoVXOR_VX_MF8, 0x3, false }, // 2863
|
|
{ PseudoVZEXT_VF2_M1_MASK, PseudoVZEXT_VF2_M1, 0x2, false }, // 2864
|
|
{ PseudoVZEXT_VF2_M2_MASK, PseudoVZEXT_VF2_M2, 0x2, false }, // 2865
|
|
{ PseudoVZEXT_VF2_M4_MASK, PseudoVZEXT_VF2_M4, 0x2, false }, // 2866
|
|
{ PseudoVZEXT_VF2_M8_MASK, PseudoVZEXT_VF2_M8, 0x2, false }, // 2867
|
|
{ PseudoVZEXT_VF2_MF2_MASK, PseudoVZEXT_VF2_MF2, 0x2, false }, // 2868
|
|
{ PseudoVZEXT_VF2_MF4_MASK, PseudoVZEXT_VF2_MF4, 0x2, false }, // 2869
|
|
{ PseudoVZEXT_VF4_M1_MASK, PseudoVZEXT_VF4_M1, 0x2, false }, // 2870
|
|
{ PseudoVZEXT_VF4_M2_MASK, PseudoVZEXT_VF4_M2, 0x2, false }, // 2871
|
|
{ PseudoVZEXT_VF4_M4_MASK, PseudoVZEXT_VF4_M4, 0x2, false }, // 2872
|
|
{ PseudoVZEXT_VF4_M8_MASK, PseudoVZEXT_VF4_M8, 0x2, false }, // 2873
|
|
{ PseudoVZEXT_VF4_MF2_MASK, PseudoVZEXT_VF4_MF2, 0x2, false }, // 2874
|
|
{ PseudoVZEXT_VF8_M1_MASK, PseudoVZEXT_VF8_M1, 0x2, false }, // 2875
|
|
{ PseudoVZEXT_VF8_M2_MASK, PseudoVZEXT_VF8_M2, 0x2, false }, // 2876
|
|
{ PseudoVZEXT_VF8_M4_MASK, PseudoVZEXT_VF8_M4, 0x2, false }, // 2877
|
|
{ PseudoVZEXT_VF8_M8_MASK, PseudoVZEXT_VF8_M8, 0x2, false }, // 2878
|
|
};
|
|
|
|
const RISCV_RISCVMaskedPseudoInfo *RISCV_getMaskedPseudoInfo(unsigned MaskedPseudo) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedPseudo);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVMaskedPseudosTable[Index[i].index];
|
|
}
|
|
|
|
const RISCV_RISCVMaskedPseudoInfo *RISCV_lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo) {
|
|
static const struct IndexType Index[] = {
|
|
{ PseudoTHVdotVMAQASU_VV_M1, 0 },
|
|
{ PseudoTHVdotVMAQASU_VV_M2, 1 },
|
|
{ PseudoTHVdotVMAQASU_VV_M4, 2 },
|
|
{ PseudoTHVdotVMAQASU_VV_M8, 3 },
|
|
{ PseudoTHVdotVMAQASU_VV_MF2, 4 },
|
|
{ PseudoTHVdotVMAQASU_VX_M1, 5 },
|
|
{ PseudoTHVdotVMAQASU_VX_M2, 6 },
|
|
{ PseudoTHVdotVMAQASU_VX_M4, 7 },
|
|
{ PseudoTHVdotVMAQASU_VX_M8, 8 },
|
|
{ PseudoTHVdotVMAQASU_VX_MF2, 9 },
|
|
{ PseudoTHVdotVMAQAUS_VX_M1, 10 },
|
|
{ PseudoTHVdotVMAQAUS_VX_M2, 11 },
|
|
{ PseudoTHVdotVMAQAUS_VX_M4, 12 },
|
|
{ PseudoTHVdotVMAQAUS_VX_M8, 13 },
|
|
{ PseudoTHVdotVMAQAUS_VX_MF2, 14 },
|
|
{ PseudoTHVdotVMAQAU_VV_M1, 15 },
|
|
{ PseudoTHVdotVMAQAU_VV_M2, 16 },
|
|
{ PseudoTHVdotVMAQAU_VV_M4, 17 },
|
|
{ PseudoTHVdotVMAQAU_VV_M8, 18 },
|
|
{ PseudoTHVdotVMAQAU_VV_MF2, 19 },
|
|
{ PseudoTHVdotVMAQAU_VX_M1, 20 },
|
|
{ PseudoTHVdotVMAQAU_VX_M2, 21 },
|
|
{ PseudoTHVdotVMAQAU_VX_M4, 22 },
|
|
{ PseudoTHVdotVMAQAU_VX_M8, 23 },
|
|
{ PseudoTHVdotVMAQAU_VX_MF2, 24 },
|
|
{ PseudoTHVdotVMAQA_VV_M1, 25 },
|
|
{ PseudoTHVdotVMAQA_VV_M2, 26 },
|
|
{ PseudoTHVdotVMAQA_VV_M4, 27 },
|
|
{ PseudoTHVdotVMAQA_VV_M8, 28 },
|
|
{ PseudoTHVdotVMAQA_VV_MF2, 29 },
|
|
{ PseudoTHVdotVMAQA_VX_M1, 30 },
|
|
{ PseudoTHVdotVMAQA_VX_M2, 31 },
|
|
{ PseudoTHVdotVMAQA_VX_M4, 32 },
|
|
{ PseudoTHVdotVMAQA_VX_M8, 33 },
|
|
{ PseudoTHVdotVMAQA_VX_MF2, 34 },
|
|
{ PseudoVAADDU_VV_M1, 35 },
|
|
{ PseudoVAADDU_VV_M2, 36 },
|
|
{ PseudoVAADDU_VV_M4, 37 },
|
|
{ PseudoVAADDU_VV_M8, 38 },
|
|
{ PseudoVAADDU_VV_MF2, 39 },
|
|
{ PseudoVAADDU_VV_MF4, 40 },
|
|
{ PseudoVAADDU_VV_MF8, 41 },
|
|
{ PseudoVAADDU_VX_M1, 42 },
|
|
{ PseudoVAADDU_VX_M2, 43 },
|
|
{ PseudoVAADDU_VX_M4, 44 },
|
|
{ PseudoVAADDU_VX_M8, 45 },
|
|
{ PseudoVAADDU_VX_MF2, 46 },
|
|
{ PseudoVAADDU_VX_MF4, 47 },
|
|
{ PseudoVAADDU_VX_MF8, 48 },
|
|
{ PseudoVAADD_VV_M1, 49 },
|
|
{ PseudoVAADD_VV_M2, 50 },
|
|
{ PseudoVAADD_VV_M4, 51 },
|
|
{ PseudoVAADD_VV_M8, 52 },
|
|
{ PseudoVAADD_VV_MF2, 53 },
|
|
{ PseudoVAADD_VV_MF4, 54 },
|
|
{ PseudoVAADD_VV_MF8, 55 },
|
|
{ PseudoVAADD_VX_M1, 56 },
|
|
{ PseudoVAADD_VX_M2, 57 },
|
|
{ PseudoVAADD_VX_M4, 58 },
|
|
{ PseudoVAADD_VX_M8, 59 },
|
|
{ PseudoVAADD_VX_MF2, 60 },
|
|
{ PseudoVAADD_VX_MF4, 61 },
|
|
{ PseudoVAADD_VX_MF8, 62 },
|
|
{ PseudoVADD_VI_M1, 63 },
|
|
{ PseudoVADD_VI_M2, 64 },
|
|
{ PseudoVADD_VI_M4, 65 },
|
|
{ PseudoVADD_VI_M8, 66 },
|
|
{ PseudoVADD_VI_MF2, 67 },
|
|
{ PseudoVADD_VI_MF4, 68 },
|
|
{ PseudoVADD_VI_MF8, 69 },
|
|
{ PseudoVADD_VV_M1, 70 },
|
|
{ PseudoVADD_VV_M2, 71 },
|
|
{ PseudoVADD_VV_M4, 72 },
|
|
{ PseudoVADD_VV_M8, 73 },
|
|
{ PseudoVADD_VV_MF2, 74 },
|
|
{ PseudoVADD_VV_MF4, 75 },
|
|
{ PseudoVADD_VV_MF8, 76 },
|
|
{ PseudoVADD_VX_M1, 77 },
|
|
{ PseudoVADD_VX_M2, 78 },
|
|
{ PseudoVADD_VX_M4, 79 },
|
|
{ PseudoVADD_VX_M8, 80 },
|
|
{ PseudoVADD_VX_MF2, 81 },
|
|
{ PseudoVADD_VX_MF4, 82 },
|
|
{ PseudoVADD_VX_MF8, 83 },
|
|
{ PseudoVANDN_VV_M1, 84 },
|
|
{ PseudoVANDN_VV_M2, 85 },
|
|
{ PseudoVANDN_VV_M4, 86 },
|
|
{ PseudoVANDN_VV_M8, 87 },
|
|
{ PseudoVANDN_VV_MF2, 88 },
|
|
{ PseudoVANDN_VV_MF4, 89 },
|
|
{ PseudoVANDN_VV_MF8, 90 },
|
|
{ PseudoVANDN_VX_M1, 91 },
|
|
{ PseudoVANDN_VX_M2, 92 },
|
|
{ PseudoVANDN_VX_M4, 93 },
|
|
{ PseudoVANDN_VX_M8, 94 },
|
|
{ PseudoVANDN_VX_MF2, 95 },
|
|
{ PseudoVANDN_VX_MF4, 96 },
|
|
{ PseudoVANDN_VX_MF8, 97 },
|
|
{ PseudoVAND_VI_M1, 98 },
|
|
{ PseudoVAND_VI_M2, 99 },
|
|
{ PseudoVAND_VI_M4, 100 },
|
|
{ PseudoVAND_VI_M8, 101 },
|
|
{ PseudoVAND_VI_MF2, 102 },
|
|
{ PseudoVAND_VI_MF4, 103 },
|
|
{ PseudoVAND_VI_MF8, 104 },
|
|
{ PseudoVAND_VV_M1, 105 },
|
|
{ PseudoVAND_VV_M2, 106 },
|
|
{ PseudoVAND_VV_M4, 107 },
|
|
{ PseudoVAND_VV_M8, 108 },
|
|
{ PseudoVAND_VV_MF2, 109 },
|
|
{ PseudoVAND_VV_MF4, 110 },
|
|
{ PseudoVAND_VV_MF8, 111 },
|
|
{ PseudoVAND_VX_M1, 112 },
|
|
{ PseudoVAND_VX_M2, 113 },
|
|
{ PseudoVAND_VX_M4, 114 },
|
|
{ PseudoVAND_VX_M8, 115 },
|
|
{ PseudoVAND_VX_MF2, 116 },
|
|
{ PseudoVAND_VX_MF4, 117 },
|
|
{ PseudoVAND_VX_MF8, 118 },
|
|
{ PseudoVASUBU_VV_M1, 119 },
|
|
{ PseudoVASUBU_VV_M2, 120 },
|
|
{ PseudoVASUBU_VV_M4, 121 },
|
|
{ PseudoVASUBU_VV_M8, 122 },
|
|
{ PseudoVASUBU_VV_MF2, 123 },
|
|
{ PseudoVASUBU_VV_MF4, 124 },
|
|
{ PseudoVASUBU_VV_MF8, 125 },
|
|
{ PseudoVASUBU_VX_M1, 126 },
|
|
{ PseudoVASUBU_VX_M2, 127 },
|
|
{ PseudoVASUBU_VX_M4, 128 },
|
|
{ PseudoVASUBU_VX_M8, 129 },
|
|
{ PseudoVASUBU_VX_MF2, 130 },
|
|
{ PseudoVASUBU_VX_MF4, 131 },
|
|
{ PseudoVASUBU_VX_MF8, 132 },
|
|
{ PseudoVASUB_VV_M1, 133 },
|
|
{ PseudoVASUB_VV_M2, 134 },
|
|
{ PseudoVASUB_VV_M4, 135 },
|
|
{ PseudoVASUB_VV_M8, 136 },
|
|
{ PseudoVASUB_VV_MF2, 137 },
|
|
{ PseudoVASUB_VV_MF4, 138 },
|
|
{ PseudoVASUB_VV_MF8, 139 },
|
|
{ PseudoVASUB_VX_M1, 140 },
|
|
{ PseudoVASUB_VX_M2, 141 },
|
|
{ PseudoVASUB_VX_M4, 142 },
|
|
{ PseudoVASUB_VX_M8, 143 },
|
|
{ PseudoVASUB_VX_MF2, 144 },
|
|
{ PseudoVASUB_VX_MF4, 145 },
|
|
{ PseudoVASUB_VX_MF8, 146 },
|
|
{ PseudoVBREV8_V_M1, 147 },
|
|
{ PseudoVBREV8_V_M2, 148 },
|
|
{ PseudoVBREV8_V_M4, 149 },
|
|
{ PseudoVBREV8_V_M8, 150 },
|
|
{ PseudoVBREV8_V_MF2, 151 },
|
|
{ PseudoVBREV8_V_MF4, 152 },
|
|
{ PseudoVBREV8_V_MF8, 153 },
|
|
{ PseudoVBREV_V_M1, 154 },
|
|
{ PseudoVBREV_V_M2, 155 },
|
|
{ PseudoVBREV_V_M4, 156 },
|
|
{ PseudoVBREV_V_M8, 157 },
|
|
{ PseudoVBREV_V_MF2, 158 },
|
|
{ PseudoVBREV_V_MF4, 159 },
|
|
{ PseudoVBREV_V_MF8, 160 },
|
|
{ PseudoVCLMULH_VV_M1, 161 },
|
|
{ PseudoVCLMULH_VV_M2, 162 },
|
|
{ PseudoVCLMULH_VV_M4, 163 },
|
|
{ PseudoVCLMULH_VV_M8, 164 },
|
|
{ PseudoVCLMULH_VV_MF2, 165 },
|
|
{ PseudoVCLMULH_VV_MF4, 166 },
|
|
{ PseudoVCLMULH_VV_MF8, 167 },
|
|
{ PseudoVCLMULH_VX_M1, 168 },
|
|
{ PseudoVCLMULH_VX_M2, 169 },
|
|
{ PseudoVCLMULH_VX_M4, 170 },
|
|
{ PseudoVCLMULH_VX_M8, 171 },
|
|
{ PseudoVCLMULH_VX_MF2, 172 },
|
|
{ PseudoVCLMULH_VX_MF4, 173 },
|
|
{ PseudoVCLMULH_VX_MF8, 174 },
|
|
{ PseudoVCLMUL_VV_M1, 175 },
|
|
{ PseudoVCLMUL_VV_M2, 176 },
|
|
{ PseudoVCLMUL_VV_M4, 177 },
|
|
{ PseudoVCLMUL_VV_M8, 178 },
|
|
{ PseudoVCLMUL_VV_MF2, 179 },
|
|
{ PseudoVCLMUL_VV_MF4, 180 },
|
|
{ PseudoVCLMUL_VV_MF8, 181 },
|
|
{ PseudoVCLMUL_VX_M1, 182 },
|
|
{ PseudoVCLMUL_VX_M2, 183 },
|
|
{ PseudoVCLMUL_VX_M4, 184 },
|
|
{ PseudoVCLMUL_VX_M8, 185 },
|
|
{ PseudoVCLMUL_VX_MF2, 186 },
|
|
{ PseudoVCLMUL_VX_MF4, 187 },
|
|
{ PseudoVCLMUL_VX_MF8, 188 },
|
|
{ PseudoVCLZ_V_M1, 189 },
|
|
{ PseudoVCLZ_V_M2, 190 },
|
|
{ PseudoVCLZ_V_M4, 191 },
|
|
{ PseudoVCLZ_V_M8, 192 },
|
|
{ PseudoVCLZ_V_MF2, 193 },
|
|
{ PseudoVCLZ_V_MF4, 194 },
|
|
{ PseudoVCLZ_V_MF8, 195 },
|
|
{ PseudoVCPOP_V_M1, 196 },
|
|
{ PseudoVCPOP_V_M2, 197 },
|
|
{ PseudoVCPOP_V_M4, 198 },
|
|
{ PseudoVCPOP_V_M8, 199 },
|
|
{ PseudoVCPOP_V_MF2, 200 },
|
|
{ PseudoVCPOP_V_MF4, 201 },
|
|
{ PseudoVCPOP_V_MF8, 202 },
|
|
{ PseudoVCTZ_V_M1, 203 },
|
|
{ PseudoVCTZ_V_M2, 204 },
|
|
{ PseudoVCTZ_V_M4, 205 },
|
|
{ PseudoVCTZ_V_M8, 206 },
|
|
{ PseudoVCTZ_V_MF2, 207 },
|
|
{ PseudoVCTZ_V_MF4, 208 },
|
|
{ PseudoVCTZ_V_MF8, 209 },
|
|
{ PseudoVDIVU_VV_M1_E16, 210 },
|
|
{ PseudoVDIVU_VV_M1_E32, 211 },
|
|
{ PseudoVDIVU_VV_M1_E64, 212 },
|
|
{ PseudoVDIVU_VV_M1_E8, 213 },
|
|
{ PseudoVDIVU_VV_M2_E16, 214 },
|
|
{ PseudoVDIVU_VV_M2_E32, 215 },
|
|
{ PseudoVDIVU_VV_M2_E64, 216 },
|
|
{ PseudoVDIVU_VV_M2_E8, 217 },
|
|
{ PseudoVDIVU_VV_M4_E16, 218 },
|
|
{ PseudoVDIVU_VV_M4_E32, 219 },
|
|
{ PseudoVDIVU_VV_M4_E64, 220 },
|
|
{ PseudoVDIVU_VV_M4_E8, 221 },
|
|
{ PseudoVDIVU_VV_M8_E16, 222 },
|
|
{ PseudoVDIVU_VV_M8_E32, 223 },
|
|
{ PseudoVDIVU_VV_M8_E64, 224 },
|
|
{ PseudoVDIVU_VV_M8_E8, 225 },
|
|
{ PseudoVDIVU_VV_MF2_E16, 226 },
|
|
{ PseudoVDIVU_VV_MF2_E32, 227 },
|
|
{ PseudoVDIVU_VV_MF2_E8, 228 },
|
|
{ PseudoVDIVU_VV_MF4_E16, 229 },
|
|
{ PseudoVDIVU_VV_MF4_E8, 230 },
|
|
{ PseudoVDIVU_VV_MF8_E8, 231 },
|
|
{ PseudoVDIVU_VX_M1_E16, 232 },
|
|
{ PseudoVDIVU_VX_M1_E32, 233 },
|
|
{ PseudoVDIVU_VX_M1_E64, 234 },
|
|
{ PseudoVDIVU_VX_M1_E8, 235 },
|
|
{ PseudoVDIVU_VX_M2_E16, 236 },
|
|
{ PseudoVDIVU_VX_M2_E32, 237 },
|
|
{ PseudoVDIVU_VX_M2_E64, 238 },
|
|
{ PseudoVDIVU_VX_M2_E8, 239 },
|
|
{ PseudoVDIVU_VX_M4_E16, 240 },
|
|
{ PseudoVDIVU_VX_M4_E32, 241 },
|
|
{ PseudoVDIVU_VX_M4_E64, 242 },
|
|
{ PseudoVDIVU_VX_M4_E8, 243 },
|
|
{ PseudoVDIVU_VX_M8_E16, 244 },
|
|
{ PseudoVDIVU_VX_M8_E32, 245 },
|
|
{ PseudoVDIVU_VX_M8_E64, 246 },
|
|
{ PseudoVDIVU_VX_M8_E8, 247 },
|
|
{ PseudoVDIVU_VX_MF2_E16, 248 },
|
|
{ PseudoVDIVU_VX_MF2_E32, 249 },
|
|
{ PseudoVDIVU_VX_MF2_E8, 250 },
|
|
{ PseudoVDIVU_VX_MF4_E16, 251 },
|
|
{ PseudoVDIVU_VX_MF4_E8, 252 },
|
|
{ PseudoVDIVU_VX_MF8_E8, 253 },
|
|
{ PseudoVDIV_VV_M1_E16, 254 },
|
|
{ PseudoVDIV_VV_M1_E32, 255 },
|
|
{ PseudoVDIV_VV_M1_E64, 256 },
|
|
{ PseudoVDIV_VV_M1_E8, 257 },
|
|
{ PseudoVDIV_VV_M2_E16, 258 },
|
|
{ PseudoVDIV_VV_M2_E32, 259 },
|
|
{ PseudoVDIV_VV_M2_E64, 260 },
|
|
{ PseudoVDIV_VV_M2_E8, 261 },
|
|
{ PseudoVDIV_VV_M4_E16, 262 },
|
|
{ PseudoVDIV_VV_M4_E32, 263 },
|
|
{ PseudoVDIV_VV_M4_E64, 264 },
|
|
{ PseudoVDIV_VV_M4_E8, 265 },
|
|
{ PseudoVDIV_VV_M8_E16, 266 },
|
|
{ PseudoVDIV_VV_M8_E32, 267 },
|
|
{ PseudoVDIV_VV_M8_E64, 268 },
|
|
{ PseudoVDIV_VV_M8_E8, 269 },
|
|
{ PseudoVDIV_VV_MF2_E16, 270 },
|
|
{ PseudoVDIV_VV_MF2_E32, 271 },
|
|
{ PseudoVDIV_VV_MF2_E8, 272 },
|
|
{ PseudoVDIV_VV_MF4_E16, 273 },
|
|
{ PseudoVDIV_VV_MF4_E8, 274 },
|
|
{ PseudoVDIV_VV_MF8_E8, 275 },
|
|
{ PseudoVDIV_VX_M1_E16, 276 },
|
|
{ PseudoVDIV_VX_M1_E32, 277 },
|
|
{ PseudoVDIV_VX_M1_E64, 278 },
|
|
{ PseudoVDIV_VX_M1_E8, 279 },
|
|
{ PseudoVDIV_VX_M2_E16, 280 },
|
|
{ PseudoVDIV_VX_M2_E32, 281 },
|
|
{ PseudoVDIV_VX_M2_E64, 282 },
|
|
{ PseudoVDIV_VX_M2_E8, 283 },
|
|
{ PseudoVDIV_VX_M4_E16, 284 },
|
|
{ PseudoVDIV_VX_M4_E32, 285 },
|
|
{ PseudoVDIV_VX_M4_E64, 286 },
|
|
{ PseudoVDIV_VX_M4_E8, 287 },
|
|
{ PseudoVDIV_VX_M8_E16, 288 },
|
|
{ PseudoVDIV_VX_M8_E32, 289 },
|
|
{ PseudoVDIV_VX_M8_E64, 290 },
|
|
{ PseudoVDIV_VX_M8_E8, 291 },
|
|
{ PseudoVDIV_VX_MF2_E16, 292 },
|
|
{ PseudoVDIV_VX_MF2_E32, 293 },
|
|
{ PseudoVDIV_VX_MF2_E8, 294 },
|
|
{ PseudoVDIV_VX_MF4_E16, 295 },
|
|
{ PseudoVDIV_VX_MF4_E8, 296 },
|
|
{ PseudoVDIV_VX_MF8_E8, 297 },
|
|
{ PseudoVFADD_VFPR16_M1, 298 },
|
|
{ PseudoVFADD_VFPR16_M2, 299 },
|
|
{ PseudoVFADD_VFPR16_M4, 300 },
|
|
{ PseudoVFADD_VFPR16_M8, 301 },
|
|
{ PseudoVFADD_VFPR16_MF2, 302 },
|
|
{ PseudoVFADD_VFPR16_MF4, 303 },
|
|
{ PseudoVFADD_VFPR32_M1, 304 },
|
|
{ PseudoVFADD_VFPR32_M2, 305 },
|
|
{ PseudoVFADD_VFPR32_M4, 306 },
|
|
{ PseudoVFADD_VFPR32_M8, 307 },
|
|
{ PseudoVFADD_VFPR32_MF2, 308 },
|
|
{ PseudoVFADD_VFPR64_M1, 309 },
|
|
{ PseudoVFADD_VFPR64_M2, 310 },
|
|
{ PseudoVFADD_VFPR64_M4, 311 },
|
|
{ PseudoVFADD_VFPR64_M8, 312 },
|
|
{ PseudoVFADD_VV_M1, 313 },
|
|
{ PseudoVFADD_VV_M2, 314 },
|
|
{ PseudoVFADD_VV_M4, 315 },
|
|
{ PseudoVFADD_VV_M8, 316 },
|
|
{ PseudoVFADD_VV_MF2, 317 },
|
|
{ PseudoVFADD_VV_MF4, 318 },
|
|
{ PseudoVFCLASS_V_M1, 319 },
|
|
{ PseudoVFCLASS_V_M2, 320 },
|
|
{ PseudoVFCLASS_V_M4, 321 },
|
|
{ PseudoVFCLASS_V_M8, 322 },
|
|
{ PseudoVFCLASS_V_MF2, 323 },
|
|
{ PseudoVFCLASS_V_MF4, 324 },
|
|
{ PseudoVFCVT_F_XU_V_M1, 325 },
|
|
{ PseudoVFCVT_F_XU_V_M2, 326 },
|
|
{ PseudoVFCVT_F_XU_V_M4, 327 },
|
|
{ PseudoVFCVT_F_XU_V_M8, 328 },
|
|
{ PseudoVFCVT_F_XU_V_MF2, 329 },
|
|
{ PseudoVFCVT_F_XU_V_MF4, 330 },
|
|
{ PseudoVFCVT_F_X_V_M1, 331 },
|
|
{ PseudoVFCVT_F_X_V_M2, 332 },
|
|
{ PseudoVFCVT_F_X_V_M4, 333 },
|
|
{ PseudoVFCVT_F_X_V_M8, 334 },
|
|
{ PseudoVFCVT_F_X_V_MF2, 335 },
|
|
{ PseudoVFCVT_F_X_V_MF4, 336 },
|
|
{ PseudoVFCVT_RM_F_XU_V_M1, 337 },
|
|
{ PseudoVFCVT_RM_F_XU_V_M2, 338 },
|
|
{ PseudoVFCVT_RM_F_XU_V_M4, 339 },
|
|
{ PseudoVFCVT_RM_F_XU_V_M8, 340 },
|
|
{ PseudoVFCVT_RM_F_XU_V_MF2, 341 },
|
|
{ PseudoVFCVT_RM_F_XU_V_MF4, 342 },
|
|
{ PseudoVFCVT_RM_F_X_V_M1, 343 },
|
|
{ PseudoVFCVT_RM_F_X_V_M2, 344 },
|
|
{ PseudoVFCVT_RM_F_X_V_M4, 345 },
|
|
{ PseudoVFCVT_RM_F_X_V_M8, 346 },
|
|
{ PseudoVFCVT_RM_F_X_V_MF2, 347 },
|
|
{ PseudoVFCVT_RM_F_X_V_MF4, 348 },
|
|
{ PseudoVFCVT_RM_XU_F_V_M1, 349 },
|
|
{ PseudoVFCVT_RM_XU_F_V_M2, 350 },
|
|
{ PseudoVFCVT_RM_XU_F_V_M4, 351 },
|
|
{ PseudoVFCVT_RM_XU_F_V_M8, 352 },
|
|
{ PseudoVFCVT_RM_XU_F_V_MF2, 353 },
|
|
{ PseudoVFCVT_RM_XU_F_V_MF4, 354 },
|
|
{ PseudoVFCVT_RM_X_F_V_M1, 355 },
|
|
{ PseudoVFCVT_RM_X_F_V_M2, 356 },
|
|
{ PseudoVFCVT_RM_X_F_V_M4, 357 },
|
|
{ PseudoVFCVT_RM_X_F_V_M8, 358 },
|
|
{ PseudoVFCVT_RM_X_F_V_MF2, 359 },
|
|
{ PseudoVFCVT_RM_X_F_V_MF4, 360 },
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M1, 361 },
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M2, 362 },
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M4, 363 },
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M8, 364 },
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF2, 365 },
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF4, 366 },
|
|
{ PseudoVFCVT_RTZ_X_F_V_M1, 367 },
|
|
{ PseudoVFCVT_RTZ_X_F_V_M2, 368 },
|
|
{ PseudoVFCVT_RTZ_X_F_V_M4, 369 },
|
|
{ PseudoVFCVT_RTZ_X_F_V_M8, 370 },
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF2, 371 },
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF4, 372 },
|
|
{ PseudoVFCVT_XU_F_V_M1, 373 },
|
|
{ PseudoVFCVT_XU_F_V_M2, 374 },
|
|
{ PseudoVFCVT_XU_F_V_M4, 375 },
|
|
{ PseudoVFCVT_XU_F_V_M8, 376 },
|
|
{ PseudoVFCVT_XU_F_V_MF2, 377 },
|
|
{ PseudoVFCVT_XU_F_V_MF4, 378 },
|
|
{ PseudoVFCVT_X_F_V_M1, 379 },
|
|
{ PseudoVFCVT_X_F_V_M2, 380 },
|
|
{ PseudoVFCVT_X_F_V_M4, 381 },
|
|
{ PseudoVFCVT_X_F_V_M8, 382 },
|
|
{ PseudoVFCVT_X_F_V_MF2, 383 },
|
|
{ PseudoVFCVT_X_F_V_MF4, 384 },
|
|
{ PseudoVFDIV_VFPR16_M1_E16, 385 },
|
|
{ PseudoVFDIV_VFPR16_M2_E16, 386 },
|
|
{ PseudoVFDIV_VFPR16_M4_E16, 387 },
|
|
{ PseudoVFDIV_VFPR16_M8_E16, 388 },
|
|
{ PseudoVFDIV_VFPR16_MF2_E16, 389 },
|
|
{ PseudoVFDIV_VFPR16_MF4_E16, 390 },
|
|
{ PseudoVFDIV_VFPR32_M1_E32, 391 },
|
|
{ PseudoVFDIV_VFPR32_M2_E32, 392 },
|
|
{ PseudoVFDIV_VFPR32_M4_E32, 393 },
|
|
{ PseudoVFDIV_VFPR32_M8_E32, 394 },
|
|
{ PseudoVFDIV_VFPR32_MF2_E32, 395 },
|
|
{ PseudoVFDIV_VFPR64_M1_E64, 396 },
|
|
{ PseudoVFDIV_VFPR64_M2_E64, 397 },
|
|
{ PseudoVFDIV_VFPR64_M4_E64, 398 },
|
|
{ PseudoVFDIV_VFPR64_M8_E64, 399 },
|
|
{ PseudoVFDIV_VV_M1_E16, 400 },
|
|
{ PseudoVFDIV_VV_M1_E32, 401 },
|
|
{ PseudoVFDIV_VV_M1_E64, 402 },
|
|
{ PseudoVFDIV_VV_M2_E16, 403 },
|
|
{ PseudoVFDIV_VV_M2_E32, 404 },
|
|
{ PseudoVFDIV_VV_M2_E64, 405 },
|
|
{ PseudoVFDIV_VV_M4_E16, 406 },
|
|
{ PseudoVFDIV_VV_M4_E32, 407 },
|
|
{ PseudoVFDIV_VV_M4_E64, 408 },
|
|
{ PseudoVFDIV_VV_M8_E16, 409 },
|
|
{ PseudoVFDIV_VV_M8_E32, 410 },
|
|
{ PseudoVFDIV_VV_M8_E64, 411 },
|
|
{ PseudoVFDIV_VV_MF2_E16, 412 },
|
|
{ PseudoVFDIV_VV_MF2_E32, 413 },
|
|
{ PseudoVFDIV_VV_MF4_E16, 414 },
|
|
{ PseudoVFMACC_VFPR16_M1, 415 },
|
|
{ PseudoVFMACC_VFPR16_M2, 416 },
|
|
{ PseudoVFMACC_VFPR16_M4, 417 },
|
|
{ PseudoVFMACC_VFPR16_M8, 418 },
|
|
{ PseudoVFMACC_VFPR16_MF2, 419 },
|
|
{ PseudoVFMACC_VFPR16_MF4, 420 },
|
|
{ PseudoVFMACC_VFPR32_M1, 421 },
|
|
{ PseudoVFMACC_VFPR32_M2, 422 },
|
|
{ PseudoVFMACC_VFPR32_M4, 423 },
|
|
{ PseudoVFMACC_VFPR32_M8, 424 },
|
|
{ PseudoVFMACC_VFPR32_MF2, 425 },
|
|
{ PseudoVFMACC_VFPR64_M1, 426 },
|
|
{ PseudoVFMACC_VFPR64_M2, 427 },
|
|
{ PseudoVFMACC_VFPR64_M4, 428 },
|
|
{ PseudoVFMACC_VFPR64_M8, 429 },
|
|
{ PseudoVFMACC_VV_M1, 430 },
|
|
{ PseudoVFMACC_VV_M2, 431 },
|
|
{ PseudoVFMACC_VV_M4, 432 },
|
|
{ PseudoVFMACC_VV_M8, 433 },
|
|
{ PseudoVFMACC_VV_MF2, 434 },
|
|
{ PseudoVFMACC_VV_MF4, 435 },
|
|
{ PseudoVFMADD_VFPR16_M1, 436 },
|
|
{ PseudoVFMADD_VFPR16_M2, 437 },
|
|
{ PseudoVFMADD_VFPR16_M4, 438 },
|
|
{ PseudoVFMADD_VFPR16_M8, 439 },
|
|
{ PseudoVFMADD_VFPR16_MF2, 440 },
|
|
{ PseudoVFMADD_VFPR16_MF4, 441 },
|
|
{ PseudoVFMADD_VFPR32_M1, 442 },
|
|
{ PseudoVFMADD_VFPR32_M2, 443 },
|
|
{ PseudoVFMADD_VFPR32_M4, 444 },
|
|
{ PseudoVFMADD_VFPR32_M8, 445 },
|
|
{ PseudoVFMADD_VFPR32_MF2, 446 },
|
|
{ PseudoVFMADD_VFPR64_M1, 447 },
|
|
{ PseudoVFMADD_VFPR64_M2, 448 },
|
|
{ PseudoVFMADD_VFPR64_M4, 449 },
|
|
{ PseudoVFMADD_VFPR64_M8, 450 },
|
|
{ PseudoVFMADD_VV_M1, 451 },
|
|
{ PseudoVFMADD_VV_M2, 452 },
|
|
{ PseudoVFMADD_VV_M4, 453 },
|
|
{ PseudoVFMADD_VV_M8, 454 },
|
|
{ PseudoVFMADD_VV_MF2, 455 },
|
|
{ PseudoVFMADD_VV_MF4, 456 },
|
|
{ PseudoVFMAX_VFPR16_M1, 457 },
|
|
{ PseudoVFMAX_VFPR16_M2, 458 },
|
|
{ PseudoVFMAX_VFPR16_M4, 459 },
|
|
{ PseudoVFMAX_VFPR16_M8, 460 },
|
|
{ PseudoVFMAX_VFPR16_MF2, 461 },
|
|
{ PseudoVFMAX_VFPR16_MF4, 462 },
|
|
{ PseudoVFMAX_VFPR32_M1, 463 },
|
|
{ PseudoVFMAX_VFPR32_M2, 464 },
|
|
{ PseudoVFMAX_VFPR32_M4, 465 },
|
|
{ PseudoVFMAX_VFPR32_M8, 466 },
|
|
{ PseudoVFMAX_VFPR32_MF2, 467 },
|
|
{ PseudoVFMAX_VFPR64_M1, 468 },
|
|
{ PseudoVFMAX_VFPR64_M2, 469 },
|
|
{ PseudoVFMAX_VFPR64_M4, 470 },
|
|
{ PseudoVFMAX_VFPR64_M8, 471 },
|
|
{ PseudoVFMAX_VV_M1, 472 },
|
|
{ PseudoVFMAX_VV_M2, 473 },
|
|
{ PseudoVFMAX_VV_M4, 474 },
|
|
{ PseudoVFMAX_VV_M8, 475 },
|
|
{ PseudoVFMAX_VV_MF2, 476 },
|
|
{ PseudoVFMAX_VV_MF4, 477 },
|
|
{ PseudoVFMIN_VFPR16_M1, 478 },
|
|
{ PseudoVFMIN_VFPR16_M2, 479 },
|
|
{ PseudoVFMIN_VFPR16_M4, 480 },
|
|
{ PseudoVFMIN_VFPR16_M8, 481 },
|
|
{ PseudoVFMIN_VFPR16_MF2, 482 },
|
|
{ PseudoVFMIN_VFPR16_MF4, 483 },
|
|
{ PseudoVFMIN_VFPR32_M1, 484 },
|
|
{ PseudoVFMIN_VFPR32_M2, 485 },
|
|
{ PseudoVFMIN_VFPR32_M4, 486 },
|
|
{ PseudoVFMIN_VFPR32_M8, 487 },
|
|
{ PseudoVFMIN_VFPR32_MF2, 488 },
|
|
{ PseudoVFMIN_VFPR64_M1, 489 },
|
|
{ PseudoVFMIN_VFPR64_M2, 490 },
|
|
{ PseudoVFMIN_VFPR64_M4, 491 },
|
|
{ PseudoVFMIN_VFPR64_M8, 492 },
|
|
{ PseudoVFMIN_VV_M1, 493 },
|
|
{ PseudoVFMIN_VV_M2, 494 },
|
|
{ PseudoVFMIN_VV_M4, 495 },
|
|
{ PseudoVFMIN_VV_M8, 496 },
|
|
{ PseudoVFMIN_VV_MF2, 497 },
|
|
{ PseudoVFMIN_VV_MF4, 498 },
|
|
{ PseudoVFMSAC_VFPR16_M1, 499 },
|
|
{ PseudoVFMSAC_VFPR16_M2, 500 },
|
|
{ PseudoVFMSAC_VFPR16_M4, 501 },
|
|
{ PseudoVFMSAC_VFPR16_M8, 502 },
|
|
{ PseudoVFMSAC_VFPR16_MF2, 503 },
|
|
{ PseudoVFMSAC_VFPR16_MF4, 504 },
|
|
{ PseudoVFMSAC_VFPR32_M1, 505 },
|
|
{ PseudoVFMSAC_VFPR32_M2, 506 },
|
|
{ PseudoVFMSAC_VFPR32_M4, 507 },
|
|
{ PseudoVFMSAC_VFPR32_M8, 508 },
|
|
{ PseudoVFMSAC_VFPR32_MF2, 509 },
|
|
{ PseudoVFMSAC_VFPR64_M1, 510 },
|
|
{ PseudoVFMSAC_VFPR64_M2, 511 },
|
|
{ PseudoVFMSAC_VFPR64_M4, 512 },
|
|
{ PseudoVFMSAC_VFPR64_M8, 513 },
|
|
{ PseudoVFMSAC_VV_M1, 514 },
|
|
{ PseudoVFMSAC_VV_M2, 515 },
|
|
{ PseudoVFMSAC_VV_M4, 516 },
|
|
{ PseudoVFMSAC_VV_M8, 517 },
|
|
{ PseudoVFMSAC_VV_MF2, 518 },
|
|
{ PseudoVFMSAC_VV_MF4, 519 },
|
|
{ PseudoVFMSUB_VFPR16_M1, 520 },
|
|
{ PseudoVFMSUB_VFPR16_M2, 521 },
|
|
{ PseudoVFMSUB_VFPR16_M4, 522 },
|
|
{ PseudoVFMSUB_VFPR16_M8, 523 },
|
|
{ PseudoVFMSUB_VFPR16_MF2, 524 },
|
|
{ PseudoVFMSUB_VFPR16_MF4, 525 },
|
|
{ PseudoVFMSUB_VFPR32_M1, 526 },
|
|
{ PseudoVFMSUB_VFPR32_M2, 527 },
|
|
{ PseudoVFMSUB_VFPR32_M4, 528 },
|
|
{ PseudoVFMSUB_VFPR32_M8, 529 },
|
|
{ PseudoVFMSUB_VFPR32_MF2, 530 },
|
|
{ PseudoVFMSUB_VFPR64_M1, 531 },
|
|
{ PseudoVFMSUB_VFPR64_M2, 532 },
|
|
{ PseudoVFMSUB_VFPR64_M4, 533 },
|
|
{ PseudoVFMSUB_VFPR64_M8, 534 },
|
|
{ PseudoVFMSUB_VV_M1, 535 },
|
|
{ PseudoVFMSUB_VV_M2, 536 },
|
|
{ PseudoVFMSUB_VV_M4, 537 },
|
|
{ PseudoVFMSUB_VV_M8, 538 },
|
|
{ PseudoVFMSUB_VV_MF2, 539 },
|
|
{ PseudoVFMSUB_VV_MF4, 540 },
|
|
{ PseudoVFMUL_VFPR16_M1, 541 },
|
|
{ PseudoVFMUL_VFPR16_M2, 542 },
|
|
{ PseudoVFMUL_VFPR16_M4, 543 },
|
|
{ PseudoVFMUL_VFPR16_M8, 544 },
|
|
{ PseudoVFMUL_VFPR16_MF2, 545 },
|
|
{ PseudoVFMUL_VFPR16_MF4, 546 },
|
|
{ PseudoVFMUL_VFPR32_M1, 547 },
|
|
{ PseudoVFMUL_VFPR32_M2, 548 },
|
|
{ PseudoVFMUL_VFPR32_M4, 549 },
|
|
{ PseudoVFMUL_VFPR32_M8, 550 },
|
|
{ PseudoVFMUL_VFPR32_MF2, 551 },
|
|
{ PseudoVFMUL_VFPR64_M1, 552 },
|
|
{ PseudoVFMUL_VFPR64_M2, 553 },
|
|
{ PseudoVFMUL_VFPR64_M4, 554 },
|
|
{ PseudoVFMUL_VFPR64_M8, 555 },
|
|
{ PseudoVFMUL_VV_M1, 556 },
|
|
{ PseudoVFMUL_VV_M2, 557 },
|
|
{ PseudoVFMUL_VV_M4, 558 },
|
|
{ PseudoVFMUL_VV_M8, 559 },
|
|
{ PseudoVFMUL_VV_MF2, 560 },
|
|
{ PseudoVFMUL_VV_MF4, 561 },
|
|
{ PseudoVFNCVTBF16_F_F_W_M1, 562 },
|
|
{ PseudoVFNCVTBF16_F_F_W_M2, 563 },
|
|
{ PseudoVFNCVTBF16_F_F_W_M4, 564 },
|
|
{ PseudoVFNCVTBF16_F_F_W_MF2, 565 },
|
|
{ PseudoVFNCVTBF16_F_F_W_MF4, 566 },
|
|
{ PseudoVFNCVT_F_F_W_M1, 567 },
|
|
{ PseudoVFNCVT_F_F_W_M2, 568 },
|
|
{ PseudoVFNCVT_F_F_W_M4, 569 },
|
|
{ PseudoVFNCVT_F_F_W_MF2, 570 },
|
|
{ PseudoVFNCVT_F_F_W_MF4, 571 },
|
|
{ PseudoVFNCVT_F_XU_W_M1, 572 },
|
|
{ PseudoVFNCVT_F_XU_W_M2, 573 },
|
|
{ PseudoVFNCVT_F_XU_W_M4, 574 },
|
|
{ PseudoVFNCVT_F_XU_W_MF2, 575 },
|
|
{ PseudoVFNCVT_F_XU_W_MF4, 576 },
|
|
{ PseudoVFNCVT_F_X_W_M1, 577 },
|
|
{ PseudoVFNCVT_F_X_W_M2, 578 },
|
|
{ PseudoVFNCVT_F_X_W_M4, 579 },
|
|
{ PseudoVFNCVT_F_X_W_MF2, 580 },
|
|
{ PseudoVFNCVT_F_X_W_MF4, 581 },
|
|
{ PseudoVFNCVT_RM_F_XU_W_M1, 582 },
|
|
{ PseudoVFNCVT_RM_F_XU_W_M2, 583 },
|
|
{ PseudoVFNCVT_RM_F_XU_W_M4, 584 },
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF2, 585 },
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF4, 586 },
|
|
{ PseudoVFNCVT_RM_F_X_W_M1, 587 },
|
|
{ PseudoVFNCVT_RM_F_X_W_M2, 588 },
|
|
{ PseudoVFNCVT_RM_F_X_W_M4, 589 },
|
|
{ PseudoVFNCVT_RM_F_X_W_MF2, 590 },
|
|
{ PseudoVFNCVT_RM_F_X_W_MF4, 591 },
|
|
{ PseudoVFNCVT_RM_XU_F_W_M1, 592 },
|
|
{ PseudoVFNCVT_RM_XU_F_W_M2, 593 },
|
|
{ PseudoVFNCVT_RM_XU_F_W_M4, 594 },
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF2, 595 },
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF4, 596 },
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF8, 597 },
|
|
{ PseudoVFNCVT_RM_X_F_W_M1, 598 },
|
|
{ PseudoVFNCVT_RM_X_F_W_M2, 599 },
|
|
{ PseudoVFNCVT_RM_X_F_W_M4, 600 },
|
|
{ PseudoVFNCVT_RM_X_F_W_MF2, 601 },
|
|
{ PseudoVFNCVT_RM_X_F_W_MF4, 602 },
|
|
{ PseudoVFNCVT_RM_X_F_W_MF8, 603 },
|
|
{ PseudoVFNCVT_ROD_F_F_W_M1, 604 },
|
|
{ PseudoVFNCVT_ROD_F_F_W_M2, 605 },
|
|
{ PseudoVFNCVT_ROD_F_F_W_M4, 606 },
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF2, 607 },
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF4, 608 },
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M1, 609 },
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M2, 610 },
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M4, 611 },
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF2, 612 },
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF4, 613 },
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF8, 614 },
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M1, 615 },
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M2, 616 },
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M4, 617 },
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF2, 618 },
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF4, 619 },
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF8, 620 },
|
|
{ PseudoVFNCVT_XU_F_W_M1, 621 },
|
|
{ PseudoVFNCVT_XU_F_W_M2, 622 },
|
|
{ PseudoVFNCVT_XU_F_W_M4, 623 },
|
|
{ PseudoVFNCVT_XU_F_W_MF2, 624 },
|
|
{ PseudoVFNCVT_XU_F_W_MF4, 625 },
|
|
{ PseudoVFNCVT_XU_F_W_MF8, 626 },
|
|
{ PseudoVFNCVT_X_F_W_M1, 627 },
|
|
{ PseudoVFNCVT_X_F_W_M2, 628 },
|
|
{ PseudoVFNCVT_X_F_W_M4, 629 },
|
|
{ PseudoVFNCVT_X_F_W_MF2, 630 },
|
|
{ PseudoVFNCVT_X_F_W_MF4, 631 },
|
|
{ PseudoVFNCVT_X_F_W_MF8, 632 },
|
|
{ PseudoVFNMACC_VFPR16_M1, 633 },
|
|
{ PseudoVFNMACC_VFPR16_M2, 634 },
|
|
{ PseudoVFNMACC_VFPR16_M4, 635 },
|
|
{ PseudoVFNMACC_VFPR16_M8, 636 },
|
|
{ PseudoVFNMACC_VFPR16_MF2, 637 },
|
|
{ PseudoVFNMACC_VFPR16_MF4, 638 },
|
|
{ PseudoVFNMACC_VFPR32_M1, 639 },
|
|
{ PseudoVFNMACC_VFPR32_M2, 640 },
|
|
{ PseudoVFNMACC_VFPR32_M4, 641 },
|
|
{ PseudoVFNMACC_VFPR32_M8, 642 },
|
|
{ PseudoVFNMACC_VFPR32_MF2, 643 },
|
|
{ PseudoVFNMACC_VFPR64_M1, 644 },
|
|
{ PseudoVFNMACC_VFPR64_M2, 645 },
|
|
{ PseudoVFNMACC_VFPR64_M4, 646 },
|
|
{ PseudoVFNMACC_VFPR64_M8, 647 },
|
|
{ PseudoVFNMACC_VV_M1, 648 },
|
|
{ PseudoVFNMACC_VV_M2, 649 },
|
|
{ PseudoVFNMACC_VV_M4, 650 },
|
|
{ PseudoVFNMACC_VV_M8, 651 },
|
|
{ PseudoVFNMACC_VV_MF2, 652 },
|
|
{ PseudoVFNMACC_VV_MF4, 653 },
|
|
{ PseudoVFNMADD_VFPR16_M1, 654 },
|
|
{ PseudoVFNMADD_VFPR16_M2, 655 },
|
|
{ PseudoVFNMADD_VFPR16_M4, 656 },
|
|
{ PseudoVFNMADD_VFPR16_M8, 657 },
|
|
{ PseudoVFNMADD_VFPR16_MF2, 658 },
|
|
{ PseudoVFNMADD_VFPR16_MF4, 659 },
|
|
{ PseudoVFNMADD_VFPR32_M1, 660 },
|
|
{ PseudoVFNMADD_VFPR32_M2, 661 },
|
|
{ PseudoVFNMADD_VFPR32_M4, 662 },
|
|
{ PseudoVFNMADD_VFPR32_M8, 663 },
|
|
{ PseudoVFNMADD_VFPR32_MF2, 664 },
|
|
{ PseudoVFNMADD_VFPR64_M1, 665 },
|
|
{ PseudoVFNMADD_VFPR64_M2, 666 },
|
|
{ PseudoVFNMADD_VFPR64_M4, 667 },
|
|
{ PseudoVFNMADD_VFPR64_M8, 668 },
|
|
{ PseudoVFNMADD_VV_M1, 669 },
|
|
{ PseudoVFNMADD_VV_M2, 670 },
|
|
{ PseudoVFNMADD_VV_M4, 671 },
|
|
{ PseudoVFNMADD_VV_M8, 672 },
|
|
{ PseudoVFNMADD_VV_MF2, 673 },
|
|
{ PseudoVFNMADD_VV_MF4, 674 },
|
|
{ PseudoVFNMSAC_VFPR16_M1, 675 },
|
|
{ PseudoVFNMSAC_VFPR16_M2, 676 },
|
|
{ PseudoVFNMSAC_VFPR16_M4, 677 },
|
|
{ PseudoVFNMSAC_VFPR16_M8, 678 },
|
|
{ PseudoVFNMSAC_VFPR16_MF2, 679 },
|
|
{ PseudoVFNMSAC_VFPR16_MF4, 680 },
|
|
{ PseudoVFNMSAC_VFPR32_M1, 681 },
|
|
{ PseudoVFNMSAC_VFPR32_M2, 682 },
|
|
{ PseudoVFNMSAC_VFPR32_M4, 683 },
|
|
{ PseudoVFNMSAC_VFPR32_M8, 684 },
|
|
{ PseudoVFNMSAC_VFPR32_MF2, 685 },
|
|
{ PseudoVFNMSAC_VFPR64_M1, 686 },
|
|
{ PseudoVFNMSAC_VFPR64_M2, 687 },
|
|
{ PseudoVFNMSAC_VFPR64_M4, 688 },
|
|
{ PseudoVFNMSAC_VFPR64_M8, 689 },
|
|
{ PseudoVFNMSAC_VV_M1, 690 },
|
|
{ PseudoVFNMSAC_VV_M2, 691 },
|
|
{ PseudoVFNMSAC_VV_M4, 692 },
|
|
{ PseudoVFNMSAC_VV_M8, 693 },
|
|
{ PseudoVFNMSAC_VV_MF2, 694 },
|
|
{ PseudoVFNMSAC_VV_MF4, 695 },
|
|
{ PseudoVFNMSUB_VFPR16_M1, 696 },
|
|
{ PseudoVFNMSUB_VFPR16_M2, 697 },
|
|
{ PseudoVFNMSUB_VFPR16_M4, 698 },
|
|
{ PseudoVFNMSUB_VFPR16_M8, 699 },
|
|
{ PseudoVFNMSUB_VFPR16_MF2, 700 },
|
|
{ PseudoVFNMSUB_VFPR16_MF4, 701 },
|
|
{ PseudoVFNMSUB_VFPR32_M1, 702 },
|
|
{ PseudoVFNMSUB_VFPR32_M2, 703 },
|
|
{ PseudoVFNMSUB_VFPR32_M4, 704 },
|
|
{ PseudoVFNMSUB_VFPR32_M8, 705 },
|
|
{ PseudoVFNMSUB_VFPR32_MF2, 706 },
|
|
{ PseudoVFNMSUB_VFPR64_M1, 707 },
|
|
{ PseudoVFNMSUB_VFPR64_M2, 708 },
|
|
{ PseudoVFNMSUB_VFPR64_M4, 709 },
|
|
{ PseudoVFNMSUB_VFPR64_M8, 710 },
|
|
{ PseudoVFNMSUB_VV_M1, 711 },
|
|
{ PseudoVFNMSUB_VV_M2, 712 },
|
|
{ PseudoVFNMSUB_VV_M4, 713 },
|
|
{ PseudoVFNMSUB_VV_M8, 714 },
|
|
{ PseudoVFNMSUB_VV_MF2, 715 },
|
|
{ PseudoVFNMSUB_VV_MF4, 716 },
|
|
{ PseudoVFNRCLIP_XU_F_QF_M1, 717 },
|
|
{ PseudoVFNRCLIP_XU_F_QF_M2, 718 },
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF2, 719 },
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF4, 720 },
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF8, 721 },
|
|
{ PseudoVFNRCLIP_X_F_QF_M1, 722 },
|
|
{ PseudoVFNRCLIP_X_F_QF_M2, 723 },
|
|
{ PseudoVFNRCLIP_X_F_QF_MF2, 724 },
|
|
{ PseudoVFNRCLIP_X_F_QF_MF4, 725 },
|
|
{ PseudoVFNRCLIP_X_F_QF_MF8, 726 },
|
|
{ PseudoVFRDIV_VFPR16_M1_E16, 727 },
|
|
{ PseudoVFRDIV_VFPR16_M2_E16, 728 },
|
|
{ PseudoVFRDIV_VFPR16_M4_E16, 729 },
|
|
{ PseudoVFRDIV_VFPR16_M8_E16, 730 },
|
|
{ PseudoVFRDIV_VFPR16_MF2_E16, 731 },
|
|
{ PseudoVFRDIV_VFPR16_MF4_E16, 732 },
|
|
{ PseudoVFRDIV_VFPR32_M1_E32, 733 },
|
|
{ PseudoVFRDIV_VFPR32_M2_E32, 734 },
|
|
{ PseudoVFRDIV_VFPR32_M4_E32, 735 },
|
|
{ PseudoVFRDIV_VFPR32_M8_E32, 736 },
|
|
{ PseudoVFRDIV_VFPR32_MF2_E32, 737 },
|
|
{ PseudoVFRDIV_VFPR64_M1_E64, 738 },
|
|
{ PseudoVFRDIV_VFPR64_M2_E64, 739 },
|
|
{ PseudoVFRDIV_VFPR64_M4_E64, 740 },
|
|
{ PseudoVFRDIV_VFPR64_M8_E64, 741 },
|
|
{ PseudoVFREC7_V_M1, 742 },
|
|
{ PseudoVFREC7_V_M2, 743 },
|
|
{ PseudoVFREC7_V_M4, 744 },
|
|
{ PseudoVFREC7_V_M8, 745 },
|
|
{ PseudoVFREC7_V_MF2, 746 },
|
|
{ PseudoVFREC7_V_MF4, 747 },
|
|
{ PseudoVFREDMAX_VS_M1_E16, 748 },
|
|
{ PseudoVFREDMAX_VS_M1_E32, 749 },
|
|
{ PseudoVFREDMAX_VS_M1_E64, 750 },
|
|
{ PseudoVFREDMAX_VS_M2_E16, 751 },
|
|
{ PseudoVFREDMAX_VS_M2_E32, 752 },
|
|
{ PseudoVFREDMAX_VS_M2_E64, 753 },
|
|
{ PseudoVFREDMAX_VS_M4_E16, 754 },
|
|
{ PseudoVFREDMAX_VS_M4_E32, 755 },
|
|
{ PseudoVFREDMAX_VS_M4_E64, 756 },
|
|
{ PseudoVFREDMAX_VS_M8_E16, 757 },
|
|
{ PseudoVFREDMAX_VS_M8_E32, 758 },
|
|
{ PseudoVFREDMAX_VS_M8_E64, 759 },
|
|
{ PseudoVFREDMAX_VS_MF2_E16, 760 },
|
|
{ PseudoVFREDMAX_VS_MF2_E32, 761 },
|
|
{ PseudoVFREDMAX_VS_MF4_E16, 762 },
|
|
{ PseudoVFREDMIN_VS_M1_E16, 763 },
|
|
{ PseudoVFREDMIN_VS_M1_E32, 764 },
|
|
{ PseudoVFREDMIN_VS_M1_E64, 765 },
|
|
{ PseudoVFREDMIN_VS_M2_E16, 766 },
|
|
{ PseudoVFREDMIN_VS_M2_E32, 767 },
|
|
{ PseudoVFREDMIN_VS_M2_E64, 768 },
|
|
{ PseudoVFREDMIN_VS_M4_E16, 769 },
|
|
{ PseudoVFREDMIN_VS_M4_E32, 770 },
|
|
{ PseudoVFREDMIN_VS_M4_E64, 771 },
|
|
{ PseudoVFREDMIN_VS_M8_E16, 772 },
|
|
{ PseudoVFREDMIN_VS_M8_E32, 773 },
|
|
{ PseudoVFREDMIN_VS_M8_E64, 774 },
|
|
{ PseudoVFREDMIN_VS_MF2_E16, 775 },
|
|
{ PseudoVFREDMIN_VS_MF2_E32, 776 },
|
|
{ PseudoVFREDMIN_VS_MF4_E16, 777 },
|
|
{ PseudoVFREDOSUM_VS_M1_E16, 778 },
|
|
{ PseudoVFREDOSUM_VS_M1_E32, 779 },
|
|
{ PseudoVFREDOSUM_VS_M1_E64, 780 },
|
|
{ PseudoVFREDOSUM_VS_M2_E16, 781 },
|
|
{ PseudoVFREDOSUM_VS_M2_E32, 782 },
|
|
{ PseudoVFREDOSUM_VS_M2_E64, 783 },
|
|
{ PseudoVFREDOSUM_VS_M4_E16, 784 },
|
|
{ PseudoVFREDOSUM_VS_M4_E32, 785 },
|
|
{ PseudoVFREDOSUM_VS_M4_E64, 786 },
|
|
{ PseudoVFREDOSUM_VS_M8_E16, 787 },
|
|
{ PseudoVFREDOSUM_VS_M8_E32, 788 },
|
|
{ PseudoVFREDOSUM_VS_M8_E64, 789 },
|
|
{ PseudoVFREDOSUM_VS_MF2_E16, 790 },
|
|
{ PseudoVFREDOSUM_VS_MF2_E32, 791 },
|
|
{ PseudoVFREDOSUM_VS_MF4_E16, 792 },
|
|
{ PseudoVFREDUSUM_VS_M1_E16, 793 },
|
|
{ PseudoVFREDUSUM_VS_M1_E32, 794 },
|
|
{ PseudoVFREDUSUM_VS_M1_E64, 795 },
|
|
{ PseudoVFREDUSUM_VS_M2_E16, 796 },
|
|
{ PseudoVFREDUSUM_VS_M2_E32, 797 },
|
|
{ PseudoVFREDUSUM_VS_M2_E64, 798 },
|
|
{ PseudoVFREDUSUM_VS_M4_E16, 799 },
|
|
{ PseudoVFREDUSUM_VS_M4_E32, 800 },
|
|
{ PseudoVFREDUSUM_VS_M4_E64, 801 },
|
|
{ PseudoVFREDUSUM_VS_M8_E16, 802 },
|
|
{ PseudoVFREDUSUM_VS_M8_E32, 803 },
|
|
{ PseudoVFREDUSUM_VS_M8_E64, 804 },
|
|
{ PseudoVFREDUSUM_VS_MF2_E16, 805 },
|
|
{ PseudoVFREDUSUM_VS_MF2_E32, 806 },
|
|
{ PseudoVFREDUSUM_VS_MF4_E16, 807 },
|
|
{ PseudoVFRSQRT7_V_M1, 808 },
|
|
{ PseudoVFRSQRT7_V_M2, 809 },
|
|
{ PseudoVFRSQRT7_V_M4, 810 },
|
|
{ PseudoVFRSQRT7_V_M8, 811 },
|
|
{ PseudoVFRSQRT7_V_MF2, 812 },
|
|
{ PseudoVFRSQRT7_V_MF4, 813 },
|
|
{ PseudoVFRSUB_VFPR16_M1, 814 },
|
|
{ PseudoVFRSUB_VFPR16_M2, 815 },
|
|
{ PseudoVFRSUB_VFPR16_M4, 816 },
|
|
{ PseudoVFRSUB_VFPR16_M8, 817 },
|
|
{ PseudoVFRSUB_VFPR16_MF2, 818 },
|
|
{ PseudoVFRSUB_VFPR16_MF4, 819 },
|
|
{ PseudoVFRSUB_VFPR32_M1, 820 },
|
|
{ PseudoVFRSUB_VFPR32_M2, 821 },
|
|
{ PseudoVFRSUB_VFPR32_M4, 822 },
|
|
{ PseudoVFRSUB_VFPR32_M8, 823 },
|
|
{ PseudoVFRSUB_VFPR32_MF2, 824 },
|
|
{ PseudoVFRSUB_VFPR64_M1, 825 },
|
|
{ PseudoVFRSUB_VFPR64_M2, 826 },
|
|
{ PseudoVFRSUB_VFPR64_M4, 827 },
|
|
{ PseudoVFRSUB_VFPR64_M8, 828 },
|
|
{ PseudoVFSGNJN_VFPR16_M1, 829 },
|
|
{ PseudoVFSGNJN_VFPR16_M2, 830 },
|
|
{ PseudoVFSGNJN_VFPR16_M4, 831 },
|
|
{ PseudoVFSGNJN_VFPR16_M8, 832 },
|
|
{ PseudoVFSGNJN_VFPR16_MF2, 833 },
|
|
{ PseudoVFSGNJN_VFPR16_MF4, 834 },
|
|
{ PseudoVFSGNJN_VFPR32_M1, 835 },
|
|
{ PseudoVFSGNJN_VFPR32_M2, 836 },
|
|
{ PseudoVFSGNJN_VFPR32_M4, 837 },
|
|
{ PseudoVFSGNJN_VFPR32_M8, 838 },
|
|
{ PseudoVFSGNJN_VFPR32_MF2, 839 },
|
|
{ PseudoVFSGNJN_VFPR64_M1, 840 },
|
|
{ PseudoVFSGNJN_VFPR64_M2, 841 },
|
|
{ PseudoVFSGNJN_VFPR64_M4, 842 },
|
|
{ PseudoVFSGNJN_VFPR64_M8, 843 },
|
|
{ PseudoVFSGNJN_VV_M1, 844 },
|
|
{ PseudoVFSGNJN_VV_M2, 845 },
|
|
{ PseudoVFSGNJN_VV_M4, 846 },
|
|
{ PseudoVFSGNJN_VV_M8, 847 },
|
|
{ PseudoVFSGNJN_VV_MF2, 848 },
|
|
{ PseudoVFSGNJN_VV_MF4, 849 },
|
|
{ PseudoVFSGNJX_VFPR16_M1, 850 },
|
|
{ PseudoVFSGNJX_VFPR16_M2, 851 },
|
|
{ PseudoVFSGNJX_VFPR16_M4, 852 },
|
|
{ PseudoVFSGNJX_VFPR16_M8, 853 },
|
|
{ PseudoVFSGNJX_VFPR16_MF2, 854 },
|
|
{ PseudoVFSGNJX_VFPR16_MF4, 855 },
|
|
{ PseudoVFSGNJX_VFPR32_M1, 856 },
|
|
{ PseudoVFSGNJX_VFPR32_M2, 857 },
|
|
{ PseudoVFSGNJX_VFPR32_M4, 858 },
|
|
{ PseudoVFSGNJX_VFPR32_M8, 859 },
|
|
{ PseudoVFSGNJX_VFPR32_MF2, 860 },
|
|
{ PseudoVFSGNJX_VFPR64_M1, 861 },
|
|
{ PseudoVFSGNJX_VFPR64_M2, 862 },
|
|
{ PseudoVFSGNJX_VFPR64_M4, 863 },
|
|
{ PseudoVFSGNJX_VFPR64_M8, 864 },
|
|
{ PseudoVFSGNJX_VV_M1, 865 },
|
|
{ PseudoVFSGNJX_VV_M2, 866 },
|
|
{ PseudoVFSGNJX_VV_M4, 867 },
|
|
{ PseudoVFSGNJX_VV_M8, 868 },
|
|
{ PseudoVFSGNJX_VV_MF2, 869 },
|
|
{ PseudoVFSGNJX_VV_MF4, 870 },
|
|
{ PseudoVFSGNJ_VFPR16_M1, 871 },
|
|
{ PseudoVFSGNJ_VFPR16_M2, 872 },
|
|
{ PseudoVFSGNJ_VFPR16_M4, 873 },
|
|
{ PseudoVFSGNJ_VFPR16_M8, 874 },
|
|
{ PseudoVFSGNJ_VFPR16_MF2, 875 },
|
|
{ PseudoVFSGNJ_VFPR16_MF4, 876 },
|
|
{ PseudoVFSGNJ_VFPR32_M1, 877 },
|
|
{ PseudoVFSGNJ_VFPR32_M2, 878 },
|
|
{ PseudoVFSGNJ_VFPR32_M4, 879 },
|
|
{ PseudoVFSGNJ_VFPR32_M8, 880 },
|
|
{ PseudoVFSGNJ_VFPR32_MF2, 881 },
|
|
{ PseudoVFSGNJ_VFPR64_M1, 882 },
|
|
{ PseudoVFSGNJ_VFPR64_M2, 883 },
|
|
{ PseudoVFSGNJ_VFPR64_M4, 884 },
|
|
{ PseudoVFSGNJ_VFPR64_M8, 885 },
|
|
{ PseudoVFSGNJ_VV_M1, 886 },
|
|
{ PseudoVFSGNJ_VV_M2, 887 },
|
|
{ PseudoVFSGNJ_VV_M4, 888 },
|
|
{ PseudoVFSGNJ_VV_M8, 889 },
|
|
{ PseudoVFSGNJ_VV_MF2, 890 },
|
|
{ PseudoVFSGNJ_VV_MF4, 891 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M1, 892 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M2, 893 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M4, 894 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M8, 895 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF2, 896 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF4, 897 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M1, 898 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M2, 899 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M4, 900 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M8, 901 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_MF2, 902 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M1, 903 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M2, 904 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M4, 905 },
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M8, 906 },
|
|
{ PseudoVFSLIDE1UP_VFPR16_M1, 907 },
|
|
{ PseudoVFSLIDE1UP_VFPR16_M2, 908 },
|
|
{ PseudoVFSLIDE1UP_VFPR16_M4, 909 },
|
|
{ PseudoVFSLIDE1UP_VFPR16_M8, 910 },
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF2, 911 },
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF4, 912 },
|
|
{ PseudoVFSLIDE1UP_VFPR32_M1, 913 },
|
|
{ PseudoVFSLIDE1UP_VFPR32_M2, 914 },
|
|
{ PseudoVFSLIDE1UP_VFPR32_M4, 915 },
|
|
{ PseudoVFSLIDE1UP_VFPR32_M8, 916 },
|
|
{ PseudoVFSLIDE1UP_VFPR32_MF2, 917 },
|
|
{ PseudoVFSLIDE1UP_VFPR64_M1, 918 },
|
|
{ PseudoVFSLIDE1UP_VFPR64_M2, 919 },
|
|
{ PseudoVFSLIDE1UP_VFPR64_M4, 920 },
|
|
{ PseudoVFSLIDE1UP_VFPR64_M8, 921 },
|
|
{ PseudoVFSQRT_V_M1_E16, 922 },
|
|
{ PseudoVFSQRT_V_M1_E32, 923 },
|
|
{ PseudoVFSQRT_V_M1_E64, 924 },
|
|
{ PseudoVFSQRT_V_M2_E16, 925 },
|
|
{ PseudoVFSQRT_V_M2_E32, 926 },
|
|
{ PseudoVFSQRT_V_M2_E64, 927 },
|
|
{ PseudoVFSQRT_V_M4_E16, 928 },
|
|
{ PseudoVFSQRT_V_M4_E32, 929 },
|
|
{ PseudoVFSQRT_V_M4_E64, 930 },
|
|
{ PseudoVFSQRT_V_M8_E16, 931 },
|
|
{ PseudoVFSQRT_V_M8_E32, 932 },
|
|
{ PseudoVFSQRT_V_M8_E64, 933 },
|
|
{ PseudoVFSQRT_V_MF2_E16, 934 },
|
|
{ PseudoVFSQRT_V_MF2_E32, 935 },
|
|
{ PseudoVFSQRT_V_MF4_E16, 936 },
|
|
{ PseudoVFSUB_VFPR16_M1, 937 },
|
|
{ PseudoVFSUB_VFPR16_M2, 938 },
|
|
{ PseudoVFSUB_VFPR16_M4, 939 },
|
|
{ PseudoVFSUB_VFPR16_M8, 940 },
|
|
{ PseudoVFSUB_VFPR16_MF2, 941 },
|
|
{ PseudoVFSUB_VFPR16_MF4, 942 },
|
|
{ PseudoVFSUB_VFPR32_M1, 943 },
|
|
{ PseudoVFSUB_VFPR32_M2, 944 },
|
|
{ PseudoVFSUB_VFPR32_M4, 945 },
|
|
{ PseudoVFSUB_VFPR32_M8, 946 },
|
|
{ PseudoVFSUB_VFPR32_MF2, 947 },
|
|
{ PseudoVFSUB_VFPR64_M1, 948 },
|
|
{ PseudoVFSUB_VFPR64_M2, 949 },
|
|
{ PseudoVFSUB_VFPR64_M4, 950 },
|
|
{ PseudoVFSUB_VFPR64_M8, 951 },
|
|
{ PseudoVFSUB_VV_M1, 952 },
|
|
{ PseudoVFSUB_VV_M2, 953 },
|
|
{ PseudoVFSUB_VV_M4, 954 },
|
|
{ PseudoVFSUB_VV_M8, 955 },
|
|
{ PseudoVFSUB_VV_MF2, 956 },
|
|
{ PseudoVFSUB_VV_MF4, 957 },
|
|
{ PseudoVFWADD_VFPR16_M1, 958 },
|
|
{ PseudoVFWADD_VFPR16_M2, 959 },
|
|
{ PseudoVFWADD_VFPR16_M4, 960 },
|
|
{ PseudoVFWADD_VFPR16_MF2, 961 },
|
|
{ PseudoVFWADD_VFPR16_MF4, 962 },
|
|
{ PseudoVFWADD_VFPR32_M1, 963 },
|
|
{ PseudoVFWADD_VFPR32_M2, 964 },
|
|
{ PseudoVFWADD_VFPR32_M4, 965 },
|
|
{ PseudoVFWADD_VFPR32_MF2, 966 },
|
|
{ PseudoVFWADD_VV_M1, 967 },
|
|
{ PseudoVFWADD_VV_M2, 968 },
|
|
{ PseudoVFWADD_VV_M4, 969 },
|
|
{ PseudoVFWADD_VV_MF2, 970 },
|
|
{ PseudoVFWADD_VV_MF4, 971 },
|
|
{ PseudoVFWADD_WFPR16_M1, 972 },
|
|
{ PseudoVFWADD_WFPR16_M2, 973 },
|
|
{ PseudoVFWADD_WFPR16_M4, 974 },
|
|
{ PseudoVFWADD_WFPR16_MF2, 975 },
|
|
{ PseudoVFWADD_WFPR16_MF4, 976 },
|
|
{ PseudoVFWADD_WFPR32_M1, 977 },
|
|
{ PseudoVFWADD_WFPR32_M2, 978 },
|
|
{ PseudoVFWADD_WFPR32_M4, 979 },
|
|
{ PseudoVFWADD_WFPR32_MF2, 980 },
|
|
{ PseudoVFWADD_WV_M1, 981 },
|
|
{ PseudoVFWADD_WV_M2, 982 },
|
|
{ PseudoVFWADD_WV_M4, 983 },
|
|
{ PseudoVFWADD_WV_MF2, 984 },
|
|
{ PseudoVFWADD_WV_MF4, 985 },
|
|
{ PseudoVFWCVTBF16_F_F_V_M1, 986 },
|
|
{ PseudoVFWCVTBF16_F_F_V_M2, 987 },
|
|
{ PseudoVFWCVTBF16_F_F_V_M4, 988 },
|
|
{ PseudoVFWCVTBF16_F_F_V_MF2, 989 },
|
|
{ PseudoVFWCVTBF16_F_F_V_MF4, 990 },
|
|
{ PseudoVFWCVT_F_F_V_M1, 991 },
|
|
{ PseudoVFWCVT_F_F_V_M2, 992 },
|
|
{ PseudoVFWCVT_F_F_V_M4, 993 },
|
|
{ PseudoVFWCVT_F_F_V_MF2, 994 },
|
|
{ PseudoVFWCVT_F_F_V_MF4, 995 },
|
|
{ PseudoVFWCVT_F_XU_V_M1, 996 },
|
|
{ PseudoVFWCVT_F_XU_V_M2, 997 },
|
|
{ PseudoVFWCVT_F_XU_V_M4, 998 },
|
|
{ PseudoVFWCVT_F_XU_V_MF2, 999 },
|
|
{ PseudoVFWCVT_F_XU_V_MF4, 1000 },
|
|
{ PseudoVFWCVT_F_XU_V_MF8, 1001 },
|
|
{ PseudoVFWCVT_F_X_V_M1, 1002 },
|
|
{ PseudoVFWCVT_F_X_V_M2, 1003 },
|
|
{ PseudoVFWCVT_F_X_V_M4, 1004 },
|
|
{ PseudoVFWCVT_F_X_V_MF2, 1005 },
|
|
{ PseudoVFWCVT_F_X_V_MF4, 1006 },
|
|
{ PseudoVFWCVT_F_X_V_MF8, 1007 },
|
|
{ PseudoVFWCVT_RM_XU_F_V_M1, 1008 },
|
|
{ PseudoVFWCVT_RM_XU_F_V_M2, 1009 },
|
|
{ PseudoVFWCVT_RM_XU_F_V_M4, 1010 },
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF2, 1011 },
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF4, 1012 },
|
|
{ PseudoVFWCVT_RM_X_F_V_M1, 1013 },
|
|
{ PseudoVFWCVT_RM_X_F_V_M2, 1014 },
|
|
{ PseudoVFWCVT_RM_X_F_V_M4, 1015 },
|
|
{ PseudoVFWCVT_RM_X_F_V_MF2, 1016 },
|
|
{ PseudoVFWCVT_RM_X_F_V_MF4, 1017 },
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M1, 1018 },
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M2, 1019 },
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M4, 1020 },
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF2, 1021 },
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF4, 1022 },
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M1, 1023 },
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M2, 1024 },
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M4, 1025 },
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF2, 1026 },
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF4, 1027 },
|
|
{ PseudoVFWCVT_XU_F_V_M1, 1028 },
|
|
{ PseudoVFWCVT_XU_F_V_M2, 1029 },
|
|
{ PseudoVFWCVT_XU_F_V_M4, 1030 },
|
|
{ PseudoVFWCVT_XU_F_V_MF2, 1031 },
|
|
{ PseudoVFWCVT_XU_F_V_MF4, 1032 },
|
|
{ PseudoVFWCVT_X_F_V_M1, 1033 },
|
|
{ PseudoVFWCVT_X_F_V_M2, 1034 },
|
|
{ PseudoVFWCVT_X_F_V_M4, 1035 },
|
|
{ PseudoVFWCVT_X_F_V_MF2, 1036 },
|
|
{ PseudoVFWCVT_X_F_V_MF4, 1037 },
|
|
{ PseudoVFWMACCBF16_VFPR16_M1, 1038 },
|
|
{ PseudoVFWMACCBF16_VFPR16_M2, 1039 },
|
|
{ PseudoVFWMACCBF16_VFPR16_M4, 1040 },
|
|
{ PseudoVFWMACCBF16_VFPR16_MF2, 1041 },
|
|
{ PseudoVFWMACCBF16_VFPR16_MF4, 1042 },
|
|
{ PseudoVFWMACCBF16_VV_M1, 1043 },
|
|
{ PseudoVFWMACCBF16_VV_M2, 1044 },
|
|
{ PseudoVFWMACCBF16_VV_M4, 1045 },
|
|
{ PseudoVFWMACCBF16_VV_MF2, 1046 },
|
|
{ PseudoVFWMACCBF16_VV_MF4, 1047 },
|
|
{ PseudoVFWMACC_VFPR16_M1, 1048 },
|
|
{ PseudoVFWMACC_VFPR16_M2, 1049 },
|
|
{ PseudoVFWMACC_VFPR16_M4, 1050 },
|
|
{ PseudoVFWMACC_VFPR16_MF2, 1051 },
|
|
{ PseudoVFWMACC_VFPR16_MF4, 1052 },
|
|
{ PseudoVFWMACC_VFPR32_M1, 1053 },
|
|
{ PseudoVFWMACC_VFPR32_M2, 1054 },
|
|
{ PseudoVFWMACC_VFPR32_M4, 1055 },
|
|
{ PseudoVFWMACC_VFPR32_MF2, 1056 },
|
|
{ PseudoVFWMACC_VV_M1, 1057 },
|
|
{ PseudoVFWMACC_VV_M2, 1058 },
|
|
{ PseudoVFWMACC_VV_M4, 1059 },
|
|
{ PseudoVFWMACC_VV_MF2, 1060 },
|
|
{ PseudoVFWMACC_VV_MF4, 1061 },
|
|
{ PseudoVFWMSAC_VFPR16_M1, 1062 },
|
|
{ PseudoVFWMSAC_VFPR16_M2, 1063 },
|
|
{ PseudoVFWMSAC_VFPR16_M4, 1064 },
|
|
{ PseudoVFWMSAC_VFPR16_MF2, 1065 },
|
|
{ PseudoVFWMSAC_VFPR16_MF4, 1066 },
|
|
{ PseudoVFWMSAC_VFPR32_M1, 1067 },
|
|
{ PseudoVFWMSAC_VFPR32_M2, 1068 },
|
|
{ PseudoVFWMSAC_VFPR32_M4, 1069 },
|
|
{ PseudoVFWMSAC_VFPR32_MF2, 1070 },
|
|
{ PseudoVFWMSAC_VV_M1, 1071 },
|
|
{ PseudoVFWMSAC_VV_M2, 1072 },
|
|
{ PseudoVFWMSAC_VV_M4, 1073 },
|
|
{ PseudoVFWMSAC_VV_MF2, 1074 },
|
|
{ PseudoVFWMSAC_VV_MF4, 1075 },
|
|
{ PseudoVFWMUL_VFPR16_M1, 1076 },
|
|
{ PseudoVFWMUL_VFPR16_M2, 1077 },
|
|
{ PseudoVFWMUL_VFPR16_M4, 1078 },
|
|
{ PseudoVFWMUL_VFPR16_MF2, 1079 },
|
|
{ PseudoVFWMUL_VFPR16_MF4, 1080 },
|
|
{ PseudoVFWMUL_VFPR32_M1, 1081 },
|
|
{ PseudoVFWMUL_VFPR32_M2, 1082 },
|
|
{ PseudoVFWMUL_VFPR32_M4, 1083 },
|
|
{ PseudoVFWMUL_VFPR32_MF2, 1084 },
|
|
{ PseudoVFWMUL_VV_M1, 1085 },
|
|
{ PseudoVFWMUL_VV_M2, 1086 },
|
|
{ PseudoVFWMUL_VV_M4, 1087 },
|
|
{ PseudoVFWMUL_VV_MF2, 1088 },
|
|
{ PseudoVFWMUL_VV_MF4, 1089 },
|
|
{ PseudoVFWNMACC_VFPR16_M1, 1090 },
|
|
{ PseudoVFWNMACC_VFPR16_M2, 1091 },
|
|
{ PseudoVFWNMACC_VFPR16_M4, 1092 },
|
|
{ PseudoVFWNMACC_VFPR16_MF2, 1093 },
|
|
{ PseudoVFWNMACC_VFPR16_MF4, 1094 },
|
|
{ PseudoVFWNMACC_VFPR32_M1, 1095 },
|
|
{ PseudoVFWNMACC_VFPR32_M2, 1096 },
|
|
{ PseudoVFWNMACC_VFPR32_M4, 1097 },
|
|
{ PseudoVFWNMACC_VFPR32_MF2, 1098 },
|
|
{ PseudoVFWNMACC_VV_M1, 1099 },
|
|
{ PseudoVFWNMACC_VV_M2, 1100 },
|
|
{ PseudoVFWNMACC_VV_M4, 1101 },
|
|
{ PseudoVFWNMACC_VV_MF2, 1102 },
|
|
{ PseudoVFWNMACC_VV_MF4, 1103 },
|
|
{ PseudoVFWNMSAC_VFPR16_M1, 1104 },
|
|
{ PseudoVFWNMSAC_VFPR16_M2, 1105 },
|
|
{ PseudoVFWNMSAC_VFPR16_M4, 1106 },
|
|
{ PseudoVFWNMSAC_VFPR16_MF2, 1107 },
|
|
{ PseudoVFWNMSAC_VFPR16_MF4, 1108 },
|
|
{ PseudoVFWNMSAC_VFPR32_M1, 1109 },
|
|
{ PseudoVFWNMSAC_VFPR32_M2, 1110 },
|
|
{ PseudoVFWNMSAC_VFPR32_M4, 1111 },
|
|
{ PseudoVFWNMSAC_VFPR32_MF2, 1112 },
|
|
{ PseudoVFWNMSAC_VV_M1, 1113 },
|
|
{ PseudoVFWNMSAC_VV_M2, 1114 },
|
|
{ PseudoVFWNMSAC_VV_M4, 1115 },
|
|
{ PseudoVFWNMSAC_VV_MF2, 1116 },
|
|
{ PseudoVFWNMSAC_VV_MF4, 1117 },
|
|
{ PseudoVFWREDOSUM_VS_M1_E16, 1118 },
|
|
{ PseudoVFWREDOSUM_VS_M1_E32, 1119 },
|
|
{ PseudoVFWREDOSUM_VS_M2_E16, 1120 },
|
|
{ PseudoVFWREDOSUM_VS_M2_E32, 1121 },
|
|
{ PseudoVFWREDOSUM_VS_M4_E16, 1122 },
|
|
{ PseudoVFWREDOSUM_VS_M4_E32, 1123 },
|
|
{ PseudoVFWREDOSUM_VS_M8_E16, 1124 },
|
|
{ PseudoVFWREDOSUM_VS_M8_E32, 1125 },
|
|
{ PseudoVFWREDOSUM_VS_MF2_E16, 1126 },
|
|
{ PseudoVFWREDOSUM_VS_MF2_E32, 1127 },
|
|
{ PseudoVFWREDOSUM_VS_MF4_E16, 1128 },
|
|
{ PseudoVFWREDUSUM_VS_M1_E16, 1129 },
|
|
{ PseudoVFWREDUSUM_VS_M1_E32, 1130 },
|
|
{ PseudoVFWREDUSUM_VS_M2_E16, 1131 },
|
|
{ PseudoVFWREDUSUM_VS_M2_E32, 1132 },
|
|
{ PseudoVFWREDUSUM_VS_M4_E16, 1133 },
|
|
{ PseudoVFWREDUSUM_VS_M4_E32, 1134 },
|
|
{ PseudoVFWREDUSUM_VS_M8_E16, 1135 },
|
|
{ PseudoVFWREDUSUM_VS_M8_E32, 1136 },
|
|
{ PseudoVFWREDUSUM_VS_MF2_E16, 1137 },
|
|
{ PseudoVFWREDUSUM_VS_MF2_E32, 1138 },
|
|
{ PseudoVFWREDUSUM_VS_MF4_E16, 1139 },
|
|
{ PseudoVFWSUB_VFPR16_M1, 1140 },
|
|
{ PseudoVFWSUB_VFPR16_M2, 1141 },
|
|
{ PseudoVFWSUB_VFPR16_M4, 1142 },
|
|
{ PseudoVFWSUB_VFPR16_MF2, 1143 },
|
|
{ PseudoVFWSUB_VFPR16_MF4, 1144 },
|
|
{ PseudoVFWSUB_VFPR32_M1, 1145 },
|
|
{ PseudoVFWSUB_VFPR32_M2, 1146 },
|
|
{ PseudoVFWSUB_VFPR32_M4, 1147 },
|
|
{ PseudoVFWSUB_VFPR32_MF2, 1148 },
|
|
{ PseudoVFWSUB_VV_M1, 1149 },
|
|
{ PseudoVFWSUB_VV_M2, 1150 },
|
|
{ PseudoVFWSUB_VV_M4, 1151 },
|
|
{ PseudoVFWSUB_VV_MF2, 1152 },
|
|
{ PseudoVFWSUB_VV_MF4, 1153 },
|
|
{ PseudoVFWSUB_WFPR16_M1, 1154 },
|
|
{ PseudoVFWSUB_WFPR16_M2, 1155 },
|
|
{ PseudoVFWSUB_WFPR16_M4, 1156 },
|
|
{ PseudoVFWSUB_WFPR16_MF2, 1157 },
|
|
{ PseudoVFWSUB_WFPR16_MF4, 1158 },
|
|
{ PseudoVFWSUB_WFPR32_M1, 1159 },
|
|
{ PseudoVFWSUB_WFPR32_M2, 1160 },
|
|
{ PseudoVFWSUB_WFPR32_M4, 1161 },
|
|
{ PseudoVFWSUB_WFPR32_MF2, 1162 },
|
|
{ PseudoVFWSUB_WV_M1, 1163 },
|
|
{ PseudoVFWSUB_WV_M2, 1164 },
|
|
{ PseudoVFWSUB_WV_M4, 1165 },
|
|
{ PseudoVFWSUB_WV_MF2, 1166 },
|
|
{ PseudoVFWSUB_WV_MF4, 1167 },
|
|
{ PseudoVID_V_M1, 1168 },
|
|
{ PseudoVID_V_M2, 1169 },
|
|
{ PseudoVID_V_M4, 1170 },
|
|
{ PseudoVID_V_M8, 1171 },
|
|
{ PseudoVID_V_MF2, 1172 },
|
|
{ PseudoVID_V_MF4, 1173 },
|
|
{ PseudoVID_V_MF8, 1174 },
|
|
{ PseudoVIOTA_M_M1, 1175 },
|
|
{ PseudoVIOTA_M_M2, 1176 },
|
|
{ PseudoVIOTA_M_M4, 1177 },
|
|
{ PseudoVIOTA_M_M8, 1178 },
|
|
{ PseudoVIOTA_M_MF2, 1179 },
|
|
{ PseudoVIOTA_M_MF4, 1180 },
|
|
{ PseudoVIOTA_M_MF8, 1181 },
|
|
{ PseudoVLE16FF_V_M1, 1182 },
|
|
{ PseudoVLE16FF_V_M2, 1183 },
|
|
{ PseudoVLE16FF_V_M4, 1184 },
|
|
{ PseudoVLE16FF_V_M8, 1185 },
|
|
{ PseudoVLE16FF_V_MF2, 1186 },
|
|
{ PseudoVLE16FF_V_MF4, 1187 },
|
|
{ PseudoVLE16_V_M1, 1188 },
|
|
{ PseudoVLE16_V_M2, 1189 },
|
|
{ PseudoVLE16_V_M4, 1190 },
|
|
{ PseudoVLE16_V_M8, 1191 },
|
|
{ PseudoVLE16_V_MF2, 1192 },
|
|
{ PseudoVLE16_V_MF4, 1193 },
|
|
{ PseudoVLE32FF_V_M1, 1194 },
|
|
{ PseudoVLE32FF_V_M2, 1195 },
|
|
{ PseudoVLE32FF_V_M4, 1196 },
|
|
{ PseudoVLE32FF_V_M8, 1197 },
|
|
{ PseudoVLE32FF_V_MF2, 1198 },
|
|
{ PseudoVLE32_V_M1, 1199 },
|
|
{ PseudoVLE32_V_M2, 1200 },
|
|
{ PseudoVLE32_V_M4, 1201 },
|
|
{ PseudoVLE32_V_M8, 1202 },
|
|
{ PseudoVLE32_V_MF2, 1203 },
|
|
{ PseudoVLE64FF_V_M1, 1204 },
|
|
{ PseudoVLE64FF_V_M2, 1205 },
|
|
{ PseudoVLE64FF_V_M4, 1206 },
|
|
{ PseudoVLE64FF_V_M8, 1207 },
|
|
{ PseudoVLE64_V_M1, 1208 },
|
|
{ PseudoVLE64_V_M2, 1209 },
|
|
{ PseudoVLE64_V_M4, 1210 },
|
|
{ PseudoVLE64_V_M8, 1211 },
|
|
{ PseudoVLE8FF_V_M1, 1212 },
|
|
{ PseudoVLE8FF_V_M2, 1213 },
|
|
{ PseudoVLE8FF_V_M4, 1214 },
|
|
{ PseudoVLE8FF_V_M8, 1215 },
|
|
{ PseudoVLE8FF_V_MF2, 1216 },
|
|
{ PseudoVLE8FF_V_MF4, 1217 },
|
|
{ PseudoVLE8FF_V_MF8, 1218 },
|
|
{ PseudoVLE8_V_M1, 1219 },
|
|
{ PseudoVLE8_V_M2, 1220 },
|
|
{ PseudoVLE8_V_M4, 1221 },
|
|
{ PseudoVLE8_V_M8, 1222 },
|
|
{ PseudoVLE8_V_MF2, 1223 },
|
|
{ PseudoVLE8_V_MF4, 1224 },
|
|
{ PseudoVLE8_V_MF8, 1225 },
|
|
{ PseudoVLOXEI16_V_M1_M1, 1226 },
|
|
{ PseudoVLOXEI16_V_M1_M2, 1227 },
|
|
{ PseudoVLOXEI16_V_M1_M4, 1228 },
|
|
{ PseudoVLOXEI16_V_M1_MF2, 1229 },
|
|
{ PseudoVLOXEI16_V_M2_M1, 1230 },
|
|
{ PseudoVLOXEI16_V_M2_M2, 1231 },
|
|
{ PseudoVLOXEI16_V_M2_M4, 1232 },
|
|
{ PseudoVLOXEI16_V_M2_M8, 1233 },
|
|
{ PseudoVLOXEI16_V_M4_M2, 1234 },
|
|
{ PseudoVLOXEI16_V_M4_M4, 1235 },
|
|
{ PseudoVLOXEI16_V_M4_M8, 1236 },
|
|
{ PseudoVLOXEI16_V_M8_M4, 1237 },
|
|
{ PseudoVLOXEI16_V_M8_M8, 1238 },
|
|
{ PseudoVLOXEI16_V_MF2_M1, 1239 },
|
|
{ PseudoVLOXEI16_V_MF2_M2, 1240 },
|
|
{ PseudoVLOXEI16_V_MF2_MF2, 1241 },
|
|
{ PseudoVLOXEI16_V_MF2_MF4, 1242 },
|
|
{ PseudoVLOXEI16_V_MF4_M1, 1243 },
|
|
{ PseudoVLOXEI16_V_MF4_MF2, 1244 },
|
|
{ PseudoVLOXEI16_V_MF4_MF4, 1245 },
|
|
{ PseudoVLOXEI16_V_MF4_MF8, 1246 },
|
|
{ PseudoVLOXEI32_V_M1_M1, 1247 },
|
|
{ PseudoVLOXEI32_V_M1_M2, 1248 },
|
|
{ PseudoVLOXEI32_V_M1_MF2, 1249 },
|
|
{ PseudoVLOXEI32_V_M1_MF4, 1250 },
|
|
{ PseudoVLOXEI32_V_M2_M1, 1251 },
|
|
{ PseudoVLOXEI32_V_M2_M2, 1252 },
|
|
{ PseudoVLOXEI32_V_M2_M4, 1253 },
|
|
{ PseudoVLOXEI32_V_M2_MF2, 1254 },
|
|
{ PseudoVLOXEI32_V_M4_M1, 1255 },
|
|
{ PseudoVLOXEI32_V_M4_M2, 1256 },
|
|
{ PseudoVLOXEI32_V_M4_M4, 1257 },
|
|
{ PseudoVLOXEI32_V_M4_M8, 1258 },
|
|
{ PseudoVLOXEI32_V_M8_M2, 1259 },
|
|
{ PseudoVLOXEI32_V_M8_M4, 1260 },
|
|
{ PseudoVLOXEI32_V_M8_M8, 1261 },
|
|
{ PseudoVLOXEI32_V_MF2_M1, 1262 },
|
|
{ PseudoVLOXEI32_V_MF2_MF2, 1263 },
|
|
{ PseudoVLOXEI32_V_MF2_MF4, 1264 },
|
|
{ PseudoVLOXEI32_V_MF2_MF8, 1265 },
|
|
{ PseudoVLOXEI64_V_M1_M1, 1266 },
|
|
{ PseudoVLOXEI64_V_M1_MF2, 1267 },
|
|
{ PseudoVLOXEI64_V_M1_MF4, 1268 },
|
|
{ PseudoVLOXEI64_V_M1_MF8, 1269 },
|
|
{ PseudoVLOXEI64_V_M2_M1, 1270 },
|
|
{ PseudoVLOXEI64_V_M2_M2, 1271 },
|
|
{ PseudoVLOXEI64_V_M2_MF2, 1272 },
|
|
{ PseudoVLOXEI64_V_M2_MF4, 1273 },
|
|
{ PseudoVLOXEI64_V_M4_M1, 1274 },
|
|
{ PseudoVLOXEI64_V_M4_M2, 1275 },
|
|
{ PseudoVLOXEI64_V_M4_M4, 1276 },
|
|
{ PseudoVLOXEI64_V_M4_MF2, 1277 },
|
|
{ PseudoVLOXEI64_V_M8_M1, 1278 },
|
|
{ PseudoVLOXEI64_V_M8_M2, 1279 },
|
|
{ PseudoVLOXEI64_V_M8_M4, 1280 },
|
|
{ PseudoVLOXEI64_V_M8_M8, 1281 },
|
|
{ PseudoVLOXEI8_V_M1_M1, 1282 },
|
|
{ PseudoVLOXEI8_V_M1_M2, 1283 },
|
|
{ PseudoVLOXEI8_V_M1_M4, 1284 },
|
|
{ PseudoVLOXEI8_V_M1_M8, 1285 },
|
|
{ PseudoVLOXEI8_V_M2_M2, 1286 },
|
|
{ PseudoVLOXEI8_V_M2_M4, 1287 },
|
|
{ PseudoVLOXEI8_V_M2_M8, 1288 },
|
|
{ PseudoVLOXEI8_V_M4_M4, 1289 },
|
|
{ PseudoVLOXEI8_V_M4_M8, 1290 },
|
|
{ PseudoVLOXEI8_V_M8_M8, 1291 },
|
|
{ PseudoVLOXEI8_V_MF2_M1, 1292 },
|
|
{ PseudoVLOXEI8_V_MF2_M2, 1293 },
|
|
{ PseudoVLOXEI8_V_MF2_M4, 1294 },
|
|
{ PseudoVLOXEI8_V_MF2_MF2, 1295 },
|
|
{ PseudoVLOXEI8_V_MF4_M1, 1296 },
|
|
{ PseudoVLOXEI8_V_MF4_M2, 1297 },
|
|
{ PseudoVLOXEI8_V_MF4_MF2, 1298 },
|
|
{ PseudoVLOXEI8_V_MF4_MF4, 1299 },
|
|
{ PseudoVLOXEI8_V_MF8_M1, 1300 },
|
|
{ PseudoVLOXEI8_V_MF8_MF2, 1301 },
|
|
{ PseudoVLOXEI8_V_MF8_MF4, 1302 },
|
|
{ PseudoVLOXEI8_V_MF8_MF8, 1303 },
|
|
{ PseudoVLSE16_V_M1, 1304 },
|
|
{ PseudoVLSE16_V_M2, 1305 },
|
|
{ PseudoVLSE16_V_M4, 1306 },
|
|
{ PseudoVLSE16_V_M8, 1307 },
|
|
{ PseudoVLSE16_V_MF2, 1308 },
|
|
{ PseudoVLSE16_V_MF4, 1309 },
|
|
{ PseudoVLSE32_V_M1, 1310 },
|
|
{ PseudoVLSE32_V_M2, 1311 },
|
|
{ PseudoVLSE32_V_M4, 1312 },
|
|
{ PseudoVLSE32_V_M8, 1313 },
|
|
{ PseudoVLSE32_V_MF2, 1314 },
|
|
{ PseudoVLSE64_V_M1, 1315 },
|
|
{ PseudoVLSE64_V_M2, 1316 },
|
|
{ PseudoVLSE64_V_M4, 1317 },
|
|
{ PseudoVLSE64_V_M8, 1318 },
|
|
{ PseudoVLSE8_V_M1, 1319 },
|
|
{ PseudoVLSE8_V_M2, 1320 },
|
|
{ PseudoVLSE8_V_M4, 1321 },
|
|
{ PseudoVLSE8_V_M8, 1322 },
|
|
{ PseudoVLSE8_V_MF2, 1323 },
|
|
{ PseudoVLSE8_V_MF4, 1324 },
|
|
{ PseudoVLSE8_V_MF8, 1325 },
|
|
{ PseudoVLUXEI16_V_M1_M1, 1326 },
|
|
{ PseudoVLUXEI16_V_M1_M2, 1327 },
|
|
{ PseudoVLUXEI16_V_M1_M4, 1328 },
|
|
{ PseudoVLUXEI16_V_M1_MF2, 1329 },
|
|
{ PseudoVLUXEI16_V_M2_M1, 1330 },
|
|
{ PseudoVLUXEI16_V_M2_M2, 1331 },
|
|
{ PseudoVLUXEI16_V_M2_M4, 1332 },
|
|
{ PseudoVLUXEI16_V_M2_M8, 1333 },
|
|
{ PseudoVLUXEI16_V_M4_M2, 1334 },
|
|
{ PseudoVLUXEI16_V_M4_M4, 1335 },
|
|
{ PseudoVLUXEI16_V_M4_M8, 1336 },
|
|
{ PseudoVLUXEI16_V_M8_M4, 1337 },
|
|
{ PseudoVLUXEI16_V_M8_M8, 1338 },
|
|
{ PseudoVLUXEI16_V_MF2_M1, 1339 },
|
|
{ PseudoVLUXEI16_V_MF2_M2, 1340 },
|
|
{ PseudoVLUXEI16_V_MF2_MF2, 1341 },
|
|
{ PseudoVLUXEI16_V_MF2_MF4, 1342 },
|
|
{ PseudoVLUXEI16_V_MF4_M1, 1343 },
|
|
{ PseudoVLUXEI16_V_MF4_MF2, 1344 },
|
|
{ PseudoVLUXEI16_V_MF4_MF4, 1345 },
|
|
{ PseudoVLUXEI16_V_MF4_MF8, 1346 },
|
|
{ PseudoVLUXEI32_V_M1_M1, 1347 },
|
|
{ PseudoVLUXEI32_V_M1_M2, 1348 },
|
|
{ PseudoVLUXEI32_V_M1_MF2, 1349 },
|
|
{ PseudoVLUXEI32_V_M1_MF4, 1350 },
|
|
{ PseudoVLUXEI32_V_M2_M1, 1351 },
|
|
{ PseudoVLUXEI32_V_M2_M2, 1352 },
|
|
{ PseudoVLUXEI32_V_M2_M4, 1353 },
|
|
{ PseudoVLUXEI32_V_M2_MF2, 1354 },
|
|
{ PseudoVLUXEI32_V_M4_M1, 1355 },
|
|
{ PseudoVLUXEI32_V_M4_M2, 1356 },
|
|
{ PseudoVLUXEI32_V_M4_M4, 1357 },
|
|
{ PseudoVLUXEI32_V_M4_M8, 1358 },
|
|
{ PseudoVLUXEI32_V_M8_M2, 1359 },
|
|
{ PseudoVLUXEI32_V_M8_M4, 1360 },
|
|
{ PseudoVLUXEI32_V_M8_M8, 1361 },
|
|
{ PseudoVLUXEI32_V_MF2_M1, 1362 },
|
|
{ PseudoVLUXEI32_V_MF2_MF2, 1363 },
|
|
{ PseudoVLUXEI32_V_MF2_MF4, 1364 },
|
|
{ PseudoVLUXEI32_V_MF2_MF8, 1365 },
|
|
{ PseudoVLUXEI64_V_M1_M1, 1366 },
|
|
{ PseudoVLUXEI64_V_M1_MF2, 1367 },
|
|
{ PseudoVLUXEI64_V_M1_MF4, 1368 },
|
|
{ PseudoVLUXEI64_V_M1_MF8, 1369 },
|
|
{ PseudoVLUXEI64_V_M2_M1, 1370 },
|
|
{ PseudoVLUXEI64_V_M2_M2, 1371 },
|
|
{ PseudoVLUXEI64_V_M2_MF2, 1372 },
|
|
{ PseudoVLUXEI64_V_M2_MF4, 1373 },
|
|
{ PseudoVLUXEI64_V_M4_M1, 1374 },
|
|
{ PseudoVLUXEI64_V_M4_M2, 1375 },
|
|
{ PseudoVLUXEI64_V_M4_M4, 1376 },
|
|
{ PseudoVLUXEI64_V_M4_MF2, 1377 },
|
|
{ PseudoVLUXEI64_V_M8_M1, 1378 },
|
|
{ PseudoVLUXEI64_V_M8_M2, 1379 },
|
|
{ PseudoVLUXEI64_V_M8_M4, 1380 },
|
|
{ PseudoVLUXEI64_V_M8_M8, 1381 },
|
|
{ PseudoVLUXEI8_V_M1_M1, 1382 },
|
|
{ PseudoVLUXEI8_V_M1_M2, 1383 },
|
|
{ PseudoVLUXEI8_V_M1_M4, 1384 },
|
|
{ PseudoVLUXEI8_V_M1_M8, 1385 },
|
|
{ PseudoVLUXEI8_V_M2_M2, 1386 },
|
|
{ PseudoVLUXEI8_V_M2_M4, 1387 },
|
|
{ PseudoVLUXEI8_V_M2_M8, 1388 },
|
|
{ PseudoVLUXEI8_V_M4_M4, 1389 },
|
|
{ PseudoVLUXEI8_V_M4_M8, 1390 },
|
|
{ PseudoVLUXEI8_V_M8_M8, 1391 },
|
|
{ PseudoVLUXEI8_V_MF2_M1, 1392 },
|
|
{ PseudoVLUXEI8_V_MF2_M2, 1393 },
|
|
{ PseudoVLUXEI8_V_MF2_M4, 1394 },
|
|
{ PseudoVLUXEI8_V_MF2_MF2, 1395 },
|
|
{ PseudoVLUXEI8_V_MF4_M1, 1396 },
|
|
{ PseudoVLUXEI8_V_MF4_M2, 1397 },
|
|
{ PseudoVLUXEI8_V_MF4_MF2, 1398 },
|
|
{ PseudoVLUXEI8_V_MF4_MF4, 1399 },
|
|
{ PseudoVLUXEI8_V_MF8_M1, 1400 },
|
|
{ PseudoVLUXEI8_V_MF8_MF2, 1401 },
|
|
{ PseudoVLUXEI8_V_MF8_MF4, 1402 },
|
|
{ PseudoVLUXEI8_V_MF8_MF8, 1403 },
|
|
{ PseudoVMACC_VV_M1, 1404 },
|
|
{ PseudoVMACC_VV_M2, 1405 },
|
|
{ PseudoVMACC_VV_M4, 1406 },
|
|
{ PseudoVMACC_VV_M8, 1407 },
|
|
{ PseudoVMACC_VV_MF2, 1408 },
|
|
{ PseudoVMACC_VV_MF4, 1409 },
|
|
{ PseudoVMACC_VV_MF8, 1410 },
|
|
{ PseudoVMACC_VX_M1, 1411 },
|
|
{ PseudoVMACC_VX_M2, 1412 },
|
|
{ PseudoVMACC_VX_M4, 1413 },
|
|
{ PseudoVMACC_VX_M8, 1414 },
|
|
{ PseudoVMACC_VX_MF2, 1415 },
|
|
{ PseudoVMACC_VX_MF4, 1416 },
|
|
{ PseudoVMACC_VX_MF8, 1417 },
|
|
{ PseudoVMADD_VV_M1, 1418 },
|
|
{ PseudoVMADD_VV_M2, 1419 },
|
|
{ PseudoVMADD_VV_M4, 1420 },
|
|
{ PseudoVMADD_VV_M8, 1421 },
|
|
{ PseudoVMADD_VV_MF2, 1422 },
|
|
{ PseudoVMADD_VV_MF4, 1423 },
|
|
{ PseudoVMADD_VV_MF8, 1424 },
|
|
{ PseudoVMADD_VX_M1, 1425 },
|
|
{ PseudoVMADD_VX_M2, 1426 },
|
|
{ PseudoVMADD_VX_M4, 1427 },
|
|
{ PseudoVMADD_VX_M8, 1428 },
|
|
{ PseudoVMADD_VX_MF2, 1429 },
|
|
{ PseudoVMADD_VX_MF4, 1430 },
|
|
{ PseudoVMADD_VX_MF8, 1431 },
|
|
{ PseudoVMAXU_VV_M1, 1432 },
|
|
{ PseudoVMAXU_VV_M2, 1433 },
|
|
{ PseudoVMAXU_VV_M4, 1434 },
|
|
{ PseudoVMAXU_VV_M8, 1435 },
|
|
{ PseudoVMAXU_VV_MF2, 1436 },
|
|
{ PseudoVMAXU_VV_MF4, 1437 },
|
|
{ PseudoVMAXU_VV_MF8, 1438 },
|
|
{ PseudoVMAXU_VX_M1, 1439 },
|
|
{ PseudoVMAXU_VX_M2, 1440 },
|
|
{ PseudoVMAXU_VX_M4, 1441 },
|
|
{ PseudoVMAXU_VX_M8, 1442 },
|
|
{ PseudoVMAXU_VX_MF2, 1443 },
|
|
{ PseudoVMAXU_VX_MF4, 1444 },
|
|
{ PseudoVMAXU_VX_MF8, 1445 },
|
|
{ PseudoVMAX_VV_M1, 1446 },
|
|
{ PseudoVMAX_VV_M2, 1447 },
|
|
{ PseudoVMAX_VV_M4, 1448 },
|
|
{ PseudoVMAX_VV_M8, 1449 },
|
|
{ PseudoVMAX_VV_MF2, 1450 },
|
|
{ PseudoVMAX_VV_MF4, 1451 },
|
|
{ PseudoVMAX_VV_MF8, 1452 },
|
|
{ PseudoVMAX_VX_M1, 1453 },
|
|
{ PseudoVMAX_VX_M2, 1454 },
|
|
{ PseudoVMAX_VX_M4, 1455 },
|
|
{ PseudoVMAX_VX_M8, 1456 },
|
|
{ PseudoVMAX_VX_MF2, 1457 },
|
|
{ PseudoVMAX_VX_MF4, 1458 },
|
|
{ PseudoVMAX_VX_MF8, 1459 },
|
|
{ PseudoVMFEQ_VFPR16_M1, 1460 },
|
|
{ PseudoVMFEQ_VFPR16_M2, 1461 },
|
|
{ PseudoVMFEQ_VFPR16_M4, 1462 },
|
|
{ PseudoVMFEQ_VFPR16_M8, 1463 },
|
|
{ PseudoVMFEQ_VFPR16_MF2, 1464 },
|
|
{ PseudoVMFEQ_VFPR16_MF4, 1465 },
|
|
{ PseudoVMFEQ_VFPR32_M1, 1466 },
|
|
{ PseudoVMFEQ_VFPR32_M2, 1467 },
|
|
{ PseudoVMFEQ_VFPR32_M4, 1468 },
|
|
{ PseudoVMFEQ_VFPR32_M8, 1469 },
|
|
{ PseudoVMFEQ_VFPR32_MF2, 1470 },
|
|
{ PseudoVMFEQ_VFPR64_M1, 1471 },
|
|
{ PseudoVMFEQ_VFPR64_M2, 1472 },
|
|
{ PseudoVMFEQ_VFPR64_M4, 1473 },
|
|
{ PseudoVMFEQ_VFPR64_M8, 1474 },
|
|
{ PseudoVMFEQ_VV_M1, 1475 },
|
|
{ PseudoVMFEQ_VV_M2, 1476 },
|
|
{ PseudoVMFEQ_VV_M4, 1477 },
|
|
{ PseudoVMFEQ_VV_M8, 1478 },
|
|
{ PseudoVMFEQ_VV_MF2, 1479 },
|
|
{ PseudoVMFEQ_VV_MF4, 1480 },
|
|
{ PseudoVMFGE_VFPR16_M1, 1481 },
|
|
{ PseudoVMFGE_VFPR16_M2, 1482 },
|
|
{ PseudoVMFGE_VFPR16_M4, 1483 },
|
|
{ PseudoVMFGE_VFPR16_M8, 1484 },
|
|
{ PseudoVMFGE_VFPR16_MF2, 1485 },
|
|
{ PseudoVMFGE_VFPR16_MF4, 1486 },
|
|
{ PseudoVMFGE_VFPR32_M1, 1487 },
|
|
{ PseudoVMFGE_VFPR32_M2, 1488 },
|
|
{ PseudoVMFGE_VFPR32_M4, 1489 },
|
|
{ PseudoVMFGE_VFPR32_M8, 1490 },
|
|
{ PseudoVMFGE_VFPR32_MF2, 1491 },
|
|
{ PseudoVMFGE_VFPR64_M1, 1492 },
|
|
{ PseudoVMFGE_VFPR64_M2, 1493 },
|
|
{ PseudoVMFGE_VFPR64_M4, 1494 },
|
|
{ PseudoVMFGE_VFPR64_M8, 1495 },
|
|
{ PseudoVMFGT_VFPR16_M1, 1496 },
|
|
{ PseudoVMFGT_VFPR16_M2, 1497 },
|
|
{ PseudoVMFGT_VFPR16_M4, 1498 },
|
|
{ PseudoVMFGT_VFPR16_M8, 1499 },
|
|
{ PseudoVMFGT_VFPR16_MF2, 1500 },
|
|
{ PseudoVMFGT_VFPR16_MF4, 1501 },
|
|
{ PseudoVMFGT_VFPR32_M1, 1502 },
|
|
{ PseudoVMFGT_VFPR32_M2, 1503 },
|
|
{ PseudoVMFGT_VFPR32_M4, 1504 },
|
|
{ PseudoVMFGT_VFPR32_M8, 1505 },
|
|
{ PseudoVMFGT_VFPR32_MF2, 1506 },
|
|
{ PseudoVMFGT_VFPR64_M1, 1507 },
|
|
{ PseudoVMFGT_VFPR64_M2, 1508 },
|
|
{ PseudoVMFGT_VFPR64_M4, 1509 },
|
|
{ PseudoVMFGT_VFPR64_M8, 1510 },
|
|
{ PseudoVMFLE_VFPR16_M1, 1511 },
|
|
{ PseudoVMFLE_VFPR16_M2, 1512 },
|
|
{ PseudoVMFLE_VFPR16_M4, 1513 },
|
|
{ PseudoVMFLE_VFPR16_M8, 1514 },
|
|
{ PseudoVMFLE_VFPR16_MF2, 1515 },
|
|
{ PseudoVMFLE_VFPR16_MF4, 1516 },
|
|
{ PseudoVMFLE_VFPR32_M1, 1517 },
|
|
{ PseudoVMFLE_VFPR32_M2, 1518 },
|
|
{ PseudoVMFLE_VFPR32_M4, 1519 },
|
|
{ PseudoVMFLE_VFPR32_M8, 1520 },
|
|
{ PseudoVMFLE_VFPR32_MF2, 1521 },
|
|
{ PseudoVMFLE_VFPR64_M1, 1522 },
|
|
{ PseudoVMFLE_VFPR64_M2, 1523 },
|
|
{ PseudoVMFLE_VFPR64_M4, 1524 },
|
|
{ PseudoVMFLE_VFPR64_M8, 1525 },
|
|
{ PseudoVMFLE_VV_M1, 1526 },
|
|
{ PseudoVMFLE_VV_M2, 1527 },
|
|
{ PseudoVMFLE_VV_M4, 1528 },
|
|
{ PseudoVMFLE_VV_M8, 1529 },
|
|
{ PseudoVMFLE_VV_MF2, 1530 },
|
|
{ PseudoVMFLE_VV_MF4, 1531 },
|
|
{ PseudoVMFLT_VFPR16_M1, 1532 },
|
|
{ PseudoVMFLT_VFPR16_M2, 1533 },
|
|
{ PseudoVMFLT_VFPR16_M4, 1534 },
|
|
{ PseudoVMFLT_VFPR16_M8, 1535 },
|
|
{ PseudoVMFLT_VFPR16_MF2, 1536 },
|
|
{ PseudoVMFLT_VFPR16_MF4, 1537 },
|
|
{ PseudoVMFLT_VFPR32_M1, 1538 },
|
|
{ PseudoVMFLT_VFPR32_M2, 1539 },
|
|
{ PseudoVMFLT_VFPR32_M4, 1540 },
|
|
{ PseudoVMFLT_VFPR32_M8, 1541 },
|
|
{ PseudoVMFLT_VFPR32_MF2, 1542 },
|
|
{ PseudoVMFLT_VFPR64_M1, 1543 },
|
|
{ PseudoVMFLT_VFPR64_M2, 1544 },
|
|
{ PseudoVMFLT_VFPR64_M4, 1545 },
|
|
{ PseudoVMFLT_VFPR64_M8, 1546 },
|
|
{ PseudoVMFLT_VV_M1, 1547 },
|
|
{ PseudoVMFLT_VV_M2, 1548 },
|
|
{ PseudoVMFLT_VV_M4, 1549 },
|
|
{ PseudoVMFLT_VV_M8, 1550 },
|
|
{ PseudoVMFLT_VV_MF2, 1551 },
|
|
{ PseudoVMFLT_VV_MF4, 1552 },
|
|
{ PseudoVMFNE_VFPR16_M1, 1553 },
|
|
{ PseudoVMFNE_VFPR16_M2, 1554 },
|
|
{ PseudoVMFNE_VFPR16_M4, 1555 },
|
|
{ PseudoVMFNE_VFPR16_M8, 1556 },
|
|
{ PseudoVMFNE_VFPR16_MF2, 1557 },
|
|
{ PseudoVMFNE_VFPR16_MF4, 1558 },
|
|
{ PseudoVMFNE_VFPR32_M1, 1559 },
|
|
{ PseudoVMFNE_VFPR32_M2, 1560 },
|
|
{ PseudoVMFNE_VFPR32_M4, 1561 },
|
|
{ PseudoVMFNE_VFPR32_M8, 1562 },
|
|
{ PseudoVMFNE_VFPR32_MF2, 1563 },
|
|
{ PseudoVMFNE_VFPR64_M1, 1564 },
|
|
{ PseudoVMFNE_VFPR64_M2, 1565 },
|
|
{ PseudoVMFNE_VFPR64_M4, 1566 },
|
|
{ PseudoVMFNE_VFPR64_M8, 1567 },
|
|
{ PseudoVMFNE_VV_M1, 1568 },
|
|
{ PseudoVMFNE_VV_M2, 1569 },
|
|
{ PseudoVMFNE_VV_M4, 1570 },
|
|
{ PseudoVMFNE_VV_M8, 1571 },
|
|
{ PseudoVMFNE_VV_MF2, 1572 },
|
|
{ PseudoVMFNE_VV_MF4, 1573 },
|
|
{ PseudoVMINU_VV_M1, 1574 },
|
|
{ PseudoVMINU_VV_M2, 1575 },
|
|
{ PseudoVMINU_VV_M4, 1576 },
|
|
{ PseudoVMINU_VV_M8, 1577 },
|
|
{ PseudoVMINU_VV_MF2, 1578 },
|
|
{ PseudoVMINU_VV_MF4, 1579 },
|
|
{ PseudoVMINU_VV_MF8, 1580 },
|
|
{ PseudoVMINU_VX_M1, 1581 },
|
|
{ PseudoVMINU_VX_M2, 1582 },
|
|
{ PseudoVMINU_VX_M4, 1583 },
|
|
{ PseudoVMINU_VX_M8, 1584 },
|
|
{ PseudoVMINU_VX_MF2, 1585 },
|
|
{ PseudoVMINU_VX_MF4, 1586 },
|
|
{ PseudoVMINU_VX_MF8, 1587 },
|
|
{ PseudoVMIN_VV_M1, 1588 },
|
|
{ PseudoVMIN_VV_M2, 1589 },
|
|
{ PseudoVMIN_VV_M4, 1590 },
|
|
{ PseudoVMIN_VV_M8, 1591 },
|
|
{ PseudoVMIN_VV_MF2, 1592 },
|
|
{ PseudoVMIN_VV_MF4, 1593 },
|
|
{ PseudoVMIN_VV_MF8, 1594 },
|
|
{ PseudoVMIN_VX_M1, 1595 },
|
|
{ PseudoVMIN_VX_M2, 1596 },
|
|
{ PseudoVMIN_VX_M4, 1597 },
|
|
{ PseudoVMIN_VX_M8, 1598 },
|
|
{ PseudoVMIN_VX_MF2, 1599 },
|
|
{ PseudoVMIN_VX_MF4, 1600 },
|
|
{ PseudoVMIN_VX_MF8, 1601 },
|
|
{ PseudoVMSEQ_VI_M1, 1602 },
|
|
{ PseudoVMSEQ_VI_M2, 1603 },
|
|
{ PseudoVMSEQ_VI_M4, 1604 },
|
|
{ PseudoVMSEQ_VI_M8, 1605 },
|
|
{ PseudoVMSEQ_VI_MF2, 1606 },
|
|
{ PseudoVMSEQ_VI_MF4, 1607 },
|
|
{ PseudoVMSEQ_VI_MF8, 1608 },
|
|
{ PseudoVMSEQ_VV_M1, 1609 },
|
|
{ PseudoVMSEQ_VV_M2, 1610 },
|
|
{ PseudoVMSEQ_VV_M4, 1611 },
|
|
{ PseudoVMSEQ_VV_M8, 1612 },
|
|
{ PseudoVMSEQ_VV_MF2, 1613 },
|
|
{ PseudoVMSEQ_VV_MF4, 1614 },
|
|
{ PseudoVMSEQ_VV_MF8, 1615 },
|
|
{ PseudoVMSEQ_VX_M1, 1616 },
|
|
{ PseudoVMSEQ_VX_M2, 1617 },
|
|
{ PseudoVMSEQ_VX_M4, 1618 },
|
|
{ PseudoVMSEQ_VX_M8, 1619 },
|
|
{ PseudoVMSEQ_VX_MF2, 1620 },
|
|
{ PseudoVMSEQ_VX_MF4, 1621 },
|
|
{ PseudoVMSEQ_VX_MF8, 1622 },
|
|
{ PseudoVMSGTU_VI_M1, 1623 },
|
|
{ PseudoVMSGTU_VI_M2, 1624 },
|
|
{ PseudoVMSGTU_VI_M4, 1625 },
|
|
{ PseudoVMSGTU_VI_M8, 1626 },
|
|
{ PseudoVMSGTU_VI_MF2, 1627 },
|
|
{ PseudoVMSGTU_VI_MF4, 1628 },
|
|
{ PseudoVMSGTU_VI_MF8, 1629 },
|
|
{ PseudoVMSGTU_VX_M1, 1630 },
|
|
{ PseudoVMSGTU_VX_M2, 1631 },
|
|
{ PseudoVMSGTU_VX_M4, 1632 },
|
|
{ PseudoVMSGTU_VX_M8, 1633 },
|
|
{ PseudoVMSGTU_VX_MF2, 1634 },
|
|
{ PseudoVMSGTU_VX_MF4, 1635 },
|
|
{ PseudoVMSGTU_VX_MF8, 1636 },
|
|
{ PseudoVMSGT_VI_M1, 1637 },
|
|
{ PseudoVMSGT_VI_M2, 1638 },
|
|
{ PseudoVMSGT_VI_M4, 1639 },
|
|
{ PseudoVMSGT_VI_M8, 1640 },
|
|
{ PseudoVMSGT_VI_MF2, 1641 },
|
|
{ PseudoVMSGT_VI_MF4, 1642 },
|
|
{ PseudoVMSGT_VI_MF8, 1643 },
|
|
{ PseudoVMSGT_VX_M1, 1644 },
|
|
{ PseudoVMSGT_VX_M2, 1645 },
|
|
{ PseudoVMSGT_VX_M4, 1646 },
|
|
{ PseudoVMSGT_VX_M8, 1647 },
|
|
{ PseudoVMSGT_VX_MF2, 1648 },
|
|
{ PseudoVMSGT_VX_MF4, 1649 },
|
|
{ PseudoVMSGT_VX_MF8, 1650 },
|
|
{ PseudoVMSLEU_VI_M1, 1651 },
|
|
{ PseudoVMSLEU_VI_M2, 1652 },
|
|
{ PseudoVMSLEU_VI_M4, 1653 },
|
|
{ PseudoVMSLEU_VI_M8, 1654 },
|
|
{ PseudoVMSLEU_VI_MF2, 1655 },
|
|
{ PseudoVMSLEU_VI_MF4, 1656 },
|
|
{ PseudoVMSLEU_VI_MF8, 1657 },
|
|
{ PseudoVMSLEU_VV_M1, 1658 },
|
|
{ PseudoVMSLEU_VV_M2, 1659 },
|
|
{ PseudoVMSLEU_VV_M4, 1660 },
|
|
{ PseudoVMSLEU_VV_M8, 1661 },
|
|
{ PseudoVMSLEU_VV_MF2, 1662 },
|
|
{ PseudoVMSLEU_VV_MF4, 1663 },
|
|
{ PseudoVMSLEU_VV_MF8, 1664 },
|
|
{ PseudoVMSLEU_VX_M1, 1665 },
|
|
{ PseudoVMSLEU_VX_M2, 1666 },
|
|
{ PseudoVMSLEU_VX_M4, 1667 },
|
|
{ PseudoVMSLEU_VX_M8, 1668 },
|
|
{ PseudoVMSLEU_VX_MF2, 1669 },
|
|
{ PseudoVMSLEU_VX_MF4, 1670 },
|
|
{ PseudoVMSLEU_VX_MF8, 1671 },
|
|
{ PseudoVMSLE_VI_M1, 1672 },
|
|
{ PseudoVMSLE_VI_M2, 1673 },
|
|
{ PseudoVMSLE_VI_M4, 1674 },
|
|
{ PseudoVMSLE_VI_M8, 1675 },
|
|
{ PseudoVMSLE_VI_MF2, 1676 },
|
|
{ PseudoVMSLE_VI_MF4, 1677 },
|
|
{ PseudoVMSLE_VI_MF8, 1678 },
|
|
{ PseudoVMSLE_VV_M1, 1679 },
|
|
{ PseudoVMSLE_VV_M2, 1680 },
|
|
{ PseudoVMSLE_VV_M4, 1681 },
|
|
{ PseudoVMSLE_VV_M8, 1682 },
|
|
{ PseudoVMSLE_VV_MF2, 1683 },
|
|
{ PseudoVMSLE_VV_MF4, 1684 },
|
|
{ PseudoVMSLE_VV_MF8, 1685 },
|
|
{ PseudoVMSLE_VX_M1, 1686 },
|
|
{ PseudoVMSLE_VX_M2, 1687 },
|
|
{ PseudoVMSLE_VX_M4, 1688 },
|
|
{ PseudoVMSLE_VX_M8, 1689 },
|
|
{ PseudoVMSLE_VX_MF2, 1690 },
|
|
{ PseudoVMSLE_VX_MF4, 1691 },
|
|
{ PseudoVMSLE_VX_MF8, 1692 },
|
|
{ PseudoVMSLTU_VV_M1, 1693 },
|
|
{ PseudoVMSLTU_VV_M2, 1694 },
|
|
{ PseudoVMSLTU_VV_M4, 1695 },
|
|
{ PseudoVMSLTU_VV_M8, 1696 },
|
|
{ PseudoVMSLTU_VV_MF2, 1697 },
|
|
{ PseudoVMSLTU_VV_MF4, 1698 },
|
|
{ PseudoVMSLTU_VV_MF8, 1699 },
|
|
{ PseudoVMSLTU_VX_M1, 1700 },
|
|
{ PseudoVMSLTU_VX_M2, 1701 },
|
|
{ PseudoVMSLTU_VX_M4, 1702 },
|
|
{ PseudoVMSLTU_VX_M8, 1703 },
|
|
{ PseudoVMSLTU_VX_MF2, 1704 },
|
|
{ PseudoVMSLTU_VX_MF4, 1705 },
|
|
{ PseudoVMSLTU_VX_MF8, 1706 },
|
|
{ PseudoVMSLT_VV_M1, 1707 },
|
|
{ PseudoVMSLT_VV_M2, 1708 },
|
|
{ PseudoVMSLT_VV_M4, 1709 },
|
|
{ PseudoVMSLT_VV_M8, 1710 },
|
|
{ PseudoVMSLT_VV_MF2, 1711 },
|
|
{ PseudoVMSLT_VV_MF4, 1712 },
|
|
{ PseudoVMSLT_VV_MF8, 1713 },
|
|
{ PseudoVMSLT_VX_M1, 1714 },
|
|
{ PseudoVMSLT_VX_M2, 1715 },
|
|
{ PseudoVMSLT_VX_M4, 1716 },
|
|
{ PseudoVMSLT_VX_M8, 1717 },
|
|
{ PseudoVMSLT_VX_MF2, 1718 },
|
|
{ PseudoVMSLT_VX_MF4, 1719 },
|
|
{ PseudoVMSLT_VX_MF8, 1720 },
|
|
{ PseudoVMSNE_VI_M1, 1721 },
|
|
{ PseudoVMSNE_VI_M2, 1722 },
|
|
{ PseudoVMSNE_VI_M4, 1723 },
|
|
{ PseudoVMSNE_VI_M8, 1724 },
|
|
{ PseudoVMSNE_VI_MF2, 1725 },
|
|
{ PseudoVMSNE_VI_MF4, 1726 },
|
|
{ PseudoVMSNE_VI_MF8, 1727 },
|
|
{ PseudoVMSNE_VV_M1, 1728 },
|
|
{ PseudoVMSNE_VV_M2, 1729 },
|
|
{ PseudoVMSNE_VV_M4, 1730 },
|
|
{ PseudoVMSNE_VV_M8, 1731 },
|
|
{ PseudoVMSNE_VV_MF2, 1732 },
|
|
{ PseudoVMSNE_VV_MF4, 1733 },
|
|
{ PseudoVMSNE_VV_MF8, 1734 },
|
|
{ PseudoVMSNE_VX_M1, 1735 },
|
|
{ PseudoVMSNE_VX_M2, 1736 },
|
|
{ PseudoVMSNE_VX_M4, 1737 },
|
|
{ PseudoVMSNE_VX_M8, 1738 },
|
|
{ PseudoVMSNE_VX_MF2, 1739 },
|
|
{ PseudoVMSNE_VX_MF4, 1740 },
|
|
{ PseudoVMSNE_VX_MF8, 1741 },
|
|
{ PseudoVMULHSU_VV_M1, 1742 },
|
|
{ PseudoVMULHSU_VV_M2, 1743 },
|
|
{ PseudoVMULHSU_VV_M4, 1744 },
|
|
{ PseudoVMULHSU_VV_M8, 1745 },
|
|
{ PseudoVMULHSU_VV_MF2, 1746 },
|
|
{ PseudoVMULHSU_VV_MF4, 1747 },
|
|
{ PseudoVMULHSU_VV_MF8, 1748 },
|
|
{ PseudoVMULHSU_VX_M1, 1749 },
|
|
{ PseudoVMULHSU_VX_M2, 1750 },
|
|
{ PseudoVMULHSU_VX_M4, 1751 },
|
|
{ PseudoVMULHSU_VX_M8, 1752 },
|
|
{ PseudoVMULHSU_VX_MF2, 1753 },
|
|
{ PseudoVMULHSU_VX_MF4, 1754 },
|
|
{ PseudoVMULHSU_VX_MF8, 1755 },
|
|
{ PseudoVMULHU_VV_M1, 1756 },
|
|
{ PseudoVMULHU_VV_M2, 1757 },
|
|
{ PseudoVMULHU_VV_M4, 1758 },
|
|
{ PseudoVMULHU_VV_M8, 1759 },
|
|
{ PseudoVMULHU_VV_MF2, 1760 },
|
|
{ PseudoVMULHU_VV_MF4, 1761 },
|
|
{ PseudoVMULHU_VV_MF8, 1762 },
|
|
{ PseudoVMULHU_VX_M1, 1763 },
|
|
{ PseudoVMULHU_VX_M2, 1764 },
|
|
{ PseudoVMULHU_VX_M4, 1765 },
|
|
{ PseudoVMULHU_VX_M8, 1766 },
|
|
{ PseudoVMULHU_VX_MF2, 1767 },
|
|
{ PseudoVMULHU_VX_MF4, 1768 },
|
|
{ PseudoVMULHU_VX_MF8, 1769 },
|
|
{ PseudoVMULH_VV_M1, 1770 },
|
|
{ PseudoVMULH_VV_M2, 1771 },
|
|
{ PseudoVMULH_VV_M4, 1772 },
|
|
{ PseudoVMULH_VV_M8, 1773 },
|
|
{ PseudoVMULH_VV_MF2, 1774 },
|
|
{ PseudoVMULH_VV_MF4, 1775 },
|
|
{ PseudoVMULH_VV_MF8, 1776 },
|
|
{ PseudoVMULH_VX_M1, 1777 },
|
|
{ PseudoVMULH_VX_M2, 1778 },
|
|
{ PseudoVMULH_VX_M4, 1779 },
|
|
{ PseudoVMULH_VX_M8, 1780 },
|
|
{ PseudoVMULH_VX_MF2, 1781 },
|
|
{ PseudoVMULH_VX_MF4, 1782 },
|
|
{ PseudoVMULH_VX_MF8, 1783 },
|
|
{ PseudoVMUL_VV_M1, 1784 },
|
|
{ PseudoVMUL_VV_M2, 1785 },
|
|
{ PseudoVMUL_VV_M4, 1786 },
|
|
{ PseudoVMUL_VV_M8, 1787 },
|
|
{ PseudoVMUL_VV_MF2, 1788 },
|
|
{ PseudoVMUL_VV_MF4, 1789 },
|
|
{ PseudoVMUL_VV_MF8, 1790 },
|
|
{ PseudoVMUL_VX_M1, 1791 },
|
|
{ PseudoVMUL_VX_M2, 1792 },
|
|
{ PseudoVMUL_VX_M4, 1793 },
|
|
{ PseudoVMUL_VX_M8, 1794 },
|
|
{ PseudoVMUL_VX_MF2, 1795 },
|
|
{ PseudoVMUL_VX_MF4, 1796 },
|
|
{ PseudoVMUL_VX_MF8, 1797 },
|
|
{ PseudoVNCLIPU_WI_M1, 1798 },
|
|
{ PseudoVNCLIPU_WI_M2, 1799 },
|
|
{ PseudoVNCLIPU_WI_M4, 1800 },
|
|
{ PseudoVNCLIPU_WI_MF2, 1801 },
|
|
{ PseudoVNCLIPU_WI_MF4, 1802 },
|
|
{ PseudoVNCLIPU_WI_MF8, 1803 },
|
|
{ PseudoVNCLIPU_WV_M1, 1804 },
|
|
{ PseudoVNCLIPU_WV_M2, 1805 },
|
|
{ PseudoVNCLIPU_WV_M4, 1806 },
|
|
{ PseudoVNCLIPU_WV_MF2, 1807 },
|
|
{ PseudoVNCLIPU_WV_MF4, 1808 },
|
|
{ PseudoVNCLIPU_WV_MF8, 1809 },
|
|
{ PseudoVNCLIPU_WX_M1, 1810 },
|
|
{ PseudoVNCLIPU_WX_M2, 1811 },
|
|
{ PseudoVNCLIPU_WX_M4, 1812 },
|
|
{ PseudoVNCLIPU_WX_MF2, 1813 },
|
|
{ PseudoVNCLIPU_WX_MF4, 1814 },
|
|
{ PseudoVNCLIPU_WX_MF8, 1815 },
|
|
{ PseudoVNCLIP_WI_M1, 1816 },
|
|
{ PseudoVNCLIP_WI_M2, 1817 },
|
|
{ PseudoVNCLIP_WI_M4, 1818 },
|
|
{ PseudoVNCLIP_WI_MF2, 1819 },
|
|
{ PseudoVNCLIP_WI_MF4, 1820 },
|
|
{ PseudoVNCLIP_WI_MF8, 1821 },
|
|
{ PseudoVNCLIP_WV_M1, 1822 },
|
|
{ PseudoVNCLIP_WV_M2, 1823 },
|
|
{ PseudoVNCLIP_WV_M4, 1824 },
|
|
{ PseudoVNCLIP_WV_MF2, 1825 },
|
|
{ PseudoVNCLIP_WV_MF4, 1826 },
|
|
{ PseudoVNCLIP_WV_MF8, 1827 },
|
|
{ PseudoVNCLIP_WX_M1, 1828 },
|
|
{ PseudoVNCLIP_WX_M2, 1829 },
|
|
{ PseudoVNCLIP_WX_M4, 1830 },
|
|
{ PseudoVNCLIP_WX_MF2, 1831 },
|
|
{ PseudoVNCLIP_WX_MF4, 1832 },
|
|
{ PseudoVNCLIP_WX_MF8, 1833 },
|
|
{ PseudoVNMSAC_VV_M1, 1834 },
|
|
{ PseudoVNMSAC_VV_M2, 1835 },
|
|
{ PseudoVNMSAC_VV_M4, 1836 },
|
|
{ PseudoVNMSAC_VV_M8, 1837 },
|
|
{ PseudoVNMSAC_VV_MF2, 1838 },
|
|
{ PseudoVNMSAC_VV_MF4, 1839 },
|
|
{ PseudoVNMSAC_VV_MF8, 1840 },
|
|
{ PseudoVNMSAC_VX_M1, 1841 },
|
|
{ PseudoVNMSAC_VX_M2, 1842 },
|
|
{ PseudoVNMSAC_VX_M4, 1843 },
|
|
{ PseudoVNMSAC_VX_M8, 1844 },
|
|
{ PseudoVNMSAC_VX_MF2, 1845 },
|
|
{ PseudoVNMSAC_VX_MF4, 1846 },
|
|
{ PseudoVNMSAC_VX_MF8, 1847 },
|
|
{ PseudoVNMSUB_VV_M1, 1848 },
|
|
{ PseudoVNMSUB_VV_M2, 1849 },
|
|
{ PseudoVNMSUB_VV_M4, 1850 },
|
|
{ PseudoVNMSUB_VV_M8, 1851 },
|
|
{ PseudoVNMSUB_VV_MF2, 1852 },
|
|
{ PseudoVNMSUB_VV_MF4, 1853 },
|
|
{ PseudoVNMSUB_VV_MF8, 1854 },
|
|
{ PseudoVNMSUB_VX_M1, 1855 },
|
|
{ PseudoVNMSUB_VX_M2, 1856 },
|
|
{ PseudoVNMSUB_VX_M4, 1857 },
|
|
{ PseudoVNMSUB_VX_M8, 1858 },
|
|
{ PseudoVNMSUB_VX_MF2, 1859 },
|
|
{ PseudoVNMSUB_VX_MF4, 1860 },
|
|
{ PseudoVNMSUB_VX_MF8, 1861 },
|
|
{ PseudoVNSRA_WI_M1, 1862 },
|
|
{ PseudoVNSRA_WI_M2, 1863 },
|
|
{ PseudoVNSRA_WI_M4, 1864 },
|
|
{ PseudoVNSRA_WI_MF2, 1865 },
|
|
{ PseudoVNSRA_WI_MF4, 1866 },
|
|
{ PseudoVNSRA_WI_MF8, 1867 },
|
|
{ PseudoVNSRA_WV_M1, 1868 },
|
|
{ PseudoVNSRA_WV_M2, 1869 },
|
|
{ PseudoVNSRA_WV_M4, 1870 },
|
|
{ PseudoVNSRA_WV_MF2, 1871 },
|
|
{ PseudoVNSRA_WV_MF4, 1872 },
|
|
{ PseudoVNSRA_WV_MF8, 1873 },
|
|
{ PseudoVNSRA_WX_M1, 1874 },
|
|
{ PseudoVNSRA_WX_M2, 1875 },
|
|
{ PseudoVNSRA_WX_M4, 1876 },
|
|
{ PseudoVNSRA_WX_MF2, 1877 },
|
|
{ PseudoVNSRA_WX_MF4, 1878 },
|
|
{ PseudoVNSRA_WX_MF8, 1879 },
|
|
{ PseudoVNSRL_WI_M1, 1880 },
|
|
{ PseudoVNSRL_WI_M2, 1881 },
|
|
{ PseudoVNSRL_WI_M4, 1882 },
|
|
{ PseudoVNSRL_WI_MF2, 1883 },
|
|
{ PseudoVNSRL_WI_MF4, 1884 },
|
|
{ PseudoVNSRL_WI_MF8, 1885 },
|
|
{ PseudoVNSRL_WV_M1, 1886 },
|
|
{ PseudoVNSRL_WV_M2, 1887 },
|
|
{ PseudoVNSRL_WV_M4, 1888 },
|
|
{ PseudoVNSRL_WV_MF2, 1889 },
|
|
{ PseudoVNSRL_WV_MF4, 1890 },
|
|
{ PseudoVNSRL_WV_MF8, 1891 },
|
|
{ PseudoVNSRL_WX_M1, 1892 },
|
|
{ PseudoVNSRL_WX_M2, 1893 },
|
|
{ PseudoVNSRL_WX_M4, 1894 },
|
|
{ PseudoVNSRL_WX_MF2, 1895 },
|
|
{ PseudoVNSRL_WX_MF4, 1896 },
|
|
{ PseudoVNSRL_WX_MF8, 1897 },
|
|
{ PseudoVOR_VI_M1, 1898 },
|
|
{ PseudoVOR_VI_M2, 1899 },
|
|
{ PseudoVOR_VI_M4, 1900 },
|
|
{ PseudoVOR_VI_M8, 1901 },
|
|
{ PseudoVOR_VI_MF2, 1902 },
|
|
{ PseudoVOR_VI_MF4, 1903 },
|
|
{ PseudoVOR_VI_MF8, 1904 },
|
|
{ PseudoVOR_VV_M1, 1905 },
|
|
{ PseudoVOR_VV_M2, 1906 },
|
|
{ PseudoVOR_VV_M4, 1907 },
|
|
{ PseudoVOR_VV_M8, 1908 },
|
|
{ PseudoVOR_VV_MF2, 1909 },
|
|
{ PseudoVOR_VV_MF4, 1910 },
|
|
{ PseudoVOR_VV_MF8, 1911 },
|
|
{ PseudoVOR_VX_M1, 1912 },
|
|
{ PseudoVOR_VX_M2, 1913 },
|
|
{ PseudoVOR_VX_M4, 1914 },
|
|
{ PseudoVOR_VX_M8, 1915 },
|
|
{ PseudoVOR_VX_MF2, 1916 },
|
|
{ PseudoVOR_VX_MF4, 1917 },
|
|
{ PseudoVOR_VX_MF8, 1918 },
|
|
{ PseudoVREDAND_VS_M1_E16, 1919 },
|
|
{ PseudoVREDAND_VS_M1_E32, 1920 },
|
|
{ PseudoVREDAND_VS_M1_E64, 1921 },
|
|
{ PseudoVREDAND_VS_M1_E8, 1922 },
|
|
{ PseudoVREDAND_VS_M2_E16, 1923 },
|
|
{ PseudoVREDAND_VS_M2_E32, 1924 },
|
|
{ PseudoVREDAND_VS_M2_E64, 1925 },
|
|
{ PseudoVREDAND_VS_M2_E8, 1926 },
|
|
{ PseudoVREDAND_VS_M4_E16, 1927 },
|
|
{ PseudoVREDAND_VS_M4_E32, 1928 },
|
|
{ PseudoVREDAND_VS_M4_E64, 1929 },
|
|
{ PseudoVREDAND_VS_M4_E8, 1930 },
|
|
{ PseudoVREDAND_VS_M8_E16, 1931 },
|
|
{ PseudoVREDAND_VS_M8_E32, 1932 },
|
|
{ PseudoVREDAND_VS_M8_E64, 1933 },
|
|
{ PseudoVREDAND_VS_M8_E8, 1934 },
|
|
{ PseudoVREDAND_VS_MF2_E16, 1935 },
|
|
{ PseudoVREDAND_VS_MF2_E32, 1936 },
|
|
{ PseudoVREDAND_VS_MF2_E8, 1937 },
|
|
{ PseudoVREDAND_VS_MF4_E16, 1938 },
|
|
{ PseudoVREDAND_VS_MF4_E8, 1939 },
|
|
{ PseudoVREDAND_VS_MF8_E8, 1940 },
|
|
{ PseudoVREDMAXU_VS_M1_E16, 1941 },
|
|
{ PseudoVREDMAXU_VS_M1_E32, 1942 },
|
|
{ PseudoVREDMAXU_VS_M1_E64, 1943 },
|
|
{ PseudoVREDMAXU_VS_M1_E8, 1944 },
|
|
{ PseudoVREDMAXU_VS_M2_E16, 1945 },
|
|
{ PseudoVREDMAXU_VS_M2_E32, 1946 },
|
|
{ PseudoVREDMAXU_VS_M2_E64, 1947 },
|
|
{ PseudoVREDMAXU_VS_M2_E8, 1948 },
|
|
{ PseudoVREDMAXU_VS_M4_E16, 1949 },
|
|
{ PseudoVREDMAXU_VS_M4_E32, 1950 },
|
|
{ PseudoVREDMAXU_VS_M4_E64, 1951 },
|
|
{ PseudoVREDMAXU_VS_M4_E8, 1952 },
|
|
{ PseudoVREDMAXU_VS_M8_E16, 1953 },
|
|
{ PseudoVREDMAXU_VS_M8_E32, 1954 },
|
|
{ PseudoVREDMAXU_VS_M8_E64, 1955 },
|
|
{ PseudoVREDMAXU_VS_M8_E8, 1956 },
|
|
{ PseudoVREDMAXU_VS_MF2_E16, 1957 },
|
|
{ PseudoVREDMAXU_VS_MF2_E32, 1958 },
|
|
{ PseudoVREDMAXU_VS_MF2_E8, 1959 },
|
|
{ PseudoVREDMAXU_VS_MF4_E16, 1960 },
|
|
{ PseudoVREDMAXU_VS_MF4_E8, 1961 },
|
|
{ PseudoVREDMAXU_VS_MF8_E8, 1962 },
|
|
{ PseudoVREDMAX_VS_M1_E16, 1963 },
|
|
{ PseudoVREDMAX_VS_M1_E32, 1964 },
|
|
{ PseudoVREDMAX_VS_M1_E64, 1965 },
|
|
{ PseudoVREDMAX_VS_M1_E8, 1966 },
|
|
{ PseudoVREDMAX_VS_M2_E16, 1967 },
|
|
{ PseudoVREDMAX_VS_M2_E32, 1968 },
|
|
{ PseudoVREDMAX_VS_M2_E64, 1969 },
|
|
{ PseudoVREDMAX_VS_M2_E8, 1970 },
|
|
{ PseudoVREDMAX_VS_M4_E16, 1971 },
|
|
{ PseudoVREDMAX_VS_M4_E32, 1972 },
|
|
{ PseudoVREDMAX_VS_M4_E64, 1973 },
|
|
{ PseudoVREDMAX_VS_M4_E8, 1974 },
|
|
{ PseudoVREDMAX_VS_M8_E16, 1975 },
|
|
{ PseudoVREDMAX_VS_M8_E32, 1976 },
|
|
{ PseudoVREDMAX_VS_M8_E64, 1977 },
|
|
{ PseudoVREDMAX_VS_M8_E8, 1978 },
|
|
{ PseudoVREDMAX_VS_MF2_E16, 1979 },
|
|
{ PseudoVREDMAX_VS_MF2_E32, 1980 },
|
|
{ PseudoVREDMAX_VS_MF2_E8, 1981 },
|
|
{ PseudoVREDMAX_VS_MF4_E16, 1982 },
|
|
{ PseudoVREDMAX_VS_MF4_E8, 1983 },
|
|
{ PseudoVREDMAX_VS_MF8_E8, 1984 },
|
|
{ PseudoVREDMINU_VS_M1_E16, 1985 },
|
|
{ PseudoVREDMINU_VS_M1_E32, 1986 },
|
|
{ PseudoVREDMINU_VS_M1_E64, 1987 },
|
|
{ PseudoVREDMINU_VS_M1_E8, 1988 },
|
|
{ PseudoVREDMINU_VS_M2_E16, 1989 },
|
|
{ PseudoVREDMINU_VS_M2_E32, 1990 },
|
|
{ PseudoVREDMINU_VS_M2_E64, 1991 },
|
|
{ PseudoVREDMINU_VS_M2_E8, 1992 },
|
|
{ PseudoVREDMINU_VS_M4_E16, 1993 },
|
|
{ PseudoVREDMINU_VS_M4_E32, 1994 },
|
|
{ PseudoVREDMINU_VS_M4_E64, 1995 },
|
|
{ PseudoVREDMINU_VS_M4_E8, 1996 },
|
|
{ PseudoVREDMINU_VS_M8_E16, 1997 },
|
|
{ PseudoVREDMINU_VS_M8_E32, 1998 },
|
|
{ PseudoVREDMINU_VS_M8_E64, 1999 },
|
|
{ PseudoVREDMINU_VS_M8_E8, 2000 },
|
|
{ PseudoVREDMINU_VS_MF2_E16, 2001 },
|
|
{ PseudoVREDMINU_VS_MF2_E32, 2002 },
|
|
{ PseudoVREDMINU_VS_MF2_E8, 2003 },
|
|
{ PseudoVREDMINU_VS_MF4_E16, 2004 },
|
|
{ PseudoVREDMINU_VS_MF4_E8, 2005 },
|
|
{ PseudoVREDMINU_VS_MF8_E8, 2006 },
|
|
{ PseudoVREDMIN_VS_M1_E16, 2007 },
|
|
{ PseudoVREDMIN_VS_M1_E32, 2008 },
|
|
{ PseudoVREDMIN_VS_M1_E64, 2009 },
|
|
{ PseudoVREDMIN_VS_M1_E8, 2010 },
|
|
{ PseudoVREDMIN_VS_M2_E16, 2011 },
|
|
{ PseudoVREDMIN_VS_M2_E32, 2012 },
|
|
{ PseudoVREDMIN_VS_M2_E64, 2013 },
|
|
{ PseudoVREDMIN_VS_M2_E8, 2014 },
|
|
{ PseudoVREDMIN_VS_M4_E16, 2015 },
|
|
{ PseudoVREDMIN_VS_M4_E32, 2016 },
|
|
{ PseudoVREDMIN_VS_M4_E64, 2017 },
|
|
{ PseudoVREDMIN_VS_M4_E8, 2018 },
|
|
{ PseudoVREDMIN_VS_M8_E16, 2019 },
|
|
{ PseudoVREDMIN_VS_M8_E32, 2020 },
|
|
{ PseudoVREDMIN_VS_M8_E64, 2021 },
|
|
{ PseudoVREDMIN_VS_M8_E8, 2022 },
|
|
{ PseudoVREDMIN_VS_MF2_E16, 2023 },
|
|
{ PseudoVREDMIN_VS_MF2_E32, 2024 },
|
|
{ PseudoVREDMIN_VS_MF2_E8, 2025 },
|
|
{ PseudoVREDMIN_VS_MF4_E16, 2026 },
|
|
{ PseudoVREDMIN_VS_MF4_E8, 2027 },
|
|
{ PseudoVREDMIN_VS_MF8_E8, 2028 },
|
|
{ PseudoVREDOR_VS_M1_E16, 2029 },
|
|
{ PseudoVREDOR_VS_M1_E32, 2030 },
|
|
{ PseudoVREDOR_VS_M1_E64, 2031 },
|
|
{ PseudoVREDOR_VS_M1_E8, 2032 },
|
|
{ PseudoVREDOR_VS_M2_E16, 2033 },
|
|
{ PseudoVREDOR_VS_M2_E32, 2034 },
|
|
{ PseudoVREDOR_VS_M2_E64, 2035 },
|
|
{ PseudoVREDOR_VS_M2_E8, 2036 },
|
|
{ PseudoVREDOR_VS_M4_E16, 2037 },
|
|
{ PseudoVREDOR_VS_M4_E32, 2038 },
|
|
{ PseudoVREDOR_VS_M4_E64, 2039 },
|
|
{ PseudoVREDOR_VS_M4_E8, 2040 },
|
|
{ PseudoVREDOR_VS_M8_E16, 2041 },
|
|
{ PseudoVREDOR_VS_M8_E32, 2042 },
|
|
{ PseudoVREDOR_VS_M8_E64, 2043 },
|
|
{ PseudoVREDOR_VS_M8_E8, 2044 },
|
|
{ PseudoVREDOR_VS_MF2_E16, 2045 },
|
|
{ PseudoVREDOR_VS_MF2_E32, 2046 },
|
|
{ PseudoVREDOR_VS_MF2_E8, 2047 },
|
|
{ PseudoVREDOR_VS_MF4_E16, 2048 },
|
|
{ PseudoVREDOR_VS_MF4_E8, 2049 },
|
|
{ PseudoVREDOR_VS_MF8_E8, 2050 },
|
|
{ PseudoVREDSUM_VS_M1_E16, 2051 },
|
|
{ PseudoVREDSUM_VS_M1_E32, 2052 },
|
|
{ PseudoVREDSUM_VS_M1_E64, 2053 },
|
|
{ PseudoVREDSUM_VS_M1_E8, 2054 },
|
|
{ PseudoVREDSUM_VS_M2_E16, 2055 },
|
|
{ PseudoVREDSUM_VS_M2_E32, 2056 },
|
|
{ PseudoVREDSUM_VS_M2_E64, 2057 },
|
|
{ PseudoVREDSUM_VS_M2_E8, 2058 },
|
|
{ PseudoVREDSUM_VS_M4_E16, 2059 },
|
|
{ PseudoVREDSUM_VS_M4_E32, 2060 },
|
|
{ PseudoVREDSUM_VS_M4_E64, 2061 },
|
|
{ PseudoVREDSUM_VS_M4_E8, 2062 },
|
|
{ PseudoVREDSUM_VS_M8_E16, 2063 },
|
|
{ PseudoVREDSUM_VS_M8_E32, 2064 },
|
|
{ PseudoVREDSUM_VS_M8_E64, 2065 },
|
|
{ PseudoVREDSUM_VS_M8_E8, 2066 },
|
|
{ PseudoVREDSUM_VS_MF2_E16, 2067 },
|
|
{ PseudoVREDSUM_VS_MF2_E32, 2068 },
|
|
{ PseudoVREDSUM_VS_MF2_E8, 2069 },
|
|
{ PseudoVREDSUM_VS_MF4_E16, 2070 },
|
|
{ PseudoVREDSUM_VS_MF4_E8, 2071 },
|
|
{ PseudoVREDSUM_VS_MF8_E8, 2072 },
|
|
{ PseudoVREDXOR_VS_M1_E16, 2073 },
|
|
{ PseudoVREDXOR_VS_M1_E32, 2074 },
|
|
{ PseudoVREDXOR_VS_M1_E64, 2075 },
|
|
{ PseudoVREDXOR_VS_M1_E8, 2076 },
|
|
{ PseudoVREDXOR_VS_M2_E16, 2077 },
|
|
{ PseudoVREDXOR_VS_M2_E32, 2078 },
|
|
{ PseudoVREDXOR_VS_M2_E64, 2079 },
|
|
{ PseudoVREDXOR_VS_M2_E8, 2080 },
|
|
{ PseudoVREDXOR_VS_M4_E16, 2081 },
|
|
{ PseudoVREDXOR_VS_M4_E32, 2082 },
|
|
{ PseudoVREDXOR_VS_M4_E64, 2083 },
|
|
{ PseudoVREDXOR_VS_M4_E8, 2084 },
|
|
{ PseudoVREDXOR_VS_M8_E16, 2085 },
|
|
{ PseudoVREDXOR_VS_M8_E32, 2086 },
|
|
{ PseudoVREDXOR_VS_M8_E64, 2087 },
|
|
{ PseudoVREDXOR_VS_M8_E8, 2088 },
|
|
{ PseudoVREDXOR_VS_MF2_E16, 2089 },
|
|
{ PseudoVREDXOR_VS_MF2_E32, 2090 },
|
|
{ PseudoVREDXOR_VS_MF2_E8, 2091 },
|
|
{ PseudoVREDXOR_VS_MF4_E16, 2092 },
|
|
{ PseudoVREDXOR_VS_MF4_E8, 2093 },
|
|
{ PseudoVREDXOR_VS_MF8_E8, 2094 },
|
|
{ PseudoVREMU_VV_M1_E16, 2095 },
|
|
{ PseudoVREMU_VV_M1_E32, 2096 },
|
|
{ PseudoVREMU_VV_M1_E64, 2097 },
|
|
{ PseudoVREMU_VV_M1_E8, 2098 },
|
|
{ PseudoVREMU_VV_M2_E16, 2099 },
|
|
{ PseudoVREMU_VV_M2_E32, 2100 },
|
|
{ PseudoVREMU_VV_M2_E64, 2101 },
|
|
{ PseudoVREMU_VV_M2_E8, 2102 },
|
|
{ PseudoVREMU_VV_M4_E16, 2103 },
|
|
{ PseudoVREMU_VV_M4_E32, 2104 },
|
|
{ PseudoVREMU_VV_M4_E64, 2105 },
|
|
{ PseudoVREMU_VV_M4_E8, 2106 },
|
|
{ PseudoVREMU_VV_M8_E16, 2107 },
|
|
{ PseudoVREMU_VV_M8_E32, 2108 },
|
|
{ PseudoVREMU_VV_M8_E64, 2109 },
|
|
{ PseudoVREMU_VV_M8_E8, 2110 },
|
|
{ PseudoVREMU_VV_MF2_E16, 2111 },
|
|
{ PseudoVREMU_VV_MF2_E32, 2112 },
|
|
{ PseudoVREMU_VV_MF2_E8, 2113 },
|
|
{ PseudoVREMU_VV_MF4_E16, 2114 },
|
|
{ PseudoVREMU_VV_MF4_E8, 2115 },
|
|
{ PseudoVREMU_VV_MF8_E8, 2116 },
|
|
{ PseudoVREMU_VX_M1_E16, 2117 },
|
|
{ PseudoVREMU_VX_M1_E32, 2118 },
|
|
{ PseudoVREMU_VX_M1_E64, 2119 },
|
|
{ PseudoVREMU_VX_M1_E8, 2120 },
|
|
{ PseudoVREMU_VX_M2_E16, 2121 },
|
|
{ PseudoVREMU_VX_M2_E32, 2122 },
|
|
{ PseudoVREMU_VX_M2_E64, 2123 },
|
|
{ PseudoVREMU_VX_M2_E8, 2124 },
|
|
{ PseudoVREMU_VX_M4_E16, 2125 },
|
|
{ PseudoVREMU_VX_M4_E32, 2126 },
|
|
{ PseudoVREMU_VX_M4_E64, 2127 },
|
|
{ PseudoVREMU_VX_M4_E8, 2128 },
|
|
{ PseudoVREMU_VX_M8_E16, 2129 },
|
|
{ PseudoVREMU_VX_M8_E32, 2130 },
|
|
{ PseudoVREMU_VX_M8_E64, 2131 },
|
|
{ PseudoVREMU_VX_M8_E8, 2132 },
|
|
{ PseudoVREMU_VX_MF2_E16, 2133 },
|
|
{ PseudoVREMU_VX_MF2_E32, 2134 },
|
|
{ PseudoVREMU_VX_MF2_E8, 2135 },
|
|
{ PseudoVREMU_VX_MF4_E16, 2136 },
|
|
{ PseudoVREMU_VX_MF4_E8, 2137 },
|
|
{ PseudoVREMU_VX_MF8_E8, 2138 },
|
|
{ PseudoVREM_VV_M1_E16, 2139 },
|
|
{ PseudoVREM_VV_M1_E32, 2140 },
|
|
{ PseudoVREM_VV_M1_E64, 2141 },
|
|
{ PseudoVREM_VV_M1_E8, 2142 },
|
|
{ PseudoVREM_VV_M2_E16, 2143 },
|
|
{ PseudoVREM_VV_M2_E32, 2144 },
|
|
{ PseudoVREM_VV_M2_E64, 2145 },
|
|
{ PseudoVREM_VV_M2_E8, 2146 },
|
|
{ PseudoVREM_VV_M4_E16, 2147 },
|
|
{ PseudoVREM_VV_M4_E32, 2148 },
|
|
{ PseudoVREM_VV_M4_E64, 2149 },
|
|
{ PseudoVREM_VV_M4_E8, 2150 },
|
|
{ PseudoVREM_VV_M8_E16, 2151 },
|
|
{ PseudoVREM_VV_M8_E32, 2152 },
|
|
{ PseudoVREM_VV_M8_E64, 2153 },
|
|
{ PseudoVREM_VV_M8_E8, 2154 },
|
|
{ PseudoVREM_VV_MF2_E16, 2155 },
|
|
{ PseudoVREM_VV_MF2_E32, 2156 },
|
|
{ PseudoVREM_VV_MF2_E8, 2157 },
|
|
{ PseudoVREM_VV_MF4_E16, 2158 },
|
|
{ PseudoVREM_VV_MF4_E8, 2159 },
|
|
{ PseudoVREM_VV_MF8_E8, 2160 },
|
|
{ PseudoVREM_VX_M1_E16, 2161 },
|
|
{ PseudoVREM_VX_M1_E32, 2162 },
|
|
{ PseudoVREM_VX_M1_E64, 2163 },
|
|
{ PseudoVREM_VX_M1_E8, 2164 },
|
|
{ PseudoVREM_VX_M2_E16, 2165 },
|
|
{ PseudoVREM_VX_M2_E32, 2166 },
|
|
{ PseudoVREM_VX_M2_E64, 2167 },
|
|
{ PseudoVREM_VX_M2_E8, 2168 },
|
|
{ PseudoVREM_VX_M4_E16, 2169 },
|
|
{ PseudoVREM_VX_M4_E32, 2170 },
|
|
{ PseudoVREM_VX_M4_E64, 2171 },
|
|
{ PseudoVREM_VX_M4_E8, 2172 },
|
|
{ PseudoVREM_VX_M8_E16, 2173 },
|
|
{ PseudoVREM_VX_M8_E32, 2174 },
|
|
{ PseudoVREM_VX_M8_E64, 2175 },
|
|
{ PseudoVREM_VX_M8_E8, 2176 },
|
|
{ PseudoVREM_VX_MF2_E16, 2177 },
|
|
{ PseudoVREM_VX_MF2_E32, 2178 },
|
|
{ PseudoVREM_VX_MF2_E8, 2179 },
|
|
{ PseudoVREM_VX_MF4_E16, 2180 },
|
|
{ PseudoVREM_VX_MF4_E8, 2181 },
|
|
{ PseudoVREM_VX_MF8_E8, 2182 },
|
|
{ PseudoVREV8_V_M1, 2183 },
|
|
{ PseudoVREV8_V_M2, 2184 },
|
|
{ PseudoVREV8_V_M4, 2185 },
|
|
{ PseudoVREV8_V_M8, 2186 },
|
|
{ PseudoVREV8_V_MF2, 2187 },
|
|
{ PseudoVREV8_V_MF4, 2188 },
|
|
{ PseudoVREV8_V_MF8, 2189 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M1, 2190 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M2, 2191 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF2, 2192 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF4, 2193 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M1, 2194 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M2, 2195 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF2, 2196 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF4, 2197 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M1, 2198 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M2, 2199 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF2, 2200 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF4, 2201 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M1, 2202 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M2, 2203 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF2, 2204 },
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF4, 2205 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M1, 2206 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M2, 2207 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M4, 2208 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_MF2, 2209 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M1, 2210 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M2, 2211 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M4, 2212 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_MF2, 2213 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M1, 2214 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M2, 2215 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M4, 2216 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_MF2, 2217 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M1, 2218 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M2, 2219 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M4, 2220 },
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_MF2, 2221 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M1, 2222 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M2, 2223 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M4, 2224 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M8, 2225 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M1, 2226 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M2, 2227 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M4, 2228 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M8, 2229 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M1, 2230 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M2, 2231 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M4, 2232 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M8, 2233 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M1, 2234 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M2, 2235 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M4, 2236 },
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M8, 2237 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M2, 2238 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M4, 2239 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M8, 2240 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M2, 2241 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M4, 2242 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M8, 2243 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M2, 2244 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M4, 2245 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M8, 2246 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M2, 2247 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M4, 2248 },
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M8, 2249 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_M1, 2250 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF2, 2251 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF4, 2252 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF8, 2253 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_M1, 2254 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF2, 2255 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF4, 2256 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF8, 2257 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_M1, 2258 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF2, 2259 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF4, 2260 },
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF8, 2261 },
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF2, 2262 },
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF4, 2263 },
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF8, 2264 },
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF2, 2265 },
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF4, 2266 },
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF8, 2267 },
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF4, 2268 },
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF8, 2269 },
|
|
{ PseudoVRGATHER_VI_M1, 2270 },
|
|
{ PseudoVRGATHER_VI_M2, 2271 },
|
|
{ PseudoVRGATHER_VI_M4, 2272 },
|
|
{ PseudoVRGATHER_VI_M8, 2273 },
|
|
{ PseudoVRGATHER_VI_MF2, 2274 },
|
|
{ PseudoVRGATHER_VI_MF4, 2275 },
|
|
{ PseudoVRGATHER_VI_MF8, 2276 },
|
|
{ PseudoVRGATHER_VV_M1_E16, 2277 },
|
|
{ PseudoVRGATHER_VV_M1_E32, 2278 },
|
|
{ PseudoVRGATHER_VV_M1_E64, 2279 },
|
|
{ PseudoVRGATHER_VV_M1_E8, 2280 },
|
|
{ PseudoVRGATHER_VV_M2_E16, 2281 },
|
|
{ PseudoVRGATHER_VV_M2_E32, 2282 },
|
|
{ PseudoVRGATHER_VV_M2_E64, 2283 },
|
|
{ PseudoVRGATHER_VV_M2_E8, 2284 },
|
|
{ PseudoVRGATHER_VV_M4_E16, 2285 },
|
|
{ PseudoVRGATHER_VV_M4_E32, 2286 },
|
|
{ PseudoVRGATHER_VV_M4_E64, 2287 },
|
|
{ PseudoVRGATHER_VV_M4_E8, 2288 },
|
|
{ PseudoVRGATHER_VV_M8_E16, 2289 },
|
|
{ PseudoVRGATHER_VV_M8_E32, 2290 },
|
|
{ PseudoVRGATHER_VV_M8_E64, 2291 },
|
|
{ PseudoVRGATHER_VV_M8_E8, 2292 },
|
|
{ PseudoVRGATHER_VV_MF2_E16, 2293 },
|
|
{ PseudoVRGATHER_VV_MF2_E32, 2294 },
|
|
{ PseudoVRGATHER_VV_MF2_E8, 2295 },
|
|
{ PseudoVRGATHER_VV_MF4_E16, 2296 },
|
|
{ PseudoVRGATHER_VV_MF4_E8, 2297 },
|
|
{ PseudoVRGATHER_VV_MF8_E8, 2298 },
|
|
{ PseudoVRGATHER_VX_M1, 2299 },
|
|
{ PseudoVRGATHER_VX_M2, 2300 },
|
|
{ PseudoVRGATHER_VX_M4, 2301 },
|
|
{ PseudoVRGATHER_VX_M8, 2302 },
|
|
{ PseudoVRGATHER_VX_MF2, 2303 },
|
|
{ PseudoVRGATHER_VX_MF4, 2304 },
|
|
{ PseudoVRGATHER_VX_MF8, 2305 },
|
|
{ PseudoVROL_VV_M1, 2306 },
|
|
{ PseudoVROL_VV_M2, 2307 },
|
|
{ PseudoVROL_VV_M4, 2308 },
|
|
{ PseudoVROL_VV_M8, 2309 },
|
|
{ PseudoVROL_VV_MF2, 2310 },
|
|
{ PseudoVROL_VV_MF4, 2311 },
|
|
{ PseudoVROL_VV_MF8, 2312 },
|
|
{ PseudoVROL_VX_M1, 2313 },
|
|
{ PseudoVROL_VX_M2, 2314 },
|
|
{ PseudoVROL_VX_M4, 2315 },
|
|
{ PseudoVROL_VX_M8, 2316 },
|
|
{ PseudoVROL_VX_MF2, 2317 },
|
|
{ PseudoVROL_VX_MF4, 2318 },
|
|
{ PseudoVROL_VX_MF8, 2319 },
|
|
{ PseudoVROR_VI_M1, 2320 },
|
|
{ PseudoVROR_VI_M2, 2321 },
|
|
{ PseudoVROR_VI_M4, 2322 },
|
|
{ PseudoVROR_VI_M8, 2323 },
|
|
{ PseudoVROR_VI_MF2, 2324 },
|
|
{ PseudoVROR_VI_MF4, 2325 },
|
|
{ PseudoVROR_VI_MF8, 2326 },
|
|
{ PseudoVROR_VV_M1, 2327 },
|
|
{ PseudoVROR_VV_M2, 2328 },
|
|
{ PseudoVROR_VV_M4, 2329 },
|
|
{ PseudoVROR_VV_M8, 2330 },
|
|
{ PseudoVROR_VV_MF2, 2331 },
|
|
{ PseudoVROR_VV_MF4, 2332 },
|
|
{ PseudoVROR_VV_MF8, 2333 },
|
|
{ PseudoVROR_VX_M1, 2334 },
|
|
{ PseudoVROR_VX_M2, 2335 },
|
|
{ PseudoVROR_VX_M4, 2336 },
|
|
{ PseudoVROR_VX_M8, 2337 },
|
|
{ PseudoVROR_VX_MF2, 2338 },
|
|
{ PseudoVROR_VX_MF4, 2339 },
|
|
{ PseudoVROR_VX_MF8, 2340 },
|
|
{ PseudoVRSUB_VI_M1, 2341 },
|
|
{ PseudoVRSUB_VI_M2, 2342 },
|
|
{ PseudoVRSUB_VI_M4, 2343 },
|
|
{ PseudoVRSUB_VI_M8, 2344 },
|
|
{ PseudoVRSUB_VI_MF2, 2345 },
|
|
{ PseudoVRSUB_VI_MF4, 2346 },
|
|
{ PseudoVRSUB_VI_MF8, 2347 },
|
|
{ PseudoVRSUB_VX_M1, 2348 },
|
|
{ PseudoVRSUB_VX_M2, 2349 },
|
|
{ PseudoVRSUB_VX_M4, 2350 },
|
|
{ PseudoVRSUB_VX_M8, 2351 },
|
|
{ PseudoVRSUB_VX_MF2, 2352 },
|
|
{ PseudoVRSUB_VX_MF4, 2353 },
|
|
{ PseudoVRSUB_VX_MF8, 2354 },
|
|
{ PseudoVSADDU_VI_M1, 2355 },
|
|
{ PseudoVSADDU_VI_M2, 2356 },
|
|
{ PseudoVSADDU_VI_M4, 2357 },
|
|
{ PseudoVSADDU_VI_M8, 2358 },
|
|
{ PseudoVSADDU_VI_MF2, 2359 },
|
|
{ PseudoVSADDU_VI_MF4, 2360 },
|
|
{ PseudoVSADDU_VI_MF8, 2361 },
|
|
{ PseudoVSADDU_VV_M1, 2362 },
|
|
{ PseudoVSADDU_VV_M2, 2363 },
|
|
{ PseudoVSADDU_VV_M4, 2364 },
|
|
{ PseudoVSADDU_VV_M8, 2365 },
|
|
{ PseudoVSADDU_VV_MF2, 2366 },
|
|
{ PseudoVSADDU_VV_MF4, 2367 },
|
|
{ PseudoVSADDU_VV_MF8, 2368 },
|
|
{ PseudoVSADDU_VX_M1, 2369 },
|
|
{ PseudoVSADDU_VX_M2, 2370 },
|
|
{ PseudoVSADDU_VX_M4, 2371 },
|
|
{ PseudoVSADDU_VX_M8, 2372 },
|
|
{ PseudoVSADDU_VX_MF2, 2373 },
|
|
{ PseudoVSADDU_VX_MF4, 2374 },
|
|
{ PseudoVSADDU_VX_MF8, 2375 },
|
|
{ PseudoVSADD_VI_M1, 2376 },
|
|
{ PseudoVSADD_VI_M2, 2377 },
|
|
{ PseudoVSADD_VI_M4, 2378 },
|
|
{ PseudoVSADD_VI_M8, 2379 },
|
|
{ PseudoVSADD_VI_MF2, 2380 },
|
|
{ PseudoVSADD_VI_MF4, 2381 },
|
|
{ PseudoVSADD_VI_MF8, 2382 },
|
|
{ PseudoVSADD_VV_M1, 2383 },
|
|
{ PseudoVSADD_VV_M2, 2384 },
|
|
{ PseudoVSADD_VV_M4, 2385 },
|
|
{ PseudoVSADD_VV_M8, 2386 },
|
|
{ PseudoVSADD_VV_MF2, 2387 },
|
|
{ PseudoVSADD_VV_MF4, 2388 },
|
|
{ PseudoVSADD_VV_MF8, 2389 },
|
|
{ PseudoVSADD_VX_M1, 2390 },
|
|
{ PseudoVSADD_VX_M2, 2391 },
|
|
{ PseudoVSADD_VX_M4, 2392 },
|
|
{ PseudoVSADD_VX_M8, 2393 },
|
|
{ PseudoVSADD_VX_MF2, 2394 },
|
|
{ PseudoVSADD_VX_MF4, 2395 },
|
|
{ PseudoVSADD_VX_MF8, 2396 },
|
|
{ PseudoVSEXT_VF2_M1, 2397 },
|
|
{ PseudoVSEXT_VF2_M2, 2398 },
|
|
{ PseudoVSEXT_VF2_M4, 2399 },
|
|
{ PseudoVSEXT_VF2_M8, 2400 },
|
|
{ PseudoVSEXT_VF2_MF2, 2401 },
|
|
{ PseudoVSEXT_VF2_MF4, 2402 },
|
|
{ PseudoVSEXT_VF4_M1, 2403 },
|
|
{ PseudoVSEXT_VF4_M2, 2404 },
|
|
{ PseudoVSEXT_VF4_M4, 2405 },
|
|
{ PseudoVSEXT_VF4_M8, 2406 },
|
|
{ PseudoVSEXT_VF4_MF2, 2407 },
|
|
{ PseudoVSEXT_VF8_M1, 2408 },
|
|
{ PseudoVSEXT_VF8_M2, 2409 },
|
|
{ PseudoVSEXT_VF8_M4, 2410 },
|
|
{ PseudoVSEXT_VF8_M8, 2411 },
|
|
{ PseudoVSLIDE1DOWN_VX_M1, 2412 },
|
|
{ PseudoVSLIDE1DOWN_VX_M2, 2413 },
|
|
{ PseudoVSLIDE1DOWN_VX_M4, 2414 },
|
|
{ PseudoVSLIDE1DOWN_VX_M8, 2415 },
|
|
{ PseudoVSLIDE1DOWN_VX_MF2, 2416 },
|
|
{ PseudoVSLIDE1DOWN_VX_MF4, 2417 },
|
|
{ PseudoVSLIDE1DOWN_VX_MF8, 2418 },
|
|
{ PseudoVSLIDE1UP_VX_M1, 2419 },
|
|
{ PseudoVSLIDE1UP_VX_M2, 2420 },
|
|
{ PseudoVSLIDE1UP_VX_M4, 2421 },
|
|
{ PseudoVSLIDE1UP_VX_M8, 2422 },
|
|
{ PseudoVSLIDE1UP_VX_MF2, 2423 },
|
|
{ PseudoVSLIDE1UP_VX_MF4, 2424 },
|
|
{ PseudoVSLIDE1UP_VX_MF8, 2425 },
|
|
{ PseudoVSLIDEDOWN_VI_M1, 2426 },
|
|
{ PseudoVSLIDEDOWN_VI_M2, 2427 },
|
|
{ PseudoVSLIDEDOWN_VI_M4, 2428 },
|
|
{ PseudoVSLIDEDOWN_VI_M8, 2429 },
|
|
{ PseudoVSLIDEDOWN_VI_MF2, 2430 },
|
|
{ PseudoVSLIDEDOWN_VI_MF4, 2431 },
|
|
{ PseudoVSLIDEDOWN_VI_MF8, 2432 },
|
|
{ PseudoVSLIDEDOWN_VX_M1, 2433 },
|
|
{ PseudoVSLIDEDOWN_VX_M2, 2434 },
|
|
{ PseudoVSLIDEDOWN_VX_M4, 2435 },
|
|
{ PseudoVSLIDEDOWN_VX_M8, 2436 },
|
|
{ PseudoVSLIDEDOWN_VX_MF2, 2437 },
|
|
{ PseudoVSLIDEDOWN_VX_MF4, 2438 },
|
|
{ PseudoVSLIDEDOWN_VX_MF8, 2439 },
|
|
{ PseudoVSLIDEUP_VI_M1, 2440 },
|
|
{ PseudoVSLIDEUP_VI_M2, 2441 },
|
|
{ PseudoVSLIDEUP_VI_M4, 2442 },
|
|
{ PseudoVSLIDEUP_VI_M8, 2443 },
|
|
{ PseudoVSLIDEUP_VI_MF2, 2444 },
|
|
{ PseudoVSLIDEUP_VI_MF4, 2445 },
|
|
{ PseudoVSLIDEUP_VI_MF8, 2446 },
|
|
{ PseudoVSLIDEUP_VX_M1, 2447 },
|
|
{ PseudoVSLIDEUP_VX_M2, 2448 },
|
|
{ PseudoVSLIDEUP_VX_M4, 2449 },
|
|
{ PseudoVSLIDEUP_VX_M8, 2450 },
|
|
{ PseudoVSLIDEUP_VX_MF2, 2451 },
|
|
{ PseudoVSLIDEUP_VX_MF4, 2452 },
|
|
{ PseudoVSLIDEUP_VX_MF8, 2453 },
|
|
{ PseudoVSLL_VI_M1, 2454 },
|
|
{ PseudoVSLL_VI_M2, 2455 },
|
|
{ PseudoVSLL_VI_M4, 2456 },
|
|
{ PseudoVSLL_VI_M8, 2457 },
|
|
{ PseudoVSLL_VI_MF2, 2458 },
|
|
{ PseudoVSLL_VI_MF4, 2459 },
|
|
{ PseudoVSLL_VI_MF8, 2460 },
|
|
{ PseudoVSLL_VV_M1, 2461 },
|
|
{ PseudoVSLL_VV_M2, 2462 },
|
|
{ PseudoVSLL_VV_M4, 2463 },
|
|
{ PseudoVSLL_VV_M8, 2464 },
|
|
{ PseudoVSLL_VV_MF2, 2465 },
|
|
{ PseudoVSLL_VV_MF4, 2466 },
|
|
{ PseudoVSLL_VV_MF8, 2467 },
|
|
{ PseudoVSLL_VX_M1, 2468 },
|
|
{ PseudoVSLL_VX_M2, 2469 },
|
|
{ PseudoVSLL_VX_M4, 2470 },
|
|
{ PseudoVSLL_VX_M8, 2471 },
|
|
{ PseudoVSLL_VX_MF2, 2472 },
|
|
{ PseudoVSLL_VX_MF4, 2473 },
|
|
{ PseudoVSLL_VX_MF8, 2474 },
|
|
{ PseudoVSMUL_VV_M1, 2475 },
|
|
{ PseudoVSMUL_VV_M2, 2476 },
|
|
{ PseudoVSMUL_VV_M4, 2477 },
|
|
{ PseudoVSMUL_VV_M8, 2478 },
|
|
{ PseudoVSMUL_VV_MF2, 2479 },
|
|
{ PseudoVSMUL_VV_MF4, 2480 },
|
|
{ PseudoVSMUL_VV_MF8, 2481 },
|
|
{ PseudoVSMUL_VX_M1, 2482 },
|
|
{ PseudoVSMUL_VX_M2, 2483 },
|
|
{ PseudoVSMUL_VX_M4, 2484 },
|
|
{ PseudoVSMUL_VX_M8, 2485 },
|
|
{ PseudoVSMUL_VX_MF2, 2486 },
|
|
{ PseudoVSMUL_VX_MF4, 2487 },
|
|
{ PseudoVSMUL_VX_MF8, 2488 },
|
|
{ PseudoVSRA_VI_M1, 2489 },
|
|
{ PseudoVSRA_VI_M2, 2490 },
|
|
{ PseudoVSRA_VI_M4, 2491 },
|
|
{ PseudoVSRA_VI_M8, 2492 },
|
|
{ PseudoVSRA_VI_MF2, 2493 },
|
|
{ PseudoVSRA_VI_MF4, 2494 },
|
|
{ PseudoVSRA_VI_MF8, 2495 },
|
|
{ PseudoVSRA_VV_M1, 2496 },
|
|
{ PseudoVSRA_VV_M2, 2497 },
|
|
{ PseudoVSRA_VV_M4, 2498 },
|
|
{ PseudoVSRA_VV_M8, 2499 },
|
|
{ PseudoVSRA_VV_MF2, 2500 },
|
|
{ PseudoVSRA_VV_MF4, 2501 },
|
|
{ PseudoVSRA_VV_MF8, 2502 },
|
|
{ PseudoVSRA_VX_M1, 2503 },
|
|
{ PseudoVSRA_VX_M2, 2504 },
|
|
{ PseudoVSRA_VX_M4, 2505 },
|
|
{ PseudoVSRA_VX_M8, 2506 },
|
|
{ PseudoVSRA_VX_MF2, 2507 },
|
|
{ PseudoVSRA_VX_MF4, 2508 },
|
|
{ PseudoVSRA_VX_MF8, 2509 },
|
|
{ PseudoVSRL_VI_M1, 2510 },
|
|
{ PseudoVSRL_VI_M2, 2511 },
|
|
{ PseudoVSRL_VI_M4, 2512 },
|
|
{ PseudoVSRL_VI_M8, 2513 },
|
|
{ PseudoVSRL_VI_MF2, 2514 },
|
|
{ PseudoVSRL_VI_MF4, 2515 },
|
|
{ PseudoVSRL_VI_MF8, 2516 },
|
|
{ PseudoVSRL_VV_M1, 2517 },
|
|
{ PseudoVSRL_VV_M2, 2518 },
|
|
{ PseudoVSRL_VV_M4, 2519 },
|
|
{ PseudoVSRL_VV_M8, 2520 },
|
|
{ PseudoVSRL_VV_MF2, 2521 },
|
|
{ PseudoVSRL_VV_MF4, 2522 },
|
|
{ PseudoVSRL_VV_MF8, 2523 },
|
|
{ PseudoVSRL_VX_M1, 2524 },
|
|
{ PseudoVSRL_VX_M2, 2525 },
|
|
{ PseudoVSRL_VX_M4, 2526 },
|
|
{ PseudoVSRL_VX_M8, 2527 },
|
|
{ PseudoVSRL_VX_MF2, 2528 },
|
|
{ PseudoVSRL_VX_MF4, 2529 },
|
|
{ PseudoVSRL_VX_MF8, 2530 },
|
|
{ PseudoVSSRA_VI_M1, 2531 },
|
|
{ PseudoVSSRA_VI_M2, 2532 },
|
|
{ PseudoVSSRA_VI_M4, 2533 },
|
|
{ PseudoVSSRA_VI_M8, 2534 },
|
|
{ PseudoVSSRA_VI_MF2, 2535 },
|
|
{ PseudoVSSRA_VI_MF4, 2536 },
|
|
{ PseudoVSSRA_VI_MF8, 2537 },
|
|
{ PseudoVSSRA_VV_M1, 2538 },
|
|
{ PseudoVSSRA_VV_M2, 2539 },
|
|
{ PseudoVSSRA_VV_M4, 2540 },
|
|
{ PseudoVSSRA_VV_M8, 2541 },
|
|
{ PseudoVSSRA_VV_MF2, 2542 },
|
|
{ PseudoVSSRA_VV_MF4, 2543 },
|
|
{ PseudoVSSRA_VV_MF8, 2544 },
|
|
{ PseudoVSSRA_VX_M1, 2545 },
|
|
{ PseudoVSSRA_VX_M2, 2546 },
|
|
{ PseudoVSSRA_VX_M4, 2547 },
|
|
{ PseudoVSSRA_VX_M8, 2548 },
|
|
{ PseudoVSSRA_VX_MF2, 2549 },
|
|
{ PseudoVSSRA_VX_MF4, 2550 },
|
|
{ PseudoVSSRA_VX_MF8, 2551 },
|
|
{ PseudoVSSRL_VI_M1, 2552 },
|
|
{ PseudoVSSRL_VI_M2, 2553 },
|
|
{ PseudoVSSRL_VI_M4, 2554 },
|
|
{ PseudoVSSRL_VI_M8, 2555 },
|
|
{ PseudoVSSRL_VI_MF2, 2556 },
|
|
{ PseudoVSSRL_VI_MF4, 2557 },
|
|
{ PseudoVSSRL_VI_MF8, 2558 },
|
|
{ PseudoVSSRL_VV_M1, 2559 },
|
|
{ PseudoVSSRL_VV_M2, 2560 },
|
|
{ PseudoVSSRL_VV_M4, 2561 },
|
|
{ PseudoVSSRL_VV_M8, 2562 },
|
|
{ PseudoVSSRL_VV_MF2, 2563 },
|
|
{ PseudoVSSRL_VV_MF4, 2564 },
|
|
{ PseudoVSSRL_VV_MF8, 2565 },
|
|
{ PseudoVSSRL_VX_M1, 2566 },
|
|
{ PseudoVSSRL_VX_M2, 2567 },
|
|
{ PseudoVSSRL_VX_M4, 2568 },
|
|
{ PseudoVSSRL_VX_M8, 2569 },
|
|
{ PseudoVSSRL_VX_MF2, 2570 },
|
|
{ PseudoVSSRL_VX_MF4, 2571 },
|
|
{ PseudoVSSRL_VX_MF8, 2572 },
|
|
{ PseudoVSSUBU_VV_M1, 2573 },
|
|
{ PseudoVSSUBU_VV_M2, 2574 },
|
|
{ PseudoVSSUBU_VV_M4, 2575 },
|
|
{ PseudoVSSUBU_VV_M8, 2576 },
|
|
{ PseudoVSSUBU_VV_MF2, 2577 },
|
|
{ PseudoVSSUBU_VV_MF4, 2578 },
|
|
{ PseudoVSSUBU_VV_MF8, 2579 },
|
|
{ PseudoVSSUBU_VX_M1, 2580 },
|
|
{ PseudoVSSUBU_VX_M2, 2581 },
|
|
{ PseudoVSSUBU_VX_M4, 2582 },
|
|
{ PseudoVSSUBU_VX_M8, 2583 },
|
|
{ PseudoVSSUBU_VX_MF2, 2584 },
|
|
{ PseudoVSSUBU_VX_MF4, 2585 },
|
|
{ PseudoVSSUBU_VX_MF8, 2586 },
|
|
{ PseudoVSSUB_VV_M1, 2587 },
|
|
{ PseudoVSSUB_VV_M2, 2588 },
|
|
{ PseudoVSSUB_VV_M4, 2589 },
|
|
{ PseudoVSSUB_VV_M8, 2590 },
|
|
{ PseudoVSSUB_VV_MF2, 2591 },
|
|
{ PseudoVSSUB_VV_MF4, 2592 },
|
|
{ PseudoVSSUB_VV_MF8, 2593 },
|
|
{ PseudoVSSUB_VX_M1, 2594 },
|
|
{ PseudoVSSUB_VX_M2, 2595 },
|
|
{ PseudoVSSUB_VX_M4, 2596 },
|
|
{ PseudoVSSUB_VX_M8, 2597 },
|
|
{ PseudoVSSUB_VX_MF2, 2598 },
|
|
{ PseudoVSSUB_VX_MF4, 2599 },
|
|
{ PseudoVSSUB_VX_MF8, 2600 },
|
|
{ PseudoVSUB_VV_M1, 2601 },
|
|
{ PseudoVSUB_VV_M2, 2602 },
|
|
{ PseudoVSUB_VV_M4, 2603 },
|
|
{ PseudoVSUB_VV_M8, 2604 },
|
|
{ PseudoVSUB_VV_MF2, 2605 },
|
|
{ PseudoVSUB_VV_MF4, 2606 },
|
|
{ PseudoVSUB_VV_MF8, 2607 },
|
|
{ PseudoVSUB_VX_M1, 2608 },
|
|
{ PseudoVSUB_VX_M2, 2609 },
|
|
{ PseudoVSUB_VX_M4, 2610 },
|
|
{ PseudoVSUB_VX_M8, 2611 },
|
|
{ PseudoVSUB_VX_MF2, 2612 },
|
|
{ PseudoVSUB_VX_MF4, 2613 },
|
|
{ PseudoVSUB_VX_MF8, 2614 },
|
|
{ PseudoVWADDU_VV_M1, 2615 },
|
|
{ PseudoVWADDU_VV_M2, 2616 },
|
|
{ PseudoVWADDU_VV_M4, 2617 },
|
|
{ PseudoVWADDU_VV_MF2, 2618 },
|
|
{ PseudoVWADDU_VV_MF4, 2619 },
|
|
{ PseudoVWADDU_VV_MF8, 2620 },
|
|
{ PseudoVWADDU_VX_M1, 2621 },
|
|
{ PseudoVWADDU_VX_M2, 2622 },
|
|
{ PseudoVWADDU_VX_M4, 2623 },
|
|
{ PseudoVWADDU_VX_MF2, 2624 },
|
|
{ PseudoVWADDU_VX_MF4, 2625 },
|
|
{ PseudoVWADDU_VX_MF8, 2626 },
|
|
{ PseudoVWADDU_WV_M1, 2627 },
|
|
{ PseudoVWADDU_WV_M2, 2628 },
|
|
{ PseudoVWADDU_WV_M4, 2629 },
|
|
{ PseudoVWADDU_WV_MF2, 2630 },
|
|
{ PseudoVWADDU_WV_MF4, 2631 },
|
|
{ PseudoVWADDU_WV_MF8, 2632 },
|
|
{ PseudoVWADDU_WX_M1, 2633 },
|
|
{ PseudoVWADDU_WX_M2, 2634 },
|
|
{ PseudoVWADDU_WX_M4, 2635 },
|
|
{ PseudoVWADDU_WX_MF2, 2636 },
|
|
{ PseudoVWADDU_WX_MF4, 2637 },
|
|
{ PseudoVWADDU_WX_MF8, 2638 },
|
|
{ PseudoVWADD_VV_M1, 2639 },
|
|
{ PseudoVWADD_VV_M2, 2640 },
|
|
{ PseudoVWADD_VV_M4, 2641 },
|
|
{ PseudoVWADD_VV_MF2, 2642 },
|
|
{ PseudoVWADD_VV_MF4, 2643 },
|
|
{ PseudoVWADD_VV_MF8, 2644 },
|
|
{ PseudoVWADD_VX_M1, 2645 },
|
|
{ PseudoVWADD_VX_M2, 2646 },
|
|
{ PseudoVWADD_VX_M4, 2647 },
|
|
{ PseudoVWADD_VX_MF2, 2648 },
|
|
{ PseudoVWADD_VX_MF4, 2649 },
|
|
{ PseudoVWADD_VX_MF8, 2650 },
|
|
{ PseudoVWADD_WV_M1, 2651 },
|
|
{ PseudoVWADD_WV_M2, 2652 },
|
|
{ PseudoVWADD_WV_M4, 2653 },
|
|
{ PseudoVWADD_WV_MF2, 2654 },
|
|
{ PseudoVWADD_WV_MF4, 2655 },
|
|
{ PseudoVWADD_WV_MF8, 2656 },
|
|
{ PseudoVWADD_WX_M1, 2657 },
|
|
{ PseudoVWADD_WX_M2, 2658 },
|
|
{ PseudoVWADD_WX_M4, 2659 },
|
|
{ PseudoVWADD_WX_MF2, 2660 },
|
|
{ PseudoVWADD_WX_MF4, 2661 },
|
|
{ PseudoVWADD_WX_MF8, 2662 },
|
|
{ PseudoVWMACCSU_VV_M1, 2663 },
|
|
{ PseudoVWMACCSU_VV_M2, 2664 },
|
|
{ PseudoVWMACCSU_VV_M4, 2665 },
|
|
{ PseudoVWMACCSU_VV_MF2, 2666 },
|
|
{ PseudoVWMACCSU_VV_MF4, 2667 },
|
|
{ PseudoVWMACCSU_VV_MF8, 2668 },
|
|
{ PseudoVWMACCSU_VX_M1, 2669 },
|
|
{ PseudoVWMACCSU_VX_M2, 2670 },
|
|
{ PseudoVWMACCSU_VX_M4, 2671 },
|
|
{ PseudoVWMACCSU_VX_MF2, 2672 },
|
|
{ PseudoVWMACCSU_VX_MF4, 2673 },
|
|
{ PseudoVWMACCSU_VX_MF8, 2674 },
|
|
{ PseudoVWMACCUS_VX_M1, 2675 },
|
|
{ PseudoVWMACCUS_VX_M2, 2676 },
|
|
{ PseudoVWMACCUS_VX_M4, 2677 },
|
|
{ PseudoVWMACCUS_VX_MF2, 2678 },
|
|
{ PseudoVWMACCUS_VX_MF4, 2679 },
|
|
{ PseudoVWMACCUS_VX_MF8, 2680 },
|
|
{ PseudoVWMACCU_VV_M1, 2681 },
|
|
{ PseudoVWMACCU_VV_M2, 2682 },
|
|
{ PseudoVWMACCU_VV_M4, 2683 },
|
|
{ PseudoVWMACCU_VV_MF2, 2684 },
|
|
{ PseudoVWMACCU_VV_MF4, 2685 },
|
|
{ PseudoVWMACCU_VV_MF8, 2686 },
|
|
{ PseudoVWMACCU_VX_M1, 2687 },
|
|
{ PseudoVWMACCU_VX_M2, 2688 },
|
|
{ PseudoVWMACCU_VX_M4, 2689 },
|
|
{ PseudoVWMACCU_VX_MF2, 2690 },
|
|
{ PseudoVWMACCU_VX_MF4, 2691 },
|
|
{ PseudoVWMACCU_VX_MF8, 2692 },
|
|
{ PseudoVWMACC_VV_M1, 2693 },
|
|
{ PseudoVWMACC_VV_M2, 2694 },
|
|
{ PseudoVWMACC_VV_M4, 2695 },
|
|
{ PseudoVWMACC_VV_MF2, 2696 },
|
|
{ PseudoVWMACC_VV_MF4, 2697 },
|
|
{ PseudoVWMACC_VV_MF8, 2698 },
|
|
{ PseudoVWMACC_VX_M1, 2699 },
|
|
{ PseudoVWMACC_VX_M2, 2700 },
|
|
{ PseudoVWMACC_VX_M4, 2701 },
|
|
{ PseudoVWMACC_VX_MF2, 2702 },
|
|
{ PseudoVWMACC_VX_MF4, 2703 },
|
|
{ PseudoVWMACC_VX_MF8, 2704 },
|
|
{ PseudoVWMULSU_VV_M1, 2705 },
|
|
{ PseudoVWMULSU_VV_M2, 2706 },
|
|
{ PseudoVWMULSU_VV_M4, 2707 },
|
|
{ PseudoVWMULSU_VV_MF2, 2708 },
|
|
{ PseudoVWMULSU_VV_MF4, 2709 },
|
|
{ PseudoVWMULSU_VV_MF8, 2710 },
|
|
{ PseudoVWMULSU_VX_M1, 2711 },
|
|
{ PseudoVWMULSU_VX_M2, 2712 },
|
|
{ PseudoVWMULSU_VX_M4, 2713 },
|
|
{ PseudoVWMULSU_VX_MF2, 2714 },
|
|
{ PseudoVWMULSU_VX_MF4, 2715 },
|
|
{ PseudoVWMULSU_VX_MF8, 2716 },
|
|
{ PseudoVWMULU_VV_M1, 2717 },
|
|
{ PseudoVWMULU_VV_M2, 2718 },
|
|
{ PseudoVWMULU_VV_M4, 2719 },
|
|
{ PseudoVWMULU_VV_MF2, 2720 },
|
|
{ PseudoVWMULU_VV_MF4, 2721 },
|
|
{ PseudoVWMULU_VV_MF8, 2722 },
|
|
{ PseudoVWMULU_VX_M1, 2723 },
|
|
{ PseudoVWMULU_VX_M2, 2724 },
|
|
{ PseudoVWMULU_VX_M4, 2725 },
|
|
{ PseudoVWMULU_VX_MF2, 2726 },
|
|
{ PseudoVWMULU_VX_MF4, 2727 },
|
|
{ PseudoVWMULU_VX_MF8, 2728 },
|
|
{ PseudoVWMUL_VV_M1, 2729 },
|
|
{ PseudoVWMUL_VV_M2, 2730 },
|
|
{ PseudoVWMUL_VV_M4, 2731 },
|
|
{ PseudoVWMUL_VV_MF2, 2732 },
|
|
{ PseudoVWMUL_VV_MF4, 2733 },
|
|
{ PseudoVWMUL_VV_MF8, 2734 },
|
|
{ PseudoVWMUL_VX_M1, 2735 },
|
|
{ PseudoVWMUL_VX_M2, 2736 },
|
|
{ PseudoVWMUL_VX_M4, 2737 },
|
|
{ PseudoVWMUL_VX_MF2, 2738 },
|
|
{ PseudoVWMUL_VX_MF4, 2739 },
|
|
{ PseudoVWMUL_VX_MF8, 2740 },
|
|
{ PseudoVWREDSUMU_VS_M1_E16, 2741 },
|
|
{ PseudoVWREDSUMU_VS_M1_E32, 2742 },
|
|
{ PseudoVWREDSUMU_VS_M1_E8, 2743 },
|
|
{ PseudoVWREDSUMU_VS_M2_E16, 2744 },
|
|
{ PseudoVWREDSUMU_VS_M2_E32, 2745 },
|
|
{ PseudoVWREDSUMU_VS_M2_E8, 2746 },
|
|
{ PseudoVWREDSUMU_VS_M4_E16, 2747 },
|
|
{ PseudoVWREDSUMU_VS_M4_E32, 2748 },
|
|
{ PseudoVWREDSUMU_VS_M4_E8, 2749 },
|
|
{ PseudoVWREDSUMU_VS_M8_E16, 2750 },
|
|
{ PseudoVWREDSUMU_VS_M8_E32, 2751 },
|
|
{ PseudoVWREDSUMU_VS_M8_E8, 2752 },
|
|
{ PseudoVWREDSUMU_VS_MF2_E16, 2753 },
|
|
{ PseudoVWREDSUMU_VS_MF2_E32, 2754 },
|
|
{ PseudoVWREDSUMU_VS_MF2_E8, 2755 },
|
|
{ PseudoVWREDSUMU_VS_MF4_E16, 2756 },
|
|
{ PseudoVWREDSUMU_VS_MF4_E8, 2757 },
|
|
{ PseudoVWREDSUMU_VS_MF8_E8, 2758 },
|
|
{ PseudoVWREDSUM_VS_M1_E16, 2759 },
|
|
{ PseudoVWREDSUM_VS_M1_E32, 2760 },
|
|
{ PseudoVWREDSUM_VS_M1_E8, 2761 },
|
|
{ PseudoVWREDSUM_VS_M2_E16, 2762 },
|
|
{ PseudoVWREDSUM_VS_M2_E32, 2763 },
|
|
{ PseudoVWREDSUM_VS_M2_E8, 2764 },
|
|
{ PseudoVWREDSUM_VS_M4_E16, 2765 },
|
|
{ PseudoVWREDSUM_VS_M4_E32, 2766 },
|
|
{ PseudoVWREDSUM_VS_M4_E8, 2767 },
|
|
{ PseudoVWREDSUM_VS_M8_E16, 2768 },
|
|
{ PseudoVWREDSUM_VS_M8_E32, 2769 },
|
|
{ PseudoVWREDSUM_VS_M8_E8, 2770 },
|
|
{ PseudoVWREDSUM_VS_MF2_E16, 2771 },
|
|
{ PseudoVWREDSUM_VS_MF2_E32, 2772 },
|
|
{ PseudoVWREDSUM_VS_MF2_E8, 2773 },
|
|
{ PseudoVWREDSUM_VS_MF4_E16, 2774 },
|
|
{ PseudoVWREDSUM_VS_MF4_E8, 2775 },
|
|
{ PseudoVWREDSUM_VS_MF8_E8, 2776 },
|
|
{ PseudoVWSLL_VI_M1, 2777 },
|
|
{ PseudoVWSLL_VI_M2, 2778 },
|
|
{ PseudoVWSLL_VI_M4, 2779 },
|
|
{ PseudoVWSLL_VI_MF2, 2780 },
|
|
{ PseudoVWSLL_VI_MF4, 2781 },
|
|
{ PseudoVWSLL_VI_MF8, 2782 },
|
|
{ PseudoVWSLL_VV_M1, 2783 },
|
|
{ PseudoVWSLL_VV_M2, 2784 },
|
|
{ PseudoVWSLL_VV_M4, 2785 },
|
|
{ PseudoVWSLL_VV_MF2, 2786 },
|
|
{ PseudoVWSLL_VV_MF4, 2787 },
|
|
{ PseudoVWSLL_VV_MF8, 2788 },
|
|
{ PseudoVWSLL_VX_M1, 2789 },
|
|
{ PseudoVWSLL_VX_M2, 2790 },
|
|
{ PseudoVWSLL_VX_M4, 2791 },
|
|
{ PseudoVWSLL_VX_MF2, 2792 },
|
|
{ PseudoVWSLL_VX_MF4, 2793 },
|
|
{ PseudoVWSLL_VX_MF8, 2794 },
|
|
{ PseudoVWSUBU_VV_M1, 2795 },
|
|
{ PseudoVWSUBU_VV_M2, 2796 },
|
|
{ PseudoVWSUBU_VV_M4, 2797 },
|
|
{ PseudoVWSUBU_VV_MF2, 2798 },
|
|
{ PseudoVWSUBU_VV_MF4, 2799 },
|
|
{ PseudoVWSUBU_VV_MF8, 2800 },
|
|
{ PseudoVWSUBU_VX_M1, 2801 },
|
|
{ PseudoVWSUBU_VX_M2, 2802 },
|
|
{ PseudoVWSUBU_VX_M4, 2803 },
|
|
{ PseudoVWSUBU_VX_MF2, 2804 },
|
|
{ PseudoVWSUBU_VX_MF4, 2805 },
|
|
{ PseudoVWSUBU_VX_MF8, 2806 },
|
|
{ PseudoVWSUBU_WV_M1, 2807 },
|
|
{ PseudoVWSUBU_WV_M2, 2808 },
|
|
{ PseudoVWSUBU_WV_M4, 2809 },
|
|
{ PseudoVWSUBU_WV_MF2, 2810 },
|
|
{ PseudoVWSUBU_WV_MF4, 2811 },
|
|
{ PseudoVWSUBU_WV_MF8, 2812 },
|
|
{ PseudoVWSUBU_WX_M1, 2813 },
|
|
{ PseudoVWSUBU_WX_M2, 2814 },
|
|
{ PseudoVWSUBU_WX_M4, 2815 },
|
|
{ PseudoVWSUBU_WX_MF2, 2816 },
|
|
{ PseudoVWSUBU_WX_MF4, 2817 },
|
|
{ PseudoVWSUBU_WX_MF8, 2818 },
|
|
{ PseudoVWSUB_VV_M1, 2819 },
|
|
{ PseudoVWSUB_VV_M2, 2820 },
|
|
{ PseudoVWSUB_VV_M4, 2821 },
|
|
{ PseudoVWSUB_VV_MF2, 2822 },
|
|
{ PseudoVWSUB_VV_MF4, 2823 },
|
|
{ PseudoVWSUB_VV_MF8, 2824 },
|
|
{ PseudoVWSUB_VX_M1, 2825 },
|
|
{ PseudoVWSUB_VX_M2, 2826 },
|
|
{ PseudoVWSUB_VX_M4, 2827 },
|
|
{ PseudoVWSUB_VX_MF2, 2828 },
|
|
{ PseudoVWSUB_VX_MF4, 2829 },
|
|
{ PseudoVWSUB_VX_MF8, 2830 },
|
|
{ PseudoVWSUB_WV_M1, 2831 },
|
|
{ PseudoVWSUB_WV_M2, 2832 },
|
|
{ PseudoVWSUB_WV_M4, 2833 },
|
|
{ PseudoVWSUB_WV_MF2, 2834 },
|
|
{ PseudoVWSUB_WV_MF4, 2835 },
|
|
{ PseudoVWSUB_WV_MF8, 2836 },
|
|
{ PseudoVWSUB_WX_M1, 2837 },
|
|
{ PseudoVWSUB_WX_M2, 2838 },
|
|
{ PseudoVWSUB_WX_M4, 2839 },
|
|
{ PseudoVWSUB_WX_MF2, 2840 },
|
|
{ PseudoVWSUB_WX_MF4, 2841 },
|
|
{ PseudoVWSUB_WX_MF8, 2842 },
|
|
{ PseudoVXOR_VI_M1, 2843 },
|
|
{ PseudoVXOR_VI_M2, 2844 },
|
|
{ PseudoVXOR_VI_M4, 2845 },
|
|
{ PseudoVXOR_VI_M8, 2846 },
|
|
{ PseudoVXOR_VI_MF2, 2847 },
|
|
{ PseudoVXOR_VI_MF4, 2848 },
|
|
{ PseudoVXOR_VI_MF8, 2849 },
|
|
{ PseudoVXOR_VV_M1, 2850 },
|
|
{ PseudoVXOR_VV_M2, 2851 },
|
|
{ PseudoVXOR_VV_M4, 2852 },
|
|
{ PseudoVXOR_VV_M8, 2853 },
|
|
{ PseudoVXOR_VV_MF2, 2854 },
|
|
{ PseudoVXOR_VV_MF4, 2855 },
|
|
{ PseudoVXOR_VV_MF8, 2856 },
|
|
{ PseudoVXOR_VX_M1, 2857 },
|
|
{ PseudoVXOR_VX_M2, 2858 },
|
|
{ PseudoVXOR_VX_M4, 2859 },
|
|
{ PseudoVXOR_VX_M8, 2860 },
|
|
{ PseudoVXOR_VX_MF2, 2861 },
|
|
{ PseudoVXOR_VX_MF4, 2862 },
|
|
{ PseudoVXOR_VX_MF8, 2863 },
|
|
{ PseudoVZEXT_VF2_M1, 2864 },
|
|
{ PseudoVZEXT_VF2_M2, 2865 },
|
|
{ PseudoVZEXT_VF2_M4, 2866 },
|
|
{ PseudoVZEXT_VF2_M8, 2867 },
|
|
{ PseudoVZEXT_VF2_MF2, 2868 },
|
|
{ PseudoVZEXT_VF2_MF4, 2869 },
|
|
{ PseudoVZEXT_VF4_M1, 2870 },
|
|
{ PseudoVZEXT_VF4_M2, 2871 },
|
|
{ PseudoVZEXT_VF4_M4, 2872 },
|
|
{ PseudoVZEXT_VF4_M8, 2873 },
|
|
{ PseudoVZEXT_VF4_MF2, 2874 },
|
|
{ PseudoVZEXT_VF8_M1, 2875 },
|
|
{ PseudoVZEXT_VF8_M2, 2876 },
|
|
{ PseudoVZEXT_VF8_M4, 2877 },
|
|
{ PseudoVZEXT_VF8_M8, 2878 },
|
|
};
|
|
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), UnmaskedPseudo);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVMaskedPseudosTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVOpcodesList_IMPL
|
|
static const RISCV_RISCVOpcode RISCVOpcodesList[] = {
|
|
{ "LOAD", { .raw_val = RISCV_RISCVOPCODE_LOAD }, 0x3 }, // 0
|
|
{ "LOAD_FP", { .raw_val = RISCV_RISCVOPCODE_LOAD_FP }, 0x7 }, // 1
|
|
{ "CUSTOM_0", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_0 }, 0xB }, // 2
|
|
{ "MISC_MEM", { .raw_val = RISCV_RISCVOPCODE_MISC_MEM }, 0xF }, // 3
|
|
{ "OP_IMM", { .raw_val = RISCV_RISCVOPCODE_OP_IMM }, 0x13 }, // 4
|
|
{ "AUIPC", { .raw_val = RISCV_RISCVOPCODE_AUIPC }, 0x17 }, // 5
|
|
{ "OP_IMM_32", { .raw_val = RISCV_RISCVOPCODE_OP_IMM_32 }, 0x1B }, // 6
|
|
{ "STORE", { .raw_val = RISCV_RISCVOPCODE_STORE }, 0x23 }, // 7
|
|
{ "STORE_FP", { .raw_val = RISCV_RISCVOPCODE_STORE_FP }, 0x27 }, // 8
|
|
{ "CUSTOM_1", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_1 }, 0x2B }, // 9
|
|
{ "AMO", { .raw_val = RISCV_RISCVOPCODE_AMO }, 0x2F }, // 10
|
|
{ "OP", { .raw_val = RISCV_RISCVOPCODE_OP }, 0x33 }, // 11
|
|
{ "LUI", { .raw_val = RISCV_RISCVOPCODE_LUI }, 0x37 }, // 12
|
|
{ "OP_32", { .raw_val = RISCV_RISCVOPCODE_OP_32 }, 0x3B }, // 13
|
|
{ "MADD", { .raw_val = RISCV_RISCVOPCODE_MADD }, 0x43 }, // 14
|
|
{ "MSUB", { .raw_val = RISCV_RISCVOPCODE_MSUB }, 0x47 }, // 15
|
|
{ "NMSUB", { .raw_val = RISCV_RISCVOPCODE_NMSUB }, 0x4B }, // 16
|
|
{ "NMADD", { .raw_val = RISCV_RISCVOPCODE_NMADD }, 0x4F }, // 17
|
|
{ "OP_FP", { .raw_val = RISCV_RISCVOPCODE_OP_FP }, 0x53 }, // 18
|
|
{ "OP_V", { .raw_val = RISCV_RISCVOPCODE_OP_V }, 0x57 }, // 19
|
|
{ "CUSTOM_2", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_2 }, 0x5B }, // 20
|
|
{ "BRANCH", { .raw_val = RISCV_RISCVOPCODE_BRANCH }, 0x63 }, // 21
|
|
{ "JALR", { .raw_val = RISCV_RISCVOPCODE_JALR }, 0x67 }, // 22
|
|
{ "JAL", { .raw_val = RISCV_RISCVOPCODE_JAL }, 0x6F }, // 23
|
|
{ "SYSTEM", { .raw_val = RISCV_RISCVOPCODE_SYSTEM }, 0x73 }, // 24
|
|
{ "OP_P", { .raw_val = RISCV_RISCVOPCODE_OP_P }, 0x77 }, // 25
|
|
{ "CUSTOM_3", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_3 }, 0x7B }, // 26
|
|
};
|
|
|
|
const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByValue(uint8_t Value) {
|
|
static const struct IndexType Index[] = {
|
|
{3,0},
|
|
{7,1},
|
|
{11,2},
|
|
{15,3},
|
|
{19,4},
|
|
{23,5},
|
|
{27,6},
|
|
{35,7},
|
|
{39,8},
|
|
{43,9},
|
|
{47,10},
|
|
{51,11},
|
|
{55,12},
|
|
{59,13},
|
|
{67,14},
|
|
{71,15},
|
|
{75,16},
|
|
{79,17},
|
|
{83,18},
|
|
{87,19},
|
|
{91,20},
|
|
{99,21},
|
|
{103,22},
|
|
{111,23},
|
|
{115,24},
|
|
{119,25},
|
|
{123,26},
|
|
};
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Value);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVOpcodesList[Index[i].index];
|
|
}
|
|
|
|
const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByName(const char * Name) {
|
|
static const struct IndexTypeStr Index[] = {
|
|
{ "AMO", 10 },
|
|
{ "AUIPC", 5 },
|
|
{ "BRANCH", 21 },
|
|
{ "CUSTOM_0", 2 },
|
|
{ "CUSTOM_1", 9 },
|
|
{ "CUSTOM_2", 20 },
|
|
{ "CUSTOM_3", 26 },
|
|
{ "JAL", 23 },
|
|
{ "JALR", 22 },
|
|
{ "LOAD", 0 },
|
|
{ "LOAD_FP", 1 },
|
|
{ "LUI", 12 },
|
|
{ "MADD", 14 },
|
|
{ "MISC_MEM", 3 },
|
|
{ "MSUB", 15 },
|
|
{ "NMADD", 17 },
|
|
{ "NMSUB", 16 },
|
|
{ "OP", 11 },
|
|
{ "OP_32", 13 },
|
|
{ "OP_FP", 18 },
|
|
{ "OP_IMM", 4 },
|
|
{ "OP_IMM_32", 6 },
|
|
{ "OP_P", 25 },
|
|
{ "OP_V", 19 },
|
|
{ "STORE", 7 },
|
|
{ "STORE_FP", 8 },
|
|
{ "SYSTEM", 24 },
|
|
};
|
|
|
|
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVOpcodesList[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVTuneInfoTable_IMPL
|
|
static const RISCV_RISCVTuneInfo RISCVTuneInfoTable[] = {
|
|
{ "generic", { .raw_val = RISCV_RISCVTUNEINFO_GENERIC }, 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 0
|
|
{ "generic-rv32", { .raw_val = RISCV_RISCVTUNEINFO_GENERIC-RV32 }, 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 1
|
|
{ "generic-rv64", { .raw_val = RISCV_RISCVTUNEINFO_GENERIC-RV64 }, 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 2
|
|
};
|
|
|
|
const RISCV_RISCVTuneInfo *RISCV_getRISCVTuneInfo(const char * Name) {
|
|
static const struct IndexTypeStr Index[] = {
|
|
{ "GENERIC", 0 },
|
|
{ "GENERIC-RV32", 1 },
|
|
{ "GENERIC-RV64", 2 },
|
|
};
|
|
|
|
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVTuneInfoTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVInversePseudosTable_IMPL
|
|
static const RISCV_PseudoInfo RISCVVInversePseudosTable[] = {
|
|
{ PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV, 0x0, 0x0 }, // 0
|
|
{ PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV, 0x0, 0x0 }, // 1
|
|
{ PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV, 0x1, 0x0 }, // 2
|
|
{ PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV, 0x1, 0x0 }, // 3
|
|
{ PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV, 0x2, 0x0 }, // 4
|
|
{ PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV, 0x2, 0x0 }, // 5
|
|
{ PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV, 0x3, 0x0 }, // 6
|
|
{ PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV, 0x3, 0x0 }, // 7
|
|
{ PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV, 0x7, 0x0 }, // 8
|
|
{ PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV, 0x7, 0x0 }, // 9
|
|
{ PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX, 0x0, 0x0 }, // 10
|
|
{ PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX, 0x0, 0x0 }, // 11
|
|
{ PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX, 0x1, 0x0 }, // 12
|
|
{ PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX, 0x1, 0x0 }, // 13
|
|
{ PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX, 0x2, 0x0 }, // 14
|
|
{ PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX, 0x2, 0x0 }, // 15
|
|
{ PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX, 0x3, 0x0 }, // 16
|
|
{ PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX, 0x3, 0x0 }, // 17
|
|
{ PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX, 0x7, 0x0 }, // 18
|
|
{ PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX, 0x7, 0x0 }, // 19
|
|
{ PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 20
|
|
{ PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 21
|
|
{ PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 22
|
|
{ PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 23
|
|
{ PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 24
|
|
{ PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 25
|
|
{ PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 26
|
|
{ PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 27
|
|
{ PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 28
|
|
{ PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 29
|
|
{ PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV, 0x0, 0x0 }, // 30
|
|
{ PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV, 0x0, 0x0 }, // 31
|
|
{ PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV, 0x1, 0x0 }, // 32
|
|
{ PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV, 0x1, 0x0 }, // 33
|
|
{ PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV, 0x2, 0x0 }, // 34
|
|
{ PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV, 0x2, 0x0 }, // 35
|
|
{ PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV, 0x3, 0x0 }, // 36
|
|
{ PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV, 0x3, 0x0 }, // 37
|
|
{ PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV, 0x7, 0x0 }, // 38
|
|
{ PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV, 0x7, 0x0 }, // 39
|
|
{ PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX, 0x0, 0x0 }, // 40
|
|
{ PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX, 0x0, 0x0 }, // 41
|
|
{ PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX, 0x1, 0x0 }, // 42
|
|
{ PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX, 0x1, 0x0 }, // 43
|
|
{ PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX, 0x2, 0x0 }, // 44
|
|
{ PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX, 0x2, 0x0 }, // 45
|
|
{ PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX, 0x3, 0x0 }, // 46
|
|
{ PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX, 0x3, 0x0 }, // 47
|
|
{ PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX, 0x7, 0x0 }, // 48
|
|
{ PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX, 0x7, 0x0 }, // 49
|
|
{ PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV, 0x0, 0x0 }, // 50
|
|
{ PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV, 0x0, 0x0 }, // 51
|
|
{ PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV, 0x1, 0x0 }, // 52
|
|
{ PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV, 0x1, 0x0 }, // 53
|
|
{ PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV, 0x2, 0x0 }, // 54
|
|
{ PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV, 0x2, 0x0 }, // 55
|
|
{ PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV, 0x3, 0x0 }, // 56
|
|
{ PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV, 0x3, 0x0 }, // 57
|
|
{ PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV, 0x7, 0x0 }, // 58
|
|
{ PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV, 0x7, 0x0 }, // 59
|
|
{ PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX, 0x0, 0x0 }, // 60
|
|
{ PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX, 0x0, 0x0 }, // 61
|
|
{ PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX, 0x1, 0x0 }, // 62
|
|
{ PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX, 0x1, 0x0 }, // 63
|
|
{ PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX, 0x2, 0x0 }, // 64
|
|
{ PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX, 0x2, 0x0 }, // 65
|
|
{ PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX, 0x3, 0x0 }, // 66
|
|
{ PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX, 0x3, 0x0 }, // 67
|
|
{ PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX, 0x7, 0x0 }, // 68
|
|
{ PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX, 0x7, 0x0 }, // 69
|
|
{ PseudoVAADDU_VV_M1, VAADDU_VV, 0x0, 0x0 }, // 70
|
|
{ PseudoVAADDU_VV_M1_MASK, VAADDU_VV, 0x0, 0x0 }, // 71
|
|
{ PseudoVAADDU_VV_M2, VAADDU_VV, 0x1, 0x0 }, // 72
|
|
{ PseudoVAADDU_VV_M2_MASK, VAADDU_VV, 0x1, 0x0 }, // 73
|
|
{ PseudoVAADDU_VV_M4, VAADDU_VV, 0x2, 0x0 }, // 74
|
|
{ PseudoVAADDU_VV_M4_MASK, VAADDU_VV, 0x2, 0x0 }, // 75
|
|
{ PseudoVAADDU_VV_M8, VAADDU_VV, 0x3, 0x0 }, // 76
|
|
{ PseudoVAADDU_VV_M8_MASK, VAADDU_VV, 0x3, 0x0 }, // 77
|
|
{ PseudoVAADDU_VV_MF8, VAADDU_VV, 0x5, 0x0 }, // 78
|
|
{ PseudoVAADDU_VV_MF8_MASK, VAADDU_VV, 0x5, 0x0 }, // 79
|
|
{ PseudoVAADDU_VV_MF4, VAADDU_VV, 0x6, 0x0 }, // 80
|
|
{ PseudoVAADDU_VV_MF4_MASK, VAADDU_VV, 0x6, 0x0 }, // 81
|
|
{ PseudoVAADDU_VV_MF2, VAADDU_VV, 0x7, 0x0 }, // 82
|
|
{ PseudoVAADDU_VV_MF2_MASK, VAADDU_VV, 0x7, 0x0 }, // 83
|
|
{ PseudoVAADDU_VX_M1, VAADDU_VX, 0x0, 0x0 }, // 84
|
|
{ PseudoVAADDU_VX_M1_MASK, VAADDU_VX, 0x0, 0x0 }, // 85
|
|
{ PseudoVAADDU_VX_M2, VAADDU_VX, 0x1, 0x0 }, // 86
|
|
{ PseudoVAADDU_VX_M2_MASK, VAADDU_VX, 0x1, 0x0 }, // 87
|
|
{ PseudoVAADDU_VX_M4, VAADDU_VX, 0x2, 0x0 }, // 88
|
|
{ PseudoVAADDU_VX_M4_MASK, VAADDU_VX, 0x2, 0x0 }, // 89
|
|
{ PseudoVAADDU_VX_M8, VAADDU_VX, 0x3, 0x0 }, // 90
|
|
{ PseudoVAADDU_VX_M8_MASK, VAADDU_VX, 0x3, 0x0 }, // 91
|
|
{ PseudoVAADDU_VX_MF8, VAADDU_VX, 0x5, 0x0 }, // 92
|
|
{ PseudoVAADDU_VX_MF8_MASK, VAADDU_VX, 0x5, 0x0 }, // 93
|
|
{ PseudoVAADDU_VX_MF4, VAADDU_VX, 0x6, 0x0 }, // 94
|
|
{ PseudoVAADDU_VX_MF4_MASK, VAADDU_VX, 0x6, 0x0 }, // 95
|
|
{ PseudoVAADDU_VX_MF2, VAADDU_VX, 0x7, 0x0 }, // 96
|
|
{ PseudoVAADDU_VX_MF2_MASK, VAADDU_VX, 0x7, 0x0 }, // 97
|
|
{ PseudoVAADD_VV_M1, VAADD_VV, 0x0, 0x0 }, // 98
|
|
{ PseudoVAADD_VV_M1_MASK, VAADD_VV, 0x0, 0x0 }, // 99
|
|
{ PseudoVAADD_VV_M2, VAADD_VV, 0x1, 0x0 }, // 100
|
|
{ PseudoVAADD_VV_M2_MASK, VAADD_VV, 0x1, 0x0 }, // 101
|
|
{ PseudoVAADD_VV_M4, VAADD_VV, 0x2, 0x0 }, // 102
|
|
{ PseudoVAADD_VV_M4_MASK, VAADD_VV, 0x2, 0x0 }, // 103
|
|
{ PseudoVAADD_VV_M8, VAADD_VV, 0x3, 0x0 }, // 104
|
|
{ PseudoVAADD_VV_M8_MASK, VAADD_VV, 0x3, 0x0 }, // 105
|
|
{ PseudoVAADD_VV_MF8, VAADD_VV, 0x5, 0x0 }, // 106
|
|
{ PseudoVAADD_VV_MF8_MASK, VAADD_VV, 0x5, 0x0 }, // 107
|
|
{ PseudoVAADD_VV_MF4, VAADD_VV, 0x6, 0x0 }, // 108
|
|
{ PseudoVAADD_VV_MF4_MASK, VAADD_VV, 0x6, 0x0 }, // 109
|
|
{ PseudoVAADD_VV_MF2, VAADD_VV, 0x7, 0x0 }, // 110
|
|
{ PseudoVAADD_VV_MF2_MASK, VAADD_VV, 0x7, 0x0 }, // 111
|
|
{ PseudoVAADD_VX_M1, VAADD_VX, 0x0, 0x0 }, // 112
|
|
{ PseudoVAADD_VX_M1_MASK, VAADD_VX, 0x0, 0x0 }, // 113
|
|
{ PseudoVAADD_VX_M2, VAADD_VX, 0x1, 0x0 }, // 114
|
|
{ PseudoVAADD_VX_M2_MASK, VAADD_VX, 0x1, 0x0 }, // 115
|
|
{ PseudoVAADD_VX_M4, VAADD_VX, 0x2, 0x0 }, // 116
|
|
{ PseudoVAADD_VX_M4_MASK, VAADD_VX, 0x2, 0x0 }, // 117
|
|
{ PseudoVAADD_VX_M8, VAADD_VX, 0x3, 0x0 }, // 118
|
|
{ PseudoVAADD_VX_M8_MASK, VAADD_VX, 0x3, 0x0 }, // 119
|
|
{ PseudoVAADD_VX_MF8, VAADD_VX, 0x5, 0x0 }, // 120
|
|
{ PseudoVAADD_VX_MF8_MASK, VAADD_VX, 0x5, 0x0 }, // 121
|
|
{ PseudoVAADD_VX_MF4, VAADD_VX, 0x6, 0x0 }, // 122
|
|
{ PseudoVAADD_VX_MF4_MASK, VAADD_VX, 0x6, 0x0 }, // 123
|
|
{ PseudoVAADD_VX_MF2, VAADD_VX, 0x7, 0x0 }, // 124
|
|
{ PseudoVAADD_VX_MF2_MASK, VAADD_VX, 0x7, 0x0 }, // 125
|
|
{ PseudoVADC_VIM_M1, VADC_VIM, 0x0, 0x0 }, // 126
|
|
{ PseudoVADC_VIM_M2, VADC_VIM, 0x1, 0x0 }, // 127
|
|
{ PseudoVADC_VIM_M4, VADC_VIM, 0x2, 0x0 }, // 128
|
|
{ PseudoVADC_VIM_M8, VADC_VIM, 0x3, 0x0 }, // 129
|
|
{ PseudoVADC_VIM_MF8, VADC_VIM, 0x5, 0x0 }, // 130
|
|
{ PseudoVADC_VIM_MF4, VADC_VIM, 0x6, 0x0 }, // 131
|
|
{ PseudoVADC_VIM_MF2, VADC_VIM, 0x7, 0x0 }, // 132
|
|
{ PseudoVADC_VVM_M1, VADC_VVM, 0x0, 0x0 }, // 133
|
|
{ PseudoVADC_VVM_M2, VADC_VVM, 0x1, 0x0 }, // 134
|
|
{ PseudoVADC_VVM_M4, VADC_VVM, 0x2, 0x0 }, // 135
|
|
{ PseudoVADC_VVM_M8, VADC_VVM, 0x3, 0x0 }, // 136
|
|
{ PseudoVADC_VVM_MF8, VADC_VVM, 0x5, 0x0 }, // 137
|
|
{ PseudoVADC_VVM_MF4, VADC_VVM, 0x6, 0x0 }, // 138
|
|
{ PseudoVADC_VVM_MF2, VADC_VVM, 0x7, 0x0 }, // 139
|
|
{ PseudoVADC_VXM_M1, VADC_VXM, 0x0, 0x0 }, // 140
|
|
{ PseudoVADC_VXM_M2, VADC_VXM, 0x1, 0x0 }, // 141
|
|
{ PseudoVADC_VXM_M4, VADC_VXM, 0x2, 0x0 }, // 142
|
|
{ PseudoVADC_VXM_M8, VADC_VXM, 0x3, 0x0 }, // 143
|
|
{ PseudoVADC_VXM_MF8, VADC_VXM, 0x5, 0x0 }, // 144
|
|
{ PseudoVADC_VXM_MF4, VADC_VXM, 0x6, 0x0 }, // 145
|
|
{ PseudoVADC_VXM_MF2, VADC_VXM, 0x7, 0x0 }, // 146
|
|
{ PseudoVADD_VI_M1, VADD_VI, 0x0, 0x0 }, // 147
|
|
{ PseudoVADD_VI_M1_MASK, VADD_VI, 0x0, 0x0 }, // 148
|
|
{ PseudoVADD_VI_M2, VADD_VI, 0x1, 0x0 }, // 149
|
|
{ PseudoVADD_VI_M2_MASK, VADD_VI, 0x1, 0x0 }, // 150
|
|
{ PseudoVADD_VI_M4, VADD_VI, 0x2, 0x0 }, // 151
|
|
{ PseudoVADD_VI_M4_MASK, VADD_VI, 0x2, 0x0 }, // 152
|
|
{ PseudoVADD_VI_M8, VADD_VI, 0x3, 0x0 }, // 153
|
|
{ PseudoVADD_VI_M8_MASK, VADD_VI, 0x3, 0x0 }, // 154
|
|
{ PseudoVADD_VI_MF8, VADD_VI, 0x5, 0x0 }, // 155
|
|
{ PseudoVADD_VI_MF8_MASK, VADD_VI, 0x5, 0x0 }, // 156
|
|
{ PseudoVADD_VI_MF4, VADD_VI, 0x6, 0x0 }, // 157
|
|
{ PseudoVADD_VI_MF4_MASK, VADD_VI, 0x6, 0x0 }, // 158
|
|
{ PseudoVADD_VI_MF2, VADD_VI, 0x7, 0x0 }, // 159
|
|
{ PseudoVADD_VI_MF2_MASK, VADD_VI, 0x7, 0x0 }, // 160
|
|
{ PseudoVADD_VV_M1, VADD_VV, 0x0, 0x0 }, // 161
|
|
{ PseudoVADD_VV_M1_MASK, VADD_VV, 0x0, 0x0 }, // 162
|
|
{ PseudoVADD_VV_M2, VADD_VV, 0x1, 0x0 }, // 163
|
|
{ PseudoVADD_VV_M2_MASK, VADD_VV, 0x1, 0x0 }, // 164
|
|
{ PseudoVADD_VV_M4, VADD_VV, 0x2, 0x0 }, // 165
|
|
{ PseudoVADD_VV_M4_MASK, VADD_VV, 0x2, 0x0 }, // 166
|
|
{ PseudoVADD_VV_M8, VADD_VV, 0x3, 0x0 }, // 167
|
|
{ PseudoVADD_VV_M8_MASK, VADD_VV, 0x3, 0x0 }, // 168
|
|
{ PseudoVADD_VV_MF8, VADD_VV, 0x5, 0x0 }, // 169
|
|
{ PseudoVADD_VV_MF8_MASK, VADD_VV, 0x5, 0x0 }, // 170
|
|
{ PseudoVADD_VV_MF4, VADD_VV, 0x6, 0x0 }, // 171
|
|
{ PseudoVADD_VV_MF4_MASK, VADD_VV, 0x6, 0x0 }, // 172
|
|
{ PseudoVADD_VV_MF2, VADD_VV, 0x7, 0x0 }, // 173
|
|
{ PseudoVADD_VV_MF2_MASK, VADD_VV, 0x7, 0x0 }, // 174
|
|
{ PseudoVADD_VX_M1, VADD_VX, 0x0, 0x0 }, // 175
|
|
{ PseudoVADD_VX_M1_MASK, VADD_VX, 0x0, 0x0 }, // 176
|
|
{ PseudoVADD_VX_M2, VADD_VX, 0x1, 0x0 }, // 177
|
|
{ PseudoVADD_VX_M2_MASK, VADD_VX, 0x1, 0x0 }, // 178
|
|
{ PseudoVADD_VX_M4, VADD_VX, 0x2, 0x0 }, // 179
|
|
{ PseudoVADD_VX_M4_MASK, VADD_VX, 0x2, 0x0 }, // 180
|
|
{ PseudoVADD_VX_M8, VADD_VX, 0x3, 0x0 }, // 181
|
|
{ PseudoVADD_VX_M8_MASK, VADD_VX, 0x3, 0x0 }, // 182
|
|
{ PseudoVADD_VX_MF8, VADD_VX, 0x5, 0x0 }, // 183
|
|
{ PseudoVADD_VX_MF8_MASK, VADD_VX, 0x5, 0x0 }, // 184
|
|
{ PseudoVADD_VX_MF4, VADD_VX, 0x6, 0x0 }, // 185
|
|
{ PseudoVADD_VX_MF4_MASK, VADD_VX, 0x6, 0x0 }, // 186
|
|
{ PseudoVADD_VX_MF2, VADD_VX, 0x7, 0x0 }, // 187
|
|
{ PseudoVADD_VX_MF2_MASK, VADD_VX, 0x7, 0x0 }, // 188
|
|
{ PseudoVAESDF_VS_M1_M1, VAESDF_VS, 0x0, 0x0 }, // 189
|
|
{ PseudoVAESDF_VS_M1_MF2, VAESDF_VS, 0x0, 0x0 }, // 190
|
|
{ PseudoVAESDF_VS_M1_MF4, VAESDF_VS, 0x0, 0x0 }, // 191
|
|
{ PseudoVAESDF_VS_M1_MF8, VAESDF_VS, 0x0, 0x0 }, // 192
|
|
{ PseudoVAESDF_VS_M2_M1, VAESDF_VS, 0x1, 0x0 }, // 193
|
|
{ PseudoVAESDF_VS_M2_M2, VAESDF_VS, 0x1, 0x0 }, // 194
|
|
{ PseudoVAESDF_VS_M2_MF2, VAESDF_VS, 0x1, 0x0 }, // 195
|
|
{ PseudoVAESDF_VS_M2_MF4, VAESDF_VS, 0x1, 0x0 }, // 196
|
|
{ PseudoVAESDF_VS_M2_MF8, VAESDF_VS, 0x1, 0x0 }, // 197
|
|
{ PseudoVAESDF_VS_M4_M1, VAESDF_VS, 0x2, 0x0 }, // 198
|
|
{ PseudoVAESDF_VS_M4_M2, VAESDF_VS, 0x2, 0x0 }, // 199
|
|
{ PseudoVAESDF_VS_M4_M4, VAESDF_VS, 0x2, 0x0 }, // 200
|
|
{ PseudoVAESDF_VS_M4_MF2, VAESDF_VS, 0x2, 0x0 }, // 201
|
|
{ PseudoVAESDF_VS_M4_MF4, VAESDF_VS, 0x2, 0x0 }, // 202
|
|
{ PseudoVAESDF_VS_M4_MF8, VAESDF_VS, 0x2, 0x0 }, // 203
|
|
{ PseudoVAESDF_VS_M8_M1, VAESDF_VS, 0x3, 0x0 }, // 204
|
|
{ PseudoVAESDF_VS_M8_M2, VAESDF_VS, 0x3, 0x0 }, // 205
|
|
{ PseudoVAESDF_VS_M8_M4, VAESDF_VS, 0x3, 0x0 }, // 206
|
|
{ PseudoVAESDF_VS_M8_MF2, VAESDF_VS, 0x3, 0x0 }, // 207
|
|
{ PseudoVAESDF_VS_M8_MF4, VAESDF_VS, 0x3, 0x0 }, // 208
|
|
{ PseudoVAESDF_VS_M8_MF8, VAESDF_VS, 0x3, 0x0 }, // 209
|
|
{ PseudoVAESDF_VS_MF2_MF2, VAESDF_VS, 0x7, 0x0 }, // 210
|
|
{ PseudoVAESDF_VS_MF2_MF4, VAESDF_VS, 0x7, 0x0 }, // 211
|
|
{ PseudoVAESDF_VS_MF2_MF8, VAESDF_VS, 0x7, 0x0 }, // 212
|
|
{ PseudoVAESDF_VV_M1, VAESDF_VV, 0x0, 0x0 }, // 213
|
|
{ PseudoVAESDF_VV_M2, VAESDF_VV, 0x1, 0x0 }, // 214
|
|
{ PseudoVAESDF_VV_M4, VAESDF_VV, 0x2, 0x0 }, // 215
|
|
{ PseudoVAESDF_VV_M8, VAESDF_VV, 0x3, 0x0 }, // 216
|
|
{ PseudoVAESDF_VV_MF2, VAESDF_VV, 0x7, 0x0 }, // 217
|
|
{ PseudoVAESDM_VS_M1_M1, VAESDM_VS, 0x0, 0x0 }, // 218
|
|
{ PseudoVAESDM_VS_M1_MF2, VAESDM_VS, 0x0, 0x0 }, // 219
|
|
{ PseudoVAESDM_VS_M1_MF4, VAESDM_VS, 0x0, 0x0 }, // 220
|
|
{ PseudoVAESDM_VS_M1_MF8, VAESDM_VS, 0x0, 0x0 }, // 221
|
|
{ PseudoVAESDM_VS_M2_M1, VAESDM_VS, 0x1, 0x0 }, // 222
|
|
{ PseudoVAESDM_VS_M2_M2, VAESDM_VS, 0x1, 0x0 }, // 223
|
|
{ PseudoVAESDM_VS_M2_MF2, VAESDM_VS, 0x1, 0x0 }, // 224
|
|
{ PseudoVAESDM_VS_M2_MF4, VAESDM_VS, 0x1, 0x0 }, // 225
|
|
{ PseudoVAESDM_VS_M2_MF8, VAESDM_VS, 0x1, 0x0 }, // 226
|
|
{ PseudoVAESDM_VS_M4_M1, VAESDM_VS, 0x2, 0x0 }, // 227
|
|
{ PseudoVAESDM_VS_M4_M2, VAESDM_VS, 0x2, 0x0 }, // 228
|
|
{ PseudoVAESDM_VS_M4_M4, VAESDM_VS, 0x2, 0x0 }, // 229
|
|
{ PseudoVAESDM_VS_M4_MF2, VAESDM_VS, 0x2, 0x0 }, // 230
|
|
{ PseudoVAESDM_VS_M4_MF4, VAESDM_VS, 0x2, 0x0 }, // 231
|
|
{ PseudoVAESDM_VS_M4_MF8, VAESDM_VS, 0x2, 0x0 }, // 232
|
|
{ PseudoVAESDM_VS_M8_M1, VAESDM_VS, 0x3, 0x0 }, // 233
|
|
{ PseudoVAESDM_VS_M8_M2, VAESDM_VS, 0x3, 0x0 }, // 234
|
|
{ PseudoVAESDM_VS_M8_M4, VAESDM_VS, 0x3, 0x0 }, // 235
|
|
{ PseudoVAESDM_VS_M8_MF2, VAESDM_VS, 0x3, 0x0 }, // 236
|
|
{ PseudoVAESDM_VS_M8_MF4, VAESDM_VS, 0x3, 0x0 }, // 237
|
|
{ PseudoVAESDM_VS_M8_MF8, VAESDM_VS, 0x3, 0x0 }, // 238
|
|
{ PseudoVAESDM_VS_MF2_MF2, VAESDM_VS, 0x7, 0x0 }, // 239
|
|
{ PseudoVAESDM_VS_MF2_MF4, VAESDM_VS, 0x7, 0x0 }, // 240
|
|
{ PseudoVAESDM_VS_MF2_MF8, VAESDM_VS, 0x7, 0x0 }, // 241
|
|
{ PseudoVAESDM_VV_M1, VAESDM_VV, 0x0, 0x0 }, // 242
|
|
{ PseudoVAESDM_VV_M2, VAESDM_VV, 0x1, 0x0 }, // 243
|
|
{ PseudoVAESDM_VV_M4, VAESDM_VV, 0x2, 0x0 }, // 244
|
|
{ PseudoVAESDM_VV_M8, VAESDM_VV, 0x3, 0x0 }, // 245
|
|
{ PseudoVAESDM_VV_MF2, VAESDM_VV, 0x7, 0x0 }, // 246
|
|
{ PseudoVAESEF_VS_M1_M1, VAESEF_VS, 0x0, 0x0 }, // 247
|
|
{ PseudoVAESEF_VS_M1_MF2, VAESEF_VS, 0x0, 0x0 }, // 248
|
|
{ PseudoVAESEF_VS_M1_MF4, VAESEF_VS, 0x0, 0x0 }, // 249
|
|
{ PseudoVAESEF_VS_M1_MF8, VAESEF_VS, 0x0, 0x0 }, // 250
|
|
{ PseudoVAESEF_VS_M2_M1, VAESEF_VS, 0x1, 0x0 }, // 251
|
|
{ PseudoVAESEF_VS_M2_M2, VAESEF_VS, 0x1, 0x0 }, // 252
|
|
{ PseudoVAESEF_VS_M2_MF2, VAESEF_VS, 0x1, 0x0 }, // 253
|
|
{ PseudoVAESEF_VS_M2_MF4, VAESEF_VS, 0x1, 0x0 }, // 254
|
|
{ PseudoVAESEF_VS_M2_MF8, VAESEF_VS, 0x1, 0x0 }, // 255
|
|
{ PseudoVAESEF_VS_M4_M1, VAESEF_VS, 0x2, 0x0 }, // 256
|
|
{ PseudoVAESEF_VS_M4_M2, VAESEF_VS, 0x2, 0x0 }, // 257
|
|
{ PseudoVAESEF_VS_M4_M4, VAESEF_VS, 0x2, 0x0 }, // 258
|
|
{ PseudoVAESEF_VS_M4_MF2, VAESEF_VS, 0x2, 0x0 }, // 259
|
|
{ PseudoVAESEF_VS_M4_MF4, VAESEF_VS, 0x2, 0x0 }, // 260
|
|
{ PseudoVAESEF_VS_M4_MF8, VAESEF_VS, 0x2, 0x0 }, // 261
|
|
{ PseudoVAESEF_VS_M8_M1, VAESEF_VS, 0x3, 0x0 }, // 262
|
|
{ PseudoVAESEF_VS_M8_M2, VAESEF_VS, 0x3, 0x0 }, // 263
|
|
{ PseudoVAESEF_VS_M8_M4, VAESEF_VS, 0x3, 0x0 }, // 264
|
|
{ PseudoVAESEF_VS_M8_MF2, VAESEF_VS, 0x3, 0x0 }, // 265
|
|
{ PseudoVAESEF_VS_M8_MF4, VAESEF_VS, 0x3, 0x0 }, // 266
|
|
{ PseudoVAESEF_VS_M8_MF8, VAESEF_VS, 0x3, 0x0 }, // 267
|
|
{ PseudoVAESEF_VS_MF2_MF2, VAESEF_VS, 0x7, 0x0 }, // 268
|
|
{ PseudoVAESEF_VS_MF2_MF4, VAESEF_VS, 0x7, 0x0 }, // 269
|
|
{ PseudoVAESEF_VS_MF2_MF8, VAESEF_VS, 0x7, 0x0 }, // 270
|
|
{ PseudoVAESEF_VV_M1, VAESEF_VV, 0x0, 0x0 }, // 271
|
|
{ PseudoVAESEF_VV_M2, VAESEF_VV, 0x1, 0x0 }, // 272
|
|
{ PseudoVAESEF_VV_M4, VAESEF_VV, 0x2, 0x0 }, // 273
|
|
{ PseudoVAESEF_VV_M8, VAESEF_VV, 0x3, 0x0 }, // 274
|
|
{ PseudoVAESEF_VV_MF2, VAESEF_VV, 0x7, 0x0 }, // 275
|
|
{ PseudoVAESEM_VS_M1_M1, VAESEM_VS, 0x0, 0x0 }, // 276
|
|
{ PseudoVAESEM_VS_M1_MF2, VAESEM_VS, 0x0, 0x0 }, // 277
|
|
{ PseudoVAESEM_VS_M1_MF4, VAESEM_VS, 0x0, 0x0 }, // 278
|
|
{ PseudoVAESEM_VS_M1_MF8, VAESEM_VS, 0x0, 0x0 }, // 279
|
|
{ PseudoVAESEM_VS_M2_M1, VAESEM_VS, 0x1, 0x0 }, // 280
|
|
{ PseudoVAESEM_VS_M2_M2, VAESEM_VS, 0x1, 0x0 }, // 281
|
|
{ PseudoVAESEM_VS_M2_MF2, VAESEM_VS, 0x1, 0x0 }, // 282
|
|
{ PseudoVAESEM_VS_M2_MF4, VAESEM_VS, 0x1, 0x0 }, // 283
|
|
{ PseudoVAESEM_VS_M2_MF8, VAESEM_VS, 0x1, 0x0 }, // 284
|
|
{ PseudoVAESEM_VS_M4_M1, VAESEM_VS, 0x2, 0x0 }, // 285
|
|
{ PseudoVAESEM_VS_M4_M2, VAESEM_VS, 0x2, 0x0 }, // 286
|
|
{ PseudoVAESEM_VS_M4_M4, VAESEM_VS, 0x2, 0x0 }, // 287
|
|
{ PseudoVAESEM_VS_M4_MF2, VAESEM_VS, 0x2, 0x0 }, // 288
|
|
{ PseudoVAESEM_VS_M4_MF4, VAESEM_VS, 0x2, 0x0 }, // 289
|
|
{ PseudoVAESEM_VS_M4_MF8, VAESEM_VS, 0x2, 0x0 }, // 290
|
|
{ PseudoVAESEM_VS_M8_M1, VAESEM_VS, 0x3, 0x0 }, // 291
|
|
{ PseudoVAESEM_VS_M8_M2, VAESEM_VS, 0x3, 0x0 }, // 292
|
|
{ PseudoVAESEM_VS_M8_M4, VAESEM_VS, 0x3, 0x0 }, // 293
|
|
{ PseudoVAESEM_VS_M8_MF2, VAESEM_VS, 0x3, 0x0 }, // 294
|
|
{ PseudoVAESEM_VS_M8_MF4, VAESEM_VS, 0x3, 0x0 }, // 295
|
|
{ PseudoVAESEM_VS_M8_MF8, VAESEM_VS, 0x3, 0x0 }, // 296
|
|
{ PseudoVAESEM_VS_MF2_MF2, VAESEM_VS, 0x7, 0x0 }, // 297
|
|
{ PseudoVAESEM_VS_MF2_MF4, VAESEM_VS, 0x7, 0x0 }, // 298
|
|
{ PseudoVAESEM_VS_MF2_MF8, VAESEM_VS, 0x7, 0x0 }, // 299
|
|
{ PseudoVAESEM_VV_M1, VAESEM_VV, 0x0, 0x0 }, // 300
|
|
{ PseudoVAESEM_VV_M2, VAESEM_VV, 0x1, 0x0 }, // 301
|
|
{ PseudoVAESEM_VV_M4, VAESEM_VV, 0x2, 0x0 }, // 302
|
|
{ PseudoVAESEM_VV_M8, VAESEM_VV, 0x3, 0x0 }, // 303
|
|
{ PseudoVAESEM_VV_MF2, VAESEM_VV, 0x7, 0x0 }, // 304
|
|
{ PseudoVAESKF1_VI_M1, VAESKF1_VI, 0x0, 0x0 }, // 305
|
|
{ PseudoVAESKF1_VI_M2, VAESKF1_VI, 0x1, 0x0 }, // 306
|
|
{ PseudoVAESKF1_VI_M4, VAESKF1_VI, 0x2, 0x0 }, // 307
|
|
{ PseudoVAESKF1_VI_M8, VAESKF1_VI, 0x3, 0x0 }, // 308
|
|
{ PseudoVAESKF1_VI_MF2, VAESKF1_VI, 0x7, 0x0 }, // 309
|
|
{ PseudoVAESKF2_VI_M1, VAESKF2_VI, 0x0, 0x0 }, // 310
|
|
{ PseudoVAESKF2_VI_M2, VAESKF2_VI, 0x1, 0x0 }, // 311
|
|
{ PseudoVAESKF2_VI_M4, VAESKF2_VI, 0x2, 0x0 }, // 312
|
|
{ PseudoVAESKF2_VI_M8, VAESKF2_VI, 0x3, 0x0 }, // 313
|
|
{ PseudoVAESKF2_VI_MF2, VAESKF2_VI, 0x7, 0x0 }, // 314
|
|
{ PseudoVAESZ_VS_M1_M1, VAESZ_VS, 0x0, 0x0 }, // 315
|
|
{ PseudoVAESZ_VS_M1_MF2, VAESZ_VS, 0x0, 0x0 }, // 316
|
|
{ PseudoVAESZ_VS_M1_MF4, VAESZ_VS, 0x0, 0x0 }, // 317
|
|
{ PseudoVAESZ_VS_M1_MF8, VAESZ_VS, 0x0, 0x0 }, // 318
|
|
{ PseudoVAESZ_VS_M2_M1, VAESZ_VS, 0x1, 0x0 }, // 319
|
|
{ PseudoVAESZ_VS_M2_M2, VAESZ_VS, 0x1, 0x0 }, // 320
|
|
{ PseudoVAESZ_VS_M2_MF2, VAESZ_VS, 0x1, 0x0 }, // 321
|
|
{ PseudoVAESZ_VS_M2_MF4, VAESZ_VS, 0x1, 0x0 }, // 322
|
|
{ PseudoVAESZ_VS_M2_MF8, VAESZ_VS, 0x1, 0x0 }, // 323
|
|
{ PseudoVAESZ_VS_M4_M1, VAESZ_VS, 0x2, 0x0 }, // 324
|
|
{ PseudoVAESZ_VS_M4_M2, VAESZ_VS, 0x2, 0x0 }, // 325
|
|
{ PseudoVAESZ_VS_M4_M4, VAESZ_VS, 0x2, 0x0 }, // 326
|
|
{ PseudoVAESZ_VS_M4_MF2, VAESZ_VS, 0x2, 0x0 }, // 327
|
|
{ PseudoVAESZ_VS_M4_MF4, VAESZ_VS, 0x2, 0x0 }, // 328
|
|
{ PseudoVAESZ_VS_M4_MF8, VAESZ_VS, 0x2, 0x0 }, // 329
|
|
{ PseudoVAESZ_VS_M8_M1, VAESZ_VS, 0x3, 0x0 }, // 330
|
|
{ PseudoVAESZ_VS_M8_M2, VAESZ_VS, 0x3, 0x0 }, // 331
|
|
{ PseudoVAESZ_VS_M8_M4, VAESZ_VS, 0x3, 0x0 }, // 332
|
|
{ PseudoVAESZ_VS_M8_MF2, VAESZ_VS, 0x3, 0x0 }, // 333
|
|
{ PseudoVAESZ_VS_M8_MF4, VAESZ_VS, 0x3, 0x0 }, // 334
|
|
{ PseudoVAESZ_VS_M8_MF8, VAESZ_VS, 0x3, 0x0 }, // 335
|
|
{ PseudoVAESZ_VS_MF2_MF2, VAESZ_VS, 0x7, 0x0 }, // 336
|
|
{ PseudoVAESZ_VS_MF2_MF4, VAESZ_VS, 0x7, 0x0 }, // 337
|
|
{ PseudoVAESZ_VS_MF2_MF8, VAESZ_VS, 0x7, 0x0 }, // 338
|
|
{ PseudoVANDN_VV_M1, VANDN_VV, 0x0, 0x0 }, // 339
|
|
{ PseudoVANDN_VV_M1_MASK, VANDN_VV, 0x0, 0x0 }, // 340
|
|
{ PseudoVANDN_VV_M2, VANDN_VV, 0x1, 0x0 }, // 341
|
|
{ PseudoVANDN_VV_M2_MASK, VANDN_VV, 0x1, 0x0 }, // 342
|
|
{ PseudoVANDN_VV_M4, VANDN_VV, 0x2, 0x0 }, // 343
|
|
{ PseudoVANDN_VV_M4_MASK, VANDN_VV, 0x2, 0x0 }, // 344
|
|
{ PseudoVANDN_VV_M8, VANDN_VV, 0x3, 0x0 }, // 345
|
|
{ PseudoVANDN_VV_M8_MASK, VANDN_VV, 0x3, 0x0 }, // 346
|
|
{ PseudoVANDN_VV_MF8, VANDN_VV, 0x5, 0x0 }, // 347
|
|
{ PseudoVANDN_VV_MF8_MASK, VANDN_VV, 0x5, 0x0 }, // 348
|
|
{ PseudoVANDN_VV_MF4, VANDN_VV, 0x6, 0x0 }, // 349
|
|
{ PseudoVANDN_VV_MF4_MASK, VANDN_VV, 0x6, 0x0 }, // 350
|
|
{ PseudoVANDN_VV_MF2, VANDN_VV, 0x7, 0x0 }, // 351
|
|
{ PseudoVANDN_VV_MF2_MASK, VANDN_VV, 0x7, 0x0 }, // 352
|
|
{ PseudoVANDN_VX_M1, VANDN_VX, 0x0, 0x0 }, // 353
|
|
{ PseudoVANDN_VX_M1_MASK, VANDN_VX, 0x0, 0x0 }, // 354
|
|
{ PseudoVANDN_VX_M2, VANDN_VX, 0x1, 0x0 }, // 355
|
|
{ PseudoVANDN_VX_M2_MASK, VANDN_VX, 0x1, 0x0 }, // 356
|
|
{ PseudoVANDN_VX_M4, VANDN_VX, 0x2, 0x0 }, // 357
|
|
{ PseudoVANDN_VX_M4_MASK, VANDN_VX, 0x2, 0x0 }, // 358
|
|
{ PseudoVANDN_VX_M8, VANDN_VX, 0x3, 0x0 }, // 359
|
|
{ PseudoVANDN_VX_M8_MASK, VANDN_VX, 0x3, 0x0 }, // 360
|
|
{ PseudoVANDN_VX_MF8, VANDN_VX, 0x5, 0x0 }, // 361
|
|
{ PseudoVANDN_VX_MF8_MASK, VANDN_VX, 0x5, 0x0 }, // 362
|
|
{ PseudoVANDN_VX_MF4, VANDN_VX, 0x6, 0x0 }, // 363
|
|
{ PseudoVANDN_VX_MF4_MASK, VANDN_VX, 0x6, 0x0 }, // 364
|
|
{ PseudoVANDN_VX_MF2, VANDN_VX, 0x7, 0x0 }, // 365
|
|
{ PseudoVANDN_VX_MF2_MASK, VANDN_VX, 0x7, 0x0 }, // 366
|
|
{ PseudoVAND_VI_M1, VAND_VI, 0x0, 0x0 }, // 367
|
|
{ PseudoVAND_VI_M1_MASK, VAND_VI, 0x0, 0x0 }, // 368
|
|
{ PseudoVAND_VI_M2, VAND_VI, 0x1, 0x0 }, // 369
|
|
{ PseudoVAND_VI_M2_MASK, VAND_VI, 0x1, 0x0 }, // 370
|
|
{ PseudoVAND_VI_M4, VAND_VI, 0x2, 0x0 }, // 371
|
|
{ PseudoVAND_VI_M4_MASK, VAND_VI, 0x2, 0x0 }, // 372
|
|
{ PseudoVAND_VI_M8, VAND_VI, 0x3, 0x0 }, // 373
|
|
{ PseudoVAND_VI_M8_MASK, VAND_VI, 0x3, 0x0 }, // 374
|
|
{ PseudoVAND_VI_MF8, VAND_VI, 0x5, 0x0 }, // 375
|
|
{ PseudoVAND_VI_MF8_MASK, VAND_VI, 0x5, 0x0 }, // 376
|
|
{ PseudoVAND_VI_MF4, VAND_VI, 0x6, 0x0 }, // 377
|
|
{ PseudoVAND_VI_MF4_MASK, VAND_VI, 0x6, 0x0 }, // 378
|
|
{ PseudoVAND_VI_MF2, VAND_VI, 0x7, 0x0 }, // 379
|
|
{ PseudoVAND_VI_MF2_MASK, VAND_VI, 0x7, 0x0 }, // 380
|
|
{ PseudoVAND_VV_M1, VAND_VV, 0x0, 0x0 }, // 381
|
|
{ PseudoVAND_VV_M1_MASK, VAND_VV, 0x0, 0x0 }, // 382
|
|
{ PseudoVAND_VV_M2, VAND_VV, 0x1, 0x0 }, // 383
|
|
{ PseudoVAND_VV_M2_MASK, VAND_VV, 0x1, 0x0 }, // 384
|
|
{ PseudoVAND_VV_M4, VAND_VV, 0x2, 0x0 }, // 385
|
|
{ PseudoVAND_VV_M4_MASK, VAND_VV, 0x2, 0x0 }, // 386
|
|
{ PseudoVAND_VV_M8, VAND_VV, 0x3, 0x0 }, // 387
|
|
{ PseudoVAND_VV_M8_MASK, VAND_VV, 0x3, 0x0 }, // 388
|
|
{ PseudoVAND_VV_MF8, VAND_VV, 0x5, 0x0 }, // 389
|
|
{ PseudoVAND_VV_MF8_MASK, VAND_VV, 0x5, 0x0 }, // 390
|
|
{ PseudoVAND_VV_MF4, VAND_VV, 0x6, 0x0 }, // 391
|
|
{ PseudoVAND_VV_MF4_MASK, VAND_VV, 0x6, 0x0 }, // 392
|
|
{ PseudoVAND_VV_MF2, VAND_VV, 0x7, 0x0 }, // 393
|
|
{ PseudoVAND_VV_MF2_MASK, VAND_VV, 0x7, 0x0 }, // 394
|
|
{ PseudoVAND_VX_M1, VAND_VX, 0x0, 0x0 }, // 395
|
|
{ PseudoVAND_VX_M1_MASK, VAND_VX, 0x0, 0x0 }, // 396
|
|
{ PseudoVAND_VX_M2, VAND_VX, 0x1, 0x0 }, // 397
|
|
{ PseudoVAND_VX_M2_MASK, VAND_VX, 0x1, 0x0 }, // 398
|
|
{ PseudoVAND_VX_M4, VAND_VX, 0x2, 0x0 }, // 399
|
|
{ PseudoVAND_VX_M4_MASK, VAND_VX, 0x2, 0x0 }, // 400
|
|
{ PseudoVAND_VX_M8, VAND_VX, 0x3, 0x0 }, // 401
|
|
{ PseudoVAND_VX_M8_MASK, VAND_VX, 0x3, 0x0 }, // 402
|
|
{ PseudoVAND_VX_MF8, VAND_VX, 0x5, 0x0 }, // 403
|
|
{ PseudoVAND_VX_MF8_MASK, VAND_VX, 0x5, 0x0 }, // 404
|
|
{ PseudoVAND_VX_MF4, VAND_VX, 0x6, 0x0 }, // 405
|
|
{ PseudoVAND_VX_MF4_MASK, VAND_VX, 0x6, 0x0 }, // 406
|
|
{ PseudoVAND_VX_MF2, VAND_VX, 0x7, 0x0 }, // 407
|
|
{ PseudoVAND_VX_MF2_MASK, VAND_VX, 0x7, 0x0 }, // 408
|
|
{ PseudoVASUBU_VV_M1, VASUBU_VV, 0x0, 0x0 }, // 409
|
|
{ PseudoVASUBU_VV_M1_MASK, VASUBU_VV, 0x0, 0x0 }, // 410
|
|
{ PseudoVASUBU_VV_M2, VASUBU_VV, 0x1, 0x0 }, // 411
|
|
{ PseudoVASUBU_VV_M2_MASK, VASUBU_VV, 0x1, 0x0 }, // 412
|
|
{ PseudoVASUBU_VV_M4, VASUBU_VV, 0x2, 0x0 }, // 413
|
|
{ PseudoVASUBU_VV_M4_MASK, VASUBU_VV, 0x2, 0x0 }, // 414
|
|
{ PseudoVASUBU_VV_M8, VASUBU_VV, 0x3, 0x0 }, // 415
|
|
{ PseudoVASUBU_VV_M8_MASK, VASUBU_VV, 0x3, 0x0 }, // 416
|
|
{ PseudoVASUBU_VV_MF8, VASUBU_VV, 0x5, 0x0 }, // 417
|
|
{ PseudoVASUBU_VV_MF8_MASK, VASUBU_VV, 0x5, 0x0 }, // 418
|
|
{ PseudoVASUBU_VV_MF4, VASUBU_VV, 0x6, 0x0 }, // 419
|
|
{ PseudoVASUBU_VV_MF4_MASK, VASUBU_VV, 0x6, 0x0 }, // 420
|
|
{ PseudoVASUBU_VV_MF2, VASUBU_VV, 0x7, 0x0 }, // 421
|
|
{ PseudoVASUBU_VV_MF2_MASK, VASUBU_VV, 0x7, 0x0 }, // 422
|
|
{ PseudoVASUBU_VX_M1, VASUBU_VX, 0x0, 0x0 }, // 423
|
|
{ PseudoVASUBU_VX_M1_MASK, VASUBU_VX, 0x0, 0x0 }, // 424
|
|
{ PseudoVASUBU_VX_M2, VASUBU_VX, 0x1, 0x0 }, // 425
|
|
{ PseudoVASUBU_VX_M2_MASK, VASUBU_VX, 0x1, 0x0 }, // 426
|
|
{ PseudoVASUBU_VX_M4, VASUBU_VX, 0x2, 0x0 }, // 427
|
|
{ PseudoVASUBU_VX_M4_MASK, VASUBU_VX, 0x2, 0x0 }, // 428
|
|
{ PseudoVASUBU_VX_M8, VASUBU_VX, 0x3, 0x0 }, // 429
|
|
{ PseudoVASUBU_VX_M8_MASK, VASUBU_VX, 0x3, 0x0 }, // 430
|
|
{ PseudoVASUBU_VX_MF8, VASUBU_VX, 0x5, 0x0 }, // 431
|
|
{ PseudoVASUBU_VX_MF8_MASK, VASUBU_VX, 0x5, 0x0 }, // 432
|
|
{ PseudoVASUBU_VX_MF4, VASUBU_VX, 0x6, 0x0 }, // 433
|
|
{ PseudoVASUBU_VX_MF4_MASK, VASUBU_VX, 0x6, 0x0 }, // 434
|
|
{ PseudoVASUBU_VX_MF2, VASUBU_VX, 0x7, 0x0 }, // 435
|
|
{ PseudoVASUBU_VX_MF2_MASK, VASUBU_VX, 0x7, 0x0 }, // 436
|
|
{ PseudoVASUB_VV_M1, VASUB_VV, 0x0, 0x0 }, // 437
|
|
{ PseudoVASUB_VV_M1_MASK, VASUB_VV, 0x0, 0x0 }, // 438
|
|
{ PseudoVASUB_VV_M2, VASUB_VV, 0x1, 0x0 }, // 439
|
|
{ PseudoVASUB_VV_M2_MASK, VASUB_VV, 0x1, 0x0 }, // 440
|
|
{ PseudoVASUB_VV_M4, VASUB_VV, 0x2, 0x0 }, // 441
|
|
{ PseudoVASUB_VV_M4_MASK, VASUB_VV, 0x2, 0x0 }, // 442
|
|
{ PseudoVASUB_VV_M8, VASUB_VV, 0x3, 0x0 }, // 443
|
|
{ PseudoVASUB_VV_M8_MASK, VASUB_VV, 0x3, 0x0 }, // 444
|
|
{ PseudoVASUB_VV_MF8, VASUB_VV, 0x5, 0x0 }, // 445
|
|
{ PseudoVASUB_VV_MF8_MASK, VASUB_VV, 0x5, 0x0 }, // 446
|
|
{ PseudoVASUB_VV_MF4, VASUB_VV, 0x6, 0x0 }, // 447
|
|
{ PseudoVASUB_VV_MF4_MASK, VASUB_VV, 0x6, 0x0 }, // 448
|
|
{ PseudoVASUB_VV_MF2, VASUB_VV, 0x7, 0x0 }, // 449
|
|
{ PseudoVASUB_VV_MF2_MASK, VASUB_VV, 0x7, 0x0 }, // 450
|
|
{ PseudoVASUB_VX_M1, VASUB_VX, 0x0, 0x0 }, // 451
|
|
{ PseudoVASUB_VX_M1_MASK, VASUB_VX, 0x0, 0x0 }, // 452
|
|
{ PseudoVASUB_VX_M2, VASUB_VX, 0x1, 0x0 }, // 453
|
|
{ PseudoVASUB_VX_M2_MASK, VASUB_VX, 0x1, 0x0 }, // 454
|
|
{ PseudoVASUB_VX_M4, VASUB_VX, 0x2, 0x0 }, // 455
|
|
{ PseudoVASUB_VX_M4_MASK, VASUB_VX, 0x2, 0x0 }, // 456
|
|
{ PseudoVASUB_VX_M8, VASUB_VX, 0x3, 0x0 }, // 457
|
|
{ PseudoVASUB_VX_M8_MASK, VASUB_VX, 0x3, 0x0 }, // 458
|
|
{ PseudoVASUB_VX_MF8, VASUB_VX, 0x5, 0x0 }, // 459
|
|
{ PseudoVASUB_VX_MF8_MASK, VASUB_VX, 0x5, 0x0 }, // 460
|
|
{ PseudoVASUB_VX_MF4, VASUB_VX, 0x6, 0x0 }, // 461
|
|
{ PseudoVASUB_VX_MF4_MASK, VASUB_VX, 0x6, 0x0 }, // 462
|
|
{ PseudoVASUB_VX_MF2, VASUB_VX, 0x7, 0x0 }, // 463
|
|
{ PseudoVASUB_VX_MF2_MASK, VASUB_VX, 0x7, 0x0 }, // 464
|
|
{ PseudoVBREV8_V_M1, VBREV8_V, 0x0, 0x0 }, // 465
|
|
{ PseudoVBREV8_V_M1_MASK, VBREV8_V, 0x0, 0x0 }, // 466
|
|
{ PseudoVBREV8_V_M2, VBREV8_V, 0x1, 0x0 }, // 467
|
|
{ PseudoVBREV8_V_M2_MASK, VBREV8_V, 0x1, 0x0 }, // 468
|
|
{ PseudoVBREV8_V_M4, VBREV8_V, 0x2, 0x0 }, // 469
|
|
{ PseudoVBREV8_V_M4_MASK, VBREV8_V, 0x2, 0x0 }, // 470
|
|
{ PseudoVBREV8_V_M8, VBREV8_V, 0x3, 0x0 }, // 471
|
|
{ PseudoVBREV8_V_M8_MASK, VBREV8_V, 0x3, 0x0 }, // 472
|
|
{ PseudoVBREV8_V_MF8, VBREV8_V, 0x5, 0x0 }, // 473
|
|
{ PseudoVBREV8_V_MF8_MASK, VBREV8_V, 0x5, 0x0 }, // 474
|
|
{ PseudoVBREV8_V_MF4, VBREV8_V, 0x6, 0x0 }, // 475
|
|
{ PseudoVBREV8_V_MF4_MASK, VBREV8_V, 0x6, 0x0 }, // 476
|
|
{ PseudoVBREV8_V_MF2, VBREV8_V, 0x7, 0x0 }, // 477
|
|
{ PseudoVBREV8_V_MF2_MASK, VBREV8_V, 0x7, 0x0 }, // 478
|
|
{ PseudoVBREV_V_M1, VBREV_V, 0x0, 0x0 }, // 479
|
|
{ PseudoVBREV_V_M1_MASK, VBREV_V, 0x0, 0x0 }, // 480
|
|
{ PseudoVBREV_V_M2, VBREV_V, 0x1, 0x0 }, // 481
|
|
{ PseudoVBREV_V_M2_MASK, VBREV_V, 0x1, 0x0 }, // 482
|
|
{ PseudoVBREV_V_M4, VBREV_V, 0x2, 0x0 }, // 483
|
|
{ PseudoVBREV_V_M4_MASK, VBREV_V, 0x2, 0x0 }, // 484
|
|
{ PseudoVBREV_V_M8, VBREV_V, 0x3, 0x0 }, // 485
|
|
{ PseudoVBREV_V_M8_MASK, VBREV_V, 0x3, 0x0 }, // 486
|
|
{ PseudoVBREV_V_MF8, VBREV_V, 0x5, 0x0 }, // 487
|
|
{ PseudoVBREV_V_MF8_MASK, VBREV_V, 0x5, 0x0 }, // 488
|
|
{ PseudoVBREV_V_MF4, VBREV_V, 0x6, 0x0 }, // 489
|
|
{ PseudoVBREV_V_MF4_MASK, VBREV_V, 0x6, 0x0 }, // 490
|
|
{ PseudoVBREV_V_MF2, VBREV_V, 0x7, 0x0 }, // 491
|
|
{ PseudoVBREV_V_MF2_MASK, VBREV_V, 0x7, 0x0 }, // 492
|
|
{ PseudoVCLMULH_VV_M1, VCLMULH_VV, 0x0, 0x0 }, // 493
|
|
{ PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV, 0x0, 0x0 }, // 494
|
|
{ PseudoVCLMULH_VV_M2, VCLMULH_VV, 0x1, 0x0 }, // 495
|
|
{ PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV, 0x1, 0x0 }, // 496
|
|
{ PseudoVCLMULH_VV_M4, VCLMULH_VV, 0x2, 0x0 }, // 497
|
|
{ PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV, 0x2, 0x0 }, // 498
|
|
{ PseudoVCLMULH_VV_M8, VCLMULH_VV, 0x3, 0x0 }, // 499
|
|
{ PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV, 0x3, 0x0 }, // 500
|
|
{ PseudoVCLMULH_VV_MF8, VCLMULH_VV, 0x5, 0x0 }, // 501
|
|
{ PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV, 0x5, 0x0 }, // 502
|
|
{ PseudoVCLMULH_VV_MF4, VCLMULH_VV, 0x6, 0x0 }, // 503
|
|
{ PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV, 0x6, 0x0 }, // 504
|
|
{ PseudoVCLMULH_VV_MF2, VCLMULH_VV, 0x7, 0x0 }, // 505
|
|
{ PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV, 0x7, 0x0 }, // 506
|
|
{ PseudoVCLMULH_VX_M1, VCLMULH_VX, 0x0, 0x0 }, // 507
|
|
{ PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX, 0x0, 0x0 }, // 508
|
|
{ PseudoVCLMULH_VX_M2, VCLMULH_VX, 0x1, 0x0 }, // 509
|
|
{ PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX, 0x1, 0x0 }, // 510
|
|
{ PseudoVCLMULH_VX_M4, VCLMULH_VX, 0x2, 0x0 }, // 511
|
|
{ PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX, 0x2, 0x0 }, // 512
|
|
{ PseudoVCLMULH_VX_M8, VCLMULH_VX, 0x3, 0x0 }, // 513
|
|
{ PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX, 0x3, 0x0 }, // 514
|
|
{ PseudoVCLMULH_VX_MF8, VCLMULH_VX, 0x5, 0x0 }, // 515
|
|
{ PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX, 0x5, 0x0 }, // 516
|
|
{ PseudoVCLMULH_VX_MF4, VCLMULH_VX, 0x6, 0x0 }, // 517
|
|
{ PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX, 0x6, 0x0 }, // 518
|
|
{ PseudoVCLMULH_VX_MF2, VCLMULH_VX, 0x7, 0x0 }, // 519
|
|
{ PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX, 0x7, 0x0 }, // 520
|
|
{ PseudoVCLMUL_VV_M1, VCLMUL_VV, 0x0, 0x0 }, // 521
|
|
{ PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV, 0x0, 0x0 }, // 522
|
|
{ PseudoVCLMUL_VV_M2, VCLMUL_VV, 0x1, 0x0 }, // 523
|
|
{ PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV, 0x1, 0x0 }, // 524
|
|
{ PseudoVCLMUL_VV_M4, VCLMUL_VV, 0x2, 0x0 }, // 525
|
|
{ PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV, 0x2, 0x0 }, // 526
|
|
{ PseudoVCLMUL_VV_M8, VCLMUL_VV, 0x3, 0x0 }, // 527
|
|
{ PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV, 0x3, 0x0 }, // 528
|
|
{ PseudoVCLMUL_VV_MF8, VCLMUL_VV, 0x5, 0x0 }, // 529
|
|
{ PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV, 0x5, 0x0 }, // 530
|
|
{ PseudoVCLMUL_VV_MF4, VCLMUL_VV, 0x6, 0x0 }, // 531
|
|
{ PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV, 0x6, 0x0 }, // 532
|
|
{ PseudoVCLMUL_VV_MF2, VCLMUL_VV, 0x7, 0x0 }, // 533
|
|
{ PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV, 0x7, 0x0 }, // 534
|
|
{ PseudoVCLMUL_VX_M1, VCLMUL_VX, 0x0, 0x0 }, // 535
|
|
{ PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX, 0x0, 0x0 }, // 536
|
|
{ PseudoVCLMUL_VX_M2, VCLMUL_VX, 0x1, 0x0 }, // 537
|
|
{ PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX, 0x1, 0x0 }, // 538
|
|
{ PseudoVCLMUL_VX_M4, VCLMUL_VX, 0x2, 0x0 }, // 539
|
|
{ PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX, 0x2, 0x0 }, // 540
|
|
{ PseudoVCLMUL_VX_M8, VCLMUL_VX, 0x3, 0x0 }, // 541
|
|
{ PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX, 0x3, 0x0 }, // 542
|
|
{ PseudoVCLMUL_VX_MF8, VCLMUL_VX, 0x5, 0x0 }, // 543
|
|
{ PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX, 0x5, 0x0 }, // 544
|
|
{ PseudoVCLMUL_VX_MF4, VCLMUL_VX, 0x6, 0x0 }, // 545
|
|
{ PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX, 0x6, 0x0 }, // 546
|
|
{ PseudoVCLMUL_VX_MF2, VCLMUL_VX, 0x7, 0x0 }, // 547
|
|
{ PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX, 0x7, 0x0 }, // 548
|
|
{ PseudoVCLZ_V_M1, VCLZ_V, 0x0, 0x0 }, // 549
|
|
{ PseudoVCLZ_V_M1_MASK, VCLZ_V, 0x0, 0x0 }, // 550
|
|
{ PseudoVCLZ_V_M2, VCLZ_V, 0x1, 0x0 }, // 551
|
|
{ PseudoVCLZ_V_M2_MASK, VCLZ_V, 0x1, 0x0 }, // 552
|
|
{ PseudoVCLZ_V_M4, VCLZ_V, 0x2, 0x0 }, // 553
|
|
{ PseudoVCLZ_V_M4_MASK, VCLZ_V, 0x2, 0x0 }, // 554
|
|
{ PseudoVCLZ_V_M8, VCLZ_V, 0x3, 0x0 }, // 555
|
|
{ PseudoVCLZ_V_M8_MASK, VCLZ_V, 0x3, 0x0 }, // 556
|
|
{ PseudoVCLZ_V_MF8, VCLZ_V, 0x5, 0x0 }, // 557
|
|
{ PseudoVCLZ_V_MF8_MASK, VCLZ_V, 0x5, 0x0 }, // 558
|
|
{ PseudoVCLZ_V_MF4, VCLZ_V, 0x6, 0x0 }, // 559
|
|
{ PseudoVCLZ_V_MF4_MASK, VCLZ_V, 0x6, 0x0 }, // 560
|
|
{ PseudoVCLZ_V_MF2, VCLZ_V, 0x7, 0x0 }, // 561
|
|
{ PseudoVCLZ_V_MF2_MASK, VCLZ_V, 0x7, 0x0 }, // 562
|
|
{ PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM, 0x0, 0x8 }, // 563
|
|
{ PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM, 0x0, 0x10 }, // 564
|
|
{ PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM, 0x0, 0x20 }, // 565
|
|
{ PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM, 0x0, 0x40 }, // 566
|
|
{ PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM, 0x1, 0x8 }, // 567
|
|
{ PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM, 0x1, 0x10 }, // 568
|
|
{ PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM, 0x1, 0x20 }, // 569
|
|
{ PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM, 0x1, 0x40 }, // 570
|
|
{ PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM, 0x2, 0x8 }, // 571
|
|
{ PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM, 0x2, 0x10 }, // 572
|
|
{ PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM, 0x2, 0x20 }, // 573
|
|
{ PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM, 0x2, 0x40 }, // 574
|
|
{ PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM, 0x3, 0x8 }, // 575
|
|
{ PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM, 0x3, 0x10 }, // 576
|
|
{ PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM, 0x3, 0x20 }, // 577
|
|
{ PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM, 0x3, 0x40 }, // 578
|
|
{ PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM, 0x5, 0x8 }, // 579
|
|
{ PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM, 0x6, 0x8 }, // 580
|
|
{ PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM, 0x6, 0x10 }, // 581
|
|
{ PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM, 0x7, 0x8 }, // 582
|
|
{ PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM, 0x7, 0x10 }, // 583
|
|
{ PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM, 0x7, 0x20 }, // 584
|
|
{ PseudoVCPOP_M_B8, VCPOP_M, 0x0, 0x0 }, // 585
|
|
{ PseudoVCPOP_M_B8_MASK, VCPOP_M, 0x0, 0x0 }, // 586
|
|
{ PseudoVCPOP_M_B16, VCPOP_M, 0x1, 0x0 }, // 587
|
|
{ PseudoVCPOP_M_B16_MASK, VCPOP_M, 0x1, 0x0 }, // 588
|
|
{ PseudoVCPOP_M_B32, VCPOP_M, 0x2, 0x0 }, // 589
|
|
{ PseudoVCPOP_M_B32_MASK, VCPOP_M, 0x2, 0x0 }, // 590
|
|
{ PseudoVCPOP_M_B64, VCPOP_M, 0x3, 0x0 }, // 591
|
|
{ PseudoVCPOP_M_B64_MASK, VCPOP_M, 0x3, 0x0 }, // 592
|
|
{ PseudoVCPOP_M_B1, VCPOP_M, 0x5, 0x0 }, // 593
|
|
{ PseudoVCPOP_M_B1_MASK, VCPOP_M, 0x5, 0x0 }, // 594
|
|
{ PseudoVCPOP_M_B2, VCPOP_M, 0x6, 0x0 }, // 595
|
|
{ PseudoVCPOP_M_B2_MASK, VCPOP_M, 0x6, 0x0 }, // 596
|
|
{ PseudoVCPOP_M_B4, VCPOP_M, 0x7, 0x0 }, // 597
|
|
{ PseudoVCPOP_M_B4_MASK, VCPOP_M, 0x7, 0x0 }, // 598
|
|
{ PseudoVCPOP_V_M1, VCPOP_V, 0x0, 0x0 }, // 599
|
|
{ PseudoVCPOP_V_M1_MASK, VCPOP_V, 0x0, 0x0 }, // 600
|
|
{ PseudoVCPOP_V_M2, VCPOP_V, 0x1, 0x0 }, // 601
|
|
{ PseudoVCPOP_V_M2_MASK, VCPOP_V, 0x1, 0x0 }, // 602
|
|
{ PseudoVCPOP_V_M4, VCPOP_V, 0x2, 0x0 }, // 603
|
|
{ PseudoVCPOP_V_M4_MASK, VCPOP_V, 0x2, 0x0 }, // 604
|
|
{ PseudoVCPOP_V_M8, VCPOP_V, 0x3, 0x0 }, // 605
|
|
{ PseudoVCPOP_V_M8_MASK, VCPOP_V, 0x3, 0x0 }, // 606
|
|
{ PseudoVCPOP_V_MF8, VCPOP_V, 0x5, 0x0 }, // 607
|
|
{ PseudoVCPOP_V_MF8_MASK, VCPOP_V, 0x5, 0x0 }, // 608
|
|
{ PseudoVCPOP_V_MF4, VCPOP_V, 0x6, 0x0 }, // 609
|
|
{ PseudoVCPOP_V_MF4_MASK, VCPOP_V, 0x6, 0x0 }, // 610
|
|
{ PseudoVCPOP_V_MF2, VCPOP_V, 0x7, 0x0 }, // 611
|
|
{ PseudoVCPOP_V_MF2_MASK, VCPOP_V, 0x7, 0x0 }, // 612
|
|
{ PseudoVCTZ_V_M1, VCTZ_V, 0x0, 0x0 }, // 613
|
|
{ PseudoVCTZ_V_M1_MASK, VCTZ_V, 0x0, 0x0 }, // 614
|
|
{ PseudoVCTZ_V_M2, VCTZ_V, 0x1, 0x0 }, // 615
|
|
{ PseudoVCTZ_V_M2_MASK, VCTZ_V, 0x1, 0x0 }, // 616
|
|
{ PseudoVCTZ_V_M4, VCTZ_V, 0x2, 0x0 }, // 617
|
|
{ PseudoVCTZ_V_M4_MASK, VCTZ_V, 0x2, 0x0 }, // 618
|
|
{ PseudoVCTZ_V_M8, VCTZ_V, 0x3, 0x0 }, // 619
|
|
{ PseudoVCTZ_V_M8_MASK, VCTZ_V, 0x3, 0x0 }, // 620
|
|
{ PseudoVCTZ_V_MF8, VCTZ_V, 0x5, 0x0 }, // 621
|
|
{ PseudoVCTZ_V_MF8_MASK, VCTZ_V, 0x5, 0x0 }, // 622
|
|
{ PseudoVCTZ_V_MF4, VCTZ_V, 0x6, 0x0 }, // 623
|
|
{ PseudoVCTZ_V_MF4_MASK, VCTZ_V, 0x6, 0x0 }, // 624
|
|
{ PseudoVCTZ_V_MF2, VCTZ_V, 0x7, 0x0 }, // 625
|
|
{ PseudoVCTZ_V_MF2_MASK, VCTZ_V, 0x7, 0x0 }, // 626
|
|
{ PseudoVC_FPR16V_SE_M1, VC_FV, 0x0, 0x0 }, // 627
|
|
{ PseudoVC_FPR32V_SE_M1, VC_FV, 0x0, 0x0 }, // 628
|
|
{ PseudoVC_FPR64V_SE_M1, VC_FV, 0x0, 0x0 }, // 629
|
|
{ PseudoVC_FPR16V_SE_M2, VC_FV, 0x1, 0x0 }, // 630
|
|
{ PseudoVC_FPR32V_SE_M2, VC_FV, 0x1, 0x0 }, // 631
|
|
{ PseudoVC_FPR64V_SE_M2, VC_FV, 0x1, 0x0 }, // 632
|
|
{ PseudoVC_FPR16V_SE_M4, VC_FV, 0x2, 0x0 }, // 633
|
|
{ PseudoVC_FPR32V_SE_M4, VC_FV, 0x2, 0x0 }, // 634
|
|
{ PseudoVC_FPR64V_SE_M4, VC_FV, 0x2, 0x0 }, // 635
|
|
{ PseudoVC_FPR16V_SE_M8, VC_FV, 0x3, 0x0 }, // 636
|
|
{ PseudoVC_FPR32V_SE_M8, VC_FV, 0x3, 0x0 }, // 637
|
|
{ PseudoVC_FPR64V_SE_M8, VC_FV, 0x3, 0x0 }, // 638
|
|
{ PseudoVC_FPR16V_SE_MF4, VC_FV, 0x6, 0x0 }, // 639
|
|
{ PseudoVC_FPR16V_SE_MF2, VC_FV, 0x7, 0x0 }, // 640
|
|
{ PseudoVC_FPR32V_SE_MF2, VC_FV, 0x7, 0x0 }, // 641
|
|
{ PseudoVC_FPR16VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 642
|
|
{ PseudoVC_FPR32VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 643
|
|
{ PseudoVC_FPR64VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 644
|
|
{ PseudoVC_FPR16VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 645
|
|
{ PseudoVC_FPR32VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 646
|
|
{ PseudoVC_FPR64VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 647
|
|
{ PseudoVC_FPR16VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 648
|
|
{ PseudoVC_FPR32VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 649
|
|
{ PseudoVC_FPR64VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 650
|
|
{ PseudoVC_FPR16VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 651
|
|
{ PseudoVC_FPR32VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 652
|
|
{ PseudoVC_FPR64VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 653
|
|
{ PseudoVC_FPR16VV_SE_MF4, VC_FVV, 0x6, 0x0 }, // 654
|
|
{ PseudoVC_FPR16VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 655
|
|
{ PseudoVC_FPR32VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 656
|
|
{ PseudoVC_FPR16VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 657
|
|
{ PseudoVC_FPR32VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 658
|
|
{ PseudoVC_FPR16VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 659
|
|
{ PseudoVC_FPR32VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 660
|
|
{ PseudoVC_FPR16VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 661
|
|
{ PseudoVC_FPR32VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 662
|
|
{ PseudoVC_FPR16VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 663
|
|
{ PseudoVC_FPR32VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 664
|
|
{ PseudoVC_FPR16VW_SE_MF4, VC_FVW, 0x6, 0x0 }, // 665
|
|
{ PseudoVC_FPR16VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 666
|
|
{ PseudoVC_FPR32VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 667
|
|
{ PseudoVC_I_SE_M1, VC_I, 0x0, 0x0 }, // 668
|
|
{ PseudoVC_I_SE_M2, VC_I, 0x1, 0x0 }, // 669
|
|
{ PseudoVC_I_SE_M4, VC_I, 0x2, 0x0 }, // 670
|
|
{ PseudoVC_I_SE_M8, VC_I, 0x3, 0x0 }, // 671
|
|
{ PseudoVC_I_SE_MF8, VC_I, 0x5, 0x0 }, // 672
|
|
{ PseudoVC_I_SE_MF4, VC_I, 0x6, 0x0 }, // 673
|
|
{ PseudoVC_I_SE_MF2, VC_I, 0x7, 0x0 }, // 674
|
|
{ PseudoVC_IV_SE_M1, VC_IV, 0x0, 0x0 }, // 675
|
|
{ PseudoVC_IV_SE_M2, VC_IV, 0x1, 0x0 }, // 676
|
|
{ PseudoVC_IV_SE_M4, VC_IV, 0x2, 0x0 }, // 677
|
|
{ PseudoVC_IV_SE_M8, VC_IV, 0x3, 0x0 }, // 678
|
|
{ PseudoVC_IV_SE_MF8, VC_IV, 0x5, 0x0 }, // 679
|
|
{ PseudoVC_IV_SE_MF4, VC_IV, 0x6, 0x0 }, // 680
|
|
{ PseudoVC_IV_SE_MF2, VC_IV, 0x7, 0x0 }, // 681
|
|
{ PseudoVC_IVV_SE_M1, VC_IVV, 0x0, 0x0 }, // 682
|
|
{ PseudoVC_IVV_SE_M2, VC_IVV, 0x1, 0x0 }, // 683
|
|
{ PseudoVC_IVV_SE_M4, VC_IVV, 0x2, 0x0 }, // 684
|
|
{ PseudoVC_IVV_SE_M8, VC_IVV, 0x3, 0x0 }, // 685
|
|
{ PseudoVC_IVV_SE_MF8, VC_IVV, 0x5, 0x0 }, // 686
|
|
{ PseudoVC_IVV_SE_MF4, VC_IVV, 0x6, 0x0 }, // 687
|
|
{ PseudoVC_IVV_SE_MF2, VC_IVV, 0x7, 0x0 }, // 688
|
|
{ PseudoVC_IVW_SE_M1, VC_IVW, 0x0, 0x0 }, // 689
|
|
{ PseudoVC_IVW_SE_M2, VC_IVW, 0x1, 0x0 }, // 690
|
|
{ PseudoVC_IVW_SE_M4, VC_IVW, 0x2, 0x0 }, // 691
|
|
{ PseudoVC_IVW_SE_MF8, VC_IVW, 0x5, 0x0 }, // 692
|
|
{ PseudoVC_IVW_SE_MF4, VC_IVW, 0x6, 0x0 }, // 693
|
|
{ PseudoVC_IVW_SE_MF2, VC_IVW, 0x7, 0x0 }, // 694
|
|
{ PseudoVC_VV_SE_M1, VC_VV, 0x0, 0x0 }, // 695
|
|
{ PseudoVC_VV_SE_M2, VC_VV, 0x1, 0x0 }, // 696
|
|
{ PseudoVC_VV_SE_M4, VC_VV, 0x2, 0x0 }, // 697
|
|
{ PseudoVC_VV_SE_M8, VC_VV, 0x3, 0x0 }, // 698
|
|
{ PseudoVC_VV_SE_MF8, VC_VV, 0x5, 0x0 }, // 699
|
|
{ PseudoVC_VV_SE_MF4, VC_VV, 0x6, 0x0 }, // 700
|
|
{ PseudoVC_VV_SE_MF2, VC_VV, 0x7, 0x0 }, // 701
|
|
{ PseudoVC_VVV_SE_M1, VC_VVV, 0x0, 0x0 }, // 702
|
|
{ PseudoVC_VVV_SE_M2, VC_VVV, 0x1, 0x0 }, // 703
|
|
{ PseudoVC_VVV_SE_M4, VC_VVV, 0x2, 0x0 }, // 704
|
|
{ PseudoVC_VVV_SE_M8, VC_VVV, 0x3, 0x0 }, // 705
|
|
{ PseudoVC_VVV_SE_MF8, VC_VVV, 0x5, 0x0 }, // 706
|
|
{ PseudoVC_VVV_SE_MF4, VC_VVV, 0x6, 0x0 }, // 707
|
|
{ PseudoVC_VVV_SE_MF2, VC_VVV, 0x7, 0x0 }, // 708
|
|
{ PseudoVC_VVW_SE_M1, VC_VVW, 0x0, 0x0 }, // 709
|
|
{ PseudoVC_VVW_SE_M2, VC_VVW, 0x1, 0x0 }, // 710
|
|
{ PseudoVC_VVW_SE_M4, VC_VVW, 0x2, 0x0 }, // 711
|
|
{ PseudoVC_VVW_SE_MF8, VC_VVW, 0x5, 0x0 }, // 712
|
|
{ PseudoVC_VVW_SE_MF4, VC_VVW, 0x6, 0x0 }, // 713
|
|
{ PseudoVC_VVW_SE_MF2, VC_VVW, 0x7, 0x0 }, // 714
|
|
{ PseudoVC_V_FPR16V_M1, VC_V_FV, 0x0, 0x0 }, // 715
|
|
{ PseudoVC_V_FPR16V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 716
|
|
{ PseudoVC_V_FPR32V_M1, VC_V_FV, 0x0, 0x0 }, // 717
|
|
{ PseudoVC_V_FPR32V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 718
|
|
{ PseudoVC_V_FPR64V_M1, VC_V_FV, 0x0, 0x0 }, // 719
|
|
{ PseudoVC_V_FPR64V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 720
|
|
{ PseudoVC_V_FPR16V_M2, VC_V_FV, 0x1, 0x0 }, // 721
|
|
{ PseudoVC_V_FPR16V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 722
|
|
{ PseudoVC_V_FPR32V_M2, VC_V_FV, 0x1, 0x0 }, // 723
|
|
{ PseudoVC_V_FPR32V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 724
|
|
{ PseudoVC_V_FPR64V_M2, VC_V_FV, 0x1, 0x0 }, // 725
|
|
{ PseudoVC_V_FPR64V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 726
|
|
{ PseudoVC_V_FPR16V_M4, VC_V_FV, 0x2, 0x0 }, // 727
|
|
{ PseudoVC_V_FPR16V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 728
|
|
{ PseudoVC_V_FPR32V_M4, VC_V_FV, 0x2, 0x0 }, // 729
|
|
{ PseudoVC_V_FPR32V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 730
|
|
{ PseudoVC_V_FPR64V_M4, VC_V_FV, 0x2, 0x0 }, // 731
|
|
{ PseudoVC_V_FPR64V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 732
|
|
{ PseudoVC_V_FPR16V_M8, VC_V_FV, 0x3, 0x0 }, // 733
|
|
{ PseudoVC_V_FPR16V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 734
|
|
{ PseudoVC_V_FPR32V_M8, VC_V_FV, 0x3, 0x0 }, // 735
|
|
{ PseudoVC_V_FPR32V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 736
|
|
{ PseudoVC_V_FPR64V_M8, VC_V_FV, 0x3, 0x0 }, // 737
|
|
{ PseudoVC_V_FPR64V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 738
|
|
{ PseudoVC_V_FPR16V_MF4, VC_V_FV, 0x6, 0x0 }, // 739
|
|
{ PseudoVC_V_FPR16V_SE_MF4, VC_V_FV, 0x6, 0x0 }, // 740
|
|
{ PseudoVC_V_FPR16V_MF2, VC_V_FV, 0x7, 0x0 }, // 741
|
|
{ PseudoVC_V_FPR16V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 742
|
|
{ PseudoVC_V_FPR32V_MF2, VC_V_FV, 0x7, 0x0 }, // 743
|
|
{ PseudoVC_V_FPR32V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 744
|
|
{ PseudoVC_V_FPR16VV_M1, VC_V_FVV, 0x0, 0x0 }, // 745
|
|
{ PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 746
|
|
{ PseudoVC_V_FPR32VV_M1, VC_V_FVV, 0x0, 0x0 }, // 747
|
|
{ PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 748
|
|
{ PseudoVC_V_FPR64VV_M1, VC_V_FVV, 0x0, 0x0 }, // 749
|
|
{ PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 750
|
|
{ PseudoVC_V_FPR16VV_M2, VC_V_FVV, 0x1, 0x0 }, // 751
|
|
{ PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 752
|
|
{ PseudoVC_V_FPR32VV_M2, VC_V_FVV, 0x1, 0x0 }, // 753
|
|
{ PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 754
|
|
{ PseudoVC_V_FPR64VV_M2, VC_V_FVV, 0x1, 0x0 }, // 755
|
|
{ PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 756
|
|
{ PseudoVC_V_FPR16VV_M4, VC_V_FVV, 0x2, 0x0 }, // 757
|
|
{ PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 758
|
|
{ PseudoVC_V_FPR32VV_M4, VC_V_FVV, 0x2, 0x0 }, // 759
|
|
{ PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 760
|
|
{ PseudoVC_V_FPR64VV_M4, VC_V_FVV, 0x2, 0x0 }, // 761
|
|
{ PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 762
|
|
{ PseudoVC_V_FPR16VV_M8, VC_V_FVV, 0x3, 0x0 }, // 763
|
|
{ PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 764
|
|
{ PseudoVC_V_FPR32VV_M8, VC_V_FVV, 0x3, 0x0 }, // 765
|
|
{ PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 766
|
|
{ PseudoVC_V_FPR64VV_M8, VC_V_FVV, 0x3, 0x0 }, // 767
|
|
{ PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 768
|
|
{ PseudoVC_V_FPR16VV_MF4, VC_V_FVV, 0x6, 0x0 }, // 769
|
|
{ PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV, 0x6, 0x0 }, // 770
|
|
{ PseudoVC_V_FPR16VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 771
|
|
{ PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 772
|
|
{ PseudoVC_V_FPR32VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 773
|
|
{ PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 774
|
|
{ PseudoVC_V_FPR16VW_M1, VC_V_FVW, 0x0, 0x0 }, // 775
|
|
{ PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 776
|
|
{ PseudoVC_V_FPR32VW_M1, VC_V_FVW, 0x0, 0x0 }, // 777
|
|
{ PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 778
|
|
{ PseudoVC_V_FPR16VW_M2, VC_V_FVW, 0x1, 0x0 }, // 779
|
|
{ PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 780
|
|
{ PseudoVC_V_FPR32VW_M2, VC_V_FVW, 0x1, 0x0 }, // 781
|
|
{ PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 782
|
|
{ PseudoVC_V_FPR16VW_M4, VC_V_FVW, 0x2, 0x0 }, // 783
|
|
{ PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 784
|
|
{ PseudoVC_V_FPR32VW_M4, VC_V_FVW, 0x2, 0x0 }, // 785
|
|
{ PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 786
|
|
{ PseudoVC_V_FPR16VW_M8, VC_V_FVW, 0x3, 0x0 }, // 787
|
|
{ PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 788
|
|
{ PseudoVC_V_FPR32VW_M8, VC_V_FVW, 0x3, 0x0 }, // 789
|
|
{ PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 790
|
|
{ PseudoVC_V_FPR16VW_MF4, VC_V_FVW, 0x6, 0x0 }, // 791
|
|
{ PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW, 0x6, 0x0 }, // 792
|
|
{ PseudoVC_V_FPR16VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 793
|
|
{ PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 794
|
|
{ PseudoVC_V_FPR32VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 795
|
|
{ PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 796
|
|
{ PseudoVC_V_I_M1, VC_V_I, 0x0, 0x0 }, // 797
|
|
{ PseudoVC_V_I_SE_M1, VC_V_I, 0x0, 0x0 }, // 798
|
|
{ PseudoVC_V_I_M2, VC_V_I, 0x1, 0x0 }, // 799
|
|
{ PseudoVC_V_I_SE_M2, VC_V_I, 0x1, 0x0 }, // 800
|
|
{ PseudoVC_V_I_M4, VC_V_I, 0x2, 0x0 }, // 801
|
|
{ PseudoVC_V_I_SE_M4, VC_V_I, 0x2, 0x0 }, // 802
|
|
{ PseudoVC_V_I_M8, VC_V_I, 0x3, 0x0 }, // 803
|
|
{ PseudoVC_V_I_SE_M8, VC_V_I, 0x3, 0x0 }, // 804
|
|
{ PseudoVC_V_I_MF8, VC_V_I, 0x5, 0x0 }, // 805
|
|
{ PseudoVC_V_I_SE_MF8, VC_V_I, 0x5, 0x0 }, // 806
|
|
{ PseudoVC_V_I_MF4, VC_V_I, 0x6, 0x0 }, // 807
|
|
{ PseudoVC_V_I_SE_MF4, VC_V_I, 0x6, 0x0 }, // 808
|
|
{ PseudoVC_V_I_MF2, VC_V_I, 0x7, 0x0 }, // 809
|
|
{ PseudoVC_V_I_SE_MF2, VC_V_I, 0x7, 0x0 }, // 810
|
|
{ PseudoVC_V_IV_M1, VC_V_IV, 0x0, 0x0 }, // 811
|
|
{ PseudoVC_V_IV_SE_M1, VC_V_IV, 0x0, 0x0 }, // 812
|
|
{ PseudoVC_V_IV_M2, VC_V_IV, 0x1, 0x0 }, // 813
|
|
{ PseudoVC_V_IV_SE_M2, VC_V_IV, 0x1, 0x0 }, // 814
|
|
{ PseudoVC_V_IV_M4, VC_V_IV, 0x2, 0x0 }, // 815
|
|
{ PseudoVC_V_IV_SE_M4, VC_V_IV, 0x2, 0x0 }, // 816
|
|
{ PseudoVC_V_IV_M8, VC_V_IV, 0x3, 0x0 }, // 817
|
|
{ PseudoVC_V_IV_SE_M8, VC_V_IV, 0x3, 0x0 }, // 818
|
|
{ PseudoVC_V_IV_MF8, VC_V_IV, 0x5, 0x0 }, // 819
|
|
{ PseudoVC_V_IV_SE_MF8, VC_V_IV, 0x5, 0x0 }, // 820
|
|
{ PseudoVC_V_IV_MF4, VC_V_IV, 0x6, 0x0 }, // 821
|
|
{ PseudoVC_V_IV_SE_MF4, VC_V_IV, 0x6, 0x0 }, // 822
|
|
{ PseudoVC_V_IV_MF2, VC_V_IV, 0x7, 0x0 }, // 823
|
|
{ PseudoVC_V_IV_SE_MF2, VC_V_IV, 0x7, 0x0 }, // 824
|
|
{ PseudoVC_V_IVV_M1, VC_V_IVV, 0x0, 0x0 }, // 825
|
|
{ PseudoVC_V_IVV_SE_M1, VC_V_IVV, 0x0, 0x0 }, // 826
|
|
{ PseudoVC_V_IVV_M2, VC_V_IVV, 0x1, 0x0 }, // 827
|
|
{ PseudoVC_V_IVV_SE_M2, VC_V_IVV, 0x1, 0x0 }, // 828
|
|
{ PseudoVC_V_IVV_M4, VC_V_IVV, 0x2, 0x0 }, // 829
|
|
{ PseudoVC_V_IVV_SE_M4, VC_V_IVV, 0x2, 0x0 }, // 830
|
|
{ PseudoVC_V_IVV_M8, VC_V_IVV, 0x3, 0x0 }, // 831
|
|
{ PseudoVC_V_IVV_SE_M8, VC_V_IVV, 0x3, 0x0 }, // 832
|
|
{ PseudoVC_V_IVV_MF8, VC_V_IVV, 0x5, 0x0 }, // 833
|
|
{ PseudoVC_V_IVV_SE_MF8, VC_V_IVV, 0x5, 0x0 }, // 834
|
|
{ PseudoVC_V_IVV_MF4, VC_V_IVV, 0x6, 0x0 }, // 835
|
|
{ PseudoVC_V_IVV_SE_MF4, VC_V_IVV, 0x6, 0x0 }, // 836
|
|
{ PseudoVC_V_IVV_MF2, VC_V_IVV, 0x7, 0x0 }, // 837
|
|
{ PseudoVC_V_IVV_SE_MF2, VC_V_IVV, 0x7, 0x0 }, // 838
|
|
{ PseudoVC_V_IVW_M1, VC_V_IVW, 0x0, 0x0 }, // 839
|
|
{ PseudoVC_V_IVW_SE_M1, VC_V_IVW, 0x0, 0x0 }, // 840
|
|
{ PseudoVC_V_IVW_M2, VC_V_IVW, 0x1, 0x0 }, // 841
|
|
{ PseudoVC_V_IVW_SE_M2, VC_V_IVW, 0x1, 0x0 }, // 842
|
|
{ PseudoVC_V_IVW_M4, VC_V_IVW, 0x2, 0x0 }, // 843
|
|
{ PseudoVC_V_IVW_SE_M4, VC_V_IVW, 0x2, 0x0 }, // 844
|
|
{ PseudoVC_V_IVW_MF8, VC_V_IVW, 0x5, 0x0 }, // 845
|
|
{ PseudoVC_V_IVW_SE_MF8, VC_V_IVW, 0x5, 0x0 }, // 846
|
|
{ PseudoVC_V_IVW_MF4, VC_V_IVW, 0x6, 0x0 }, // 847
|
|
{ PseudoVC_V_IVW_SE_MF4, VC_V_IVW, 0x6, 0x0 }, // 848
|
|
{ PseudoVC_V_IVW_MF2, VC_V_IVW, 0x7, 0x0 }, // 849
|
|
{ PseudoVC_V_IVW_SE_MF2, VC_V_IVW, 0x7, 0x0 }, // 850
|
|
{ PseudoVC_V_VV_M1, VC_V_VV, 0x0, 0x0 }, // 851
|
|
{ PseudoVC_V_VV_SE_M1, VC_V_VV, 0x0, 0x0 }, // 852
|
|
{ PseudoVC_V_VV_M2, VC_V_VV, 0x1, 0x0 }, // 853
|
|
{ PseudoVC_V_VV_SE_M2, VC_V_VV, 0x1, 0x0 }, // 854
|
|
{ PseudoVC_V_VV_M4, VC_V_VV, 0x2, 0x0 }, // 855
|
|
{ PseudoVC_V_VV_SE_M4, VC_V_VV, 0x2, 0x0 }, // 856
|
|
{ PseudoVC_V_VV_M8, VC_V_VV, 0x3, 0x0 }, // 857
|
|
{ PseudoVC_V_VV_SE_M8, VC_V_VV, 0x3, 0x0 }, // 858
|
|
{ PseudoVC_V_VV_MF8, VC_V_VV, 0x5, 0x0 }, // 859
|
|
{ PseudoVC_V_VV_SE_MF8, VC_V_VV, 0x5, 0x0 }, // 860
|
|
{ PseudoVC_V_VV_MF4, VC_V_VV, 0x6, 0x0 }, // 861
|
|
{ PseudoVC_V_VV_SE_MF4, VC_V_VV, 0x6, 0x0 }, // 862
|
|
{ PseudoVC_V_VV_MF2, VC_V_VV, 0x7, 0x0 }, // 863
|
|
{ PseudoVC_V_VV_SE_MF2, VC_V_VV, 0x7, 0x0 }, // 864
|
|
{ PseudoVC_V_VVV_M1, VC_V_VVV, 0x0, 0x0 }, // 865
|
|
{ PseudoVC_V_VVV_SE_M1, VC_V_VVV, 0x0, 0x0 }, // 866
|
|
{ PseudoVC_V_VVV_M2, VC_V_VVV, 0x1, 0x0 }, // 867
|
|
{ PseudoVC_V_VVV_SE_M2, VC_V_VVV, 0x1, 0x0 }, // 868
|
|
{ PseudoVC_V_VVV_M4, VC_V_VVV, 0x2, 0x0 }, // 869
|
|
{ PseudoVC_V_VVV_SE_M4, VC_V_VVV, 0x2, 0x0 }, // 870
|
|
{ PseudoVC_V_VVV_M8, VC_V_VVV, 0x3, 0x0 }, // 871
|
|
{ PseudoVC_V_VVV_SE_M8, VC_V_VVV, 0x3, 0x0 }, // 872
|
|
{ PseudoVC_V_VVV_MF8, VC_V_VVV, 0x5, 0x0 }, // 873
|
|
{ PseudoVC_V_VVV_SE_MF8, VC_V_VVV, 0x5, 0x0 }, // 874
|
|
{ PseudoVC_V_VVV_MF4, VC_V_VVV, 0x6, 0x0 }, // 875
|
|
{ PseudoVC_V_VVV_SE_MF4, VC_V_VVV, 0x6, 0x0 }, // 876
|
|
{ PseudoVC_V_VVV_MF2, VC_V_VVV, 0x7, 0x0 }, // 877
|
|
{ PseudoVC_V_VVV_SE_MF2, VC_V_VVV, 0x7, 0x0 }, // 878
|
|
{ PseudoVC_V_VVW_M1, VC_V_VVW, 0x0, 0x0 }, // 879
|
|
{ PseudoVC_V_VVW_SE_M1, VC_V_VVW, 0x0, 0x0 }, // 880
|
|
{ PseudoVC_V_VVW_M2, VC_V_VVW, 0x1, 0x0 }, // 881
|
|
{ PseudoVC_V_VVW_SE_M2, VC_V_VVW, 0x1, 0x0 }, // 882
|
|
{ PseudoVC_V_VVW_M4, VC_V_VVW, 0x2, 0x0 }, // 883
|
|
{ PseudoVC_V_VVW_SE_M4, VC_V_VVW, 0x2, 0x0 }, // 884
|
|
{ PseudoVC_V_VVW_MF8, VC_V_VVW, 0x5, 0x0 }, // 885
|
|
{ PseudoVC_V_VVW_SE_MF8, VC_V_VVW, 0x5, 0x0 }, // 886
|
|
{ PseudoVC_V_VVW_MF4, VC_V_VVW, 0x6, 0x0 }, // 887
|
|
{ PseudoVC_V_VVW_SE_MF4, VC_V_VVW, 0x6, 0x0 }, // 888
|
|
{ PseudoVC_V_VVW_MF2, VC_V_VVW, 0x7, 0x0 }, // 889
|
|
{ PseudoVC_V_VVW_SE_MF2, VC_V_VVW, 0x7, 0x0 }, // 890
|
|
{ PseudoVC_V_X_M1, VC_V_X, 0x0, 0x0 }, // 891
|
|
{ PseudoVC_V_X_SE_M1, VC_V_X, 0x0, 0x0 }, // 892
|
|
{ PseudoVC_V_X_M2, VC_V_X, 0x1, 0x0 }, // 893
|
|
{ PseudoVC_V_X_SE_M2, VC_V_X, 0x1, 0x0 }, // 894
|
|
{ PseudoVC_V_X_M4, VC_V_X, 0x2, 0x0 }, // 895
|
|
{ PseudoVC_V_X_SE_M4, VC_V_X, 0x2, 0x0 }, // 896
|
|
{ PseudoVC_V_X_M8, VC_V_X, 0x3, 0x0 }, // 897
|
|
{ PseudoVC_V_X_SE_M8, VC_V_X, 0x3, 0x0 }, // 898
|
|
{ PseudoVC_V_X_MF8, VC_V_X, 0x5, 0x0 }, // 899
|
|
{ PseudoVC_V_X_SE_MF8, VC_V_X, 0x5, 0x0 }, // 900
|
|
{ PseudoVC_V_X_MF4, VC_V_X, 0x6, 0x0 }, // 901
|
|
{ PseudoVC_V_X_SE_MF4, VC_V_X, 0x6, 0x0 }, // 902
|
|
{ PseudoVC_V_X_MF2, VC_V_X, 0x7, 0x0 }, // 903
|
|
{ PseudoVC_V_X_SE_MF2, VC_V_X, 0x7, 0x0 }, // 904
|
|
{ PseudoVC_V_XV_M1, VC_V_XV, 0x0, 0x0 }, // 905
|
|
{ PseudoVC_V_XV_SE_M1, VC_V_XV, 0x0, 0x0 }, // 906
|
|
{ PseudoVC_V_XV_M2, VC_V_XV, 0x1, 0x0 }, // 907
|
|
{ PseudoVC_V_XV_SE_M2, VC_V_XV, 0x1, 0x0 }, // 908
|
|
{ PseudoVC_V_XV_M4, VC_V_XV, 0x2, 0x0 }, // 909
|
|
{ PseudoVC_V_XV_SE_M4, VC_V_XV, 0x2, 0x0 }, // 910
|
|
{ PseudoVC_V_XV_M8, VC_V_XV, 0x3, 0x0 }, // 911
|
|
{ PseudoVC_V_XV_SE_M8, VC_V_XV, 0x3, 0x0 }, // 912
|
|
{ PseudoVC_V_XV_MF8, VC_V_XV, 0x5, 0x0 }, // 913
|
|
{ PseudoVC_V_XV_SE_MF8, VC_V_XV, 0x5, 0x0 }, // 914
|
|
{ PseudoVC_V_XV_MF4, VC_V_XV, 0x6, 0x0 }, // 915
|
|
{ PseudoVC_V_XV_SE_MF4, VC_V_XV, 0x6, 0x0 }, // 916
|
|
{ PseudoVC_V_XV_MF2, VC_V_XV, 0x7, 0x0 }, // 917
|
|
{ PseudoVC_V_XV_SE_MF2, VC_V_XV, 0x7, 0x0 }, // 918
|
|
{ PseudoVC_V_XVV_M1, VC_V_XVV, 0x0, 0x0 }, // 919
|
|
{ PseudoVC_V_XVV_SE_M1, VC_V_XVV, 0x0, 0x0 }, // 920
|
|
{ PseudoVC_V_XVV_M2, VC_V_XVV, 0x1, 0x0 }, // 921
|
|
{ PseudoVC_V_XVV_SE_M2, VC_V_XVV, 0x1, 0x0 }, // 922
|
|
{ PseudoVC_V_XVV_M4, VC_V_XVV, 0x2, 0x0 }, // 923
|
|
{ PseudoVC_V_XVV_SE_M4, VC_V_XVV, 0x2, 0x0 }, // 924
|
|
{ PseudoVC_V_XVV_M8, VC_V_XVV, 0x3, 0x0 }, // 925
|
|
{ PseudoVC_V_XVV_SE_M8, VC_V_XVV, 0x3, 0x0 }, // 926
|
|
{ PseudoVC_V_XVV_MF8, VC_V_XVV, 0x5, 0x0 }, // 927
|
|
{ PseudoVC_V_XVV_SE_MF8, VC_V_XVV, 0x5, 0x0 }, // 928
|
|
{ PseudoVC_V_XVV_MF4, VC_V_XVV, 0x6, 0x0 }, // 929
|
|
{ PseudoVC_V_XVV_SE_MF4, VC_V_XVV, 0x6, 0x0 }, // 930
|
|
{ PseudoVC_V_XVV_MF2, VC_V_XVV, 0x7, 0x0 }, // 931
|
|
{ PseudoVC_V_XVV_SE_MF2, VC_V_XVV, 0x7, 0x0 }, // 932
|
|
{ PseudoVC_V_XVW_M1, VC_V_XVW, 0x0, 0x0 }, // 933
|
|
{ PseudoVC_V_XVW_SE_M1, VC_V_XVW, 0x0, 0x0 }, // 934
|
|
{ PseudoVC_V_XVW_M2, VC_V_XVW, 0x1, 0x0 }, // 935
|
|
{ PseudoVC_V_XVW_SE_M2, VC_V_XVW, 0x1, 0x0 }, // 936
|
|
{ PseudoVC_V_XVW_M4, VC_V_XVW, 0x2, 0x0 }, // 937
|
|
{ PseudoVC_V_XVW_SE_M4, VC_V_XVW, 0x2, 0x0 }, // 938
|
|
{ PseudoVC_V_XVW_MF8, VC_V_XVW, 0x5, 0x0 }, // 939
|
|
{ PseudoVC_V_XVW_SE_MF8, VC_V_XVW, 0x5, 0x0 }, // 940
|
|
{ PseudoVC_V_XVW_MF4, VC_V_XVW, 0x6, 0x0 }, // 941
|
|
{ PseudoVC_V_XVW_SE_MF4, VC_V_XVW, 0x6, 0x0 }, // 942
|
|
{ PseudoVC_V_XVW_MF2, VC_V_XVW, 0x7, 0x0 }, // 943
|
|
{ PseudoVC_V_XVW_SE_MF2, VC_V_XVW, 0x7, 0x0 }, // 944
|
|
{ PseudoVC_X_SE_M1, VC_X, 0x0, 0x0 }, // 945
|
|
{ PseudoVC_X_SE_M2, VC_X, 0x1, 0x0 }, // 946
|
|
{ PseudoVC_X_SE_M4, VC_X, 0x2, 0x0 }, // 947
|
|
{ PseudoVC_X_SE_M8, VC_X, 0x3, 0x0 }, // 948
|
|
{ PseudoVC_X_SE_MF8, VC_X, 0x5, 0x0 }, // 949
|
|
{ PseudoVC_X_SE_MF4, VC_X, 0x6, 0x0 }, // 950
|
|
{ PseudoVC_X_SE_MF2, VC_X, 0x7, 0x0 }, // 951
|
|
{ PseudoVC_XV_SE_M1, VC_XV, 0x0, 0x0 }, // 952
|
|
{ PseudoVC_XV_SE_M2, VC_XV, 0x1, 0x0 }, // 953
|
|
{ PseudoVC_XV_SE_M4, VC_XV, 0x2, 0x0 }, // 954
|
|
{ PseudoVC_XV_SE_M8, VC_XV, 0x3, 0x0 }, // 955
|
|
{ PseudoVC_XV_SE_MF8, VC_XV, 0x5, 0x0 }, // 956
|
|
{ PseudoVC_XV_SE_MF4, VC_XV, 0x6, 0x0 }, // 957
|
|
{ PseudoVC_XV_SE_MF2, VC_XV, 0x7, 0x0 }, // 958
|
|
{ PseudoVC_XVV_SE_M1, VC_XVV, 0x0, 0x0 }, // 959
|
|
{ PseudoVC_XVV_SE_M2, VC_XVV, 0x1, 0x0 }, // 960
|
|
{ PseudoVC_XVV_SE_M4, VC_XVV, 0x2, 0x0 }, // 961
|
|
{ PseudoVC_XVV_SE_M8, VC_XVV, 0x3, 0x0 }, // 962
|
|
{ PseudoVC_XVV_SE_MF8, VC_XVV, 0x5, 0x0 }, // 963
|
|
{ PseudoVC_XVV_SE_MF4, VC_XVV, 0x6, 0x0 }, // 964
|
|
{ PseudoVC_XVV_SE_MF2, VC_XVV, 0x7, 0x0 }, // 965
|
|
{ PseudoVC_XVW_SE_M1, VC_XVW, 0x0, 0x0 }, // 966
|
|
{ PseudoVC_XVW_SE_M2, VC_XVW, 0x1, 0x0 }, // 967
|
|
{ PseudoVC_XVW_SE_M4, VC_XVW, 0x2, 0x0 }, // 968
|
|
{ PseudoVC_XVW_SE_MF8, VC_XVW, 0x5, 0x0 }, // 969
|
|
{ PseudoVC_XVW_SE_MF4, VC_XVW, 0x6, 0x0 }, // 970
|
|
{ PseudoVC_XVW_SE_MF2, VC_XVW, 0x7, 0x0 }, // 971
|
|
{ PseudoVDIVU_VV_M1_E8, VDIVU_VV, 0x0, 0x8 }, // 972
|
|
{ PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV, 0x0, 0x8 }, // 973
|
|
{ PseudoVDIVU_VV_M1_E16, VDIVU_VV, 0x0, 0x10 }, // 974
|
|
{ PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV, 0x0, 0x10 }, // 975
|
|
{ PseudoVDIVU_VV_M1_E32, VDIVU_VV, 0x0, 0x20 }, // 976
|
|
{ PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV, 0x0, 0x20 }, // 977
|
|
{ PseudoVDIVU_VV_M1_E64, VDIVU_VV, 0x0, 0x40 }, // 978
|
|
{ PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV, 0x0, 0x40 }, // 979
|
|
{ PseudoVDIVU_VV_M2_E8, VDIVU_VV, 0x1, 0x8 }, // 980
|
|
{ PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV, 0x1, 0x8 }, // 981
|
|
{ PseudoVDIVU_VV_M2_E16, VDIVU_VV, 0x1, 0x10 }, // 982
|
|
{ PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV, 0x1, 0x10 }, // 983
|
|
{ PseudoVDIVU_VV_M2_E32, VDIVU_VV, 0x1, 0x20 }, // 984
|
|
{ PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV, 0x1, 0x20 }, // 985
|
|
{ PseudoVDIVU_VV_M2_E64, VDIVU_VV, 0x1, 0x40 }, // 986
|
|
{ PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV, 0x1, 0x40 }, // 987
|
|
{ PseudoVDIVU_VV_M4_E8, VDIVU_VV, 0x2, 0x8 }, // 988
|
|
{ PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV, 0x2, 0x8 }, // 989
|
|
{ PseudoVDIVU_VV_M4_E16, VDIVU_VV, 0x2, 0x10 }, // 990
|
|
{ PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV, 0x2, 0x10 }, // 991
|
|
{ PseudoVDIVU_VV_M4_E32, VDIVU_VV, 0x2, 0x20 }, // 992
|
|
{ PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV, 0x2, 0x20 }, // 993
|
|
{ PseudoVDIVU_VV_M4_E64, VDIVU_VV, 0x2, 0x40 }, // 994
|
|
{ PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV, 0x2, 0x40 }, // 995
|
|
{ PseudoVDIVU_VV_M8_E8, VDIVU_VV, 0x3, 0x8 }, // 996
|
|
{ PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV, 0x3, 0x8 }, // 997
|
|
{ PseudoVDIVU_VV_M8_E16, VDIVU_VV, 0x3, 0x10 }, // 998
|
|
{ PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV, 0x3, 0x10 }, // 999
|
|
{ PseudoVDIVU_VV_M8_E32, VDIVU_VV, 0x3, 0x20 }, // 1000
|
|
{ PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV, 0x3, 0x20 }, // 1001
|
|
{ PseudoVDIVU_VV_M8_E64, VDIVU_VV, 0x3, 0x40 }, // 1002
|
|
{ PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV, 0x3, 0x40 }, // 1003
|
|
{ PseudoVDIVU_VV_MF8_E8, VDIVU_VV, 0x5, 0x8 }, // 1004
|
|
{ PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV, 0x5, 0x8 }, // 1005
|
|
{ PseudoVDIVU_VV_MF4_E8, VDIVU_VV, 0x6, 0x8 }, // 1006
|
|
{ PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV, 0x6, 0x8 }, // 1007
|
|
{ PseudoVDIVU_VV_MF4_E16, VDIVU_VV, 0x6, 0x10 }, // 1008
|
|
{ PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV, 0x6, 0x10 }, // 1009
|
|
{ PseudoVDIVU_VV_MF2_E8, VDIVU_VV, 0x7, 0x8 }, // 1010
|
|
{ PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV, 0x7, 0x8 }, // 1011
|
|
{ PseudoVDIVU_VV_MF2_E16, VDIVU_VV, 0x7, 0x10 }, // 1012
|
|
{ PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV, 0x7, 0x10 }, // 1013
|
|
{ PseudoVDIVU_VV_MF2_E32, VDIVU_VV, 0x7, 0x20 }, // 1014
|
|
{ PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV, 0x7, 0x20 }, // 1015
|
|
{ PseudoVDIVU_VX_M1_E8, VDIVU_VX, 0x0, 0x8 }, // 1016
|
|
{ PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX, 0x0, 0x8 }, // 1017
|
|
{ PseudoVDIVU_VX_M1_E16, VDIVU_VX, 0x0, 0x10 }, // 1018
|
|
{ PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX, 0x0, 0x10 }, // 1019
|
|
{ PseudoVDIVU_VX_M1_E32, VDIVU_VX, 0x0, 0x20 }, // 1020
|
|
{ PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX, 0x0, 0x20 }, // 1021
|
|
{ PseudoVDIVU_VX_M1_E64, VDIVU_VX, 0x0, 0x40 }, // 1022
|
|
{ PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX, 0x0, 0x40 }, // 1023
|
|
{ PseudoVDIVU_VX_M2_E8, VDIVU_VX, 0x1, 0x8 }, // 1024
|
|
{ PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX, 0x1, 0x8 }, // 1025
|
|
{ PseudoVDIVU_VX_M2_E16, VDIVU_VX, 0x1, 0x10 }, // 1026
|
|
{ PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX, 0x1, 0x10 }, // 1027
|
|
{ PseudoVDIVU_VX_M2_E32, VDIVU_VX, 0x1, 0x20 }, // 1028
|
|
{ PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX, 0x1, 0x20 }, // 1029
|
|
{ PseudoVDIVU_VX_M2_E64, VDIVU_VX, 0x1, 0x40 }, // 1030
|
|
{ PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX, 0x1, 0x40 }, // 1031
|
|
{ PseudoVDIVU_VX_M4_E8, VDIVU_VX, 0x2, 0x8 }, // 1032
|
|
{ PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX, 0x2, 0x8 }, // 1033
|
|
{ PseudoVDIVU_VX_M4_E16, VDIVU_VX, 0x2, 0x10 }, // 1034
|
|
{ PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX, 0x2, 0x10 }, // 1035
|
|
{ PseudoVDIVU_VX_M4_E32, VDIVU_VX, 0x2, 0x20 }, // 1036
|
|
{ PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX, 0x2, 0x20 }, // 1037
|
|
{ PseudoVDIVU_VX_M4_E64, VDIVU_VX, 0x2, 0x40 }, // 1038
|
|
{ PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX, 0x2, 0x40 }, // 1039
|
|
{ PseudoVDIVU_VX_M8_E8, VDIVU_VX, 0x3, 0x8 }, // 1040
|
|
{ PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX, 0x3, 0x8 }, // 1041
|
|
{ PseudoVDIVU_VX_M8_E16, VDIVU_VX, 0x3, 0x10 }, // 1042
|
|
{ PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX, 0x3, 0x10 }, // 1043
|
|
{ PseudoVDIVU_VX_M8_E32, VDIVU_VX, 0x3, 0x20 }, // 1044
|
|
{ PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX, 0x3, 0x20 }, // 1045
|
|
{ PseudoVDIVU_VX_M8_E64, VDIVU_VX, 0x3, 0x40 }, // 1046
|
|
{ PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX, 0x3, 0x40 }, // 1047
|
|
{ PseudoVDIVU_VX_MF8_E8, VDIVU_VX, 0x5, 0x8 }, // 1048
|
|
{ PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX, 0x5, 0x8 }, // 1049
|
|
{ PseudoVDIVU_VX_MF4_E8, VDIVU_VX, 0x6, 0x8 }, // 1050
|
|
{ PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX, 0x6, 0x8 }, // 1051
|
|
{ PseudoVDIVU_VX_MF4_E16, VDIVU_VX, 0x6, 0x10 }, // 1052
|
|
{ PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX, 0x6, 0x10 }, // 1053
|
|
{ PseudoVDIVU_VX_MF2_E8, VDIVU_VX, 0x7, 0x8 }, // 1054
|
|
{ PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX, 0x7, 0x8 }, // 1055
|
|
{ PseudoVDIVU_VX_MF2_E16, VDIVU_VX, 0x7, 0x10 }, // 1056
|
|
{ PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX, 0x7, 0x10 }, // 1057
|
|
{ PseudoVDIVU_VX_MF2_E32, VDIVU_VX, 0x7, 0x20 }, // 1058
|
|
{ PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX, 0x7, 0x20 }, // 1059
|
|
{ PseudoVDIV_VV_M1_E8, VDIV_VV, 0x0, 0x8 }, // 1060
|
|
{ PseudoVDIV_VV_M1_E8_MASK, VDIV_VV, 0x0, 0x8 }, // 1061
|
|
{ PseudoVDIV_VV_M1_E16, VDIV_VV, 0x0, 0x10 }, // 1062
|
|
{ PseudoVDIV_VV_M1_E16_MASK, VDIV_VV, 0x0, 0x10 }, // 1063
|
|
{ PseudoVDIV_VV_M1_E32, VDIV_VV, 0x0, 0x20 }, // 1064
|
|
{ PseudoVDIV_VV_M1_E32_MASK, VDIV_VV, 0x0, 0x20 }, // 1065
|
|
{ PseudoVDIV_VV_M1_E64, VDIV_VV, 0x0, 0x40 }, // 1066
|
|
{ PseudoVDIV_VV_M1_E64_MASK, VDIV_VV, 0x0, 0x40 }, // 1067
|
|
{ PseudoVDIV_VV_M2_E8, VDIV_VV, 0x1, 0x8 }, // 1068
|
|
{ PseudoVDIV_VV_M2_E8_MASK, VDIV_VV, 0x1, 0x8 }, // 1069
|
|
{ PseudoVDIV_VV_M2_E16, VDIV_VV, 0x1, 0x10 }, // 1070
|
|
{ PseudoVDIV_VV_M2_E16_MASK, VDIV_VV, 0x1, 0x10 }, // 1071
|
|
{ PseudoVDIV_VV_M2_E32, VDIV_VV, 0x1, 0x20 }, // 1072
|
|
{ PseudoVDIV_VV_M2_E32_MASK, VDIV_VV, 0x1, 0x20 }, // 1073
|
|
{ PseudoVDIV_VV_M2_E64, VDIV_VV, 0x1, 0x40 }, // 1074
|
|
{ PseudoVDIV_VV_M2_E64_MASK, VDIV_VV, 0x1, 0x40 }, // 1075
|
|
{ PseudoVDIV_VV_M4_E8, VDIV_VV, 0x2, 0x8 }, // 1076
|
|
{ PseudoVDIV_VV_M4_E8_MASK, VDIV_VV, 0x2, 0x8 }, // 1077
|
|
{ PseudoVDIV_VV_M4_E16, VDIV_VV, 0x2, 0x10 }, // 1078
|
|
{ PseudoVDIV_VV_M4_E16_MASK, VDIV_VV, 0x2, 0x10 }, // 1079
|
|
{ PseudoVDIV_VV_M4_E32, VDIV_VV, 0x2, 0x20 }, // 1080
|
|
{ PseudoVDIV_VV_M4_E32_MASK, VDIV_VV, 0x2, 0x20 }, // 1081
|
|
{ PseudoVDIV_VV_M4_E64, VDIV_VV, 0x2, 0x40 }, // 1082
|
|
{ PseudoVDIV_VV_M4_E64_MASK, VDIV_VV, 0x2, 0x40 }, // 1083
|
|
{ PseudoVDIV_VV_M8_E8, VDIV_VV, 0x3, 0x8 }, // 1084
|
|
{ PseudoVDIV_VV_M8_E8_MASK, VDIV_VV, 0x3, 0x8 }, // 1085
|
|
{ PseudoVDIV_VV_M8_E16, VDIV_VV, 0x3, 0x10 }, // 1086
|
|
{ PseudoVDIV_VV_M8_E16_MASK, VDIV_VV, 0x3, 0x10 }, // 1087
|
|
{ PseudoVDIV_VV_M8_E32, VDIV_VV, 0x3, 0x20 }, // 1088
|
|
{ PseudoVDIV_VV_M8_E32_MASK, VDIV_VV, 0x3, 0x20 }, // 1089
|
|
{ PseudoVDIV_VV_M8_E64, VDIV_VV, 0x3, 0x40 }, // 1090
|
|
{ PseudoVDIV_VV_M8_E64_MASK, VDIV_VV, 0x3, 0x40 }, // 1091
|
|
{ PseudoVDIV_VV_MF8_E8, VDIV_VV, 0x5, 0x8 }, // 1092
|
|
{ PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV, 0x5, 0x8 }, // 1093
|
|
{ PseudoVDIV_VV_MF4_E8, VDIV_VV, 0x6, 0x8 }, // 1094
|
|
{ PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV, 0x6, 0x8 }, // 1095
|
|
{ PseudoVDIV_VV_MF4_E16, VDIV_VV, 0x6, 0x10 }, // 1096
|
|
{ PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV, 0x6, 0x10 }, // 1097
|
|
{ PseudoVDIV_VV_MF2_E8, VDIV_VV, 0x7, 0x8 }, // 1098
|
|
{ PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV, 0x7, 0x8 }, // 1099
|
|
{ PseudoVDIV_VV_MF2_E16, VDIV_VV, 0x7, 0x10 }, // 1100
|
|
{ PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV, 0x7, 0x10 }, // 1101
|
|
{ PseudoVDIV_VV_MF2_E32, VDIV_VV, 0x7, 0x20 }, // 1102
|
|
{ PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV, 0x7, 0x20 }, // 1103
|
|
{ PseudoVDIV_VX_M1_E8, VDIV_VX, 0x0, 0x8 }, // 1104
|
|
{ PseudoVDIV_VX_M1_E8_MASK, VDIV_VX, 0x0, 0x8 }, // 1105
|
|
{ PseudoVDIV_VX_M1_E16, VDIV_VX, 0x0, 0x10 }, // 1106
|
|
{ PseudoVDIV_VX_M1_E16_MASK, VDIV_VX, 0x0, 0x10 }, // 1107
|
|
{ PseudoVDIV_VX_M1_E32, VDIV_VX, 0x0, 0x20 }, // 1108
|
|
{ PseudoVDIV_VX_M1_E32_MASK, VDIV_VX, 0x0, 0x20 }, // 1109
|
|
{ PseudoVDIV_VX_M1_E64, VDIV_VX, 0x0, 0x40 }, // 1110
|
|
{ PseudoVDIV_VX_M1_E64_MASK, VDIV_VX, 0x0, 0x40 }, // 1111
|
|
{ PseudoVDIV_VX_M2_E8, VDIV_VX, 0x1, 0x8 }, // 1112
|
|
{ PseudoVDIV_VX_M2_E8_MASK, VDIV_VX, 0x1, 0x8 }, // 1113
|
|
{ PseudoVDIV_VX_M2_E16, VDIV_VX, 0x1, 0x10 }, // 1114
|
|
{ PseudoVDIV_VX_M2_E16_MASK, VDIV_VX, 0x1, 0x10 }, // 1115
|
|
{ PseudoVDIV_VX_M2_E32, VDIV_VX, 0x1, 0x20 }, // 1116
|
|
{ PseudoVDIV_VX_M2_E32_MASK, VDIV_VX, 0x1, 0x20 }, // 1117
|
|
{ PseudoVDIV_VX_M2_E64, VDIV_VX, 0x1, 0x40 }, // 1118
|
|
{ PseudoVDIV_VX_M2_E64_MASK, VDIV_VX, 0x1, 0x40 }, // 1119
|
|
{ PseudoVDIV_VX_M4_E8, VDIV_VX, 0x2, 0x8 }, // 1120
|
|
{ PseudoVDIV_VX_M4_E8_MASK, VDIV_VX, 0x2, 0x8 }, // 1121
|
|
{ PseudoVDIV_VX_M4_E16, VDIV_VX, 0x2, 0x10 }, // 1122
|
|
{ PseudoVDIV_VX_M4_E16_MASK, VDIV_VX, 0x2, 0x10 }, // 1123
|
|
{ PseudoVDIV_VX_M4_E32, VDIV_VX, 0x2, 0x20 }, // 1124
|
|
{ PseudoVDIV_VX_M4_E32_MASK, VDIV_VX, 0x2, 0x20 }, // 1125
|
|
{ PseudoVDIV_VX_M4_E64, VDIV_VX, 0x2, 0x40 }, // 1126
|
|
{ PseudoVDIV_VX_M4_E64_MASK, VDIV_VX, 0x2, 0x40 }, // 1127
|
|
{ PseudoVDIV_VX_M8_E8, VDIV_VX, 0x3, 0x8 }, // 1128
|
|
{ PseudoVDIV_VX_M8_E8_MASK, VDIV_VX, 0x3, 0x8 }, // 1129
|
|
{ PseudoVDIV_VX_M8_E16, VDIV_VX, 0x3, 0x10 }, // 1130
|
|
{ PseudoVDIV_VX_M8_E16_MASK, VDIV_VX, 0x3, 0x10 }, // 1131
|
|
{ PseudoVDIV_VX_M8_E32, VDIV_VX, 0x3, 0x20 }, // 1132
|
|
{ PseudoVDIV_VX_M8_E32_MASK, VDIV_VX, 0x3, 0x20 }, // 1133
|
|
{ PseudoVDIV_VX_M8_E64, VDIV_VX, 0x3, 0x40 }, // 1134
|
|
{ PseudoVDIV_VX_M8_E64_MASK, VDIV_VX, 0x3, 0x40 }, // 1135
|
|
{ PseudoVDIV_VX_MF8_E8, VDIV_VX, 0x5, 0x8 }, // 1136
|
|
{ PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX, 0x5, 0x8 }, // 1137
|
|
{ PseudoVDIV_VX_MF4_E8, VDIV_VX, 0x6, 0x8 }, // 1138
|
|
{ PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX, 0x6, 0x8 }, // 1139
|
|
{ PseudoVDIV_VX_MF4_E16, VDIV_VX, 0x6, 0x10 }, // 1140
|
|
{ PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX, 0x6, 0x10 }, // 1141
|
|
{ PseudoVDIV_VX_MF2_E8, VDIV_VX, 0x7, 0x8 }, // 1142
|
|
{ PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX, 0x7, 0x8 }, // 1143
|
|
{ PseudoVDIV_VX_MF2_E16, VDIV_VX, 0x7, 0x10 }, // 1144
|
|
{ PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX, 0x7, 0x10 }, // 1145
|
|
{ PseudoVDIV_VX_MF2_E32, VDIV_VX, 0x7, 0x20 }, // 1146
|
|
{ PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX, 0x7, 0x20 }, // 1147
|
|
{ PseudoVFADD_VFPR16_M1, VFADD_VF, 0x0, 0x0 }, // 1148
|
|
{ PseudoVFADD_VFPR16_M1_MASK, VFADD_VF, 0x0, 0x0 }, // 1149
|
|
{ PseudoVFADD_VFPR32_M1, VFADD_VF, 0x0, 0x0 }, // 1150
|
|
{ PseudoVFADD_VFPR32_M1_MASK, VFADD_VF, 0x0, 0x0 }, // 1151
|
|
{ PseudoVFADD_VFPR64_M1, VFADD_VF, 0x0, 0x0 }, // 1152
|
|
{ PseudoVFADD_VFPR64_M1_MASK, VFADD_VF, 0x0, 0x0 }, // 1153
|
|
{ PseudoVFADD_VFPR16_M2, VFADD_VF, 0x1, 0x0 }, // 1154
|
|
{ PseudoVFADD_VFPR16_M2_MASK, VFADD_VF, 0x1, 0x0 }, // 1155
|
|
{ PseudoVFADD_VFPR32_M2, VFADD_VF, 0x1, 0x0 }, // 1156
|
|
{ PseudoVFADD_VFPR32_M2_MASK, VFADD_VF, 0x1, 0x0 }, // 1157
|
|
{ PseudoVFADD_VFPR64_M2, VFADD_VF, 0x1, 0x0 }, // 1158
|
|
{ PseudoVFADD_VFPR64_M2_MASK, VFADD_VF, 0x1, 0x0 }, // 1159
|
|
{ PseudoVFADD_VFPR16_M4, VFADD_VF, 0x2, 0x0 }, // 1160
|
|
{ PseudoVFADD_VFPR16_M4_MASK, VFADD_VF, 0x2, 0x0 }, // 1161
|
|
{ PseudoVFADD_VFPR32_M4, VFADD_VF, 0x2, 0x0 }, // 1162
|
|
{ PseudoVFADD_VFPR32_M4_MASK, VFADD_VF, 0x2, 0x0 }, // 1163
|
|
{ PseudoVFADD_VFPR64_M4, VFADD_VF, 0x2, 0x0 }, // 1164
|
|
{ PseudoVFADD_VFPR64_M4_MASK, VFADD_VF, 0x2, 0x0 }, // 1165
|
|
{ PseudoVFADD_VFPR16_M8, VFADD_VF, 0x3, 0x0 }, // 1166
|
|
{ PseudoVFADD_VFPR16_M8_MASK, VFADD_VF, 0x3, 0x0 }, // 1167
|
|
{ PseudoVFADD_VFPR32_M8, VFADD_VF, 0x3, 0x0 }, // 1168
|
|
{ PseudoVFADD_VFPR32_M8_MASK, VFADD_VF, 0x3, 0x0 }, // 1169
|
|
{ PseudoVFADD_VFPR64_M8, VFADD_VF, 0x3, 0x0 }, // 1170
|
|
{ PseudoVFADD_VFPR64_M8_MASK, VFADD_VF, 0x3, 0x0 }, // 1171
|
|
{ PseudoVFADD_VFPR16_MF4, VFADD_VF, 0x6, 0x0 }, // 1172
|
|
{ PseudoVFADD_VFPR16_MF4_MASK, VFADD_VF, 0x6, 0x0 }, // 1173
|
|
{ PseudoVFADD_VFPR16_MF2, VFADD_VF, 0x7, 0x0 }, // 1174
|
|
{ PseudoVFADD_VFPR16_MF2_MASK, VFADD_VF, 0x7, 0x0 }, // 1175
|
|
{ PseudoVFADD_VFPR32_MF2, VFADD_VF, 0x7, 0x0 }, // 1176
|
|
{ PseudoVFADD_VFPR32_MF2_MASK, VFADD_VF, 0x7, 0x0 }, // 1177
|
|
{ PseudoVFADD_VV_M1, VFADD_VV, 0x0, 0x0 }, // 1178
|
|
{ PseudoVFADD_VV_M1_MASK, VFADD_VV, 0x0, 0x0 }, // 1179
|
|
{ PseudoVFADD_VV_M2, VFADD_VV, 0x1, 0x0 }, // 1180
|
|
{ PseudoVFADD_VV_M2_MASK, VFADD_VV, 0x1, 0x0 }, // 1181
|
|
{ PseudoVFADD_VV_M4, VFADD_VV, 0x2, 0x0 }, // 1182
|
|
{ PseudoVFADD_VV_M4_MASK, VFADD_VV, 0x2, 0x0 }, // 1183
|
|
{ PseudoVFADD_VV_M8, VFADD_VV, 0x3, 0x0 }, // 1184
|
|
{ PseudoVFADD_VV_M8_MASK, VFADD_VV, 0x3, 0x0 }, // 1185
|
|
{ PseudoVFADD_VV_MF4, VFADD_VV, 0x6, 0x0 }, // 1186
|
|
{ PseudoVFADD_VV_MF4_MASK, VFADD_VV, 0x6, 0x0 }, // 1187
|
|
{ PseudoVFADD_VV_MF2, VFADD_VV, 0x7, 0x0 }, // 1188
|
|
{ PseudoVFADD_VV_MF2_MASK, VFADD_VV, 0x7, 0x0 }, // 1189
|
|
{ PseudoVFCLASS_V_M1, VFCLASS_V, 0x0, 0x0 }, // 1190
|
|
{ PseudoVFCLASS_V_M1_MASK, VFCLASS_V, 0x0, 0x0 }, // 1191
|
|
{ PseudoVFCLASS_V_M2, VFCLASS_V, 0x1, 0x0 }, // 1192
|
|
{ PseudoVFCLASS_V_M2_MASK, VFCLASS_V, 0x1, 0x0 }, // 1193
|
|
{ PseudoVFCLASS_V_M4, VFCLASS_V, 0x2, 0x0 }, // 1194
|
|
{ PseudoVFCLASS_V_M4_MASK, VFCLASS_V, 0x2, 0x0 }, // 1195
|
|
{ PseudoVFCLASS_V_M8, VFCLASS_V, 0x3, 0x0 }, // 1196
|
|
{ PseudoVFCLASS_V_M8_MASK, VFCLASS_V, 0x3, 0x0 }, // 1197
|
|
{ PseudoVFCLASS_V_MF4, VFCLASS_V, 0x6, 0x0 }, // 1198
|
|
{ PseudoVFCLASS_V_MF4_MASK, VFCLASS_V, 0x6, 0x0 }, // 1199
|
|
{ PseudoVFCLASS_V_MF2, VFCLASS_V, 0x7, 0x0 }, // 1200
|
|
{ PseudoVFCLASS_V_MF2_MASK, VFCLASS_V, 0x7, 0x0 }, // 1201
|
|
{ PseudoVFCVT_F_XU_V_M1, VFCVT_F_XU_V, 0x0, 0x0 }, // 1202
|
|
{ PseudoVFCVT_F_XU_V_M1_MASK, VFCVT_F_XU_V, 0x0, 0x0 }, // 1203
|
|
{ PseudoVFCVT_RM_F_XU_V_M1, VFCVT_F_XU_V, 0x0, 0x0 }, // 1204
|
|
{ PseudoVFCVT_RM_F_XU_V_M1_MASK, VFCVT_F_XU_V, 0x0, 0x0 }, // 1205
|
|
{ PseudoVFCVT_F_XU_V_M2, VFCVT_F_XU_V, 0x1, 0x0 }, // 1206
|
|
{ PseudoVFCVT_F_XU_V_M2_MASK, VFCVT_F_XU_V, 0x1, 0x0 }, // 1207
|
|
{ PseudoVFCVT_RM_F_XU_V_M2, VFCVT_F_XU_V, 0x1, 0x0 }, // 1208
|
|
{ PseudoVFCVT_RM_F_XU_V_M2_MASK, VFCVT_F_XU_V, 0x1, 0x0 }, // 1209
|
|
{ PseudoVFCVT_F_XU_V_M4, VFCVT_F_XU_V, 0x2, 0x0 }, // 1210
|
|
{ PseudoVFCVT_F_XU_V_M4_MASK, VFCVT_F_XU_V, 0x2, 0x0 }, // 1211
|
|
{ PseudoVFCVT_RM_F_XU_V_M4, VFCVT_F_XU_V, 0x2, 0x0 }, // 1212
|
|
{ PseudoVFCVT_RM_F_XU_V_M4_MASK, VFCVT_F_XU_V, 0x2, 0x0 }, // 1213
|
|
{ PseudoVFCVT_F_XU_V_M8, VFCVT_F_XU_V, 0x3, 0x0 }, // 1214
|
|
{ PseudoVFCVT_F_XU_V_M8_MASK, VFCVT_F_XU_V, 0x3, 0x0 }, // 1215
|
|
{ PseudoVFCVT_RM_F_XU_V_M8, VFCVT_F_XU_V, 0x3, 0x0 }, // 1216
|
|
{ PseudoVFCVT_RM_F_XU_V_M8_MASK, VFCVT_F_XU_V, 0x3, 0x0 }, // 1217
|
|
{ PseudoVFCVT_F_XU_V_MF4, VFCVT_F_XU_V, 0x6, 0x0 }, // 1218
|
|
{ PseudoVFCVT_F_XU_V_MF4_MASK, VFCVT_F_XU_V, 0x6, 0x0 }, // 1219
|
|
{ PseudoVFCVT_RM_F_XU_V_MF4, VFCVT_F_XU_V, 0x6, 0x0 }, // 1220
|
|
{ PseudoVFCVT_RM_F_XU_V_MF4_MASK, VFCVT_F_XU_V, 0x6, 0x0 }, // 1221
|
|
{ PseudoVFCVT_F_XU_V_MF2, VFCVT_F_XU_V, 0x7, 0x0 }, // 1222
|
|
{ PseudoVFCVT_F_XU_V_MF2_MASK, VFCVT_F_XU_V, 0x7, 0x0 }, // 1223
|
|
{ PseudoVFCVT_RM_F_XU_V_MF2, VFCVT_F_XU_V, 0x7, 0x0 }, // 1224
|
|
{ PseudoVFCVT_RM_F_XU_V_MF2_MASK, VFCVT_F_XU_V, 0x7, 0x0 }, // 1225
|
|
{ PseudoVFCVT_F_X_V_M1, VFCVT_F_X_V, 0x0, 0x0 }, // 1226
|
|
{ PseudoVFCVT_F_X_V_M1_MASK, VFCVT_F_X_V, 0x0, 0x0 }, // 1227
|
|
{ PseudoVFCVT_RM_F_X_V_M1, VFCVT_F_X_V, 0x0, 0x0 }, // 1228
|
|
{ PseudoVFCVT_RM_F_X_V_M1_MASK, VFCVT_F_X_V, 0x0, 0x0 }, // 1229
|
|
{ PseudoVFCVT_F_X_V_M2, VFCVT_F_X_V, 0x1, 0x0 }, // 1230
|
|
{ PseudoVFCVT_F_X_V_M2_MASK, VFCVT_F_X_V, 0x1, 0x0 }, // 1231
|
|
{ PseudoVFCVT_RM_F_X_V_M2, VFCVT_F_X_V, 0x1, 0x0 }, // 1232
|
|
{ PseudoVFCVT_RM_F_X_V_M2_MASK, VFCVT_F_X_V, 0x1, 0x0 }, // 1233
|
|
{ PseudoVFCVT_F_X_V_M4, VFCVT_F_X_V, 0x2, 0x0 }, // 1234
|
|
{ PseudoVFCVT_F_X_V_M4_MASK, VFCVT_F_X_V, 0x2, 0x0 }, // 1235
|
|
{ PseudoVFCVT_RM_F_X_V_M4, VFCVT_F_X_V, 0x2, 0x0 }, // 1236
|
|
{ PseudoVFCVT_RM_F_X_V_M4_MASK, VFCVT_F_X_V, 0x2, 0x0 }, // 1237
|
|
{ PseudoVFCVT_F_X_V_M8, VFCVT_F_X_V, 0x3, 0x0 }, // 1238
|
|
{ PseudoVFCVT_F_X_V_M8_MASK, VFCVT_F_X_V, 0x3, 0x0 }, // 1239
|
|
{ PseudoVFCVT_RM_F_X_V_M8, VFCVT_F_X_V, 0x3, 0x0 }, // 1240
|
|
{ PseudoVFCVT_RM_F_X_V_M8_MASK, VFCVT_F_X_V, 0x3, 0x0 }, // 1241
|
|
{ PseudoVFCVT_F_X_V_MF4, VFCVT_F_X_V, 0x6, 0x0 }, // 1242
|
|
{ PseudoVFCVT_F_X_V_MF4_MASK, VFCVT_F_X_V, 0x6, 0x0 }, // 1243
|
|
{ PseudoVFCVT_RM_F_X_V_MF4, VFCVT_F_X_V, 0x6, 0x0 }, // 1244
|
|
{ PseudoVFCVT_RM_F_X_V_MF4_MASK, VFCVT_F_X_V, 0x6, 0x0 }, // 1245
|
|
{ PseudoVFCVT_F_X_V_MF2, VFCVT_F_X_V, 0x7, 0x0 }, // 1246
|
|
{ PseudoVFCVT_F_X_V_MF2_MASK, VFCVT_F_X_V, 0x7, 0x0 }, // 1247
|
|
{ PseudoVFCVT_RM_F_X_V_MF2, VFCVT_F_X_V, 0x7, 0x0 }, // 1248
|
|
{ PseudoVFCVT_RM_F_X_V_MF2_MASK, VFCVT_F_X_V, 0x7, 0x0 }, // 1249
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1250
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1251
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1252
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1253
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1254
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1255
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1256
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1257
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1258
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1259
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1260
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1261
|
|
{ PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1262
|
|
{ PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1263
|
|
{ PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1264
|
|
{ PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1265
|
|
{ PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1266
|
|
{ PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1267
|
|
{ PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1268
|
|
{ PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1269
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1270
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1271
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1272
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1273
|
|
{ PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1274
|
|
{ PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1275
|
|
{ PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1276
|
|
{ PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1277
|
|
{ PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1278
|
|
{ PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1279
|
|
{ PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1280
|
|
{ PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1281
|
|
{ PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1282
|
|
{ PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1283
|
|
{ PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1284
|
|
{ PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1285
|
|
{ PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1286
|
|
{ PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1287
|
|
{ PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1288
|
|
{ PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1289
|
|
{ PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1290
|
|
{ PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1291
|
|
{ PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1292
|
|
{ PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1293
|
|
{ PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1294
|
|
{ PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1295
|
|
{ PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1296
|
|
{ PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1297
|
|
{ PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1298
|
|
{ PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1299
|
|
{ PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1300
|
|
{ PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1301
|
|
{ PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1302
|
|
{ PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1303
|
|
{ PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1304
|
|
{ PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1305
|
|
{ PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1306
|
|
{ PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1307
|
|
{ PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1308
|
|
{ PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1309
|
|
{ PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1310
|
|
{ PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1311
|
|
{ PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1312
|
|
{ PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1313
|
|
{ PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1314
|
|
{ PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1315
|
|
{ PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1316
|
|
{ PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1317
|
|
{ PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1318
|
|
{ PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1319
|
|
{ PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1320
|
|
{ PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1321
|
|
{ PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF, 0x0, 0x10 }, // 1322
|
|
{ PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF, 0x0, 0x10 }, // 1323
|
|
{ PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF, 0x0, 0x20 }, // 1324
|
|
{ PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF, 0x0, 0x20 }, // 1325
|
|
{ PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF, 0x0, 0x40 }, // 1326
|
|
{ PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF, 0x0, 0x40 }, // 1327
|
|
{ PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF, 0x1, 0x10 }, // 1328
|
|
{ PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF, 0x1, 0x10 }, // 1329
|
|
{ PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF, 0x1, 0x20 }, // 1330
|
|
{ PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF, 0x1, 0x20 }, // 1331
|
|
{ PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF, 0x1, 0x40 }, // 1332
|
|
{ PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF, 0x1, 0x40 }, // 1333
|
|
{ PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF, 0x2, 0x10 }, // 1334
|
|
{ PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF, 0x2, 0x10 }, // 1335
|
|
{ PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF, 0x2, 0x20 }, // 1336
|
|
{ PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF, 0x2, 0x20 }, // 1337
|
|
{ PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF, 0x2, 0x40 }, // 1338
|
|
{ PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF, 0x2, 0x40 }, // 1339
|
|
{ PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF, 0x3, 0x10 }, // 1340
|
|
{ PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF, 0x3, 0x10 }, // 1341
|
|
{ PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF, 0x3, 0x20 }, // 1342
|
|
{ PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF, 0x3, 0x20 }, // 1343
|
|
{ PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF, 0x3, 0x40 }, // 1344
|
|
{ PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF, 0x3, 0x40 }, // 1345
|
|
{ PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF, 0x6, 0x10 }, // 1346
|
|
{ PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF, 0x6, 0x10 }, // 1347
|
|
{ PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF, 0x7, 0x10 }, // 1348
|
|
{ PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF, 0x7, 0x10 }, // 1349
|
|
{ PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF, 0x7, 0x20 }, // 1350
|
|
{ PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF, 0x7, 0x20 }, // 1351
|
|
{ PseudoVFDIV_VV_M1_E16, VFDIV_VV, 0x0, 0x10 }, // 1352
|
|
{ PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV, 0x0, 0x10 }, // 1353
|
|
{ PseudoVFDIV_VV_M1_E32, VFDIV_VV, 0x0, 0x20 }, // 1354
|
|
{ PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV, 0x0, 0x20 }, // 1355
|
|
{ PseudoVFDIV_VV_M1_E64, VFDIV_VV, 0x0, 0x40 }, // 1356
|
|
{ PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV, 0x0, 0x40 }, // 1357
|
|
{ PseudoVFDIV_VV_M2_E16, VFDIV_VV, 0x1, 0x10 }, // 1358
|
|
{ PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV, 0x1, 0x10 }, // 1359
|
|
{ PseudoVFDIV_VV_M2_E32, VFDIV_VV, 0x1, 0x20 }, // 1360
|
|
{ PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV, 0x1, 0x20 }, // 1361
|
|
{ PseudoVFDIV_VV_M2_E64, VFDIV_VV, 0x1, 0x40 }, // 1362
|
|
{ PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV, 0x1, 0x40 }, // 1363
|
|
{ PseudoVFDIV_VV_M4_E16, VFDIV_VV, 0x2, 0x10 }, // 1364
|
|
{ PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV, 0x2, 0x10 }, // 1365
|
|
{ PseudoVFDIV_VV_M4_E32, VFDIV_VV, 0x2, 0x20 }, // 1366
|
|
{ PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV, 0x2, 0x20 }, // 1367
|
|
{ PseudoVFDIV_VV_M4_E64, VFDIV_VV, 0x2, 0x40 }, // 1368
|
|
{ PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV, 0x2, 0x40 }, // 1369
|
|
{ PseudoVFDIV_VV_M8_E16, VFDIV_VV, 0x3, 0x10 }, // 1370
|
|
{ PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV, 0x3, 0x10 }, // 1371
|
|
{ PseudoVFDIV_VV_M8_E32, VFDIV_VV, 0x3, 0x20 }, // 1372
|
|
{ PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV, 0x3, 0x20 }, // 1373
|
|
{ PseudoVFDIV_VV_M8_E64, VFDIV_VV, 0x3, 0x40 }, // 1374
|
|
{ PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV, 0x3, 0x40 }, // 1375
|
|
{ PseudoVFDIV_VV_MF4_E16, VFDIV_VV, 0x6, 0x10 }, // 1376
|
|
{ PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV, 0x6, 0x10 }, // 1377
|
|
{ PseudoVFDIV_VV_MF2_E16, VFDIV_VV, 0x7, 0x10 }, // 1378
|
|
{ PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV, 0x7, 0x10 }, // 1379
|
|
{ PseudoVFDIV_VV_MF2_E32, VFDIV_VV, 0x7, 0x20 }, // 1380
|
|
{ PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV, 0x7, 0x20 }, // 1381
|
|
{ PseudoVFIRST_M_B8, VFIRST_M, 0x0, 0x0 }, // 1382
|
|
{ PseudoVFIRST_M_B8_MASK, VFIRST_M, 0x0, 0x0 }, // 1383
|
|
{ PseudoVFIRST_M_B16, VFIRST_M, 0x1, 0x0 }, // 1384
|
|
{ PseudoVFIRST_M_B16_MASK, VFIRST_M, 0x1, 0x0 }, // 1385
|
|
{ PseudoVFIRST_M_B32, VFIRST_M, 0x2, 0x0 }, // 1386
|
|
{ PseudoVFIRST_M_B32_MASK, VFIRST_M, 0x2, 0x0 }, // 1387
|
|
{ PseudoVFIRST_M_B64, VFIRST_M, 0x3, 0x0 }, // 1388
|
|
{ PseudoVFIRST_M_B64_MASK, VFIRST_M, 0x3, 0x0 }, // 1389
|
|
{ PseudoVFIRST_M_B1, VFIRST_M, 0x5, 0x0 }, // 1390
|
|
{ PseudoVFIRST_M_B1_MASK, VFIRST_M, 0x5, 0x0 }, // 1391
|
|
{ PseudoVFIRST_M_B2, VFIRST_M, 0x6, 0x0 }, // 1392
|
|
{ PseudoVFIRST_M_B2_MASK, VFIRST_M, 0x6, 0x0 }, // 1393
|
|
{ PseudoVFIRST_M_B4, VFIRST_M, 0x7, 0x0 }, // 1394
|
|
{ PseudoVFIRST_M_B4_MASK, VFIRST_M, 0x7, 0x0 }, // 1395
|
|
{ PseudoVFMACC_VFPR16_M1, VFMACC_VF, 0x0, 0x0 }, // 1396
|
|
{ PseudoVFMACC_VFPR16_M1_MASK, VFMACC_VF, 0x0, 0x0 }, // 1397
|
|
{ PseudoVFMACC_VFPR32_M1, VFMACC_VF, 0x0, 0x0 }, // 1398
|
|
{ PseudoVFMACC_VFPR32_M1_MASK, VFMACC_VF, 0x0, 0x0 }, // 1399
|
|
{ PseudoVFMACC_VFPR64_M1, VFMACC_VF, 0x0, 0x0 }, // 1400
|
|
{ PseudoVFMACC_VFPR64_M1_MASK, VFMACC_VF, 0x0, 0x0 }, // 1401
|
|
{ PseudoVFMACC_VFPR16_M2, VFMACC_VF, 0x1, 0x0 }, // 1402
|
|
{ PseudoVFMACC_VFPR16_M2_MASK, VFMACC_VF, 0x1, 0x0 }, // 1403
|
|
{ PseudoVFMACC_VFPR32_M2, VFMACC_VF, 0x1, 0x0 }, // 1404
|
|
{ PseudoVFMACC_VFPR32_M2_MASK, VFMACC_VF, 0x1, 0x0 }, // 1405
|
|
{ PseudoVFMACC_VFPR64_M2, VFMACC_VF, 0x1, 0x0 }, // 1406
|
|
{ PseudoVFMACC_VFPR64_M2_MASK, VFMACC_VF, 0x1, 0x0 }, // 1407
|
|
{ PseudoVFMACC_VFPR16_M4, VFMACC_VF, 0x2, 0x0 }, // 1408
|
|
{ PseudoVFMACC_VFPR16_M4_MASK, VFMACC_VF, 0x2, 0x0 }, // 1409
|
|
{ PseudoVFMACC_VFPR32_M4, VFMACC_VF, 0x2, 0x0 }, // 1410
|
|
{ PseudoVFMACC_VFPR32_M4_MASK, VFMACC_VF, 0x2, 0x0 }, // 1411
|
|
{ PseudoVFMACC_VFPR64_M4, VFMACC_VF, 0x2, 0x0 }, // 1412
|
|
{ PseudoVFMACC_VFPR64_M4_MASK, VFMACC_VF, 0x2, 0x0 }, // 1413
|
|
{ PseudoVFMACC_VFPR16_M8, VFMACC_VF, 0x3, 0x0 }, // 1414
|
|
{ PseudoVFMACC_VFPR16_M8_MASK, VFMACC_VF, 0x3, 0x0 }, // 1415
|
|
{ PseudoVFMACC_VFPR32_M8, VFMACC_VF, 0x3, 0x0 }, // 1416
|
|
{ PseudoVFMACC_VFPR32_M8_MASK, VFMACC_VF, 0x3, 0x0 }, // 1417
|
|
{ PseudoVFMACC_VFPR64_M8, VFMACC_VF, 0x3, 0x0 }, // 1418
|
|
{ PseudoVFMACC_VFPR64_M8_MASK, VFMACC_VF, 0x3, 0x0 }, // 1419
|
|
{ PseudoVFMACC_VFPR16_MF4, VFMACC_VF, 0x6, 0x0 }, // 1420
|
|
{ PseudoVFMACC_VFPR16_MF4_MASK, VFMACC_VF, 0x6, 0x0 }, // 1421
|
|
{ PseudoVFMACC_VFPR16_MF2, VFMACC_VF, 0x7, 0x0 }, // 1422
|
|
{ PseudoVFMACC_VFPR16_MF2_MASK, VFMACC_VF, 0x7, 0x0 }, // 1423
|
|
{ PseudoVFMACC_VFPR32_MF2, VFMACC_VF, 0x7, 0x0 }, // 1424
|
|
{ PseudoVFMACC_VFPR32_MF2_MASK, VFMACC_VF, 0x7, 0x0 }, // 1425
|
|
{ PseudoVFMACC_VV_M1, VFMACC_VV, 0x0, 0x0 }, // 1426
|
|
{ PseudoVFMACC_VV_M1_MASK, VFMACC_VV, 0x0, 0x0 }, // 1427
|
|
{ PseudoVFMACC_VV_M2, VFMACC_VV, 0x1, 0x0 }, // 1428
|
|
{ PseudoVFMACC_VV_M2_MASK, VFMACC_VV, 0x1, 0x0 }, // 1429
|
|
{ PseudoVFMACC_VV_M4, VFMACC_VV, 0x2, 0x0 }, // 1430
|
|
{ PseudoVFMACC_VV_M4_MASK, VFMACC_VV, 0x2, 0x0 }, // 1431
|
|
{ PseudoVFMACC_VV_M8, VFMACC_VV, 0x3, 0x0 }, // 1432
|
|
{ PseudoVFMACC_VV_M8_MASK, VFMACC_VV, 0x3, 0x0 }, // 1433
|
|
{ PseudoVFMACC_VV_MF4, VFMACC_VV, 0x6, 0x0 }, // 1434
|
|
{ PseudoVFMACC_VV_MF4_MASK, VFMACC_VV, 0x6, 0x0 }, // 1435
|
|
{ PseudoVFMACC_VV_MF2, VFMACC_VV, 0x7, 0x0 }, // 1436
|
|
{ PseudoVFMACC_VV_MF2_MASK, VFMACC_VV, 0x7, 0x0 }, // 1437
|
|
{ PseudoVFMADD_VFPR16_M1, VFMADD_VF, 0x0, 0x0 }, // 1438
|
|
{ PseudoVFMADD_VFPR16_M1_MASK, VFMADD_VF, 0x0, 0x0 }, // 1439
|
|
{ PseudoVFMADD_VFPR32_M1, VFMADD_VF, 0x0, 0x0 }, // 1440
|
|
{ PseudoVFMADD_VFPR32_M1_MASK, VFMADD_VF, 0x0, 0x0 }, // 1441
|
|
{ PseudoVFMADD_VFPR64_M1, VFMADD_VF, 0x0, 0x0 }, // 1442
|
|
{ PseudoVFMADD_VFPR64_M1_MASK, VFMADD_VF, 0x0, 0x0 }, // 1443
|
|
{ PseudoVFMADD_VFPR16_M2, VFMADD_VF, 0x1, 0x0 }, // 1444
|
|
{ PseudoVFMADD_VFPR16_M2_MASK, VFMADD_VF, 0x1, 0x0 }, // 1445
|
|
{ PseudoVFMADD_VFPR32_M2, VFMADD_VF, 0x1, 0x0 }, // 1446
|
|
{ PseudoVFMADD_VFPR32_M2_MASK, VFMADD_VF, 0x1, 0x0 }, // 1447
|
|
{ PseudoVFMADD_VFPR64_M2, VFMADD_VF, 0x1, 0x0 }, // 1448
|
|
{ PseudoVFMADD_VFPR64_M2_MASK, VFMADD_VF, 0x1, 0x0 }, // 1449
|
|
{ PseudoVFMADD_VFPR16_M4, VFMADD_VF, 0x2, 0x0 }, // 1450
|
|
{ PseudoVFMADD_VFPR16_M4_MASK, VFMADD_VF, 0x2, 0x0 }, // 1451
|
|
{ PseudoVFMADD_VFPR32_M4, VFMADD_VF, 0x2, 0x0 }, // 1452
|
|
{ PseudoVFMADD_VFPR32_M4_MASK, VFMADD_VF, 0x2, 0x0 }, // 1453
|
|
{ PseudoVFMADD_VFPR64_M4, VFMADD_VF, 0x2, 0x0 }, // 1454
|
|
{ PseudoVFMADD_VFPR64_M4_MASK, VFMADD_VF, 0x2, 0x0 }, // 1455
|
|
{ PseudoVFMADD_VFPR16_M8, VFMADD_VF, 0x3, 0x0 }, // 1456
|
|
{ PseudoVFMADD_VFPR16_M8_MASK, VFMADD_VF, 0x3, 0x0 }, // 1457
|
|
{ PseudoVFMADD_VFPR32_M8, VFMADD_VF, 0x3, 0x0 }, // 1458
|
|
{ PseudoVFMADD_VFPR32_M8_MASK, VFMADD_VF, 0x3, 0x0 }, // 1459
|
|
{ PseudoVFMADD_VFPR64_M8, VFMADD_VF, 0x3, 0x0 }, // 1460
|
|
{ PseudoVFMADD_VFPR64_M8_MASK, VFMADD_VF, 0x3, 0x0 }, // 1461
|
|
{ PseudoVFMADD_VFPR16_MF4, VFMADD_VF, 0x6, 0x0 }, // 1462
|
|
{ PseudoVFMADD_VFPR16_MF4_MASK, VFMADD_VF, 0x6, 0x0 }, // 1463
|
|
{ PseudoVFMADD_VFPR16_MF2, VFMADD_VF, 0x7, 0x0 }, // 1464
|
|
{ PseudoVFMADD_VFPR16_MF2_MASK, VFMADD_VF, 0x7, 0x0 }, // 1465
|
|
{ PseudoVFMADD_VFPR32_MF2, VFMADD_VF, 0x7, 0x0 }, // 1466
|
|
{ PseudoVFMADD_VFPR32_MF2_MASK, VFMADD_VF, 0x7, 0x0 }, // 1467
|
|
{ PseudoVFMADD_VV_M1, VFMADD_VV, 0x0, 0x0 }, // 1468
|
|
{ PseudoVFMADD_VV_M1_MASK, VFMADD_VV, 0x0, 0x0 }, // 1469
|
|
{ PseudoVFMADD_VV_M2, VFMADD_VV, 0x1, 0x0 }, // 1470
|
|
{ PseudoVFMADD_VV_M2_MASK, VFMADD_VV, 0x1, 0x0 }, // 1471
|
|
{ PseudoVFMADD_VV_M4, VFMADD_VV, 0x2, 0x0 }, // 1472
|
|
{ PseudoVFMADD_VV_M4_MASK, VFMADD_VV, 0x2, 0x0 }, // 1473
|
|
{ PseudoVFMADD_VV_M8, VFMADD_VV, 0x3, 0x0 }, // 1474
|
|
{ PseudoVFMADD_VV_M8_MASK, VFMADD_VV, 0x3, 0x0 }, // 1475
|
|
{ PseudoVFMADD_VV_MF4, VFMADD_VV, 0x6, 0x0 }, // 1476
|
|
{ PseudoVFMADD_VV_MF4_MASK, VFMADD_VV, 0x6, 0x0 }, // 1477
|
|
{ PseudoVFMADD_VV_MF2, VFMADD_VV, 0x7, 0x0 }, // 1478
|
|
{ PseudoVFMADD_VV_MF2_MASK, VFMADD_VV, 0x7, 0x0 }, // 1479
|
|
{ PseudoVFMAX_VFPR16_M1, VFMAX_VF, 0x0, 0x0 }, // 1480
|
|
{ PseudoVFMAX_VFPR16_M1_MASK, VFMAX_VF, 0x0, 0x0 }, // 1481
|
|
{ PseudoVFMAX_VFPR32_M1, VFMAX_VF, 0x0, 0x0 }, // 1482
|
|
{ PseudoVFMAX_VFPR32_M1_MASK, VFMAX_VF, 0x0, 0x0 }, // 1483
|
|
{ PseudoVFMAX_VFPR64_M1, VFMAX_VF, 0x0, 0x0 }, // 1484
|
|
{ PseudoVFMAX_VFPR64_M1_MASK, VFMAX_VF, 0x0, 0x0 }, // 1485
|
|
{ PseudoVFMAX_VFPR16_M2, VFMAX_VF, 0x1, 0x0 }, // 1486
|
|
{ PseudoVFMAX_VFPR16_M2_MASK, VFMAX_VF, 0x1, 0x0 }, // 1487
|
|
{ PseudoVFMAX_VFPR32_M2, VFMAX_VF, 0x1, 0x0 }, // 1488
|
|
{ PseudoVFMAX_VFPR32_M2_MASK, VFMAX_VF, 0x1, 0x0 }, // 1489
|
|
{ PseudoVFMAX_VFPR64_M2, VFMAX_VF, 0x1, 0x0 }, // 1490
|
|
{ PseudoVFMAX_VFPR64_M2_MASK, VFMAX_VF, 0x1, 0x0 }, // 1491
|
|
{ PseudoVFMAX_VFPR16_M4, VFMAX_VF, 0x2, 0x0 }, // 1492
|
|
{ PseudoVFMAX_VFPR16_M4_MASK, VFMAX_VF, 0x2, 0x0 }, // 1493
|
|
{ PseudoVFMAX_VFPR32_M4, VFMAX_VF, 0x2, 0x0 }, // 1494
|
|
{ PseudoVFMAX_VFPR32_M4_MASK, VFMAX_VF, 0x2, 0x0 }, // 1495
|
|
{ PseudoVFMAX_VFPR64_M4, VFMAX_VF, 0x2, 0x0 }, // 1496
|
|
{ PseudoVFMAX_VFPR64_M4_MASK, VFMAX_VF, 0x2, 0x0 }, // 1497
|
|
{ PseudoVFMAX_VFPR16_M8, VFMAX_VF, 0x3, 0x0 }, // 1498
|
|
{ PseudoVFMAX_VFPR16_M8_MASK, VFMAX_VF, 0x3, 0x0 }, // 1499
|
|
{ PseudoVFMAX_VFPR32_M8, VFMAX_VF, 0x3, 0x0 }, // 1500
|
|
{ PseudoVFMAX_VFPR32_M8_MASK, VFMAX_VF, 0x3, 0x0 }, // 1501
|
|
{ PseudoVFMAX_VFPR64_M8, VFMAX_VF, 0x3, 0x0 }, // 1502
|
|
{ PseudoVFMAX_VFPR64_M8_MASK, VFMAX_VF, 0x3, 0x0 }, // 1503
|
|
{ PseudoVFMAX_VFPR16_MF4, VFMAX_VF, 0x6, 0x0 }, // 1504
|
|
{ PseudoVFMAX_VFPR16_MF4_MASK, VFMAX_VF, 0x6, 0x0 }, // 1505
|
|
{ PseudoVFMAX_VFPR16_MF2, VFMAX_VF, 0x7, 0x0 }, // 1506
|
|
{ PseudoVFMAX_VFPR16_MF2_MASK, VFMAX_VF, 0x7, 0x0 }, // 1507
|
|
{ PseudoVFMAX_VFPR32_MF2, VFMAX_VF, 0x7, 0x0 }, // 1508
|
|
{ PseudoVFMAX_VFPR32_MF2_MASK, VFMAX_VF, 0x7, 0x0 }, // 1509
|
|
{ PseudoVFMAX_VV_M1, VFMAX_VV, 0x0, 0x0 }, // 1510
|
|
{ PseudoVFMAX_VV_M1_MASK, VFMAX_VV, 0x0, 0x0 }, // 1511
|
|
{ PseudoVFMAX_VV_M2, VFMAX_VV, 0x1, 0x0 }, // 1512
|
|
{ PseudoVFMAX_VV_M2_MASK, VFMAX_VV, 0x1, 0x0 }, // 1513
|
|
{ PseudoVFMAX_VV_M4, VFMAX_VV, 0x2, 0x0 }, // 1514
|
|
{ PseudoVFMAX_VV_M4_MASK, VFMAX_VV, 0x2, 0x0 }, // 1515
|
|
{ PseudoVFMAX_VV_M8, VFMAX_VV, 0x3, 0x0 }, // 1516
|
|
{ PseudoVFMAX_VV_M8_MASK, VFMAX_VV, 0x3, 0x0 }, // 1517
|
|
{ PseudoVFMAX_VV_MF4, VFMAX_VV, 0x6, 0x0 }, // 1518
|
|
{ PseudoVFMAX_VV_MF4_MASK, VFMAX_VV, 0x6, 0x0 }, // 1519
|
|
{ PseudoVFMAX_VV_MF2, VFMAX_VV, 0x7, 0x0 }, // 1520
|
|
{ PseudoVFMAX_VV_MF2_MASK, VFMAX_VV, 0x7, 0x0 }, // 1521
|
|
{ PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1522
|
|
{ PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1523
|
|
{ PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1524
|
|
{ PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1525
|
|
{ PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1526
|
|
{ PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1527
|
|
{ PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1528
|
|
{ PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1529
|
|
{ PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1530
|
|
{ PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1531
|
|
{ PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1532
|
|
{ PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1533
|
|
{ PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM, 0x6, 0x0 }, // 1534
|
|
{ PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1535
|
|
{ PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1536
|
|
{ PseudoVFMIN_VFPR16_M1, VFMIN_VF, 0x0, 0x0 }, // 1537
|
|
{ PseudoVFMIN_VFPR16_M1_MASK, VFMIN_VF, 0x0, 0x0 }, // 1538
|
|
{ PseudoVFMIN_VFPR32_M1, VFMIN_VF, 0x0, 0x0 }, // 1539
|
|
{ PseudoVFMIN_VFPR32_M1_MASK, VFMIN_VF, 0x0, 0x0 }, // 1540
|
|
{ PseudoVFMIN_VFPR64_M1, VFMIN_VF, 0x0, 0x0 }, // 1541
|
|
{ PseudoVFMIN_VFPR64_M1_MASK, VFMIN_VF, 0x0, 0x0 }, // 1542
|
|
{ PseudoVFMIN_VFPR16_M2, VFMIN_VF, 0x1, 0x0 }, // 1543
|
|
{ PseudoVFMIN_VFPR16_M2_MASK, VFMIN_VF, 0x1, 0x0 }, // 1544
|
|
{ PseudoVFMIN_VFPR32_M2, VFMIN_VF, 0x1, 0x0 }, // 1545
|
|
{ PseudoVFMIN_VFPR32_M2_MASK, VFMIN_VF, 0x1, 0x0 }, // 1546
|
|
{ PseudoVFMIN_VFPR64_M2, VFMIN_VF, 0x1, 0x0 }, // 1547
|
|
{ PseudoVFMIN_VFPR64_M2_MASK, VFMIN_VF, 0x1, 0x0 }, // 1548
|
|
{ PseudoVFMIN_VFPR16_M4, VFMIN_VF, 0x2, 0x0 }, // 1549
|
|
{ PseudoVFMIN_VFPR16_M4_MASK, VFMIN_VF, 0x2, 0x0 }, // 1550
|
|
{ PseudoVFMIN_VFPR32_M4, VFMIN_VF, 0x2, 0x0 }, // 1551
|
|
{ PseudoVFMIN_VFPR32_M4_MASK, VFMIN_VF, 0x2, 0x0 }, // 1552
|
|
{ PseudoVFMIN_VFPR64_M4, VFMIN_VF, 0x2, 0x0 }, // 1553
|
|
{ PseudoVFMIN_VFPR64_M4_MASK, VFMIN_VF, 0x2, 0x0 }, // 1554
|
|
{ PseudoVFMIN_VFPR16_M8, VFMIN_VF, 0x3, 0x0 }, // 1555
|
|
{ PseudoVFMIN_VFPR16_M8_MASK, VFMIN_VF, 0x3, 0x0 }, // 1556
|
|
{ PseudoVFMIN_VFPR32_M8, VFMIN_VF, 0x3, 0x0 }, // 1557
|
|
{ PseudoVFMIN_VFPR32_M8_MASK, VFMIN_VF, 0x3, 0x0 }, // 1558
|
|
{ PseudoVFMIN_VFPR64_M8, VFMIN_VF, 0x3, 0x0 }, // 1559
|
|
{ PseudoVFMIN_VFPR64_M8_MASK, VFMIN_VF, 0x3, 0x0 }, // 1560
|
|
{ PseudoVFMIN_VFPR16_MF4, VFMIN_VF, 0x6, 0x0 }, // 1561
|
|
{ PseudoVFMIN_VFPR16_MF4_MASK, VFMIN_VF, 0x6, 0x0 }, // 1562
|
|
{ PseudoVFMIN_VFPR16_MF2, VFMIN_VF, 0x7, 0x0 }, // 1563
|
|
{ PseudoVFMIN_VFPR16_MF2_MASK, VFMIN_VF, 0x7, 0x0 }, // 1564
|
|
{ PseudoVFMIN_VFPR32_MF2, VFMIN_VF, 0x7, 0x0 }, // 1565
|
|
{ PseudoVFMIN_VFPR32_MF2_MASK, VFMIN_VF, 0x7, 0x0 }, // 1566
|
|
{ PseudoVFMIN_VV_M1, VFMIN_VV, 0x0, 0x0 }, // 1567
|
|
{ PseudoVFMIN_VV_M1_MASK, VFMIN_VV, 0x0, 0x0 }, // 1568
|
|
{ PseudoVFMIN_VV_M2, VFMIN_VV, 0x1, 0x0 }, // 1569
|
|
{ PseudoVFMIN_VV_M2_MASK, VFMIN_VV, 0x1, 0x0 }, // 1570
|
|
{ PseudoVFMIN_VV_M4, VFMIN_VV, 0x2, 0x0 }, // 1571
|
|
{ PseudoVFMIN_VV_M4_MASK, VFMIN_VV, 0x2, 0x0 }, // 1572
|
|
{ PseudoVFMIN_VV_M8, VFMIN_VV, 0x3, 0x0 }, // 1573
|
|
{ PseudoVFMIN_VV_M8_MASK, VFMIN_VV, 0x3, 0x0 }, // 1574
|
|
{ PseudoVFMIN_VV_MF4, VFMIN_VV, 0x6, 0x0 }, // 1575
|
|
{ PseudoVFMIN_VV_MF4_MASK, VFMIN_VV, 0x6, 0x0 }, // 1576
|
|
{ PseudoVFMIN_VV_MF2, VFMIN_VV, 0x7, 0x0 }, // 1577
|
|
{ PseudoVFMIN_VV_MF2_MASK, VFMIN_VV, 0x7, 0x0 }, // 1578
|
|
{ PseudoVFMSAC_VFPR16_M1, VFMSAC_VF, 0x0, 0x0 }, // 1579
|
|
{ PseudoVFMSAC_VFPR16_M1_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1580
|
|
{ PseudoVFMSAC_VFPR32_M1, VFMSAC_VF, 0x0, 0x0 }, // 1581
|
|
{ PseudoVFMSAC_VFPR32_M1_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1582
|
|
{ PseudoVFMSAC_VFPR64_M1, VFMSAC_VF, 0x0, 0x0 }, // 1583
|
|
{ PseudoVFMSAC_VFPR64_M1_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1584
|
|
{ PseudoVFMSAC_VFPR16_M2, VFMSAC_VF, 0x1, 0x0 }, // 1585
|
|
{ PseudoVFMSAC_VFPR16_M2_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1586
|
|
{ PseudoVFMSAC_VFPR32_M2, VFMSAC_VF, 0x1, 0x0 }, // 1587
|
|
{ PseudoVFMSAC_VFPR32_M2_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1588
|
|
{ PseudoVFMSAC_VFPR64_M2, VFMSAC_VF, 0x1, 0x0 }, // 1589
|
|
{ PseudoVFMSAC_VFPR64_M2_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1590
|
|
{ PseudoVFMSAC_VFPR16_M4, VFMSAC_VF, 0x2, 0x0 }, // 1591
|
|
{ PseudoVFMSAC_VFPR16_M4_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1592
|
|
{ PseudoVFMSAC_VFPR32_M4, VFMSAC_VF, 0x2, 0x0 }, // 1593
|
|
{ PseudoVFMSAC_VFPR32_M4_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1594
|
|
{ PseudoVFMSAC_VFPR64_M4, VFMSAC_VF, 0x2, 0x0 }, // 1595
|
|
{ PseudoVFMSAC_VFPR64_M4_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1596
|
|
{ PseudoVFMSAC_VFPR16_M8, VFMSAC_VF, 0x3, 0x0 }, // 1597
|
|
{ PseudoVFMSAC_VFPR16_M8_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1598
|
|
{ PseudoVFMSAC_VFPR32_M8, VFMSAC_VF, 0x3, 0x0 }, // 1599
|
|
{ PseudoVFMSAC_VFPR32_M8_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1600
|
|
{ PseudoVFMSAC_VFPR64_M8, VFMSAC_VF, 0x3, 0x0 }, // 1601
|
|
{ PseudoVFMSAC_VFPR64_M8_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1602
|
|
{ PseudoVFMSAC_VFPR16_MF4, VFMSAC_VF, 0x6, 0x0 }, // 1603
|
|
{ PseudoVFMSAC_VFPR16_MF4_MASK, VFMSAC_VF, 0x6, 0x0 }, // 1604
|
|
{ PseudoVFMSAC_VFPR16_MF2, VFMSAC_VF, 0x7, 0x0 }, // 1605
|
|
{ PseudoVFMSAC_VFPR16_MF2_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1606
|
|
{ PseudoVFMSAC_VFPR32_MF2, VFMSAC_VF, 0x7, 0x0 }, // 1607
|
|
{ PseudoVFMSAC_VFPR32_MF2_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1608
|
|
{ PseudoVFMSAC_VV_M1, VFMSAC_VV, 0x0, 0x0 }, // 1609
|
|
{ PseudoVFMSAC_VV_M1_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1610
|
|
{ PseudoVFMSAC_VV_M2, VFMSAC_VV, 0x1, 0x0 }, // 1611
|
|
{ PseudoVFMSAC_VV_M2_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1612
|
|
{ PseudoVFMSAC_VV_M4, VFMSAC_VV, 0x2, 0x0 }, // 1613
|
|
{ PseudoVFMSAC_VV_M4_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1614
|
|
{ PseudoVFMSAC_VV_M8, VFMSAC_VV, 0x3, 0x0 }, // 1615
|
|
{ PseudoVFMSAC_VV_M8_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1616
|
|
{ PseudoVFMSAC_VV_MF4, VFMSAC_VV, 0x6, 0x0 }, // 1617
|
|
{ PseudoVFMSAC_VV_MF4_MASK, VFMSAC_VV, 0x6, 0x0 }, // 1618
|
|
{ PseudoVFMSAC_VV_MF2, VFMSAC_VV, 0x7, 0x0 }, // 1619
|
|
{ PseudoVFMSAC_VV_MF2_MASK, VFMSAC_VV, 0x7, 0x0 }, // 1620
|
|
{ PseudoVFMSUB_VFPR16_M1, VFMSUB_VF, 0x0, 0x0 }, // 1621
|
|
{ PseudoVFMSUB_VFPR16_M1_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1622
|
|
{ PseudoVFMSUB_VFPR32_M1, VFMSUB_VF, 0x0, 0x0 }, // 1623
|
|
{ PseudoVFMSUB_VFPR32_M1_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1624
|
|
{ PseudoVFMSUB_VFPR64_M1, VFMSUB_VF, 0x0, 0x0 }, // 1625
|
|
{ PseudoVFMSUB_VFPR64_M1_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1626
|
|
{ PseudoVFMSUB_VFPR16_M2, VFMSUB_VF, 0x1, 0x0 }, // 1627
|
|
{ PseudoVFMSUB_VFPR16_M2_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1628
|
|
{ PseudoVFMSUB_VFPR32_M2, VFMSUB_VF, 0x1, 0x0 }, // 1629
|
|
{ PseudoVFMSUB_VFPR32_M2_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1630
|
|
{ PseudoVFMSUB_VFPR64_M2, VFMSUB_VF, 0x1, 0x0 }, // 1631
|
|
{ PseudoVFMSUB_VFPR64_M2_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1632
|
|
{ PseudoVFMSUB_VFPR16_M4, VFMSUB_VF, 0x2, 0x0 }, // 1633
|
|
{ PseudoVFMSUB_VFPR16_M4_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1634
|
|
{ PseudoVFMSUB_VFPR32_M4, VFMSUB_VF, 0x2, 0x0 }, // 1635
|
|
{ PseudoVFMSUB_VFPR32_M4_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1636
|
|
{ PseudoVFMSUB_VFPR64_M4, VFMSUB_VF, 0x2, 0x0 }, // 1637
|
|
{ PseudoVFMSUB_VFPR64_M4_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1638
|
|
{ PseudoVFMSUB_VFPR16_M8, VFMSUB_VF, 0x3, 0x0 }, // 1639
|
|
{ PseudoVFMSUB_VFPR16_M8_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1640
|
|
{ PseudoVFMSUB_VFPR32_M8, VFMSUB_VF, 0x3, 0x0 }, // 1641
|
|
{ PseudoVFMSUB_VFPR32_M8_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1642
|
|
{ PseudoVFMSUB_VFPR64_M8, VFMSUB_VF, 0x3, 0x0 }, // 1643
|
|
{ PseudoVFMSUB_VFPR64_M8_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1644
|
|
{ PseudoVFMSUB_VFPR16_MF4, VFMSUB_VF, 0x6, 0x0 }, // 1645
|
|
{ PseudoVFMSUB_VFPR16_MF4_MASK, VFMSUB_VF, 0x6, 0x0 }, // 1646
|
|
{ PseudoVFMSUB_VFPR16_MF2, VFMSUB_VF, 0x7, 0x0 }, // 1647
|
|
{ PseudoVFMSUB_VFPR16_MF2_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1648
|
|
{ PseudoVFMSUB_VFPR32_MF2, VFMSUB_VF, 0x7, 0x0 }, // 1649
|
|
{ PseudoVFMSUB_VFPR32_MF2_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1650
|
|
{ PseudoVFMSUB_VV_M1, VFMSUB_VV, 0x0, 0x0 }, // 1651
|
|
{ PseudoVFMSUB_VV_M1_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1652
|
|
{ PseudoVFMSUB_VV_M2, VFMSUB_VV, 0x1, 0x0 }, // 1653
|
|
{ PseudoVFMSUB_VV_M2_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1654
|
|
{ PseudoVFMSUB_VV_M4, VFMSUB_VV, 0x2, 0x0 }, // 1655
|
|
{ PseudoVFMSUB_VV_M4_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1656
|
|
{ PseudoVFMSUB_VV_M8, VFMSUB_VV, 0x3, 0x0 }, // 1657
|
|
{ PseudoVFMSUB_VV_M8_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1658
|
|
{ PseudoVFMSUB_VV_MF4, VFMSUB_VV, 0x6, 0x0 }, // 1659
|
|
{ PseudoVFMSUB_VV_MF4_MASK, VFMSUB_VV, 0x6, 0x0 }, // 1660
|
|
{ PseudoVFMSUB_VV_MF2, VFMSUB_VV, 0x7, 0x0 }, // 1661
|
|
{ PseudoVFMSUB_VV_MF2_MASK, VFMSUB_VV, 0x7, 0x0 }, // 1662
|
|
{ PseudoVFMUL_VFPR16_M1, VFMUL_VF, 0x0, 0x0 }, // 1663
|
|
{ PseudoVFMUL_VFPR16_M1_MASK, VFMUL_VF, 0x0, 0x0 }, // 1664
|
|
{ PseudoVFMUL_VFPR32_M1, VFMUL_VF, 0x0, 0x0 }, // 1665
|
|
{ PseudoVFMUL_VFPR32_M1_MASK, VFMUL_VF, 0x0, 0x0 }, // 1666
|
|
{ PseudoVFMUL_VFPR64_M1, VFMUL_VF, 0x0, 0x0 }, // 1667
|
|
{ PseudoVFMUL_VFPR64_M1_MASK, VFMUL_VF, 0x0, 0x0 }, // 1668
|
|
{ PseudoVFMUL_VFPR16_M2, VFMUL_VF, 0x1, 0x0 }, // 1669
|
|
{ PseudoVFMUL_VFPR16_M2_MASK, VFMUL_VF, 0x1, 0x0 }, // 1670
|
|
{ PseudoVFMUL_VFPR32_M2, VFMUL_VF, 0x1, 0x0 }, // 1671
|
|
{ PseudoVFMUL_VFPR32_M2_MASK, VFMUL_VF, 0x1, 0x0 }, // 1672
|
|
{ PseudoVFMUL_VFPR64_M2, VFMUL_VF, 0x1, 0x0 }, // 1673
|
|
{ PseudoVFMUL_VFPR64_M2_MASK, VFMUL_VF, 0x1, 0x0 }, // 1674
|
|
{ PseudoVFMUL_VFPR16_M4, VFMUL_VF, 0x2, 0x0 }, // 1675
|
|
{ PseudoVFMUL_VFPR16_M4_MASK, VFMUL_VF, 0x2, 0x0 }, // 1676
|
|
{ PseudoVFMUL_VFPR32_M4, VFMUL_VF, 0x2, 0x0 }, // 1677
|
|
{ PseudoVFMUL_VFPR32_M4_MASK, VFMUL_VF, 0x2, 0x0 }, // 1678
|
|
{ PseudoVFMUL_VFPR64_M4, VFMUL_VF, 0x2, 0x0 }, // 1679
|
|
{ PseudoVFMUL_VFPR64_M4_MASK, VFMUL_VF, 0x2, 0x0 }, // 1680
|
|
{ PseudoVFMUL_VFPR16_M8, VFMUL_VF, 0x3, 0x0 }, // 1681
|
|
{ PseudoVFMUL_VFPR16_M8_MASK, VFMUL_VF, 0x3, 0x0 }, // 1682
|
|
{ PseudoVFMUL_VFPR32_M8, VFMUL_VF, 0x3, 0x0 }, // 1683
|
|
{ PseudoVFMUL_VFPR32_M8_MASK, VFMUL_VF, 0x3, 0x0 }, // 1684
|
|
{ PseudoVFMUL_VFPR64_M8, VFMUL_VF, 0x3, 0x0 }, // 1685
|
|
{ PseudoVFMUL_VFPR64_M8_MASK, VFMUL_VF, 0x3, 0x0 }, // 1686
|
|
{ PseudoVFMUL_VFPR16_MF4, VFMUL_VF, 0x6, 0x0 }, // 1687
|
|
{ PseudoVFMUL_VFPR16_MF4_MASK, VFMUL_VF, 0x6, 0x0 }, // 1688
|
|
{ PseudoVFMUL_VFPR16_MF2, VFMUL_VF, 0x7, 0x0 }, // 1689
|
|
{ PseudoVFMUL_VFPR16_MF2_MASK, VFMUL_VF, 0x7, 0x0 }, // 1690
|
|
{ PseudoVFMUL_VFPR32_MF2, VFMUL_VF, 0x7, 0x0 }, // 1691
|
|
{ PseudoVFMUL_VFPR32_MF2_MASK, VFMUL_VF, 0x7, 0x0 }, // 1692
|
|
{ PseudoVFMUL_VV_M1, VFMUL_VV, 0x0, 0x0 }, // 1693
|
|
{ PseudoVFMUL_VV_M1_MASK, VFMUL_VV, 0x0, 0x0 }, // 1694
|
|
{ PseudoVFMUL_VV_M2, VFMUL_VV, 0x1, 0x0 }, // 1695
|
|
{ PseudoVFMUL_VV_M2_MASK, VFMUL_VV, 0x1, 0x0 }, // 1696
|
|
{ PseudoVFMUL_VV_M4, VFMUL_VV, 0x2, 0x0 }, // 1697
|
|
{ PseudoVFMUL_VV_M4_MASK, VFMUL_VV, 0x2, 0x0 }, // 1698
|
|
{ PseudoVFMUL_VV_M8, VFMUL_VV, 0x3, 0x0 }, // 1699
|
|
{ PseudoVFMUL_VV_M8_MASK, VFMUL_VV, 0x3, 0x0 }, // 1700
|
|
{ PseudoVFMUL_VV_MF4, VFMUL_VV, 0x6, 0x0 }, // 1701
|
|
{ PseudoVFMUL_VV_MF4_MASK, VFMUL_VV, 0x6, 0x0 }, // 1702
|
|
{ PseudoVFMUL_VV_MF2, VFMUL_VV, 0x7, 0x0 }, // 1703
|
|
{ PseudoVFMUL_VV_MF2_MASK, VFMUL_VV, 0x7, 0x0 }, // 1704
|
|
{ PseudoVFMV_FPR16_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1705
|
|
{ PseudoVFMV_FPR32_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1706
|
|
{ PseudoVFMV_FPR64_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1707
|
|
{ PseudoVFMV_FPR16_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1708
|
|
{ PseudoVFMV_FPR32_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1709
|
|
{ PseudoVFMV_FPR64_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1710
|
|
{ PseudoVFMV_FPR16_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1711
|
|
{ PseudoVFMV_FPR32_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1712
|
|
{ PseudoVFMV_FPR64_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1713
|
|
{ PseudoVFMV_FPR16_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1714
|
|
{ PseudoVFMV_FPR32_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1715
|
|
{ PseudoVFMV_FPR64_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1716
|
|
{ PseudoVFMV_FPR16_S_MF4, VFMV_F_S, 0x6, 0x0 }, // 1717
|
|
{ PseudoVFMV_FPR16_S_MF2, VFMV_F_S, 0x7, 0x0 }, // 1718
|
|
{ PseudoVFMV_FPR32_S_MF2, VFMV_F_S, 0x7, 0x0 }, // 1719
|
|
{ PseudoVFMV_S_FPR16_M1, VFMV_S_F, 0x0, 0x0 }, // 1720
|
|
{ PseudoVFMV_S_FPR32_M1, VFMV_S_F, 0x0, 0x0 }, // 1721
|
|
{ PseudoVFMV_S_FPR64_M1, VFMV_S_F, 0x0, 0x0 }, // 1722
|
|
{ PseudoVFMV_S_FPR16_M2, VFMV_S_F, 0x1, 0x0 }, // 1723
|
|
{ PseudoVFMV_S_FPR32_M2, VFMV_S_F, 0x1, 0x0 }, // 1724
|
|
{ PseudoVFMV_S_FPR64_M2, VFMV_S_F, 0x1, 0x0 }, // 1725
|
|
{ PseudoVFMV_S_FPR16_M4, VFMV_S_F, 0x2, 0x0 }, // 1726
|
|
{ PseudoVFMV_S_FPR32_M4, VFMV_S_F, 0x2, 0x0 }, // 1727
|
|
{ PseudoVFMV_S_FPR64_M4, VFMV_S_F, 0x2, 0x0 }, // 1728
|
|
{ PseudoVFMV_S_FPR16_M8, VFMV_S_F, 0x3, 0x0 }, // 1729
|
|
{ PseudoVFMV_S_FPR32_M8, VFMV_S_F, 0x3, 0x0 }, // 1730
|
|
{ PseudoVFMV_S_FPR64_M8, VFMV_S_F, 0x3, 0x0 }, // 1731
|
|
{ PseudoVFMV_S_FPR16_MF4, VFMV_S_F, 0x6, 0x0 }, // 1732
|
|
{ PseudoVFMV_S_FPR16_MF2, VFMV_S_F, 0x7, 0x0 }, // 1733
|
|
{ PseudoVFMV_S_FPR32_MF2, VFMV_S_F, 0x7, 0x0 }, // 1734
|
|
{ PseudoVFMV_V_FPR16_M1, VFMV_V_F, 0x0, 0x0 }, // 1735
|
|
{ PseudoVFMV_V_FPR32_M1, VFMV_V_F, 0x0, 0x0 }, // 1736
|
|
{ PseudoVFMV_V_FPR64_M1, VFMV_V_F, 0x0, 0x0 }, // 1737
|
|
{ PseudoVFMV_V_FPR16_M2, VFMV_V_F, 0x1, 0x0 }, // 1738
|
|
{ PseudoVFMV_V_FPR32_M2, VFMV_V_F, 0x1, 0x0 }, // 1739
|
|
{ PseudoVFMV_V_FPR64_M2, VFMV_V_F, 0x1, 0x0 }, // 1740
|
|
{ PseudoVFMV_V_FPR16_M4, VFMV_V_F, 0x2, 0x0 }, // 1741
|
|
{ PseudoVFMV_V_FPR32_M4, VFMV_V_F, 0x2, 0x0 }, // 1742
|
|
{ PseudoVFMV_V_FPR64_M4, VFMV_V_F, 0x2, 0x0 }, // 1743
|
|
{ PseudoVFMV_V_FPR16_M8, VFMV_V_F, 0x3, 0x0 }, // 1744
|
|
{ PseudoVFMV_V_FPR32_M8, VFMV_V_F, 0x3, 0x0 }, // 1745
|
|
{ PseudoVFMV_V_FPR64_M8, VFMV_V_F, 0x3, 0x0 }, // 1746
|
|
{ PseudoVFMV_V_FPR16_MF4, VFMV_V_F, 0x6, 0x0 }, // 1747
|
|
{ PseudoVFMV_V_FPR16_MF2, VFMV_V_F, 0x7, 0x0 }, // 1748
|
|
{ PseudoVFMV_V_FPR32_MF2, VFMV_V_F, 0x7, 0x0 }, // 1749
|
|
{ PseudoVFNCVTBF16_F_F_W_M1, VFNCVTBF16_F_F_W, 0x0, 0x0 }, // 1750
|
|
{ PseudoVFNCVTBF16_F_F_W_M1_MASK, VFNCVTBF16_F_F_W, 0x0, 0x0 }, // 1751
|
|
{ PseudoVFNCVTBF16_F_F_W_M2, VFNCVTBF16_F_F_W, 0x1, 0x0 }, // 1752
|
|
{ PseudoVFNCVTBF16_F_F_W_M2_MASK, VFNCVTBF16_F_F_W, 0x1, 0x0 }, // 1753
|
|
{ PseudoVFNCVTBF16_F_F_W_M4, VFNCVTBF16_F_F_W, 0x2, 0x0 }, // 1754
|
|
{ PseudoVFNCVTBF16_F_F_W_M4_MASK, VFNCVTBF16_F_F_W, 0x2, 0x0 }, // 1755
|
|
{ PseudoVFNCVTBF16_F_F_W_MF4, VFNCVTBF16_F_F_W, 0x6, 0x0 }, // 1756
|
|
{ PseudoVFNCVTBF16_F_F_W_MF4_MASK, VFNCVTBF16_F_F_W, 0x6, 0x0 }, // 1757
|
|
{ PseudoVFNCVTBF16_F_F_W_MF2, VFNCVTBF16_F_F_W, 0x7, 0x0 }, // 1758
|
|
{ PseudoVFNCVTBF16_F_F_W_MF2_MASK, VFNCVTBF16_F_F_W, 0x7, 0x0 }, // 1759
|
|
{ PseudoVFNCVT_F_F_W_M1, VFNCVT_F_F_W, 0x0, 0x0 }, // 1760
|
|
{ PseudoVFNCVT_F_F_W_M1_MASK, VFNCVT_F_F_W, 0x0, 0x0 }, // 1761
|
|
{ PseudoVFNCVT_F_F_W_M2, VFNCVT_F_F_W, 0x1, 0x0 }, // 1762
|
|
{ PseudoVFNCVT_F_F_W_M2_MASK, VFNCVT_F_F_W, 0x1, 0x0 }, // 1763
|
|
{ PseudoVFNCVT_F_F_W_M4, VFNCVT_F_F_W, 0x2, 0x0 }, // 1764
|
|
{ PseudoVFNCVT_F_F_W_M4_MASK, VFNCVT_F_F_W, 0x2, 0x0 }, // 1765
|
|
{ PseudoVFNCVT_F_F_W_MF4, VFNCVT_F_F_W, 0x6, 0x0 }, // 1766
|
|
{ PseudoVFNCVT_F_F_W_MF4_MASK, VFNCVT_F_F_W, 0x6, 0x0 }, // 1767
|
|
{ PseudoVFNCVT_F_F_W_MF2, VFNCVT_F_F_W, 0x7, 0x0 }, // 1768
|
|
{ PseudoVFNCVT_F_F_W_MF2_MASK, VFNCVT_F_F_W, 0x7, 0x0 }, // 1769
|
|
{ PseudoVFNCVT_F_XU_W_M1, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1770
|
|
{ PseudoVFNCVT_F_XU_W_M1_MASK, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1771
|
|
{ PseudoVFNCVT_RM_F_XU_W_M1, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1772
|
|
{ PseudoVFNCVT_RM_F_XU_W_M1_MASK, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1773
|
|
{ PseudoVFNCVT_F_XU_W_M2, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1774
|
|
{ PseudoVFNCVT_F_XU_W_M2_MASK, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1775
|
|
{ PseudoVFNCVT_RM_F_XU_W_M2, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1776
|
|
{ PseudoVFNCVT_RM_F_XU_W_M2_MASK, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1777
|
|
{ PseudoVFNCVT_F_XU_W_M4, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1778
|
|
{ PseudoVFNCVT_F_XU_W_M4_MASK, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1779
|
|
{ PseudoVFNCVT_RM_F_XU_W_M4, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1780
|
|
{ PseudoVFNCVT_RM_F_XU_W_M4_MASK, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1781
|
|
{ PseudoVFNCVT_F_XU_W_MF4, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1782
|
|
{ PseudoVFNCVT_F_XU_W_MF4_MASK, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1783
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF4, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1784
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF4_MASK, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1785
|
|
{ PseudoVFNCVT_F_XU_W_MF2, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1786
|
|
{ PseudoVFNCVT_F_XU_W_MF2_MASK, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1787
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF2, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1788
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF2_MASK, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1789
|
|
{ PseudoVFNCVT_F_X_W_M1, VFNCVT_F_X_W, 0x0, 0x0 }, // 1790
|
|
{ PseudoVFNCVT_F_X_W_M1_MASK, VFNCVT_F_X_W, 0x0, 0x0 }, // 1791
|
|
{ PseudoVFNCVT_RM_F_X_W_M1, VFNCVT_F_X_W, 0x0, 0x0 }, // 1792
|
|
{ PseudoVFNCVT_RM_F_X_W_M1_MASK, VFNCVT_F_X_W, 0x0, 0x0 }, // 1793
|
|
{ PseudoVFNCVT_F_X_W_M2, VFNCVT_F_X_W, 0x1, 0x0 }, // 1794
|
|
{ PseudoVFNCVT_F_X_W_M2_MASK, VFNCVT_F_X_W, 0x1, 0x0 }, // 1795
|
|
{ PseudoVFNCVT_RM_F_X_W_M2, VFNCVT_F_X_W, 0x1, 0x0 }, // 1796
|
|
{ PseudoVFNCVT_RM_F_X_W_M2_MASK, VFNCVT_F_X_W, 0x1, 0x0 }, // 1797
|
|
{ PseudoVFNCVT_F_X_W_M4, VFNCVT_F_X_W, 0x2, 0x0 }, // 1798
|
|
{ PseudoVFNCVT_F_X_W_M4_MASK, VFNCVT_F_X_W, 0x2, 0x0 }, // 1799
|
|
{ PseudoVFNCVT_RM_F_X_W_M4, VFNCVT_F_X_W, 0x2, 0x0 }, // 1800
|
|
{ PseudoVFNCVT_RM_F_X_W_M4_MASK, VFNCVT_F_X_W, 0x2, 0x0 }, // 1801
|
|
{ PseudoVFNCVT_F_X_W_MF4, VFNCVT_F_X_W, 0x6, 0x0 }, // 1802
|
|
{ PseudoVFNCVT_F_X_W_MF4_MASK, VFNCVT_F_X_W, 0x6, 0x0 }, // 1803
|
|
{ PseudoVFNCVT_RM_F_X_W_MF4, VFNCVT_F_X_W, 0x6, 0x0 }, // 1804
|
|
{ PseudoVFNCVT_RM_F_X_W_MF4_MASK, VFNCVT_F_X_W, 0x6, 0x0 }, // 1805
|
|
{ PseudoVFNCVT_F_X_W_MF2, VFNCVT_F_X_W, 0x7, 0x0 }, // 1806
|
|
{ PseudoVFNCVT_F_X_W_MF2_MASK, VFNCVT_F_X_W, 0x7, 0x0 }, // 1807
|
|
{ PseudoVFNCVT_RM_F_X_W_MF2, VFNCVT_F_X_W, 0x7, 0x0 }, // 1808
|
|
{ PseudoVFNCVT_RM_F_X_W_MF2_MASK, VFNCVT_F_X_W, 0x7, 0x0 }, // 1809
|
|
{ PseudoVFNCVT_ROD_F_F_W_M1, VFNCVT_ROD_F_F_W, 0x0, 0x0 }, // 1810
|
|
{ PseudoVFNCVT_ROD_F_F_W_M1_MASK, VFNCVT_ROD_F_F_W, 0x0, 0x0 }, // 1811
|
|
{ PseudoVFNCVT_ROD_F_F_W_M2, VFNCVT_ROD_F_F_W, 0x1, 0x0 }, // 1812
|
|
{ PseudoVFNCVT_ROD_F_F_W_M2_MASK, VFNCVT_ROD_F_F_W, 0x1, 0x0 }, // 1813
|
|
{ PseudoVFNCVT_ROD_F_F_W_M4, VFNCVT_ROD_F_F_W, 0x2, 0x0 }, // 1814
|
|
{ PseudoVFNCVT_ROD_F_F_W_M4_MASK, VFNCVT_ROD_F_F_W, 0x2, 0x0 }, // 1815
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF4, VFNCVT_ROD_F_F_W, 0x6, 0x0 }, // 1816
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF4_MASK, VFNCVT_ROD_F_F_W, 0x6, 0x0 }, // 1817
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF2, VFNCVT_ROD_F_F_W, 0x7, 0x0 }, // 1818
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF2_MASK, VFNCVT_ROD_F_F_W, 0x7, 0x0 }, // 1819
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 1820
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 1821
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 1822
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 1823
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 1824
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 1825
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 1826
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 1827
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 1828
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 1829
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 1830
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 1831
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 1832
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 1833
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 1834
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 1835
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 1836
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 1837
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 1838
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 1839
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 1840
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 1841
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 1842
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 1843
|
|
{ PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1844
|
|
{ PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1845
|
|
{ PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1846
|
|
{ PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1847
|
|
{ PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1848
|
|
{ PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1849
|
|
{ PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1850
|
|
{ PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1851
|
|
{ PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1852
|
|
{ PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1853
|
|
{ PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1854
|
|
{ PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1855
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1856
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1857
|
|
{ PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1858
|
|
{ PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1859
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1860
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1861
|
|
{ PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1862
|
|
{ PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1863
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1864
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1865
|
|
{ PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1866
|
|
{ PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1867
|
|
{ PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 1868
|
|
{ PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 1869
|
|
{ PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 1870
|
|
{ PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 1871
|
|
{ PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 1872
|
|
{ PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 1873
|
|
{ PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 1874
|
|
{ PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 1875
|
|
{ PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 1876
|
|
{ PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 1877
|
|
{ PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 1878
|
|
{ PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 1879
|
|
{ PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 1880
|
|
{ PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 1881
|
|
{ PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 1882
|
|
{ PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 1883
|
|
{ PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 1884
|
|
{ PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 1885
|
|
{ PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 1886
|
|
{ PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 1887
|
|
{ PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 1888
|
|
{ PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 1889
|
|
{ PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 1890
|
|
{ PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 1891
|
|
{ PseudoVFNMACC_VFPR16_M1, VFNMACC_VF, 0x0, 0x0 }, // 1892
|
|
{ PseudoVFNMACC_VFPR16_M1_MASK, VFNMACC_VF, 0x0, 0x0 }, // 1893
|
|
{ PseudoVFNMACC_VFPR32_M1, VFNMACC_VF, 0x0, 0x0 }, // 1894
|
|
{ PseudoVFNMACC_VFPR32_M1_MASK, VFNMACC_VF, 0x0, 0x0 }, // 1895
|
|
{ PseudoVFNMACC_VFPR64_M1, VFNMACC_VF, 0x0, 0x0 }, // 1896
|
|
{ PseudoVFNMACC_VFPR64_M1_MASK, VFNMACC_VF, 0x0, 0x0 }, // 1897
|
|
{ PseudoVFNMACC_VFPR16_M2, VFNMACC_VF, 0x1, 0x0 }, // 1898
|
|
{ PseudoVFNMACC_VFPR16_M2_MASK, VFNMACC_VF, 0x1, 0x0 }, // 1899
|
|
{ PseudoVFNMACC_VFPR32_M2, VFNMACC_VF, 0x1, 0x0 }, // 1900
|
|
{ PseudoVFNMACC_VFPR32_M2_MASK, VFNMACC_VF, 0x1, 0x0 }, // 1901
|
|
{ PseudoVFNMACC_VFPR64_M2, VFNMACC_VF, 0x1, 0x0 }, // 1902
|
|
{ PseudoVFNMACC_VFPR64_M2_MASK, VFNMACC_VF, 0x1, 0x0 }, // 1903
|
|
{ PseudoVFNMACC_VFPR16_M4, VFNMACC_VF, 0x2, 0x0 }, // 1904
|
|
{ PseudoVFNMACC_VFPR16_M4_MASK, VFNMACC_VF, 0x2, 0x0 }, // 1905
|
|
{ PseudoVFNMACC_VFPR32_M4, VFNMACC_VF, 0x2, 0x0 }, // 1906
|
|
{ PseudoVFNMACC_VFPR32_M4_MASK, VFNMACC_VF, 0x2, 0x0 }, // 1907
|
|
{ PseudoVFNMACC_VFPR64_M4, VFNMACC_VF, 0x2, 0x0 }, // 1908
|
|
{ PseudoVFNMACC_VFPR64_M4_MASK, VFNMACC_VF, 0x2, 0x0 }, // 1909
|
|
{ PseudoVFNMACC_VFPR16_M8, VFNMACC_VF, 0x3, 0x0 }, // 1910
|
|
{ PseudoVFNMACC_VFPR16_M8_MASK, VFNMACC_VF, 0x3, 0x0 }, // 1911
|
|
{ PseudoVFNMACC_VFPR32_M8, VFNMACC_VF, 0x3, 0x0 }, // 1912
|
|
{ PseudoVFNMACC_VFPR32_M8_MASK, VFNMACC_VF, 0x3, 0x0 }, // 1913
|
|
{ PseudoVFNMACC_VFPR64_M8, VFNMACC_VF, 0x3, 0x0 }, // 1914
|
|
{ PseudoVFNMACC_VFPR64_M8_MASK, VFNMACC_VF, 0x3, 0x0 }, // 1915
|
|
{ PseudoVFNMACC_VFPR16_MF4, VFNMACC_VF, 0x6, 0x0 }, // 1916
|
|
{ PseudoVFNMACC_VFPR16_MF4_MASK, VFNMACC_VF, 0x6, 0x0 }, // 1917
|
|
{ PseudoVFNMACC_VFPR16_MF2, VFNMACC_VF, 0x7, 0x0 }, // 1918
|
|
{ PseudoVFNMACC_VFPR16_MF2_MASK, VFNMACC_VF, 0x7, 0x0 }, // 1919
|
|
{ PseudoVFNMACC_VFPR32_MF2, VFNMACC_VF, 0x7, 0x0 }, // 1920
|
|
{ PseudoVFNMACC_VFPR32_MF2_MASK, VFNMACC_VF, 0x7, 0x0 }, // 1921
|
|
{ PseudoVFNMACC_VV_M1, VFNMACC_VV, 0x0, 0x0 }, // 1922
|
|
{ PseudoVFNMACC_VV_M1_MASK, VFNMACC_VV, 0x0, 0x0 }, // 1923
|
|
{ PseudoVFNMACC_VV_M2, VFNMACC_VV, 0x1, 0x0 }, // 1924
|
|
{ PseudoVFNMACC_VV_M2_MASK, VFNMACC_VV, 0x1, 0x0 }, // 1925
|
|
{ PseudoVFNMACC_VV_M4, VFNMACC_VV, 0x2, 0x0 }, // 1926
|
|
{ PseudoVFNMACC_VV_M4_MASK, VFNMACC_VV, 0x2, 0x0 }, // 1927
|
|
{ PseudoVFNMACC_VV_M8, VFNMACC_VV, 0x3, 0x0 }, // 1928
|
|
{ PseudoVFNMACC_VV_M8_MASK, VFNMACC_VV, 0x3, 0x0 }, // 1929
|
|
{ PseudoVFNMACC_VV_MF4, VFNMACC_VV, 0x6, 0x0 }, // 1930
|
|
{ PseudoVFNMACC_VV_MF4_MASK, VFNMACC_VV, 0x6, 0x0 }, // 1931
|
|
{ PseudoVFNMACC_VV_MF2, VFNMACC_VV, 0x7, 0x0 }, // 1932
|
|
{ PseudoVFNMACC_VV_MF2_MASK, VFNMACC_VV, 0x7, 0x0 }, // 1933
|
|
{ PseudoVFNMADD_VFPR16_M1, VFNMADD_VF, 0x0, 0x0 }, // 1934
|
|
{ PseudoVFNMADD_VFPR16_M1_MASK, VFNMADD_VF, 0x0, 0x0 }, // 1935
|
|
{ PseudoVFNMADD_VFPR32_M1, VFNMADD_VF, 0x0, 0x0 }, // 1936
|
|
{ PseudoVFNMADD_VFPR32_M1_MASK, VFNMADD_VF, 0x0, 0x0 }, // 1937
|
|
{ PseudoVFNMADD_VFPR64_M1, VFNMADD_VF, 0x0, 0x0 }, // 1938
|
|
{ PseudoVFNMADD_VFPR64_M1_MASK, VFNMADD_VF, 0x0, 0x0 }, // 1939
|
|
{ PseudoVFNMADD_VFPR16_M2, VFNMADD_VF, 0x1, 0x0 }, // 1940
|
|
{ PseudoVFNMADD_VFPR16_M2_MASK, VFNMADD_VF, 0x1, 0x0 }, // 1941
|
|
{ PseudoVFNMADD_VFPR32_M2, VFNMADD_VF, 0x1, 0x0 }, // 1942
|
|
{ PseudoVFNMADD_VFPR32_M2_MASK, VFNMADD_VF, 0x1, 0x0 }, // 1943
|
|
{ PseudoVFNMADD_VFPR64_M2, VFNMADD_VF, 0x1, 0x0 }, // 1944
|
|
{ PseudoVFNMADD_VFPR64_M2_MASK, VFNMADD_VF, 0x1, 0x0 }, // 1945
|
|
{ PseudoVFNMADD_VFPR16_M4, VFNMADD_VF, 0x2, 0x0 }, // 1946
|
|
{ PseudoVFNMADD_VFPR16_M4_MASK, VFNMADD_VF, 0x2, 0x0 }, // 1947
|
|
{ PseudoVFNMADD_VFPR32_M4, VFNMADD_VF, 0x2, 0x0 }, // 1948
|
|
{ PseudoVFNMADD_VFPR32_M4_MASK, VFNMADD_VF, 0x2, 0x0 }, // 1949
|
|
{ PseudoVFNMADD_VFPR64_M4, VFNMADD_VF, 0x2, 0x0 }, // 1950
|
|
{ PseudoVFNMADD_VFPR64_M4_MASK, VFNMADD_VF, 0x2, 0x0 }, // 1951
|
|
{ PseudoVFNMADD_VFPR16_M8, VFNMADD_VF, 0x3, 0x0 }, // 1952
|
|
{ PseudoVFNMADD_VFPR16_M8_MASK, VFNMADD_VF, 0x3, 0x0 }, // 1953
|
|
{ PseudoVFNMADD_VFPR32_M8, VFNMADD_VF, 0x3, 0x0 }, // 1954
|
|
{ PseudoVFNMADD_VFPR32_M8_MASK, VFNMADD_VF, 0x3, 0x0 }, // 1955
|
|
{ PseudoVFNMADD_VFPR64_M8, VFNMADD_VF, 0x3, 0x0 }, // 1956
|
|
{ PseudoVFNMADD_VFPR64_M8_MASK, VFNMADD_VF, 0x3, 0x0 }, // 1957
|
|
{ PseudoVFNMADD_VFPR16_MF4, VFNMADD_VF, 0x6, 0x0 }, // 1958
|
|
{ PseudoVFNMADD_VFPR16_MF4_MASK, VFNMADD_VF, 0x6, 0x0 }, // 1959
|
|
{ PseudoVFNMADD_VFPR16_MF2, VFNMADD_VF, 0x7, 0x0 }, // 1960
|
|
{ PseudoVFNMADD_VFPR16_MF2_MASK, VFNMADD_VF, 0x7, 0x0 }, // 1961
|
|
{ PseudoVFNMADD_VFPR32_MF2, VFNMADD_VF, 0x7, 0x0 }, // 1962
|
|
{ PseudoVFNMADD_VFPR32_MF2_MASK, VFNMADD_VF, 0x7, 0x0 }, // 1963
|
|
{ PseudoVFNMADD_VV_M1, VFNMADD_VV, 0x0, 0x0 }, // 1964
|
|
{ PseudoVFNMADD_VV_M1_MASK, VFNMADD_VV, 0x0, 0x0 }, // 1965
|
|
{ PseudoVFNMADD_VV_M2, VFNMADD_VV, 0x1, 0x0 }, // 1966
|
|
{ PseudoVFNMADD_VV_M2_MASK, VFNMADD_VV, 0x1, 0x0 }, // 1967
|
|
{ PseudoVFNMADD_VV_M4, VFNMADD_VV, 0x2, 0x0 }, // 1968
|
|
{ PseudoVFNMADD_VV_M4_MASK, VFNMADD_VV, 0x2, 0x0 }, // 1969
|
|
{ PseudoVFNMADD_VV_M8, VFNMADD_VV, 0x3, 0x0 }, // 1970
|
|
{ PseudoVFNMADD_VV_M8_MASK, VFNMADD_VV, 0x3, 0x0 }, // 1971
|
|
{ PseudoVFNMADD_VV_MF4, VFNMADD_VV, 0x6, 0x0 }, // 1972
|
|
{ PseudoVFNMADD_VV_MF4_MASK, VFNMADD_VV, 0x6, 0x0 }, // 1973
|
|
{ PseudoVFNMADD_VV_MF2, VFNMADD_VV, 0x7, 0x0 }, // 1974
|
|
{ PseudoVFNMADD_VV_MF2_MASK, VFNMADD_VV, 0x7, 0x0 }, // 1975
|
|
{ PseudoVFNMSAC_VFPR16_M1, VFNMSAC_VF, 0x0, 0x0 }, // 1976
|
|
{ PseudoVFNMSAC_VFPR16_M1_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 1977
|
|
{ PseudoVFNMSAC_VFPR32_M1, VFNMSAC_VF, 0x0, 0x0 }, // 1978
|
|
{ PseudoVFNMSAC_VFPR32_M1_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 1979
|
|
{ PseudoVFNMSAC_VFPR64_M1, VFNMSAC_VF, 0x0, 0x0 }, // 1980
|
|
{ PseudoVFNMSAC_VFPR64_M1_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 1981
|
|
{ PseudoVFNMSAC_VFPR16_M2, VFNMSAC_VF, 0x1, 0x0 }, // 1982
|
|
{ PseudoVFNMSAC_VFPR16_M2_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 1983
|
|
{ PseudoVFNMSAC_VFPR32_M2, VFNMSAC_VF, 0x1, 0x0 }, // 1984
|
|
{ PseudoVFNMSAC_VFPR32_M2_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 1985
|
|
{ PseudoVFNMSAC_VFPR64_M2, VFNMSAC_VF, 0x1, 0x0 }, // 1986
|
|
{ PseudoVFNMSAC_VFPR64_M2_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 1987
|
|
{ PseudoVFNMSAC_VFPR16_M4, VFNMSAC_VF, 0x2, 0x0 }, // 1988
|
|
{ PseudoVFNMSAC_VFPR16_M4_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 1989
|
|
{ PseudoVFNMSAC_VFPR32_M4, VFNMSAC_VF, 0x2, 0x0 }, // 1990
|
|
{ PseudoVFNMSAC_VFPR32_M4_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 1991
|
|
{ PseudoVFNMSAC_VFPR64_M4, VFNMSAC_VF, 0x2, 0x0 }, // 1992
|
|
{ PseudoVFNMSAC_VFPR64_M4_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 1993
|
|
{ PseudoVFNMSAC_VFPR16_M8, VFNMSAC_VF, 0x3, 0x0 }, // 1994
|
|
{ PseudoVFNMSAC_VFPR16_M8_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 1995
|
|
{ PseudoVFNMSAC_VFPR32_M8, VFNMSAC_VF, 0x3, 0x0 }, // 1996
|
|
{ PseudoVFNMSAC_VFPR32_M8_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 1997
|
|
{ PseudoVFNMSAC_VFPR64_M8, VFNMSAC_VF, 0x3, 0x0 }, // 1998
|
|
{ PseudoVFNMSAC_VFPR64_M8_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 1999
|
|
{ PseudoVFNMSAC_VFPR16_MF4, VFNMSAC_VF, 0x6, 0x0 }, // 2000
|
|
{ PseudoVFNMSAC_VFPR16_MF4_MASK, VFNMSAC_VF, 0x6, 0x0 }, // 2001
|
|
{ PseudoVFNMSAC_VFPR16_MF2, VFNMSAC_VF, 0x7, 0x0 }, // 2002
|
|
{ PseudoVFNMSAC_VFPR16_MF2_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2003
|
|
{ PseudoVFNMSAC_VFPR32_MF2, VFNMSAC_VF, 0x7, 0x0 }, // 2004
|
|
{ PseudoVFNMSAC_VFPR32_MF2_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2005
|
|
{ PseudoVFNMSAC_VV_M1, VFNMSAC_VV, 0x0, 0x0 }, // 2006
|
|
{ PseudoVFNMSAC_VV_M1_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2007
|
|
{ PseudoVFNMSAC_VV_M2, VFNMSAC_VV, 0x1, 0x0 }, // 2008
|
|
{ PseudoVFNMSAC_VV_M2_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2009
|
|
{ PseudoVFNMSAC_VV_M4, VFNMSAC_VV, 0x2, 0x0 }, // 2010
|
|
{ PseudoVFNMSAC_VV_M4_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2011
|
|
{ PseudoVFNMSAC_VV_M8, VFNMSAC_VV, 0x3, 0x0 }, // 2012
|
|
{ PseudoVFNMSAC_VV_M8_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2013
|
|
{ PseudoVFNMSAC_VV_MF4, VFNMSAC_VV, 0x6, 0x0 }, // 2014
|
|
{ PseudoVFNMSAC_VV_MF4_MASK, VFNMSAC_VV, 0x6, 0x0 }, // 2015
|
|
{ PseudoVFNMSAC_VV_MF2, VFNMSAC_VV, 0x7, 0x0 }, // 2016
|
|
{ PseudoVFNMSAC_VV_MF2_MASK, VFNMSAC_VV, 0x7, 0x0 }, // 2017
|
|
{ PseudoVFNMSUB_VFPR16_M1, VFNMSUB_VF, 0x0, 0x0 }, // 2018
|
|
{ PseudoVFNMSUB_VFPR16_M1_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2019
|
|
{ PseudoVFNMSUB_VFPR32_M1, VFNMSUB_VF, 0x0, 0x0 }, // 2020
|
|
{ PseudoVFNMSUB_VFPR32_M1_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2021
|
|
{ PseudoVFNMSUB_VFPR64_M1, VFNMSUB_VF, 0x0, 0x0 }, // 2022
|
|
{ PseudoVFNMSUB_VFPR64_M1_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2023
|
|
{ PseudoVFNMSUB_VFPR16_M2, VFNMSUB_VF, 0x1, 0x0 }, // 2024
|
|
{ PseudoVFNMSUB_VFPR16_M2_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2025
|
|
{ PseudoVFNMSUB_VFPR32_M2, VFNMSUB_VF, 0x1, 0x0 }, // 2026
|
|
{ PseudoVFNMSUB_VFPR32_M2_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2027
|
|
{ PseudoVFNMSUB_VFPR64_M2, VFNMSUB_VF, 0x1, 0x0 }, // 2028
|
|
{ PseudoVFNMSUB_VFPR64_M2_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2029
|
|
{ PseudoVFNMSUB_VFPR16_M4, VFNMSUB_VF, 0x2, 0x0 }, // 2030
|
|
{ PseudoVFNMSUB_VFPR16_M4_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2031
|
|
{ PseudoVFNMSUB_VFPR32_M4, VFNMSUB_VF, 0x2, 0x0 }, // 2032
|
|
{ PseudoVFNMSUB_VFPR32_M4_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2033
|
|
{ PseudoVFNMSUB_VFPR64_M4, VFNMSUB_VF, 0x2, 0x0 }, // 2034
|
|
{ PseudoVFNMSUB_VFPR64_M4_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2035
|
|
{ PseudoVFNMSUB_VFPR16_M8, VFNMSUB_VF, 0x3, 0x0 }, // 2036
|
|
{ PseudoVFNMSUB_VFPR16_M8_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2037
|
|
{ PseudoVFNMSUB_VFPR32_M8, VFNMSUB_VF, 0x3, 0x0 }, // 2038
|
|
{ PseudoVFNMSUB_VFPR32_M8_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2039
|
|
{ PseudoVFNMSUB_VFPR64_M8, VFNMSUB_VF, 0x3, 0x0 }, // 2040
|
|
{ PseudoVFNMSUB_VFPR64_M8_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2041
|
|
{ PseudoVFNMSUB_VFPR16_MF4, VFNMSUB_VF, 0x6, 0x0 }, // 2042
|
|
{ PseudoVFNMSUB_VFPR16_MF4_MASK, VFNMSUB_VF, 0x6, 0x0 }, // 2043
|
|
{ PseudoVFNMSUB_VFPR16_MF2, VFNMSUB_VF, 0x7, 0x0 }, // 2044
|
|
{ PseudoVFNMSUB_VFPR16_MF2_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2045
|
|
{ PseudoVFNMSUB_VFPR32_MF2, VFNMSUB_VF, 0x7, 0x0 }, // 2046
|
|
{ PseudoVFNMSUB_VFPR32_MF2_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2047
|
|
{ PseudoVFNMSUB_VV_M1, VFNMSUB_VV, 0x0, 0x0 }, // 2048
|
|
{ PseudoVFNMSUB_VV_M1_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2049
|
|
{ PseudoVFNMSUB_VV_M2, VFNMSUB_VV, 0x1, 0x0 }, // 2050
|
|
{ PseudoVFNMSUB_VV_M2_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2051
|
|
{ PseudoVFNMSUB_VV_M4, VFNMSUB_VV, 0x2, 0x0 }, // 2052
|
|
{ PseudoVFNMSUB_VV_M4_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2053
|
|
{ PseudoVFNMSUB_VV_M8, VFNMSUB_VV, 0x3, 0x0 }, // 2054
|
|
{ PseudoVFNMSUB_VV_M8_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2055
|
|
{ PseudoVFNMSUB_VV_MF4, VFNMSUB_VV, 0x6, 0x0 }, // 2056
|
|
{ PseudoVFNMSUB_VV_MF4_MASK, VFNMSUB_VV, 0x6, 0x0 }, // 2057
|
|
{ PseudoVFNMSUB_VV_MF2, VFNMSUB_VV, 0x7, 0x0 }, // 2058
|
|
{ PseudoVFNMSUB_VV_MF2_MASK, VFNMSUB_VV, 0x7, 0x0 }, // 2059
|
|
{ PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2060
|
|
{ PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2061
|
|
{ PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2062
|
|
{ PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2063
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2064
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2065
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2066
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2067
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2068
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2069
|
|
{ PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2070
|
|
{ PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2071
|
|
{ PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2072
|
|
{ PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2073
|
|
{ PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2074
|
|
{ PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2075
|
|
{ PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2076
|
|
{ PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2077
|
|
{ PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2078
|
|
{ PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2079
|
|
{ PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF, 0x0, 0x10 }, // 2080
|
|
{ PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF, 0x0, 0x10 }, // 2081
|
|
{ PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF, 0x0, 0x20 }, // 2082
|
|
{ PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF, 0x0, 0x20 }, // 2083
|
|
{ PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF, 0x0, 0x40 }, // 2084
|
|
{ PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF, 0x0, 0x40 }, // 2085
|
|
{ PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF, 0x1, 0x10 }, // 2086
|
|
{ PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF, 0x1, 0x10 }, // 2087
|
|
{ PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF, 0x1, 0x20 }, // 2088
|
|
{ PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF, 0x1, 0x20 }, // 2089
|
|
{ PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF, 0x1, 0x40 }, // 2090
|
|
{ PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF, 0x1, 0x40 }, // 2091
|
|
{ PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF, 0x2, 0x10 }, // 2092
|
|
{ PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF, 0x2, 0x10 }, // 2093
|
|
{ PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF, 0x2, 0x20 }, // 2094
|
|
{ PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF, 0x2, 0x20 }, // 2095
|
|
{ PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF, 0x2, 0x40 }, // 2096
|
|
{ PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF, 0x2, 0x40 }, // 2097
|
|
{ PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF, 0x3, 0x10 }, // 2098
|
|
{ PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF, 0x3, 0x10 }, // 2099
|
|
{ PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF, 0x3, 0x20 }, // 2100
|
|
{ PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF, 0x3, 0x20 }, // 2101
|
|
{ PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF, 0x3, 0x40 }, // 2102
|
|
{ PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF, 0x3, 0x40 }, // 2103
|
|
{ PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF, 0x6, 0x10 }, // 2104
|
|
{ PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF, 0x6, 0x10 }, // 2105
|
|
{ PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF, 0x7, 0x10 }, // 2106
|
|
{ PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF, 0x7, 0x10 }, // 2107
|
|
{ PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF, 0x7, 0x20 }, // 2108
|
|
{ PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF, 0x7, 0x20 }, // 2109
|
|
{ PseudoVFREC7_V_M1, VFREC7_V, 0x0, 0x0 }, // 2110
|
|
{ PseudoVFREC7_V_M1_MASK, VFREC7_V, 0x0, 0x0 }, // 2111
|
|
{ PseudoVFREC7_V_M2, VFREC7_V, 0x1, 0x0 }, // 2112
|
|
{ PseudoVFREC7_V_M2_MASK, VFREC7_V, 0x1, 0x0 }, // 2113
|
|
{ PseudoVFREC7_V_M4, VFREC7_V, 0x2, 0x0 }, // 2114
|
|
{ PseudoVFREC7_V_M4_MASK, VFREC7_V, 0x2, 0x0 }, // 2115
|
|
{ PseudoVFREC7_V_M8, VFREC7_V, 0x3, 0x0 }, // 2116
|
|
{ PseudoVFREC7_V_M8_MASK, VFREC7_V, 0x3, 0x0 }, // 2117
|
|
{ PseudoVFREC7_V_MF4, VFREC7_V, 0x6, 0x0 }, // 2118
|
|
{ PseudoVFREC7_V_MF4_MASK, VFREC7_V, 0x6, 0x0 }, // 2119
|
|
{ PseudoVFREC7_V_MF2, VFREC7_V, 0x7, 0x0 }, // 2120
|
|
{ PseudoVFREC7_V_MF2_MASK, VFREC7_V, 0x7, 0x0 }, // 2121
|
|
{ PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS, 0x0, 0x10 }, // 2122
|
|
{ PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS, 0x0, 0x10 }, // 2123
|
|
{ PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS, 0x0, 0x20 }, // 2124
|
|
{ PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS, 0x0, 0x20 }, // 2125
|
|
{ PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS, 0x0, 0x40 }, // 2126
|
|
{ PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS, 0x0, 0x40 }, // 2127
|
|
{ PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS, 0x1, 0x10 }, // 2128
|
|
{ PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS, 0x1, 0x10 }, // 2129
|
|
{ PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS, 0x1, 0x20 }, // 2130
|
|
{ PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS, 0x1, 0x20 }, // 2131
|
|
{ PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS, 0x1, 0x40 }, // 2132
|
|
{ PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS, 0x1, 0x40 }, // 2133
|
|
{ PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS, 0x2, 0x10 }, // 2134
|
|
{ PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS, 0x2, 0x10 }, // 2135
|
|
{ PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS, 0x2, 0x20 }, // 2136
|
|
{ PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS, 0x2, 0x20 }, // 2137
|
|
{ PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS, 0x2, 0x40 }, // 2138
|
|
{ PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS, 0x2, 0x40 }, // 2139
|
|
{ PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS, 0x3, 0x10 }, // 2140
|
|
{ PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS, 0x3, 0x10 }, // 2141
|
|
{ PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS, 0x3, 0x20 }, // 2142
|
|
{ PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS, 0x3, 0x20 }, // 2143
|
|
{ PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS, 0x3, 0x40 }, // 2144
|
|
{ PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS, 0x3, 0x40 }, // 2145
|
|
{ PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS, 0x6, 0x10 }, // 2146
|
|
{ PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS, 0x6, 0x10 }, // 2147
|
|
{ PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS, 0x7, 0x10 }, // 2148
|
|
{ PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS, 0x7, 0x10 }, // 2149
|
|
{ PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS, 0x7, 0x20 }, // 2150
|
|
{ PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS, 0x7, 0x20 }, // 2151
|
|
{ PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS, 0x0, 0x10 }, // 2152
|
|
{ PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS, 0x0, 0x10 }, // 2153
|
|
{ PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS, 0x0, 0x20 }, // 2154
|
|
{ PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS, 0x0, 0x20 }, // 2155
|
|
{ PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS, 0x0, 0x40 }, // 2156
|
|
{ PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS, 0x0, 0x40 }, // 2157
|
|
{ PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS, 0x1, 0x10 }, // 2158
|
|
{ PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS, 0x1, 0x10 }, // 2159
|
|
{ PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS, 0x1, 0x20 }, // 2160
|
|
{ PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS, 0x1, 0x20 }, // 2161
|
|
{ PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS, 0x1, 0x40 }, // 2162
|
|
{ PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS, 0x1, 0x40 }, // 2163
|
|
{ PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS, 0x2, 0x10 }, // 2164
|
|
{ PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS, 0x2, 0x10 }, // 2165
|
|
{ PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS, 0x2, 0x20 }, // 2166
|
|
{ PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS, 0x2, 0x20 }, // 2167
|
|
{ PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS, 0x2, 0x40 }, // 2168
|
|
{ PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS, 0x2, 0x40 }, // 2169
|
|
{ PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS, 0x3, 0x10 }, // 2170
|
|
{ PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS, 0x3, 0x10 }, // 2171
|
|
{ PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS, 0x3, 0x20 }, // 2172
|
|
{ PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS, 0x3, 0x20 }, // 2173
|
|
{ PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS, 0x3, 0x40 }, // 2174
|
|
{ PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS, 0x3, 0x40 }, // 2175
|
|
{ PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS, 0x6, 0x10 }, // 2176
|
|
{ PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS, 0x6, 0x10 }, // 2177
|
|
{ PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS, 0x7, 0x10 }, // 2178
|
|
{ PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS, 0x7, 0x10 }, // 2179
|
|
{ PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS, 0x7, 0x20 }, // 2180
|
|
{ PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS, 0x7, 0x20 }, // 2181
|
|
{ PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS, 0x0, 0x10 }, // 2182
|
|
{ PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS, 0x0, 0x10 }, // 2183
|
|
{ PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS, 0x0, 0x20 }, // 2184
|
|
{ PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS, 0x0, 0x20 }, // 2185
|
|
{ PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS, 0x0, 0x40 }, // 2186
|
|
{ PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS, 0x0, 0x40 }, // 2187
|
|
{ PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS, 0x1, 0x10 }, // 2188
|
|
{ PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS, 0x1, 0x10 }, // 2189
|
|
{ PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS, 0x1, 0x20 }, // 2190
|
|
{ PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS, 0x1, 0x20 }, // 2191
|
|
{ PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS, 0x1, 0x40 }, // 2192
|
|
{ PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS, 0x1, 0x40 }, // 2193
|
|
{ PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS, 0x2, 0x10 }, // 2194
|
|
{ PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS, 0x2, 0x10 }, // 2195
|
|
{ PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS, 0x2, 0x20 }, // 2196
|
|
{ PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS, 0x2, 0x20 }, // 2197
|
|
{ PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS, 0x2, 0x40 }, // 2198
|
|
{ PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS, 0x2, 0x40 }, // 2199
|
|
{ PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS, 0x3, 0x10 }, // 2200
|
|
{ PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS, 0x3, 0x10 }, // 2201
|
|
{ PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS, 0x3, 0x20 }, // 2202
|
|
{ PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS, 0x3, 0x20 }, // 2203
|
|
{ PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS, 0x3, 0x40 }, // 2204
|
|
{ PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS, 0x3, 0x40 }, // 2205
|
|
{ PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS, 0x6, 0x10 }, // 2206
|
|
{ PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS, 0x6, 0x10 }, // 2207
|
|
{ PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS, 0x7, 0x10 }, // 2208
|
|
{ PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS, 0x7, 0x10 }, // 2209
|
|
{ PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS, 0x7, 0x20 }, // 2210
|
|
{ PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS, 0x7, 0x20 }, // 2211
|
|
{ PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS, 0x0, 0x10 }, // 2212
|
|
{ PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS, 0x0, 0x10 }, // 2213
|
|
{ PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS, 0x0, 0x20 }, // 2214
|
|
{ PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS, 0x0, 0x20 }, // 2215
|
|
{ PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS, 0x0, 0x40 }, // 2216
|
|
{ PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS, 0x0, 0x40 }, // 2217
|
|
{ PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS, 0x1, 0x10 }, // 2218
|
|
{ PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS, 0x1, 0x10 }, // 2219
|
|
{ PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS, 0x1, 0x20 }, // 2220
|
|
{ PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS, 0x1, 0x20 }, // 2221
|
|
{ PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS, 0x1, 0x40 }, // 2222
|
|
{ PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS, 0x1, 0x40 }, // 2223
|
|
{ PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS, 0x2, 0x10 }, // 2224
|
|
{ PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS, 0x2, 0x10 }, // 2225
|
|
{ PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS, 0x2, 0x20 }, // 2226
|
|
{ PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS, 0x2, 0x20 }, // 2227
|
|
{ PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS, 0x2, 0x40 }, // 2228
|
|
{ PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS, 0x2, 0x40 }, // 2229
|
|
{ PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS, 0x3, 0x10 }, // 2230
|
|
{ PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS, 0x3, 0x10 }, // 2231
|
|
{ PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS, 0x3, 0x20 }, // 2232
|
|
{ PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS, 0x3, 0x20 }, // 2233
|
|
{ PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS, 0x3, 0x40 }, // 2234
|
|
{ PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS, 0x3, 0x40 }, // 2235
|
|
{ PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS, 0x6, 0x10 }, // 2236
|
|
{ PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS, 0x6, 0x10 }, // 2237
|
|
{ PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS, 0x7, 0x10 }, // 2238
|
|
{ PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS, 0x7, 0x10 }, // 2239
|
|
{ PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS, 0x7, 0x20 }, // 2240
|
|
{ PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS, 0x7, 0x20 }, // 2241
|
|
{ PseudoVFRSQRT7_V_M1, VFRSQRT7_V, 0x0, 0x0 }, // 2242
|
|
{ PseudoVFRSQRT7_V_M1_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2243
|
|
{ PseudoVFRSQRT7_V_M2, VFRSQRT7_V, 0x1, 0x0 }, // 2244
|
|
{ PseudoVFRSQRT7_V_M2_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2245
|
|
{ PseudoVFRSQRT7_V_M4, VFRSQRT7_V, 0x2, 0x0 }, // 2246
|
|
{ PseudoVFRSQRT7_V_M4_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2247
|
|
{ PseudoVFRSQRT7_V_M8, VFRSQRT7_V, 0x3, 0x0 }, // 2248
|
|
{ PseudoVFRSQRT7_V_M8_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2249
|
|
{ PseudoVFRSQRT7_V_MF4, VFRSQRT7_V, 0x6, 0x0 }, // 2250
|
|
{ PseudoVFRSQRT7_V_MF4_MASK, VFRSQRT7_V, 0x6, 0x0 }, // 2251
|
|
{ PseudoVFRSQRT7_V_MF2, VFRSQRT7_V, 0x7, 0x0 }, // 2252
|
|
{ PseudoVFRSQRT7_V_MF2_MASK, VFRSQRT7_V, 0x7, 0x0 }, // 2253
|
|
{ PseudoVFRSUB_VFPR16_M1, VFRSUB_VF, 0x0, 0x0 }, // 2254
|
|
{ PseudoVFRSUB_VFPR16_M1_MASK, VFRSUB_VF, 0x0, 0x0 }, // 2255
|
|
{ PseudoVFRSUB_VFPR32_M1, VFRSUB_VF, 0x0, 0x0 }, // 2256
|
|
{ PseudoVFRSUB_VFPR32_M1_MASK, VFRSUB_VF, 0x0, 0x0 }, // 2257
|
|
{ PseudoVFRSUB_VFPR64_M1, VFRSUB_VF, 0x0, 0x0 }, // 2258
|
|
{ PseudoVFRSUB_VFPR64_M1_MASK, VFRSUB_VF, 0x0, 0x0 }, // 2259
|
|
{ PseudoVFRSUB_VFPR16_M2, VFRSUB_VF, 0x1, 0x0 }, // 2260
|
|
{ PseudoVFRSUB_VFPR16_M2_MASK, VFRSUB_VF, 0x1, 0x0 }, // 2261
|
|
{ PseudoVFRSUB_VFPR32_M2, VFRSUB_VF, 0x1, 0x0 }, // 2262
|
|
{ PseudoVFRSUB_VFPR32_M2_MASK, VFRSUB_VF, 0x1, 0x0 }, // 2263
|
|
{ PseudoVFRSUB_VFPR64_M2, VFRSUB_VF, 0x1, 0x0 }, // 2264
|
|
{ PseudoVFRSUB_VFPR64_M2_MASK, VFRSUB_VF, 0x1, 0x0 }, // 2265
|
|
{ PseudoVFRSUB_VFPR16_M4, VFRSUB_VF, 0x2, 0x0 }, // 2266
|
|
{ PseudoVFRSUB_VFPR16_M4_MASK, VFRSUB_VF, 0x2, 0x0 }, // 2267
|
|
{ PseudoVFRSUB_VFPR32_M4, VFRSUB_VF, 0x2, 0x0 }, // 2268
|
|
{ PseudoVFRSUB_VFPR32_M4_MASK, VFRSUB_VF, 0x2, 0x0 }, // 2269
|
|
{ PseudoVFRSUB_VFPR64_M4, VFRSUB_VF, 0x2, 0x0 }, // 2270
|
|
{ PseudoVFRSUB_VFPR64_M4_MASK, VFRSUB_VF, 0x2, 0x0 }, // 2271
|
|
{ PseudoVFRSUB_VFPR16_M8, VFRSUB_VF, 0x3, 0x0 }, // 2272
|
|
{ PseudoVFRSUB_VFPR16_M8_MASK, VFRSUB_VF, 0x3, 0x0 }, // 2273
|
|
{ PseudoVFRSUB_VFPR32_M8, VFRSUB_VF, 0x3, 0x0 }, // 2274
|
|
{ PseudoVFRSUB_VFPR32_M8_MASK, VFRSUB_VF, 0x3, 0x0 }, // 2275
|
|
{ PseudoVFRSUB_VFPR64_M8, VFRSUB_VF, 0x3, 0x0 }, // 2276
|
|
{ PseudoVFRSUB_VFPR64_M8_MASK, VFRSUB_VF, 0x3, 0x0 }, // 2277
|
|
{ PseudoVFRSUB_VFPR16_MF4, VFRSUB_VF, 0x6, 0x0 }, // 2278
|
|
{ PseudoVFRSUB_VFPR16_MF4_MASK, VFRSUB_VF, 0x6, 0x0 }, // 2279
|
|
{ PseudoVFRSUB_VFPR16_MF2, VFRSUB_VF, 0x7, 0x0 }, // 2280
|
|
{ PseudoVFRSUB_VFPR16_MF2_MASK, VFRSUB_VF, 0x7, 0x0 }, // 2281
|
|
{ PseudoVFRSUB_VFPR32_MF2, VFRSUB_VF, 0x7, 0x0 }, // 2282
|
|
{ PseudoVFRSUB_VFPR32_MF2_MASK, VFRSUB_VF, 0x7, 0x0 }, // 2283
|
|
{ PseudoVFSGNJN_VFPR16_M1, VFSGNJN_VF, 0x0, 0x0 }, // 2284
|
|
{ PseudoVFSGNJN_VFPR16_M1_MASK, VFSGNJN_VF, 0x0, 0x0 }, // 2285
|
|
{ PseudoVFSGNJN_VFPR32_M1, VFSGNJN_VF, 0x0, 0x0 }, // 2286
|
|
{ PseudoVFSGNJN_VFPR32_M1_MASK, VFSGNJN_VF, 0x0, 0x0 }, // 2287
|
|
{ PseudoVFSGNJN_VFPR64_M1, VFSGNJN_VF, 0x0, 0x0 }, // 2288
|
|
{ PseudoVFSGNJN_VFPR64_M1_MASK, VFSGNJN_VF, 0x0, 0x0 }, // 2289
|
|
{ PseudoVFSGNJN_VFPR16_M2, VFSGNJN_VF, 0x1, 0x0 }, // 2290
|
|
{ PseudoVFSGNJN_VFPR16_M2_MASK, VFSGNJN_VF, 0x1, 0x0 }, // 2291
|
|
{ PseudoVFSGNJN_VFPR32_M2, VFSGNJN_VF, 0x1, 0x0 }, // 2292
|
|
{ PseudoVFSGNJN_VFPR32_M2_MASK, VFSGNJN_VF, 0x1, 0x0 }, // 2293
|
|
{ PseudoVFSGNJN_VFPR64_M2, VFSGNJN_VF, 0x1, 0x0 }, // 2294
|
|
{ PseudoVFSGNJN_VFPR64_M2_MASK, VFSGNJN_VF, 0x1, 0x0 }, // 2295
|
|
{ PseudoVFSGNJN_VFPR16_M4, VFSGNJN_VF, 0x2, 0x0 }, // 2296
|
|
{ PseudoVFSGNJN_VFPR16_M4_MASK, VFSGNJN_VF, 0x2, 0x0 }, // 2297
|
|
{ PseudoVFSGNJN_VFPR32_M4, VFSGNJN_VF, 0x2, 0x0 }, // 2298
|
|
{ PseudoVFSGNJN_VFPR32_M4_MASK, VFSGNJN_VF, 0x2, 0x0 }, // 2299
|
|
{ PseudoVFSGNJN_VFPR64_M4, VFSGNJN_VF, 0x2, 0x0 }, // 2300
|
|
{ PseudoVFSGNJN_VFPR64_M4_MASK, VFSGNJN_VF, 0x2, 0x0 }, // 2301
|
|
{ PseudoVFSGNJN_VFPR16_M8, VFSGNJN_VF, 0x3, 0x0 }, // 2302
|
|
{ PseudoVFSGNJN_VFPR16_M8_MASK, VFSGNJN_VF, 0x3, 0x0 }, // 2303
|
|
{ PseudoVFSGNJN_VFPR32_M8, VFSGNJN_VF, 0x3, 0x0 }, // 2304
|
|
{ PseudoVFSGNJN_VFPR32_M8_MASK, VFSGNJN_VF, 0x3, 0x0 }, // 2305
|
|
{ PseudoVFSGNJN_VFPR64_M8, VFSGNJN_VF, 0x3, 0x0 }, // 2306
|
|
{ PseudoVFSGNJN_VFPR64_M8_MASK, VFSGNJN_VF, 0x3, 0x0 }, // 2307
|
|
{ PseudoVFSGNJN_VFPR16_MF4, VFSGNJN_VF, 0x6, 0x0 }, // 2308
|
|
{ PseudoVFSGNJN_VFPR16_MF4_MASK, VFSGNJN_VF, 0x6, 0x0 }, // 2309
|
|
{ PseudoVFSGNJN_VFPR16_MF2, VFSGNJN_VF, 0x7, 0x0 }, // 2310
|
|
{ PseudoVFSGNJN_VFPR16_MF2_MASK, VFSGNJN_VF, 0x7, 0x0 }, // 2311
|
|
{ PseudoVFSGNJN_VFPR32_MF2, VFSGNJN_VF, 0x7, 0x0 }, // 2312
|
|
{ PseudoVFSGNJN_VFPR32_MF2_MASK, VFSGNJN_VF, 0x7, 0x0 }, // 2313
|
|
{ PseudoVFSGNJN_VV_M1, VFSGNJN_VV, 0x0, 0x0 }, // 2314
|
|
{ PseudoVFSGNJN_VV_M1_MASK, VFSGNJN_VV, 0x0, 0x0 }, // 2315
|
|
{ PseudoVFSGNJN_VV_M2, VFSGNJN_VV, 0x1, 0x0 }, // 2316
|
|
{ PseudoVFSGNJN_VV_M2_MASK, VFSGNJN_VV, 0x1, 0x0 }, // 2317
|
|
{ PseudoVFSGNJN_VV_M4, VFSGNJN_VV, 0x2, 0x0 }, // 2318
|
|
{ PseudoVFSGNJN_VV_M4_MASK, VFSGNJN_VV, 0x2, 0x0 }, // 2319
|
|
{ PseudoVFSGNJN_VV_M8, VFSGNJN_VV, 0x3, 0x0 }, // 2320
|
|
{ PseudoVFSGNJN_VV_M8_MASK, VFSGNJN_VV, 0x3, 0x0 }, // 2321
|
|
{ PseudoVFSGNJN_VV_MF4, VFSGNJN_VV, 0x6, 0x0 }, // 2322
|
|
{ PseudoVFSGNJN_VV_MF4_MASK, VFSGNJN_VV, 0x6, 0x0 }, // 2323
|
|
{ PseudoVFSGNJN_VV_MF2, VFSGNJN_VV, 0x7, 0x0 }, // 2324
|
|
{ PseudoVFSGNJN_VV_MF2_MASK, VFSGNJN_VV, 0x7, 0x0 }, // 2325
|
|
{ PseudoVFSGNJX_VFPR16_M1, VFSGNJX_VF, 0x0, 0x0 }, // 2326
|
|
{ PseudoVFSGNJX_VFPR16_M1_MASK, VFSGNJX_VF, 0x0, 0x0 }, // 2327
|
|
{ PseudoVFSGNJX_VFPR32_M1, VFSGNJX_VF, 0x0, 0x0 }, // 2328
|
|
{ PseudoVFSGNJX_VFPR32_M1_MASK, VFSGNJX_VF, 0x0, 0x0 }, // 2329
|
|
{ PseudoVFSGNJX_VFPR64_M1, VFSGNJX_VF, 0x0, 0x0 }, // 2330
|
|
{ PseudoVFSGNJX_VFPR64_M1_MASK, VFSGNJX_VF, 0x0, 0x0 }, // 2331
|
|
{ PseudoVFSGNJX_VFPR16_M2, VFSGNJX_VF, 0x1, 0x0 }, // 2332
|
|
{ PseudoVFSGNJX_VFPR16_M2_MASK, VFSGNJX_VF, 0x1, 0x0 }, // 2333
|
|
{ PseudoVFSGNJX_VFPR32_M2, VFSGNJX_VF, 0x1, 0x0 }, // 2334
|
|
{ PseudoVFSGNJX_VFPR32_M2_MASK, VFSGNJX_VF, 0x1, 0x0 }, // 2335
|
|
{ PseudoVFSGNJX_VFPR64_M2, VFSGNJX_VF, 0x1, 0x0 }, // 2336
|
|
{ PseudoVFSGNJX_VFPR64_M2_MASK, VFSGNJX_VF, 0x1, 0x0 }, // 2337
|
|
{ PseudoVFSGNJX_VFPR16_M4, VFSGNJX_VF, 0x2, 0x0 }, // 2338
|
|
{ PseudoVFSGNJX_VFPR16_M4_MASK, VFSGNJX_VF, 0x2, 0x0 }, // 2339
|
|
{ PseudoVFSGNJX_VFPR32_M4, VFSGNJX_VF, 0x2, 0x0 }, // 2340
|
|
{ PseudoVFSGNJX_VFPR32_M4_MASK, VFSGNJX_VF, 0x2, 0x0 }, // 2341
|
|
{ PseudoVFSGNJX_VFPR64_M4, VFSGNJX_VF, 0x2, 0x0 }, // 2342
|
|
{ PseudoVFSGNJX_VFPR64_M4_MASK, VFSGNJX_VF, 0x2, 0x0 }, // 2343
|
|
{ PseudoVFSGNJX_VFPR16_M8, VFSGNJX_VF, 0x3, 0x0 }, // 2344
|
|
{ PseudoVFSGNJX_VFPR16_M8_MASK, VFSGNJX_VF, 0x3, 0x0 }, // 2345
|
|
{ PseudoVFSGNJX_VFPR32_M8, VFSGNJX_VF, 0x3, 0x0 }, // 2346
|
|
{ PseudoVFSGNJX_VFPR32_M8_MASK, VFSGNJX_VF, 0x3, 0x0 }, // 2347
|
|
{ PseudoVFSGNJX_VFPR64_M8, VFSGNJX_VF, 0x3, 0x0 }, // 2348
|
|
{ PseudoVFSGNJX_VFPR64_M8_MASK, VFSGNJX_VF, 0x3, 0x0 }, // 2349
|
|
{ PseudoVFSGNJX_VFPR16_MF4, VFSGNJX_VF, 0x6, 0x0 }, // 2350
|
|
{ PseudoVFSGNJX_VFPR16_MF4_MASK, VFSGNJX_VF, 0x6, 0x0 }, // 2351
|
|
{ PseudoVFSGNJX_VFPR16_MF2, VFSGNJX_VF, 0x7, 0x0 }, // 2352
|
|
{ PseudoVFSGNJX_VFPR16_MF2_MASK, VFSGNJX_VF, 0x7, 0x0 }, // 2353
|
|
{ PseudoVFSGNJX_VFPR32_MF2, VFSGNJX_VF, 0x7, 0x0 }, // 2354
|
|
{ PseudoVFSGNJX_VFPR32_MF2_MASK, VFSGNJX_VF, 0x7, 0x0 }, // 2355
|
|
{ PseudoVFSGNJX_VV_M1, VFSGNJX_VV, 0x0, 0x0 }, // 2356
|
|
{ PseudoVFSGNJX_VV_M1_MASK, VFSGNJX_VV, 0x0, 0x0 }, // 2357
|
|
{ PseudoVFSGNJX_VV_M2, VFSGNJX_VV, 0x1, 0x0 }, // 2358
|
|
{ PseudoVFSGNJX_VV_M2_MASK, VFSGNJX_VV, 0x1, 0x0 }, // 2359
|
|
{ PseudoVFSGNJX_VV_M4, VFSGNJX_VV, 0x2, 0x0 }, // 2360
|
|
{ PseudoVFSGNJX_VV_M4_MASK, VFSGNJX_VV, 0x2, 0x0 }, // 2361
|
|
{ PseudoVFSGNJX_VV_M8, VFSGNJX_VV, 0x3, 0x0 }, // 2362
|
|
{ PseudoVFSGNJX_VV_M8_MASK, VFSGNJX_VV, 0x3, 0x0 }, // 2363
|
|
{ PseudoVFSGNJX_VV_MF4, VFSGNJX_VV, 0x6, 0x0 }, // 2364
|
|
{ PseudoVFSGNJX_VV_MF4_MASK, VFSGNJX_VV, 0x6, 0x0 }, // 2365
|
|
{ PseudoVFSGNJX_VV_MF2, VFSGNJX_VV, 0x7, 0x0 }, // 2366
|
|
{ PseudoVFSGNJX_VV_MF2_MASK, VFSGNJX_VV, 0x7, 0x0 }, // 2367
|
|
{ PseudoVFSGNJ_VFPR16_M1, VFSGNJ_VF, 0x0, 0x0 }, // 2368
|
|
{ PseudoVFSGNJ_VFPR16_M1_MASK, VFSGNJ_VF, 0x0, 0x0 }, // 2369
|
|
{ PseudoVFSGNJ_VFPR32_M1, VFSGNJ_VF, 0x0, 0x0 }, // 2370
|
|
{ PseudoVFSGNJ_VFPR32_M1_MASK, VFSGNJ_VF, 0x0, 0x0 }, // 2371
|
|
{ PseudoVFSGNJ_VFPR64_M1, VFSGNJ_VF, 0x0, 0x0 }, // 2372
|
|
{ PseudoVFSGNJ_VFPR64_M1_MASK, VFSGNJ_VF, 0x0, 0x0 }, // 2373
|
|
{ PseudoVFSGNJ_VFPR16_M2, VFSGNJ_VF, 0x1, 0x0 }, // 2374
|
|
{ PseudoVFSGNJ_VFPR16_M2_MASK, VFSGNJ_VF, 0x1, 0x0 }, // 2375
|
|
{ PseudoVFSGNJ_VFPR32_M2, VFSGNJ_VF, 0x1, 0x0 }, // 2376
|
|
{ PseudoVFSGNJ_VFPR32_M2_MASK, VFSGNJ_VF, 0x1, 0x0 }, // 2377
|
|
{ PseudoVFSGNJ_VFPR64_M2, VFSGNJ_VF, 0x1, 0x0 }, // 2378
|
|
{ PseudoVFSGNJ_VFPR64_M2_MASK, VFSGNJ_VF, 0x1, 0x0 }, // 2379
|
|
{ PseudoVFSGNJ_VFPR16_M4, VFSGNJ_VF, 0x2, 0x0 }, // 2380
|
|
{ PseudoVFSGNJ_VFPR16_M4_MASK, VFSGNJ_VF, 0x2, 0x0 }, // 2381
|
|
{ PseudoVFSGNJ_VFPR32_M4, VFSGNJ_VF, 0x2, 0x0 }, // 2382
|
|
{ PseudoVFSGNJ_VFPR32_M4_MASK, VFSGNJ_VF, 0x2, 0x0 }, // 2383
|
|
{ PseudoVFSGNJ_VFPR64_M4, VFSGNJ_VF, 0x2, 0x0 }, // 2384
|
|
{ PseudoVFSGNJ_VFPR64_M4_MASK, VFSGNJ_VF, 0x2, 0x0 }, // 2385
|
|
{ PseudoVFSGNJ_VFPR16_M8, VFSGNJ_VF, 0x3, 0x0 }, // 2386
|
|
{ PseudoVFSGNJ_VFPR16_M8_MASK, VFSGNJ_VF, 0x3, 0x0 }, // 2387
|
|
{ PseudoVFSGNJ_VFPR32_M8, VFSGNJ_VF, 0x3, 0x0 }, // 2388
|
|
{ PseudoVFSGNJ_VFPR32_M8_MASK, VFSGNJ_VF, 0x3, 0x0 }, // 2389
|
|
{ PseudoVFSGNJ_VFPR64_M8, VFSGNJ_VF, 0x3, 0x0 }, // 2390
|
|
{ PseudoVFSGNJ_VFPR64_M8_MASK, VFSGNJ_VF, 0x3, 0x0 }, // 2391
|
|
{ PseudoVFSGNJ_VFPR16_MF4, VFSGNJ_VF, 0x6, 0x0 }, // 2392
|
|
{ PseudoVFSGNJ_VFPR16_MF4_MASK, VFSGNJ_VF, 0x6, 0x0 }, // 2393
|
|
{ PseudoVFSGNJ_VFPR16_MF2, VFSGNJ_VF, 0x7, 0x0 }, // 2394
|
|
{ PseudoVFSGNJ_VFPR16_MF2_MASK, VFSGNJ_VF, 0x7, 0x0 }, // 2395
|
|
{ PseudoVFSGNJ_VFPR32_MF2, VFSGNJ_VF, 0x7, 0x0 }, // 2396
|
|
{ PseudoVFSGNJ_VFPR32_MF2_MASK, VFSGNJ_VF, 0x7, 0x0 }, // 2397
|
|
{ PseudoVFSGNJ_VV_M1, VFSGNJ_VV, 0x0, 0x0 }, // 2398
|
|
{ PseudoVFSGNJ_VV_M1_MASK, VFSGNJ_VV, 0x0, 0x0 }, // 2399
|
|
{ PseudoVFSGNJ_VV_M2, VFSGNJ_VV, 0x1, 0x0 }, // 2400
|
|
{ PseudoVFSGNJ_VV_M2_MASK, VFSGNJ_VV, 0x1, 0x0 }, // 2401
|
|
{ PseudoVFSGNJ_VV_M4, VFSGNJ_VV, 0x2, 0x0 }, // 2402
|
|
{ PseudoVFSGNJ_VV_M4_MASK, VFSGNJ_VV, 0x2, 0x0 }, // 2403
|
|
{ PseudoVFSGNJ_VV_M8, VFSGNJ_VV, 0x3, 0x0 }, // 2404
|
|
{ PseudoVFSGNJ_VV_M8_MASK, VFSGNJ_VV, 0x3, 0x0 }, // 2405
|
|
{ PseudoVFSGNJ_VV_MF4, VFSGNJ_VV, 0x6, 0x0 }, // 2406
|
|
{ PseudoVFSGNJ_VV_MF4_MASK, VFSGNJ_VV, 0x6, 0x0 }, // 2407
|
|
{ PseudoVFSGNJ_VV_MF2, VFSGNJ_VV, 0x7, 0x0 }, // 2408
|
|
{ PseudoVFSGNJ_VV_MF2_MASK, VFSGNJ_VV, 0x7, 0x0 }, // 2409
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2410
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2411
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2412
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2413
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2414
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2415
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2416
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2417
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2418
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2419
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2420
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2421
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2422
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2423
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2424
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2425
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2426
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2427
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2428
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2429
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2430
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2431
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2432
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2433
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2434
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2435
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2436
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2437
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2438
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2439
|
|
{ PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2440
|
|
{ PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2441
|
|
{ PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2442
|
|
{ PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2443
|
|
{ PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2444
|
|
{ PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2445
|
|
{ PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2446
|
|
{ PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2447
|
|
{ PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2448
|
|
{ PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2449
|
|
{ PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2450
|
|
{ PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2451
|
|
{ PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2452
|
|
{ PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2453
|
|
{ PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2454
|
|
{ PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2455
|
|
{ PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2456
|
|
{ PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2457
|
|
{ PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2458
|
|
{ PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2459
|
|
{ PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2460
|
|
{ PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2461
|
|
{ PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2462
|
|
{ PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2463
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2464
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2465
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2466
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2467
|
|
{ PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2468
|
|
{ PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2469
|
|
{ PseudoVFSQRT_V_M1_E16, VFSQRT_V, 0x0, 0x10 }, // 2470
|
|
{ PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V, 0x0, 0x10 }, // 2471
|
|
{ PseudoVFSQRT_V_M1_E32, VFSQRT_V, 0x0, 0x20 }, // 2472
|
|
{ PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V, 0x0, 0x20 }, // 2473
|
|
{ PseudoVFSQRT_V_M1_E64, VFSQRT_V, 0x0, 0x40 }, // 2474
|
|
{ PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V, 0x0, 0x40 }, // 2475
|
|
{ PseudoVFSQRT_V_M2_E16, VFSQRT_V, 0x1, 0x10 }, // 2476
|
|
{ PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V, 0x1, 0x10 }, // 2477
|
|
{ PseudoVFSQRT_V_M2_E32, VFSQRT_V, 0x1, 0x20 }, // 2478
|
|
{ PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V, 0x1, 0x20 }, // 2479
|
|
{ PseudoVFSQRT_V_M2_E64, VFSQRT_V, 0x1, 0x40 }, // 2480
|
|
{ PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V, 0x1, 0x40 }, // 2481
|
|
{ PseudoVFSQRT_V_M4_E16, VFSQRT_V, 0x2, 0x10 }, // 2482
|
|
{ PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V, 0x2, 0x10 }, // 2483
|
|
{ PseudoVFSQRT_V_M4_E32, VFSQRT_V, 0x2, 0x20 }, // 2484
|
|
{ PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V, 0x2, 0x20 }, // 2485
|
|
{ PseudoVFSQRT_V_M4_E64, VFSQRT_V, 0x2, 0x40 }, // 2486
|
|
{ PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V, 0x2, 0x40 }, // 2487
|
|
{ PseudoVFSQRT_V_M8_E16, VFSQRT_V, 0x3, 0x10 }, // 2488
|
|
{ PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V, 0x3, 0x10 }, // 2489
|
|
{ PseudoVFSQRT_V_M8_E32, VFSQRT_V, 0x3, 0x20 }, // 2490
|
|
{ PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V, 0x3, 0x20 }, // 2491
|
|
{ PseudoVFSQRT_V_M8_E64, VFSQRT_V, 0x3, 0x40 }, // 2492
|
|
{ PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V, 0x3, 0x40 }, // 2493
|
|
{ PseudoVFSQRT_V_MF4_E16, VFSQRT_V, 0x6, 0x10 }, // 2494
|
|
{ PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V, 0x6, 0x10 }, // 2495
|
|
{ PseudoVFSQRT_V_MF2_E16, VFSQRT_V, 0x7, 0x10 }, // 2496
|
|
{ PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V, 0x7, 0x10 }, // 2497
|
|
{ PseudoVFSQRT_V_MF2_E32, VFSQRT_V, 0x7, 0x20 }, // 2498
|
|
{ PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V, 0x7, 0x20 }, // 2499
|
|
{ PseudoVFSUB_VFPR16_M1, VFSUB_VF, 0x0, 0x0 }, // 2500
|
|
{ PseudoVFSUB_VFPR16_M1_MASK, VFSUB_VF, 0x0, 0x0 }, // 2501
|
|
{ PseudoVFSUB_VFPR32_M1, VFSUB_VF, 0x0, 0x0 }, // 2502
|
|
{ PseudoVFSUB_VFPR32_M1_MASK, VFSUB_VF, 0x0, 0x0 }, // 2503
|
|
{ PseudoVFSUB_VFPR64_M1, VFSUB_VF, 0x0, 0x0 }, // 2504
|
|
{ PseudoVFSUB_VFPR64_M1_MASK, VFSUB_VF, 0x0, 0x0 }, // 2505
|
|
{ PseudoVFSUB_VFPR16_M2, VFSUB_VF, 0x1, 0x0 }, // 2506
|
|
{ PseudoVFSUB_VFPR16_M2_MASK, VFSUB_VF, 0x1, 0x0 }, // 2507
|
|
{ PseudoVFSUB_VFPR32_M2, VFSUB_VF, 0x1, 0x0 }, // 2508
|
|
{ PseudoVFSUB_VFPR32_M2_MASK, VFSUB_VF, 0x1, 0x0 }, // 2509
|
|
{ PseudoVFSUB_VFPR64_M2, VFSUB_VF, 0x1, 0x0 }, // 2510
|
|
{ PseudoVFSUB_VFPR64_M2_MASK, VFSUB_VF, 0x1, 0x0 }, // 2511
|
|
{ PseudoVFSUB_VFPR16_M4, VFSUB_VF, 0x2, 0x0 }, // 2512
|
|
{ PseudoVFSUB_VFPR16_M4_MASK, VFSUB_VF, 0x2, 0x0 }, // 2513
|
|
{ PseudoVFSUB_VFPR32_M4, VFSUB_VF, 0x2, 0x0 }, // 2514
|
|
{ PseudoVFSUB_VFPR32_M4_MASK, VFSUB_VF, 0x2, 0x0 }, // 2515
|
|
{ PseudoVFSUB_VFPR64_M4, VFSUB_VF, 0x2, 0x0 }, // 2516
|
|
{ PseudoVFSUB_VFPR64_M4_MASK, VFSUB_VF, 0x2, 0x0 }, // 2517
|
|
{ PseudoVFSUB_VFPR16_M8, VFSUB_VF, 0x3, 0x0 }, // 2518
|
|
{ PseudoVFSUB_VFPR16_M8_MASK, VFSUB_VF, 0x3, 0x0 }, // 2519
|
|
{ PseudoVFSUB_VFPR32_M8, VFSUB_VF, 0x3, 0x0 }, // 2520
|
|
{ PseudoVFSUB_VFPR32_M8_MASK, VFSUB_VF, 0x3, 0x0 }, // 2521
|
|
{ PseudoVFSUB_VFPR64_M8, VFSUB_VF, 0x3, 0x0 }, // 2522
|
|
{ PseudoVFSUB_VFPR64_M8_MASK, VFSUB_VF, 0x3, 0x0 }, // 2523
|
|
{ PseudoVFSUB_VFPR16_MF4, VFSUB_VF, 0x6, 0x0 }, // 2524
|
|
{ PseudoVFSUB_VFPR16_MF4_MASK, VFSUB_VF, 0x6, 0x0 }, // 2525
|
|
{ PseudoVFSUB_VFPR16_MF2, VFSUB_VF, 0x7, 0x0 }, // 2526
|
|
{ PseudoVFSUB_VFPR16_MF2_MASK, VFSUB_VF, 0x7, 0x0 }, // 2527
|
|
{ PseudoVFSUB_VFPR32_MF2, VFSUB_VF, 0x7, 0x0 }, // 2528
|
|
{ PseudoVFSUB_VFPR32_MF2_MASK, VFSUB_VF, 0x7, 0x0 }, // 2529
|
|
{ PseudoVFSUB_VV_M1, VFSUB_VV, 0x0, 0x0 }, // 2530
|
|
{ PseudoVFSUB_VV_M1_MASK, VFSUB_VV, 0x0, 0x0 }, // 2531
|
|
{ PseudoVFSUB_VV_M2, VFSUB_VV, 0x1, 0x0 }, // 2532
|
|
{ PseudoVFSUB_VV_M2_MASK, VFSUB_VV, 0x1, 0x0 }, // 2533
|
|
{ PseudoVFSUB_VV_M4, VFSUB_VV, 0x2, 0x0 }, // 2534
|
|
{ PseudoVFSUB_VV_M4_MASK, VFSUB_VV, 0x2, 0x0 }, // 2535
|
|
{ PseudoVFSUB_VV_M8, VFSUB_VV, 0x3, 0x0 }, // 2536
|
|
{ PseudoVFSUB_VV_M8_MASK, VFSUB_VV, 0x3, 0x0 }, // 2537
|
|
{ PseudoVFSUB_VV_MF4, VFSUB_VV, 0x6, 0x0 }, // 2538
|
|
{ PseudoVFSUB_VV_MF4_MASK, VFSUB_VV, 0x6, 0x0 }, // 2539
|
|
{ PseudoVFSUB_VV_MF2, VFSUB_VV, 0x7, 0x0 }, // 2540
|
|
{ PseudoVFSUB_VV_MF2_MASK, VFSUB_VV, 0x7, 0x0 }, // 2541
|
|
{ PseudoVFWADD_VFPR16_M1, VFWADD_VF, 0x0, 0x0 }, // 2542
|
|
{ PseudoVFWADD_VFPR16_M1_MASK, VFWADD_VF, 0x0, 0x0 }, // 2543
|
|
{ PseudoVFWADD_VFPR32_M1, VFWADD_VF, 0x0, 0x0 }, // 2544
|
|
{ PseudoVFWADD_VFPR32_M1_MASK, VFWADD_VF, 0x0, 0x0 }, // 2545
|
|
{ PseudoVFWADD_VFPR16_M2, VFWADD_VF, 0x1, 0x0 }, // 2546
|
|
{ PseudoVFWADD_VFPR16_M2_MASK, VFWADD_VF, 0x1, 0x0 }, // 2547
|
|
{ PseudoVFWADD_VFPR32_M2, VFWADD_VF, 0x1, 0x0 }, // 2548
|
|
{ PseudoVFWADD_VFPR32_M2_MASK, VFWADD_VF, 0x1, 0x0 }, // 2549
|
|
{ PseudoVFWADD_VFPR16_M4, VFWADD_VF, 0x2, 0x0 }, // 2550
|
|
{ PseudoVFWADD_VFPR16_M4_MASK, VFWADD_VF, 0x2, 0x0 }, // 2551
|
|
{ PseudoVFWADD_VFPR32_M4, VFWADD_VF, 0x2, 0x0 }, // 2552
|
|
{ PseudoVFWADD_VFPR32_M4_MASK, VFWADD_VF, 0x2, 0x0 }, // 2553
|
|
{ PseudoVFWADD_VFPR16_MF4, VFWADD_VF, 0x6, 0x0 }, // 2554
|
|
{ PseudoVFWADD_VFPR16_MF4_MASK, VFWADD_VF, 0x6, 0x0 }, // 2555
|
|
{ PseudoVFWADD_VFPR16_MF2, VFWADD_VF, 0x7, 0x0 }, // 2556
|
|
{ PseudoVFWADD_VFPR16_MF2_MASK, VFWADD_VF, 0x7, 0x0 }, // 2557
|
|
{ PseudoVFWADD_VFPR32_MF2, VFWADD_VF, 0x7, 0x0 }, // 2558
|
|
{ PseudoVFWADD_VFPR32_MF2_MASK, VFWADD_VF, 0x7, 0x0 }, // 2559
|
|
{ PseudoVFWADD_VV_M1, VFWADD_VV, 0x0, 0x0 }, // 2560
|
|
{ PseudoVFWADD_VV_M1_MASK, VFWADD_VV, 0x0, 0x0 }, // 2561
|
|
{ PseudoVFWADD_VV_M2, VFWADD_VV, 0x1, 0x0 }, // 2562
|
|
{ PseudoVFWADD_VV_M2_MASK, VFWADD_VV, 0x1, 0x0 }, // 2563
|
|
{ PseudoVFWADD_VV_M4, VFWADD_VV, 0x2, 0x0 }, // 2564
|
|
{ PseudoVFWADD_VV_M4_MASK, VFWADD_VV, 0x2, 0x0 }, // 2565
|
|
{ PseudoVFWADD_VV_MF4, VFWADD_VV, 0x6, 0x0 }, // 2566
|
|
{ PseudoVFWADD_VV_MF4_MASK, VFWADD_VV, 0x6, 0x0 }, // 2567
|
|
{ PseudoVFWADD_VV_MF2, VFWADD_VV, 0x7, 0x0 }, // 2568
|
|
{ PseudoVFWADD_VV_MF2_MASK, VFWADD_VV, 0x7, 0x0 }, // 2569
|
|
{ PseudoVFWADD_WFPR16_M1, VFWADD_WF, 0x0, 0x0 }, // 2570
|
|
{ PseudoVFWADD_WFPR16_M1_MASK, VFWADD_WF, 0x0, 0x0 }, // 2571
|
|
{ PseudoVFWADD_WFPR32_M1, VFWADD_WF, 0x0, 0x0 }, // 2572
|
|
{ PseudoVFWADD_WFPR32_M1_MASK, VFWADD_WF, 0x0, 0x0 }, // 2573
|
|
{ PseudoVFWADD_WFPR16_M2, VFWADD_WF, 0x1, 0x0 }, // 2574
|
|
{ PseudoVFWADD_WFPR16_M2_MASK, VFWADD_WF, 0x1, 0x0 }, // 2575
|
|
{ PseudoVFWADD_WFPR32_M2, VFWADD_WF, 0x1, 0x0 }, // 2576
|
|
{ PseudoVFWADD_WFPR32_M2_MASK, VFWADD_WF, 0x1, 0x0 }, // 2577
|
|
{ PseudoVFWADD_WFPR16_M4, VFWADD_WF, 0x2, 0x0 }, // 2578
|
|
{ PseudoVFWADD_WFPR16_M4_MASK, VFWADD_WF, 0x2, 0x0 }, // 2579
|
|
{ PseudoVFWADD_WFPR32_M4, VFWADD_WF, 0x2, 0x0 }, // 2580
|
|
{ PseudoVFWADD_WFPR32_M4_MASK, VFWADD_WF, 0x2, 0x0 }, // 2581
|
|
{ PseudoVFWADD_WFPR16_MF4, VFWADD_WF, 0x6, 0x0 }, // 2582
|
|
{ PseudoVFWADD_WFPR16_MF4_MASK, VFWADD_WF, 0x6, 0x0 }, // 2583
|
|
{ PseudoVFWADD_WFPR16_MF2, VFWADD_WF, 0x7, 0x0 }, // 2584
|
|
{ PseudoVFWADD_WFPR16_MF2_MASK, VFWADD_WF, 0x7, 0x0 }, // 2585
|
|
{ PseudoVFWADD_WFPR32_MF2, VFWADD_WF, 0x7, 0x0 }, // 2586
|
|
{ PseudoVFWADD_WFPR32_MF2_MASK, VFWADD_WF, 0x7, 0x0 }, // 2587
|
|
{ PseudoVFWADD_WV_M1, VFWADD_WV, 0x0, 0x0 }, // 2588
|
|
{ PseudoVFWADD_WV_M1_MASK, VFWADD_WV, 0x0, 0x0 }, // 2589
|
|
{ PseudoVFWADD_WV_M1_MASK_TIED, VFWADD_WV, 0x0, 0x0 }, // 2590
|
|
{ PseudoVFWADD_WV_M1_TIED, VFWADD_WV, 0x0, 0x0 }, // 2591
|
|
{ PseudoVFWADD_WV_M2, VFWADD_WV, 0x1, 0x0 }, // 2592
|
|
{ PseudoVFWADD_WV_M2_MASK, VFWADD_WV, 0x1, 0x0 }, // 2593
|
|
{ PseudoVFWADD_WV_M2_MASK_TIED, VFWADD_WV, 0x1, 0x0 }, // 2594
|
|
{ PseudoVFWADD_WV_M2_TIED, VFWADD_WV, 0x1, 0x0 }, // 2595
|
|
{ PseudoVFWADD_WV_M4, VFWADD_WV, 0x2, 0x0 }, // 2596
|
|
{ PseudoVFWADD_WV_M4_MASK, VFWADD_WV, 0x2, 0x0 }, // 2597
|
|
{ PseudoVFWADD_WV_M4_MASK_TIED, VFWADD_WV, 0x2, 0x0 }, // 2598
|
|
{ PseudoVFWADD_WV_M4_TIED, VFWADD_WV, 0x2, 0x0 }, // 2599
|
|
{ PseudoVFWADD_WV_MF4, VFWADD_WV, 0x6, 0x0 }, // 2600
|
|
{ PseudoVFWADD_WV_MF4_MASK, VFWADD_WV, 0x6, 0x0 }, // 2601
|
|
{ PseudoVFWADD_WV_MF4_MASK_TIED, VFWADD_WV, 0x6, 0x0 }, // 2602
|
|
{ PseudoVFWADD_WV_MF4_TIED, VFWADD_WV, 0x6, 0x0 }, // 2603
|
|
{ PseudoVFWADD_WV_MF2, VFWADD_WV, 0x7, 0x0 }, // 2604
|
|
{ PseudoVFWADD_WV_MF2_MASK, VFWADD_WV, 0x7, 0x0 }, // 2605
|
|
{ PseudoVFWADD_WV_MF2_MASK_TIED, VFWADD_WV, 0x7, 0x0 }, // 2606
|
|
{ PseudoVFWADD_WV_MF2_TIED, VFWADD_WV, 0x7, 0x0 }, // 2607
|
|
{ PseudoVFWCVTBF16_F_F_V_M1, VFWCVTBF16_F_F_V, 0x0, 0x0 }, // 2608
|
|
{ PseudoVFWCVTBF16_F_F_V_M1_MASK, VFWCVTBF16_F_F_V, 0x0, 0x0 }, // 2609
|
|
{ PseudoVFWCVTBF16_F_F_V_M2, VFWCVTBF16_F_F_V, 0x1, 0x0 }, // 2610
|
|
{ PseudoVFWCVTBF16_F_F_V_M2_MASK, VFWCVTBF16_F_F_V, 0x1, 0x0 }, // 2611
|
|
{ PseudoVFWCVTBF16_F_F_V_M4, VFWCVTBF16_F_F_V, 0x2, 0x0 }, // 2612
|
|
{ PseudoVFWCVTBF16_F_F_V_M4_MASK, VFWCVTBF16_F_F_V, 0x2, 0x0 }, // 2613
|
|
{ PseudoVFWCVTBF16_F_F_V_MF4, VFWCVTBF16_F_F_V, 0x6, 0x0 }, // 2614
|
|
{ PseudoVFWCVTBF16_F_F_V_MF4_MASK, VFWCVTBF16_F_F_V, 0x6, 0x0 }, // 2615
|
|
{ PseudoVFWCVTBF16_F_F_V_MF2, VFWCVTBF16_F_F_V, 0x7, 0x0 }, // 2616
|
|
{ PseudoVFWCVTBF16_F_F_V_MF2_MASK, VFWCVTBF16_F_F_V, 0x7, 0x0 }, // 2617
|
|
{ PseudoVFWCVT_F_F_V_M1, VFWCVT_F_F_V, 0x0, 0x0 }, // 2618
|
|
{ PseudoVFWCVT_F_F_V_M1_MASK, VFWCVT_F_F_V, 0x0, 0x0 }, // 2619
|
|
{ PseudoVFWCVT_F_F_V_M2, VFWCVT_F_F_V, 0x1, 0x0 }, // 2620
|
|
{ PseudoVFWCVT_F_F_V_M2_MASK, VFWCVT_F_F_V, 0x1, 0x0 }, // 2621
|
|
{ PseudoVFWCVT_F_F_V_M4, VFWCVT_F_F_V, 0x2, 0x0 }, // 2622
|
|
{ PseudoVFWCVT_F_F_V_M4_MASK, VFWCVT_F_F_V, 0x2, 0x0 }, // 2623
|
|
{ PseudoVFWCVT_F_F_V_MF4, VFWCVT_F_F_V, 0x6, 0x0 }, // 2624
|
|
{ PseudoVFWCVT_F_F_V_MF4_MASK, VFWCVT_F_F_V, 0x6, 0x0 }, // 2625
|
|
{ PseudoVFWCVT_F_F_V_MF2, VFWCVT_F_F_V, 0x7, 0x0 }, // 2626
|
|
{ PseudoVFWCVT_F_F_V_MF2_MASK, VFWCVT_F_F_V, 0x7, 0x0 }, // 2627
|
|
{ PseudoVFWCVT_F_XU_V_M1, VFWCVT_F_XU_V, 0x0, 0x0 }, // 2628
|
|
{ PseudoVFWCVT_F_XU_V_M1_MASK, VFWCVT_F_XU_V, 0x0, 0x0 }, // 2629
|
|
{ PseudoVFWCVT_F_XU_V_M2, VFWCVT_F_XU_V, 0x1, 0x0 }, // 2630
|
|
{ PseudoVFWCVT_F_XU_V_M2_MASK, VFWCVT_F_XU_V, 0x1, 0x0 }, // 2631
|
|
{ PseudoVFWCVT_F_XU_V_M4, VFWCVT_F_XU_V, 0x2, 0x0 }, // 2632
|
|
{ PseudoVFWCVT_F_XU_V_M4_MASK, VFWCVT_F_XU_V, 0x2, 0x0 }, // 2633
|
|
{ PseudoVFWCVT_F_XU_V_MF8, VFWCVT_F_XU_V, 0x5, 0x0 }, // 2634
|
|
{ PseudoVFWCVT_F_XU_V_MF8_MASK, VFWCVT_F_XU_V, 0x5, 0x0 }, // 2635
|
|
{ PseudoVFWCVT_F_XU_V_MF4, VFWCVT_F_XU_V, 0x6, 0x0 }, // 2636
|
|
{ PseudoVFWCVT_F_XU_V_MF4_MASK, VFWCVT_F_XU_V, 0x6, 0x0 }, // 2637
|
|
{ PseudoVFWCVT_F_XU_V_MF2, VFWCVT_F_XU_V, 0x7, 0x0 }, // 2638
|
|
{ PseudoVFWCVT_F_XU_V_MF2_MASK, VFWCVT_F_XU_V, 0x7, 0x0 }, // 2639
|
|
{ PseudoVFWCVT_F_X_V_M1, VFWCVT_F_X_V, 0x0, 0x0 }, // 2640
|
|
{ PseudoVFWCVT_F_X_V_M1_MASK, VFWCVT_F_X_V, 0x0, 0x0 }, // 2641
|
|
{ PseudoVFWCVT_F_X_V_M2, VFWCVT_F_X_V, 0x1, 0x0 }, // 2642
|
|
{ PseudoVFWCVT_F_X_V_M2_MASK, VFWCVT_F_X_V, 0x1, 0x0 }, // 2643
|
|
{ PseudoVFWCVT_F_X_V_M4, VFWCVT_F_X_V, 0x2, 0x0 }, // 2644
|
|
{ PseudoVFWCVT_F_X_V_M4_MASK, VFWCVT_F_X_V, 0x2, 0x0 }, // 2645
|
|
{ PseudoVFWCVT_F_X_V_MF8, VFWCVT_F_X_V, 0x5, 0x0 }, // 2646
|
|
{ PseudoVFWCVT_F_X_V_MF8_MASK, VFWCVT_F_X_V, 0x5, 0x0 }, // 2647
|
|
{ PseudoVFWCVT_F_X_V_MF4, VFWCVT_F_X_V, 0x6, 0x0 }, // 2648
|
|
{ PseudoVFWCVT_F_X_V_MF4_MASK, VFWCVT_F_X_V, 0x6, 0x0 }, // 2649
|
|
{ PseudoVFWCVT_F_X_V_MF2, VFWCVT_F_X_V, 0x7, 0x0 }, // 2650
|
|
{ PseudoVFWCVT_F_X_V_MF2_MASK, VFWCVT_F_X_V, 0x7, 0x0 }, // 2651
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 2652
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 2653
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 2654
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 2655
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 2656
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 2657
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 2658
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 2659
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 2660
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 2661
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 2662
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 2663
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 2664
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 2665
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 2666
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 2667
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 2668
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 2669
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 2670
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 2671
|
|
{ PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2672
|
|
{ PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2673
|
|
{ PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2674
|
|
{ PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2675
|
|
{ PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2676
|
|
{ PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2677
|
|
{ PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2678
|
|
{ PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2679
|
|
{ PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2680
|
|
{ PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2681
|
|
{ PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2682
|
|
{ PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2683
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2684
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2685
|
|
{ PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2686
|
|
{ PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2687
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2688
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2689
|
|
{ PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2690
|
|
{ PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2691
|
|
{ PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 2692
|
|
{ PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 2693
|
|
{ PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 2694
|
|
{ PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 2695
|
|
{ PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 2696
|
|
{ PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 2697
|
|
{ PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 2698
|
|
{ PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 2699
|
|
{ PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 2700
|
|
{ PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 2701
|
|
{ PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 2702
|
|
{ PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 2703
|
|
{ PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 2704
|
|
{ PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 2705
|
|
{ PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 2706
|
|
{ PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 2707
|
|
{ PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 2708
|
|
{ PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 2709
|
|
{ PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 2710
|
|
{ PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 2711
|
|
{ PseudoVFWMACCBF16_VFPR16_M1, VFWMACCBF16_VF, 0x0, 0x0 }, // 2712
|
|
{ PseudoVFWMACCBF16_VFPR16_M1_MASK, VFWMACCBF16_VF, 0x0, 0x0 }, // 2713
|
|
{ PseudoVFWMACCBF16_VFPR16_M2, VFWMACCBF16_VF, 0x1, 0x0 }, // 2714
|
|
{ PseudoVFWMACCBF16_VFPR16_M2_MASK, VFWMACCBF16_VF, 0x1, 0x0 }, // 2715
|
|
{ PseudoVFWMACCBF16_VFPR16_M4, VFWMACCBF16_VF, 0x2, 0x0 }, // 2716
|
|
{ PseudoVFWMACCBF16_VFPR16_M4_MASK, VFWMACCBF16_VF, 0x2, 0x0 }, // 2717
|
|
{ PseudoVFWMACCBF16_VFPR16_MF4, VFWMACCBF16_VF, 0x6, 0x0 }, // 2718
|
|
{ PseudoVFWMACCBF16_VFPR16_MF4_MASK, VFWMACCBF16_VF, 0x6, 0x0 }, // 2719
|
|
{ PseudoVFWMACCBF16_VFPR16_MF2, VFWMACCBF16_VF, 0x7, 0x0 }, // 2720
|
|
{ PseudoVFWMACCBF16_VFPR16_MF2_MASK, VFWMACCBF16_VF, 0x7, 0x0 }, // 2721
|
|
{ PseudoVFWMACCBF16_VV_M1, VFWMACCBF16_VV, 0x0, 0x0 }, // 2722
|
|
{ PseudoVFWMACCBF16_VV_M1_MASK, VFWMACCBF16_VV, 0x0, 0x0 }, // 2723
|
|
{ PseudoVFWMACCBF16_VV_M2, VFWMACCBF16_VV, 0x1, 0x0 }, // 2724
|
|
{ PseudoVFWMACCBF16_VV_M2_MASK, VFWMACCBF16_VV, 0x1, 0x0 }, // 2725
|
|
{ PseudoVFWMACCBF16_VV_M4, VFWMACCBF16_VV, 0x2, 0x0 }, // 2726
|
|
{ PseudoVFWMACCBF16_VV_M4_MASK, VFWMACCBF16_VV, 0x2, 0x0 }, // 2727
|
|
{ PseudoVFWMACCBF16_VV_MF4, VFWMACCBF16_VV, 0x6, 0x0 }, // 2728
|
|
{ PseudoVFWMACCBF16_VV_MF4_MASK, VFWMACCBF16_VV, 0x6, 0x0 }, // 2729
|
|
{ PseudoVFWMACCBF16_VV_MF2, VFWMACCBF16_VV, 0x7, 0x0 }, // 2730
|
|
{ PseudoVFWMACCBF16_VV_MF2_MASK, VFWMACCBF16_VV, 0x7, 0x0 }, // 2731
|
|
{ PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4, 0x0, 0x0 }, // 2732
|
|
{ PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4, 0x1, 0x0 }, // 2733
|
|
{ PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4, 0x2, 0x0 }, // 2734
|
|
{ PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4, 0x3, 0x0 }, // 2735
|
|
{ PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4, 0x6, 0x0 }, // 2736
|
|
{ PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4, 0x7, 0x0 }, // 2737
|
|
{ PseudoVFWMACC_VFPR16_M1, VFWMACC_VF, 0x0, 0x0 }, // 2738
|
|
{ PseudoVFWMACC_VFPR16_M1_MASK, VFWMACC_VF, 0x0, 0x0 }, // 2739
|
|
{ PseudoVFWMACC_VFPR32_M1, VFWMACC_VF, 0x0, 0x0 }, // 2740
|
|
{ PseudoVFWMACC_VFPR32_M1_MASK, VFWMACC_VF, 0x0, 0x0 }, // 2741
|
|
{ PseudoVFWMACC_VFPR16_M2, VFWMACC_VF, 0x1, 0x0 }, // 2742
|
|
{ PseudoVFWMACC_VFPR16_M2_MASK, VFWMACC_VF, 0x1, 0x0 }, // 2743
|
|
{ PseudoVFWMACC_VFPR32_M2, VFWMACC_VF, 0x1, 0x0 }, // 2744
|
|
{ PseudoVFWMACC_VFPR32_M2_MASK, VFWMACC_VF, 0x1, 0x0 }, // 2745
|
|
{ PseudoVFWMACC_VFPR16_M4, VFWMACC_VF, 0x2, 0x0 }, // 2746
|
|
{ PseudoVFWMACC_VFPR16_M4_MASK, VFWMACC_VF, 0x2, 0x0 }, // 2747
|
|
{ PseudoVFWMACC_VFPR32_M4, VFWMACC_VF, 0x2, 0x0 }, // 2748
|
|
{ PseudoVFWMACC_VFPR32_M4_MASK, VFWMACC_VF, 0x2, 0x0 }, // 2749
|
|
{ PseudoVFWMACC_VFPR16_MF4, VFWMACC_VF, 0x6, 0x0 }, // 2750
|
|
{ PseudoVFWMACC_VFPR16_MF4_MASK, VFWMACC_VF, 0x6, 0x0 }, // 2751
|
|
{ PseudoVFWMACC_VFPR16_MF2, VFWMACC_VF, 0x7, 0x0 }, // 2752
|
|
{ PseudoVFWMACC_VFPR16_MF2_MASK, VFWMACC_VF, 0x7, 0x0 }, // 2753
|
|
{ PseudoVFWMACC_VFPR32_MF2, VFWMACC_VF, 0x7, 0x0 }, // 2754
|
|
{ PseudoVFWMACC_VFPR32_MF2_MASK, VFWMACC_VF, 0x7, 0x0 }, // 2755
|
|
{ PseudoVFWMACC_VV_M1, VFWMACC_VV, 0x0, 0x0 }, // 2756
|
|
{ PseudoVFWMACC_VV_M1_MASK, VFWMACC_VV, 0x0, 0x0 }, // 2757
|
|
{ PseudoVFWMACC_VV_M2, VFWMACC_VV, 0x1, 0x0 }, // 2758
|
|
{ PseudoVFWMACC_VV_M2_MASK, VFWMACC_VV, 0x1, 0x0 }, // 2759
|
|
{ PseudoVFWMACC_VV_M4, VFWMACC_VV, 0x2, 0x0 }, // 2760
|
|
{ PseudoVFWMACC_VV_M4_MASK, VFWMACC_VV, 0x2, 0x0 }, // 2761
|
|
{ PseudoVFWMACC_VV_MF4, VFWMACC_VV, 0x6, 0x0 }, // 2762
|
|
{ PseudoVFWMACC_VV_MF4_MASK, VFWMACC_VV, 0x6, 0x0 }, // 2763
|
|
{ PseudoVFWMACC_VV_MF2, VFWMACC_VV, 0x7, 0x0 }, // 2764
|
|
{ PseudoVFWMACC_VV_MF2_MASK, VFWMACC_VV, 0x7, 0x0 }, // 2765
|
|
{ PseudoVFWMSAC_VFPR16_M1, VFWMSAC_VF, 0x0, 0x0 }, // 2766
|
|
{ PseudoVFWMSAC_VFPR16_M1_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 2767
|
|
{ PseudoVFWMSAC_VFPR32_M1, VFWMSAC_VF, 0x0, 0x0 }, // 2768
|
|
{ PseudoVFWMSAC_VFPR32_M1_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 2769
|
|
{ PseudoVFWMSAC_VFPR16_M2, VFWMSAC_VF, 0x1, 0x0 }, // 2770
|
|
{ PseudoVFWMSAC_VFPR16_M2_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 2771
|
|
{ PseudoVFWMSAC_VFPR32_M2, VFWMSAC_VF, 0x1, 0x0 }, // 2772
|
|
{ PseudoVFWMSAC_VFPR32_M2_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 2773
|
|
{ PseudoVFWMSAC_VFPR16_M4, VFWMSAC_VF, 0x2, 0x0 }, // 2774
|
|
{ PseudoVFWMSAC_VFPR16_M4_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 2775
|
|
{ PseudoVFWMSAC_VFPR32_M4, VFWMSAC_VF, 0x2, 0x0 }, // 2776
|
|
{ PseudoVFWMSAC_VFPR32_M4_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 2777
|
|
{ PseudoVFWMSAC_VFPR16_MF4, VFWMSAC_VF, 0x6, 0x0 }, // 2778
|
|
{ PseudoVFWMSAC_VFPR16_MF4_MASK, VFWMSAC_VF, 0x6, 0x0 }, // 2779
|
|
{ PseudoVFWMSAC_VFPR16_MF2, VFWMSAC_VF, 0x7, 0x0 }, // 2780
|
|
{ PseudoVFWMSAC_VFPR16_MF2_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 2781
|
|
{ PseudoVFWMSAC_VFPR32_MF2, VFWMSAC_VF, 0x7, 0x0 }, // 2782
|
|
{ PseudoVFWMSAC_VFPR32_MF2_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 2783
|
|
{ PseudoVFWMSAC_VV_M1, VFWMSAC_VV, 0x0, 0x0 }, // 2784
|
|
{ PseudoVFWMSAC_VV_M1_MASK, VFWMSAC_VV, 0x0, 0x0 }, // 2785
|
|
{ PseudoVFWMSAC_VV_M2, VFWMSAC_VV, 0x1, 0x0 }, // 2786
|
|
{ PseudoVFWMSAC_VV_M2_MASK, VFWMSAC_VV, 0x1, 0x0 }, // 2787
|
|
{ PseudoVFWMSAC_VV_M4, VFWMSAC_VV, 0x2, 0x0 }, // 2788
|
|
{ PseudoVFWMSAC_VV_M4_MASK, VFWMSAC_VV, 0x2, 0x0 }, // 2789
|
|
{ PseudoVFWMSAC_VV_MF4, VFWMSAC_VV, 0x6, 0x0 }, // 2790
|
|
{ PseudoVFWMSAC_VV_MF4_MASK, VFWMSAC_VV, 0x6, 0x0 }, // 2791
|
|
{ PseudoVFWMSAC_VV_MF2, VFWMSAC_VV, 0x7, 0x0 }, // 2792
|
|
{ PseudoVFWMSAC_VV_MF2_MASK, VFWMSAC_VV, 0x7, 0x0 }, // 2793
|
|
{ PseudoVFWMUL_VFPR16_M1, VFWMUL_VF, 0x0, 0x0 }, // 2794
|
|
{ PseudoVFWMUL_VFPR16_M1_MASK, VFWMUL_VF, 0x0, 0x0 }, // 2795
|
|
{ PseudoVFWMUL_VFPR32_M1, VFWMUL_VF, 0x0, 0x0 }, // 2796
|
|
{ PseudoVFWMUL_VFPR32_M1_MASK, VFWMUL_VF, 0x0, 0x0 }, // 2797
|
|
{ PseudoVFWMUL_VFPR16_M2, VFWMUL_VF, 0x1, 0x0 }, // 2798
|
|
{ PseudoVFWMUL_VFPR16_M2_MASK, VFWMUL_VF, 0x1, 0x0 }, // 2799
|
|
{ PseudoVFWMUL_VFPR32_M2, VFWMUL_VF, 0x1, 0x0 }, // 2800
|
|
{ PseudoVFWMUL_VFPR32_M2_MASK, VFWMUL_VF, 0x1, 0x0 }, // 2801
|
|
{ PseudoVFWMUL_VFPR16_M4, VFWMUL_VF, 0x2, 0x0 }, // 2802
|
|
{ PseudoVFWMUL_VFPR16_M4_MASK, VFWMUL_VF, 0x2, 0x0 }, // 2803
|
|
{ PseudoVFWMUL_VFPR32_M4, VFWMUL_VF, 0x2, 0x0 }, // 2804
|
|
{ PseudoVFWMUL_VFPR32_M4_MASK, VFWMUL_VF, 0x2, 0x0 }, // 2805
|
|
{ PseudoVFWMUL_VFPR16_MF4, VFWMUL_VF, 0x6, 0x0 }, // 2806
|
|
{ PseudoVFWMUL_VFPR16_MF4_MASK, VFWMUL_VF, 0x6, 0x0 }, // 2807
|
|
{ PseudoVFWMUL_VFPR16_MF2, VFWMUL_VF, 0x7, 0x0 }, // 2808
|
|
{ PseudoVFWMUL_VFPR16_MF2_MASK, VFWMUL_VF, 0x7, 0x0 }, // 2809
|
|
{ PseudoVFWMUL_VFPR32_MF2, VFWMUL_VF, 0x7, 0x0 }, // 2810
|
|
{ PseudoVFWMUL_VFPR32_MF2_MASK, VFWMUL_VF, 0x7, 0x0 }, // 2811
|
|
{ PseudoVFWMUL_VV_M1, VFWMUL_VV, 0x0, 0x0 }, // 2812
|
|
{ PseudoVFWMUL_VV_M1_MASK, VFWMUL_VV, 0x0, 0x0 }, // 2813
|
|
{ PseudoVFWMUL_VV_M2, VFWMUL_VV, 0x1, 0x0 }, // 2814
|
|
{ PseudoVFWMUL_VV_M2_MASK, VFWMUL_VV, 0x1, 0x0 }, // 2815
|
|
{ PseudoVFWMUL_VV_M4, VFWMUL_VV, 0x2, 0x0 }, // 2816
|
|
{ PseudoVFWMUL_VV_M4_MASK, VFWMUL_VV, 0x2, 0x0 }, // 2817
|
|
{ PseudoVFWMUL_VV_MF4, VFWMUL_VV, 0x6, 0x0 }, // 2818
|
|
{ PseudoVFWMUL_VV_MF4_MASK, VFWMUL_VV, 0x6, 0x0 }, // 2819
|
|
{ PseudoVFWMUL_VV_MF2, VFWMUL_VV, 0x7, 0x0 }, // 2820
|
|
{ PseudoVFWMUL_VV_MF2_MASK, VFWMUL_VV, 0x7, 0x0 }, // 2821
|
|
{ PseudoVFWNMACC_VFPR16_M1, VFWNMACC_VF, 0x0, 0x0 }, // 2822
|
|
{ PseudoVFWNMACC_VFPR16_M1_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 2823
|
|
{ PseudoVFWNMACC_VFPR32_M1, VFWNMACC_VF, 0x0, 0x0 }, // 2824
|
|
{ PseudoVFWNMACC_VFPR32_M1_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 2825
|
|
{ PseudoVFWNMACC_VFPR16_M2, VFWNMACC_VF, 0x1, 0x0 }, // 2826
|
|
{ PseudoVFWNMACC_VFPR16_M2_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 2827
|
|
{ PseudoVFWNMACC_VFPR32_M2, VFWNMACC_VF, 0x1, 0x0 }, // 2828
|
|
{ PseudoVFWNMACC_VFPR32_M2_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 2829
|
|
{ PseudoVFWNMACC_VFPR16_M4, VFWNMACC_VF, 0x2, 0x0 }, // 2830
|
|
{ PseudoVFWNMACC_VFPR16_M4_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 2831
|
|
{ PseudoVFWNMACC_VFPR32_M4, VFWNMACC_VF, 0x2, 0x0 }, // 2832
|
|
{ PseudoVFWNMACC_VFPR32_M4_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 2833
|
|
{ PseudoVFWNMACC_VFPR16_MF4, VFWNMACC_VF, 0x6, 0x0 }, // 2834
|
|
{ PseudoVFWNMACC_VFPR16_MF4_MASK, VFWNMACC_VF, 0x6, 0x0 }, // 2835
|
|
{ PseudoVFWNMACC_VFPR16_MF2, VFWNMACC_VF, 0x7, 0x0 }, // 2836
|
|
{ PseudoVFWNMACC_VFPR16_MF2_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 2837
|
|
{ PseudoVFWNMACC_VFPR32_MF2, VFWNMACC_VF, 0x7, 0x0 }, // 2838
|
|
{ PseudoVFWNMACC_VFPR32_MF2_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 2839
|
|
{ PseudoVFWNMACC_VV_M1, VFWNMACC_VV, 0x0, 0x0 }, // 2840
|
|
{ PseudoVFWNMACC_VV_M1_MASK, VFWNMACC_VV, 0x0, 0x0 }, // 2841
|
|
{ PseudoVFWNMACC_VV_M2, VFWNMACC_VV, 0x1, 0x0 }, // 2842
|
|
{ PseudoVFWNMACC_VV_M2_MASK, VFWNMACC_VV, 0x1, 0x0 }, // 2843
|
|
{ PseudoVFWNMACC_VV_M4, VFWNMACC_VV, 0x2, 0x0 }, // 2844
|
|
{ PseudoVFWNMACC_VV_M4_MASK, VFWNMACC_VV, 0x2, 0x0 }, // 2845
|
|
{ PseudoVFWNMACC_VV_MF4, VFWNMACC_VV, 0x6, 0x0 }, // 2846
|
|
{ PseudoVFWNMACC_VV_MF4_MASK, VFWNMACC_VV, 0x6, 0x0 }, // 2847
|
|
{ PseudoVFWNMACC_VV_MF2, VFWNMACC_VV, 0x7, 0x0 }, // 2848
|
|
{ PseudoVFWNMACC_VV_MF2_MASK, VFWNMACC_VV, 0x7, 0x0 }, // 2849
|
|
{ PseudoVFWNMSAC_VFPR16_M1, VFWNMSAC_VF, 0x0, 0x0 }, // 2850
|
|
{ PseudoVFWNMSAC_VFPR16_M1_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 2851
|
|
{ PseudoVFWNMSAC_VFPR32_M1, VFWNMSAC_VF, 0x0, 0x0 }, // 2852
|
|
{ PseudoVFWNMSAC_VFPR32_M1_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 2853
|
|
{ PseudoVFWNMSAC_VFPR16_M2, VFWNMSAC_VF, 0x1, 0x0 }, // 2854
|
|
{ PseudoVFWNMSAC_VFPR16_M2_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 2855
|
|
{ PseudoVFWNMSAC_VFPR32_M2, VFWNMSAC_VF, 0x1, 0x0 }, // 2856
|
|
{ PseudoVFWNMSAC_VFPR32_M2_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 2857
|
|
{ PseudoVFWNMSAC_VFPR16_M4, VFWNMSAC_VF, 0x2, 0x0 }, // 2858
|
|
{ PseudoVFWNMSAC_VFPR16_M4_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 2859
|
|
{ PseudoVFWNMSAC_VFPR32_M4, VFWNMSAC_VF, 0x2, 0x0 }, // 2860
|
|
{ PseudoVFWNMSAC_VFPR32_M4_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 2861
|
|
{ PseudoVFWNMSAC_VFPR16_MF4, VFWNMSAC_VF, 0x6, 0x0 }, // 2862
|
|
{ PseudoVFWNMSAC_VFPR16_MF4_MASK, VFWNMSAC_VF, 0x6, 0x0 }, // 2863
|
|
{ PseudoVFWNMSAC_VFPR16_MF2, VFWNMSAC_VF, 0x7, 0x0 }, // 2864
|
|
{ PseudoVFWNMSAC_VFPR16_MF2_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 2865
|
|
{ PseudoVFWNMSAC_VFPR32_MF2, VFWNMSAC_VF, 0x7, 0x0 }, // 2866
|
|
{ PseudoVFWNMSAC_VFPR32_MF2_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 2867
|
|
{ PseudoVFWNMSAC_VV_M1, VFWNMSAC_VV, 0x0, 0x0 }, // 2868
|
|
{ PseudoVFWNMSAC_VV_M1_MASK, VFWNMSAC_VV, 0x0, 0x0 }, // 2869
|
|
{ PseudoVFWNMSAC_VV_M2, VFWNMSAC_VV, 0x1, 0x0 }, // 2870
|
|
{ PseudoVFWNMSAC_VV_M2_MASK, VFWNMSAC_VV, 0x1, 0x0 }, // 2871
|
|
{ PseudoVFWNMSAC_VV_M4, VFWNMSAC_VV, 0x2, 0x0 }, // 2872
|
|
{ PseudoVFWNMSAC_VV_M4_MASK, VFWNMSAC_VV, 0x2, 0x0 }, // 2873
|
|
{ PseudoVFWNMSAC_VV_MF4, VFWNMSAC_VV, 0x6, 0x0 }, // 2874
|
|
{ PseudoVFWNMSAC_VV_MF4_MASK, VFWNMSAC_VV, 0x6, 0x0 }, // 2875
|
|
{ PseudoVFWNMSAC_VV_MF2, VFWNMSAC_VV, 0x7, 0x0 }, // 2876
|
|
{ PseudoVFWNMSAC_VV_MF2_MASK, VFWNMSAC_VV, 0x7, 0x0 }, // 2877
|
|
{ PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS, 0x0, 0x10 }, // 2878
|
|
{ PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS, 0x0, 0x10 }, // 2879
|
|
{ PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS, 0x0, 0x20 }, // 2880
|
|
{ PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS, 0x0, 0x20 }, // 2881
|
|
{ PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS, 0x1, 0x10 }, // 2882
|
|
{ PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS, 0x1, 0x10 }, // 2883
|
|
{ PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS, 0x1, 0x20 }, // 2884
|
|
{ PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS, 0x1, 0x20 }, // 2885
|
|
{ PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS, 0x2, 0x10 }, // 2886
|
|
{ PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS, 0x2, 0x10 }, // 2887
|
|
{ PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS, 0x2, 0x20 }, // 2888
|
|
{ PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS, 0x2, 0x20 }, // 2889
|
|
{ PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS, 0x3, 0x10 }, // 2890
|
|
{ PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS, 0x3, 0x10 }, // 2891
|
|
{ PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS, 0x3, 0x20 }, // 2892
|
|
{ PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS, 0x3, 0x20 }, // 2893
|
|
{ PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS, 0x6, 0x10 }, // 2894
|
|
{ PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS, 0x6, 0x10 }, // 2895
|
|
{ PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS, 0x7, 0x10 }, // 2896
|
|
{ PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS, 0x7, 0x10 }, // 2897
|
|
{ PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS, 0x7, 0x20 }, // 2898
|
|
{ PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS, 0x7, 0x20 }, // 2899
|
|
{ PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS, 0x0, 0x10 }, // 2900
|
|
{ PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS, 0x0, 0x10 }, // 2901
|
|
{ PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS, 0x0, 0x20 }, // 2902
|
|
{ PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS, 0x0, 0x20 }, // 2903
|
|
{ PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS, 0x1, 0x10 }, // 2904
|
|
{ PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS, 0x1, 0x10 }, // 2905
|
|
{ PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS, 0x1, 0x20 }, // 2906
|
|
{ PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS, 0x1, 0x20 }, // 2907
|
|
{ PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS, 0x2, 0x10 }, // 2908
|
|
{ PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS, 0x2, 0x10 }, // 2909
|
|
{ PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS, 0x2, 0x20 }, // 2910
|
|
{ PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS, 0x2, 0x20 }, // 2911
|
|
{ PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS, 0x3, 0x10 }, // 2912
|
|
{ PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS, 0x3, 0x10 }, // 2913
|
|
{ PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS, 0x3, 0x20 }, // 2914
|
|
{ PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS, 0x3, 0x20 }, // 2915
|
|
{ PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS, 0x6, 0x10 }, // 2916
|
|
{ PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS, 0x6, 0x10 }, // 2917
|
|
{ PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS, 0x7, 0x10 }, // 2918
|
|
{ PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS, 0x7, 0x10 }, // 2919
|
|
{ PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS, 0x7, 0x20 }, // 2920
|
|
{ PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS, 0x7, 0x20 }, // 2921
|
|
{ PseudoVFWSUB_VFPR16_M1, VFWSUB_VF, 0x0, 0x0 }, // 2922
|
|
{ PseudoVFWSUB_VFPR16_M1_MASK, VFWSUB_VF, 0x0, 0x0 }, // 2923
|
|
{ PseudoVFWSUB_VFPR32_M1, VFWSUB_VF, 0x0, 0x0 }, // 2924
|
|
{ PseudoVFWSUB_VFPR32_M1_MASK, VFWSUB_VF, 0x0, 0x0 }, // 2925
|
|
{ PseudoVFWSUB_VFPR16_M2, VFWSUB_VF, 0x1, 0x0 }, // 2926
|
|
{ PseudoVFWSUB_VFPR16_M2_MASK, VFWSUB_VF, 0x1, 0x0 }, // 2927
|
|
{ PseudoVFWSUB_VFPR32_M2, VFWSUB_VF, 0x1, 0x0 }, // 2928
|
|
{ PseudoVFWSUB_VFPR32_M2_MASK, VFWSUB_VF, 0x1, 0x0 }, // 2929
|
|
{ PseudoVFWSUB_VFPR16_M4, VFWSUB_VF, 0x2, 0x0 }, // 2930
|
|
{ PseudoVFWSUB_VFPR16_M4_MASK, VFWSUB_VF, 0x2, 0x0 }, // 2931
|
|
{ PseudoVFWSUB_VFPR32_M4, VFWSUB_VF, 0x2, 0x0 }, // 2932
|
|
{ PseudoVFWSUB_VFPR32_M4_MASK, VFWSUB_VF, 0x2, 0x0 }, // 2933
|
|
{ PseudoVFWSUB_VFPR16_MF4, VFWSUB_VF, 0x6, 0x0 }, // 2934
|
|
{ PseudoVFWSUB_VFPR16_MF4_MASK, VFWSUB_VF, 0x6, 0x0 }, // 2935
|
|
{ PseudoVFWSUB_VFPR16_MF2, VFWSUB_VF, 0x7, 0x0 }, // 2936
|
|
{ PseudoVFWSUB_VFPR16_MF2_MASK, VFWSUB_VF, 0x7, 0x0 }, // 2937
|
|
{ PseudoVFWSUB_VFPR32_MF2, VFWSUB_VF, 0x7, 0x0 }, // 2938
|
|
{ PseudoVFWSUB_VFPR32_MF2_MASK, VFWSUB_VF, 0x7, 0x0 }, // 2939
|
|
{ PseudoVFWSUB_VV_M1, VFWSUB_VV, 0x0, 0x0 }, // 2940
|
|
{ PseudoVFWSUB_VV_M1_MASK, VFWSUB_VV, 0x0, 0x0 }, // 2941
|
|
{ PseudoVFWSUB_VV_M2, VFWSUB_VV, 0x1, 0x0 }, // 2942
|
|
{ PseudoVFWSUB_VV_M2_MASK, VFWSUB_VV, 0x1, 0x0 }, // 2943
|
|
{ PseudoVFWSUB_VV_M4, VFWSUB_VV, 0x2, 0x0 }, // 2944
|
|
{ PseudoVFWSUB_VV_M4_MASK, VFWSUB_VV, 0x2, 0x0 }, // 2945
|
|
{ PseudoVFWSUB_VV_MF4, VFWSUB_VV, 0x6, 0x0 }, // 2946
|
|
{ PseudoVFWSUB_VV_MF4_MASK, VFWSUB_VV, 0x6, 0x0 }, // 2947
|
|
{ PseudoVFWSUB_VV_MF2, VFWSUB_VV, 0x7, 0x0 }, // 2948
|
|
{ PseudoVFWSUB_VV_MF2_MASK, VFWSUB_VV, 0x7, 0x0 }, // 2949
|
|
{ PseudoVFWSUB_WFPR16_M1, VFWSUB_WF, 0x0, 0x0 }, // 2950
|
|
{ PseudoVFWSUB_WFPR16_M1_MASK, VFWSUB_WF, 0x0, 0x0 }, // 2951
|
|
{ PseudoVFWSUB_WFPR32_M1, VFWSUB_WF, 0x0, 0x0 }, // 2952
|
|
{ PseudoVFWSUB_WFPR32_M1_MASK, VFWSUB_WF, 0x0, 0x0 }, // 2953
|
|
{ PseudoVFWSUB_WFPR16_M2, VFWSUB_WF, 0x1, 0x0 }, // 2954
|
|
{ PseudoVFWSUB_WFPR16_M2_MASK, VFWSUB_WF, 0x1, 0x0 }, // 2955
|
|
{ PseudoVFWSUB_WFPR32_M2, VFWSUB_WF, 0x1, 0x0 }, // 2956
|
|
{ PseudoVFWSUB_WFPR32_M2_MASK, VFWSUB_WF, 0x1, 0x0 }, // 2957
|
|
{ PseudoVFWSUB_WFPR16_M4, VFWSUB_WF, 0x2, 0x0 }, // 2958
|
|
{ PseudoVFWSUB_WFPR16_M4_MASK, VFWSUB_WF, 0x2, 0x0 }, // 2959
|
|
{ PseudoVFWSUB_WFPR32_M4, VFWSUB_WF, 0x2, 0x0 }, // 2960
|
|
{ PseudoVFWSUB_WFPR32_M4_MASK, VFWSUB_WF, 0x2, 0x0 }, // 2961
|
|
{ PseudoVFWSUB_WFPR16_MF4, VFWSUB_WF, 0x6, 0x0 }, // 2962
|
|
{ PseudoVFWSUB_WFPR16_MF4_MASK, VFWSUB_WF, 0x6, 0x0 }, // 2963
|
|
{ PseudoVFWSUB_WFPR16_MF2, VFWSUB_WF, 0x7, 0x0 }, // 2964
|
|
{ PseudoVFWSUB_WFPR16_MF2_MASK, VFWSUB_WF, 0x7, 0x0 }, // 2965
|
|
{ PseudoVFWSUB_WFPR32_MF2, VFWSUB_WF, 0x7, 0x0 }, // 2966
|
|
{ PseudoVFWSUB_WFPR32_MF2_MASK, VFWSUB_WF, 0x7, 0x0 }, // 2967
|
|
{ PseudoVFWSUB_WV_M1, VFWSUB_WV, 0x0, 0x0 }, // 2968
|
|
{ PseudoVFWSUB_WV_M1_MASK, VFWSUB_WV, 0x0, 0x0 }, // 2969
|
|
{ PseudoVFWSUB_WV_M1_MASK_TIED, VFWSUB_WV, 0x0, 0x0 }, // 2970
|
|
{ PseudoVFWSUB_WV_M1_TIED, VFWSUB_WV, 0x0, 0x0 }, // 2971
|
|
{ PseudoVFWSUB_WV_M2, VFWSUB_WV, 0x1, 0x0 }, // 2972
|
|
{ PseudoVFWSUB_WV_M2_MASK, VFWSUB_WV, 0x1, 0x0 }, // 2973
|
|
{ PseudoVFWSUB_WV_M2_MASK_TIED, VFWSUB_WV, 0x1, 0x0 }, // 2974
|
|
{ PseudoVFWSUB_WV_M2_TIED, VFWSUB_WV, 0x1, 0x0 }, // 2975
|
|
{ PseudoVFWSUB_WV_M4, VFWSUB_WV, 0x2, 0x0 }, // 2976
|
|
{ PseudoVFWSUB_WV_M4_MASK, VFWSUB_WV, 0x2, 0x0 }, // 2977
|
|
{ PseudoVFWSUB_WV_M4_MASK_TIED, VFWSUB_WV, 0x2, 0x0 }, // 2978
|
|
{ PseudoVFWSUB_WV_M4_TIED, VFWSUB_WV, 0x2, 0x0 }, // 2979
|
|
{ PseudoVFWSUB_WV_MF4, VFWSUB_WV, 0x6, 0x0 }, // 2980
|
|
{ PseudoVFWSUB_WV_MF4_MASK, VFWSUB_WV, 0x6, 0x0 }, // 2981
|
|
{ PseudoVFWSUB_WV_MF4_MASK_TIED, VFWSUB_WV, 0x6, 0x0 }, // 2982
|
|
{ PseudoVFWSUB_WV_MF4_TIED, VFWSUB_WV, 0x6, 0x0 }, // 2983
|
|
{ PseudoVFWSUB_WV_MF2, VFWSUB_WV, 0x7, 0x0 }, // 2984
|
|
{ PseudoVFWSUB_WV_MF2_MASK, VFWSUB_WV, 0x7, 0x0 }, // 2985
|
|
{ PseudoVFWSUB_WV_MF2_MASK_TIED, VFWSUB_WV, 0x7, 0x0 }, // 2986
|
|
{ PseudoVFWSUB_WV_MF2_TIED, VFWSUB_WV, 0x7, 0x0 }, // 2987
|
|
{ PseudoVGHSH_VV_M1, VGHSH_VV, 0x0, 0x0 }, // 2988
|
|
{ PseudoVGHSH_VV_M2, VGHSH_VV, 0x1, 0x0 }, // 2989
|
|
{ PseudoVGHSH_VV_M4, VGHSH_VV, 0x2, 0x0 }, // 2990
|
|
{ PseudoVGHSH_VV_M8, VGHSH_VV, 0x3, 0x0 }, // 2991
|
|
{ PseudoVGHSH_VV_MF2, VGHSH_VV, 0x7, 0x0 }, // 2992
|
|
{ PseudoVGMUL_VV_M1, VGMUL_VV, 0x0, 0x0 }, // 2993
|
|
{ PseudoVGMUL_VV_M2, VGMUL_VV, 0x1, 0x0 }, // 2994
|
|
{ PseudoVGMUL_VV_M4, VGMUL_VV, 0x2, 0x0 }, // 2995
|
|
{ PseudoVGMUL_VV_M8, VGMUL_VV, 0x3, 0x0 }, // 2996
|
|
{ PseudoVGMUL_VV_MF2, VGMUL_VV, 0x7, 0x0 }, // 2997
|
|
{ PseudoVID_V_M1, VID_V, 0x0, 0x0 }, // 2998
|
|
{ PseudoVID_V_M1_MASK, VID_V, 0x0, 0x0 }, // 2999
|
|
{ PseudoVID_V_M2, VID_V, 0x1, 0x0 }, // 3000
|
|
{ PseudoVID_V_M2_MASK, VID_V, 0x1, 0x0 }, // 3001
|
|
{ PseudoVID_V_M4, VID_V, 0x2, 0x0 }, // 3002
|
|
{ PseudoVID_V_M4_MASK, VID_V, 0x2, 0x0 }, // 3003
|
|
{ PseudoVID_V_M8, VID_V, 0x3, 0x0 }, // 3004
|
|
{ PseudoVID_V_M8_MASK, VID_V, 0x3, 0x0 }, // 3005
|
|
{ PseudoVID_V_MF8, VID_V, 0x5, 0x0 }, // 3006
|
|
{ PseudoVID_V_MF8_MASK, VID_V, 0x5, 0x0 }, // 3007
|
|
{ PseudoVID_V_MF4, VID_V, 0x6, 0x0 }, // 3008
|
|
{ PseudoVID_V_MF4_MASK, VID_V, 0x6, 0x0 }, // 3009
|
|
{ PseudoVID_V_MF2, VID_V, 0x7, 0x0 }, // 3010
|
|
{ PseudoVID_V_MF2_MASK, VID_V, 0x7, 0x0 }, // 3011
|
|
{ PseudoVIOTA_M_M1, VIOTA_M, 0x0, 0x0 }, // 3012
|
|
{ PseudoVIOTA_M_M1_MASK, VIOTA_M, 0x0, 0x0 }, // 3013
|
|
{ PseudoVIOTA_M_M2, VIOTA_M, 0x1, 0x0 }, // 3014
|
|
{ PseudoVIOTA_M_M2_MASK, VIOTA_M, 0x1, 0x0 }, // 3015
|
|
{ PseudoVIOTA_M_M4, VIOTA_M, 0x2, 0x0 }, // 3016
|
|
{ PseudoVIOTA_M_M4_MASK, VIOTA_M, 0x2, 0x0 }, // 3017
|
|
{ PseudoVIOTA_M_M8, VIOTA_M, 0x3, 0x0 }, // 3018
|
|
{ PseudoVIOTA_M_M8_MASK, VIOTA_M, 0x3, 0x0 }, // 3019
|
|
{ PseudoVIOTA_M_MF8, VIOTA_M, 0x5, 0x0 }, // 3020
|
|
{ PseudoVIOTA_M_MF8_MASK, VIOTA_M, 0x5, 0x0 }, // 3021
|
|
{ PseudoVIOTA_M_MF4, VIOTA_M, 0x6, 0x0 }, // 3022
|
|
{ PseudoVIOTA_M_MF4_MASK, VIOTA_M, 0x6, 0x0 }, // 3023
|
|
{ PseudoVIOTA_M_MF2, VIOTA_M, 0x7, 0x0 }, // 3024
|
|
{ PseudoVIOTA_M_MF2_MASK, VIOTA_M, 0x7, 0x0 }, // 3025
|
|
{ PseudoVLE16FF_V_M1, VLE16FF_V, 0x0, 0x10 }, // 3026
|
|
{ PseudoVLE16FF_V_M1_MASK, VLE16FF_V, 0x0, 0x10 }, // 3027
|
|
{ PseudoVLE16FF_V_M2, VLE16FF_V, 0x1, 0x10 }, // 3028
|
|
{ PseudoVLE16FF_V_M2_MASK, VLE16FF_V, 0x1, 0x10 }, // 3029
|
|
{ PseudoVLE16FF_V_M4, VLE16FF_V, 0x2, 0x10 }, // 3030
|
|
{ PseudoVLE16FF_V_M4_MASK, VLE16FF_V, 0x2, 0x10 }, // 3031
|
|
{ PseudoVLE16FF_V_M8, VLE16FF_V, 0x3, 0x10 }, // 3032
|
|
{ PseudoVLE16FF_V_M8_MASK, VLE16FF_V, 0x3, 0x10 }, // 3033
|
|
{ PseudoVLE16FF_V_MF4, VLE16FF_V, 0x6, 0x10 }, // 3034
|
|
{ PseudoVLE16FF_V_MF4_MASK, VLE16FF_V, 0x6, 0x10 }, // 3035
|
|
{ PseudoVLE16FF_V_MF2, VLE16FF_V, 0x7, 0x10 }, // 3036
|
|
{ PseudoVLE16FF_V_MF2_MASK, VLE16FF_V, 0x7, 0x10 }, // 3037
|
|
{ PseudoVLE16_V_M1, VLE16_V, 0x0, 0x10 }, // 3038
|
|
{ PseudoVLE16_V_M1_MASK, VLE16_V, 0x0, 0x10 }, // 3039
|
|
{ PseudoVLE16_V_M2, VLE16_V, 0x1, 0x10 }, // 3040
|
|
{ PseudoVLE16_V_M2_MASK, VLE16_V, 0x1, 0x10 }, // 3041
|
|
{ PseudoVLE16_V_M4, VLE16_V, 0x2, 0x10 }, // 3042
|
|
{ PseudoVLE16_V_M4_MASK, VLE16_V, 0x2, 0x10 }, // 3043
|
|
{ PseudoVLE16_V_M8, VLE16_V, 0x3, 0x10 }, // 3044
|
|
{ PseudoVLE16_V_M8_MASK, VLE16_V, 0x3, 0x10 }, // 3045
|
|
{ PseudoVLE16_V_MF4, VLE16_V, 0x6, 0x10 }, // 3046
|
|
{ PseudoVLE16_V_MF4_MASK, VLE16_V, 0x6, 0x10 }, // 3047
|
|
{ PseudoVLE16_V_MF2, VLE16_V, 0x7, 0x10 }, // 3048
|
|
{ PseudoVLE16_V_MF2_MASK, VLE16_V, 0x7, 0x10 }, // 3049
|
|
{ PseudoVLE32FF_V_M1, VLE32FF_V, 0x0, 0x20 }, // 3050
|
|
{ PseudoVLE32FF_V_M1_MASK, VLE32FF_V, 0x0, 0x20 }, // 3051
|
|
{ PseudoVLE32FF_V_M2, VLE32FF_V, 0x1, 0x20 }, // 3052
|
|
{ PseudoVLE32FF_V_M2_MASK, VLE32FF_V, 0x1, 0x20 }, // 3053
|
|
{ PseudoVLE32FF_V_M4, VLE32FF_V, 0x2, 0x20 }, // 3054
|
|
{ PseudoVLE32FF_V_M4_MASK, VLE32FF_V, 0x2, 0x20 }, // 3055
|
|
{ PseudoVLE32FF_V_M8, VLE32FF_V, 0x3, 0x20 }, // 3056
|
|
{ PseudoVLE32FF_V_M8_MASK, VLE32FF_V, 0x3, 0x20 }, // 3057
|
|
{ PseudoVLE32FF_V_MF2, VLE32FF_V, 0x7, 0x20 }, // 3058
|
|
{ PseudoVLE32FF_V_MF2_MASK, VLE32FF_V, 0x7, 0x20 }, // 3059
|
|
{ PseudoVLE32_V_M1, VLE32_V, 0x0, 0x20 }, // 3060
|
|
{ PseudoVLE32_V_M1_MASK, VLE32_V, 0x0, 0x20 }, // 3061
|
|
{ PseudoVLE32_V_M2, VLE32_V, 0x1, 0x20 }, // 3062
|
|
{ PseudoVLE32_V_M2_MASK, VLE32_V, 0x1, 0x20 }, // 3063
|
|
{ PseudoVLE32_V_M4, VLE32_V, 0x2, 0x20 }, // 3064
|
|
{ PseudoVLE32_V_M4_MASK, VLE32_V, 0x2, 0x20 }, // 3065
|
|
{ PseudoVLE32_V_M8, VLE32_V, 0x3, 0x20 }, // 3066
|
|
{ PseudoVLE32_V_M8_MASK, VLE32_V, 0x3, 0x20 }, // 3067
|
|
{ PseudoVLE32_V_MF2, VLE32_V, 0x7, 0x20 }, // 3068
|
|
{ PseudoVLE32_V_MF2_MASK, VLE32_V, 0x7, 0x20 }, // 3069
|
|
{ PseudoVLE64FF_V_M1, VLE64FF_V, 0x0, 0x40 }, // 3070
|
|
{ PseudoVLE64FF_V_M1_MASK, VLE64FF_V, 0x0, 0x40 }, // 3071
|
|
{ PseudoVLE64FF_V_M2, VLE64FF_V, 0x1, 0x40 }, // 3072
|
|
{ PseudoVLE64FF_V_M2_MASK, VLE64FF_V, 0x1, 0x40 }, // 3073
|
|
{ PseudoVLE64FF_V_M4, VLE64FF_V, 0x2, 0x40 }, // 3074
|
|
{ PseudoVLE64FF_V_M4_MASK, VLE64FF_V, 0x2, 0x40 }, // 3075
|
|
{ PseudoVLE64FF_V_M8, VLE64FF_V, 0x3, 0x40 }, // 3076
|
|
{ PseudoVLE64FF_V_M8_MASK, VLE64FF_V, 0x3, 0x40 }, // 3077
|
|
{ PseudoVLE64_V_M1, VLE64_V, 0x0, 0x40 }, // 3078
|
|
{ PseudoVLE64_V_M1_MASK, VLE64_V, 0x0, 0x40 }, // 3079
|
|
{ PseudoVLE64_V_M2, VLE64_V, 0x1, 0x40 }, // 3080
|
|
{ PseudoVLE64_V_M2_MASK, VLE64_V, 0x1, 0x40 }, // 3081
|
|
{ PseudoVLE64_V_M4, VLE64_V, 0x2, 0x40 }, // 3082
|
|
{ PseudoVLE64_V_M4_MASK, VLE64_V, 0x2, 0x40 }, // 3083
|
|
{ PseudoVLE64_V_M8, VLE64_V, 0x3, 0x40 }, // 3084
|
|
{ PseudoVLE64_V_M8_MASK, VLE64_V, 0x3, 0x40 }, // 3085
|
|
{ PseudoVLE8FF_V_M1, VLE8FF_V, 0x0, 0x8 }, // 3086
|
|
{ PseudoVLE8FF_V_M1_MASK, VLE8FF_V, 0x0, 0x8 }, // 3087
|
|
{ PseudoVLE8FF_V_M2, VLE8FF_V, 0x1, 0x8 }, // 3088
|
|
{ PseudoVLE8FF_V_M2_MASK, VLE8FF_V, 0x1, 0x8 }, // 3089
|
|
{ PseudoVLE8FF_V_M4, VLE8FF_V, 0x2, 0x8 }, // 3090
|
|
{ PseudoVLE8FF_V_M4_MASK, VLE8FF_V, 0x2, 0x8 }, // 3091
|
|
{ PseudoVLE8FF_V_M8, VLE8FF_V, 0x3, 0x8 }, // 3092
|
|
{ PseudoVLE8FF_V_M8_MASK, VLE8FF_V, 0x3, 0x8 }, // 3093
|
|
{ PseudoVLE8FF_V_MF8, VLE8FF_V, 0x5, 0x8 }, // 3094
|
|
{ PseudoVLE8FF_V_MF8_MASK, VLE8FF_V, 0x5, 0x8 }, // 3095
|
|
{ PseudoVLE8FF_V_MF4, VLE8FF_V, 0x6, 0x8 }, // 3096
|
|
{ PseudoVLE8FF_V_MF4_MASK, VLE8FF_V, 0x6, 0x8 }, // 3097
|
|
{ PseudoVLE8FF_V_MF2, VLE8FF_V, 0x7, 0x8 }, // 3098
|
|
{ PseudoVLE8FF_V_MF2_MASK, VLE8FF_V, 0x7, 0x8 }, // 3099
|
|
{ PseudoVLE8_V_M1, VLE8_V, 0x0, 0x8 }, // 3100
|
|
{ PseudoVLE8_V_M1_MASK, VLE8_V, 0x0, 0x8 }, // 3101
|
|
{ PseudoVLE8_V_M2, VLE8_V, 0x1, 0x8 }, // 3102
|
|
{ PseudoVLE8_V_M2_MASK, VLE8_V, 0x1, 0x8 }, // 3103
|
|
{ PseudoVLE8_V_M4, VLE8_V, 0x2, 0x8 }, // 3104
|
|
{ PseudoVLE8_V_M4_MASK, VLE8_V, 0x2, 0x8 }, // 3105
|
|
{ PseudoVLE8_V_M8, VLE8_V, 0x3, 0x8 }, // 3106
|
|
{ PseudoVLE8_V_M8_MASK, VLE8_V, 0x3, 0x8 }, // 3107
|
|
{ PseudoVLE8_V_MF8, VLE8_V, 0x5, 0x8 }, // 3108
|
|
{ PseudoVLE8_V_MF8_MASK, VLE8_V, 0x5, 0x8 }, // 3109
|
|
{ PseudoVLE8_V_MF4, VLE8_V, 0x6, 0x8 }, // 3110
|
|
{ PseudoVLE8_V_MF4_MASK, VLE8_V, 0x6, 0x8 }, // 3111
|
|
{ PseudoVLE8_V_MF2, VLE8_V, 0x7, 0x8 }, // 3112
|
|
{ PseudoVLE8_V_MF2_MASK, VLE8_V, 0x7, 0x8 }, // 3113
|
|
{ PseudoVLM_V_B8, VLM_V, 0x0, 0x0 }, // 3114
|
|
{ PseudoVLM_V_B16, VLM_V, 0x1, 0x0 }, // 3115
|
|
{ PseudoVLM_V_B32, VLM_V, 0x2, 0x0 }, // 3116
|
|
{ PseudoVLM_V_B64, VLM_V, 0x3, 0x0 }, // 3117
|
|
{ PseudoVLM_V_B1, VLM_V, 0x5, 0x0 }, // 3118
|
|
{ PseudoVLM_V_B2, VLM_V, 0x6, 0x0 }, // 3119
|
|
{ PseudoVLM_V_B4, VLM_V, 0x7, 0x0 }, // 3120
|
|
{ PseudoVLOXEI16_V_M1_M1, VLOXEI16_V, 0x0, 0x0 }, // 3121
|
|
{ PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3122
|
|
{ PseudoVLOXEI16_V_M2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3123
|
|
{ PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3124
|
|
{ PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3125
|
|
{ PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3126
|
|
{ PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V, 0x0, 0x0 }, // 3127
|
|
{ PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3128
|
|
{ PseudoVLOXEI16_V_M1_M2, VLOXEI16_V, 0x1, 0x0 }, // 3129
|
|
{ PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3130
|
|
{ PseudoVLOXEI16_V_M2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3131
|
|
{ PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3132
|
|
{ PseudoVLOXEI16_V_M4_M2, VLOXEI16_V, 0x1, 0x0 }, // 3133
|
|
{ PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3134
|
|
{ PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3135
|
|
{ PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3136
|
|
{ PseudoVLOXEI16_V_M1_M4, VLOXEI16_V, 0x2, 0x0 }, // 3137
|
|
{ PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3138
|
|
{ PseudoVLOXEI16_V_M2_M4, VLOXEI16_V, 0x2, 0x0 }, // 3139
|
|
{ PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3140
|
|
{ PseudoVLOXEI16_V_M4_M4, VLOXEI16_V, 0x2, 0x0 }, // 3141
|
|
{ PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3142
|
|
{ PseudoVLOXEI16_V_M8_M4, VLOXEI16_V, 0x2, 0x0 }, // 3143
|
|
{ PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3144
|
|
{ PseudoVLOXEI16_V_M2_M8, VLOXEI16_V, 0x3, 0x0 }, // 3145
|
|
{ PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3146
|
|
{ PseudoVLOXEI16_V_M4_M8, VLOXEI16_V, 0x3, 0x0 }, // 3147
|
|
{ PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3148
|
|
{ PseudoVLOXEI16_V_M8_M8, VLOXEI16_V, 0x3, 0x0 }, // 3149
|
|
{ PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3150
|
|
{ PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V, 0x5, 0x0 }, // 3151
|
|
{ PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V, 0x5, 0x0 }, // 3152
|
|
{ PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3153
|
|
{ PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3154
|
|
{ PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3155
|
|
{ PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3156
|
|
{ PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3157
|
|
{ PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3158
|
|
{ PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3159
|
|
{ PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3160
|
|
{ PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3161
|
|
{ PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3162
|
|
{ PseudoVLOXEI32_V_M1_M1, VLOXEI32_V, 0x0, 0x0 }, // 3163
|
|
{ PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3164
|
|
{ PseudoVLOXEI32_V_M2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3165
|
|
{ PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3166
|
|
{ PseudoVLOXEI32_V_M4_M1, VLOXEI32_V, 0x0, 0x0 }, // 3167
|
|
{ PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3168
|
|
{ PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3169
|
|
{ PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3170
|
|
{ PseudoVLOXEI32_V_M1_M2, VLOXEI32_V, 0x1, 0x0 }, // 3171
|
|
{ PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3172
|
|
{ PseudoVLOXEI32_V_M2_M2, VLOXEI32_V, 0x1, 0x0 }, // 3173
|
|
{ PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3174
|
|
{ PseudoVLOXEI32_V_M4_M2, VLOXEI32_V, 0x1, 0x0 }, // 3175
|
|
{ PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3176
|
|
{ PseudoVLOXEI32_V_M8_M2, VLOXEI32_V, 0x1, 0x0 }, // 3177
|
|
{ PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3178
|
|
{ PseudoVLOXEI32_V_M2_M4, VLOXEI32_V, 0x2, 0x0 }, // 3179
|
|
{ PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3180
|
|
{ PseudoVLOXEI32_V_M4_M4, VLOXEI32_V, 0x2, 0x0 }, // 3181
|
|
{ PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3182
|
|
{ PseudoVLOXEI32_V_M8_M4, VLOXEI32_V, 0x2, 0x0 }, // 3183
|
|
{ PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3184
|
|
{ PseudoVLOXEI32_V_M4_M8, VLOXEI32_V, 0x3, 0x0 }, // 3185
|
|
{ PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3186
|
|
{ PseudoVLOXEI32_V_M8_M8, VLOXEI32_V, 0x3, 0x0 }, // 3187
|
|
{ PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3188
|
|
{ PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V, 0x5, 0x0 }, // 3189
|
|
{ PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V, 0x5, 0x0 }, // 3190
|
|
{ PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3191
|
|
{ PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3192
|
|
{ PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3193
|
|
{ PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3194
|
|
{ PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3195
|
|
{ PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3196
|
|
{ PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3197
|
|
{ PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3198
|
|
{ PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3199
|
|
{ PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3200
|
|
{ PseudoVLOXEI64_V_M1_M1, VLOXEI64_V, 0x0, 0x0 }, // 3201
|
|
{ PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3202
|
|
{ PseudoVLOXEI64_V_M2_M1, VLOXEI64_V, 0x0, 0x0 }, // 3203
|
|
{ PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3204
|
|
{ PseudoVLOXEI64_V_M4_M1, VLOXEI64_V, 0x0, 0x0 }, // 3205
|
|
{ PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3206
|
|
{ PseudoVLOXEI64_V_M8_M1, VLOXEI64_V, 0x0, 0x0 }, // 3207
|
|
{ PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3208
|
|
{ PseudoVLOXEI64_V_M2_M2, VLOXEI64_V, 0x1, 0x0 }, // 3209
|
|
{ PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3210
|
|
{ PseudoVLOXEI64_V_M4_M2, VLOXEI64_V, 0x1, 0x0 }, // 3211
|
|
{ PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3212
|
|
{ PseudoVLOXEI64_V_M8_M2, VLOXEI64_V, 0x1, 0x0 }, // 3213
|
|
{ PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3214
|
|
{ PseudoVLOXEI64_V_M4_M4, VLOXEI64_V, 0x2, 0x0 }, // 3215
|
|
{ PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3216
|
|
{ PseudoVLOXEI64_V_M8_M4, VLOXEI64_V, 0x2, 0x0 }, // 3217
|
|
{ PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3218
|
|
{ PseudoVLOXEI64_V_M8_M8, VLOXEI64_V, 0x3, 0x0 }, // 3219
|
|
{ PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V, 0x3, 0x0 }, // 3220
|
|
{ PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V, 0x5, 0x0 }, // 3221
|
|
{ PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V, 0x5, 0x0 }, // 3222
|
|
{ PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3223
|
|
{ PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3224
|
|
{ PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3225
|
|
{ PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3226
|
|
{ PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3227
|
|
{ PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3228
|
|
{ PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3229
|
|
{ PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3230
|
|
{ PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3231
|
|
{ PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3232
|
|
{ PseudoVLOXEI8_V_M1_M1, VLOXEI8_V, 0x0, 0x0 }, // 3233
|
|
{ PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3234
|
|
{ PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V, 0x0, 0x0 }, // 3235
|
|
{ PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3236
|
|
{ PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V, 0x0, 0x0 }, // 3237
|
|
{ PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3238
|
|
{ PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V, 0x0, 0x0 }, // 3239
|
|
{ PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3240
|
|
{ PseudoVLOXEI8_V_M1_M2, VLOXEI8_V, 0x1, 0x0 }, // 3241
|
|
{ PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3242
|
|
{ PseudoVLOXEI8_V_M2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3243
|
|
{ PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3244
|
|
{ PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3245
|
|
{ PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3246
|
|
{ PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V, 0x1, 0x0 }, // 3247
|
|
{ PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3248
|
|
{ PseudoVLOXEI8_V_M1_M4, VLOXEI8_V, 0x2, 0x0 }, // 3249
|
|
{ PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3250
|
|
{ PseudoVLOXEI8_V_M2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3251
|
|
{ PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3252
|
|
{ PseudoVLOXEI8_V_M4_M4, VLOXEI8_V, 0x2, 0x0 }, // 3253
|
|
{ PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3254
|
|
{ PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3255
|
|
{ PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3256
|
|
{ PseudoVLOXEI8_V_M1_M8, VLOXEI8_V, 0x3, 0x0 }, // 3257
|
|
{ PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3258
|
|
{ PseudoVLOXEI8_V_M2_M8, VLOXEI8_V, 0x3, 0x0 }, // 3259
|
|
{ PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3260
|
|
{ PseudoVLOXEI8_V_M4_M8, VLOXEI8_V, 0x3, 0x0 }, // 3261
|
|
{ PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3262
|
|
{ PseudoVLOXEI8_V_M8_M8, VLOXEI8_V, 0x3, 0x0 }, // 3263
|
|
{ PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3264
|
|
{ PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V, 0x5, 0x0 }, // 3265
|
|
{ PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V, 0x5, 0x0 }, // 3266
|
|
{ PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3267
|
|
{ PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3268
|
|
{ PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3269
|
|
{ PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3270
|
|
{ PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3271
|
|
{ PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3272
|
|
{ PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3273
|
|
{ PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3274
|
|
{ PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3275
|
|
{ PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3276
|
|
{ PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3277
|
|
{ PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3278
|
|
{ PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3279
|
|
{ PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3280
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3281
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3282
|
|
{ PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3283
|
|
{ PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3284
|
|
{ PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3285
|
|
{ PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3286
|
|
{ PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3287
|
|
{ PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3288
|
|
{ PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3289
|
|
{ PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3290
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3291
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3292
|
|
{ PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3293
|
|
{ PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3294
|
|
{ PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3295
|
|
{ PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3296
|
|
{ PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3297
|
|
{ PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3298
|
|
{ PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3299
|
|
{ PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3300
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3301
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3302
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3303
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3304
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3305
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3306
|
|
{ PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3307
|
|
{ PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3308
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3309
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3310
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3311
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3312
|
|
{ PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3313
|
|
{ PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3314
|
|
{ PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3315
|
|
{ PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3316
|
|
{ PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3317
|
|
{ PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3318
|
|
{ PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3319
|
|
{ PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3320
|
|
{ PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3321
|
|
{ PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3322
|
|
{ PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3323
|
|
{ PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3324
|
|
{ PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3325
|
|
{ PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3326
|
|
{ PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3327
|
|
{ PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3328
|
|
{ PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3329
|
|
{ PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3330
|
|
{ PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3331
|
|
{ PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3332
|
|
{ PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3333
|
|
{ PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3334
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3335
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3336
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3337
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3338
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3339
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3340
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3341
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3342
|
|
{ PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3343
|
|
{ PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3344
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3345
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3346
|
|
{ PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3347
|
|
{ PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3348
|
|
{ PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3349
|
|
{ PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3350
|
|
{ PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3351
|
|
{ PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3352
|
|
{ PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3353
|
|
{ PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3354
|
|
{ PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3355
|
|
{ PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3356
|
|
{ PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3357
|
|
{ PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3358
|
|
{ PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3359
|
|
{ PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3360
|
|
{ PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3361
|
|
{ PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3362
|
|
{ PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3363
|
|
{ PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3364
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3365
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3366
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3367
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3368
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3369
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3370
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3371
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3372
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3373
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3374
|
|
{ PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3375
|
|
{ PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3376
|
|
{ PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3377
|
|
{ PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3378
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3379
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3380
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3381
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3382
|
|
{ PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3383
|
|
{ PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3384
|
|
{ PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3385
|
|
{ PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3386
|
|
{ PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3387
|
|
{ PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3388
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3389
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3390
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3391
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3392
|
|
{ PseudoVLOXSEG2EI8_V_M1_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3393
|
|
{ PseudoVLOXSEG2EI8_V_M1_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3394
|
|
{ PseudoVLOXSEG2EI8_V_M2_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3395
|
|
{ PseudoVLOXSEG2EI8_V_M2_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3396
|
|
{ PseudoVLOXSEG2EI8_V_M4_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3397
|
|
{ PseudoVLOXSEG2EI8_V_M4_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3398
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3399
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3400
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF8, VLOXSEG2EI8_V, 0x5, 0x0 }, // 3401
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, VLOXSEG2EI8_V, 0x5, 0x0 }, // 3402
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF4, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3403
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3404
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF4, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3405
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3406
|
|
{ PseudoVLOXSEG2EI8_V_MF2_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3407
|
|
{ PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3408
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3409
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3410
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3411
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3412
|
|
{ PseudoVLOXSEG3EI16_V_M1_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3413
|
|
{ PseudoVLOXSEG3EI16_V_M1_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3414
|
|
{ PseudoVLOXSEG3EI16_V_M2_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3415
|
|
{ PseudoVLOXSEG3EI16_V_M2_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3416
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3417
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3418
|
|
{ PseudoVLOXSEG3EI16_V_MF4_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3419
|
|
{ PseudoVLOXSEG3EI16_V_MF4_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3420
|
|
{ PseudoVLOXSEG3EI16_V_M1_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3421
|
|
{ PseudoVLOXSEG3EI16_V_M1_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3422
|
|
{ PseudoVLOXSEG3EI16_V_M2_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3423
|
|
{ PseudoVLOXSEG3EI16_V_M2_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3424
|
|
{ PseudoVLOXSEG3EI16_V_M4_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3425
|
|
{ PseudoVLOXSEG3EI16_V_M4_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3426
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3427
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3428
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF8, VLOXSEG3EI16_V, 0x5, 0x0 }, // 3429
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, VLOXSEG3EI16_V, 0x5, 0x0 }, // 3430
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF4, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3431
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3432
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF4, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3433
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3434
|
|
{ PseudoVLOXSEG3EI16_V_M1_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3435
|
|
{ PseudoVLOXSEG3EI16_V_M1_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3436
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3437
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3438
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3439
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3440
|
|
{ PseudoVLOXSEG3EI32_V_M1_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3441
|
|
{ PseudoVLOXSEG3EI32_V_M1_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3442
|
|
{ PseudoVLOXSEG3EI32_V_M2_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3443
|
|
{ PseudoVLOXSEG3EI32_V_M2_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3444
|
|
{ PseudoVLOXSEG3EI32_V_M4_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3445
|
|
{ PseudoVLOXSEG3EI32_V_M4_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3446
|
|
{ PseudoVLOXSEG3EI32_V_MF2_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3447
|
|
{ PseudoVLOXSEG3EI32_V_MF2_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3448
|
|
{ PseudoVLOXSEG3EI32_V_M1_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3449
|
|
{ PseudoVLOXSEG3EI32_V_M1_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3450
|
|
{ PseudoVLOXSEG3EI32_V_M2_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3451
|
|
{ PseudoVLOXSEG3EI32_V_M2_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3452
|
|
{ PseudoVLOXSEG3EI32_V_M4_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3453
|
|
{ PseudoVLOXSEG3EI32_V_M4_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3454
|
|
{ PseudoVLOXSEG3EI32_V_M8_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3455
|
|
{ PseudoVLOXSEG3EI32_V_M8_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3456
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF8, VLOXSEG3EI32_V, 0x5, 0x0 }, // 3457
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, VLOXSEG3EI32_V, 0x5, 0x0 }, // 3458
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF4, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3459
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF4_MASK, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3460
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF4, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3461
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3462
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3463
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3464
|
|
{ PseudoVLOXSEG3EI32_V_M2_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3465
|
|
{ PseudoVLOXSEG3EI32_V_M2_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3466
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3467
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3468
|
|
{ PseudoVLOXSEG3EI64_V_M1_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3469
|
|
{ PseudoVLOXSEG3EI64_V_M1_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3470
|
|
{ PseudoVLOXSEG3EI64_V_M2_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3471
|
|
{ PseudoVLOXSEG3EI64_V_M2_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3472
|
|
{ PseudoVLOXSEG3EI64_V_M4_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3473
|
|
{ PseudoVLOXSEG3EI64_V_M4_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3474
|
|
{ PseudoVLOXSEG3EI64_V_M8_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3475
|
|
{ PseudoVLOXSEG3EI64_V_M8_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3476
|
|
{ PseudoVLOXSEG3EI64_V_M2_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3477
|
|
{ PseudoVLOXSEG3EI64_V_M2_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3478
|
|
{ PseudoVLOXSEG3EI64_V_M4_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3479
|
|
{ PseudoVLOXSEG3EI64_V_M4_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3480
|
|
{ PseudoVLOXSEG3EI64_V_M8_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3481
|
|
{ PseudoVLOXSEG3EI64_V_M8_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3482
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF8, VLOXSEG3EI64_V, 0x5, 0x0 }, // 3483
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF8_MASK, VLOXSEG3EI64_V, 0x5, 0x0 }, // 3484
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF4, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3485
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF4_MASK, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3486
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF4, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3487
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF4_MASK, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3488
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3489
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3490
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3491
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3492
|
|
{ PseudoVLOXSEG3EI64_V_M4_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3493
|
|
{ PseudoVLOXSEG3EI64_V_M4_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3494
|
|
{ PseudoVLOXSEG3EI8_V_M1_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3495
|
|
{ PseudoVLOXSEG3EI8_V_M1_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3496
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3497
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3498
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3499
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3500
|
|
{ PseudoVLOXSEG3EI8_V_MF8_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3501
|
|
{ PseudoVLOXSEG3EI8_V_MF8_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3502
|
|
{ PseudoVLOXSEG3EI8_V_M1_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3503
|
|
{ PseudoVLOXSEG3EI8_V_M1_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3504
|
|
{ PseudoVLOXSEG3EI8_V_M2_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3505
|
|
{ PseudoVLOXSEG3EI8_V_M2_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3506
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3507
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3508
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3509
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3510
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF8, VLOXSEG3EI8_V, 0x5, 0x0 }, // 3511
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, VLOXSEG3EI8_V, 0x5, 0x0 }, // 3512
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF4, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3513
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3514
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF4, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3515
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3516
|
|
{ PseudoVLOXSEG3EI8_V_MF2_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3517
|
|
{ PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3518
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3519
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3520
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3521
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3522
|
|
{ PseudoVLOXSEG4EI16_V_M1_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3523
|
|
{ PseudoVLOXSEG4EI16_V_M1_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3524
|
|
{ PseudoVLOXSEG4EI16_V_M2_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3525
|
|
{ PseudoVLOXSEG4EI16_V_M2_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3526
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3527
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3528
|
|
{ PseudoVLOXSEG4EI16_V_MF4_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3529
|
|
{ PseudoVLOXSEG4EI16_V_MF4_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3530
|
|
{ PseudoVLOXSEG4EI16_V_M1_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3531
|
|
{ PseudoVLOXSEG4EI16_V_M1_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3532
|
|
{ PseudoVLOXSEG4EI16_V_M2_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3533
|
|
{ PseudoVLOXSEG4EI16_V_M2_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3534
|
|
{ PseudoVLOXSEG4EI16_V_M4_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3535
|
|
{ PseudoVLOXSEG4EI16_V_M4_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3536
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3537
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3538
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF8, VLOXSEG4EI16_V, 0x5, 0x0 }, // 3539
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, VLOXSEG4EI16_V, 0x5, 0x0 }, // 3540
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF4, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3541
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3542
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF4, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3543
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3544
|
|
{ PseudoVLOXSEG4EI16_V_M1_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3545
|
|
{ PseudoVLOXSEG4EI16_V_M1_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3546
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3547
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3548
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3549
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3550
|
|
{ PseudoVLOXSEG4EI32_V_M1_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3551
|
|
{ PseudoVLOXSEG4EI32_V_M1_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3552
|
|
{ PseudoVLOXSEG4EI32_V_M2_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3553
|
|
{ PseudoVLOXSEG4EI32_V_M2_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3554
|
|
{ PseudoVLOXSEG4EI32_V_M4_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3555
|
|
{ PseudoVLOXSEG4EI32_V_M4_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3556
|
|
{ PseudoVLOXSEG4EI32_V_MF2_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3557
|
|
{ PseudoVLOXSEG4EI32_V_MF2_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3558
|
|
{ PseudoVLOXSEG4EI32_V_M1_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3559
|
|
{ PseudoVLOXSEG4EI32_V_M1_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3560
|
|
{ PseudoVLOXSEG4EI32_V_M2_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3561
|
|
{ PseudoVLOXSEG4EI32_V_M2_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3562
|
|
{ PseudoVLOXSEG4EI32_V_M4_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3563
|
|
{ PseudoVLOXSEG4EI32_V_M4_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3564
|
|
{ PseudoVLOXSEG4EI32_V_M8_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3565
|
|
{ PseudoVLOXSEG4EI32_V_M8_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3566
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF8, VLOXSEG4EI32_V, 0x5, 0x0 }, // 3567
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, VLOXSEG4EI32_V, 0x5, 0x0 }, // 3568
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF4, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3569
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF4_MASK, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3570
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF4, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3571
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3572
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3573
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3574
|
|
{ PseudoVLOXSEG4EI32_V_M2_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3575
|
|
{ PseudoVLOXSEG4EI32_V_M2_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3576
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3577
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3578
|
|
{ PseudoVLOXSEG4EI64_V_M1_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3579
|
|
{ PseudoVLOXSEG4EI64_V_M1_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3580
|
|
{ PseudoVLOXSEG4EI64_V_M2_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3581
|
|
{ PseudoVLOXSEG4EI64_V_M2_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3582
|
|
{ PseudoVLOXSEG4EI64_V_M4_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3583
|
|
{ PseudoVLOXSEG4EI64_V_M4_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3584
|
|
{ PseudoVLOXSEG4EI64_V_M8_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3585
|
|
{ PseudoVLOXSEG4EI64_V_M8_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3586
|
|
{ PseudoVLOXSEG4EI64_V_M2_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3587
|
|
{ PseudoVLOXSEG4EI64_V_M2_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3588
|
|
{ PseudoVLOXSEG4EI64_V_M4_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3589
|
|
{ PseudoVLOXSEG4EI64_V_M4_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3590
|
|
{ PseudoVLOXSEG4EI64_V_M8_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3591
|
|
{ PseudoVLOXSEG4EI64_V_M8_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3592
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF8, VLOXSEG4EI64_V, 0x5, 0x0 }, // 3593
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF8_MASK, VLOXSEG4EI64_V, 0x5, 0x0 }, // 3594
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF4, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3595
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF4_MASK, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3596
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF4, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3597
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF4_MASK, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3598
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3599
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3600
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3601
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3602
|
|
{ PseudoVLOXSEG4EI64_V_M4_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3603
|
|
{ PseudoVLOXSEG4EI64_V_M4_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3604
|
|
{ PseudoVLOXSEG4EI8_V_M1_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3605
|
|
{ PseudoVLOXSEG4EI8_V_M1_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3606
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3607
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3608
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3609
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3610
|
|
{ PseudoVLOXSEG4EI8_V_MF8_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3611
|
|
{ PseudoVLOXSEG4EI8_V_MF8_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3612
|
|
{ PseudoVLOXSEG4EI8_V_M1_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3613
|
|
{ PseudoVLOXSEG4EI8_V_M1_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3614
|
|
{ PseudoVLOXSEG4EI8_V_M2_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3615
|
|
{ PseudoVLOXSEG4EI8_V_M2_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3616
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3617
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3618
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3619
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3620
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF8, VLOXSEG4EI8_V, 0x5, 0x0 }, // 3621
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, VLOXSEG4EI8_V, 0x5, 0x0 }, // 3622
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF4, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3623
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3624
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF4, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3625
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3626
|
|
{ PseudoVLOXSEG4EI8_V_MF2_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3627
|
|
{ PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3628
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3629
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3630
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3631
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3632
|
|
{ PseudoVLOXSEG5EI16_V_M1_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3633
|
|
{ PseudoVLOXSEG5EI16_V_M1_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3634
|
|
{ PseudoVLOXSEG5EI16_V_M2_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3635
|
|
{ PseudoVLOXSEG5EI16_V_M2_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3636
|
|
{ PseudoVLOXSEG5EI16_V_MF2_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3637
|
|
{ PseudoVLOXSEG5EI16_V_MF2_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3638
|
|
{ PseudoVLOXSEG5EI16_V_MF4_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3639
|
|
{ PseudoVLOXSEG5EI16_V_MF4_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3640
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF8, VLOXSEG5EI16_V, 0x5, 0x0 }, // 3641
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, VLOXSEG5EI16_V, 0x5, 0x0 }, // 3642
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF4, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3643
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3644
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF4, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3645
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3646
|
|
{ PseudoVLOXSEG5EI16_V_M1_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3647
|
|
{ PseudoVLOXSEG5EI16_V_M1_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3648
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3649
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3650
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3651
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3652
|
|
{ PseudoVLOXSEG5EI32_V_M1_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3653
|
|
{ PseudoVLOXSEG5EI32_V_M1_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3654
|
|
{ PseudoVLOXSEG5EI32_V_M2_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3655
|
|
{ PseudoVLOXSEG5EI32_V_M2_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3656
|
|
{ PseudoVLOXSEG5EI32_V_M4_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3657
|
|
{ PseudoVLOXSEG5EI32_V_M4_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3658
|
|
{ PseudoVLOXSEG5EI32_V_MF2_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3659
|
|
{ PseudoVLOXSEG5EI32_V_MF2_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3660
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF8, VLOXSEG5EI32_V, 0x5, 0x0 }, // 3661
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, VLOXSEG5EI32_V, 0x5, 0x0 }, // 3662
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF4, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3663
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF4_MASK, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3664
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF4, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3665
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3666
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3667
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3668
|
|
{ PseudoVLOXSEG5EI32_V_M2_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3669
|
|
{ PseudoVLOXSEG5EI32_V_M2_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3670
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3671
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3672
|
|
{ PseudoVLOXSEG5EI64_V_M1_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3673
|
|
{ PseudoVLOXSEG5EI64_V_M1_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3674
|
|
{ PseudoVLOXSEG5EI64_V_M2_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3675
|
|
{ PseudoVLOXSEG5EI64_V_M2_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3676
|
|
{ PseudoVLOXSEG5EI64_V_M4_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3677
|
|
{ PseudoVLOXSEG5EI64_V_M4_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3678
|
|
{ PseudoVLOXSEG5EI64_V_M8_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3679
|
|
{ PseudoVLOXSEG5EI64_V_M8_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3680
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF8, VLOXSEG5EI64_V, 0x5, 0x0 }, // 3681
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF8_MASK, VLOXSEG5EI64_V, 0x5, 0x0 }, // 3682
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF4, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3683
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF4_MASK, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3684
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF4, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3685
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF4_MASK, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3686
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3687
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3688
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3689
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3690
|
|
{ PseudoVLOXSEG5EI64_V_M4_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3691
|
|
{ PseudoVLOXSEG5EI64_V_M4_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3692
|
|
{ PseudoVLOXSEG5EI8_V_M1_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3693
|
|
{ PseudoVLOXSEG5EI8_V_M1_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3694
|
|
{ PseudoVLOXSEG5EI8_V_MF2_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3695
|
|
{ PseudoVLOXSEG5EI8_V_MF2_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3696
|
|
{ PseudoVLOXSEG5EI8_V_MF4_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3697
|
|
{ PseudoVLOXSEG5EI8_V_MF4_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3698
|
|
{ PseudoVLOXSEG5EI8_V_MF8_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3699
|
|
{ PseudoVLOXSEG5EI8_V_MF8_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3700
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF8, VLOXSEG5EI8_V, 0x5, 0x0 }, // 3701
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, VLOXSEG5EI8_V, 0x5, 0x0 }, // 3702
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF4, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3703
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3704
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF4, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3705
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3706
|
|
{ PseudoVLOXSEG5EI8_V_MF2_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3707
|
|
{ PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3708
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3709
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3710
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3711
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3712
|
|
{ PseudoVLOXSEG6EI16_V_M1_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3713
|
|
{ PseudoVLOXSEG6EI16_V_M1_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3714
|
|
{ PseudoVLOXSEG6EI16_V_M2_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3715
|
|
{ PseudoVLOXSEG6EI16_V_M2_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3716
|
|
{ PseudoVLOXSEG6EI16_V_MF2_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3717
|
|
{ PseudoVLOXSEG6EI16_V_MF2_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3718
|
|
{ PseudoVLOXSEG6EI16_V_MF4_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3719
|
|
{ PseudoVLOXSEG6EI16_V_MF4_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3720
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF8, VLOXSEG6EI16_V, 0x5, 0x0 }, // 3721
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, VLOXSEG6EI16_V, 0x5, 0x0 }, // 3722
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF4, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3723
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3724
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF4, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3725
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3726
|
|
{ PseudoVLOXSEG6EI16_V_M1_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3727
|
|
{ PseudoVLOXSEG6EI16_V_M1_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3728
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3729
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3730
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3731
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3732
|
|
{ PseudoVLOXSEG6EI32_V_M1_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3733
|
|
{ PseudoVLOXSEG6EI32_V_M1_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3734
|
|
{ PseudoVLOXSEG6EI32_V_M2_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3735
|
|
{ PseudoVLOXSEG6EI32_V_M2_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3736
|
|
{ PseudoVLOXSEG6EI32_V_M4_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3737
|
|
{ PseudoVLOXSEG6EI32_V_M4_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3738
|
|
{ PseudoVLOXSEG6EI32_V_MF2_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3739
|
|
{ PseudoVLOXSEG6EI32_V_MF2_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3740
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF8, VLOXSEG6EI32_V, 0x5, 0x0 }, // 3741
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, VLOXSEG6EI32_V, 0x5, 0x0 }, // 3742
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF4, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3743
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF4_MASK, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3744
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF4, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3745
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3746
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3747
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3748
|
|
{ PseudoVLOXSEG6EI32_V_M2_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3749
|
|
{ PseudoVLOXSEG6EI32_V_M2_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3750
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3751
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3752
|
|
{ PseudoVLOXSEG6EI64_V_M1_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3753
|
|
{ PseudoVLOXSEG6EI64_V_M1_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3754
|
|
{ PseudoVLOXSEG6EI64_V_M2_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3755
|
|
{ PseudoVLOXSEG6EI64_V_M2_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3756
|
|
{ PseudoVLOXSEG6EI64_V_M4_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3757
|
|
{ PseudoVLOXSEG6EI64_V_M4_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3758
|
|
{ PseudoVLOXSEG6EI64_V_M8_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3759
|
|
{ PseudoVLOXSEG6EI64_V_M8_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3760
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF8, VLOXSEG6EI64_V, 0x5, 0x0 }, // 3761
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF8_MASK, VLOXSEG6EI64_V, 0x5, 0x0 }, // 3762
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF4, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3763
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF4_MASK, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3764
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF4, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3765
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF4_MASK, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3766
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3767
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3768
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3769
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3770
|
|
{ PseudoVLOXSEG6EI64_V_M4_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3771
|
|
{ PseudoVLOXSEG6EI64_V_M4_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3772
|
|
{ PseudoVLOXSEG6EI8_V_M1_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3773
|
|
{ PseudoVLOXSEG6EI8_V_M1_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3774
|
|
{ PseudoVLOXSEG6EI8_V_MF2_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3775
|
|
{ PseudoVLOXSEG6EI8_V_MF2_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3776
|
|
{ PseudoVLOXSEG6EI8_V_MF4_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3777
|
|
{ PseudoVLOXSEG6EI8_V_MF4_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3778
|
|
{ PseudoVLOXSEG6EI8_V_MF8_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3779
|
|
{ PseudoVLOXSEG6EI8_V_MF8_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3780
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF8, VLOXSEG6EI8_V, 0x5, 0x0 }, // 3781
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, VLOXSEG6EI8_V, 0x5, 0x0 }, // 3782
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF4, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3783
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3784
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF4, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3785
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3786
|
|
{ PseudoVLOXSEG6EI8_V_MF2_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3787
|
|
{ PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3788
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3789
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3790
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3791
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3792
|
|
{ PseudoVLOXSEG7EI16_V_M1_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3793
|
|
{ PseudoVLOXSEG7EI16_V_M1_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3794
|
|
{ PseudoVLOXSEG7EI16_V_M2_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3795
|
|
{ PseudoVLOXSEG7EI16_V_M2_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3796
|
|
{ PseudoVLOXSEG7EI16_V_MF2_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3797
|
|
{ PseudoVLOXSEG7EI16_V_MF2_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3798
|
|
{ PseudoVLOXSEG7EI16_V_MF4_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3799
|
|
{ PseudoVLOXSEG7EI16_V_MF4_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3800
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF8, VLOXSEG7EI16_V, 0x5, 0x0 }, // 3801
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, VLOXSEG7EI16_V, 0x5, 0x0 }, // 3802
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF4, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3803
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3804
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF4, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3805
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3806
|
|
{ PseudoVLOXSEG7EI16_V_M1_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3807
|
|
{ PseudoVLOXSEG7EI16_V_M1_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3808
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3809
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3810
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3811
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3812
|
|
{ PseudoVLOXSEG7EI32_V_M1_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3813
|
|
{ PseudoVLOXSEG7EI32_V_M1_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3814
|
|
{ PseudoVLOXSEG7EI32_V_M2_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3815
|
|
{ PseudoVLOXSEG7EI32_V_M2_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3816
|
|
{ PseudoVLOXSEG7EI32_V_M4_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3817
|
|
{ PseudoVLOXSEG7EI32_V_M4_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3818
|
|
{ PseudoVLOXSEG7EI32_V_MF2_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3819
|
|
{ PseudoVLOXSEG7EI32_V_MF2_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3820
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF8, VLOXSEG7EI32_V, 0x5, 0x0 }, // 3821
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, VLOXSEG7EI32_V, 0x5, 0x0 }, // 3822
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF4, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3823
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF4_MASK, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3824
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF4, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3825
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3826
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3827
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3828
|
|
{ PseudoVLOXSEG7EI32_V_M2_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3829
|
|
{ PseudoVLOXSEG7EI32_V_M2_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3830
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3831
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3832
|
|
{ PseudoVLOXSEG7EI64_V_M1_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3833
|
|
{ PseudoVLOXSEG7EI64_V_M1_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3834
|
|
{ PseudoVLOXSEG7EI64_V_M2_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3835
|
|
{ PseudoVLOXSEG7EI64_V_M2_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3836
|
|
{ PseudoVLOXSEG7EI64_V_M4_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3837
|
|
{ PseudoVLOXSEG7EI64_V_M4_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3838
|
|
{ PseudoVLOXSEG7EI64_V_M8_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3839
|
|
{ PseudoVLOXSEG7EI64_V_M8_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3840
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF8, VLOXSEG7EI64_V, 0x5, 0x0 }, // 3841
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF8_MASK, VLOXSEG7EI64_V, 0x5, 0x0 }, // 3842
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF4, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3843
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF4_MASK, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3844
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF4, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3845
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF4_MASK, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3846
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3847
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3848
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3849
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3850
|
|
{ PseudoVLOXSEG7EI64_V_M4_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3851
|
|
{ PseudoVLOXSEG7EI64_V_M4_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3852
|
|
{ PseudoVLOXSEG7EI8_V_M1_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3853
|
|
{ PseudoVLOXSEG7EI8_V_M1_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3854
|
|
{ PseudoVLOXSEG7EI8_V_MF2_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3855
|
|
{ PseudoVLOXSEG7EI8_V_MF2_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3856
|
|
{ PseudoVLOXSEG7EI8_V_MF4_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3857
|
|
{ PseudoVLOXSEG7EI8_V_MF4_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3858
|
|
{ PseudoVLOXSEG7EI8_V_MF8_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3859
|
|
{ PseudoVLOXSEG7EI8_V_MF8_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3860
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF8, VLOXSEG7EI8_V, 0x5, 0x0 }, // 3861
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, VLOXSEG7EI8_V, 0x5, 0x0 }, // 3862
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF4, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3863
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3864
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF4, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3865
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3866
|
|
{ PseudoVLOXSEG7EI8_V_MF2_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3867
|
|
{ PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3868
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3869
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3870
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3871
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3872
|
|
{ PseudoVLOXSEG8EI16_V_M1_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3873
|
|
{ PseudoVLOXSEG8EI16_V_M1_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3874
|
|
{ PseudoVLOXSEG8EI16_V_M2_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3875
|
|
{ PseudoVLOXSEG8EI16_V_M2_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3876
|
|
{ PseudoVLOXSEG8EI16_V_MF2_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3877
|
|
{ PseudoVLOXSEG8EI16_V_MF2_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3878
|
|
{ PseudoVLOXSEG8EI16_V_MF4_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3879
|
|
{ PseudoVLOXSEG8EI16_V_MF4_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3880
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF8, VLOXSEG8EI16_V, 0x5, 0x0 }, // 3881
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, VLOXSEG8EI16_V, 0x5, 0x0 }, // 3882
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF4, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3883
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3884
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF4, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3885
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3886
|
|
{ PseudoVLOXSEG8EI16_V_M1_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3887
|
|
{ PseudoVLOXSEG8EI16_V_M1_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3888
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3889
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3890
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3891
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3892
|
|
{ PseudoVLOXSEG8EI32_V_M1_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3893
|
|
{ PseudoVLOXSEG8EI32_V_M1_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3894
|
|
{ PseudoVLOXSEG8EI32_V_M2_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3895
|
|
{ PseudoVLOXSEG8EI32_V_M2_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3896
|
|
{ PseudoVLOXSEG8EI32_V_M4_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3897
|
|
{ PseudoVLOXSEG8EI32_V_M4_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3898
|
|
{ PseudoVLOXSEG8EI32_V_MF2_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3899
|
|
{ PseudoVLOXSEG8EI32_V_MF2_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3900
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF8, VLOXSEG8EI32_V, 0x5, 0x0 }, // 3901
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, VLOXSEG8EI32_V, 0x5, 0x0 }, // 3902
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF4, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3903
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF4_MASK, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3904
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF4, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3905
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3906
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3907
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3908
|
|
{ PseudoVLOXSEG8EI32_V_M2_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3909
|
|
{ PseudoVLOXSEG8EI32_V_M2_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3910
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3911
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3912
|
|
{ PseudoVLOXSEG8EI64_V_M1_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3913
|
|
{ PseudoVLOXSEG8EI64_V_M1_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3914
|
|
{ PseudoVLOXSEG8EI64_V_M2_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3915
|
|
{ PseudoVLOXSEG8EI64_V_M2_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3916
|
|
{ PseudoVLOXSEG8EI64_V_M4_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3917
|
|
{ PseudoVLOXSEG8EI64_V_M4_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3918
|
|
{ PseudoVLOXSEG8EI64_V_M8_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3919
|
|
{ PseudoVLOXSEG8EI64_V_M8_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3920
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF8, VLOXSEG8EI64_V, 0x5, 0x0 }, // 3921
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF8_MASK, VLOXSEG8EI64_V, 0x5, 0x0 }, // 3922
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF4, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3923
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF4_MASK, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3924
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF4, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3925
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF4_MASK, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3926
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3927
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3928
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3929
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3930
|
|
{ PseudoVLOXSEG8EI64_V_M4_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3931
|
|
{ PseudoVLOXSEG8EI64_V_M4_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3932
|
|
{ PseudoVLOXSEG8EI8_V_M1_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3933
|
|
{ PseudoVLOXSEG8EI8_V_M1_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3934
|
|
{ PseudoVLOXSEG8EI8_V_MF2_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3935
|
|
{ PseudoVLOXSEG8EI8_V_MF2_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3936
|
|
{ PseudoVLOXSEG8EI8_V_MF4_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3937
|
|
{ PseudoVLOXSEG8EI8_V_MF4_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3938
|
|
{ PseudoVLOXSEG8EI8_V_MF8_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3939
|
|
{ PseudoVLOXSEG8EI8_V_MF8_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3940
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF8, VLOXSEG8EI8_V, 0x5, 0x0 }, // 3941
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, VLOXSEG8EI8_V, 0x5, 0x0 }, // 3942
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF4, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3943
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3944
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF4, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3945
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3946
|
|
{ PseudoVLOXSEG8EI8_V_MF2_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3947
|
|
{ PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3948
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3949
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3950
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3951
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3952
|
|
{ PseudoVLSE16_V_M1, VLSE16_V, 0x0, 0x10 }, // 3953
|
|
{ PseudoVLSE16_V_M1_MASK, VLSE16_V, 0x0, 0x10 }, // 3954
|
|
{ PseudoVLSE16_V_M2, VLSE16_V, 0x1, 0x10 }, // 3955
|
|
{ PseudoVLSE16_V_M2_MASK, VLSE16_V, 0x1, 0x10 }, // 3956
|
|
{ PseudoVLSE16_V_M4, VLSE16_V, 0x2, 0x10 }, // 3957
|
|
{ PseudoVLSE16_V_M4_MASK, VLSE16_V, 0x2, 0x10 }, // 3958
|
|
{ PseudoVLSE16_V_M8, VLSE16_V, 0x3, 0x10 }, // 3959
|
|
{ PseudoVLSE16_V_M8_MASK, VLSE16_V, 0x3, 0x10 }, // 3960
|
|
{ PseudoVLSE16_V_MF4, VLSE16_V, 0x6, 0x10 }, // 3961
|
|
{ PseudoVLSE16_V_MF4_MASK, VLSE16_V, 0x6, 0x10 }, // 3962
|
|
{ PseudoVLSE16_V_MF2, VLSE16_V, 0x7, 0x10 }, // 3963
|
|
{ PseudoVLSE16_V_MF2_MASK, VLSE16_V, 0x7, 0x10 }, // 3964
|
|
{ PseudoVLSE32_V_M1, VLSE32_V, 0x0, 0x20 }, // 3965
|
|
{ PseudoVLSE32_V_M1_MASK, VLSE32_V, 0x0, 0x20 }, // 3966
|
|
{ PseudoVLSE32_V_M2, VLSE32_V, 0x1, 0x20 }, // 3967
|
|
{ PseudoVLSE32_V_M2_MASK, VLSE32_V, 0x1, 0x20 }, // 3968
|
|
{ PseudoVLSE32_V_M4, VLSE32_V, 0x2, 0x20 }, // 3969
|
|
{ PseudoVLSE32_V_M4_MASK, VLSE32_V, 0x2, 0x20 }, // 3970
|
|
{ PseudoVLSE32_V_M8, VLSE32_V, 0x3, 0x20 }, // 3971
|
|
{ PseudoVLSE32_V_M8_MASK, VLSE32_V, 0x3, 0x20 }, // 3972
|
|
{ PseudoVLSE32_V_MF2, VLSE32_V, 0x7, 0x20 }, // 3973
|
|
{ PseudoVLSE32_V_MF2_MASK, VLSE32_V, 0x7, 0x20 }, // 3974
|
|
{ PseudoVLSE64_V_M1, VLSE64_V, 0x0, 0x40 }, // 3975
|
|
{ PseudoVLSE64_V_M1_MASK, VLSE64_V, 0x0, 0x40 }, // 3976
|
|
{ PseudoVLSE64_V_M2, VLSE64_V, 0x1, 0x40 }, // 3977
|
|
{ PseudoVLSE64_V_M2_MASK, VLSE64_V, 0x1, 0x40 }, // 3978
|
|
{ PseudoVLSE64_V_M4, VLSE64_V, 0x2, 0x40 }, // 3979
|
|
{ PseudoVLSE64_V_M4_MASK, VLSE64_V, 0x2, 0x40 }, // 3980
|
|
{ PseudoVLSE64_V_M8, VLSE64_V, 0x3, 0x40 }, // 3981
|
|
{ PseudoVLSE64_V_M8_MASK, VLSE64_V, 0x3, 0x40 }, // 3982
|
|
{ PseudoVLSE8_V_M1, VLSE8_V, 0x0, 0x8 }, // 3983
|
|
{ PseudoVLSE8_V_M1_MASK, VLSE8_V, 0x0, 0x8 }, // 3984
|
|
{ PseudoVLSE8_V_M2, VLSE8_V, 0x1, 0x8 }, // 3985
|
|
{ PseudoVLSE8_V_M2_MASK, VLSE8_V, 0x1, 0x8 }, // 3986
|
|
{ PseudoVLSE8_V_M4, VLSE8_V, 0x2, 0x8 }, // 3987
|
|
{ PseudoVLSE8_V_M4_MASK, VLSE8_V, 0x2, 0x8 }, // 3988
|
|
{ PseudoVLSE8_V_M8, VLSE8_V, 0x3, 0x8 }, // 3989
|
|
{ PseudoVLSE8_V_M8_MASK, VLSE8_V, 0x3, 0x8 }, // 3990
|
|
{ PseudoVLSE8_V_MF8, VLSE8_V, 0x5, 0x8 }, // 3991
|
|
{ PseudoVLSE8_V_MF8_MASK, VLSE8_V, 0x5, 0x8 }, // 3992
|
|
{ PseudoVLSE8_V_MF4, VLSE8_V, 0x6, 0x8 }, // 3993
|
|
{ PseudoVLSE8_V_MF4_MASK, VLSE8_V, 0x6, 0x8 }, // 3994
|
|
{ PseudoVLSE8_V_MF2, VLSE8_V, 0x7, 0x8 }, // 3995
|
|
{ PseudoVLSE8_V_MF2_MASK, VLSE8_V, 0x7, 0x8 }, // 3996
|
|
{ PseudoVLSEG2E16FF_V_M1, VLSEG2E16FF_V, 0x0, 0x10 }, // 3997
|
|
{ PseudoVLSEG2E16FF_V_M1_MASK, VLSEG2E16FF_V, 0x0, 0x10 }, // 3998
|
|
{ PseudoVLSEG2E16FF_V_M2, VLSEG2E16FF_V, 0x1, 0x10 }, // 3999
|
|
{ PseudoVLSEG2E16FF_V_M2_MASK, VLSEG2E16FF_V, 0x1, 0x10 }, // 4000
|
|
{ PseudoVLSEG2E16FF_V_M4, VLSEG2E16FF_V, 0x2, 0x10 }, // 4001
|
|
{ PseudoVLSEG2E16FF_V_M4_MASK, VLSEG2E16FF_V, 0x2, 0x10 }, // 4002
|
|
{ PseudoVLSEG2E16FF_V_MF4, VLSEG2E16FF_V, 0x6, 0x10 }, // 4003
|
|
{ PseudoVLSEG2E16FF_V_MF4_MASK, VLSEG2E16FF_V, 0x6, 0x10 }, // 4004
|
|
{ PseudoVLSEG2E16FF_V_MF2, VLSEG2E16FF_V, 0x7, 0x10 }, // 4005
|
|
{ PseudoVLSEG2E16FF_V_MF2_MASK, VLSEG2E16FF_V, 0x7, 0x10 }, // 4006
|
|
{ PseudoVLSEG2E16_V_M1, VLSEG2E16_V, 0x0, 0x10 }, // 4007
|
|
{ PseudoVLSEG2E16_V_M1_MASK, VLSEG2E16_V, 0x0, 0x10 }, // 4008
|
|
{ PseudoVLSEG2E16_V_M2, VLSEG2E16_V, 0x1, 0x10 }, // 4009
|
|
{ PseudoVLSEG2E16_V_M2_MASK, VLSEG2E16_V, 0x1, 0x10 }, // 4010
|
|
{ PseudoVLSEG2E16_V_M4, VLSEG2E16_V, 0x2, 0x10 }, // 4011
|
|
{ PseudoVLSEG2E16_V_M4_MASK, VLSEG2E16_V, 0x2, 0x10 }, // 4012
|
|
{ PseudoVLSEG2E16_V_MF4, VLSEG2E16_V, 0x6, 0x10 }, // 4013
|
|
{ PseudoVLSEG2E16_V_MF4_MASK, VLSEG2E16_V, 0x6, 0x10 }, // 4014
|
|
{ PseudoVLSEG2E16_V_MF2, VLSEG2E16_V, 0x7, 0x10 }, // 4015
|
|
{ PseudoVLSEG2E16_V_MF2_MASK, VLSEG2E16_V, 0x7, 0x10 }, // 4016
|
|
{ PseudoVLSEG2E32FF_V_M1, VLSEG2E32FF_V, 0x0, 0x20 }, // 4017
|
|
{ PseudoVLSEG2E32FF_V_M1_MASK, VLSEG2E32FF_V, 0x0, 0x20 }, // 4018
|
|
{ PseudoVLSEG2E32FF_V_M2, VLSEG2E32FF_V, 0x1, 0x20 }, // 4019
|
|
{ PseudoVLSEG2E32FF_V_M2_MASK, VLSEG2E32FF_V, 0x1, 0x20 }, // 4020
|
|
{ PseudoVLSEG2E32FF_V_M4, VLSEG2E32FF_V, 0x2, 0x20 }, // 4021
|
|
{ PseudoVLSEG2E32FF_V_M4_MASK, VLSEG2E32FF_V, 0x2, 0x20 }, // 4022
|
|
{ PseudoVLSEG2E32FF_V_MF2, VLSEG2E32FF_V, 0x7, 0x20 }, // 4023
|
|
{ PseudoVLSEG2E32FF_V_MF2_MASK, VLSEG2E32FF_V, 0x7, 0x20 }, // 4024
|
|
{ PseudoVLSEG2E32_V_M1, VLSEG2E32_V, 0x0, 0x20 }, // 4025
|
|
{ PseudoVLSEG2E32_V_M1_MASK, VLSEG2E32_V, 0x0, 0x20 }, // 4026
|
|
{ PseudoVLSEG2E32_V_M2, VLSEG2E32_V, 0x1, 0x20 }, // 4027
|
|
{ PseudoVLSEG2E32_V_M2_MASK, VLSEG2E32_V, 0x1, 0x20 }, // 4028
|
|
{ PseudoVLSEG2E32_V_M4, VLSEG2E32_V, 0x2, 0x20 }, // 4029
|
|
{ PseudoVLSEG2E32_V_M4_MASK, VLSEG2E32_V, 0x2, 0x20 }, // 4030
|
|
{ PseudoVLSEG2E32_V_MF2, VLSEG2E32_V, 0x7, 0x20 }, // 4031
|
|
{ PseudoVLSEG2E32_V_MF2_MASK, VLSEG2E32_V, 0x7, 0x20 }, // 4032
|
|
{ PseudoVLSEG2E64FF_V_M1, VLSEG2E64FF_V, 0x0, 0x40 }, // 4033
|
|
{ PseudoVLSEG2E64FF_V_M1_MASK, VLSEG2E64FF_V, 0x0, 0x40 }, // 4034
|
|
{ PseudoVLSEG2E64FF_V_M2, VLSEG2E64FF_V, 0x1, 0x40 }, // 4035
|
|
{ PseudoVLSEG2E64FF_V_M2_MASK, VLSEG2E64FF_V, 0x1, 0x40 }, // 4036
|
|
{ PseudoVLSEG2E64FF_V_M4, VLSEG2E64FF_V, 0x2, 0x40 }, // 4037
|
|
{ PseudoVLSEG2E64FF_V_M4_MASK, VLSEG2E64FF_V, 0x2, 0x40 }, // 4038
|
|
{ PseudoVLSEG2E64_V_M1, VLSEG2E64_V, 0x0, 0x40 }, // 4039
|
|
{ PseudoVLSEG2E64_V_M1_MASK, VLSEG2E64_V, 0x0, 0x40 }, // 4040
|
|
{ PseudoVLSEG2E64_V_M2, VLSEG2E64_V, 0x1, 0x40 }, // 4041
|
|
{ PseudoVLSEG2E64_V_M2_MASK, VLSEG2E64_V, 0x1, 0x40 }, // 4042
|
|
{ PseudoVLSEG2E64_V_M4, VLSEG2E64_V, 0x2, 0x40 }, // 4043
|
|
{ PseudoVLSEG2E64_V_M4_MASK, VLSEG2E64_V, 0x2, 0x40 }, // 4044
|
|
{ PseudoVLSEG2E8FF_V_M1, VLSEG2E8FF_V, 0x0, 0x8 }, // 4045
|
|
{ PseudoVLSEG2E8FF_V_M1_MASK, VLSEG2E8FF_V, 0x0, 0x8 }, // 4046
|
|
{ PseudoVLSEG2E8FF_V_M2, VLSEG2E8FF_V, 0x1, 0x8 }, // 4047
|
|
{ PseudoVLSEG2E8FF_V_M2_MASK, VLSEG2E8FF_V, 0x1, 0x8 }, // 4048
|
|
{ PseudoVLSEG2E8FF_V_M4, VLSEG2E8FF_V, 0x2, 0x8 }, // 4049
|
|
{ PseudoVLSEG2E8FF_V_M4_MASK, VLSEG2E8FF_V, 0x2, 0x8 }, // 4050
|
|
{ PseudoVLSEG2E8FF_V_MF8, VLSEG2E8FF_V, 0x5, 0x8 }, // 4051
|
|
{ PseudoVLSEG2E8FF_V_MF8_MASK, VLSEG2E8FF_V, 0x5, 0x8 }, // 4052
|
|
{ PseudoVLSEG2E8FF_V_MF4, VLSEG2E8FF_V, 0x6, 0x8 }, // 4053
|
|
{ PseudoVLSEG2E8FF_V_MF4_MASK, VLSEG2E8FF_V, 0x6, 0x8 }, // 4054
|
|
{ PseudoVLSEG2E8FF_V_MF2, VLSEG2E8FF_V, 0x7, 0x8 }, // 4055
|
|
{ PseudoVLSEG2E8FF_V_MF2_MASK, VLSEG2E8FF_V, 0x7, 0x8 }, // 4056
|
|
{ PseudoVLSEG2E8_V_M1, VLSEG2E8_V, 0x0, 0x8 }, // 4057
|
|
{ PseudoVLSEG2E8_V_M1_MASK, VLSEG2E8_V, 0x0, 0x8 }, // 4058
|
|
{ PseudoVLSEG2E8_V_M2, VLSEG2E8_V, 0x1, 0x8 }, // 4059
|
|
{ PseudoVLSEG2E8_V_M2_MASK, VLSEG2E8_V, 0x1, 0x8 }, // 4060
|
|
{ PseudoVLSEG2E8_V_M4, VLSEG2E8_V, 0x2, 0x8 }, // 4061
|
|
{ PseudoVLSEG2E8_V_M4_MASK, VLSEG2E8_V, 0x2, 0x8 }, // 4062
|
|
{ PseudoVLSEG2E8_V_MF8, VLSEG2E8_V, 0x5, 0x8 }, // 4063
|
|
{ PseudoVLSEG2E8_V_MF8_MASK, VLSEG2E8_V, 0x5, 0x8 }, // 4064
|
|
{ PseudoVLSEG2E8_V_MF4, VLSEG2E8_V, 0x6, 0x8 }, // 4065
|
|
{ PseudoVLSEG2E8_V_MF4_MASK, VLSEG2E8_V, 0x6, 0x8 }, // 4066
|
|
{ PseudoVLSEG2E8_V_MF2, VLSEG2E8_V, 0x7, 0x8 }, // 4067
|
|
{ PseudoVLSEG2E8_V_MF2_MASK, VLSEG2E8_V, 0x7, 0x8 }, // 4068
|
|
{ PseudoVLSEG3E16FF_V_M1, VLSEG3E16FF_V, 0x0, 0x10 }, // 4069
|
|
{ PseudoVLSEG3E16FF_V_M1_MASK, VLSEG3E16FF_V, 0x0, 0x10 }, // 4070
|
|
{ PseudoVLSEG3E16FF_V_M2, VLSEG3E16FF_V, 0x1, 0x10 }, // 4071
|
|
{ PseudoVLSEG3E16FF_V_M2_MASK, VLSEG3E16FF_V, 0x1, 0x10 }, // 4072
|
|
{ PseudoVLSEG3E16FF_V_MF4, VLSEG3E16FF_V, 0x6, 0x10 }, // 4073
|
|
{ PseudoVLSEG3E16FF_V_MF4_MASK, VLSEG3E16FF_V, 0x6, 0x10 }, // 4074
|
|
{ PseudoVLSEG3E16FF_V_MF2, VLSEG3E16FF_V, 0x7, 0x10 }, // 4075
|
|
{ PseudoVLSEG3E16FF_V_MF2_MASK, VLSEG3E16FF_V, 0x7, 0x10 }, // 4076
|
|
{ PseudoVLSEG3E16_V_M1, VLSEG3E16_V, 0x0, 0x10 }, // 4077
|
|
{ PseudoVLSEG3E16_V_M1_MASK, VLSEG3E16_V, 0x0, 0x10 }, // 4078
|
|
{ PseudoVLSEG3E16_V_M2, VLSEG3E16_V, 0x1, 0x10 }, // 4079
|
|
{ PseudoVLSEG3E16_V_M2_MASK, VLSEG3E16_V, 0x1, 0x10 }, // 4080
|
|
{ PseudoVLSEG3E16_V_MF4, VLSEG3E16_V, 0x6, 0x10 }, // 4081
|
|
{ PseudoVLSEG3E16_V_MF4_MASK, VLSEG3E16_V, 0x6, 0x10 }, // 4082
|
|
{ PseudoVLSEG3E16_V_MF2, VLSEG3E16_V, 0x7, 0x10 }, // 4083
|
|
{ PseudoVLSEG3E16_V_MF2_MASK, VLSEG3E16_V, 0x7, 0x10 }, // 4084
|
|
{ PseudoVLSEG3E32FF_V_M1, VLSEG3E32FF_V, 0x0, 0x20 }, // 4085
|
|
{ PseudoVLSEG3E32FF_V_M1_MASK, VLSEG3E32FF_V, 0x0, 0x20 }, // 4086
|
|
{ PseudoVLSEG3E32FF_V_M2, VLSEG3E32FF_V, 0x1, 0x20 }, // 4087
|
|
{ PseudoVLSEG3E32FF_V_M2_MASK, VLSEG3E32FF_V, 0x1, 0x20 }, // 4088
|
|
{ PseudoVLSEG3E32FF_V_MF2, VLSEG3E32FF_V, 0x7, 0x20 }, // 4089
|
|
{ PseudoVLSEG3E32FF_V_MF2_MASK, VLSEG3E32FF_V, 0x7, 0x20 }, // 4090
|
|
{ PseudoVLSEG3E32_V_M1, VLSEG3E32_V, 0x0, 0x20 }, // 4091
|
|
{ PseudoVLSEG3E32_V_M1_MASK, VLSEG3E32_V, 0x0, 0x20 }, // 4092
|
|
{ PseudoVLSEG3E32_V_M2, VLSEG3E32_V, 0x1, 0x20 }, // 4093
|
|
{ PseudoVLSEG3E32_V_M2_MASK, VLSEG3E32_V, 0x1, 0x20 }, // 4094
|
|
{ PseudoVLSEG3E32_V_MF2, VLSEG3E32_V, 0x7, 0x20 }, // 4095
|
|
{ PseudoVLSEG3E32_V_MF2_MASK, VLSEG3E32_V, 0x7, 0x20 }, // 4096
|
|
{ PseudoVLSEG3E64FF_V_M1, VLSEG3E64FF_V, 0x0, 0x40 }, // 4097
|
|
{ PseudoVLSEG3E64FF_V_M1_MASK, VLSEG3E64FF_V, 0x0, 0x40 }, // 4098
|
|
{ PseudoVLSEG3E64FF_V_M2, VLSEG3E64FF_V, 0x1, 0x40 }, // 4099
|
|
{ PseudoVLSEG3E64FF_V_M2_MASK, VLSEG3E64FF_V, 0x1, 0x40 }, // 4100
|
|
{ PseudoVLSEG3E64_V_M1, VLSEG3E64_V, 0x0, 0x40 }, // 4101
|
|
{ PseudoVLSEG3E64_V_M1_MASK, VLSEG3E64_V, 0x0, 0x40 }, // 4102
|
|
{ PseudoVLSEG3E64_V_M2, VLSEG3E64_V, 0x1, 0x40 }, // 4103
|
|
{ PseudoVLSEG3E64_V_M2_MASK, VLSEG3E64_V, 0x1, 0x40 }, // 4104
|
|
{ PseudoVLSEG3E8FF_V_M1, VLSEG3E8FF_V, 0x0, 0x8 }, // 4105
|
|
{ PseudoVLSEG3E8FF_V_M1_MASK, VLSEG3E8FF_V, 0x0, 0x8 }, // 4106
|
|
{ PseudoVLSEG3E8FF_V_M2, VLSEG3E8FF_V, 0x1, 0x8 }, // 4107
|
|
{ PseudoVLSEG3E8FF_V_M2_MASK, VLSEG3E8FF_V, 0x1, 0x8 }, // 4108
|
|
{ PseudoVLSEG3E8FF_V_MF8, VLSEG3E8FF_V, 0x5, 0x8 }, // 4109
|
|
{ PseudoVLSEG3E8FF_V_MF8_MASK, VLSEG3E8FF_V, 0x5, 0x8 }, // 4110
|
|
{ PseudoVLSEG3E8FF_V_MF4, VLSEG3E8FF_V, 0x6, 0x8 }, // 4111
|
|
{ PseudoVLSEG3E8FF_V_MF4_MASK, VLSEG3E8FF_V, 0x6, 0x8 }, // 4112
|
|
{ PseudoVLSEG3E8FF_V_MF2, VLSEG3E8FF_V, 0x7, 0x8 }, // 4113
|
|
{ PseudoVLSEG3E8FF_V_MF2_MASK, VLSEG3E8FF_V, 0x7, 0x8 }, // 4114
|
|
{ PseudoVLSEG3E8_V_M1, VLSEG3E8_V, 0x0, 0x8 }, // 4115
|
|
{ PseudoVLSEG3E8_V_M1_MASK, VLSEG3E8_V, 0x0, 0x8 }, // 4116
|
|
{ PseudoVLSEG3E8_V_M2, VLSEG3E8_V, 0x1, 0x8 }, // 4117
|
|
{ PseudoVLSEG3E8_V_M2_MASK, VLSEG3E8_V, 0x1, 0x8 }, // 4118
|
|
{ PseudoVLSEG3E8_V_MF8, VLSEG3E8_V, 0x5, 0x8 }, // 4119
|
|
{ PseudoVLSEG3E8_V_MF8_MASK, VLSEG3E8_V, 0x5, 0x8 }, // 4120
|
|
{ PseudoVLSEG3E8_V_MF4, VLSEG3E8_V, 0x6, 0x8 }, // 4121
|
|
{ PseudoVLSEG3E8_V_MF4_MASK, VLSEG3E8_V, 0x6, 0x8 }, // 4122
|
|
{ PseudoVLSEG3E8_V_MF2, VLSEG3E8_V, 0x7, 0x8 }, // 4123
|
|
{ PseudoVLSEG3E8_V_MF2_MASK, VLSEG3E8_V, 0x7, 0x8 }, // 4124
|
|
{ PseudoVLSEG4E16FF_V_M1, VLSEG4E16FF_V, 0x0, 0x10 }, // 4125
|
|
{ PseudoVLSEG4E16FF_V_M1_MASK, VLSEG4E16FF_V, 0x0, 0x10 }, // 4126
|
|
{ PseudoVLSEG4E16FF_V_M2, VLSEG4E16FF_V, 0x1, 0x10 }, // 4127
|
|
{ PseudoVLSEG4E16FF_V_M2_MASK, VLSEG4E16FF_V, 0x1, 0x10 }, // 4128
|
|
{ PseudoVLSEG4E16FF_V_MF4, VLSEG4E16FF_V, 0x6, 0x10 }, // 4129
|
|
{ PseudoVLSEG4E16FF_V_MF4_MASK, VLSEG4E16FF_V, 0x6, 0x10 }, // 4130
|
|
{ PseudoVLSEG4E16FF_V_MF2, VLSEG4E16FF_V, 0x7, 0x10 }, // 4131
|
|
{ PseudoVLSEG4E16FF_V_MF2_MASK, VLSEG4E16FF_V, 0x7, 0x10 }, // 4132
|
|
{ PseudoVLSEG4E16_V_M1, VLSEG4E16_V, 0x0, 0x10 }, // 4133
|
|
{ PseudoVLSEG4E16_V_M1_MASK, VLSEG4E16_V, 0x0, 0x10 }, // 4134
|
|
{ PseudoVLSEG4E16_V_M2, VLSEG4E16_V, 0x1, 0x10 }, // 4135
|
|
{ PseudoVLSEG4E16_V_M2_MASK, VLSEG4E16_V, 0x1, 0x10 }, // 4136
|
|
{ PseudoVLSEG4E16_V_MF4, VLSEG4E16_V, 0x6, 0x10 }, // 4137
|
|
{ PseudoVLSEG4E16_V_MF4_MASK, VLSEG4E16_V, 0x6, 0x10 }, // 4138
|
|
{ PseudoVLSEG4E16_V_MF2, VLSEG4E16_V, 0x7, 0x10 }, // 4139
|
|
{ PseudoVLSEG4E16_V_MF2_MASK, VLSEG4E16_V, 0x7, 0x10 }, // 4140
|
|
{ PseudoVLSEG4E32FF_V_M1, VLSEG4E32FF_V, 0x0, 0x20 }, // 4141
|
|
{ PseudoVLSEG4E32FF_V_M1_MASK, VLSEG4E32FF_V, 0x0, 0x20 }, // 4142
|
|
{ PseudoVLSEG4E32FF_V_M2, VLSEG4E32FF_V, 0x1, 0x20 }, // 4143
|
|
{ PseudoVLSEG4E32FF_V_M2_MASK, VLSEG4E32FF_V, 0x1, 0x20 }, // 4144
|
|
{ PseudoVLSEG4E32FF_V_MF2, VLSEG4E32FF_V, 0x7, 0x20 }, // 4145
|
|
{ PseudoVLSEG4E32FF_V_MF2_MASK, VLSEG4E32FF_V, 0x7, 0x20 }, // 4146
|
|
{ PseudoVLSEG4E32_V_M1, VLSEG4E32_V, 0x0, 0x20 }, // 4147
|
|
{ PseudoVLSEG4E32_V_M1_MASK, VLSEG4E32_V, 0x0, 0x20 }, // 4148
|
|
{ PseudoVLSEG4E32_V_M2, VLSEG4E32_V, 0x1, 0x20 }, // 4149
|
|
{ PseudoVLSEG4E32_V_M2_MASK, VLSEG4E32_V, 0x1, 0x20 }, // 4150
|
|
{ PseudoVLSEG4E32_V_MF2, VLSEG4E32_V, 0x7, 0x20 }, // 4151
|
|
{ PseudoVLSEG4E32_V_MF2_MASK, VLSEG4E32_V, 0x7, 0x20 }, // 4152
|
|
{ PseudoVLSEG4E64FF_V_M1, VLSEG4E64FF_V, 0x0, 0x40 }, // 4153
|
|
{ PseudoVLSEG4E64FF_V_M1_MASK, VLSEG4E64FF_V, 0x0, 0x40 }, // 4154
|
|
{ PseudoVLSEG4E64FF_V_M2, VLSEG4E64FF_V, 0x1, 0x40 }, // 4155
|
|
{ PseudoVLSEG4E64FF_V_M2_MASK, VLSEG4E64FF_V, 0x1, 0x40 }, // 4156
|
|
{ PseudoVLSEG4E64_V_M1, VLSEG4E64_V, 0x0, 0x40 }, // 4157
|
|
{ PseudoVLSEG4E64_V_M1_MASK, VLSEG4E64_V, 0x0, 0x40 }, // 4158
|
|
{ PseudoVLSEG4E64_V_M2, VLSEG4E64_V, 0x1, 0x40 }, // 4159
|
|
{ PseudoVLSEG4E64_V_M2_MASK, VLSEG4E64_V, 0x1, 0x40 }, // 4160
|
|
{ PseudoVLSEG4E8FF_V_M1, VLSEG4E8FF_V, 0x0, 0x8 }, // 4161
|
|
{ PseudoVLSEG4E8FF_V_M1_MASK, VLSEG4E8FF_V, 0x0, 0x8 }, // 4162
|
|
{ PseudoVLSEG4E8FF_V_M2, VLSEG4E8FF_V, 0x1, 0x8 }, // 4163
|
|
{ PseudoVLSEG4E8FF_V_M2_MASK, VLSEG4E8FF_V, 0x1, 0x8 }, // 4164
|
|
{ PseudoVLSEG4E8FF_V_MF8, VLSEG4E8FF_V, 0x5, 0x8 }, // 4165
|
|
{ PseudoVLSEG4E8FF_V_MF8_MASK, VLSEG4E8FF_V, 0x5, 0x8 }, // 4166
|
|
{ PseudoVLSEG4E8FF_V_MF4, VLSEG4E8FF_V, 0x6, 0x8 }, // 4167
|
|
{ PseudoVLSEG4E8FF_V_MF4_MASK, VLSEG4E8FF_V, 0x6, 0x8 }, // 4168
|
|
{ PseudoVLSEG4E8FF_V_MF2, VLSEG4E8FF_V, 0x7, 0x8 }, // 4169
|
|
{ PseudoVLSEG4E8FF_V_MF2_MASK, VLSEG4E8FF_V, 0x7, 0x8 }, // 4170
|
|
{ PseudoVLSEG4E8_V_M1, VLSEG4E8_V, 0x0, 0x8 }, // 4171
|
|
{ PseudoVLSEG4E8_V_M1_MASK, VLSEG4E8_V, 0x0, 0x8 }, // 4172
|
|
{ PseudoVLSEG4E8_V_M2, VLSEG4E8_V, 0x1, 0x8 }, // 4173
|
|
{ PseudoVLSEG4E8_V_M2_MASK, VLSEG4E8_V, 0x1, 0x8 }, // 4174
|
|
{ PseudoVLSEG4E8_V_MF8, VLSEG4E8_V, 0x5, 0x8 }, // 4175
|
|
{ PseudoVLSEG4E8_V_MF8_MASK, VLSEG4E8_V, 0x5, 0x8 }, // 4176
|
|
{ PseudoVLSEG4E8_V_MF4, VLSEG4E8_V, 0x6, 0x8 }, // 4177
|
|
{ PseudoVLSEG4E8_V_MF4_MASK, VLSEG4E8_V, 0x6, 0x8 }, // 4178
|
|
{ PseudoVLSEG4E8_V_MF2, VLSEG4E8_V, 0x7, 0x8 }, // 4179
|
|
{ PseudoVLSEG4E8_V_MF2_MASK, VLSEG4E8_V, 0x7, 0x8 }, // 4180
|
|
{ PseudoVLSEG5E16FF_V_M1, VLSEG5E16FF_V, 0x0, 0x10 }, // 4181
|
|
{ PseudoVLSEG5E16FF_V_M1_MASK, VLSEG5E16FF_V, 0x0, 0x10 }, // 4182
|
|
{ PseudoVLSEG5E16FF_V_MF4, VLSEG5E16FF_V, 0x6, 0x10 }, // 4183
|
|
{ PseudoVLSEG5E16FF_V_MF4_MASK, VLSEG5E16FF_V, 0x6, 0x10 }, // 4184
|
|
{ PseudoVLSEG5E16FF_V_MF2, VLSEG5E16FF_V, 0x7, 0x10 }, // 4185
|
|
{ PseudoVLSEG5E16FF_V_MF2_MASK, VLSEG5E16FF_V, 0x7, 0x10 }, // 4186
|
|
{ PseudoVLSEG5E16_V_M1, VLSEG5E16_V, 0x0, 0x10 }, // 4187
|
|
{ PseudoVLSEG5E16_V_M1_MASK, VLSEG5E16_V, 0x0, 0x10 }, // 4188
|
|
{ PseudoVLSEG5E16_V_MF4, VLSEG5E16_V, 0x6, 0x10 }, // 4189
|
|
{ PseudoVLSEG5E16_V_MF4_MASK, VLSEG5E16_V, 0x6, 0x10 }, // 4190
|
|
{ PseudoVLSEG5E16_V_MF2, VLSEG5E16_V, 0x7, 0x10 }, // 4191
|
|
{ PseudoVLSEG5E16_V_MF2_MASK, VLSEG5E16_V, 0x7, 0x10 }, // 4192
|
|
{ PseudoVLSEG5E32FF_V_M1, VLSEG5E32FF_V, 0x0, 0x20 }, // 4193
|
|
{ PseudoVLSEG5E32FF_V_M1_MASK, VLSEG5E32FF_V, 0x0, 0x20 }, // 4194
|
|
{ PseudoVLSEG5E32FF_V_MF2, VLSEG5E32FF_V, 0x7, 0x20 }, // 4195
|
|
{ PseudoVLSEG5E32FF_V_MF2_MASK, VLSEG5E32FF_V, 0x7, 0x20 }, // 4196
|
|
{ PseudoVLSEG5E32_V_M1, VLSEG5E32_V, 0x0, 0x20 }, // 4197
|
|
{ PseudoVLSEG5E32_V_M1_MASK, VLSEG5E32_V, 0x0, 0x20 }, // 4198
|
|
{ PseudoVLSEG5E32_V_MF2, VLSEG5E32_V, 0x7, 0x20 }, // 4199
|
|
{ PseudoVLSEG5E32_V_MF2_MASK, VLSEG5E32_V, 0x7, 0x20 }, // 4200
|
|
{ PseudoVLSEG5E64FF_V_M1, VLSEG5E64FF_V, 0x0, 0x40 }, // 4201
|
|
{ PseudoVLSEG5E64FF_V_M1_MASK, VLSEG5E64FF_V, 0x0, 0x40 }, // 4202
|
|
{ PseudoVLSEG5E64_V_M1, VLSEG5E64_V, 0x0, 0x40 }, // 4203
|
|
{ PseudoVLSEG5E64_V_M1_MASK, VLSEG5E64_V, 0x0, 0x40 }, // 4204
|
|
{ PseudoVLSEG5E8FF_V_M1, VLSEG5E8FF_V, 0x0, 0x8 }, // 4205
|
|
{ PseudoVLSEG5E8FF_V_M1_MASK, VLSEG5E8FF_V, 0x0, 0x8 }, // 4206
|
|
{ PseudoVLSEG5E8FF_V_MF8, VLSEG5E8FF_V, 0x5, 0x8 }, // 4207
|
|
{ PseudoVLSEG5E8FF_V_MF8_MASK, VLSEG5E8FF_V, 0x5, 0x8 }, // 4208
|
|
{ PseudoVLSEG5E8FF_V_MF4, VLSEG5E8FF_V, 0x6, 0x8 }, // 4209
|
|
{ PseudoVLSEG5E8FF_V_MF4_MASK, VLSEG5E8FF_V, 0x6, 0x8 }, // 4210
|
|
{ PseudoVLSEG5E8FF_V_MF2, VLSEG5E8FF_V, 0x7, 0x8 }, // 4211
|
|
{ PseudoVLSEG5E8FF_V_MF2_MASK, VLSEG5E8FF_V, 0x7, 0x8 }, // 4212
|
|
{ PseudoVLSEG5E8_V_M1, VLSEG5E8_V, 0x0, 0x8 }, // 4213
|
|
{ PseudoVLSEG5E8_V_M1_MASK, VLSEG5E8_V, 0x0, 0x8 }, // 4214
|
|
{ PseudoVLSEG5E8_V_MF8, VLSEG5E8_V, 0x5, 0x8 }, // 4215
|
|
{ PseudoVLSEG5E8_V_MF8_MASK, VLSEG5E8_V, 0x5, 0x8 }, // 4216
|
|
{ PseudoVLSEG5E8_V_MF4, VLSEG5E8_V, 0x6, 0x8 }, // 4217
|
|
{ PseudoVLSEG5E8_V_MF4_MASK, VLSEG5E8_V, 0x6, 0x8 }, // 4218
|
|
{ PseudoVLSEG5E8_V_MF2, VLSEG5E8_V, 0x7, 0x8 }, // 4219
|
|
{ PseudoVLSEG5E8_V_MF2_MASK, VLSEG5E8_V, 0x7, 0x8 }, // 4220
|
|
{ PseudoVLSEG6E16FF_V_M1, VLSEG6E16FF_V, 0x0, 0x10 }, // 4221
|
|
{ PseudoVLSEG6E16FF_V_M1_MASK, VLSEG6E16FF_V, 0x0, 0x10 }, // 4222
|
|
{ PseudoVLSEG6E16FF_V_MF4, VLSEG6E16FF_V, 0x6, 0x10 }, // 4223
|
|
{ PseudoVLSEG6E16FF_V_MF4_MASK, VLSEG6E16FF_V, 0x6, 0x10 }, // 4224
|
|
{ PseudoVLSEG6E16FF_V_MF2, VLSEG6E16FF_V, 0x7, 0x10 }, // 4225
|
|
{ PseudoVLSEG6E16FF_V_MF2_MASK, VLSEG6E16FF_V, 0x7, 0x10 }, // 4226
|
|
{ PseudoVLSEG6E16_V_M1, VLSEG6E16_V, 0x0, 0x10 }, // 4227
|
|
{ PseudoVLSEG6E16_V_M1_MASK, VLSEG6E16_V, 0x0, 0x10 }, // 4228
|
|
{ PseudoVLSEG6E16_V_MF4, VLSEG6E16_V, 0x6, 0x10 }, // 4229
|
|
{ PseudoVLSEG6E16_V_MF4_MASK, VLSEG6E16_V, 0x6, 0x10 }, // 4230
|
|
{ PseudoVLSEG6E16_V_MF2, VLSEG6E16_V, 0x7, 0x10 }, // 4231
|
|
{ PseudoVLSEG6E16_V_MF2_MASK, VLSEG6E16_V, 0x7, 0x10 }, // 4232
|
|
{ PseudoVLSEG6E32FF_V_M1, VLSEG6E32FF_V, 0x0, 0x20 }, // 4233
|
|
{ PseudoVLSEG6E32FF_V_M1_MASK, VLSEG6E32FF_V, 0x0, 0x20 }, // 4234
|
|
{ PseudoVLSEG6E32FF_V_MF2, VLSEG6E32FF_V, 0x7, 0x20 }, // 4235
|
|
{ PseudoVLSEG6E32FF_V_MF2_MASK, VLSEG6E32FF_V, 0x7, 0x20 }, // 4236
|
|
{ PseudoVLSEG6E32_V_M1, VLSEG6E32_V, 0x0, 0x20 }, // 4237
|
|
{ PseudoVLSEG6E32_V_M1_MASK, VLSEG6E32_V, 0x0, 0x20 }, // 4238
|
|
{ PseudoVLSEG6E32_V_MF2, VLSEG6E32_V, 0x7, 0x20 }, // 4239
|
|
{ PseudoVLSEG6E32_V_MF2_MASK, VLSEG6E32_V, 0x7, 0x20 }, // 4240
|
|
{ PseudoVLSEG6E64FF_V_M1, VLSEG6E64FF_V, 0x0, 0x40 }, // 4241
|
|
{ PseudoVLSEG6E64FF_V_M1_MASK, VLSEG6E64FF_V, 0x0, 0x40 }, // 4242
|
|
{ PseudoVLSEG6E64_V_M1, VLSEG6E64_V, 0x0, 0x40 }, // 4243
|
|
{ PseudoVLSEG6E64_V_M1_MASK, VLSEG6E64_V, 0x0, 0x40 }, // 4244
|
|
{ PseudoVLSEG6E8FF_V_M1, VLSEG6E8FF_V, 0x0, 0x8 }, // 4245
|
|
{ PseudoVLSEG6E8FF_V_M1_MASK, VLSEG6E8FF_V, 0x0, 0x8 }, // 4246
|
|
{ PseudoVLSEG6E8FF_V_MF8, VLSEG6E8FF_V, 0x5, 0x8 }, // 4247
|
|
{ PseudoVLSEG6E8FF_V_MF8_MASK, VLSEG6E8FF_V, 0x5, 0x8 }, // 4248
|
|
{ PseudoVLSEG6E8FF_V_MF4, VLSEG6E8FF_V, 0x6, 0x8 }, // 4249
|
|
{ PseudoVLSEG6E8FF_V_MF4_MASK, VLSEG6E8FF_V, 0x6, 0x8 }, // 4250
|
|
{ PseudoVLSEG6E8FF_V_MF2, VLSEG6E8FF_V, 0x7, 0x8 }, // 4251
|
|
{ PseudoVLSEG6E8FF_V_MF2_MASK, VLSEG6E8FF_V, 0x7, 0x8 }, // 4252
|
|
{ PseudoVLSEG6E8_V_M1, VLSEG6E8_V, 0x0, 0x8 }, // 4253
|
|
{ PseudoVLSEG6E8_V_M1_MASK, VLSEG6E8_V, 0x0, 0x8 }, // 4254
|
|
{ PseudoVLSEG6E8_V_MF8, VLSEG6E8_V, 0x5, 0x8 }, // 4255
|
|
{ PseudoVLSEG6E8_V_MF8_MASK, VLSEG6E8_V, 0x5, 0x8 }, // 4256
|
|
{ PseudoVLSEG6E8_V_MF4, VLSEG6E8_V, 0x6, 0x8 }, // 4257
|
|
{ PseudoVLSEG6E8_V_MF4_MASK, VLSEG6E8_V, 0x6, 0x8 }, // 4258
|
|
{ PseudoVLSEG6E8_V_MF2, VLSEG6E8_V, 0x7, 0x8 }, // 4259
|
|
{ PseudoVLSEG6E8_V_MF2_MASK, VLSEG6E8_V, 0x7, 0x8 }, // 4260
|
|
{ PseudoVLSEG7E16FF_V_M1, VLSEG7E16FF_V, 0x0, 0x10 }, // 4261
|
|
{ PseudoVLSEG7E16FF_V_M1_MASK, VLSEG7E16FF_V, 0x0, 0x10 }, // 4262
|
|
{ PseudoVLSEG7E16FF_V_MF4, VLSEG7E16FF_V, 0x6, 0x10 }, // 4263
|
|
{ PseudoVLSEG7E16FF_V_MF4_MASK, VLSEG7E16FF_V, 0x6, 0x10 }, // 4264
|
|
{ PseudoVLSEG7E16FF_V_MF2, VLSEG7E16FF_V, 0x7, 0x10 }, // 4265
|
|
{ PseudoVLSEG7E16FF_V_MF2_MASK, VLSEG7E16FF_V, 0x7, 0x10 }, // 4266
|
|
{ PseudoVLSEG7E16_V_M1, VLSEG7E16_V, 0x0, 0x10 }, // 4267
|
|
{ PseudoVLSEG7E16_V_M1_MASK, VLSEG7E16_V, 0x0, 0x10 }, // 4268
|
|
{ PseudoVLSEG7E16_V_MF4, VLSEG7E16_V, 0x6, 0x10 }, // 4269
|
|
{ PseudoVLSEG7E16_V_MF4_MASK, VLSEG7E16_V, 0x6, 0x10 }, // 4270
|
|
{ PseudoVLSEG7E16_V_MF2, VLSEG7E16_V, 0x7, 0x10 }, // 4271
|
|
{ PseudoVLSEG7E16_V_MF2_MASK, VLSEG7E16_V, 0x7, 0x10 }, // 4272
|
|
{ PseudoVLSEG7E32FF_V_M1, VLSEG7E32FF_V, 0x0, 0x20 }, // 4273
|
|
{ PseudoVLSEG7E32FF_V_M1_MASK, VLSEG7E32FF_V, 0x0, 0x20 }, // 4274
|
|
{ PseudoVLSEG7E32FF_V_MF2, VLSEG7E32FF_V, 0x7, 0x20 }, // 4275
|
|
{ PseudoVLSEG7E32FF_V_MF2_MASK, VLSEG7E32FF_V, 0x7, 0x20 }, // 4276
|
|
{ PseudoVLSEG7E32_V_M1, VLSEG7E32_V, 0x0, 0x20 }, // 4277
|
|
{ PseudoVLSEG7E32_V_M1_MASK, VLSEG7E32_V, 0x0, 0x20 }, // 4278
|
|
{ PseudoVLSEG7E32_V_MF2, VLSEG7E32_V, 0x7, 0x20 }, // 4279
|
|
{ PseudoVLSEG7E32_V_MF2_MASK, VLSEG7E32_V, 0x7, 0x20 }, // 4280
|
|
{ PseudoVLSEG7E64FF_V_M1, VLSEG7E64FF_V, 0x0, 0x40 }, // 4281
|
|
{ PseudoVLSEG7E64FF_V_M1_MASK, VLSEG7E64FF_V, 0x0, 0x40 }, // 4282
|
|
{ PseudoVLSEG7E64_V_M1, VLSEG7E64_V, 0x0, 0x40 }, // 4283
|
|
{ PseudoVLSEG7E64_V_M1_MASK, VLSEG7E64_V, 0x0, 0x40 }, // 4284
|
|
{ PseudoVLSEG7E8FF_V_M1, VLSEG7E8FF_V, 0x0, 0x8 }, // 4285
|
|
{ PseudoVLSEG7E8FF_V_M1_MASK, VLSEG7E8FF_V, 0x0, 0x8 }, // 4286
|
|
{ PseudoVLSEG7E8FF_V_MF8, VLSEG7E8FF_V, 0x5, 0x8 }, // 4287
|
|
{ PseudoVLSEG7E8FF_V_MF8_MASK, VLSEG7E8FF_V, 0x5, 0x8 }, // 4288
|
|
{ PseudoVLSEG7E8FF_V_MF4, VLSEG7E8FF_V, 0x6, 0x8 }, // 4289
|
|
{ PseudoVLSEG7E8FF_V_MF4_MASK, VLSEG7E8FF_V, 0x6, 0x8 }, // 4290
|
|
{ PseudoVLSEG7E8FF_V_MF2, VLSEG7E8FF_V, 0x7, 0x8 }, // 4291
|
|
{ PseudoVLSEG7E8FF_V_MF2_MASK, VLSEG7E8FF_V, 0x7, 0x8 }, // 4292
|
|
{ PseudoVLSEG7E8_V_M1, VLSEG7E8_V, 0x0, 0x8 }, // 4293
|
|
{ PseudoVLSEG7E8_V_M1_MASK, VLSEG7E8_V, 0x0, 0x8 }, // 4294
|
|
{ PseudoVLSEG7E8_V_MF8, VLSEG7E8_V, 0x5, 0x8 }, // 4295
|
|
{ PseudoVLSEG7E8_V_MF8_MASK, VLSEG7E8_V, 0x5, 0x8 }, // 4296
|
|
{ PseudoVLSEG7E8_V_MF4, VLSEG7E8_V, 0x6, 0x8 }, // 4297
|
|
{ PseudoVLSEG7E8_V_MF4_MASK, VLSEG7E8_V, 0x6, 0x8 }, // 4298
|
|
{ PseudoVLSEG7E8_V_MF2, VLSEG7E8_V, 0x7, 0x8 }, // 4299
|
|
{ PseudoVLSEG7E8_V_MF2_MASK, VLSEG7E8_V, 0x7, 0x8 }, // 4300
|
|
{ PseudoVLSEG8E16FF_V_M1, VLSEG8E16FF_V, 0x0, 0x10 }, // 4301
|
|
{ PseudoVLSEG8E16FF_V_M1_MASK, VLSEG8E16FF_V, 0x0, 0x10 }, // 4302
|
|
{ PseudoVLSEG8E16FF_V_MF4, VLSEG8E16FF_V, 0x6, 0x10 }, // 4303
|
|
{ PseudoVLSEG8E16FF_V_MF4_MASK, VLSEG8E16FF_V, 0x6, 0x10 }, // 4304
|
|
{ PseudoVLSEG8E16FF_V_MF2, VLSEG8E16FF_V, 0x7, 0x10 }, // 4305
|
|
{ PseudoVLSEG8E16FF_V_MF2_MASK, VLSEG8E16FF_V, 0x7, 0x10 }, // 4306
|
|
{ PseudoVLSEG8E16_V_M1, VLSEG8E16_V, 0x0, 0x10 }, // 4307
|
|
{ PseudoVLSEG8E16_V_M1_MASK, VLSEG8E16_V, 0x0, 0x10 }, // 4308
|
|
{ PseudoVLSEG8E16_V_MF4, VLSEG8E16_V, 0x6, 0x10 }, // 4309
|
|
{ PseudoVLSEG8E16_V_MF4_MASK, VLSEG8E16_V, 0x6, 0x10 }, // 4310
|
|
{ PseudoVLSEG8E16_V_MF2, VLSEG8E16_V, 0x7, 0x10 }, // 4311
|
|
{ PseudoVLSEG8E16_V_MF2_MASK, VLSEG8E16_V, 0x7, 0x10 }, // 4312
|
|
{ PseudoVLSEG8E32FF_V_M1, VLSEG8E32FF_V, 0x0, 0x20 }, // 4313
|
|
{ PseudoVLSEG8E32FF_V_M1_MASK, VLSEG8E32FF_V, 0x0, 0x20 }, // 4314
|
|
{ PseudoVLSEG8E32FF_V_MF2, VLSEG8E32FF_V, 0x7, 0x20 }, // 4315
|
|
{ PseudoVLSEG8E32FF_V_MF2_MASK, VLSEG8E32FF_V, 0x7, 0x20 }, // 4316
|
|
{ PseudoVLSEG8E32_V_M1, VLSEG8E32_V, 0x0, 0x20 }, // 4317
|
|
{ PseudoVLSEG8E32_V_M1_MASK, VLSEG8E32_V, 0x0, 0x20 }, // 4318
|
|
{ PseudoVLSEG8E32_V_MF2, VLSEG8E32_V, 0x7, 0x20 }, // 4319
|
|
{ PseudoVLSEG8E32_V_MF2_MASK, VLSEG8E32_V, 0x7, 0x20 }, // 4320
|
|
{ PseudoVLSEG8E64FF_V_M1, VLSEG8E64FF_V, 0x0, 0x40 }, // 4321
|
|
{ PseudoVLSEG8E64FF_V_M1_MASK, VLSEG8E64FF_V, 0x0, 0x40 }, // 4322
|
|
{ PseudoVLSEG8E64_V_M1, VLSEG8E64_V, 0x0, 0x40 }, // 4323
|
|
{ PseudoVLSEG8E64_V_M1_MASK, VLSEG8E64_V, 0x0, 0x40 }, // 4324
|
|
{ PseudoVLSEG8E8FF_V_M1, VLSEG8E8FF_V, 0x0, 0x8 }, // 4325
|
|
{ PseudoVLSEG8E8FF_V_M1_MASK, VLSEG8E8FF_V, 0x0, 0x8 }, // 4326
|
|
{ PseudoVLSEG8E8FF_V_MF8, VLSEG8E8FF_V, 0x5, 0x8 }, // 4327
|
|
{ PseudoVLSEG8E8FF_V_MF8_MASK, VLSEG8E8FF_V, 0x5, 0x8 }, // 4328
|
|
{ PseudoVLSEG8E8FF_V_MF4, VLSEG8E8FF_V, 0x6, 0x8 }, // 4329
|
|
{ PseudoVLSEG8E8FF_V_MF4_MASK, VLSEG8E8FF_V, 0x6, 0x8 }, // 4330
|
|
{ PseudoVLSEG8E8FF_V_MF2, VLSEG8E8FF_V, 0x7, 0x8 }, // 4331
|
|
{ PseudoVLSEG8E8FF_V_MF2_MASK, VLSEG8E8FF_V, 0x7, 0x8 }, // 4332
|
|
{ PseudoVLSEG8E8_V_M1, VLSEG8E8_V, 0x0, 0x8 }, // 4333
|
|
{ PseudoVLSEG8E8_V_M1_MASK, VLSEG8E8_V, 0x0, 0x8 }, // 4334
|
|
{ PseudoVLSEG8E8_V_MF8, VLSEG8E8_V, 0x5, 0x8 }, // 4335
|
|
{ PseudoVLSEG8E8_V_MF8_MASK, VLSEG8E8_V, 0x5, 0x8 }, // 4336
|
|
{ PseudoVLSEG8E8_V_MF4, VLSEG8E8_V, 0x6, 0x8 }, // 4337
|
|
{ PseudoVLSEG8E8_V_MF4_MASK, VLSEG8E8_V, 0x6, 0x8 }, // 4338
|
|
{ PseudoVLSEG8E8_V_MF2, VLSEG8E8_V, 0x7, 0x8 }, // 4339
|
|
{ PseudoVLSEG8E8_V_MF2_MASK, VLSEG8E8_V, 0x7, 0x8 }, // 4340
|
|
{ PseudoVLSSEG2E16_V_M1, VLSSEG2E16_V, 0x0, 0x10 }, // 4341
|
|
{ PseudoVLSSEG2E16_V_M1_MASK, VLSSEG2E16_V, 0x0, 0x10 }, // 4342
|
|
{ PseudoVLSSEG2E16_V_M2, VLSSEG2E16_V, 0x1, 0x10 }, // 4343
|
|
{ PseudoVLSSEG2E16_V_M2_MASK, VLSSEG2E16_V, 0x1, 0x10 }, // 4344
|
|
{ PseudoVLSSEG2E16_V_M4, VLSSEG2E16_V, 0x2, 0x10 }, // 4345
|
|
{ PseudoVLSSEG2E16_V_M4_MASK, VLSSEG2E16_V, 0x2, 0x10 }, // 4346
|
|
{ PseudoVLSSEG2E16_V_MF4, VLSSEG2E16_V, 0x6, 0x10 }, // 4347
|
|
{ PseudoVLSSEG2E16_V_MF4_MASK, VLSSEG2E16_V, 0x6, 0x10 }, // 4348
|
|
{ PseudoVLSSEG2E16_V_MF2, VLSSEG2E16_V, 0x7, 0x10 }, // 4349
|
|
{ PseudoVLSSEG2E16_V_MF2_MASK, VLSSEG2E16_V, 0x7, 0x10 }, // 4350
|
|
{ PseudoVLSSEG2E32_V_M1, VLSSEG2E32_V, 0x0, 0x20 }, // 4351
|
|
{ PseudoVLSSEG2E32_V_M1_MASK, VLSSEG2E32_V, 0x0, 0x20 }, // 4352
|
|
{ PseudoVLSSEG2E32_V_M2, VLSSEG2E32_V, 0x1, 0x20 }, // 4353
|
|
{ PseudoVLSSEG2E32_V_M2_MASK, VLSSEG2E32_V, 0x1, 0x20 }, // 4354
|
|
{ PseudoVLSSEG2E32_V_M4, VLSSEG2E32_V, 0x2, 0x20 }, // 4355
|
|
{ PseudoVLSSEG2E32_V_M4_MASK, VLSSEG2E32_V, 0x2, 0x20 }, // 4356
|
|
{ PseudoVLSSEG2E32_V_MF2, VLSSEG2E32_V, 0x7, 0x20 }, // 4357
|
|
{ PseudoVLSSEG2E32_V_MF2_MASK, VLSSEG2E32_V, 0x7, 0x20 }, // 4358
|
|
{ PseudoVLSSEG2E64_V_M1, VLSSEG2E64_V, 0x0, 0x40 }, // 4359
|
|
{ PseudoVLSSEG2E64_V_M1_MASK, VLSSEG2E64_V, 0x0, 0x40 }, // 4360
|
|
{ PseudoVLSSEG2E64_V_M2, VLSSEG2E64_V, 0x1, 0x40 }, // 4361
|
|
{ PseudoVLSSEG2E64_V_M2_MASK, VLSSEG2E64_V, 0x1, 0x40 }, // 4362
|
|
{ PseudoVLSSEG2E64_V_M4, VLSSEG2E64_V, 0x2, 0x40 }, // 4363
|
|
{ PseudoVLSSEG2E64_V_M4_MASK, VLSSEG2E64_V, 0x2, 0x40 }, // 4364
|
|
{ PseudoVLSSEG2E8_V_M1, VLSSEG2E8_V, 0x0, 0x8 }, // 4365
|
|
{ PseudoVLSSEG2E8_V_M1_MASK, VLSSEG2E8_V, 0x0, 0x8 }, // 4366
|
|
{ PseudoVLSSEG2E8_V_M2, VLSSEG2E8_V, 0x1, 0x8 }, // 4367
|
|
{ PseudoVLSSEG2E8_V_M2_MASK, VLSSEG2E8_V, 0x1, 0x8 }, // 4368
|
|
{ PseudoVLSSEG2E8_V_M4, VLSSEG2E8_V, 0x2, 0x8 }, // 4369
|
|
{ PseudoVLSSEG2E8_V_M4_MASK, VLSSEG2E8_V, 0x2, 0x8 }, // 4370
|
|
{ PseudoVLSSEG2E8_V_MF8, VLSSEG2E8_V, 0x5, 0x8 }, // 4371
|
|
{ PseudoVLSSEG2E8_V_MF8_MASK, VLSSEG2E8_V, 0x5, 0x8 }, // 4372
|
|
{ PseudoVLSSEG2E8_V_MF4, VLSSEG2E8_V, 0x6, 0x8 }, // 4373
|
|
{ PseudoVLSSEG2E8_V_MF4_MASK, VLSSEG2E8_V, 0x6, 0x8 }, // 4374
|
|
{ PseudoVLSSEG2E8_V_MF2, VLSSEG2E8_V, 0x7, 0x8 }, // 4375
|
|
{ PseudoVLSSEG2E8_V_MF2_MASK, VLSSEG2E8_V, 0x7, 0x8 }, // 4376
|
|
{ PseudoVLSSEG3E16_V_M1, VLSSEG3E16_V, 0x0, 0x10 }, // 4377
|
|
{ PseudoVLSSEG3E16_V_M1_MASK, VLSSEG3E16_V, 0x0, 0x10 }, // 4378
|
|
{ PseudoVLSSEG3E16_V_M2, VLSSEG3E16_V, 0x1, 0x10 }, // 4379
|
|
{ PseudoVLSSEG3E16_V_M2_MASK, VLSSEG3E16_V, 0x1, 0x10 }, // 4380
|
|
{ PseudoVLSSEG3E16_V_MF4, VLSSEG3E16_V, 0x6, 0x10 }, // 4381
|
|
{ PseudoVLSSEG3E16_V_MF4_MASK, VLSSEG3E16_V, 0x6, 0x10 }, // 4382
|
|
{ PseudoVLSSEG3E16_V_MF2, VLSSEG3E16_V, 0x7, 0x10 }, // 4383
|
|
{ PseudoVLSSEG3E16_V_MF2_MASK, VLSSEG3E16_V, 0x7, 0x10 }, // 4384
|
|
{ PseudoVLSSEG3E32_V_M1, VLSSEG3E32_V, 0x0, 0x20 }, // 4385
|
|
{ PseudoVLSSEG3E32_V_M1_MASK, VLSSEG3E32_V, 0x0, 0x20 }, // 4386
|
|
{ PseudoVLSSEG3E32_V_M2, VLSSEG3E32_V, 0x1, 0x20 }, // 4387
|
|
{ PseudoVLSSEG3E32_V_M2_MASK, VLSSEG3E32_V, 0x1, 0x20 }, // 4388
|
|
{ PseudoVLSSEG3E32_V_MF2, VLSSEG3E32_V, 0x7, 0x20 }, // 4389
|
|
{ PseudoVLSSEG3E32_V_MF2_MASK, VLSSEG3E32_V, 0x7, 0x20 }, // 4390
|
|
{ PseudoVLSSEG3E64_V_M1, VLSSEG3E64_V, 0x0, 0x40 }, // 4391
|
|
{ PseudoVLSSEG3E64_V_M1_MASK, VLSSEG3E64_V, 0x0, 0x40 }, // 4392
|
|
{ PseudoVLSSEG3E64_V_M2, VLSSEG3E64_V, 0x1, 0x40 }, // 4393
|
|
{ PseudoVLSSEG3E64_V_M2_MASK, VLSSEG3E64_V, 0x1, 0x40 }, // 4394
|
|
{ PseudoVLSSEG3E8_V_M1, VLSSEG3E8_V, 0x0, 0x8 }, // 4395
|
|
{ PseudoVLSSEG3E8_V_M1_MASK, VLSSEG3E8_V, 0x0, 0x8 }, // 4396
|
|
{ PseudoVLSSEG3E8_V_M2, VLSSEG3E8_V, 0x1, 0x8 }, // 4397
|
|
{ PseudoVLSSEG3E8_V_M2_MASK, VLSSEG3E8_V, 0x1, 0x8 }, // 4398
|
|
{ PseudoVLSSEG3E8_V_MF8, VLSSEG3E8_V, 0x5, 0x8 }, // 4399
|
|
{ PseudoVLSSEG3E8_V_MF8_MASK, VLSSEG3E8_V, 0x5, 0x8 }, // 4400
|
|
{ PseudoVLSSEG3E8_V_MF4, VLSSEG3E8_V, 0x6, 0x8 }, // 4401
|
|
{ PseudoVLSSEG3E8_V_MF4_MASK, VLSSEG3E8_V, 0x6, 0x8 }, // 4402
|
|
{ PseudoVLSSEG3E8_V_MF2, VLSSEG3E8_V, 0x7, 0x8 }, // 4403
|
|
{ PseudoVLSSEG3E8_V_MF2_MASK, VLSSEG3E8_V, 0x7, 0x8 }, // 4404
|
|
{ PseudoVLSSEG4E16_V_M1, VLSSEG4E16_V, 0x0, 0x10 }, // 4405
|
|
{ PseudoVLSSEG4E16_V_M1_MASK, VLSSEG4E16_V, 0x0, 0x10 }, // 4406
|
|
{ PseudoVLSSEG4E16_V_M2, VLSSEG4E16_V, 0x1, 0x10 }, // 4407
|
|
{ PseudoVLSSEG4E16_V_M2_MASK, VLSSEG4E16_V, 0x1, 0x10 }, // 4408
|
|
{ PseudoVLSSEG4E16_V_MF4, VLSSEG4E16_V, 0x6, 0x10 }, // 4409
|
|
{ PseudoVLSSEG4E16_V_MF4_MASK, VLSSEG4E16_V, 0x6, 0x10 }, // 4410
|
|
{ PseudoVLSSEG4E16_V_MF2, VLSSEG4E16_V, 0x7, 0x10 }, // 4411
|
|
{ PseudoVLSSEG4E16_V_MF2_MASK, VLSSEG4E16_V, 0x7, 0x10 }, // 4412
|
|
{ PseudoVLSSEG4E32_V_M1, VLSSEG4E32_V, 0x0, 0x20 }, // 4413
|
|
{ PseudoVLSSEG4E32_V_M1_MASK, VLSSEG4E32_V, 0x0, 0x20 }, // 4414
|
|
{ PseudoVLSSEG4E32_V_M2, VLSSEG4E32_V, 0x1, 0x20 }, // 4415
|
|
{ PseudoVLSSEG4E32_V_M2_MASK, VLSSEG4E32_V, 0x1, 0x20 }, // 4416
|
|
{ PseudoVLSSEG4E32_V_MF2, VLSSEG4E32_V, 0x7, 0x20 }, // 4417
|
|
{ PseudoVLSSEG4E32_V_MF2_MASK, VLSSEG4E32_V, 0x7, 0x20 }, // 4418
|
|
{ PseudoVLSSEG4E64_V_M1, VLSSEG4E64_V, 0x0, 0x40 }, // 4419
|
|
{ PseudoVLSSEG4E64_V_M1_MASK, VLSSEG4E64_V, 0x0, 0x40 }, // 4420
|
|
{ PseudoVLSSEG4E64_V_M2, VLSSEG4E64_V, 0x1, 0x40 }, // 4421
|
|
{ PseudoVLSSEG4E64_V_M2_MASK, VLSSEG4E64_V, 0x1, 0x40 }, // 4422
|
|
{ PseudoVLSSEG4E8_V_M1, VLSSEG4E8_V, 0x0, 0x8 }, // 4423
|
|
{ PseudoVLSSEG4E8_V_M1_MASK, VLSSEG4E8_V, 0x0, 0x8 }, // 4424
|
|
{ PseudoVLSSEG4E8_V_M2, VLSSEG4E8_V, 0x1, 0x8 }, // 4425
|
|
{ PseudoVLSSEG4E8_V_M2_MASK, VLSSEG4E8_V, 0x1, 0x8 }, // 4426
|
|
{ PseudoVLSSEG4E8_V_MF8, VLSSEG4E8_V, 0x5, 0x8 }, // 4427
|
|
{ PseudoVLSSEG4E8_V_MF8_MASK, VLSSEG4E8_V, 0x5, 0x8 }, // 4428
|
|
{ PseudoVLSSEG4E8_V_MF4, VLSSEG4E8_V, 0x6, 0x8 }, // 4429
|
|
{ PseudoVLSSEG4E8_V_MF4_MASK, VLSSEG4E8_V, 0x6, 0x8 }, // 4430
|
|
{ PseudoVLSSEG4E8_V_MF2, VLSSEG4E8_V, 0x7, 0x8 }, // 4431
|
|
{ PseudoVLSSEG4E8_V_MF2_MASK, VLSSEG4E8_V, 0x7, 0x8 }, // 4432
|
|
{ PseudoVLSSEG5E16_V_M1, VLSSEG5E16_V, 0x0, 0x10 }, // 4433
|
|
{ PseudoVLSSEG5E16_V_M1_MASK, VLSSEG5E16_V, 0x0, 0x10 }, // 4434
|
|
{ PseudoVLSSEG5E16_V_MF4, VLSSEG5E16_V, 0x6, 0x10 }, // 4435
|
|
{ PseudoVLSSEG5E16_V_MF4_MASK, VLSSEG5E16_V, 0x6, 0x10 }, // 4436
|
|
{ PseudoVLSSEG5E16_V_MF2, VLSSEG5E16_V, 0x7, 0x10 }, // 4437
|
|
{ PseudoVLSSEG5E16_V_MF2_MASK, VLSSEG5E16_V, 0x7, 0x10 }, // 4438
|
|
{ PseudoVLSSEG5E32_V_M1, VLSSEG5E32_V, 0x0, 0x20 }, // 4439
|
|
{ PseudoVLSSEG5E32_V_M1_MASK, VLSSEG5E32_V, 0x0, 0x20 }, // 4440
|
|
{ PseudoVLSSEG5E32_V_MF2, VLSSEG5E32_V, 0x7, 0x20 }, // 4441
|
|
{ PseudoVLSSEG5E32_V_MF2_MASK, VLSSEG5E32_V, 0x7, 0x20 }, // 4442
|
|
{ PseudoVLSSEG5E64_V_M1, VLSSEG5E64_V, 0x0, 0x40 }, // 4443
|
|
{ PseudoVLSSEG5E64_V_M1_MASK, VLSSEG5E64_V, 0x0, 0x40 }, // 4444
|
|
{ PseudoVLSSEG5E8_V_M1, VLSSEG5E8_V, 0x0, 0x8 }, // 4445
|
|
{ PseudoVLSSEG5E8_V_M1_MASK, VLSSEG5E8_V, 0x0, 0x8 }, // 4446
|
|
{ PseudoVLSSEG5E8_V_MF8, VLSSEG5E8_V, 0x5, 0x8 }, // 4447
|
|
{ PseudoVLSSEG5E8_V_MF8_MASK, VLSSEG5E8_V, 0x5, 0x8 }, // 4448
|
|
{ PseudoVLSSEG5E8_V_MF4, VLSSEG5E8_V, 0x6, 0x8 }, // 4449
|
|
{ PseudoVLSSEG5E8_V_MF4_MASK, VLSSEG5E8_V, 0x6, 0x8 }, // 4450
|
|
{ PseudoVLSSEG5E8_V_MF2, VLSSEG5E8_V, 0x7, 0x8 }, // 4451
|
|
{ PseudoVLSSEG5E8_V_MF2_MASK, VLSSEG5E8_V, 0x7, 0x8 }, // 4452
|
|
{ PseudoVLSSEG6E16_V_M1, VLSSEG6E16_V, 0x0, 0x10 }, // 4453
|
|
{ PseudoVLSSEG6E16_V_M1_MASK, VLSSEG6E16_V, 0x0, 0x10 }, // 4454
|
|
{ PseudoVLSSEG6E16_V_MF4, VLSSEG6E16_V, 0x6, 0x10 }, // 4455
|
|
{ PseudoVLSSEG6E16_V_MF4_MASK, VLSSEG6E16_V, 0x6, 0x10 }, // 4456
|
|
{ PseudoVLSSEG6E16_V_MF2, VLSSEG6E16_V, 0x7, 0x10 }, // 4457
|
|
{ PseudoVLSSEG6E16_V_MF2_MASK, VLSSEG6E16_V, 0x7, 0x10 }, // 4458
|
|
{ PseudoVLSSEG6E32_V_M1, VLSSEG6E32_V, 0x0, 0x20 }, // 4459
|
|
{ PseudoVLSSEG6E32_V_M1_MASK, VLSSEG6E32_V, 0x0, 0x20 }, // 4460
|
|
{ PseudoVLSSEG6E32_V_MF2, VLSSEG6E32_V, 0x7, 0x20 }, // 4461
|
|
{ PseudoVLSSEG6E32_V_MF2_MASK, VLSSEG6E32_V, 0x7, 0x20 }, // 4462
|
|
{ PseudoVLSSEG6E64_V_M1, VLSSEG6E64_V, 0x0, 0x40 }, // 4463
|
|
{ PseudoVLSSEG6E64_V_M1_MASK, VLSSEG6E64_V, 0x0, 0x40 }, // 4464
|
|
{ PseudoVLSSEG6E8_V_M1, VLSSEG6E8_V, 0x0, 0x8 }, // 4465
|
|
{ PseudoVLSSEG6E8_V_M1_MASK, VLSSEG6E8_V, 0x0, 0x8 }, // 4466
|
|
{ PseudoVLSSEG6E8_V_MF8, VLSSEG6E8_V, 0x5, 0x8 }, // 4467
|
|
{ PseudoVLSSEG6E8_V_MF8_MASK, VLSSEG6E8_V, 0x5, 0x8 }, // 4468
|
|
{ PseudoVLSSEG6E8_V_MF4, VLSSEG6E8_V, 0x6, 0x8 }, // 4469
|
|
{ PseudoVLSSEG6E8_V_MF4_MASK, VLSSEG6E8_V, 0x6, 0x8 }, // 4470
|
|
{ PseudoVLSSEG6E8_V_MF2, VLSSEG6E8_V, 0x7, 0x8 }, // 4471
|
|
{ PseudoVLSSEG6E8_V_MF2_MASK, VLSSEG6E8_V, 0x7, 0x8 }, // 4472
|
|
{ PseudoVLSSEG7E16_V_M1, VLSSEG7E16_V, 0x0, 0x10 }, // 4473
|
|
{ PseudoVLSSEG7E16_V_M1_MASK, VLSSEG7E16_V, 0x0, 0x10 }, // 4474
|
|
{ PseudoVLSSEG7E16_V_MF4, VLSSEG7E16_V, 0x6, 0x10 }, // 4475
|
|
{ PseudoVLSSEG7E16_V_MF4_MASK, VLSSEG7E16_V, 0x6, 0x10 }, // 4476
|
|
{ PseudoVLSSEG7E16_V_MF2, VLSSEG7E16_V, 0x7, 0x10 }, // 4477
|
|
{ PseudoVLSSEG7E16_V_MF2_MASK, VLSSEG7E16_V, 0x7, 0x10 }, // 4478
|
|
{ PseudoVLSSEG7E32_V_M1, VLSSEG7E32_V, 0x0, 0x20 }, // 4479
|
|
{ PseudoVLSSEG7E32_V_M1_MASK, VLSSEG7E32_V, 0x0, 0x20 }, // 4480
|
|
{ PseudoVLSSEG7E32_V_MF2, VLSSEG7E32_V, 0x7, 0x20 }, // 4481
|
|
{ PseudoVLSSEG7E32_V_MF2_MASK, VLSSEG7E32_V, 0x7, 0x20 }, // 4482
|
|
{ PseudoVLSSEG7E64_V_M1, VLSSEG7E64_V, 0x0, 0x40 }, // 4483
|
|
{ PseudoVLSSEG7E64_V_M1_MASK, VLSSEG7E64_V, 0x0, 0x40 }, // 4484
|
|
{ PseudoVLSSEG7E8_V_M1, VLSSEG7E8_V, 0x0, 0x8 }, // 4485
|
|
{ PseudoVLSSEG7E8_V_M1_MASK, VLSSEG7E8_V, 0x0, 0x8 }, // 4486
|
|
{ PseudoVLSSEG7E8_V_MF8, VLSSEG7E8_V, 0x5, 0x8 }, // 4487
|
|
{ PseudoVLSSEG7E8_V_MF8_MASK, VLSSEG7E8_V, 0x5, 0x8 }, // 4488
|
|
{ PseudoVLSSEG7E8_V_MF4, VLSSEG7E8_V, 0x6, 0x8 }, // 4489
|
|
{ PseudoVLSSEG7E8_V_MF4_MASK, VLSSEG7E8_V, 0x6, 0x8 }, // 4490
|
|
{ PseudoVLSSEG7E8_V_MF2, VLSSEG7E8_V, 0x7, 0x8 }, // 4491
|
|
{ PseudoVLSSEG7E8_V_MF2_MASK, VLSSEG7E8_V, 0x7, 0x8 }, // 4492
|
|
{ PseudoVLSSEG8E16_V_M1, VLSSEG8E16_V, 0x0, 0x10 }, // 4493
|
|
{ PseudoVLSSEG8E16_V_M1_MASK, VLSSEG8E16_V, 0x0, 0x10 }, // 4494
|
|
{ PseudoVLSSEG8E16_V_MF4, VLSSEG8E16_V, 0x6, 0x10 }, // 4495
|
|
{ PseudoVLSSEG8E16_V_MF4_MASK, VLSSEG8E16_V, 0x6, 0x10 }, // 4496
|
|
{ PseudoVLSSEG8E16_V_MF2, VLSSEG8E16_V, 0x7, 0x10 }, // 4497
|
|
{ PseudoVLSSEG8E16_V_MF2_MASK, VLSSEG8E16_V, 0x7, 0x10 }, // 4498
|
|
{ PseudoVLSSEG8E32_V_M1, VLSSEG8E32_V, 0x0, 0x20 }, // 4499
|
|
{ PseudoVLSSEG8E32_V_M1_MASK, VLSSEG8E32_V, 0x0, 0x20 }, // 4500
|
|
{ PseudoVLSSEG8E32_V_MF2, VLSSEG8E32_V, 0x7, 0x20 }, // 4501
|
|
{ PseudoVLSSEG8E32_V_MF2_MASK, VLSSEG8E32_V, 0x7, 0x20 }, // 4502
|
|
{ PseudoVLSSEG8E64_V_M1, VLSSEG8E64_V, 0x0, 0x40 }, // 4503
|
|
{ PseudoVLSSEG8E64_V_M1_MASK, VLSSEG8E64_V, 0x0, 0x40 }, // 4504
|
|
{ PseudoVLSSEG8E8_V_M1, VLSSEG8E8_V, 0x0, 0x8 }, // 4505
|
|
{ PseudoVLSSEG8E8_V_M1_MASK, VLSSEG8E8_V, 0x0, 0x8 }, // 4506
|
|
{ PseudoVLSSEG8E8_V_MF8, VLSSEG8E8_V, 0x5, 0x8 }, // 4507
|
|
{ PseudoVLSSEG8E8_V_MF8_MASK, VLSSEG8E8_V, 0x5, 0x8 }, // 4508
|
|
{ PseudoVLSSEG8E8_V_MF4, VLSSEG8E8_V, 0x6, 0x8 }, // 4509
|
|
{ PseudoVLSSEG8E8_V_MF4_MASK, VLSSEG8E8_V, 0x6, 0x8 }, // 4510
|
|
{ PseudoVLSSEG8E8_V_MF2, VLSSEG8E8_V, 0x7, 0x8 }, // 4511
|
|
{ PseudoVLSSEG8E8_V_MF2_MASK, VLSSEG8E8_V, 0x7, 0x8 }, // 4512
|
|
{ PseudoVLUXEI16_V_M1_M1, VLUXEI16_V, 0x0, 0x0 }, // 4513
|
|
{ PseudoVLUXEI16_V_M1_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4514
|
|
{ PseudoVLUXEI16_V_M2_M1, VLUXEI16_V, 0x0, 0x0 }, // 4515
|
|
{ PseudoVLUXEI16_V_M2_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4516
|
|
{ PseudoVLUXEI16_V_MF2_M1, VLUXEI16_V, 0x0, 0x0 }, // 4517
|
|
{ PseudoVLUXEI16_V_MF2_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4518
|
|
{ PseudoVLUXEI16_V_MF4_M1, VLUXEI16_V, 0x0, 0x0 }, // 4519
|
|
{ PseudoVLUXEI16_V_MF4_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4520
|
|
{ PseudoVLUXEI16_V_M1_M2, VLUXEI16_V, 0x1, 0x0 }, // 4521
|
|
{ PseudoVLUXEI16_V_M1_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4522
|
|
{ PseudoVLUXEI16_V_M2_M2, VLUXEI16_V, 0x1, 0x0 }, // 4523
|
|
{ PseudoVLUXEI16_V_M2_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4524
|
|
{ PseudoVLUXEI16_V_M4_M2, VLUXEI16_V, 0x1, 0x0 }, // 4525
|
|
{ PseudoVLUXEI16_V_M4_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4526
|
|
{ PseudoVLUXEI16_V_MF2_M2, VLUXEI16_V, 0x1, 0x0 }, // 4527
|
|
{ PseudoVLUXEI16_V_MF2_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4528
|
|
{ PseudoVLUXEI16_V_M1_M4, VLUXEI16_V, 0x2, 0x0 }, // 4529
|
|
{ PseudoVLUXEI16_V_M1_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4530
|
|
{ PseudoVLUXEI16_V_M2_M4, VLUXEI16_V, 0x2, 0x0 }, // 4531
|
|
{ PseudoVLUXEI16_V_M2_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4532
|
|
{ PseudoVLUXEI16_V_M4_M4, VLUXEI16_V, 0x2, 0x0 }, // 4533
|
|
{ PseudoVLUXEI16_V_M4_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4534
|
|
{ PseudoVLUXEI16_V_M8_M4, VLUXEI16_V, 0x2, 0x0 }, // 4535
|
|
{ PseudoVLUXEI16_V_M8_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4536
|
|
{ PseudoVLUXEI16_V_M2_M8, VLUXEI16_V, 0x3, 0x0 }, // 4537
|
|
{ PseudoVLUXEI16_V_M2_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 4538
|
|
{ PseudoVLUXEI16_V_M4_M8, VLUXEI16_V, 0x3, 0x0 }, // 4539
|
|
{ PseudoVLUXEI16_V_M4_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 4540
|
|
{ PseudoVLUXEI16_V_M8_M8, VLUXEI16_V, 0x3, 0x0 }, // 4541
|
|
{ PseudoVLUXEI16_V_M8_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 4542
|
|
{ PseudoVLUXEI16_V_MF4_MF8, VLUXEI16_V, 0x5, 0x0 }, // 4543
|
|
{ PseudoVLUXEI16_V_MF4_MF8_MASK, VLUXEI16_V, 0x5, 0x0 }, // 4544
|
|
{ PseudoVLUXEI16_V_MF2_MF4, VLUXEI16_V, 0x6, 0x0 }, // 4545
|
|
{ PseudoVLUXEI16_V_MF2_MF4_MASK, VLUXEI16_V, 0x6, 0x0 }, // 4546
|
|
{ PseudoVLUXEI16_V_MF4_MF4, VLUXEI16_V, 0x6, 0x0 }, // 4547
|
|
{ PseudoVLUXEI16_V_MF4_MF4_MASK, VLUXEI16_V, 0x6, 0x0 }, // 4548
|
|
{ PseudoVLUXEI16_V_M1_MF2, VLUXEI16_V, 0x7, 0x0 }, // 4549
|
|
{ PseudoVLUXEI16_V_M1_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 4550
|
|
{ PseudoVLUXEI16_V_MF2_MF2, VLUXEI16_V, 0x7, 0x0 }, // 4551
|
|
{ PseudoVLUXEI16_V_MF2_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 4552
|
|
{ PseudoVLUXEI16_V_MF4_MF2, VLUXEI16_V, 0x7, 0x0 }, // 4553
|
|
{ PseudoVLUXEI16_V_MF4_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 4554
|
|
{ PseudoVLUXEI32_V_M1_M1, VLUXEI32_V, 0x0, 0x0 }, // 4555
|
|
{ PseudoVLUXEI32_V_M1_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4556
|
|
{ PseudoVLUXEI32_V_M2_M1, VLUXEI32_V, 0x0, 0x0 }, // 4557
|
|
{ PseudoVLUXEI32_V_M2_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4558
|
|
{ PseudoVLUXEI32_V_M4_M1, VLUXEI32_V, 0x0, 0x0 }, // 4559
|
|
{ PseudoVLUXEI32_V_M4_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4560
|
|
{ PseudoVLUXEI32_V_MF2_M1, VLUXEI32_V, 0x0, 0x0 }, // 4561
|
|
{ PseudoVLUXEI32_V_MF2_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4562
|
|
{ PseudoVLUXEI32_V_M1_M2, VLUXEI32_V, 0x1, 0x0 }, // 4563
|
|
{ PseudoVLUXEI32_V_M1_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4564
|
|
{ PseudoVLUXEI32_V_M2_M2, VLUXEI32_V, 0x1, 0x0 }, // 4565
|
|
{ PseudoVLUXEI32_V_M2_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4566
|
|
{ PseudoVLUXEI32_V_M4_M2, VLUXEI32_V, 0x1, 0x0 }, // 4567
|
|
{ PseudoVLUXEI32_V_M4_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4568
|
|
{ PseudoVLUXEI32_V_M8_M2, VLUXEI32_V, 0x1, 0x0 }, // 4569
|
|
{ PseudoVLUXEI32_V_M8_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4570
|
|
{ PseudoVLUXEI32_V_M2_M4, VLUXEI32_V, 0x2, 0x0 }, // 4571
|
|
{ PseudoVLUXEI32_V_M2_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 4572
|
|
{ PseudoVLUXEI32_V_M4_M4, VLUXEI32_V, 0x2, 0x0 }, // 4573
|
|
{ PseudoVLUXEI32_V_M4_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 4574
|
|
{ PseudoVLUXEI32_V_M8_M4, VLUXEI32_V, 0x2, 0x0 }, // 4575
|
|
{ PseudoVLUXEI32_V_M8_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 4576
|
|
{ PseudoVLUXEI32_V_M4_M8, VLUXEI32_V, 0x3, 0x0 }, // 4577
|
|
{ PseudoVLUXEI32_V_M4_M8_MASK, VLUXEI32_V, 0x3, 0x0 }, // 4578
|
|
{ PseudoVLUXEI32_V_M8_M8, VLUXEI32_V, 0x3, 0x0 }, // 4579
|
|
{ PseudoVLUXEI32_V_M8_M8_MASK, VLUXEI32_V, 0x3, 0x0 }, // 4580
|
|
{ PseudoVLUXEI32_V_MF2_MF8, VLUXEI32_V, 0x5, 0x0 }, // 4581
|
|
{ PseudoVLUXEI32_V_MF2_MF8_MASK, VLUXEI32_V, 0x5, 0x0 }, // 4582
|
|
{ PseudoVLUXEI32_V_M1_MF4, VLUXEI32_V, 0x6, 0x0 }, // 4583
|
|
{ PseudoVLUXEI32_V_M1_MF4_MASK, VLUXEI32_V, 0x6, 0x0 }, // 4584
|
|
{ PseudoVLUXEI32_V_MF2_MF4, VLUXEI32_V, 0x6, 0x0 }, // 4585
|
|
{ PseudoVLUXEI32_V_MF2_MF4_MASK, VLUXEI32_V, 0x6, 0x0 }, // 4586
|
|
{ PseudoVLUXEI32_V_M1_MF2, VLUXEI32_V, 0x7, 0x0 }, // 4587
|
|
{ PseudoVLUXEI32_V_M1_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 4588
|
|
{ PseudoVLUXEI32_V_M2_MF2, VLUXEI32_V, 0x7, 0x0 }, // 4589
|
|
{ PseudoVLUXEI32_V_M2_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 4590
|
|
{ PseudoVLUXEI32_V_MF2_MF2, VLUXEI32_V, 0x7, 0x0 }, // 4591
|
|
{ PseudoVLUXEI32_V_MF2_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 4592
|
|
{ PseudoVLUXEI64_V_M1_M1, VLUXEI64_V, 0x0, 0x0 }, // 4593
|
|
{ PseudoVLUXEI64_V_M1_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4594
|
|
{ PseudoVLUXEI64_V_M2_M1, VLUXEI64_V, 0x0, 0x0 }, // 4595
|
|
{ PseudoVLUXEI64_V_M2_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4596
|
|
{ PseudoVLUXEI64_V_M4_M1, VLUXEI64_V, 0x0, 0x0 }, // 4597
|
|
{ PseudoVLUXEI64_V_M4_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4598
|
|
{ PseudoVLUXEI64_V_M8_M1, VLUXEI64_V, 0x0, 0x0 }, // 4599
|
|
{ PseudoVLUXEI64_V_M8_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4600
|
|
{ PseudoVLUXEI64_V_M2_M2, VLUXEI64_V, 0x1, 0x0 }, // 4601
|
|
{ PseudoVLUXEI64_V_M2_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 4602
|
|
{ PseudoVLUXEI64_V_M4_M2, VLUXEI64_V, 0x1, 0x0 }, // 4603
|
|
{ PseudoVLUXEI64_V_M4_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 4604
|
|
{ PseudoVLUXEI64_V_M8_M2, VLUXEI64_V, 0x1, 0x0 }, // 4605
|
|
{ PseudoVLUXEI64_V_M8_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 4606
|
|
{ PseudoVLUXEI64_V_M4_M4, VLUXEI64_V, 0x2, 0x0 }, // 4607
|
|
{ PseudoVLUXEI64_V_M4_M4_MASK, VLUXEI64_V, 0x2, 0x0 }, // 4608
|
|
{ PseudoVLUXEI64_V_M8_M4, VLUXEI64_V, 0x2, 0x0 }, // 4609
|
|
{ PseudoVLUXEI64_V_M8_M4_MASK, VLUXEI64_V, 0x2, 0x0 }, // 4610
|
|
{ PseudoVLUXEI64_V_M8_M8, VLUXEI64_V, 0x3, 0x0 }, // 4611
|
|
{ PseudoVLUXEI64_V_M8_M8_MASK, VLUXEI64_V, 0x3, 0x0 }, // 4612
|
|
{ PseudoVLUXEI64_V_M1_MF8, VLUXEI64_V, 0x5, 0x0 }, // 4613
|
|
{ PseudoVLUXEI64_V_M1_MF8_MASK, VLUXEI64_V, 0x5, 0x0 }, // 4614
|
|
{ PseudoVLUXEI64_V_M1_MF4, VLUXEI64_V, 0x6, 0x0 }, // 4615
|
|
{ PseudoVLUXEI64_V_M1_MF4_MASK, VLUXEI64_V, 0x6, 0x0 }, // 4616
|
|
{ PseudoVLUXEI64_V_M2_MF4, VLUXEI64_V, 0x6, 0x0 }, // 4617
|
|
{ PseudoVLUXEI64_V_M2_MF4_MASK, VLUXEI64_V, 0x6, 0x0 }, // 4618
|
|
{ PseudoVLUXEI64_V_M1_MF2, VLUXEI64_V, 0x7, 0x0 }, // 4619
|
|
{ PseudoVLUXEI64_V_M1_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 4620
|
|
{ PseudoVLUXEI64_V_M2_MF2, VLUXEI64_V, 0x7, 0x0 }, // 4621
|
|
{ PseudoVLUXEI64_V_M2_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 4622
|
|
{ PseudoVLUXEI64_V_M4_MF2, VLUXEI64_V, 0x7, 0x0 }, // 4623
|
|
{ PseudoVLUXEI64_V_M4_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 4624
|
|
{ PseudoVLUXEI8_V_M1_M1, VLUXEI8_V, 0x0, 0x0 }, // 4625
|
|
{ PseudoVLUXEI8_V_M1_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4626
|
|
{ PseudoVLUXEI8_V_MF2_M1, VLUXEI8_V, 0x0, 0x0 }, // 4627
|
|
{ PseudoVLUXEI8_V_MF2_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4628
|
|
{ PseudoVLUXEI8_V_MF4_M1, VLUXEI8_V, 0x0, 0x0 }, // 4629
|
|
{ PseudoVLUXEI8_V_MF4_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4630
|
|
{ PseudoVLUXEI8_V_MF8_M1, VLUXEI8_V, 0x0, 0x0 }, // 4631
|
|
{ PseudoVLUXEI8_V_MF8_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4632
|
|
{ PseudoVLUXEI8_V_M1_M2, VLUXEI8_V, 0x1, 0x0 }, // 4633
|
|
{ PseudoVLUXEI8_V_M1_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4634
|
|
{ PseudoVLUXEI8_V_M2_M2, VLUXEI8_V, 0x1, 0x0 }, // 4635
|
|
{ PseudoVLUXEI8_V_M2_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4636
|
|
{ PseudoVLUXEI8_V_MF2_M2, VLUXEI8_V, 0x1, 0x0 }, // 4637
|
|
{ PseudoVLUXEI8_V_MF2_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4638
|
|
{ PseudoVLUXEI8_V_MF4_M2, VLUXEI8_V, 0x1, 0x0 }, // 4639
|
|
{ PseudoVLUXEI8_V_MF4_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4640
|
|
{ PseudoVLUXEI8_V_M1_M4, VLUXEI8_V, 0x2, 0x0 }, // 4641
|
|
{ PseudoVLUXEI8_V_M1_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4642
|
|
{ PseudoVLUXEI8_V_M2_M4, VLUXEI8_V, 0x2, 0x0 }, // 4643
|
|
{ PseudoVLUXEI8_V_M2_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4644
|
|
{ PseudoVLUXEI8_V_M4_M4, VLUXEI8_V, 0x2, 0x0 }, // 4645
|
|
{ PseudoVLUXEI8_V_M4_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4646
|
|
{ PseudoVLUXEI8_V_MF2_M4, VLUXEI8_V, 0x2, 0x0 }, // 4647
|
|
{ PseudoVLUXEI8_V_MF2_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4648
|
|
{ PseudoVLUXEI8_V_M1_M8, VLUXEI8_V, 0x3, 0x0 }, // 4649
|
|
{ PseudoVLUXEI8_V_M1_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4650
|
|
{ PseudoVLUXEI8_V_M2_M8, VLUXEI8_V, 0x3, 0x0 }, // 4651
|
|
{ PseudoVLUXEI8_V_M2_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4652
|
|
{ PseudoVLUXEI8_V_M4_M8, VLUXEI8_V, 0x3, 0x0 }, // 4653
|
|
{ PseudoVLUXEI8_V_M4_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4654
|
|
{ PseudoVLUXEI8_V_M8_M8, VLUXEI8_V, 0x3, 0x0 }, // 4655
|
|
{ PseudoVLUXEI8_V_M8_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4656
|
|
{ PseudoVLUXEI8_V_MF8_MF8, VLUXEI8_V, 0x5, 0x0 }, // 4657
|
|
{ PseudoVLUXEI8_V_MF8_MF8_MASK, VLUXEI8_V, 0x5, 0x0 }, // 4658
|
|
{ PseudoVLUXEI8_V_MF4_MF4, VLUXEI8_V, 0x6, 0x0 }, // 4659
|
|
{ PseudoVLUXEI8_V_MF4_MF4_MASK, VLUXEI8_V, 0x6, 0x0 }, // 4660
|
|
{ PseudoVLUXEI8_V_MF8_MF4, VLUXEI8_V, 0x6, 0x0 }, // 4661
|
|
{ PseudoVLUXEI8_V_MF8_MF4_MASK, VLUXEI8_V, 0x6, 0x0 }, // 4662
|
|
{ PseudoVLUXEI8_V_MF2_MF2, VLUXEI8_V, 0x7, 0x0 }, // 4663
|
|
{ PseudoVLUXEI8_V_MF2_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 4664
|
|
{ PseudoVLUXEI8_V_MF4_MF2, VLUXEI8_V, 0x7, 0x0 }, // 4665
|
|
{ PseudoVLUXEI8_V_MF4_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 4666
|
|
{ PseudoVLUXEI8_V_MF8_MF2, VLUXEI8_V, 0x7, 0x0 }, // 4667
|
|
{ PseudoVLUXEI8_V_MF8_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 4668
|
|
{ PseudoVLUXSEG2EI16_V_M1_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4669
|
|
{ PseudoVLUXSEG2EI16_V_M1_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4670
|
|
{ PseudoVLUXSEG2EI16_V_M2_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4671
|
|
{ PseudoVLUXSEG2EI16_V_M2_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4672
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4673
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4674
|
|
{ PseudoVLUXSEG2EI16_V_MF4_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4675
|
|
{ PseudoVLUXSEG2EI16_V_MF4_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4676
|
|
{ PseudoVLUXSEG2EI16_V_M1_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4677
|
|
{ PseudoVLUXSEG2EI16_V_M1_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4678
|
|
{ PseudoVLUXSEG2EI16_V_M2_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4679
|
|
{ PseudoVLUXSEG2EI16_V_M2_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4680
|
|
{ PseudoVLUXSEG2EI16_V_M4_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4681
|
|
{ PseudoVLUXSEG2EI16_V_M4_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4682
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4683
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4684
|
|
{ PseudoVLUXSEG2EI16_V_M1_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4685
|
|
{ PseudoVLUXSEG2EI16_V_M1_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4686
|
|
{ PseudoVLUXSEG2EI16_V_M2_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4687
|
|
{ PseudoVLUXSEG2EI16_V_M2_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4688
|
|
{ PseudoVLUXSEG2EI16_V_M4_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4689
|
|
{ PseudoVLUXSEG2EI16_V_M4_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4690
|
|
{ PseudoVLUXSEG2EI16_V_M8_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4691
|
|
{ PseudoVLUXSEG2EI16_V_M8_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4692
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF8, VLUXSEG2EI16_V, 0x5, 0x0 }, // 4693
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, VLUXSEG2EI16_V, 0x5, 0x0 }, // 4694
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF4, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4695
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4696
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF4, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4697
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4698
|
|
{ PseudoVLUXSEG2EI16_V_M1_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4699
|
|
{ PseudoVLUXSEG2EI16_V_M1_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4700
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4701
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4702
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4703
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4704
|
|
{ PseudoVLUXSEG2EI32_V_M1_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4705
|
|
{ PseudoVLUXSEG2EI32_V_M1_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4706
|
|
{ PseudoVLUXSEG2EI32_V_M2_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4707
|
|
{ PseudoVLUXSEG2EI32_V_M2_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4708
|
|
{ PseudoVLUXSEG2EI32_V_M4_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4709
|
|
{ PseudoVLUXSEG2EI32_V_M4_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4710
|
|
{ PseudoVLUXSEG2EI32_V_MF2_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4711
|
|
{ PseudoVLUXSEG2EI32_V_MF2_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4712
|
|
{ PseudoVLUXSEG2EI32_V_M1_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4713
|
|
{ PseudoVLUXSEG2EI32_V_M1_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4714
|
|
{ PseudoVLUXSEG2EI32_V_M2_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4715
|
|
{ PseudoVLUXSEG2EI32_V_M2_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4716
|
|
{ PseudoVLUXSEG2EI32_V_M4_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4717
|
|
{ PseudoVLUXSEG2EI32_V_M4_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4718
|
|
{ PseudoVLUXSEG2EI32_V_M8_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4719
|
|
{ PseudoVLUXSEG2EI32_V_M8_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4720
|
|
{ PseudoVLUXSEG2EI32_V_M2_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4721
|
|
{ PseudoVLUXSEG2EI32_V_M2_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4722
|
|
{ PseudoVLUXSEG2EI32_V_M4_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4723
|
|
{ PseudoVLUXSEG2EI32_V_M4_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4724
|
|
{ PseudoVLUXSEG2EI32_V_M8_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4725
|
|
{ PseudoVLUXSEG2EI32_V_M8_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4726
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF8, VLUXSEG2EI32_V, 0x5, 0x0 }, // 4727
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, VLUXSEG2EI32_V, 0x5, 0x0 }, // 4728
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF4, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4729
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF4_MASK, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4730
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF4, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4731
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4732
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4733
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4734
|
|
{ PseudoVLUXSEG2EI32_V_M2_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4735
|
|
{ PseudoVLUXSEG2EI32_V_M2_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4736
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4737
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4738
|
|
{ PseudoVLUXSEG2EI64_V_M1_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4739
|
|
{ PseudoVLUXSEG2EI64_V_M1_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4740
|
|
{ PseudoVLUXSEG2EI64_V_M2_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4741
|
|
{ PseudoVLUXSEG2EI64_V_M2_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4742
|
|
{ PseudoVLUXSEG2EI64_V_M4_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4743
|
|
{ PseudoVLUXSEG2EI64_V_M4_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4744
|
|
{ PseudoVLUXSEG2EI64_V_M8_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4745
|
|
{ PseudoVLUXSEG2EI64_V_M8_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4746
|
|
{ PseudoVLUXSEG2EI64_V_M2_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4747
|
|
{ PseudoVLUXSEG2EI64_V_M2_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4748
|
|
{ PseudoVLUXSEG2EI64_V_M4_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4749
|
|
{ PseudoVLUXSEG2EI64_V_M4_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4750
|
|
{ PseudoVLUXSEG2EI64_V_M8_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4751
|
|
{ PseudoVLUXSEG2EI64_V_M8_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4752
|
|
{ PseudoVLUXSEG2EI64_V_M4_M4, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4753
|
|
{ PseudoVLUXSEG2EI64_V_M4_M4_MASK, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4754
|
|
{ PseudoVLUXSEG2EI64_V_M8_M4, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4755
|
|
{ PseudoVLUXSEG2EI64_V_M8_M4_MASK, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4756
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF8, VLUXSEG2EI64_V, 0x5, 0x0 }, // 4757
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF8_MASK, VLUXSEG2EI64_V, 0x5, 0x0 }, // 4758
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF4, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4759
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF4_MASK, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4760
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF4, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4761
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF4_MASK, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4762
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4763
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4764
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4765
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4766
|
|
{ PseudoVLUXSEG2EI64_V_M4_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4767
|
|
{ PseudoVLUXSEG2EI64_V_M4_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4768
|
|
{ PseudoVLUXSEG2EI8_V_M1_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4769
|
|
{ PseudoVLUXSEG2EI8_V_M1_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4770
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4771
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4772
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4773
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4774
|
|
{ PseudoVLUXSEG2EI8_V_MF8_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4775
|
|
{ PseudoVLUXSEG2EI8_V_MF8_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4776
|
|
{ PseudoVLUXSEG2EI8_V_M1_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4777
|
|
{ PseudoVLUXSEG2EI8_V_M1_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4778
|
|
{ PseudoVLUXSEG2EI8_V_M2_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4779
|
|
{ PseudoVLUXSEG2EI8_V_M2_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4780
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4781
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4782
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4783
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4784
|
|
{ PseudoVLUXSEG2EI8_V_M1_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4785
|
|
{ PseudoVLUXSEG2EI8_V_M1_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4786
|
|
{ PseudoVLUXSEG2EI8_V_M2_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4787
|
|
{ PseudoVLUXSEG2EI8_V_M2_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4788
|
|
{ PseudoVLUXSEG2EI8_V_M4_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4789
|
|
{ PseudoVLUXSEG2EI8_V_M4_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4790
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4791
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4792
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF8, VLUXSEG2EI8_V, 0x5, 0x0 }, // 4793
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, VLUXSEG2EI8_V, 0x5, 0x0 }, // 4794
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF4, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4795
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4796
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF4, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4797
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4798
|
|
{ PseudoVLUXSEG2EI8_V_MF2_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4799
|
|
{ PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4800
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4801
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4802
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4803
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4804
|
|
{ PseudoVLUXSEG3EI16_V_M1_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4805
|
|
{ PseudoVLUXSEG3EI16_V_M1_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4806
|
|
{ PseudoVLUXSEG3EI16_V_M2_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4807
|
|
{ PseudoVLUXSEG3EI16_V_M2_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4808
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4809
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4810
|
|
{ PseudoVLUXSEG3EI16_V_MF4_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4811
|
|
{ PseudoVLUXSEG3EI16_V_MF4_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4812
|
|
{ PseudoVLUXSEG3EI16_V_M1_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4813
|
|
{ PseudoVLUXSEG3EI16_V_M1_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4814
|
|
{ PseudoVLUXSEG3EI16_V_M2_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4815
|
|
{ PseudoVLUXSEG3EI16_V_M2_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4816
|
|
{ PseudoVLUXSEG3EI16_V_M4_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4817
|
|
{ PseudoVLUXSEG3EI16_V_M4_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4818
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4819
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4820
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF8, VLUXSEG3EI16_V, 0x5, 0x0 }, // 4821
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, VLUXSEG3EI16_V, 0x5, 0x0 }, // 4822
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF4, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4823
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4824
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF4, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4825
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4826
|
|
{ PseudoVLUXSEG3EI16_V_M1_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4827
|
|
{ PseudoVLUXSEG3EI16_V_M1_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4828
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4829
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4830
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4831
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4832
|
|
{ PseudoVLUXSEG3EI32_V_M1_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4833
|
|
{ PseudoVLUXSEG3EI32_V_M1_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4834
|
|
{ PseudoVLUXSEG3EI32_V_M2_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4835
|
|
{ PseudoVLUXSEG3EI32_V_M2_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4836
|
|
{ PseudoVLUXSEG3EI32_V_M4_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4837
|
|
{ PseudoVLUXSEG3EI32_V_M4_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4838
|
|
{ PseudoVLUXSEG3EI32_V_MF2_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4839
|
|
{ PseudoVLUXSEG3EI32_V_MF2_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4840
|
|
{ PseudoVLUXSEG3EI32_V_M1_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4841
|
|
{ PseudoVLUXSEG3EI32_V_M1_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4842
|
|
{ PseudoVLUXSEG3EI32_V_M2_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4843
|
|
{ PseudoVLUXSEG3EI32_V_M2_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4844
|
|
{ PseudoVLUXSEG3EI32_V_M4_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4845
|
|
{ PseudoVLUXSEG3EI32_V_M4_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4846
|
|
{ PseudoVLUXSEG3EI32_V_M8_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4847
|
|
{ PseudoVLUXSEG3EI32_V_M8_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4848
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF8, VLUXSEG3EI32_V, 0x5, 0x0 }, // 4849
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, VLUXSEG3EI32_V, 0x5, 0x0 }, // 4850
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF4, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4851
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF4_MASK, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4852
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF4, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4853
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4854
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4855
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4856
|
|
{ PseudoVLUXSEG3EI32_V_M2_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4857
|
|
{ PseudoVLUXSEG3EI32_V_M2_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4858
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4859
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4860
|
|
{ PseudoVLUXSEG3EI64_V_M1_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4861
|
|
{ PseudoVLUXSEG3EI64_V_M1_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4862
|
|
{ PseudoVLUXSEG3EI64_V_M2_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4863
|
|
{ PseudoVLUXSEG3EI64_V_M2_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4864
|
|
{ PseudoVLUXSEG3EI64_V_M4_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4865
|
|
{ PseudoVLUXSEG3EI64_V_M4_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4866
|
|
{ PseudoVLUXSEG3EI64_V_M8_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4867
|
|
{ PseudoVLUXSEG3EI64_V_M8_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4868
|
|
{ PseudoVLUXSEG3EI64_V_M2_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4869
|
|
{ PseudoVLUXSEG3EI64_V_M2_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4870
|
|
{ PseudoVLUXSEG3EI64_V_M4_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4871
|
|
{ PseudoVLUXSEG3EI64_V_M4_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4872
|
|
{ PseudoVLUXSEG3EI64_V_M8_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4873
|
|
{ PseudoVLUXSEG3EI64_V_M8_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4874
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF8, VLUXSEG3EI64_V, 0x5, 0x0 }, // 4875
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF8_MASK, VLUXSEG3EI64_V, 0x5, 0x0 }, // 4876
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF4, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4877
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF4_MASK, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4878
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF4, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4879
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF4_MASK, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4880
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4881
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4882
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4883
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4884
|
|
{ PseudoVLUXSEG3EI64_V_M4_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4885
|
|
{ PseudoVLUXSEG3EI64_V_M4_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4886
|
|
{ PseudoVLUXSEG3EI8_V_M1_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4887
|
|
{ PseudoVLUXSEG3EI8_V_M1_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4888
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4889
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4890
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4891
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4892
|
|
{ PseudoVLUXSEG3EI8_V_MF8_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4893
|
|
{ PseudoVLUXSEG3EI8_V_MF8_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4894
|
|
{ PseudoVLUXSEG3EI8_V_M1_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4895
|
|
{ PseudoVLUXSEG3EI8_V_M1_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4896
|
|
{ PseudoVLUXSEG3EI8_V_M2_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4897
|
|
{ PseudoVLUXSEG3EI8_V_M2_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4898
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4899
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4900
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4901
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4902
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF8, VLUXSEG3EI8_V, 0x5, 0x0 }, // 4903
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, VLUXSEG3EI8_V, 0x5, 0x0 }, // 4904
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF4, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4905
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4906
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF4, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4907
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4908
|
|
{ PseudoVLUXSEG3EI8_V_MF2_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4909
|
|
{ PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4910
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4911
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4912
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4913
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4914
|
|
{ PseudoVLUXSEG4EI16_V_M1_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4915
|
|
{ PseudoVLUXSEG4EI16_V_M1_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4916
|
|
{ PseudoVLUXSEG4EI16_V_M2_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4917
|
|
{ PseudoVLUXSEG4EI16_V_M2_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4918
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4919
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4920
|
|
{ PseudoVLUXSEG4EI16_V_MF4_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4921
|
|
{ PseudoVLUXSEG4EI16_V_MF4_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4922
|
|
{ PseudoVLUXSEG4EI16_V_M1_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4923
|
|
{ PseudoVLUXSEG4EI16_V_M1_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4924
|
|
{ PseudoVLUXSEG4EI16_V_M2_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4925
|
|
{ PseudoVLUXSEG4EI16_V_M2_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4926
|
|
{ PseudoVLUXSEG4EI16_V_M4_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4927
|
|
{ PseudoVLUXSEG4EI16_V_M4_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4928
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4929
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4930
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF8, VLUXSEG4EI16_V, 0x5, 0x0 }, // 4931
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, VLUXSEG4EI16_V, 0x5, 0x0 }, // 4932
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF4, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4933
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4934
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF4, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4935
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4936
|
|
{ PseudoVLUXSEG4EI16_V_M1_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4937
|
|
{ PseudoVLUXSEG4EI16_V_M1_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4938
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4939
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4940
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4941
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4942
|
|
{ PseudoVLUXSEG4EI32_V_M1_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4943
|
|
{ PseudoVLUXSEG4EI32_V_M1_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4944
|
|
{ PseudoVLUXSEG4EI32_V_M2_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4945
|
|
{ PseudoVLUXSEG4EI32_V_M2_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4946
|
|
{ PseudoVLUXSEG4EI32_V_M4_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4947
|
|
{ PseudoVLUXSEG4EI32_V_M4_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4948
|
|
{ PseudoVLUXSEG4EI32_V_MF2_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4949
|
|
{ PseudoVLUXSEG4EI32_V_MF2_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4950
|
|
{ PseudoVLUXSEG4EI32_V_M1_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4951
|
|
{ PseudoVLUXSEG4EI32_V_M1_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4952
|
|
{ PseudoVLUXSEG4EI32_V_M2_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4953
|
|
{ PseudoVLUXSEG4EI32_V_M2_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4954
|
|
{ PseudoVLUXSEG4EI32_V_M4_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4955
|
|
{ PseudoVLUXSEG4EI32_V_M4_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4956
|
|
{ PseudoVLUXSEG4EI32_V_M8_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4957
|
|
{ PseudoVLUXSEG4EI32_V_M8_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4958
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF8, VLUXSEG4EI32_V, 0x5, 0x0 }, // 4959
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, VLUXSEG4EI32_V, 0x5, 0x0 }, // 4960
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF4, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4961
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF4_MASK, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4962
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF4, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4963
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4964
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4965
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4966
|
|
{ PseudoVLUXSEG4EI32_V_M2_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4967
|
|
{ PseudoVLUXSEG4EI32_V_M2_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4968
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4969
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4970
|
|
{ PseudoVLUXSEG4EI64_V_M1_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4971
|
|
{ PseudoVLUXSEG4EI64_V_M1_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4972
|
|
{ PseudoVLUXSEG4EI64_V_M2_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4973
|
|
{ PseudoVLUXSEG4EI64_V_M2_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4974
|
|
{ PseudoVLUXSEG4EI64_V_M4_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4975
|
|
{ PseudoVLUXSEG4EI64_V_M4_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4976
|
|
{ PseudoVLUXSEG4EI64_V_M8_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4977
|
|
{ PseudoVLUXSEG4EI64_V_M8_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4978
|
|
{ PseudoVLUXSEG4EI64_V_M2_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4979
|
|
{ PseudoVLUXSEG4EI64_V_M2_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4980
|
|
{ PseudoVLUXSEG4EI64_V_M4_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4981
|
|
{ PseudoVLUXSEG4EI64_V_M4_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4982
|
|
{ PseudoVLUXSEG4EI64_V_M8_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4983
|
|
{ PseudoVLUXSEG4EI64_V_M8_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4984
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF8, VLUXSEG4EI64_V, 0x5, 0x0 }, // 4985
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF8_MASK, VLUXSEG4EI64_V, 0x5, 0x0 }, // 4986
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF4, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4987
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF4_MASK, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4988
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF4, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4989
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF4_MASK, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4990
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4991
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4992
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4993
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4994
|
|
{ PseudoVLUXSEG4EI64_V_M4_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4995
|
|
{ PseudoVLUXSEG4EI64_V_M4_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4996
|
|
{ PseudoVLUXSEG4EI8_V_M1_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 4997
|
|
{ PseudoVLUXSEG4EI8_V_M1_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 4998
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 4999
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5000
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5001
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5002
|
|
{ PseudoVLUXSEG4EI8_V_MF8_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5003
|
|
{ PseudoVLUXSEG4EI8_V_MF8_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5004
|
|
{ PseudoVLUXSEG4EI8_V_M1_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5005
|
|
{ PseudoVLUXSEG4EI8_V_M1_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5006
|
|
{ PseudoVLUXSEG4EI8_V_M2_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5007
|
|
{ PseudoVLUXSEG4EI8_V_M2_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5008
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5009
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5010
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5011
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5012
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF8, VLUXSEG4EI8_V, 0x5, 0x0 }, // 5013
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, VLUXSEG4EI8_V, 0x5, 0x0 }, // 5014
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF4, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5015
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5016
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF4, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5017
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5018
|
|
{ PseudoVLUXSEG4EI8_V_MF2_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5019
|
|
{ PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5020
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5021
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5022
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5023
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5024
|
|
{ PseudoVLUXSEG5EI16_V_M1_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5025
|
|
{ PseudoVLUXSEG5EI16_V_M1_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5026
|
|
{ PseudoVLUXSEG5EI16_V_M2_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5027
|
|
{ PseudoVLUXSEG5EI16_V_M2_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5028
|
|
{ PseudoVLUXSEG5EI16_V_MF2_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5029
|
|
{ PseudoVLUXSEG5EI16_V_MF2_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5030
|
|
{ PseudoVLUXSEG5EI16_V_MF4_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5031
|
|
{ PseudoVLUXSEG5EI16_V_MF4_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5032
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF8, VLUXSEG5EI16_V, 0x5, 0x0 }, // 5033
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, VLUXSEG5EI16_V, 0x5, 0x0 }, // 5034
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF4, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5035
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5036
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF4, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5037
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5038
|
|
{ PseudoVLUXSEG5EI16_V_M1_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5039
|
|
{ PseudoVLUXSEG5EI16_V_M1_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5040
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5041
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5042
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5043
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5044
|
|
{ PseudoVLUXSEG5EI32_V_M1_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5045
|
|
{ PseudoVLUXSEG5EI32_V_M1_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5046
|
|
{ PseudoVLUXSEG5EI32_V_M2_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5047
|
|
{ PseudoVLUXSEG5EI32_V_M2_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5048
|
|
{ PseudoVLUXSEG5EI32_V_M4_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5049
|
|
{ PseudoVLUXSEG5EI32_V_M4_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5050
|
|
{ PseudoVLUXSEG5EI32_V_MF2_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5051
|
|
{ PseudoVLUXSEG5EI32_V_MF2_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5052
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF8, VLUXSEG5EI32_V, 0x5, 0x0 }, // 5053
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, VLUXSEG5EI32_V, 0x5, 0x0 }, // 5054
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF4, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5055
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF4_MASK, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5056
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF4, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5057
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5058
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5059
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5060
|
|
{ PseudoVLUXSEG5EI32_V_M2_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5061
|
|
{ PseudoVLUXSEG5EI32_V_M2_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5062
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5063
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5064
|
|
{ PseudoVLUXSEG5EI64_V_M1_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5065
|
|
{ PseudoVLUXSEG5EI64_V_M1_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5066
|
|
{ PseudoVLUXSEG5EI64_V_M2_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5067
|
|
{ PseudoVLUXSEG5EI64_V_M2_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5068
|
|
{ PseudoVLUXSEG5EI64_V_M4_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5069
|
|
{ PseudoVLUXSEG5EI64_V_M4_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5070
|
|
{ PseudoVLUXSEG5EI64_V_M8_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5071
|
|
{ PseudoVLUXSEG5EI64_V_M8_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5072
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF8, VLUXSEG5EI64_V, 0x5, 0x0 }, // 5073
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF8_MASK, VLUXSEG5EI64_V, 0x5, 0x0 }, // 5074
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF4, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5075
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF4_MASK, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5076
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF4, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5077
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF4_MASK, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5078
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5079
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5080
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5081
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5082
|
|
{ PseudoVLUXSEG5EI64_V_M4_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5083
|
|
{ PseudoVLUXSEG5EI64_V_M4_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5084
|
|
{ PseudoVLUXSEG5EI8_V_M1_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5085
|
|
{ PseudoVLUXSEG5EI8_V_M1_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5086
|
|
{ PseudoVLUXSEG5EI8_V_MF2_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5087
|
|
{ PseudoVLUXSEG5EI8_V_MF2_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5088
|
|
{ PseudoVLUXSEG5EI8_V_MF4_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5089
|
|
{ PseudoVLUXSEG5EI8_V_MF4_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5090
|
|
{ PseudoVLUXSEG5EI8_V_MF8_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5091
|
|
{ PseudoVLUXSEG5EI8_V_MF8_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5092
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF8, VLUXSEG5EI8_V, 0x5, 0x0 }, // 5093
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, VLUXSEG5EI8_V, 0x5, 0x0 }, // 5094
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF4, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5095
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5096
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF4, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5097
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5098
|
|
{ PseudoVLUXSEG5EI8_V_MF2_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5099
|
|
{ PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5100
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5101
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5102
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5103
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5104
|
|
{ PseudoVLUXSEG6EI16_V_M1_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5105
|
|
{ PseudoVLUXSEG6EI16_V_M1_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5106
|
|
{ PseudoVLUXSEG6EI16_V_M2_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5107
|
|
{ PseudoVLUXSEG6EI16_V_M2_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5108
|
|
{ PseudoVLUXSEG6EI16_V_MF2_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5109
|
|
{ PseudoVLUXSEG6EI16_V_MF2_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5110
|
|
{ PseudoVLUXSEG6EI16_V_MF4_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5111
|
|
{ PseudoVLUXSEG6EI16_V_MF4_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5112
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF8, VLUXSEG6EI16_V, 0x5, 0x0 }, // 5113
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, VLUXSEG6EI16_V, 0x5, 0x0 }, // 5114
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF4, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5115
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5116
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF4, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5117
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5118
|
|
{ PseudoVLUXSEG6EI16_V_M1_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5119
|
|
{ PseudoVLUXSEG6EI16_V_M1_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5120
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5121
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5122
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5123
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5124
|
|
{ PseudoVLUXSEG6EI32_V_M1_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5125
|
|
{ PseudoVLUXSEG6EI32_V_M1_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5126
|
|
{ PseudoVLUXSEG6EI32_V_M2_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5127
|
|
{ PseudoVLUXSEG6EI32_V_M2_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5128
|
|
{ PseudoVLUXSEG6EI32_V_M4_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5129
|
|
{ PseudoVLUXSEG6EI32_V_M4_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5130
|
|
{ PseudoVLUXSEG6EI32_V_MF2_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5131
|
|
{ PseudoVLUXSEG6EI32_V_MF2_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5132
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF8, VLUXSEG6EI32_V, 0x5, 0x0 }, // 5133
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, VLUXSEG6EI32_V, 0x5, 0x0 }, // 5134
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF4, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5135
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF4_MASK, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5136
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF4, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5137
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5138
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5139
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5140
|
|
{ PseudoVLUXSEG6EI32_V_M2_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5141
|
|
{ PseudoVLUXSEG6EI32_V_M2_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5142
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5143
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5144
|
|
{ PseudoVLUXSEG6EI64_V_M1_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5145
|
|
{ PseudoVLUXSEG6EI64_V_M1_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5146
|
|
{ PseudoVLUXSEG6EI64_V_M2_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5147
|
|
{ PseudoVLUXSEG6EI64_V_M2_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5148
|
|
{ PseudoVLUXSEG6EI64_V_M4_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5149
|
|
{ PseudoVLUXSEG6EI64_V_M4_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5150
|
|
{ PseudoVLUXSEG6EI64_V_M8_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5151
|
|
{ PseudoVLUXSEG6EI64_V_M8_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5152
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF8, VLUXSEG6EI64_V, 0x5, 0x0 }, // 5153
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF8_MASK, VLUXSEG6EI64_V, 0x5, 0x0 }, // 5154
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF4, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5155
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF4_MASK, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5156
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF4, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5157
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF4_MASK, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5158
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5159
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5160
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5161
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5162
|
|
{ PseudoVLUXSEG6EI64_V_M4_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5163
|
|
{ PseudoVLUXSEG6EI64_V_M4_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5164
|
|
{ PseudoVLUXSEG6EI8_V_M1_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5165
|
|
{ PseudoVLUXSEG6EI8_V_M1_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5166
|
|
{ PseudoVLUXSEG6EI8_V_MF2_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5167
|
|
{ PseudoVLUXSEG6EI8_V_MF2_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5168
|
|
{ PseudoVLUXSEG6EI8_V_MF4_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5169
|
|
{ PseudoVLUXSEG6EI8_V_MF4_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5170
|
|
{ PseudoVLUXSEG6EI8_V_MF8_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5171
|
|
{ PseudoVLUXSEG6EI8_V_MF8_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5172
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF8, VLUXSEG6EI8_V, 0x5, 0x0 }, // 5173
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, VLUXSEG6EI8_V, 0x5, 0x0 }, // 5174
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF4, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5175
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5176
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF4, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5177
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5178
|
|
{ PseudoVLUXSEG6EI8_V_MF2_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5179
|
|
{ PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5180
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5181
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5182
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5183
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5184
|
|
{ PseudoVLUXSEG7EI16_V_M1_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5185
|
|
{ PseudoVLUXSEG7EI16_V_M1_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5186
|
|
{ PseudoVLUXSEG7EI16_V_M2_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5187
|
|
{ PseudoVLUXSEG7EI16_V_M2_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5188
|
|
{ PseudoVLUXSEG7EI16_V_MF2_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5189
|
|
{ PseudoVLUXSEG7EI16_V_MF2_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5190
|
|
{ PseudoVLUXSEG7EI16_V_MF4_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5191
|
|
{ PseudoVLUXSEG7EI16_V_MF4_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5192
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF8, VLUXSEG7EI16_V, 0x5, 0x0 }, // 5193
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, VLUXSEG7EI16_V, 0x5, 0x0 }, // 5194
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF4, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5195
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5196
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF4, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5197
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5198
|
|
{ PseudoVLUXSEG7EI16_V_M1_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5199
|
|
{ PseudoVLUXSEG7EI16_V_M1_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5200
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5201
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5202
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5203
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5204
|
|
{ PseudoVLUXSEG7EI32_V_M1_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5205
|
|
{ PseudoVLUXSEG7EI32_V_M1_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5206
|
|
{ PseudoVLUXSEG7EI32_V_M2_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5207
|
|
{ PseudoVLUXSEG7EI32_V_M2_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5208
|
|
{ PseudoVLUXSEG7EI32_V_M4_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5209
|
|
{ PseudoVLUXSEG7EI32_V_M4_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5210
|
|
{ PseudoVLUXSEG7EI32_V_MF2_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5211
|
|
{ PseudoVLUXSEG7EI32_V_MF2_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5212
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF8, VLUXSEG7EI32_V, 0x5, 0x0 }, // 5213
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, VLUXSEG7EI32_V, 0x5, 0x0 }, // 5214
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF4, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5215
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF4_MASK, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5216
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF4, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5217
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5218
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5219
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5220
|
|
{ PseudoVLUXSEG7EI32_V_M2_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5221
|
|
{ PseudoVLUXSEG7EI32_V_M2_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5222
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5223
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5224
|
|
{ PseudoVLUXSEG7EI64_V_M1_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5225
|
|
{ PseudoVLUXSEG7EI64_V_M1_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5226
|
|
{ PseudoVLUXSEG7EI64_V_M2_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5227
|
|
{ PseudoVLUXSEG7EI64_V_M2_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5228
|
|
{ PseudoVLUXSEG7EI64_V_M4_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5229
|
|
{ PseudoVLUXSEG7EI64_V_M4_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5230
|
|
{ PseudoVLUXSEG7EI64_V_M8_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5231
|
|
{ PseudoVLUXSEG7EI64_V_M8_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5232
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF8, VLUXSEG7EI64_V, 0x5, 0x0 }, // 5233
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF8_MASK, VLUXSEG7EI64_V, 0x5, 0x0 }, // 5234
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF4, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5235
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF4_MASK, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5236
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF4, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5237
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF4_MASK, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5238
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5239
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5240
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5241
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5242
|
|
{ PseudoVLUXSEG7EI64_V_M4_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5243
|
|
{ PseudoVLUXSEG7EI64_V_M4_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5244
|
|
{ PseudoVLUXSEG7EI8_V_M1_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5245
|
|
{ PseudoVLUXSEG7EI8_V_M1_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5246
|
|
{ PseudoVLUXSEG7EI8_V_MF2_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5247
|
|
{ PseudoVLUXSEG7EI8_V_MF2_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5248
|
|
{ PseudoVLUXSEG7EI8_V_MF4_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5249
|
|
{ PseudoVLUXSEG7EI8_V_MF4_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5250
|
|
{ PseudoVLUXSEG7EI8_V_MF8_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5251
|
|
{ PseudoVLUXSEG7EI8_V_MF8_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5252
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF8, VLUXSEG7EI8_V, 0x5, 0x0 }, // 5253
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, VLUXSEG7EI8_V, 0x5, 0x0 }, // 5254
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF4, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5255
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5256
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF4, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5257
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5258
|
|
{ PseudoVLUXSEG7EI8_V_MF2_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5259
|
|
{ PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5260
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5261
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5262
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5263
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5264
|
|
{ PseudoVLUXSEG8EI16_V_M1_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5265
|
|
{ PseudoVLUXSEG8EI16_V_M1_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5266
|
|
{ PseudoVLUXSEG8EI16_V_M2_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5267
|
|
{ PseudoVLUXSEG8EI16_V_M2_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5268
|
|
{ PseudoVLUXSEG8EI16_V_MF2_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5269
|
|
{ PseudoVLUXSEG8EI16_V_MF2_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5270
|
|
{ PseudoVLUXSEG8EI16_V_MF4_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5271
|
|
{ PseudoVLUXSEG8EI16_V_MF4_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5272
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF8, VLUXSEG8EI16_V, 0x5, 0x0 }, // 5273
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, VLUXSEG8EI16_V, 0x5, 0x0 }, // 5274
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF4, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5275
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5276
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF4, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5277
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5278
|
|
{ PseudoVLUXSEG8EI16_V_M1_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5279
|
|
{ PseudoVLUXSEG8EI16_V_M1_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5280
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5281
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5282
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5283
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5284
|
|
{ PseudoVLUXSEG8EI32_V_M1_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5285
|
|
{ PseudoVLUXSEG8EI32_V_M1_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5286
|
|
{ PseudoVLUXSEG8EI32_V_M2_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5287
|
|
{ PseudoVLUXSEG8EI32_V_M2_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5288
|
|
{ PseudoVLUXSEG8EI32_V_M4_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5289
|
|
{ PseudoVLUXSEG8EI32_V_M4_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5290
|
|
{ PseudoVLUXSEG8EI32_V_MF2_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5291
|
|
{ PseudoVLUXSEG8EI32_V_MF2_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5292
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF8, VLUXSEG8EI32_V, 0x5, 0x0 }, // 5293
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, VLUXSEG8EI32_V, 0x5, 0x0 }, // 5294
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF4, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5295
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF4_MASK, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5296
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF4, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5297
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5298
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5299
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5300
|
|
{ PseudoVLUXSEG8EI32_V_M2_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5301
|
|
{ PseudoVLUXSEG8EI32_V_M2_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5302
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5303
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5304
|
|
{ PseudoVLUXSEG8EI64_V_M1_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5305
|
|
{ PseudoVLUXSEG8EI64_V_M1_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5306
|
|
{ PseudoVLUXSEG8EI64_V_M2_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5307
|
|
{ PseudoVLUXSEG8EI64_V_M2_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5308
|
|
{ PseudoVLUXSEG8EI64_V_M4_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5309
|
|
{ PseudoVLUXSEG8EI64_V_M4_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5310
|
|
{ PseudoVLUXSEG8EI64_V_M8_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5311
|
|
{ PseudoVLUXSEG8EI64_V_M8_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5312
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF8, VLUXSEG8EI64_V, 0x5, 0x0 }, // 5313
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF8_MASK, VLUXSEG8EI64_V, 0x5, 0x0 }, // 5314
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF4, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5315
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF4_MASK, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5316
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF4, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5317
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF4_MASK, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5318
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5319
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5320
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5321
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5322
|
|
{ PseudoVLUXSEG8EI64_V_M4_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5323
|
|
{ PseudoVLUXSEG8EI64_V_M4_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5324
|
|
{ PseudoVLUXSEG8EI8_V_M1_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5325
|
|
{ PseudoVLUXSEG8EI8_V_M1_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5326
|
|
{ PseudoVLUXSEG8EI8_V_MF2_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5327
|
|
{ PseudoVLUXSEG8EI8_V_MF2_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5328
|
|
{ PseudoVLUXSEG8EI8_V_MF4_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5329
|
|
{ PseudoVLUXSEG8EI8_V_MF4_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5330
|
|
{ PseudoVLUXSEG8EI8_V_MF8_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5331
|
|
{ PseudoVLUXSEG8EI8_V_MF8_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5332
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF8, VLUXSEG8EI8_V, 0x5, 0x0 }, // 5333
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, VLUXSEG8EI8_V, 0x5, 0x0 }, // 5334
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF4, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5335
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5336
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF4, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5337
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5338
|
|
{ PseudoVLUXSEG8EI8_V_MF2_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5339
|
|
{ PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5340
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5341
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5342
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5343
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5344
|
|
{ PseudoVMACC_VV_M1, VMACC_VV, 0x0, 0x0 }, // 5345
|
|
{ PseudoVMACC_VV_M1_MASK, VMACC_VV, 0x0, 0x0 }, // 5346
|
|
{ PseudoVMACC_VV_M2, VMACC_VV, 0x1, 0x0 }, // 5347
|
|
{ PseudoVMACC_VV_M2_MASK, VMACC_VV, 0x1, 0x0 }, // 5348
|
|
{ PseudoVMACC_VV_M4, VMACC_VV, 0x2, 0x0 }, // 5349
|
|
{ PseudoVMACC_VV_M4_MASK, VMACC_VV, 0x2, 0x0 }, // 5350
|
|
{ PseudoVMACC_VV_M8, VMACC_VV, 0x3, 0x0 }, // 5351
|
|
{ PseudoVMACC_VV_M8_MASK, VMACC_VV, 0x3, 0x0 }, // 5352
|
|
{ PseudoVMACC_VV_MF8, VMACC_VV, 0x5, 0x0 }, // 5353
|
|
{ PseudoVMACC_VV_MF8_MASK, VMACC_VV, 0x5, 0x0 }, // 5354
|
|
{ PseudoVMACC_VV_MF4, VMACC_VV, 0x6, 0x0 }, // 5355
|
|
{ PseudoVMACC_VV_MF4_MASK, VMACC_VV, 0x6, 0x0 }, // 5356
|
|
{ PseudoVMACC_VV_MF2, VMACC_VV, 0x7, 0x0 }, // 5357
|
|
{ PseudoVMACC_VV_MF2_MASK, VMACC_VV, 0x7, 0x0 }, // 5358
|
|
{ PseudoVMACC_VX_M1, VMACC_VX, 0x0, 0x0 }, // 5359
|
|
{ PseudoVMACC_VX_M1_MASK, VMACC_VX, 0x0, 0x0 }, // 5360
|
|
{ PseudoVMACC_VX_M2, VMACC_VX, 0x1, 0x0 }, // 5361
|
|
{ PseudoVMACC_VX_M2_MASK, VMACC_VX, 0x1, 0x0 }, // 5362
|
|
{ PseudoVMACC_VX_M4, VMACC_VX, 0x2, 0x0 }, // 5363
|
|
{ PseudoVMACC_VX_M4_MASK, VMACC_VX, 0x2, 0x0 }, // 5364
|
|
{ PseudoVMACC_VX_M8, VMACC_VX, 0x3, 0x0 }, // 5365
|
|
{ PseudoVMACC_VX_M8_MASK, VMACC_VX, 0x3, 0x0 }, // 5366
|
|
{ PseudoVMACC_VX_MF8, VMACC_VX, 0x5, 0x0 }, // 5367
|
|
{ PseudoVMACC_VX_MF8_MASK, VMACC_VX, 0x5, 0x0 }, // 5368
|
|
{ PseudoVMACC_VX_MF4, VMACC_VX, 0x6, 0x0 }, // 5369
|
|
{ PseudoVMACC_VX_MF4_MASK, VMACC_VX, 0x6, 0x0 }, // 5370
|
|
{ PseudoVMACC_VX_MF2, VMACC_VX, 0x7, 0x0 }, // 5371
|
|
{ PseudoVMACC_VX_MF2_MASK, VMACC_VX, 0x7, 0x0 }, // 5372
|
|
{ PseudoVMADC_VI_M1, VMADC_VI, 0x0, 0x0 }, // 5373
|
|
{ PseudoVMADC_VI_M2, VMADC_VI, 0x1, 0x0 }, // 5374
|
|
{ PseudoVMADC_VI_M4, VMADC_VI, 0x2, 0x0 }, // 5375
|
|
{ PseudoVMADC_VI_M8, VMADC_VI, 0x3, 0x0 }, // 5376
|
|
{ PseudoVMADC_VI_MF8, VMADC_VI, 0x5, 0x0 }, // 5377
|
|
{ PseudoVMADC_VI_MF4, VMADC_VI, 0x6, 0x0 }, // 5378
|
|
{ PseudoVMADC_VI_MF2, VMADC_VI, 0x7, 0x0 }, // 5379
|
|
{ PseudoVMADC_VIM_M1, VMADC_VIM, 0x0, 0x0 }, // 5380
|
|
{ PseudoVMADC_VIM_M2, VMADC_VIM, 0x1, 0x0 }, // 5381
|
|
{ PseudoVMADC_VIM_M4, VMADC_VIM, 0x2, 0x0 }, // 5382
|
|
{ PseudoVMADC_VIM_M8, VMADC_VIM, 0x3, 0x0 }, // 5383
|
|
{ PseudoVMADC_VIM_MF8, VMADC_VIM, 0x5, 0x0 }, // 5384
|
|
{ PseudoVMADC_VIM_MF4, VMADC_VIM, 0x6, 0x0 }, // 5385
|
|
{ PseudoVMADC_VIM_MF2, VMADC_VIM, 0x7, 0x0 }, // 5386
|
|
{ PseudoVMADC_VV_M1, VMADC_VV, 0x0, 0x0 }, // 5387
|
|
{ PseudoVMADC_VV_M2, VMADC_VV, 0x1, 0x0 }, // 5388
|
|
{ PseudoVMADC_VV_M4, VMADC_VV, 0x2, 0x0 }, // 5389
|
|
{ PseudoVMADC_VV_M8, VMADC_VV, 0x3, 0x0 }, // 5390
|
|
{ PseudoVMADC_VV_MF8, VMADC_VV, 0x5, 0x0 }, // 5391
|
|
{ PseudoVMADC_VV_MF4, VMADC_VV, 0x6, 0x0 }, // 5392
|
|
{ PseudoVMADC_VV_MF2, VMADC_VV, 0x7, 0x0 }, // 5393
|
|
{ PseudoVMADC_VVM_M1, VMADC_VVM, 0x0, 0x0 }, // 5394
|
|
{ PseudoVMADC_VVM_M2, VMADC_VVM, 0x1, 0x0 }, // 5395
|
|
{ PseudoVMADC_VVM_M4, VMADC_VVM, 0x2, 0x0 }, // 5396
|
|
{ PseudoVMADC_VVM_M8, VMADC_VVM, 0x3, 0x0 }, // 5397
|
|
{ PseudoVMADC_VVM_MF8, VMADC_VVM, 0x5, 0x0 }, // 5398
|
|
{ PseudoVMADC_VVM_MF4, VMADC_VVM, 0x6, 0x0 }, // 5399
|
|
{ PseudoVMADC_VVM_MF2, VMADC_VVM, 0x7, 0x0 }, // 5400
|
|
{ PseudoVMADC_VX_M1, VMADC_VX, 0x0, 0x0 }, // 5401
|
|
{ PseudoVMADC_VX_M2, VMADC_VX, 0x1, 0x0 }, // 5402
|
|
{ PseudoVMADC_VX_M4, VMADC_VX, 0x2, 0x0 }, // 5403
|
|
{ PseudoVMADC_VX_M8, VMADC_VX, 0x3, 0x0 }, // 5404
|
|
{ PseudoVMADC_VX_MF8, VMADC_VX, 0x5, 0x0 }, // 5405
|
|
{ PseudoVMADC_VX_MF4, VMADC_VX, 0x6, 0x0 }, // 5406
|
|
{ PseudoVMADC_VX_MF2, VMADC_VX, 0x7, 0x0 }, // 5407
|
|
{ PseudoVMADC_VXM_M1, VMADC_VXM, 0x0, 0x0 }, // 5408
|
|
{ PseudoVMADC_VXM_M2, VMADC_VXM, 0x1, 0x0 }, // 5409
|
|
{ PseudoVMADC_VXM_M4, VMADC_VXM, 0x2, 0x0 }, // 5410
|
|
{ PseudoVMADC_VXM_M8, VMADC_VXM, 0x3, 0x0 }, // 5411
|
|
{ PseudoVMADC_VXM_MF8, VMADC_VXM, 0x5, 0x0 }, // 5412
|
|
{ PseudoVMADC_VXM_MF4, VMADC_VXM, 0x6, 0x0 }, // 5413
|
|
{ PseudoVMADC_VXM_MF2, VMADC_VXM, 0x7, 0x0 }, // 5414
|
|
{ PseudoVMADD_VV_M1, VMADD_VV, 0x0, 0x0 }, // 5415
|
|
{ PseudoVMADD_VV_M1_MASK, VMADD_VV, 0x0, 0x0 }, // 5416
|
|
{ PseudoVMADD_VV_M2, VMADD_VV, 0x1, 0x0 }, // 5417
|
|
{ PseudoVMADD_VV_M2_MASK, VMADD_VV, 0x1, 0x0 }, // 5418
|
|
{ PseudoVMADD_VV_M4, VMADD_VV, 0x2, 0x0 }, // 5419
|
|
{ PseudoVMADD_VV_M4_MASK, VMADD_VV, 0x2, 0x0 }, // 5420
|
|
{ PseudoVMADD_VV_M8, VMADD_VV, 0x3, 0x0 }, // 5421
|
|
{ PseudoVMADD_VV_M8_MASK, VMADD_VV, 0x3, 0x0 }, // 5422
|
|
{ PseudoVMADD_VV_MF8, VMADD_VV, 0x5, 0x0 }, // 5423
|
|
{ PseudoVMADD_VV_MF8_MASK, VMADD_VV, 0x5, 0x0 }, // 5424
|
|
{ PseudoVMADD_VV_MF4, VMADD_VV, 0x6, 0x0 }, // 5425
|
|
{ PseudoVMADD_VV_MF4_MASK, VMADD_VV, 0x6, 0x0 }, // 5426
|
|
{ PseudoVMADD_VV_MF2, VMADD_VV, 0x7, 0x0 }, // 5427
|
|
{ PseudoVMADD_VV_MF2_MASK, VMADD_VV, 0x7, 0x0 }, // 5428
|
|
{ PseudoVMADD_VX_M1, VMADD_VX, 0x0, 0x0 }, // 5429
|
|
{ PseudoVMADD_VX_M1_MASK, VMADD_VX, 0x0, 0x0 }, // 5430
|
|
{ PseudoVMADD_VX_M2, VMADD_VX, 0x1, 0x0 }, // 5431
|
|
{ PseudoVMADD_VX_M2_MASK, VMADD_VX, 0x1, 0x0 }, // 5432
|
|
{ PseudoVMADD_VX_M4, VMADD_VX, 0x2, 0x0 }, // 5433
|
|
{ PseudoVMADD_VX_M4_MASK, VMADD_VX, 0x2, 0x0 }, // 5434
|
|
{ PseudoVMADD_VX_M8, VMADD_VX, 0x3, 0x0 }, // 5435
|
|
{ PseudoVMADD_VX_M8_MASK, VMADD_VX, 0x3, 0x0 }, // 5436
|
|
{ PseudoVMADD_VX_MF8, VMADD_VX, 0x5, 0x0 }, // 5437
|
|
{ PseudoVMADD_VX_MF8_MASK, VMADD_VX, 0x5, 0x0 }, // 5438
|
|
{ PseudoVMADD_VX_MF4, VMADD_VX, 0x6, 0x0 }, // 5439
|
|
{ PseudoVMADD_VX_MF4_MASK, VMADD_VX, 0x6, 0x0 }, // 5440
|
|
{ PseudoVMADD_VX_MF2, VMADD_VX, 0x7, 0x0 }, // 5441
|
|
{ PseudoVMADD_VX_MF2_MASK, VMADD_VX, 0x7, 0x0 }, // 5442
|
|
{ PseudoVMANDN_MM_M1, VMANDN_MM, 0x0, 0x0 }, // 5443
|
|
{ PseudoVMANDN_MM_M2, VMANDN_MM, 0x1, 0x0 }, // 5444
|
|
{ PseudoVMANDN_MM_M4, VMANDN_MM, 0x2, 0x0 }, // 5445
|
|
{ PseudoVMANDN_MM_M8, VMANDN_MM, 0x3, 0x0 }, // 5446
|
|
{ PseudoVMANDN_MM_MF8, VMANDN_MM, 0x5, 0x0 }, // 5447
|
|
{ PseudoVMANDN_MM_MF4, VMANDN_MM, 0x6, 0x0 }, // 5448
|
|
{ PseudoVMANDN_MM_MF2, VMANDN_MM, 0x7, 0x0 }, // 5449
|
|
{ PseudoVMAND_MM_M1, VMAND_MM, 0x0, 0x0 }, // 5450
|
|
{ PseudoVMAND_MM_M2, VMAND_MM, 0x1, 0x0 }, // 5451
|
|
{ PseudoVMAND_MM_M4, VMAND_MM, 0x2, 0x0 }, // 5452
|
|
{ PseudoVMAND_MM_M8, VMAND_MM, 0x3, 0x0 }, // 5453
|
|
{ PseudoVMAND_MM_MF8, VMAND_MM, 0x5, 0x0 }, // 5454
|
|
{ PseudoVMAND_MM_MF4, VMAND_MM, 0x6, 0x0 }, // 5455
|
|
{ PseudoVMAND_MM_MF2, VMAND_MM, 0x7, 0x0 }, // 5456
|
|
{ PseudoVMAXU_VV_M1, VMAXU_VV, 0x0, 0x0 }, // 5457
|
|
{ PseudoVMAXU_VV_M1_MASK, VMAXU_VV, 0x0, 0x0 }, // 5458
|
|
{ PseudoVMAXU_VV_M2, VMAXU_VV, 0x1, 0x0 }, // 5459
|
|
{ PseudoVMAXU_VV_M2_MASK, VMAXU_VV, 0x1, 0x0 }, // 5460
|
|
{ PseudoVMAXU_VV_M4, VMAXU_VV, 0x2, 0x0 }, // 5461
|
|
{ PseudoVMAXU_VV_M4_MASK, VMAXU_VV, 0x2, 0x0 }, // 5462
|
|
{ PseudoVMAXU_VV_M8, VMAXU_VV, 0x3, 0x0 }, // 5463
|
|
{ PseudoVMAXU_VV_M8_MASK, VMAXU_VV, 0x3, 0x0 }, // 5464
|
|
{ PseudoVMAXU_VV_MF8, VMAXU_VV, 0x5, 0x0 }, // 5465
|
|
{ PseudoVMAXU_VV_MF8_MASK, VMAXU_VV, 0x5, 0x0 }, // 5466
|
|
{ PseudoVMAXU_VV_MF4, VMAXU_VV, 0x6, 0x0 }, // 5467
|
|
{ PseudoVMAXU_VV_MF4_MASK, VMAXU_VV, 0x6, 0x0 }, // 5468
|
|
{ PseudoVMAXU_VV_MF2, VMAXU_VV, 0x7, 0x0 }, // 5469
|
|
{ PseudoVMAXU_VV_MF2_MASK, VMAXU_VV, 0x7, 0x0 }, // 5470
|
|
{ PseudoVMAXU_VX_M1, VMAXU_VX, 0x0, 0x0 }, // 5471
|
|
{ PseudoVMAXU_VX_M1_MASK, VMAXU_VX, 0x0, 0x0 }, // 5472
|
|
{ PseudoVMAXU_VX_M2, VMAXU_VX, 0x1, 0x0 }, // 5473
|
|
{ PseudoVMAXU_VX_M2_MASK, VMAXU_VX, 0x1, 0x0 }, // 5474
|
|
{ PseudoVMAXU_VX_M4, VMAXU_VX, 0x2, 0x0 }, // 5475
|
|
{ PseudoVMAXU_VX_M4_MASK, VMAXU_VX, 0x2, 0x0 }, // 5476
|
|
{ PseudoVMAXU_VX_M8, VMAXU_VX, 0x3, 0x0 }, // 5477
|
|
{ PseudoVMAXU_VX_M8_MASK, VMAXU_VX, 0x3, 0x0 }, // 5478
|
|
{ PseudoVMAXU_VX_MF8, VMAXU_VX, 0x5, 0x0 }, // 5479
|
|
{ PseudoVMAXU_VX_MF8_MASK, VMAXU_VX, 0x5, 0x0 }, // 5480
|
|
{ PseudoVMAXU_VX_MF4, VMAXU_VX, 0x6, 0x0 }, // 5481
|
|
{ PseudoVMAXU_VX_MF4_MASK, VMAXU_VX, 0x6, 0x0 }, // 5482
|
|
{ PseudoVMAXU_VX_MF2, VMAXU_VX, 0x7, 0x0 }, // 5483
|
|
{ PseudoVMAXU_VX_MF2_MASK, VMAXU_VX, 0x7, 0x0 }, // 5484
|
|
{ PseudoVMAX_VV_M1, VMAX_VV, 0x0, 0x0 }, // 5485
|
|
{ PseudoVMAX_VV_M1_MASK, VMAX_VV, 0x0, 0x0 }, // 5486
|
|
{ PseudoVMAX_VV_M2, VMAX_VV, 0x1, 0x0 }, // 5487
|
|
{ PseudoVMAX_VV_M2_MASK, VMAX_VV, 0x1, 0x0 }, // 5488
|
|
{ PseudoVMAX_VV_M4, VMAX_VV, 0x2, 0x0 }, // 5489
|
|
{ PseudoVMAX_VV_M4_MASK, VMAX_VV, 0x2, 0x0 }, // 5490
|
|
{ PseudoVMAX_VV_M8, VMAX_VV, 0x3, 0x0 }, // 5491
|
|
{ PseudoVMAX_VV_M8_MASK, VMAX_VV, 0x3, 0x0 }, // 5492
|
|
{ PseudoVMAX_VV_MF8, VMAX_VV, 0x5, 0x0 }, // 5493
|
|
{ PseudoVMAX_VV_MF8_MASK, VMAX_VV, 0x5, 0x0 }, // 5494
|
|
{ PseudoVMAX_VV_MF4, VMAX_VV, 0x6, 0x0 }, // 5495
|
|
{ PseudoVMAX_VV_MF4_MASK, VMAX_VV, 0x6, 0x0 }, // 5496
|
|
{ PseudoVMAX_VV_MF2, VMAX_VV, 0x7, 0x0 }, // 5497
|
|
{ PseudoVMAX_VV_MF2_MASK, VMAX_VV, 0x7, 0x0 }, // 5498
|
|
{ PseudoVMAX_VX_M1, VMAX_VX, 0x0, 0x0 }, // 5499
|
|
{ PseudoVMAX_VX_M1_MASK, VMAX_VX, 0x0, 0x0 }, // 5500
|
|
{ PseudoVMAX_VX_M2, VMAX_VX, 0x1, 0x0 }, // 5501
|
|
{ PseudoVMAX_VX_M2_MASK, VMAX_VX, 0x1, 0x0 }, // 5502
|
|
{ PseudoVMAX_VX_M4, VMAX_VX, 0x2, 0x0 }, // 5503
|
|
{ PseudoVMAX_VX_M4_MASK, VMAX_VX, 0x2, 0x0 }, // 5504
|
|
{ PseudoVMAX_VX_M8, VMAX_VX, 0x3, 0x0 }, // 5505
|
|
{ PseudoVMAX_VX_M8_MASK, VMAX_VX, 0x3, 0x0 }, // 5506
|
|
{ PseudoVMAX_VX_MF8, VMAX_VX, 0x5, 0x0 }, // 5507
|
|
{ PseudoVMAX_VX_MF8_MASK, VMAX_VX, 0x5, 0x0 }, // 5508
|
|
{ PseudoVMAX_VX_MF4, VMAX_VX, 0x6, 0x0 }, // 5509
|
|
{ PseudoVMAX_VX_MF4_MASK, VMAX_VX, 0x6, 0x0 }, // 5510
|
|
{ PseudoVMAX_VX_MF2, VMAX_VX, 0x7, 0x0 }, // 5511
|
|
{ PseudoVMAX_VX_MF2_MASK, VMAX_VX, 0x7, 0x0 }, // 5512
|
|
{ PseudoVMERGE_VIM_M1, VMERGE_VIM, 0x0, 0x0 }, // 5513
|
|
{ PseudoVMERGE_VIM_M2, VMERGE_VIM, 0x1, 0x0 }, // 5514
|
|
{ PseudoVMERGE_VIM_M4, VMERGE_VIM, 0x2, 0x0 }, // 5515
|
|
{ PseudoVMERGE_VIM_M8, VMERGE_VIM, 0x3, 0x0 }, // 5516
|
|
{ PseudoVMERGE_VIM_MF8, VMERGE_VIM, 0x5, 0x0 }, // 5517
|
|
{ PseudoVMERGE_VIM_MF4, VMERGE_VIM, 0x6, 0x0 }, // 5518
|
|
{ PseudoVMERGE_VIM_MF2, VMERGE_VIM, 0x7, 0x0 }, // 5519
|
|
{ PseudoVMERGE_VVM_M1, VMERGE_VVM, 0x0, 0x0 }, // 5520
|
|
{ PseudoVMERGE_VVM_M2, VMERGE_VVM, 0x1, 0x0 }, // 5521
|
|
{ PseudoVMERGE_VVM_M4, VMERGE_VVM, 0x2, 0x0 }, // 5522
|
|
{ PseudoVMERGE_VVM_M8, VMERGE_VVM, 0x3, 0x0 }, // 5523
|
|
{ PseudoVMERGE_VVM_MF8, VMERGE_VVM, 0x5, 0x0 }, // 5524
|
|
{ PseudoVMERGE_VVM_MF4, VMERGE_VVM, 0x6, 0x0 }, // 5525
|
|
{ PseudoVMERGE_VVM_MF2, VMERGE_VVM, 0x7, 0x0 }, // 5526
|
|
{ PseudoVMERGE_VXM_M1, VMERGE_VXM, 0x0, 0x0 }, // 5527
|
|
{ PseudoVMERGE_VXM_M2, VMERGE_VXM, 0x1, 0x0 }, // 5528
|
|
{ PseudoVMERGE_VXM_M4, VMERGE_VXM, 0x2, 0x0 }, // 5529
|
|
{ PseudoVMERGE_VXM_M8, VMERGE_VXM, 0x3, 0x0 }, // 5530
|
|
{ PseudoVMERGE_VXM_MF8, VMERGE_VXM, 0x5, 0x0 }, // 5531
|
|
{ PseudoVMERGE_VXM_MF4, VMERGE_VXM, 0x6, 0x0 }, // 5532
|
|
{ PseudoVMERGE_VXM_MF2, VMERGE_VXM, 0x7, 0x0 }, // 5533
|
|
{ PseudoVMFEQ_VFPR16_M1, VMFEQ_VF, 0x0, 0x0 }, // 5534
|
|
{ PseudoVMFEQ_VFPR16_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 5535
|
|
{ PseudoVMFEQ_VFPR32_M1, VMFEQ_VF, 0x0, 0x0 }, // 5536
|
|
{ PseudoVMFEQ_VFPR32_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 5537
|
|
{ PseudoVMFEQ_VFPR64_M1, VMFEQ_VF, 0x0, 0x0 }, // 5538
|
|
{ PseudoVMFEQ_VFPR64_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 5539
|
|
{ PseudoVMFEQ_VFPR16_M2, VMFEQ_VF, 0x1, 0x0 }, // 5540
|
|
{ PseudoVMFEQ_VFPR16_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 5541
|
|
{ PseudoVMFEQ_VFPR32_M2, VMFEQ_VF, 0x1, 0x0 }, // 5542
|
|
{ PseudoVMFEQ_VFPR32_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 5543
|
|
{ PseudoVMFEQ_VFPR64_M2, VMFEQ_VF, 0x1, 0x0 }, // 5544
|
|
{ PseudoVMFEQ_VFPR64_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 5545
|
|
{ PseudoVMFEQ_VFPR16_M4, VMFEQ_VF, 0x2, 0x0 }, // 5546
|
|
{ PseudoVMFEQ_VFPR16_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 5547
|
|
{ PseudoVMFEQ_VFPR32_M4, VMFEQ_VF, 0x2, 0x0 }, // 5548
|
|
{ PseudoVMFEQ_VFPR32_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 5549
|
|
{ PseudoVMFEQ_VFPR64_M4, VMFEQ_VF, 0x2, 0x0 }, // 5550
|
|
{ PseudoVMFEQ_VFPR64_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 5551
|
|
{ PseudoVMFEQ_VFPR16_M8, VMFEQ_VF, 0x3, 0x0 }, // 5552
|
|
{ PseudoVMFEQ_VFPR16_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 5553
|
|
{ PseudoVMFEQ_VFPR32_M8, VMFEQ_VF, 0x3, 0x0 }, // 5554
|
|
{ PseudoVMFEQ_VFPR32_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 5555
|
|
{ PseudoVMFEQ_VFPR64_M8, VMFEQ_VF, 0x3, 0x0 }, // 5556
|
|
{ PseudoVMFEQ_VFPR64_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 5557
|
|
{ PseudoVMFEQ_VFPR16_MF4, VMFEQ_VF, 0x6, 0x0 }, // 5558
|
|
{ PseudoVMFEQ_VFPR16_MF4_MASK, VMFEQ_VF, 0x6, 0x0 }, // 5559
|
|
{ PseudoVMFEQ_VFPR16_MF2, VMFEQ_VF, 0x7, 0x0 }, // 5560
|
|
{ PseudoVMFEQ_VFPR16_MF2_MASK, VMFEQ_VF, 0x7, 0x0 }, // 5561
|
|
{ PseudoVMFEQ_VFPR32_MF2, VMFEQ_VF, 0x7, 0x0 }, // 5562
|
|
{ PseudoVMFEQ_VFPR32_MF2_MASK, VMFEQ_VF, 0x7, 0x0 }, // 5563
|
|
{ PseudoVMFEQ_VV_M1, VMFEQ_VV, 0x0, 0x0 }, // 5564
|
|
{ PseudoVMFEQ_VV_M1_MASK, VMFEQ_VV, 0x0, 0x0 }, // 5565
|
|
{ PseudoVMFEQ_VV_M2, VMFEQ_VV, 0x1, 0x0 }, // 5566
|
|
{ PseudoVMFEQ_VV_M2_MASK, VMFEQ_VV, 0x1, 0x0 }, // 5567
|
|
{ PseudoVMFEQ_VV_M4, VMFEQ_VV, 0x2, 0x0 }, // 5568
|
|
{ PseudoVMFEQ_VV_M4_MASK, VMFEQ_VV, 0x2, 0x0 }, // 5569
|
|
{ PseudoVMFEQ_VV_M8, VMFEQ_VV, 0x3, 0x0 }, // 5570
|
|
{ PseudoVMFEQ_VV_M8_MASK, VMFEQ_VV, 0x3, 0x0 }, // 5571
|
|
{ PseudoVMFEQ_VV_MF4, VMFEQ_VV, 0x6, 0x0 }, // 5572
|
|
{ PseudoVMFEQ_VV_MF4_MASK, VMFEQ_VV, 0x6, 0x0 }, // 5573
|
|
{ PseudoVMFEQ_VV_MF2, VMFEQ_VV, 0x7, 0x0 }, // 5574
|
|
{ PseudoVMFEQ_VV_MF2_MASK, VMFEQ_VV, 0x7, 0x0 }, // 5575
|
|
{ PseudoVMFGE_VFPR16_M1, VMFGE_VF, 0x0, 0x0 }, // 5576
|
|
{ PseudoVMFGE_VFPR16_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 5577
|
|
{ PseudoVMFGE_VFPR32_M1, VMFGE_VF, 0x0, 0x0 }, // 5578
|
|
{ PseudoVMFGE_VFPR32_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 5579
|
|
{ PseudoVMFGE_VFPR64_M1, VMFGE_VF, 0x0, 0x0 }, // 5580
|
|
{ PseudoVMFGE_VFPR64_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 5581
|
|
{ PseudoVMFGE_VFPR16_M2, VMFGE_VF, 0x1, 0x0 }, // 5582
|
|
{ PseudoVMFGE_VFPR16_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 5583
|
|
{ PseudoVMFGE_VFPR32_M2, VMFGE_VF, 0x1, 0x0 }, // 5584
|
|
{ PseudoVMFGE_VFPR32_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 5585
|
|
{ PseudoVMFGE_VFPR64_M2, VMFGE_VF, 0x1, 0x0 }, // 5586
|
|
{ PseudoVMFGE_VFPR64_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 5587
|
|
{ PseudoVMFGE_VFPR16_M4, VMFGE_VF, 0x2, 0x0 }, // 5588
|
|
{ PseudoVMFGE_VFPR16_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 5589
|
|
{ PseudoVMFGE_VFPR32_M4, VMFGE_VF, 0x2, 0x0 }, // 5590
|
|
{ PseudoVMFGE_VFPR32_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 5591
|
|
{ PseudoVMFGE_VFPR64_M4, VMFGE_VF, 0x2, 0x0 }, // 5592
|
|
{ PseudoVMFGE_VFPR64_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 5593
|
|
{ PseudoVMFGE_VFPR16_M8, VMFGE_VF, 0x3, 0x0 }, // 5594
|
|
{ PseudoVMFGE_VFPR16_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 5595
|
|
{ PseudoVMFGE_VFPR32_M8, VMFGE_VF, 0x3, 0x0 }, // 5596
|
|
{ PseudoVMFGE_VFPR32_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 5597
|
|
{ PseudoVMFGE_VFPR64_M8, VMFGE_VF, 0x3, 0x0 }, // 5598
|
|
{ PseudoVMFGE_VFPR64_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 5599
|
|
{ PseudoVMFGE_VFPR16_MF4, VMFGE_VF, 0x6, 0x0 }, // 5600
|
|
{ PseudoVMFGE_VFPR16_MF4_MASK, VMFGE_VF, 0x6, 0x0 }, // 5601
|
|
{ PseudoVMFGE_VFPR16_MF2, VMFGE_VF, 0x7, 0x0 }, // 5602
|
|
{ PseudoVMFGE_VFPR16_MF2_MASK, VMFGE_VF, 0x7, 0x0 }, // 5603
|
|
{ PseudoVMFGE_VFPR32_MF2, VMFGE_VF, 0x7, 0x0 }, // 5604
|
|
{ PseudoVMFGE_VFPR32_MF2_MASK, VMFGE_VF, 0x7, 0x0 }, // 5605
|
|
{ PseudoVMFGT_VFPR16_M1, VMFGT_VF, 0x0, 0x0 }, // 5606
|
|
{ PseudoVMFGT_VFPR16_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 5607
|
|
{ PseudoVMFGT_VFPR32_M1, VMFGT_VF, 0x0, 0x0 }, // 5608
|
|
{ PseudoVMFGT_VFPR32_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 5609
|
|
{ PseudoVMFGT_VFPR64_M1, VMFGT_VF, 0x0, 0x0 }, // 5610
|
|
{ PseudoVMFGT_VFPR64_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 5611
|
|
{ PseudoVMFGT_VFPR16_M2, VMFGT_VF, 0x1, 0x0 }, // 5612
|
|
{ PseudoVMFGT_VFPR16_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 5613
|
|
{ PseudoVMFGT_VFPR32_M2, VMFGT_VF, 0x1, 0x0 }, // 5614
|
|
{ PseudoVMFGT_VFPR32_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 5615
|
|
{ PseudoVMFGT_VFPR64_M2, VMFGT_VF, 0x1, 0x0 }, // 5616
|
|
{ PseudoVMFGT_VFPR64_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 5617
|
|
{ PseudoVMFGT_VFPR16_M4, VMFGT_VF, 0x2, 0x0 }, // 5618
|
|
{ PseudoVMFGT_VFPR16_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 5619
|
|
{ PseudoVMFGT_VFPR32_M4, VMFGT_VF, 0x2, 0x0 }, // 5620
|
|
{ PseudoVMFGT_VFPR32_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 5621
|
|
{ PseudoVMFGT_VFPR64_M4, VMFGT_VF, 0x2, 0x0 }, // 5622
|
|
{ PseudoVMFGT_VFPR64_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 5623
|
|
{ PseudoVMFGT_VFPR16_M8, VMFGT_VF, 0x3, 0x0 }, // 5624
|
|
{ PseudoVMFGT_VFPR16_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 5625
|
|
{ PseudoVMFGT_VFPR32_M8, VMFGT_VF, 0x3, 0x0 }, // 5626
|
|
{ PseudoVMFGT_VFPR32_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 5627
|
|
{ PseudoVMFGT_VFPR64_M8, VMFGT_VF, 0x3, 0x0 }, // 5628
|
|
{ PseudoVMFGT_VFPR64_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 5629
|
|
{ PseudoVMFGT_VFPR16_MF4, VMFGT_VF, 0x6, 0x0 }, // 5630
|
|
{ PseudoVMFGT_VFPR16_MF4_MASK, VMFGT_VF, 0x6, 0x0 }, // 5631
|
|
{ PseudoVMFGT_VFPR16_MF2, VMFGT_VF, 0x7, 0x0 }, // 5632
|
|
{ PseudoVMFGT_VFPR16_MF2_MASK, VMFGT_VF, 0x7, 0x0 }, // 5633
|
|
{ PseudoVMFGT_VFPR32_MF2, VMFGT_VF, 0x7, 0x0 }, // 5634
|
|
{ PseudoVMFGT_VFPR32_MF2_MASK, VMFGT_VF, 0x7, 0x0 }, // 5635
|
|
{ PseudoVMFLE_VFPR16_M1, VMFLE_VF, 0x0, 0x0 }, // 5636
|
|
{ PseudoVMFLE_VFPR16_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 5637
|
|
{ PseudoVMFLE_VFPR32_M1, VMFLE_VF, 0x0, 0x0 }, // 5638
|
|
{ PseudoVMFLE_VFPR32_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 5639
|
|
{ PseudoVMFLE_VFPR64_M1, VMFLE_VF, 0x0, 0x0 }, // 5640
|
|
{ PseudoVMFLE_VFPR64_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 5641
|
|
{ PseudoVMFLE_VFPR16_M2, VMFLE_VF, 0x1, 0x0 }, // 5642
|
|
{ PseudoVMFLE_VFPR16_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 5643
|
|
{ PseudoVMFLE_VFPR32_M2, VMFLE_VF, 0x1, 0x0 }, // 5644
|
|
{ PseudoVMFLE_VFPR32_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 5645
|
|
{ PseudoVMFLE_VFPR64_M2, VMFLE_VF, 0x1, 0x0 }, // 5646
|
|
{ PseudoVMFLE_VFPR64_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 5647
|
|
{ PseudoVMFLE_VFPR16_M4, VMFLE_VF, 0x2, 0x0 }, // 5648
|
|
{ PseudoVMFLE_VFPR16_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 5649
|
|
{ PseudoVMFLE_VFPR32_M4, VMFLE_VF, 0x2, 0x0 }, // 5650
|
|
{ PseudoVMFLE_VFPR32_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 5651
|
|
{ PseudoVMFLE_VFPR64_M4, VMFLE_VF, 0x2, 0x0 }, // 5652
|
|
{ PseudoVMFLE_VFPR64_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 5653
|
|
{ PseudoVMFLE_VFPR16_M8, VMFLE_VF, 0x3, 0x0 }, // 5654
|
|
{ PseudoVMFLE_VFPR16_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 5655
|
|
{ PseudoVMFLE_VFPR32_M8, VMFLE_VF, 0x3, 0x0 }, // 5656
|
|
{ PseudoVMFLE_VFPR32_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 5657
|
|
{ PseudoVMFLE_VFPR64_M8, VMFLE_VF, 0x3, 0x0 }, // 5658
|
|
{ PseudoVMFLE_VFPR64_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 5659
|
|
{ PseudoVMFLE_VFPR16_MF4, VMFLE_VF, 0x6, 0x0 }, // 5660
|
|
{ PseudoVMFLE_VFPR16_MF4_MASK, VMFLE_VF, 0x6, 0x0 }, // 5661
|
|
{ PseudoVMFLE_VFPR16_MF2, VMFLE_VF, 0x7, 0x0 }, // 5662
|
|
{ PseudoVMFLE_VFPR16_MF2_MASK, VMFLE_VF, 0x7, 0x0 }, // 5663
|
|
{ PseudoVMFLE_VFPR32_MF2, VMFLE_VF, 0x7, 0x0 }, // 5664
|
|
{ PseudoVMFLE_VFPR32_MF2_MASK, VMFLE_VF, 0x7, 0x0 }, // 5665
|
|
{ PseudoVMFLE_VV_M1, VMFLE_VV, 0x0, 0x0 }, // 5666
|
|
{ PseudoVMFLE_VV_M1_MASK, VMFLE_VV, 0x0, 0x0 }, // 5667
|
|
{ PseudoVMFLE_VV_M2, VMFLE_VV, 0x1, 0x0 }, // 5668
|
|
{ PseudoVMFLE_VV_M2_MASK, VMFLE_VV, 0x1, 0x0 }, // 5669
|
|
{ PseudoVMFLE_VV_M4, VMFLE_VV, 0x2, 0x0 }, // 5670
|
|
{ PseudoVMFLE_VV_M4_MASK, VMFLE_VV, 0x2, 0x0 }, // 5671
|
|
{ PseudoVMFLE_VV_M8, VMFLE_VV, 0x3, 0x0 }, // 5672
|
|
{ PseudoVMFLE_VV_M8_MASK, VMFLE_VV, 0x3, 0x0 }, // 5673
|
|
{ PseudoVMFLE_VV_MF4, VMFLE_VV, 0x6, 0x0 }, // 5674
|
|
{ PseudoVMFLE_VV_MF4_MASK, VMFLE_VV, 0x6, 0x0 }, // 5675
|
|
{ PseudoVMFLE_VV_MF2, VMFLE_VV, 0x7, 0x0 }, // 5676
|
|
{ PseudoVMFLE_VV_MF2_MASK, VMFLE_VV, 0x7, 0x0 }, // 5677
|
|
{ PseudoVMFLT_VFPR16_M1, VMFLT_VF, 0x0, 0x0 }, // 5678
|
|
{ PseudoVMFLT_VFPR16_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 5679
|
|
{ PseudoVMFLT_VFPR32_M1, VMFLT_VF, 0x0, 0x0 }, // 5680
|
|
{ PseudoVMFLT_VFPR32_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 5681
|
|
{ PseudoVMFLT_VFPR64_M1, VMFLT_VF, 0x0, 0x0 }, // 5682
|
|
{ PseudoVMFLT_VFPR64_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 5683
|
|
{ PseudoVMFLT_VFPR16_M2, VMFLT_VF, 0x1, 0x0 }, // 5684
|
|
{ PseudoVMFLT_VFPR16_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 5685
|
|
{ PseudoVMFLT_VFPR32_M2, VMFLT_VF, 0x1, 0x0 }, // 5686
|
|
{ PseudoVMFLT_VFPR32_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 5687
|
|
{ PseudoVMFLT_VFPR64_M2, VMFLT_VF, 0x1, 0x0 }, // 5688
|
|
{ PseudoVMFLT_VFPR64_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 5689
|
|
{ PseudoVMFLT_VFPR16_M4, VMFLT_VF, 0x2, 0x0 }, // 5690
|
|
{ PseudoVMFLT_VFPR16_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 5691
|
|
{ PseudoVMFLT_VFPR32_M4, VMFLT_VF, 0x2, 0x0 }, // 5692
|
|
{ PseudoVMFLT_VFPR32_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 5693
|
|
{ PseudoVMFLT_VFPR64_M4, VMFLT_VF, 0x2, 0x0 }, // 5694
|
|
{ PseudoVMFLT_VFPR64_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 5695
|
|
{ PseudoVMFLT_VFPR16_M8, VMFLT_VF, 0x3, 0x0 }, // 5696
|
|
{ PseudoVMFLT_VFPR16_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 5697
|
|
{ PseudoVMFLT_VFPR32_M8, VMFLT_VF, 0x3, 0x0 }, // 5698
|
|
{ PseudoVMFLT_VFPR32_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 5699
|
|
{ PseudoVMFLT_VFPR64_M8, VMFLT_VF, 0x3, 0x0 }, // 5700
|
|
{ PseudoVMFLT_VFPR64_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 5701
|
|
{ PseudoVMFLT_VFPR16_MF4, VMFLT_VF, 0x6, 0x0 }, // 5702
|
|
{ PseudoVMFLT_VFPR16_MF4_MASK, VMFLT_VF, 0x6, 0x0 }, // 5703
|
|
{ PseudoVMFLT_VFPR16_MF2, VMFLT_VF, 0x7, 0x0 }, // 5704
|
|
{ PseudoVMFLT_VFPR16_MF2_MASK, VMFLT_VF, 0x7, 0x0 }, // 5705
|
|
{ PseudoVMFLT_VFPR32_MF2, VMFLT_VF, 0x7, 0x0 }, // 5706
|
|
{ PseudoVMFLT_VFPR32_MF2_MASK, VMFLT_VF, 0x7, 0x0 }, // 5707
|
|
{ PseudoVMFLT_VV_M1, VMFLT_VV, 0x0, 0x0 }, // 5708
|
|
{ PseudoVMFLT_VV_M1_MASK, VMFLT_VV, 0x0, 0x0 }, // 5709
|
|
{ PseudoVMFLT_VV_M2, VMFLT_VV, 0x1, 0x0 }, // 5710
|
|
{ PseudoVMFLT_VV_M2_MASK, VMFLT_VV, 0x1, 0x0 }, // 5711
|
|
{ PseudoVMFLT_VV_M4, VMFLT_VV, 0x2, 0x0 }, // 5712
|
|
{ PseudoVMFLT_VV_M4_MASK, VMFLT_VV, 0x2, 0x0 }, // 5713
|
|
{ PseudoVMFLT_VV_M8, VMFLT_VV, 0x3, 0x0 }, // 5714
|
|
{ PseudoVMFLT_VV_M8_MASK, VMFLT_VV, 0x3, 0x0 }, // 5715
|
|
{ PseudoVMFLT_VV_MF4, VMFLT_VV, 0x6, 0x0 }, // 5716
|
|
{ PseudoVMFLT_VV_MF4_MASK, VMFLT_VV, 0x6, 0x0 }, // 5717
|
|
{ PseudoVMFLT_VV_MF2, VMFLT_VV, 0x7, 0x0 }, // 5718
|
|
{ PseudoVMFLT_VV_MF2_MASK, VMFLT_VV, 0x7, 0x0 }, // 5719
|
|
{ PseudoVMFNE_VFPR16_M1, VMFNE_VF, 0x0, 0x0 }, // 5720
|
|
{ PseudoVMFNE_VFPR16_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 5721
|
|
{ PseudoVMFNE_VFPR32_M1, VMFNE_VF, 0x0, 0x0 }, // 5722
|
|
{ PseudoVMFNE_VFPR32_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 5723
|
|
{ PseudoVMFNE_VFPR64_M1, VMFNE_VF, 0x0, 0x0 }, // 5724
|
|
{ PseudoVMFNE_VFPR64_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 5725
|
|
{ PseudoVMFNE_VFPR16_M2, VMFNE_VF, 0x1, 0x0 }, // 5726
|
|
{ PseudoVMFNE_VFPR16_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 5727
|
|
{ PseudoVMFNE_VFPR32_M2, VMFNE_VF, 0x1, 0x0 }, // 5728
|
|
{ PseudoVMFNE_VFPR32_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 5729
|
|
{ PseudoVMFNE_VFPR64_M2, VMFNE_VF, 0x1, 0x0 }, // 5730
|
|
{ PseudoVMFNE_VFPR64_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 5731
|
|
{ PseudoVMFNE_VFPR16_M4, VMFNE_VF, 0x2, 0x0 }, // 5732
|
|
{ PseudoVMFNE_VFPR16_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 5733
|
|
{ PseudoVMFNE_VFPR32_M4, VMFNE_VF, 0x2, 0x0 }, // 5734
|
|
{ PseudoVMFNE_VFPR32_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 5735
|
|
{ PseudoVMFNE_VFPR64_M4, VMFNE_VF, 0x2, 0x0 }, // 5736
|
|
{ PseudoVMFNE_VFPR64_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 5737
|
|
{ PseudoVMFNE_VFPR16_M8, VMFNE_VF, 0x3, 0x0 }, // 5738
|
|
{ PseudoVMFNE_VFPR16_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 5739
|
|
{ PseudoVMFNE_VFPR32_M8, VMFNE_VF, 0x3, 0x0 }, // 5740
|
|
{ PseudoVMFNE_VFPR32_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 5741
|
|
{ PseudoVMFNE_VFPR64_M8, VMFNE_VF, 0x3, 0x0 }, // 5742
|
|
{ PseudoVMFNE_VFPR64_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 5743
|
|
{ PseudoVMFNE_VFPR16_MF4, VMFNE_VF, 0x6, 0x0 }, // 5744
|
|
{ PseudoVMFNE_VFPR16_MF4_MASK, VMFNE_VF, 0x6, 0x0 }, // 5745
|
|
{ PseudoVMFNE_VFPR16_MF2, VMFNE_VF, 0x7, 0x0 }, // 5746
|
|
{ PseudoVMFNE_VFPR16_MF2_MASK, VMFNE_VF, 0x7, 0x0 }, // 5747
|
|
{ PseudoVMFNE_VFPR32_MF2, VMFNE_VF, 0x7, 0x0 }, // 5748
|
|
{ PseudoVMFNE_VFPR32_MF2_MASK, VMFNE_VF, 0x7, 0x0 }, // 5749
|
|
{ PseudoVMFNE_VV_M1, VMFNE_VV, 0x0, 0x0 }, // 5750
|
|
{ PseudoVMFNE_VV_M1_MASK, VMFNE_VV, 0x0, 0x0 }, // 5751
|
|
{ PseudoVMFNE_VV_M2, VMFNE_VV, 0x1, 0x0 }, // 5752
|
|
{ PseudoVMFNE_VV_M2_MASK, VMFNE_VV, 0x1, 0x0 }, // 5753
|
|
{ PseudoVMFNE_VV_M4, VMFNE_VV, 0x2, 0x0 }, // 5754
|
|
{ PseudoVMFNE_VV_M4_MASK, VMFNE_VV, 0x2, 0x0 }, // 5755
|
|
{ PseudoVMFNE_VV_M8, VMFNE_VV, 0x3, 0x0 }, // 5756
|
|
{ PseudoVMFNE_VV_M8_MASK, VMFNE_VV, 0x3, 0x0 }, // 5757
|
|
{ PseudoVMFNE_VV_MF4, VMFNE_VV, 0x6, 0x0 }, // 5758
|
|
{ PseudoVMFNE_VV_MF4_MASK, VMFNE_VV, 0x6, 0x0 }, // 5759
|
|
{ PseudoVMFNE_VV_MF2, VMFNE_VV, 0x7, 0x0 }, // 5760
|
|
{ PseudoVMFNE_VV_MF2_MASK, VMFNE_VV, 0x7, 0x0 }, // 5761
|
|
{ PseudoVMINU_VV_M1, VMINU_VV, 0x0, 0x0 }, // 5762
|
|
{ PseudoVMINU_VV_M1_MASK, VMINU_VV, 0x0, 0x0 }, // 5763
|
|
{ PseudoVMINU_VV_M2, VMINU_VV, 0x1, 0x0 }, // 5764
|
|
{ PseudoVMINU_VV_M2_MASK, VMINU_VV, 0x1, 0x0 }, // 5765
|
|
{ PseudoVMINU_VV_M4, VMINU_VV, 0x2, 0x0 }, // 5766
|
|
{ PseudoVMINU_VV_M4_MASK, VMINU_VV, 0x2, 0x0 }, // 5767
|
|
{ PseudoVMINU_VV_M8, VMINU_VV, 0x3, 0x0 }, // 5768
|
|
{ PseudoVMINU_VV_M8_MASK, VMINU_VV, 0x3, 0x0 }, // 5769
|
|
{ PseudoVMINU_VV_MF8, VMINU_VV, 0x5, 0x0 }, // 5770
|
|
{ PseudoVMINU_VV_MF8_MASK, VMINU_VV, 0x5, 0x0 }, // 5771
|
|
{ PseudoVMINU_VV_MF4, VMINU_VV, 0x6, 0x0 }, // 5772
|
|
{ PseudoVMINU_VV_MF4_MASK, VMINU_VV, 0x6, 0x0 }, // 5773
|
|
{ PseudoVMINU_VV_MF2, VMINU_VV, 0x7, 0x0 }, // 5774
|
|
{ PseudoVMINU_VV_MF2_MASK, VMINU_VV, 0x7, 0x0 }, // 5775
|
|
{ PseudoVMINU_VX_M1, VMINU_VX, 0x0, 0x0 }, // 5776
|
|
{ PseudoVMINU_VX_M1_MASK, VMINU_VX, 0x0, 0x0 }, // 5777
|
|
{ PseudoVMINU_VX_M2, VMINU_VX, 0x1, 0x0 }, // 5778
|
|
{ PseudoVMINU_VX_M2_MASK, VMINU_VX, 0x1, 0x0 }, // 5779
|
|
{ PseudoVMINU_VX_M4, VMINU_VX, 0x2, 0x0 }, // 5780
|
|
{ PseudoVMINU_VX_M4_MASK, VMINU_VX, 0x2, 0x0 }, // 5781
|
|
{ PseudoVMINU_VX_M8, VMINU_VX, 0x3, 0x0 }, // 5782
|
|
{ PseudoVMINU_VX_M8_MASK, VMINU_VX, 0x3, 0x0 }, // 5783
|
|
{ PseudoVMINU_VX_MF8, VMINU_VX, 0x5, 0x0 }, // 5784
|
|
{ PseudoVMINU_VX_MF8_MASK, VMINU_VX, 0x5, 0x0 }, // 5785
|
|
{ PseudoVMINU_VX_MF4, VMINU_VX, 0x6, 0x0 }, // 5786
|
|
{ PseudoVMINU_VX_MF4_MASK, VMINU_VX, 0x6, 0x0 }, // 5787
|
|
{ PseudoVMINU_VX_MF2, VMINU_VX, 0x7, 0x0 }, // 5788
|
|
{ PseudoVMINU_VX_MF2_MASK, VMINU_VX, 0x7, 0x0 }, // 5789
|
|
{ PseudoVMIN_VV_M1, VMIN_VV, 0x0, 0x0 }, // 5790
|
|
{ PseudoVMIN_VV_M1_MASK, VMIN_VV, 0x0, 0x0 }, // 5791
|
|
{ PseudoVMIN_VV_M2, VMIN_VV, 0x1, 0x0 }, // 5792
|
|
{ PseudoVMIN_VV_M2_MASK, VMIN_VV, 0x1, 0x0 }, // 5793
|
|
{ PseudoVMIN_VV_M4, VMIN_VV, 0x2, 0x0 }, // 5794
|
|
{ PseudoVMIN_VV_M4_MASK, VMIN_VV, 0x2, 0x0 }, // 5795
|
|
{ PseudoVMIN_VV_M8, VMIN_VV, 0x3, 0x0 }, // 5796
|
|
{ PseudoVMIN_VV_M8_MASK, VMIN_VV, 0x3, 0x0 }, // 5797
|
|
{ PseudoVMIN_VV_MF8, VMIN_VV, 0x5, 0x0 }, // 5798
|
|
{ PseudoVMIN_VV_MF8_MASK, VMIN_VV, 0x5, 0x0 }, // 5799
|
|
{ PseudoVMIN_VV_MF4, VMIN_VV, 0x6, 0x0 }, // 5800
|
|
{ PseudoVMIN_VV_MF4_MASK, VMIN_VV, 0x6, 0x0 }, // 5801
|
|
{ PseudoVMIN_VV_MF2, VMIN_VV, 0x7, 0x0 }, // 5802
|
|
{ PseudoVMIN_VV_MF2_MASK, VMIN_VV, 0x7, 0x0 }, // 5803
|
|
{ PseudoVMIN_VX_M1, VMIN_VX, 0x0, 0x0 }, // 5804
|
|
{ PseudoVMIN_VX_M1_MASK, VMIN_VX, 0x0, 0x0 }, // 5805
|
|
{ PseudoVMIN_VX_M2, VMIN_VX, 0x1, 0x0 }, // 5806
|
|
{ PseudoVMIN_VX_M2_MASK, VMIN_VX, 0x1, 0x0 }, // 5807
|
|
{ PseudoVMIN_VX_M4, VMIN_VX, 0x2, 0x0 }, // 5808
|
|
{ PseudoVMIN_VX_M4_MASK, VMIN_VX, 0x2, 0x0 }, // 5809
|
|
{ PseudoVMIN_VX_M8, VMIN_VX, 0x3, 0x0 }, // 5810
|
|
{ PseudoVMIN_VX_M8_MASK, VMIN_VX, 0x3, 0x0 }, // 5811
|
|
{ PseudoVMIN_VX_MF8, VMIN_VX, 0x5, 0x0 }, // 5812
|
|
{ PseudoVMIN_VX_MF8_MASK, VMIN_VX, 0x5, 0x0 }, // 5813
|
|
{ PseudoVMIN_VX_MF4, VMIN_VX, 0x6, 0x0 }, // 5814
|
|
{ PseudoVMIN_VX_MF4_MASK, VMIN_VX, 0x6, 0x0 }, // 5815
|
|
{ PseudoVMIN_VX_MF2, VMIN_VX, 0x7, 0x0 }, // 5816
|
|
{ PseudoVMIN_VX_MF2_MASK, VMIN_VX, 0x7, 0x0 }, // 5817
|
|
{ PseudoVMNAND_MM_M1, VMNAND_MM, 0x0, 0x0 }, // 5818
|
|
{ PseudoVMNAND_MM_M2, VMNAND_MM, 0x1, 0x0 }, // 5819
|
|
{ PseudoVMNAND_MM_M4, VMNAND_MM, 0x2, 0x0 }, // 5820
|
|
{ PseudoVMNAND_MM_M8, VMNAND_MM, 0x3, 0x0 }, // 5821
|
|
{ PseudoVMNAND_MM_MF8, VMNAND_MM, 0x5, 0x0 }, // 5822
|
|
{ PseudoVMNAND_MM_MF4, VMNAND_MM, 0x6, 0x0 }, // 5823
|
|
{ PseudoVMNAND_MM_MF2, VMNAND_MM, 0x7, 0x0 }, // 5824
|
|
{ PseudoVMNOR_MM_M1, VMNOR_MM, 0x0, 0x0 }, // 5825
|
|
{ PseudoVMNOR_MM_M2, VMNOR_MM, 0x1, 0x0 }, // 5826
|
|
{ PseudoVMNOR_MM_M4, VMNOR_MM, 0x2, 0x0 }, // 5827
|
|
{ PseudoVMNOR_MM_M8, VMNOR_MM, 0x3, 0x0 }, // 5828
|
|
{ PseudoVMNOR_MM_MF8, VMNOR_MM, 0x5, 0x0 }, // 5829
|
|
{ PseudoVMNOR_MM_MF4, VMNOR_MM, 0x6, 0x0 }, // 5830
|
|
{ PseudoVMNOR_MM_MF2, VMNOR_MM, 0x7, 0x0 }, // 5831
|
|
{ PseudoVMORN_MM_M1, VMORN_MM, 0x0, 0x0 }, // 5832
|
|
{ PseudoVMORN_MM_M2, VMORN_MM, 0x1, 0x0 }, // 5833
|
|
{ PseudoVMORN_MM_M4, VMORN_MM, 0x2, 0x0 }, // 5834
|
|
{ PseudoVMORN_MM_M8, VMORN_MM, 0x3, 0x0 }, // 5835
|
|
{ PseudoVMORN_MM_MF8, VMORN_MM, 0x5, 0x0 }, // 5836
|
|
{ PseudoVMORN_MM_MF4, VMORN_MM, 0x6, 0x0 }, // 5837
|
|
{ PseudoVMORN_MM_MF2, VMORN_MM, 0x7, 0x0 }, // 5838
|
|
{ PseudoVMOR_MM_M1, VMOR_MM, 0x0, 0x0 }, // 5839
|
|
{ PseudoVMOR_MM_M2, VMOR_MM, 0x1, 0x0 }, // 5840
|
|
{ PseudoVMOR_MM_M4, VMOR_MM, 0x2, 0x0 }, // 5841
|
|
{ PseudoVMOR_MM_M8, VMOR_MM, 0x3, 0x0 }, // 5842
|
|
{ PseudoVMOR_MM_MF8, VMOR_MM, 0x5, 0x0 }, // 5843
|
|
{ PseudoVMOR_MM_MF4, VMOR_MM, 0x6, 0x0 }, // 5844
|
|
{ PseudoVMOR_MM_MF2, VMOR_MM, 0x7, 0x0 }, // 5845
|
|
{ PseudoVMSBC_VV_M1, VMSBC_VV, 0x0, 0x0 }, // 5846
|
|
{ PseudoVMSBC_VV_M2, VMSBC_VV, 0x1, 0x0 }, // 5847
|
|
{ PseudoVMSBC_VV_M4, VMSBC_VV, 0x2, 0x0 }, // 5848
|
|
{ PseudoVMSBC_VV_M8, VMSBC_VV, 0x3, 0x0 }, // 5849
|
|
{ PseudoVMSBC_VV_MF8, VMSBC_VV, 0x5, 0x0 }, // 5850
|
|
{ PseudoVMSBC_VV_MF4, VMSBC_VV, 0x6, 0x0 }, // 5851
|
|
{ PseudoVMSBC_VV_MF2, VMSBC_VV, 0x7, 0x0 }, // 5852
|
|
{ PseudoVMSBC_VVM_M1, VMSBC_VVM, 0x0, 0x0 }, // 5853
|
|
{ PseudoVMSBC_VVM_M2, VMSBC_VVM, 0x1, 0x0 }, // 5854
|
|
{ PseudoVMSBC_VVM_M4, VMSBC_VVM, 0x2, 0x0 }, // 5855
|
|
{ PseudoVMSBC_VVM_M8, VMSBC_VVM, 0x3, 0x0 }, // 5856
|
|
{ PseudoVMSBC_VVM_MF8, VMSBC_VVM, 0x5, 0x0 }, // 5857
|
|
{ PseudoVMSBC_VVM_MF4, VMSBC_VVM, 0x6, 0x0 }, // 5858
|
|
{ PseudoVMSBC_VVM_MF2, VMSBC_VVM, 0x7, 0x0 }, // 5859
|
|
{ PseudoVMSBC_VX_M1, VMSBC_VX, 0x0, 0x0 }, // 5860
|
|
{ PseudoVMSBC_VX_M2, VMSBC_VX, 0x1, 0x0 }, // 5861
|
|
{ PseudoVMSBC_VX_M4, VMSBC_VX, 0x2, 0x0 }, // 5862
|
|
{ PseudoVMSBC_VX_M8, VMSBC_VX, 0x3, 0x0 }, // 5863
|
|
{ PseudoVMSBC_VX_MF8, VMSBC_VX, 0x5, 0x0 }, // 5864
|
|
{ PseudoVMSBC_VX_MF4, VMSBC_VX, 0x6, 0x0 }, // 5865
|
|
{ PseudoVMSBC_VX_MF2, VMSBC_VX, 0x7, 0x0 }, // 5866
|
|
{ PseudoVMSBC_VXM_M1, VMSBC_VXM, 0x0, 0x0 }, // 5867
|
|
{ PseudoVMSBC_VXM_M2, VMSBC_VXM, 0x1, 0x0 }, // 5868
|
|
{ PseudoVMSBC_VXM_M4, VMSBC_VXM, 0x2, 0x0 }, // 5869
|
|
{ PseudoVMSBC_VXM_M8, VMSBC_VXM, 0x3, 0x0 }, // 5870
|
|
{ PseudoVMSBC_VXM_MF8, VMSBC_VXM, 0x5, 0x0 }, // 5871
|
|
{ PseudoVMSBC_VXM_MF4, VMSBC_VXM, 0x6, 0x0 }, // 5872
|
|
{ PseudoVMSBC_VXM_MF2, VMSBC_VXM, 0x7, 0x0 }, // 5873
|
|
{ PseudoVMSBF_M_B8, VMSBF_M, 0x0, 0x0 }, // 5874
|
|
{ PseudoVMSBF_M_B8_MASK, VMSBF_M, 0x0, 0x0 }, // 5875
|
|
{ PseudoVMSBF_M_B16, VMSBF_M, 0x1, 0x0 }, // 5876
|
|
{ PseudoVMSBF_M_B16_MASK, VMSBF_M, 0x1, 0x0 }, // 5877
|
|
{ PseudoVMSBF_M_B32, VMSBF_M, 0x2, 0x0 }, // 5878
|
|
{ PseudoVMSBF_M_B32_MASK, VMSBF_M, 0x2, 0x0 }, // 5879
|
|
{ PseudoVMSBF_M_B64, VMSBF_M, 0x3, 0x0 }, // 5880
|
|
{ PseudoVMSBF_M_B64_MASK, VMSBF_M, 0x3, 0x0 }, // 5881
|
|
{ PseudoVMSBF_M_B1, VMSBF_M, 0x5, 0x0 }, // 5882
|
|
{ PseudoVMSBF_M_B1_MASK, VMSBF_M, 0x5, 0x0 }, // 5883
|
|
{ PseudoVMSBF_M_B2, VMSBF_M, 0x6, 0x0 }, // 5884
|
|
{ PseudoVMSBF_M_B2_MASK, VMSBF_M, 0x6, 0x0 }, // 5885
|
|
{ PseudoVMSBF_M_B4, VMSBF_M, 0x7, 0x0 }, // 5886
|
|
{ PseudoVMSBF_M_B4_MASK, VMSBF_M, 0x7, 0x0 }, // 5887
|
|
{ PseudoVMSEQ_VI_M1, VMSEQ_VI, 0x0, 0x0 }, // 5888
|
|
{ PseudoVMSEQ_VI_M1_MASK, VMSEQ_VI, 0x0, 0x0 }, // 5889
|
|
{ PseudoVMSEQ_VI_M2, VMSEQ_VI, 0x1, 0x0 }, // 5890
|
|
{ PseudoVMSEQ_VI_M2_MASK, VMSEQ_VI, 0x1, 0x0 }, // 5891
|
|
{ PseudoVMSEQ_VI_M4, VMSEQ_VI, 0x2, 0x0 }, // 5892
|
|
{ PseudoVMSEQ_VI_M4_MASK, VMSEQ_VI, 0x2, 0x0 }, // 5893
|
|
{ PseudoVMSEQ_VI_M8, VMSEQ_VI, 0x3, 0x0 }, // 5894
|
|
{ PseudoVMSEQ_VI_M8_MASK, VMSEQ_VI, 0x3, 0x0 }, // 5895
|
|
{ PseudoVMSEQ_VI_MF8, VMSEQ_VI, 0x5, 0x0 }, // 5896
|
|
{ PseudoVMSEQ_VI_MF8_MASK, VMSEQ_VI, 0x5, 0x0 }, // 5897
|
|
{ PseudoVMSEQ_VI_MF4, VMSEQ_VI, 0x6, 0x0 }, // 5898
|
|
{ PseudoVMSEQ_VI_MF4_MASK, VMSEQ_VI, 0x6, 0x0 }, // 5899
|
|
{ PseudoVMSEQ_VI_MF2, VMSEQ_VI, 0x7, 0x0 }, // 5900
|
|
{ PseudoVMSEQ_VI_MF2_MASK, VMSEQ_VI, 0x7, 0x0 }, // 5901
|
|
{ PseudoVMSEQ_VV_M1, VMSEQ_VV, 0x0, 0x0 }, // 5902
|
|
{ PseudoVMSEQ_VV_M1_MASK, VMSEQ_VV, 0x0, 0x0 }, // 5903
|
|
{ PseudoVMSEQ_VV_M2, VMSEQ_VV, 0x1, 0x0 }, // 5904
|
|
{ PseudoVMSEQ_VV_M2_MASK, VMSEQ_VV, 0x1, 0x0 }, // 5905
|
|
{ PseudoVMSEQ_VV_M4, VMSEQ_VV, 0x2, 0x0 }, // 5906
|
|
{ PseudoVMSEQ_VV_M4_MASK, VMSEQ_VV, 0x2, 0x0 }, // 5907
|
|
{ PseudoVMSEQ_VV_M8, VMSEQ_VV, 0x3, 0x0 }, // 5908
|
|
{ PseudoVMSEQ_VV_M8_MASK, VMSEQ_VV, 0x3, 0x0 }, // 5909
|
|
{ PseudoVMSEQ_VV_MF8, VMSEQ_VV, 0x5, 0x0 }, // 5910
|
|
{ PseudoVMSEQ_VV_MF8_MASK, VMSEQ_VV, 0x5, 0x0 }, // 5911
|
|
{ PseudoVMSEQ_VV_MF4, VMSEQ_VV, 0x6, 0x0 }, // 5912
|
|
{ PseudoVMSEQ_VV_MF4_MASK, VMSEQ_VV, 0x6, 0x0 }, // 5913
|
|
{ PseudoVMSEQ_VV_MF2, VMSEQ_VV, 0x7, 0x0 }, // 5914
|
|
{ PseudoVMSEQ_VV_MF2_MASK, VMSEQ_VV, 0x7, 0x0 }, // 5915
|
|
{ PseudoVMSEQ_VX_M1, VMSEQ_VX, 0x0, 0x0 }, // 5916
|
|
{ PseudoVMSEQ_VX_M1_MASK, VMSEQ_VX, 0x0, 0x0 }, // 5917
|
|
{ PseudoVMSEQ_VX_M2, VMSEQ_VX, 0x1, 0x0 }, // 5918
|
|
{ PseudoVMSEQ_VX_M2_MASK, VMSEQ_VX, 0x1, 0x0 }, // 5919
|
|
{ PseudoVMSEQ_VX_M4, VMSEQ_VX, 0x2, 0x0 }, // 5920
|
|
{ PseudoVMSEQ_VX_M4_MASK, VMSEQ_VX, 0x2, 0x0 }, // 5921
|
|
{ PseudoVMSEQ_VX_M8, VMSEQ_VX, 0x3, 0x0 }, // 5922
|
|
{ PseudoVMSEQ_VX_M8_MASK, VMSEQ_VX, 0x3, 0x0 }, // 5923
|
|
{ PseudoVMSEQ_VX_MF8, VMSEQ_VX, 0x5, 0x0 }, // 5924
|
|
{ PseudoVMSEQ_VX_MF8_MASK, VMSEQ_VX, 0x5, 0x0 }, // 5925
|
|
{ PseudoVMSEQ_VX_MF4, VMSEQ_VX, 0x6, 0x0 }, // 5926
|
|
{ PseudoVMSEQ_VX_MF4_MASK, VMSEQ_VX, 0x6, 0x0 }, // 5927
|
|
{ PseudoVMSEQ_VX_MF2, VMSEQ_VX, 0x7, 0x0 }, // 5928
|
|
{ PseudoVMSEQ_VX_MF2_MASK, VMSEQ_VX, 0x7, 0x0 }, // 5929
|
|
{ PseudoVMSGTU_VI_M1, VMSGTU_VI, 0x0, 0x0 }, // 5930
|
|
{ PseudoVMSGTU_VI_M1_MASK, VMSGTU_VI, 0x0, 0x0 }, // 5931
|
|
{ PseudoVMSGTU_VI_M2, VMSGTU_VI, 0x1, 0x0 }, // 5932
|
|
{ PseudoVMSGTU_VI_M2_MASK, VMSGTU_VI, 0x1, 0x0 }, // 5933
|
|
{ PseudoVMSGTU_VI_M4, VMSGTU_VI, 0x2, 0x0 }, // 5934
|
|
{ PseudoVMSGTU_VI_M4_MASK, VMSGTU_VI, 0x2, 0x0 }, // 5935
|
|
{ PseudoVMSGTU_VI_M8, VMSGTU_VI, 0x3, 0x0 }, // 5936
|
|
{ PseudoVMSGTU_VI_M8_MASK, VMSGTU_VI, 0x3, 0x0 }, // 5937
|
|
{ PseudoVMSGTU_VI_MF8, VMSGTU_VI, 0x5, 0x0 }, // 5938
|
|
{ PseudoVMSGTU_VI_MF8_MASK, VMSGTU_VI, 0x5, 0x0 }, // 5939
|
|
{ PseudoVMSGTU_VI_MF4, VMSGTU_VI, 0x6, 0x0 }, // 5940
|
|
{ PseudoVMSGTU_VI_MF4_MASK, VMSGTU_VI, 0x6, 0x0 }, // 5941
|
|
{ PseudoVMSGTU_VI_MF2, VMSGTU_VI, 0x7, 0x0 }, // 5942
|
|
{ PseudoVMSGTU_VI_MF2_MASK, VMSGTU_VI, 0x7, 0x0 }, // 5943
|
|
{ PseudoVMSGTU_VX_M1, VMSGTU_VX, 0x0, 0x0 }, // 5944
|
|
{ PseudoVMSGTU_VX_M1_MASK, VMSGTU_VX, 0x0, 0x0 }, // 5945
|
|
{ PseudoVMSGTU_VX_M2, VMSGTU_VX, 0x1, 0x0 }, // 5946
|
|
{ PseudoVMSGTU_VX_M2_MASK, VMSGTU_VX, 0x1, 0x0 }, // 5947
|
|
{ PseudoVMSGTU_VX_M4, VMSGTU_VX, 0x2, 0x0 }, // 5948
|
|
{ PseudoVMSGTU_VX_M4_MASK, VMSGTU_VX, 0x2, 0x0 }, // 5949
|
|
{ PseudoVMSGTU_VX_M8, VMSGTU_VX, 0x3, 0x0 }, // 5950
|
|
{ PseudoVMSGTU_VX_M8_MASK, VMSGTU_VX, 0x3, 0x0 }, // 5951
|
|
{ PseudoVMSGTU_VX_MF8, VMSGTU_VX, 0x5, 0x0 }, // 5952
|
|
{ PseudoVMSGTU_VX_MF8_MASK, VMSGTU_VX, 0x5, 0x0 }, // 5953
|
|
{ PseudoVMSGTU_VX_MF4, VMSGTU_VX, 0x6, 0x0 }, // 5954
|
|
{ PseudoVMSGTU_VX_MF4_MASK, VMSGTU_VX, 0x6, 0x0 }, // 5955
|
|
{ PseudoVMSGTU_VX_MF2, VMSGTU_VX, 0x7, 0x0 }, // 5956
|
|
{ PseudoVMSGTU_VX_MF2_MASK, VMSGTU_VX, 0x7, 0x0 }, // 5957
|
|
{ PseudoVMSGT_VI_M1, VMSGT_VI, 0x0, 0x0 }, // 5958
|
|
{ PseudoVMSGT_VI_M1_MASK, VMSGT_VI, 0x0, 0x0 }, // 5959
|
|
{ PseudoVMSGT_VI_M2, VMSGT_VI, 0x1, 0x0 }, // 5960
|
|
{ PseudoVMSGT_VI_M2_MASK, VMSGT_VI, 0x1, 0x0 }, // 5961
|
|
{ PseudoVMSGT_VI_M4, VMSGT_VI, 0x2, 0x0 }, // 5962
|
|
{ PseudoVMSGT_VI_M4_MASK, VMSGT_VI, 0x2, 0x0 }, // 5963
|
|
{ PseudoVMSGT_VI_M8, VMSGT_VI, 0x3, 0x0 }, // 5964
|
|
{ PseudoVMSGT_VI_M8_MASK, VMSGT_VI, 0x3, 0x0 }, // 5965
|
|
{ PseudoVMSGT_VI_MF8, VMSGT_VI, 0x5, 0x0 }, // 5966
|
|
{ PseudoVMSGT_VI_MF8_MASK, VMSGT_VI, 0x5, 0x0 }, // 5967
|
|
{ PseudoVMSGT_VI_MF4, VMSGT_VI, 0x6, 0x0 }, // 5968
|
|
{ PseudoVMSGT_VI_MF4_MASK, VMSGT_VI, 0x6, 0x0 }, // 5969
|
|
{ PseudoVMSGT_VI_MF2, VMSGT_VI, 0x7, 0x0 }, // 5970
|
|
{ PseudoVMSGT_VI_MF2_MASK, VMSGT_VI, 0x7, 0x0 }, // 5971
|
|
{ PseudoVMSGT_VX_M1, VMSGT_VX, 0x0, 0x0 }, // 5972
|
|
{ PseudoVMSGT_VX_M1_MASK, VMSGT_VX, 0x0, 0x0 }, // 5973
|
|
{ PseudoVMSGT_VX_M2, VMSGT_VX, 0x1, 0x0 }, // 5974
|
|
{ PseudoVMSGT_VX_M2_MASK, VMSGT_VX, 0x1, 0x0 }, // 5975
|
|
{ PseudoVMSGT_VX_M4, VMSGT_VX, 0x2, 0x0 }, // 5976
|
|
{ PseudoVMSGT_VX_M4_MASK, VMSGT_VX, 0x2, 0x0 }, // 5977
|
|
{ PseudoVMSGT_VX_M8, VMSGT_VX, 0x3, 0x0 }, // 5978
|
|
{ PseudoVMSGT_VX_M8_MASK, VMSGT_VX, 0x3, 0x0 }, // 5979
|
|
{ PseudoVMSGT_VX_MF8, VMSGT_VX, 0x5, 0x0 }, // 5980
|
|
{ PseudoVMSGT_VX_MF8_MASK, VMSGT_VX, 0x5, 0x0 }, // 5981
|
|
{ PseudoVMSGT_VX_MF4, VMSGT_VX, 0x6, 0x0 }, // 5982
|
|
{ PseudoVMSGT_VX_MF4_MASK, VMSGT_VX, 0x6, 0x0 }, // 5983
|
|
{ PseudoVMSGT_VX_MF2, VMSGT_VX, 0x7, 0x0 }, // 5984
|
|
{ PseudoVMSGT_VX_MF2_MASK, VMSGT_VX, 0x7, 0x0 }, // 5985
|
|
{ PseudoVMSIF_M_B8, VMSIF_M, 0x0, 0x0 }, // 5986
|
|
{ PseudoVMSIF_M_B8_MASK, VMSIF_M, 0x0, 0x0 }, // 5987
|
|
{ PseudoVMSIF_M_B16, VMSIF_M, 0x1, 0x0 }, // 5988
|
|
{ PseudoVMSIF_M_B16_MASK, VMSIF_M, 0x1, 0x0 }, // 5989
|
|
{ PseudoVMSIF_M_B32, VMSIF_M, 0x2, 0x0 }, // 5990
|
|
{ PseudoVMSIF_M_B32_MASK, VMSIF_M, 0x2, 0x0 }, // 5991
|
|
{ PseudoVMSIF_M_B64, VMSIF_M, 0x3, 0x0 }, // 5992
|
|
{ PseudoVMSIF_M_B64_MASK, VMSIF_M, 0x3, 0x0 }, // 5993
|
|
{ PseudoVMSIF_M_B1, VMSIF_M, 0x5, 0x0 }, // 5994
|
|
{ PseudoVMSIF_M_B1_MASK, VMSIF_M, 0x5, 0x0 }, // 5995
|
|
{ PseudoVMSIF_M_B2, VMSIF_M, 0x6, 0x0 }, // 5996
|
|
{ PseudoVMSIF_M_B2_MASK, VMSIF_M, 0x6, 0x0 }, // 5997
|
|
{ PseudoVMSIF_M_B4, VMSIF_M, 0x7, 0x0 }, // 5998
|
|
{ PseudoVMSIF_M_B4_MASK, VMSIF_M, 0x7, 0x0 }, // 5999
|
|
{ PseudoVMSLEU_VI_M1, VMSLEU_VI, 0x0, 0x0 }, // 6000
|
|
{ PseudoVMSLEU_VI_M1_MASK, VMSLEU_VI, 0x0, 0x0 }, // 6001
|
|
{ PseudoVMSLEU_VI_M2, VMSLEU_VI, 0x1, 0x0 }, // 6002
|
|
{ PseudoVMSLEU_VI_M2_MASK, VMSLEU_VI, 0x1, 0x0 }, // 6003
|
|
{ PseudoVMSLEU_VI_M4, VMSLEU_VI, 0x2, 0x0 }, // 6004
|
|
{ PseudoVMSLEU_VI_M4_MASK, VMSLEU_VI, 0x2, 0x0 }, // 6005
|
|
{ PseudoVMSLEU_VI_M8, VMSLEU_VI, 0x3, 0x0 }, // 6006
|
|
{ PseudoVMSLEU_VI_M8_MASK, VMSLEU_VI, 0x3, 0x0 }, // 6007
|
|
{ PseudoVMSLEU_VI_MF8, VMSLEU_VI, 0x5, 0x0 }, // 6008
|
|
{ PseudoVMSLEU_VI_MF8_MASK, VMSLEU_VI, 0x5, 0x0 }, // 6009
|
|
{ PseudoVMSLEU_VI_MF4, VMSLEU_VI, 0x6, 0x0 }, // 6010
|
|
{ PseudoVMSLEU_VI_MF4_MASK, VMSLEU_VI, 0x6, 0x0 }, // 6011
|
|
{ PseudoVMSLEU_VI_MF2, VMSLEU_VI, 0x7, 0x0 }, // 6012
|
|
{ PseudoVMSLEU_VI_MF2_MASK, VMSLEU_VI, 0x7, 0x0 }, // 6013
|
|
{ PseudoVMSLEU_VV_M1, VMSLEU_VV, 0x0, 0x0 }, // 6014
|
|
{ PseudoVMSLEU_VV_M1_MASK, VMSLEU_VV, 0x0, 0x0 }, // 6015
|
|
{ PseudoVMSLEU_VV_M2, VMSLEU_VV, 0x1, 0x0 }, // 6016
|
|
{ PseudoVMSLEU_VV_M2_MASK, VMSLEU_VV, 0x1, 0x0 }, // 6017
|
|
{ PseudoVMSLEU_VV_M4, VMSLEU_VV, 0x2, 0x0 }, // 6018
|
|
{ PseudoVMSLEU_VV_M4_MASK, VMSLEU_VV, 0x2, 0x0 }, // 6019
|
|
{ PseudoVMSLEU_VV_M8, VMSLEU_VV, 0x3, 0x0 }, // 6020
|
|
{ PseudoVMSLEU_VV_M8_MASK, VMSLEU_VV, 0x3, 0x0 }, // 6021
|
|
{ PseudoVMSLEU_VV_MF8, VMSLEU_VV, 0x5, 0x0 }, // 6022
|
|
{ PseudoVMSLEU_VV_MF8_MASK, VMSLEU_VV, 0x5, 0x0 }, // 6023
|
|
{ PseudoVMSLEU_VV_MF4, VMSLEU_VV, 0x6, 0x0 }, // 6024
|
|
{ PseudoVMSLEU_VV_MF4_MASK, VMSLEU_VV, 0x6, 0x0 }, // 6025
|
|
{ PseudoVMSLEU_VV_MF2, VMSLEU_VV, 0x7, 0x0 }, // 6026
|
|
{ PseudoVMSLEU_VV_MF2_MASK, VMSLEU_VV, 0x7, 0x0 }, // 6027
|
|
{ PseudoVMSLEU_VX_M1, VMSLEU_VX, 0x0, 0x0 }, // 6028
|
|
{ PseudoVMSLEU_VX_M1_MASK, VMSLEU_VX, 0x0, 0x0 }, // 6029
|
|
{ PseudoVMSLEU_VX_M2, VMSLEU_VX, 0x1, 0x0 }, // 6030
|
|
{ PseudoVMSLEU_VX_M2_MASK, VMSLEU_VX, 0x1, 0x0 }, // 6031
|
|
{ PseudoVMSLEU_VX_M4, VMSLEU_VX, 0x2, 0x0 }, // 6032
|
|
{ PseudoVMSLEU_VX_M4_MASK, VMSLEU_VX, 0x2, 0x0 }, // 6033
|
|
{ PseudoVMSLEU_VX_M8, VMSLEU_VX, 0x3, 0x0 }, // 6034
|
|
{ PseudoVMSLEU_VX_M8_MASK, VMSLEU_VX, 0x3, 0x0 }, // 6035
|
|
{ PseudoVMSLEU_VX_MF8, VMSLEU_VX, 0x5, 0x0 }, // 6036
|
|
{ PseudoVMSLEU_VX_MF8_MASK, VMSLEU_VX, 0x5, 0x0 }, // 6037
|
|
{ PseudoVMSLEU_VX_MF4, VMSLEU_VX, 0x6, 0x0 }, // 6038
|
|
{ PseudoVMSLEU_VX_MF4_MASK, VMSLEU_VX, 0x6, 0x0 }, // 6039
|
|
{ PseudoVMSLEU_VX_MF2, VMSLEU_VX, 0x7, 0x0 }, // 6040
|
|
{ PseudoVMSLEU_VX_MF2_MASK, VMSLEU_VX, 0x7, 0x0 }, // 6041
|
|
{ PseudoVMSLE_VI_M1, VMSLE_VI, 0x0, 0x0 }, // 6042
|
|
{ PseudoVMSLE_VI_M1_MASK, VMSLE_VI, 0x0, 0x0 }, // 6043
|
|
{ PseudoVMSLE_VI_M2, VMSLE_VI, 0x1, 0x0 }, // 6044
|
|
{ PseudoVMSLE_VI_M2_MASK, VMSLE_VI, 0x1, 0x0 }, // 6045
|
|
{ PseudoVMSLE_VI_M4, VMSLE_VI, 0x2, 0x0 }, // 6046
|
|
{ PseudoVMSLE_VI_M4_MASK, VMSLE_VI, 0x2, 0x0 }, // 6047
|
|
{ PseudoVMSLE_VI_M8, VMSLE_VI, 0x3, 0x0 }, // 6048
|
|
{ PseudoVMSLE_VI_M8_MASK, VMSLE_VI, 0x3, 0x0 }, // 6049
|
|
{ PseudoVMSLE_VI_MF8, VMSLE_VI, 0x5, 0x0 }, // 6050
|
|
{ PseudoVMSLE_VI_MF8_MASK, VMSLE_VI, 0x5, 0x0 }, // 6051
|
|
{ PseudoVMSLE_VI_MF4, VMSLE_VI, 0x6, 0x0 }, // 6052
|
|
{ PseudoVMSLE_VI_MF4_MASK, VMSLE_VI, 0x6, 0x0 }, // 6053
|
|
{ PseudoVMSLE_VI_MF2, VMSLE_VI, 0x7, 0x0 }, // 6054
|
|
{ PseudoVMSLE_VI_MF2_MASK, VMSLE_VI, 0x7, 0x0 }, // 6055
|
|
{ PseudoVMSLE_VV_M1, VMSLE_VV, 0x0, 0x0 }, // 6056
|
|
{ PseudoVMSLE_VV_M1_MASK, VMSLE_VV, 0x0, 0x0 }, // 6057
|
|
{ PseudoVMSLE_VV_M2, VMSLE_VV, 0x1, 0x0 }, // 6058
|
|
{ PseudoVMSLE_VV_M2_MASK, VMSLE_VV, 0x1, 0x0 }, // 6059
|
|
{ PseudoVMSLE_VV_M4, VMSLE_VV, 0x2, 0x0 }, // 6060
|
|
{ PseudoVMSLE_VV_M4_MASK, VMSLE_VV, 0x2, 0x0 }, // 6061
|
|
{ PseudoVMSLE_VV_M8, VMSLE_VV, 0x3, 0x0 }, // 6062
|
|
{ PseudoVMSLE_VV_M8_MASK, VMSLE_VV, 0x3, 0x0 }, // 6063
|
|
{ PseudoVMSLE_VV_MF8, VMSLE_VV, 0x5, 0x0 }, // 6064
|
|
{ PseudoVMSLE_VV_MF8_MASK, VMSLE_VV, 0x5, 0x0 }, // 6065
|
|
{ PseudoVMSLE_VV_MF4, VMSLE_VV, 0x6, 0x0 }, // 6066
|
|
{ PseudoVMSLE_VV_MF4_MASK, VMSLE_VV, 0x6, 0x0 }, // 6067
|
|
{ PseudoVMSLE_VV_MF2, VMSLE_VV, 0x7, 0x0 }, // 6068
|
|
{ PseudoVMSLE_VV_MF2_MASK, VMSLE_VV, 0x7, 0x0 }, // 6069
|
|
{ PseudoVMSLE_VX_M1, VMSLE_VX, 0x0, 0x0 }, // 6070
|
|
{ PseudoVMSLE_VX_M1_MASK, VMSLE_VX, 0x0, 0x0 }, // 6071
|
|
{ PseudoVMSLE_VX_M2, VMSLE_VX, 0x1, 0x0 }, // 6072
|
|
{ PseudoVMSLE_VX_M2_MASK, VMSLE_VX, 0x1, 0x0 }, // 6073
|
|
{ PseudoVMSLE_VX_M4, VMSLE_VX, 0x2, 0x0 }, // 6074
|
|
{ PseudoVMSLE_VX_M4_MASK, VMSLE_VX, 0x2, 0x0 }, // 6075
|
|
{ PseudoVMSLE_VX_M8, VMSLE_VX, 0x3, 0x0 }, // 6076
|
|
{ PseudoVMSLE_VX_M8_MASK, VMSLE_VX, 0x3, 0x0 }, // 6077
|
|
{ PseudoVMSLE_VX_MF8, VMSLE_VX, 0x5, 0x0 }, // 6078
|
|
{ PseudoVMSLE_VX_MF8_MASK, VMSLE_VX, 0x5, 0x0 }, // 6079
|
|
{ PseudoVMSLE_VX_MF4, VMSLE_VX, 0x6, 0x0 }, // 6080
|
|
{ PseudoVMSLE_VX_MF4_MASK, VMSLE_VX, 0x6, 0x0 }, // 6081
|
|
{ PseudoVMSLE_VX_MF2, VMSLE_VX, 0x7, 0x0 }, // 6082
|
|
{ PseudoVMSLE_VX_MF2_MASK, VMSLE_VX, 0x7, 0x0 }, // 6083
|
|
{ PseudoVMSLTU_VV_M1, VMSLTU_VV, 0x0, 0x0 }, // 6084
|
|
{ PseudoVMSLTU_VV_M1_MASK, VMSLTU_VV, 0x0, 0x0 }, // 6085
|
|
{ PseudoVMSLTU_VV_M2, VMSLTU_VV, 0x1, 0x0 }, // 6086
|
|
{ PseudoVMSLTU_VV_M2_MASK, VMSLTU_VV, 0x1, 0x0 }, // 6087
|
|
{ PseudoVMSLTU_VV_M4, VMSLTU_VV, 0x2, 0x0 }, // 6088
|
|
{ PseudoVMSLTU_VV_M4_MASK, VMSLTU_VV, 0x2, 0x0 }, // 6089
|
|
{ PseudoVMSLTU_VV_M8, VMSLTU_VV, 0x3, 0x0 }, // 6090
|
|
{ PseudoVMSLTU_VV_M8_MASK, VMSLTU_VV, 0x3, 0x0 }, // 6091
|
|
{ PseudoVMSLTU_VV_MF8, VMSLTU_VV, 0x5, 0x0 }, // 6092
|
|
{ PseudoVMSLTU_VV_MF8_MASK, VMSLTU_VV, 0x5, 0x0 }, // 6093
|
|
{ PseudoVMSLTU_VV_MF4, VMSLTU_VV, 0x6, 0x0 }, // 6094
|
|
{ PseudoVMSLTU_VV_MF4_MASK, VMSLTU_VV, 0x6, 0x0 }, // 6095
|
|
{ PseudoVMSLTU_VV_MF2, VMSLTU_VV, 0x7, 0x0 }, // 6096
|
|
{ PseudoVMSLTU_VV_MF2_MASK, VMSLTU_VV, 0x7, 0x0 }, // 6097
|
|
{ PseudoVMSLTU_VX_M1, VMSLTU_VX, 0x0, 0x0 }, // 6098
|
|
{ PseudoVMSLTU_VX_M1_MASK, VMSLTU_VX, 0x0, 0x0 }, // 6099
|
|
{ PseudoVMSLTU_VX_M2, VMSLTU_VX, 0x1, 0x0 }, // 6100
|
|
{ PseudoVMSLTU_VX_M2_MASK, VMSLTU_VX, 0x1, 0x0 }, // 6101
|
|
{ PseudoVMSLTU_VX_M4, VMSLTU_VX, 0x2, 0x0 }, // 6102
|
|
{ PseudoVMSLTU_VX_M4_MASK, VMSLTU_VX, 0x2, 0x0 }, // 6103
|
|
{ PseudoVMSLTU_VX_M8, VMSLTU_VX, 0x3, 0x0 }, // 6104
|
|
{ PseudoVMSLTU_VX_M8_MASK, VMSLTU_VX, 0x3, 0x0 }, // 6105
|
|
{ PseudoVMSLTU_VX_MF8, VMSLTU_VX, 0x5, 0x0 }, // 6106
|
|
{ PseudoVMSLTU_VX_MF8_MASK, VMSLTU_VX, 0x5, 0x0 }, // 6107
|
|
{ PseudoVMSLTU_VX_MF4, VMSLTU_VX, 0x6, 0x0 }, // 6108
|
|
{ PseudoVMSLTU_VX_MF4_MASK, VMSLTU_VX, 0x6, 0x0 }, // 6109
|
|
{ PseudoVMSLTU_VX_MF2, VMSLTU_VX, 0x7, 0x0 }, // 6110
|
|
{ PseudoVMSLTU_VX_MF2_MASK, VMSLTU_VX, 0x7, 0x0 }, // 6111
|
|
{ PseudoVMSLT_VV_M1, VMSLT_VV, 0x0, 0x0 }, // 6112
|
|
{ PseudoVMSLT_VV_M1_MASK, VMSLT_VV, 0x0, 0x0 }, // 6113
|
|
{ PseudoVMSLT_VV_M2, VMSLT_VV, 0x1, 0x0 }, // 6114
|
|
{ PseudoVMSLT_VV_M2_MASK, VMSLT_VV, 0x1, 0x0 }, // 6115
|
|
{ PseudoVMSLT_VV_M4, VMSLT_VV, 0x2, 0x0 }, // 6116
|
|
{ PseudoVMSLT_VV_M4_MASK, VMSLT_VV, 0x2, 0x0 }, // 6117
|
|
{ PseudoVMSLT_VV_M8, VMSLT_VV, 0x3, 0x0 }, // 6118
|
|
{ PseudoVMSLT_VV_M8_MASK, VMSLT_VV, 0x3, 0x0 }, // 6119
|
|
{ PseudoVMSLT_VV_MF8, VMSLT_VV, 0x5, 0x0 }, // 6120
|
|
{ PseudoVMSLT_VV_MF8_MASK, VMSLT_VV, 0x5, 0x0 }, // 6121
|
|
{ PseudoVMSLT_VV_MF4, VMSLT_VV, 0x6, 0x0 }, // 6122
|
|
{ PseudoVMSLT_VV_MF4_MASK, VMSLT_VV, 0x6, 0x0 }, // 6123
|
|
{ PseudoVMSLT_VV_MF2, VMSLT_VV, 0x7, 0x0 }, // 6124
|
|
{ PseudoVMSLT_VV_MF2_MASK, VMSLT_VV, 0x7, 0x0 }, // 6125
|
|
{ PseudoVMSLT_VX_M1, VMSLT_VX, 0x0, 0x0 }, // 6126
|
|
{ PseudoVMSLT_VX_M1_MASK, VMSLT_VX, 0x0, 0x0 }, // 6127
|
|
{ PseudoVMSLT_VX_M2, VMSLT_VX, 0x1, 0x0 }, // 6128
|
|
{ PseudoVMSLT_VX_M2_MASK, VMSLT_VX, 0x1, 0x0 }, // 6129
|
|
{ PseudoVMSLT_VX_M4, VMSLT_VX, 0x2, 0x0 }, // 6130
|
|
{ PseudoVMSLT_VX_M4_MASK, VMSLT_VX, 0x2, 0x0 }, // 6131
|
|
{ PseudoVMSLT_VX_M8, VMSLT_VX, 0x3, 0x0 }, // 6132
|
|
{ PseudoVMSLT_VX_M8_MASK, VMSLT_VX, 0x3, 0x0 }, // 6133
|
|
{ PseudoVMSLT_VX_MF8, VMSLT_VX, 0x5, 0x0 }, // 6134
|
|
{ PseudoVMSLT_VX_MF8_MASK, VMSLT_VX, 0x5, 0x0 }, // 6135
|
|
{ PseudoVMSLT_VX_MF4, VMSLT_VX, 0x6, 0x0 }, // 6136
|
|
{ PseudoVMSLT_VX_MF4_MASK, VMSLT_VX, 0x6, 0x0 }, // 6137
|
|
{ PseudoVMSLT_VX_MF2, VMSLT_VX, 0x7, 0x0 }, // 6138
|
|
{ PseudoVMSLT_VX_MF2_MASK, VMSLT_VX, 0x7, 0x0 }, // 6139
|
|
{ PseudoVMSNE_VI_M1, VMSNE_VI, 0x0, 0x0 }, // 6140
|
|
{ PseudoVMSNE_VI_M1_MASK, VMSNE_VI, 0x0, 0x0 }, // 6141
|
|
{ PseudoVMSNE_VI_M2, VMSNE_VI, 0x1, 0x0 }, // 6142
|
|
{ PseudoVMSNE_VI_M2_MASK, VMSNE_VI, 0x1, 0x0 }, // 6143
|
|
{ PseudoVMSNE_VI_M4, VMSNE_VI, 0x2, 0x0 }, // 6144
|
|
{ PseudoVMSNE_VI_M4_MASK, VMSNE_VI, 0x2, 0x0 }, // 6145
|
|
{ PseudoVMSNE_VI_M8, VMSNE_VI, 0x3, 0x0 }, // 6146
|
|
{ PseudoVMSNE_VI_M8_MASK, VMSNE_VI, 0x3, 0x0 }, // 6147
|
|
{ PseudoVMSNE_VI_MF8, VMSNE_VI, 0x5, 0x0 }, // 6148
|
|
{ PseudoVMSNE_VI_MF8_MASK, VMSNE_VI, 0x5, 0x0 }, // 6149
|
|
{ PseudoVMSNE_VI_MF4, VMSNE_VI, 0x6, 0x0 }, // 6150
|
|
{ PseudoVMSNE_VI_MF4_MASK, VMSNE_VI, 0x6, 0x0 }, // 6151
|
|
{ PseudoVMSNE_VI_MF2, VMSNE_VI, 0x7, 0x0 }, // 6152
|
|
{ PseudoVMSNE_VI_MF2_MASK, VMSNE_VI, 0x7, 0x0 }, // 6153
|
|
{ PseudoVMSNE_VV_M1, VMSNE_VV, 0x0, 0x0 }, // 6154
|
|
{ PseudoVMSNE_VV_M1_MASK, VMSNE_VV, 0x0, 0x0 }, // 6155
|
|
{ PseudoVMSNE_VV_M2, VMSNE_VV, 0x1, 0x0 }, // 6156
|
|
{ PseudoVMSNE_VV_M2_MASK, VMSNE_VV, 0x1, 0x0 }, // 6157
|
|
{ PseudoVMSNE_VV_M4, VMSNE_VV, 0x2, 0x0 }, // 6158
|
|
{ PseudoVMSNE_VV_M4_MASK, VMSNE_VV, 0x2, 0x0 }, // 6159
|
|
{ PseudoVMSNE_VV_M8, VMSNE_VV, 0x3, 0x0 }, // 6160
|
|
{ PseudoVMSNE_VV_M8_MASK, VMSNE_VV, 0x3, 0x0 }, // 6161
|
|
{ PseudoVMSNE_VV_MF8, VMSNE_VV, 0x5, 0x0 }, // 6162
|
|
{ PseudoVMSNE_VV_MF8_MASK, VMSNE_VV, 0x5, 0x0 }, // 6163
|
|
{ PseudoVMSNE_VV_MF4, VMSNE_VV, 0x6, 0x0 }, // 6164
|
|
{ PseudoVMSNE_VV_MF4_MASK, VMSNE_VV, 0x6, 0x0 }, // 6165
|
|
{ PseudoVMSNE_VV_MF2, VMSNE_VV, 0x7, 0x0 }, // 6166
|
|
{ PseudoVMSNE_VV_MF2_MASK, VMSNE_VV, 0x7, 0x0 }, // 6167
|
|
{ PseudoVMSNE_VX_M1, VMSNE_VX, 0x0, 0x0 }, // 6168
|
|
{ PseudoVMSNE_VX_M1_MASK, VMSNE_VX, 0x0, 0x0 }, // 6169
|
|
{ PseudoVMSNE_VX_M2, VMSNE_VX, 0x1, 0x0 }, // 6170
|
|
{ PseudoVMSNE_VX_M2_MASK, VMSNE_VX, 0x1, 0x0 }, // 6171
|
|
{ PseudoVMSNE_VX_M4, VMSNE_VX, 0x2, 0x0 }, // 6172
|
|
{ PseudoVMSNE_VX_M4_MASK, VMSNE_VX, 0x2, 0x0 }, // 6173
|
|
{ PseudoVMSNE_VX_M8, VMSNE_VX, 0x3, 0x0 }, // 6174
|
|
{ PseudoVMSNE_VX_M8_MASK, VMSNE_VX, 0x3, 0x0 }, // 6175
|
|
{ PseudoVMSNE_VX_MF8, VMSNE_VX, 0x5, 0x0 }, // 6176
|
|
{ PseudoVMSNE_VX_MF8_MASK, VMSNE_VX, 0x5, 0x0 }, // 6177
|
|
{ PseudoVMSNE_VX_MF4, VMSNE_VX, 0x6, 0x0 }, // 6178
|
|
{ PseudoVMSNE_VX_MF4_MASK, VMSNE_VX, 0x6, 0x0 }, // 6179
|
|
{ PseudoVMSNE_VX_MF2, VMSNE_VX, 0x7, 0x0 }, // 6180
|
|
{ PseudoVMSNE_VX_MF2_MASK, VMSNE_VX, 0x7, 0x0 }, // 6181
|
|
{ PseudoVMSOF_M_B8, VMSOF_M, 0x0, 0x0 }, // 6182
|
|
{ PseudoVMSOF_M_B8_MASK, VMSOF_M, 0x0, 0x0 }, // 6183
|
|
{ PseudoVMSOF_M_B16, VMSOF_M, 0x1, 0x0 }, // 6184
|
|
{ PseudoVMSOF_M_B16_MASK, VMSOF_M, 0x1, 0x0 }, // 6185
|
|
{ PseudoVMSOF_M_B32, VMSOF_M, 0x2, 0x0 }, // 6186
|
|
{ PseudoVMSOF_M_B32_MASK, VMSOF_M, 0x2, 0x0 }, // 6187
|
|
{ PseudoVMSOF_M_B64, VMSOF_M, 0x3, 0x0 }, // 6188
|
|
{ PseudoVMSOF_M_B64_MASK, VMSOF_M, 0x3, 0x0 }, // 6189
|
|
{ PseudoVMSOF_M_B1, VMSOF_M, 0x5, 0x0 }, // 6190
|
|
{ PseudoVMSOF_M_B1_MASK, VMSOF_M, 0x5, 0x0 }, // 6191
|
|
{ PseudoVMSOF_M_B2, VMSOF_M, 0x6, 0x0 }, // 6192
|
|
{ PseudoVMSOF_M_B2_MASK, VMSOF_M, 0x6, 0x0 }, // 6193
|
|
{ PseudoVMSOF_M_B4, VMSOF_M, 0x7, 0x0 }, // 6194
|
|
{ PseudoVMSOF_M_B4_MASK, VMSOF_M, 0x7, 0x0 }, // 6195
|
|
{ PseudoVMULHSU_VV_M1, VMULHSU_VV, 0x0, 0x0 }, // 6196
|
|
{ PseudoVMULHSU_VV_M1_MASK, VMULHSU_VV, 0x0, 0x0 }, // 6197
|
|
{ PseudoVMULHSU_VV_M2, VMULHSU_VV, 0x1, 0x0 }, // 6198
|
|
{ PseudoVMULHSU_VV_M2_MASK, VMULHSU_VV, 0x1, 0x0 }, // 6199
|
|
{ PseudoVMULHSU_VV_M4, VMULHSU_VV, 0x2, 0x0 }, // 6200
|
|
{ PseudoVMULHSU_VV_M4_MASK, VMULHSU_VV, 0x2, 0x0 }, // 6201
|
|
{ PseudoVMULHSU_VV_M8, VMULHSU_VV, 0x3, 0x0 }, // 6202
|
|
{ PseudoVMULHSU_VV_M8_MASK, VMULHSU_VV, 0x3, 0x0 }, // 6203
|
|
{ PseudoVMULHSU_VV_MF8, VMULHSU_VV, 0x5, 0x0 }, // 6204
|
|
{ PseudoVMULHSU_VV_MF8_MASK, VMULHSU_VV, 0x5, 0x0 }, // 6205
|
|
{ PseudoVMULHSU_VV_MF4, VMULHSU_VV, 0x6, 0x0 }, // 6206
|
|
{ PseudoVMULHSU_VV_MF4_MASK, VMULHSU_VV, 0x6, 0x0 }, // 6207
|
|
{ PseudoVMULHSU_VV_MF2, VMULHSU_VV, 0x7, 0x0 }, // 6208
|
|
{ PseudoVMULHSU_VV_MF2_MASK, VMULHSU_VV, 0x7, 0x0 }, // 6209
|
|
{ PseudoVMULHSU_VX_M1, VMULHSU_VX, 0x0, 0x0 }, // 6210
|
|
{ PseudoVMULHSU_VX_M1_MASK, VMULHSU_VX, 0x0, 0x0 }, // 6211
|
|
{ PseudoVMULHSU_VX_M2, VMULHSU_VX, 0x1, 0x0 }, // 6212
|
|
{ PseudoVMULHSU_VX_M2_MASK, VMULHSU_VX, 0x1, 0x0 }, // 6213
|
|
{ PseudoVMULHSU_VX_M4, VMULHSU_VX, 0x2, 0x0 }, // 6214
|
|
{ PseudoVMULHSU_VX_M4_MASK, VMULHSU_VX, 0x2, 0x0 }, // 6215
|
|
{ PseudoVMULHSU_VX_M8, VMULHSU_VX, 0x3, 0x0 }, // 6216
|
|
{ PseudoVMULHSU_VX_M8_MASK, VMULHSU_VX, 0x3, 0x0 }, // 6217
|
|
{ PseudoVMULHSU_VX_MF8, VMULHSU_VX, 0x5, 0x0 }, // 6218
|
|
{ PseudoVMULHSU_VX_MF8_MASK, VMULHSU_VX, 0x5, 0x0 }, // 6219
|
|
{ PseudoVMULHSU_VX_MF4, VMULHSU_VX, 0x6, 0x0 }, // 6220
|
|
{ PseudoVMULHSU_VX_MF4_MASK, VMULHSU_VX, 0x6, 0x0 }, // 6221
|
|
{ PseudoVMULHSU_VX_MF2, VMULHSU_VX, 0x7, 0x0 }, // 6222
|
|
{ PseudoVMULHSU_VX_MF2_MASK, VMULHSU_VX, 0x7, 0x0 }, // 6223
|
|
{ PseudoVMULHU_VV_M1, VMULHU_VV, 0x0, 0x0 }, // 6224
|
|
{ PseudoVMULHU_VV_M1_MASK, VMULHU_VV, 0x0, 0x0 }, // 6225
|
|
{ PseudoVMULHU_VV_M2, VMULHU_VV, 0x1, 0x0 }, // 6226
|
|
{ PseudoVMULHU_VV_M2_MASK, VMULHU_VV, 0x1, 0x0 }, // 6227
|
|
{ PseudoVMULHU_VV_M4, VMULHU_VV, 0x2, 0x0 }, // 6228
|
|
{ PseudoVMULHU_VV_M4_MASK, VMULHU_VV, 0x2, 0x0 }, // 6229
|
|
{ PseudoVMULHU_VV_M8, VMULHU_VV, 0x3, 0x0 }, // 6230
|
|
{ PseudoVMULHU_VV_M8_MASK, VMULHU_VV, 0x3, 0x0 }, // 6231
|
|
{ PseudoVMULHU_VV_MF8, VMULHU_VV, 0x5, 0x0 }, // 6232
|
|
{ PseudoVMULHU_VV_MF8_MASK, VMULHU_VV, 0x5, 0x0 }, // 6233
|
|
{ PseudoVMULHU_VV_MF4, VMULHU_VV, 0x6, 0x0 }, // 6234
|
|
{ PseudoVMULHU_VV_MF4_MASK, VMULHU_VV, 0x6, 0x0 }, // 6235
|
|
{ PseudoVMULHU_VV_MF2, VMULHU_VV, 0x7, 0x0 }, // 6236
|
|
{ PseudoVMULHU_VV_MF2_MASK, VMULHU_VV, 0x7, 0x0 }, // 6237
|
|
{ PseudoVMULHU_VX_M1, VMULHU_VX, 0x0, 0x0 }, // 6238
|
|
{ PseudoVMULHU_VX_M1_MASK, VMULHU_VX, 0x0, 0x0 }, // 6239
|
|
{ PseudoVMULHU_VX_M2, VMULHU_VX, 0x1, 0x0 }, // 6240
|
|
{ PseudoVMULHU_VX_M2_MASK, VMULHU_VX, 0x1, 0x0 }, // 6241
|
|
{ PseudoVMULHU_VX_M4, VMULHU_VX, 0x2, 0x0 }, // 6242
|
|
{ PseudoVMULHU_VX_M4_MASK, VMULHU_VX, 0x2, 0x0 }, // 6243
|
|
{ PseudoVMULHU_VX_M8, VMULHU_VX, 0x3, 0x0 }, // 6244
|
|
{ PseudoVMULHU_VX_M8_MASK, VMULHU_VX, 0x3, 0x0 }, // 6245
|
|
{ PseudoVMULHU_VX_MF8, VMULHU_VX, 0x5, 0x0 }, // 6246
|
|
{ PseudoVMULHU_VX_MF8_MASK, VMULHU_VX, 0x5, 0x0 }, // 6247
|
|
{ PseudoVMULHU_VX_MF4, VMULHU_VX, 0x6, 0x0 }, // 6248
|
|
{ PseudoVMULHU_VX_MF4_MASK, VMULHU_VX, 0x6, 0x0 }, // 6249
|
|
{ PseudoVMULHU_VX_MF2, VMULHU_VX, 0x7, 0x0 }, // 6250
|
|
{ PseudoVMULHU_VX_MF2_MASK, VMULHU_VX, 0x7, 0x0 }, // 6251
|
|
{ PseudoVMULH_VV_M1, VMULH_VV, 0x0, 0x0 }, // 6252
|
|
{ PseudoVMULH_VV_M1_MASK, VMULH_VV, 0x0, 0x0 }, // 6253
|
|
{ PseudoVMULH_VV_M2, VMULH_VV, 0x1, 0x0 }, // 6254
|
|
{ PseudoVMULH_VV_M2_MASK, VMULH_VV, 0x1, 0x0 }, // 6255
|
|
{ PseudoVMULH_VV_M4, VMULH_VV, 0x2, 0x0 }, // 6256
|
|
{ PseudoVMULH_VV_M4_MASK, VMULH_VV, 0x2, 0x0 }, // 6257
|
|
{ PseudoVMULH_VV_M8, VMULH_VV, 0x3, 0x0 }, // 6258
|
|
{ PseudoVMULH_VV_M8_MASK, VMULH_VV, 0x3, 0x0 }, // 6259
|
|
{ PseudoVMULH_VV_MF8, VMULH_VV, 0x5, 0x0 }, // 6260
|
|
{ PseudoVMULH_VV_MF8_MASK, VMULH_VV, 0x5, 0x0 }, // 6261
|
|
{ PseudoVMULH_VV_MF4, VMULH_VV, 0x6, 0x0 }, // 6262
|
|
{ PseudoVMULH_VV_MF4_MASK, VMULH_VV, 0x6, 0x0 }, // 6263
|
|
{ PseudoVMULH_VV_MF2, VMULH_VV, 0x7, 0x0 }, // 6264
|
|
{ PseudoVMULH_VV_MF2_MASK, VMULH_VV, 0x7, 0x0 }, // 6265
|
|
{ PseudoVMULH_VX_M1, VMULH_VX, 0x0, 0x0 }, // 6266
|
|
{ PseudoVMULH_VX_M1_MASK, VMULH_VX, 0x0, 0x0 }, // 6267
|
|
{ PseudoVMULH_VX_M2, VMULH_VX, 0x1, 0x0 }, // 6268
|
|
{ PseudoVMULH_VX_M2_MASK, VMULH_VX, 0x1, 0x0 }, // 6269
|
|
{ PseudoVMULH_VX_M4, VMULH_VX, 0x2, 0x0 }, // 6270
|
|
{ PseudoVMULH_VX_M4_MASK, VMULH_VX, 0x2, 0x0 }, // 6271
|
|
{ PseudoVMULH_VX_M8, VMULH_VX, 0x3, 0x0 }, // 6272
|
|
{ PseudoVMULH_VX_M8_MASK, VMULH_VX, 0x3, 0x0 }, // 6273
|
|
{ PseudoVMULH_VX_MF8, VMULH_VX, 0x5, 0x0 }, // 6274
|
|
{ PseudoVMULH_VX_MF8_MASK, VMULH_VX, 0x5, 0x0 }, // 6275
|
|
{ PseudoVMULH_VX_MF4, VMULH_VX, 0x6, 0x0 }, // 6276
|
|
{ PseudoVMULH_VX_MF4_MASK, VMULH_VX, 0x6, 0x0 }, // 6277
|
|
{ PseudoVMULH_VX_MF2, VMULH_VX, 0x7, 0x0 }, // 6278
|
|
{ PseudoVMULH_VX_MF2_MASK, VMULH_VX, 0x7, 0x0 }, // 6279
|
|
{ PseudoVMUL_VV_M1, VMUL_VV, 0x0, 0x0 }, // 6280
|
|
{ PseudoVMUL_VV_M1_MASK, VMUL_VV, 0x0, 0x0 }, // 6281
|
|
{ PseudoVMUL_VV_M2, VMUL_VV, 0x1, 0x0 }, // 6282
|
|
{ PseudoVMUL_VV_M2_MASK, VMUL_VV, 0x1, 0x0 }, // 6283
|
|
{ PseudoVMUL_VV_M4, VMUL_VV, 0x2, 0x0 }, // 6284
|
|
{ PseudoVMUL_VV_M4_MASK, VMUL_VV, 0x2, 0x0 }, // 6285
|
|
{ PseudoVMUL_VV_M8, VMUL_VV, 0x3, 0x0 }, // 6286
|
|
{ PseudoVMUL_VV_M8_MASK, VMUL_VV, 0x3, 0x0 }, // 6287
|
|
{ PseudoVMUL_VV_MF8, VMUL_VV, 0x5, 0x0 }, // 6288
|
|
{ PseudoVMUL_VV_MF8_MASK, VMUL_VV, 0x5, 0x0 }, // 6289
|
|
{ PseudoVMUL_VV_MF4, VMUL_VV, 0x6, 0x0 }, // 6290
|
|
{ PseudoVMUL_VV_MF4_MASK, VMUL_VV, 0x6, 0x0 }, // 6291
|
|
{ PseudoVMUL_VV_MF2, VMUL_VV, 0x7, 0x0 }, // 6292
|
|
{ PseudoVMUL_VV_MF2_MASK, VMUL_VV, 0x7, 0x0 }, // 6293
|
|
{ PseudoVMUL_VX_M1, VMUL_VX, 0x0, 0x0 }, // 6294
|
|
{ PseudoVMUL_VX_M1_MASK, VMUL_VX, 0x0, 0x0 }, // 6295
|
|
{ PseudoVMUL_VX_M2, VMUL_VX, 0x1, 0x0 }, // 6296
|
|
{ PseudoVMUL_VX_M2_MASK, VMUL_VX, 0x1, 0x0 }, // 6297
|
|
{ PseudoVMUL_VX_M4, VMUL_VX, 0x2, 0x0 }, // 6298
|
|
{ PseudoVMUL_VX_M4_MASK, VMUL_VX, 0x2, 0x0 }, // 6299
|
|
{ PseudoVMUL_VX_M8, VMUL_VX, 0x3, 0x0 }, // 6300
|
|
{ PseudoVMUL_VX_M8_MASK, VMUL_VX, 0x3, 0x0 }, // 6301
|
|
{ PseudoVMUL_VX_MF8, VMUL_VX, 0x5, 0x0 }, // 6302
|
|
{ PseudoVMUL_VX_MF8_MASK, VMUL_VX, 0x5, 0x0 }, // 6303
|
|
{ PseudoVMUL_VX_MF4, VMUL_VX, 0x6, 0x0 }, // 6304
|
|
{ PseudoVMUL_VX_MF4_MASK, VMUL_VX, 0x6, 0x0 }, // 6305
|
|
{ PseudoVMUL_VX_MF2, VMUL_VX, 0x7, 0x0 }, // 6306
|
|
{ PseudoVMUL_VX_MF2_MASK, VMUL_VX, 0x7, 0x0 }, // 6307
|
|
{ PseudoVMV_S_X, VMV_S_X, 0x0, 0x0 }, // 6308
|
|
{ PseudoVMV_V_I_M1, VMV_V_I, 0x0, 0x0 }, // 6309
|
|
{ PseudoVMV_V_I_M2, VMV_V_I, 0x1, 0x0 }, // 6310
|
|
{ PseudoVMV_V_I_M4, VMV_V_I, 0x2, 0x0 }, // 6311
|
|
{ PseudoVMV_V_I_M8, VMV_V_I, 0x3, 0x0 }, // 6312
|
|
{ PseudoVMV_V_I_MF8, VMV_V_I, 0x5, 0x0 }, // 6313
|
|
{ PseudoVMV_V_I_MF4, VMV_V_I, 0x6, 0x0 }, // 6314
|
|
{ PseudoVMV_V_I_MF2, VMV_V_I, 0x7, 0x0 }, // 6315
|
|
{ PseudoVMV_V_V_M1, VMV_V_V, 0x0, 0x0 }, // 6316
|
|
{ PseudoVMV_V_V_M2, VMV_V_V, 0x1, 0x0 }, // 6317
|
|
{ PseudoVMV_V_V_M4, VMV_V_V, 0x2, 0x0 }, // 6318
|
|
{ PseudoVMV_V_V_M8, VMV_V_V, 0x3, 0x0 }, // 6319
|
|
{ PseudoVMV_V_V_MF8, VMV_V_V, 0x5, 0x0 }, // 6320
|
|
{ PseudoVMV_V_V_MF4, VMV_V_V, 0x6, 0x0 }, // 6321
|
|
{ PseudoVMV_V_V_MF2, VMV_V_V, 0x7, 0x0 }, // 6322
|
|
{ PseudoVMV_V_X_M1, VMV_V_X, 0x0, 0x0 }, // 6323
|
|
{ PseudoVMV_V_X_M2, VMV_V_X, 0x1, 0x0 }, // 6324
|
|
{ PseudoVMV_V_X_M4, VMV_V_X, 0x2, 0x0 }, // 6325
|
|
{ PseudoVMV_V_X_M8, VMV_V_X, 0x3, 0x0 }, // 6326
|
|
{ PseudoVMV_V_X_MF8, VMV_V_X, 0x5, 0x0 }, // 6327
|
|
{ PseudoVMV_V_X_MF4, VMV_V_X, 0x6, 0x0 }, // 6328
|
|
{ PseudoVMV_V_X_MF2, VMV_V_X, 0x7, 0x0 }, // 6329
|
|
{ PseudoVMV_X_S, VMV_X_S, 0x0, 0x0 }, // 6330
|
|
{ PseudoVMSET_M_B8, VMXNOR_MM, 0x0, 0x0 }, // 6331
|
|
{ PseudoVMXNOR_MM_M1, VMXNOR_MM, 0x0, 0x0 }, // 6332
|
|
{ PseudoVMSET_M_B16, VMXNOR_MM, 0x1, 0x0 }, // 6333
|
|
{ PseudoVMXNOR_MM_M2, VMXNOR_MM, 0x1, 0x0 }, // 6334
|
|
{ PseudoVMSET_M_B32, VMXNOR_MM, 0x2, 0x0 }, // 6335
|
|
{ PseudoVMXNOR_MM_M4, VMXNOR_MM, 0x2, 0x0 }, // 6336
|
|
{ PseudoVMSET_M_B64, VMXNOR_MM, 0x3, 0x0 }, // 6337
|
|
{ PseudoVMXNOR_MM_M8, VMXNOR_MM, 0x3, 0x0 }, // 6338
|
|
{ PseudoVMSET_M_B1, VMXNOR_MM, 0x5, 0x0 }, // 6339
|
|
{ PseudoVMXNOR_MM_MF8, VMXNOR_MM, 0x5, 0x0 }, // 6340
|
|
{ PseudoVMSET_M_B2, VMXNOR_MM, 0x6, 0x0 }, // 6341
|
|
{ PseudoVMXNOR_MM_MF4, VMXNOR_MM, 0x6, 0x0 }, // 6342
|
|
{ PseudoVMSET_M_B4, VMXNOR_MM, 0x7, 0x0 }, // 6343
|
|
{ PseudoVMXNOR_MM_MF2, VMXNOR_MM, 0x7, 0x0 }, // 6344
|
|
{ PseudoVMCLR_M_B8, VMXOR_MM, 0x0, 0x0 }, // 6345
|
|
{ PseudoVMXOR_MM_M1, VMXOR_MM, 0x0, 0x0 }, // 6346
|
|
{ PseudoVMCLR_M_B16, VMXOR_MM, 0x1, 0x0 }, // 6347
|
|
{ PseudoVMXOR_MM_M2, VMXOR_MM, 0x1, 0x0 }, // 6348
|
|
{ PseudoVMCLR_M_B32, VMXOR_MM, 0x2, 0x0 }, // 6349
|
|
{ PseudoVMXOR_MM_M4, VMXOR_MM, 0x2, 0x0 }, // 6350
|
|
{ PseudoVMCLR_M_B64, VMXOR_MM, 0x3, 0x0 }, // 6351
|
|
{ PseudoVMXOR_MM_M8, VMXOR_MM, 0x3, 0x0 }, // 6352
|
|
{ PseudoVMCLR_M_B1, VMXOR_MM, 0x5, 0x0 }, // 6353
|
|
{ PseudoVMXOR_MM_MF8, VMXOR_MM, 0x5, 0x0 }, // 6354
|
|
{ PseudoVMCLR_M_B2, VMXOR_MM, 0x6, 0x0 }, // 6355
|
|
{ PseudoVMXOR_MM_MF4, VMXOR_MM, 0x6, 0x0 }, // 6356
|
|
{ PseudoVMCLR_M_B4, VMXOR_MM, 0x7, 0x0 }, // 6357
|
|
{ PseudoVMXOR_MM_MF2, VMXOR_MM, 0x7, 0x0 }, // 6358
|
|
{ PseudoVNCLIPU_WI_M1, VNCLIPU_WI, 0x0, 0x0 }, // 6359
|
|
{ PseudoVNCLIPU_WI_M1_MASK, VNCLIPU_WI, 0x0, 0x0 }, // 6360
|
|
{ PseudoVNCLIPU_WI_M2, VNCLIPU_WI, 0x1, 0x0 }, // 6361
|
|
{ PseudoVNCLIPU_WI_M2_MASK, VNCLIPU_WI, 0x1, 0x0 }, // 6362
|
|
{ PseudoVNCLIPU_WI_M4, VNCLIPU_WI, 0x2, 0x0 }, // 6363
|
|
{ PseudoVNCLIPU_WI_M4_MASK, VNCLIPU_WI, 0x2, 0x0 }, // 6364
|
|
{ PseudoVNCLIPU_WI_MF8, VNCLIPU_WI, 0x5, 0x0 }, // 6365
|
|
{ PseudoVNCLIPU_WI_MF8_MASK, VNCLIPU_WI, 0x5, 0x0 }, // 6366
|
|
{ PseudoVNCLIPU_WI_MF4, VNCLIPU_WI, 0x6, 0x0 }, // 6367
|
|
{ PseudoVNCLIPU_WI_MF4_MASK, VNCLIPU_WI, 0x6, 0x0 }, // 6368
|
|
{ PseudoVNCLIPU_WI_MF2, VNCLIPU_WI, 0x7, 0x0 }, // 6369
|
|
{ PseudoVNCLIPU_WI_MF2_MASK, VNCLIPU_WI, 0x7, 0x0 }, // 6370
|
|
{ PseudoVNCLIPU_WV_M1, VNCLIPU_WV, 0x0, 0x0 }, // 6371
|
|
{ PseudoVNCLIPU_WV_M1_MASK, VNCLIPU_WV, 0x0, 0x0 }, // 6372
|
|
{ PseudoVNCLIPU_WV_M2, VNCLIPU_WV, 0x1, 0x0 }, // 6373
|
|
{ PseudoVNCLIPU_WV_M2_MASK, VNCLIPU_WV, 0x1, 0x0 }, // 6374
|
|
{ PseudoVNCLIPU_WV_M4, VNCLIPU_WV, 0x2, 0x0 }, // 6375
|
|
{ PseudoVNCLIPU_WV_M4_MASK, VNCLIPU_WV, 0x2, 0x0 }, // 6376
|
|
{ PseudoVNCLIPU_WV_MF8, VNCLIPU_WV, 0x5, 0x0 }, // 6377
|
|
{ PseudoVNCLIPU_WV_MF8_MASK, VNCLIPU_WV, 0x5, 0x0 }, // 6378
|
|
{ PseudoVNCLIPU_WV_MF4, VNCLIPU_WV, 0x6, 0x0 }, // 6379
|
|
{ PseudoVNCLIPU_WV_MF4_MASK, VNCLIPU_WV, 0x6, 0x0 }, // 6380
|
|
{ PseudoVNCLIPU_WV_MF2, VNCLIPU_WV, 0x7, 0x0 }, // 6381
|
|
{ PseudoVNCLIPU_WV_MF2_MASK, VNCLIPU_WV, 0x7, 0x0 }, // 6382
|
|
{ PseudoVNCLIPU_WX_M1, VNCLIPU_WX, 0x0, 0x0 }, // 6383
|
|
{ PseudoVNCLIPU_WX_M1_MASK, VNCLIPU_WX, 0x0, 0x0 }, // 6384
|
|
{ PseudoVNCLIPU_WX_M2, VNCLIPU_WX, 0x1, 0x0 }, // 6385
|
|
{ PseudoVNCLIPU_WX_M2_MASK, VNCLIPU_WX, 0x1, 0x0 }, // 6386
|
|
{ PseudoVNCLIPU_WX_M4, VNCLIPU_WX, 0x2, 0x0 }, // 6387
|
|
{ PseudoVNCLIPU_WX_M4_MASK, VNCLIPU_WX, 0x2, 0x0 }, // 6388
|
|
{ PseudoVNCLIPU_WX_MF8, VNCLIPU_WX, 0x5, 0x0 }, // 6389
|
|
{ PseudoVNCLIPU_WX_MF8_MASK, VNCLIPU_WX, 0x5, 0x0 }, // 6390
|
|
{ PseudoVNCLIPU_WX_MF4, VNCLIPU_WX, 0x6, 0x0 }, // 6391
|
|
{ PseudoVNCLIPU_WX_MF4_MASK, VNCLIPU_WX, 0x6, 0x0 }, // 6392
|
|
{ PseudoVNCLIPU_WX_MF2, VNCLIPU_WX, 0x7, 0x0 }, // 6393
|
|
{ PseudoVNCLIPU_WX_MF2_MASK, VNCLIPU_WX, 0x7, 0x0 }, // 6394
|
|
{ PseudoVNCLIP_WI_M1, VNCLIP_WI, 0x0, 0x0 }, // 6395
|
|
{ PseudoVNCLIP_WI_M1_MASK, VNCLIP_WI, 0x0, 0x0 }, // 6396
|
|
{ PseudoVNCLIP_WI_M2, VNCLIP_WI, 0x1, 0x0 }, // 6397
|
|
{ PseudoVNCLIP_WI_M2_MASK, VNCLIP_WI, 0x1, 0x0 }, // 6398
|
|
{ PseudoVNCLIP_WI_M4, VNCLIP_WI, 0x2, 0x0 }, // 6399
|
|
{ PseudoVNCLIP_WI_M4_MASK, VNCLIP_WI, 0x2, 0x0 }, // 6400
|
|
{ PseudoVNCLIP_WI_MF8, VNCLIP_WI, 0x5, 0x0 }, // 6401
|
|
{ PseudoVNCLIP_WI_MF8_MASK, VNCLIP_WI, 0x5, 0x0 }, // 6402
|
|
{ PseudoVNCLIP_WI_MF4, VNCLIP_WI, 0x6, 0x0 }, // 6403
|
|
{ PseudoVNCLIP_WI_MF4_MASK, VNCLIP_WI, 0x6, 0x0 }, // 6404
|
|
{ PseudoVNCLIP_WI_MF2, VNCLIP_WI, 0x7, 0x0 }, // 6405
|
|
{ PseudoVNCLIP_WI_MF2_MASK, VNCLIP_WI, 0x7, 0x0 }, // 6406
|
|
{ PseudoVNCLIP_WV_M1, VNCLIP_WV, 0x0, 0x0 }, // 6407
|
|
{ PseudoVNCLIP_WV_M1_MASK, VNCLIP_WV, 0x0, 0x0 }, // 6408
|
|
{ PseudoVNCLIP_WV_M2, VNCLIP_WV, 0x1, 0x0 }, // 6409
|
|
{ PseudoVNCLIP_WV_M2_MASK, VNCLIP_WV, 0x1, 0x0 }, // 6410
|
|
{ PseudoVNCLIP_WV_M4, VNCLIP_WV, 0x2, 0x0 }, // 6411
|
|
{ PseudoVNCLIP_WV_M4_MASK, VNCLIP_WV, 0x2, 0x0 }, // 6412
|
|
{ PseudoVNCLIP_WV_MF8, VNCLIP_WV, 0x5, 0x0 }, // 6413
|
|
{ PseudoVNCLIP_WV_MF8_MASK, VNCLIP_WV, 0x5, 0x0 }, // 6414
|
|
{ PseudoVNCLIP_WV_MF4, VNCLIP_WV, 0x6, 0x0 }, // 6415
|
|
{ PseudoVNCLIP_WV_MF4_MASK, VNCLIP_WV, 0x6, 0x0 }, // 6416
|
|
{ PseudoVNCLIP_WV_MF2, VNCLIP_WV, 0x7, 0x0 }, // 6417
|
|
{ PseudoVNCLIP_WV_MF2_MASK, VNCLIP_WV, 0x7, 0x0 }, // 6418
|
|
{ PseudoVNCLIP_WX_M1, VNCLIP_WX, 0x0, 0x0 }, // 6419
|
|
{ PseudoVNCLIP_WX_M1_MASK, VNCLIP_WX, 0x0, 0x0 }, // 6420
|
|
{ PseudoVNCLIP_WX_M2, VNCLIP_WX, 0x1, 0x0 }, // 6421
|
|
{ PseudoVNCLIP_WX_M2_MASK, VNCLIP_WX, 0x1, 0x0 }, // 6422
|
|
{ PseudoVNCLIP_WX_M4, VNCLIP_WX, 0x2, 0x0 }, // 6423
|
|
{ PseudoVNCLIP_WX_M4_MASK, VNCLIP_WX, 0x2, 0x0 }, // 6424
|
|
{ PseudoVNCLIP_WX_MF8, VNCLIP_WX, 0x5, 0x0 }, // 6425
|
|
{ PseudoVNCLIP_WX_MF8_MASK, VNCLIP_WX, 0x5, 0x0 }, // 6426
|
|
{ PseudoVNCLIP_WX_MF4, VNCLIP_WX, 0x6, 0x0 }, // 6427
|
|
{ PseudoVNCLIP_WX_MF4_MASK, VNCLIP_WX, 0x6, 0x0 }, // 6428
|
|
{ PseudoVNCLIP_WX_MF2, VNCLIP_WX, 0x7, 0x0 }, // 6429
|
|
{ PseudoVNCLIP_WX_MF2_MASK, VNCLIP_WX, 0x7, 0x0 }, // 6430
|
|
{ PseudoVNMSAC_VV_M1, VNMSAC_VV, 0x0, 0x0 }, // 6431
|
|
{ PseudoVNMSAC_VV_M1_MASK, VNMSAC_VV, 0x0, 0x0 }, // 6432
|
|
{ PseudoVNMSAC_VV_M2, VNMSAC_VV, 0x1, 0x0 }, // 6433
|
|
{ PseudoVNMSAC_VV_M2_MASK, VNMSAC_VV, 0x1, 0x0 }, // 6434
|
|
{ PseudoVNMSAC_VV_M4, VNMSAC_VV, 0x2, 0x0 }, // 6435
|
|
{ PseudoVNMSAC_VV_M4_MASK, VNMSAC_VV, 0x2, 0x0 }, // 6436
|
|
{ PseudoVNMSAC_VV_M8, VNMSAC_VV, 0x3, 0x0 }, // 6437
|
|
{ PseudoVNMSAC_VV_M8_MASK, VNMSAC_VV, 0x3, 0x0 }, // 6438
|
|
{ PseudoVNMSAC_VV_MF8, VNMSAC_VV, 0x5, 0x0 }, // 6439
|
|
{ PseudoVNMSAC_VV_MF8_MASK, VNMSAC_VV, 0x5, 0x0 }, // 6440
|
|
{ PseudoVNMSAC_VV_MF4, VNMSAC_VV, 0x6, 0x0 }, // 6441
|
|
{ PseudoVNMSAC_VV_MF4_MASK, VNMSAC_VV, 0x6, 0x0 }, // 6442
|
|
{ PseudoVNMSAC_VV_MF2, VNMSAC_VV, 0x7, 0x0 }, // 6443
|
|
{ PseudoVNMSAC_VV_MF2_MASK, VNMSAC_VV, 0x7, 0x0 }, // 6444
|
|
{ PseudoVNMSAC_VX_M1, VNMSAC_VX, 0x0, 0x0 }, // 6445
|
|
{ PseudoVNMSAC_VX_M1_MASK, VNMSAC_VX, 0x0, 0x0 }, // 6446
|
|
{ PseudoVNMSAC_VX_M2, VNMSAC_VX, 0x1, 0x0 }, // 6447
|
|
{ PseudoVNMSAC_VX_M2_MASK, VNMSAC_VX, 0x1, 0x0 }, // 6448
|
|
{ PseudoVNMSAC_VX_M4, VNMSAC_VX, 0x2, 0x0 }, // 6449
|
|
{ PseudoVNMSAC_VX_M4_MASK, VNMSAC_VX, 0x2, 0x0 }, // 6450
|
|
{ PseudoVNMSAC_VX_M8, VNMSAC_VX, 0x3, 0x0 }, // 6451
|
|
{ PseudoVNMSAC_VX_M8_MASK, VNMSAC_VX, 0x3, 0x0 }, // 6452
|
|
{ PseudoVNMSAC_VX_MF8, VNMSAC_VX, 0x5, 0x0 }, // 6453
|
|
{ PseudoVNMSAC_VX_MF8_MASK, VNMSAC_VX, 0x5, 0x0 }, // 6454
|
|
{ PseudoVNMSAC_VX_MF4, VNMSAC_VX, 0x6, 0x0 }, // 6455
|
|
{ PseudoVNMSAC_VX_MF4_MASK, VNMSAC_VX, 0x6, 0x0 }, // 6456
|
|
{ PseudoVNMSAC_VX_MF2, VNMSAC_VX, 0x7, 0x0 }, // 6457
|
|
{ PseudoVNMSAC_VX_MF2_MASK, VNMSAC_VX, 0x7, 0x0 }, // 6458
|
|
{ PseudoVNMSUB_VV_M1, VNMSUB_VV, 0x0, 0x0 }, // 6459
|
|
{ PseudoVNMSUB_VV_M1_MASK, VNMSUB_VV, 0x0, 0x0 }, // 6460
|
|
{ PseudoVNMSUB_VV_M2, VNMSUB_VV, 0x1, 0x0 }, // 6461
|
|
{ PseudoVNMSUB_VV_M2_MASK, VNMSUB_VV, 0x1, 0x0 }, // 6462
|
|
{ PseudoVNMSUB_VV_M4, VNMSUB_VV, 0x2, 0x0 }, // 6463
|
|
{ PseudoVNMSUB_VV_M4_MASK, VNMSUB_VV, 0x2, 0x0 }, // 6464
|
|
{ PseudoVNMSUB_VV_M8, VNMSUB_VV, 0x3, 0x0 }, // 6465
|
|
{ PseudoVNMSUB_VV_M8_MASK, VNMSUB_VV, 0x3, 0x0 }, // 6466
|
|
{ PseudoVNMSUB_VV_MF8, VNMSUB_VV, 0x5, 0x0 }, // 6467
|
|
{ PseudoVNMSUB_VV_MF8_MASK, VNMSUB_VV, 0x5, 0x0 }, // 6468
|
|
{ PseudoVNMSUB_VV_MF4, VNMSUB_VV, 0x6, 0x0 }, // 6469
|
|
{ PseudoVNMSUB_VV_MF4_MASK, VNMSUB_VV, 0x6, 0x0 }, // 6470
|
|
{ PseudoVNMSUB_VV_MF2, VNMSUB_VV, 0x7, 0x0 }, // 6471
|
|
{ PseudoVNMSUB_VV_MF2_MASK, VNMSUB_VV, 0x7, 0x0 }, // 6472
|
|
{ PseudoVNMSUB_VX_M1, VNMSUB_VX, 0x0, 0x0 }, // 6473
|
|
{ PseudoVNMSUB_VX_M1_MASK, VNMSUB_VX, 0x0, 0x0 }, // 6474
|
|
{ PseudoVNMSUB_VX_M2, VNMSUB_VX, 0x1, 0x0 }, // 6475
|
|
{ PseudoVNMSUB_VX_M2_MASK, VNMSUB_VX, 0x1, 0x0 }, // 6476
|
|
{ PseudoVNMSUB_VX_M4, VNMSUB_VX, 0x2, 0x0 }, // 6477
|
|
{ PseudoVNMSUB_VX_M4_MASK, VNMSUB_VX, 0x2, 0x0 }, // 6478
|
|
{ PseudoVNMSUB_VX_M8, VNMSUB_VX, 0x3, 0x0 }, // 6479
|
|
{ PseudoVNMSUB_VX_M8_MASK, VNMSUB_VX, 0x3, 0x0 }, // 6480
|
|
{ PseudoVNMSUB_VX_MF8, VNMSUB_VX, 0x5, 0x0 }, // 6481
|
|
{ PseudoVNMSUB_VX_MF8_MASK, VNMSUB_VX, 0x5, 0x0 }, // 6482
|
|
{ PseudoVNMSUB_VX_MF4, VNMSUB_VX, 0x6, 0x0 }, // 6483
|
|
{ PseudoVNMSUB_VX_MF4_MASK, VNMSUB_VX, 0x6, 0x0 }, // 6484
|
|
{ PseudoVNMSUB_VX_MF2, VNMSUB_VX, 0x7, 0x0 }, // 6485
|
|
{ PseudoVNMSUB_VX_MF2_MASK, VNMSUB_VX, 0x7, 0x0 }, // 6486
|
|
{ PseudoVNSRA_WI_M1, VNSRA_WI, 0x0, 0x0 }, // 6487
|
|
{ PseudoVNSRA_WI_M1_MASK, VNSRA_WI, 0x0, 0x0 }, // 6488
|
|
{ PseudoVNSRA_WI_M2, VNSRA_WI, 0x1, 0x0 }, // 6489
|
|
{ PseudoVNSRA_WI_M2_MASK, VNSRA_WI, 0x1, 0x0 }, // 6490
|
|
{ PseudoVNSRA_WI_M4, VNSRA_WI, 0x2, 0x0 }, // 6491
|
|
{ PseudoVNSRA_WI_M4_MASK, VNSRA_WI, 0x2, 0x0 }, // 6492
|
|
{ PseudoVNSRA_WI_MF8, VNSRA_WI, 0x5, 0x0 }, // 6493
|
|
{ PseudoVNSRA_WI_MF8_MASK, VNSRA_WI, 0x5, 0x0 }, // 6494
|
|
{ PseudoVNSRA_WI_MF4, VNSRA_WI, 0x6, 0x0 }, // 6495
|
|
{ PseudoVNSRA_WI_MF4_MASK, VNSRA_WI, 0x6, 0x0 }, // 6496
|
|
{ PseudoVNSRA_WI_MF2, VNSRA_WI, 0x7, 0x0 }, // 6497
|
|
{ PseudoVNSRA_WI_MF2_MASK, VNSRA_WI, 0x7, 0x0 }, // 6498
|
|
{ PseudoVNSRA_WV_M1, VNSRA_WV, 0x0, 0x0 }, // 6499
|
|
{ PseudoVNSRA_WV_M1_MASK, VNSRA_WV, 0x0, 0x0 }, // 6500
|
|
{ PseudoVNSRA_WV_M2, VNSRA_WV, 0x1, 0x0 }, // 6501
|
|
{ PseudoVNSRA_WV_M2_MASK, VNSRA_WV, 0x1, 0x0 }, // 6502
|
|
{ PseudoVNSRA_WV_M4, VNSRA_WV, 0x2, 0x0 }, // 6503
|
|
{ PseudoVNSRA_WV_M4_MASK, VNSRA_WV, 0x2, 0x0 }, // 6504
|
|
{ PseudoVNSRA_WV_MF8, VNSRA_WV, 0x5, 0x0 }, // 6505
|
|
{ PseudoVNSRA_WV_MF8_MASK, VNSRA_WV, 0x5, 0x0 }, // 6506
|
|
{ PseudoVNSRA_WV_MF4, VNSRA_WV, 0x6, 0x0 }, // 6507
|
|
{ PseudoVNSRA_WV_MF4_MASK, VNSRA_WV, 0x6, 0x0 }, // 6508
|
|
{ PseudoVNSRA_WV_MF2, VNSRA_WV, 0x7, 0x0 }, // 6509
|
|
{ PseudoVNSRA_WV_MF2_MASK, VNSRA_WV, 0x7, 0x0 }, // 6510
|
|
{ PseudoVNSRA_WX_M1, VNSRA_WX, 0x0, 0x0 }, // 6511
|
|
{ PseudoVNSRA_WX_M1_MASK, VNSRA_WX, 0x0, 0x0 }, // 6512
|
|
{ PseudoVNSRA_WX_M2, VNSRA_WX, 0x1, 0x0 }, // 6513
|
|
{ PseudoVNSRA_WX_M2_MASK, VNSRA_WX, 0x1, 0x0 }, // 6514
|
|
{ PseudoVNSRA_WX_M4, VNSRA_WX, 0x2, 0x0 }, // 6515
|
|
{ PseudoVNSRA_WX_M4_MASK, VNSRA_WX, 0x2, 0x0 }, // 6516
|
|
{ PseudoVNSRA_WX_MF8, VNSRA_WX, 0x5, 0x0 }, // 6517
|
|
{ PseudoVNSRA_WX_MF8_MASK, VNSRA_WX, 0x5, 0x0 }, // 6518
|
|
{ PseudoVNSRA_WX_MF4, VNSRA_WX, 0x6, 0x0 }, // 6519
|
|
{ PseudoVNSRA_WX_MF4_MASK, VNSRA_WX, 0x6, 0x0 }, // 6520
|
|
{ PseudoVNSRA_WX_MF2, VNSRA_WX, 0x7, 0x0 }, // 6521
|
|
{ PseudoVNSRA_WX_MF2_MASK, VNSRA_WX, 0x7, 0x0 }, // 6522
|
|
{ PseudoVNSRL_WI_M1, VNSRL_WI, 0x0, 0x0 }, // 6523
|
|
{ PseudoVNSRL_WI_M1_MASK, VNSRL_WI, 0x0, 0x0 }, // 6524
|
|
{ PseudoVNSRL_WI_M2, VNSRL_WI, 0x1, 0x0 }, // 6525
|
|
{ PseudoVNSRL_WI_M2_MASK, VNSRL_WI, 0x1, 0x0 }, // 6526
|
|
{ PseudoVNSRL_WI_M4, VNSRL_WI, 0x2, 0x0 }, // 6527
|
|
{ PseudoVNSRL_WI_M4_MASK, VNSRL_WI, 0x2, 0x0 }, // 6528
|
|
{ PseudoVNSRL_WI_MF8, VNSRL_WI, 0x5, 0x0 }, // 6529
|
|
{ PseudoVNSRL_WI_MF8_MASK, VNSRL_WI, 0x5, 0x0 }, // 6530
|
|
{ PseudoVNSRL_WI_MF4, VNSRL_WI, 0x6, 0x0 }, // 6531
|
|
{ PseudoVNSRL_WI_MF4_MASK, VNSRL_WI, 0x6, 0x0 }, // 6532
|
|
{ PseudoVNSRL_WI_MF2, VNSRL_WI, 0x7, 0x0 }, // 6533
|
|
{ PseudoVNSRL_WI_MF2_MASK, VNSRL_WI, 0x7, 0x0 }, // 6534
|
|
{ PseudoVNSRL_WV_M1, VNSRL_WV, 0x0, 0x0 }, // 6535
|
|
{ PseudoVNSRL_WV_M1_MASK, VNSRL_WV, 0x0, 0x0 }, // 6536
|
|
{ PseudoVNSRL_WV_M2, VNSRL_WV, 0x1, 0x0 }, // 6537
|
|
{ PseudoVNSRL_WV_M2_MASK, VNSRL_WV, 0x1, 0x0 }, // 6538
|
|
{ PseudoVNSRL_WV_M4, VNSRL_WV, 0x2, 0x0 }, // 6539
|
|
{ PseudoVNSRL_WV_M4_MASK, VNSRL_WV, 0x2, 0x0 }, // 6540
|
|
{ PseudoVNSRL_WV_MF8, VNSRL_WV, 0x5, 0x0 }, // 6541
|
|
{ PseudoVNSRL_WV_MF8_MASK, VNSRL_WV, 0x5, 0x0 }, // 6542
|
|
{ PseudoVNSRL_WV_MF4, VNSRL_WV, 0x6, 0x0 }, // 6543
|
|
{ PseudoVNSRL_WV_MF4_MASK, VNSRL_WV, 0x6, 0x0 }, // 6544
|
|
{ PseudoVNSRL_WV_MF2, VNSRL_WV, 0x7, 0x0 }, // 6545
|
|
{ PseudoVNSRL_WV_MF2_MASK, VNSRL_WV, 0x7, 0x0 }, // 6546
|
|
{ PseudoVNSRL_WX_M1, VNSRL_WX, 0x0, 0x0 }, // 6547
|
|
{ PseudoVNSRL_WX_M1_MASK, VNSRL_WX, 0x0, 0x0 }, // 6548
|
|
{ PseudoVNSRL_WX_M2, VNSRL_WX, 0x1, 0x0 }, // 6549
|
|
{ PseudoVNSRL_WX_M2_MASK, VNSRL_WX, 0x1, 0x0 }, // 6550
|
|
{ PseudoVNSRL_WX_M4, VNSRL_WX, 0x2, 0x0 }, // 6551
|
|
{ PseudoVNSRL_WX_M4_MASK, VNSRL_WX, 0x2, 0x0 }, // 6552
|
|
{ PseudoVNSRL_WX_MF8, VNSRL_WX, 0x5, 0x0 }, // 6553
|
|
{ PseudoVNSRL_WX_MF8_MASK, VNSRL_WX, 0x5, 0x0 }, // 6554
|
|
{ PseudoVNSRL_WX_MF4, VNSRL_WX, 0x6, 0x0 }, // 6555
|
|
{ PseudoVNSRL_WX_MF4_MASK, VNSRL_WX, 0x6, 0x0 }, // 6556
|
|
{ PseudoVNSRL_WX_MF2, VNSRL_WX, 0x7, 0x0 }, // 6557
|
|
{ PseudoVNSRL_WX_MF2_MASK, VNSRL_WX, 0x7, 0x0 }, // 6558
|
|
{ PseudoVOR_VI_M1, VOR_VI, 0x0, 0x0 }, // 6559
|
|
{ PseudoVOR_VI_M1_MASK, VOR_VI, 0x0, 0x0 }, // 6560
|
|
{ PseudoVOR_VI_M2, VOR_VI, 0x1, 0x0 }, // 6561
|
|
{ PseudoVOR_VI_M2_MASK, VOR_VI, 0x1, 0x0 }, // 6562
|
|
{ PseudoVOR_VI_M4, VOR_VI, 0x2, 0x0 }, // 6563
|
|
{ PseudoVOR_VI_M4_MASK, VOR_VI, 0x2, 0x0 }, // 6564
|
|
{ PseudoVOR_VI_M8, VOR_VI, 0x3, 0x0 }, // 6565
|
|
{ PseudoVOR_VI_M8_MASK, VOR_VI, 0x3, 0x0 }, // 6566
|
|
{ PseudoVOR_VI_MF8, VOR_VI, 0x5, 0x0 }, // 6567
|
|
{ PseudoVOR_VI_MF8_MASK, VOR_VI, 0x5, 0x0 }, // 6568
|
|
{ PseudoVOR_VI_MF4, VOR_VI, 0x6, 0x0 }, // 6569
|
|
{ PseudoVOR_VI_MF4_MASK, VOR_VI, 0x6, 0x0 }, // 6570
|
|
{ PseudoVOR_VI_MF2, VOR_VI, 0x7, 0x0 }, // 6571
|
|
{ PseudoVOR_VI_MF2_MASK, VOR_VI, 0x7, 0x0 }, // 6572
|
|
{ PseudoVOR_VV_M1, VOR_VV, 0x0, 0x0 }, // 6573
|
|
{ PseudoVOR_VV_M1_MASK, VOR_VV, 0x0, 0x0 }, // 6574
|
|
{ PseudoVOR_VV_M2, VOR_VV, 0x1, 0x0 }, // 6575
|
|
{ PseudoVOR_VV_M2_MASK, VOR_VV, 0x1, 0x0 }, // 6576
|
|
{ PseudoVOR_VV_M4, VOR_VV, 0x2, 0x0 }, // 6577
|
|
{ PseudoVOR_VV_M4_MASK, VOR_VV, 0x2, 0x0 }, // 6578
|
|
{ PseudoVOR_VV_M8, VOR_VV, 0x3, 0x0 }, // 6579
|
|
{ PseudoVOR_VV_M8_MASK, VOR_VV, 0x3, 0x0 }, // 6580
|
|
{ PseudoVOR_VV_MF8, VOR_VV, 0x5, 0x0 }, // 6581
|
|
{ PseudoVOR_VV_MF8_MASK, VOR_VV, 0x5, 0x0 }, // 6582
|
|
{ PseudoVOR_VV_MF4, VOR_VV, 0x6, 0x0 }, // 6583
|
|
{ PseudoVOR_VV_MF4_MASK, VOR_VV, 0x6, 0x0 }, // 6584
|
|
{ PseudoVOR_VV_MF2, VOR_VV, 0x7, 0x0 }, // 6585
|
|
{ PseudoVOR_VV_MF2_MASK, VOR_VV, 0x7, 0x0 }, // 6586
|
|
{ PseudoVOR_VX_M1, VOR_VX, 0x0, 0x0 }, // 6587
|
|
{ PseudoVOR_VX_M1_MASK, VOR_VX, 0x0, 0x0 }, // 6588
|
|
{ PseudoVOR_VX_M2, VOR_VX, 0x1, 0x0 }, // 6589
|
|
{ PseudoVOR_VX_M2_MASK, VOR_VX, 0x1, 0x0 }, // 6590
|
|
{ PseudoVOR_VX_M4, VOR_VX, 0x2, 0x0 }, // 6591
|
|
{ PseudoVOR_VX_M4_MASK, VOR_VX, 0x2, 0x0 }, // 6592
|
|
{ PseudoVOR_VX_M8, VOR_VX, 0x3, 0x0 }, // 6593
|
|
{ PseudoVOR_VX_M8_MASK, VOR_VX, 0x3, 0x0 }, // 6594
|
|
{ PseudoVOR_VX_MF8, VOR_VX, 0x5, 0x0 }, // 6595
|
|
{ PseudoVOR_VX_MF8_MASK, VOR_VX, 0x5, 0x0 }, // 6596
|
|
{ PseudoVOR_VX_MF4, VOR_VX, 0x6, 0x0 }, // 6597
|
|
{ PseudoVOR_VX_MF4_MASK, VOR_VX, 0x6, 0x0 }, // 6598
|
|
{ PseudoVOR_VX_MF2, VOR_VX, 0x7, 0x0 }, // 6599
|
|
{ PseudoVOR_VX_MF2_MASK, VOR_VX, 0x7, 0x0 }, // 6600
|
|
{ PseudoVQMACCSU_2x8x2_M1, VQMACCSU_2x8x2, 0x0, 0x0 }, // 6601
|
|
{ PseudoVQMACCSU_2x8x2_M2, VQMACCSU_2x8x2, 0x1, 0x0 }, // 6602
|
|
{ PseudoVQMACCSU_2x8x2_M4, VQMACCSU_2x8x2, 0x2, 0x0 }, // 6603
|
|
{ PseudoVQMACCSU_2x8x2_M8, VQMACCSU_2x8x2, 0x3, 0x0 }, // 6604
|
|
{ PseudoVQMACCSU_4x8x4_M1, VQMACCSU_4x8x4, 0x0, 0x0 }, // 6605
|
|
{ PseudoVQMACCSU_4x8x4_M2, VQMACCSU_4x8x4, 0x1, 0x0 }, // 6606
|
|
{ PseudoVQMACCSU_4x8x4_M4, VQMACCSU_4x8x4, 0x2, 0x0 }, // 6607
|
|
{ PseudoVQMACCSU_4x8x4_MF2, VQMACCSU_4x8x4, 0x7, 0x0 }, // 6608
|
|
{ PseudoVQMACCUS_2x8x2_M1, VQMACCUS_2x8x2, 0x0, 0x0 }, // 6609
|
|
{ PseudoVQMACCUS_2x8x2_M2, VQMACCUS_2x8x2, 0x1, 0x0 }, // 6610
|
|
{ PseudoVQMACCUS_2x8x2_M4, VQMACCUS_2x8x2, 0x2, 0x0 }, // 6611
|
|
{ PseudoVQMACCUS_2x8x2_M8, VQMACCUS_2x8x2, 0x3, 0x0 }, // 6612
|
|
{ PseudoVQMACCUS_4x8x4_M1, VQMACCUS_4x8x4, 0x0, 0x0 }, // 6613
|
|
{ PseudoVQMACCUS_4x8x4_M2, VQMACCUS_4x8x4, 0x1, 0x0 }, // 6614
|
|
{ PseudoVQMACCUS_4x8x4_M4, VQMACCUS_4x8x4, 0x2, 0x0 }, // 6615
|
|
{ PseudoVQMACCUS_4x8x4_MF2, VQMACCUS_4x8x4, 0x7, 0x0 }, // 6616
|
|
{ PseudoVQMACCU_2x8x2_M1, VQMACCU_2x8x2, 0x0, 0x0 }, // 6617
|
|
{ PseudoVQMACCU_2x8x2_M2, VQMACCU_2x8x2, 0x1, 0x0 }, // 6618
|
|
{ PseudoVQMACCU_2x8x2_M4, VQMACCU_2x8x2, 0x2, 0x0 }, // 6619
|
|
{ PseudoVQMACCU_2x8x2_M8, VQMACCU_2x8x2, 0x3, 0x0 }, // 6620
|
|
{ PseudoVQMACCU_4x8x4_M1, VQMACCU_4x8x4, 0x0, 0x0 }, // 6621
|
|
{ PseudoVQMACCU_4x8x4_M2, VQMACCU_4x8x4, 0x1, 0x0 }, // 6622
|
|
{ PseudoVQMACCU_4x8x4_M4, VQMACCU_4x8x4, 0x2, 0x0 }, // 6623
|
|
{ PseudoVQMACCU_4x8x4_MF2, VQMACCU_4x8x4, 0x7, 0x0 }, // 6624
|
|
{ PseudoVQMACC_2x8x2_M1, VQMACC_2x8x2, 0x0, 0x0 }, // 6625
|
|
{ PseudoVQMACC_2x8x2_M2, VQMACC_2x8x2, 0x1, 0x0 }, // 6626
|
|
{ PseudoVQMACC_2x8x2_M4, VQMACC_2x8x2, 0x2, 0x0 }, // 6627
|
|
{ PseudoVQMACC_2x8x2_M8, VQMACC_2x8x2, 0x3, 0x0 }, // 6628
|
|
{ PseudoVQMACC_4x8x4_M1, VQMACC_4x8x4, 0x0, 0x0 }, // 6629
|
|
{ PseudoVQMACC_4x8x4_M2, VQMACC_4x8x4, 0x1, 0x0 }, // 6630
|
|
{ PseudoVQMACC_4x8x4_M4, VQMACC_4x8x4, 0x2, 0x0 }, // 6631
|
|
{ PseudoVQMACC_4x8x4_MF2, VQMACC_4x8x4, 0x7, 0x0 }, // 6632
|
|
{ PseudoVREDAND_VS_M1_E8, VREDAND_VS, 0x0, 0x8 }, // 6633
|
|
{ PseudoVREDAND_VS_M1_E8_MASK, VREDAND_VS, 0x0, 0x8 }, // 6634
|
|
{ PseudoVREDAND_VS_M1_E16, VREDAND_VS, 0x0, 0x10 }, // 6635
|
|
{ PseudoVREDAND_VS_M1_E16_MASK, VREDAND_VS, 0x0, 0x10 }, // 6636
|
|
{ PseudoVREDAND_VS_M1_E32, VREDAND_VS, 0x0, 0x20 }, // 6637
|
|
{ PseudoVREDAND_VS_M1_E32_MASK, VREDAND_VS, 0x0, 0x20 }, // 6638
|
|
{ PseudoVREDAND_VS_M1_E64, VREDAND_VS, 0x0, 0x40 }, // 6639
|
|
{ PseudoVREDAND_VS_M1_E64_MASK, VREDAND_VS, 0x0, 0x40 }, // 6640
|
|
{ PseudoVREDAND_VS_M2_E8, VREDAND_VS, 0x1, 0x8 }, // 6641
|
|
{ PseudoVREDAND_VS_M2_E8_MASK, VREDAND_VS, 0x1, 0x8 }, // 6642
|
|
{ PseudoVREDAND_VS_M2_E16, VREDAND_VS, 0x1, 0x10 }, // 6643
|
|
{ PseudoVREDAND_VS_M2_E16_MASK, VREDAND_VS, 0x1, 0x10 }, // 6644
|
|
{ PseudoVREDAND_VS_M2_E32, VREDAND_VS, 0x1, 0x20 }, // 6645
|
|
{ PseudoVREDAND_VS_M2_E32_MASK, VREDAND_VS, 0x1, 0x20 }, // 6646
|
|
{ PseudoVREDAND_VS_M2_E64, VREDAND_VS, 0x1, 0x40 }, // 6647
|
|
{ PseudoVREDAND_VS_M2_E64_MASK, VREDAND_VS, 0x1, 0x40 }, // 6648
|
|
{ PseudoVREDAND_VS_M4_E8, VREDAND_VS, 0x2, 0x8 }, // 6649
|
|
{ PseudoVREDAND_VS_M4_E8_MASK, VREDAND_VS, 0x2, 0x8 }, // 6650
|
|
{ PseudoVREDAND_VS_M4_E16, VREDAND_VS, 0x2, 0x10 }, // 6651
|
|
{ PseudoVREDAND_VS_M4_E16_MASK, VREDAND_VS, 0x2, 0x10 }, // 6652
|
|
{ PseudoVREDAND_VS_M4_E32, VREDAND_VS, 0x2, 0x20 }, // 6653
|
|
{ PseudoVREDAND_VS_M4_E32_MASK, VREDAND_VS, 0x2, 0x20 }, // 6654
|
|
{ PseudoVREDAND_VS_M4_E64, VREDAND_VS, 0x2, 0x40 }, // 6655
|
|
{ PseudoVREDAND_VS_M4_E64_MASK, VREDAND_VS, 0x2, 0x40 }, // 6656
|
|
{ PseudoVREDAND_VS_M8_E8, VREDAND_VS, 0x3, 0x8 }, // 6657
|
|
{ PseudoVREDAND_VS_M8_E8_MASK, VREDAND_VS, 0x3, 0x8 }, // 6658
|
|
{ PseudoVREDAND_VS_M8_E16, VREDAND_VS, 0x3, 0x10 }, // 6659
|
|
{ PseudoVREDAND_VS_M8_E16_MASK, VREDAND_VS, 0x3, 0x10 }, // 6660
|
|
{ PseudoVREDAND_VS_M8_E32, VREDAND_VS, 0x3, 0x20 }, // 6661
|
|
{ PseudoVREDAND_VS_M8_E32_MASK, VREDAND_VS, 0x3, 0x20 }, // 6662
|
|
{ PseudoVREDAND_VS_M8_E64, VREDAND_VS, 0x3, 0x40 }, // 6663
|
|
{ PseudoVREDAND_VS_M8_E64_MASK, VREDAND_VS, 0x3, 0x40 }, // 6664
|
|
{ PseudoVREDAND_VS_MF8_E8, VREDAND_VS, 0x5, 0x8 }, // 6665
|
|
{ PseudoVREDAND_VS_MF8_E8_MASK, VREDAND_VS, 0x5, 0x8 }, // 6666
|
|
{ PseudoVREDAND_VS_MF4_E8, VREDAND_VS, 0x6, 0x8 }, // 6667
|
|
{ PseudoVREDAND_VS_MF4_E8_MASK, VREDAND_VS, 0x6, 0x8 }, // 6668
|
|
{ PseudoVREDAND_VS_MF4_E16, VREDAND_VS, 0x6, 0x10 }, // 6669
|
|
{ PseudoVREDAND_VS_MF4_E16_MASK, VREDAND_VS, 0x6, 0x10 }, // 6670
|
|
{ PseudoVREDAND_VS_MF2_E8, VREDAND_VS, 0x7, 0x8 }, // 6671
|
|
{ PseudoVREDAND_VS_MF2_E8_MASK, VREDAND_VS, 0x7, 0x8 }, // 6672
|
|
{ PseudoVREDAND_VS_MF2_E16, VREDAND_VS, 0x7, 0x10 }, // 6673
|
|
{ PseudoVREDAND_VS_MF2_E16_MASK, VREDAND_VS, 0x7, 0x10 }, // 6674
|
|
{ PseudoVREDAND_VS_MF2_E32, VREDAND_VS, 0x7, 0x20 }, // 6675
|
|
{ PseudoVREDAND_VS_MF2_E32_MASK, VREDAND_VS, 0x7, 0x20 }, // 6676
|
|
{ PseudoVREDMAXU_VS_M1_E8, VREDMAXU_VS, 0x0, 0x8 }, // 6677
|
|
{ PseudoVREDMAXU_VS_M1_E8_MASK, VREDMAXU_VS, 0x0, 0x8 }, // 6678
|
|
{ PseudoVREDMAXU_VS_M1_E16, VREDMAXU_VS, 0x0, 0x10 }, // 6679
|
|
{ PseudoVREDMAXU_VS_M1_E16_MASK, VREDMAXU_VS, 0x0, 0x10 }, // 6680
|
|
{ PseudoVREDMAXU_VS_M1_E32, VREDMAXU_VS, 0x0, 0x20 }, // 6681
|
|
{ PseudoVREDMAXU_VS_M1_E32_MASK, VREDMAXU_VS, 0x0, 0x20 }, // 6682
|
|
{ PseudoVREDMAXU_VS_M1_E64, VREDMAXU_VS, 0x0, 0x40 }, // 6683
|
|
{ PseudoVREDMAXU_VS_M1_E64_MASK, VREDMAXU_VS, 0x0, 0x40 }, // 6684
|
|
{ PseudoVREDMAXU_VS_M2_E8, VREDMAXU_VS, 0x1, 0x8 }, // 6685
|
|
{ PseudoVREDMAXU_VS_M2_E8_MASK, VREDMAXU_VS, 0x1, 0x8 }, // 6686
|
|
{ PseudoVREDMAXU_VS_M2_E16, VREDMAXU_VS, 0x1, 0x10 }, // 6687
|
|
{ PseudoVREDMAXU_VS_M2_E16_MASK, VREDMAXU_VS, 0x1, 0x10 }, // 6688
|
|
{ PseudoVREDMAXU_VS_M2_E32, VREDMAXU_VS, 0x1, 0x20 }, // 6689
|
|
{ PseudoVREDMAXU_VS_M2_E32_MASK, VREDMAXU_VS, 0x1, 0x20 }, // 6690
|
|
{ PseudoVREDMAXU_VS_M2_E64, VREDMAXU_VS, 0x1, 0x40 }, // 6691
|
|
{ PseudoVREDMAXU_VS_M2_E64_MASK, VREDMAXU_VS, 0x1, 0x40 }, // 6692
|
|
{ PseudoVREDMAXU_VS_M4_E8, VREDMAXU_VS, 0x2, 0x8 }, // 6693
|
|
{ PseudoVREDMAXU_VS_M4_E8_MASK, VREDMAXU_VS, 0x2, 0x8 }, // 6694
|
|
{ PseudoVREDMAXU_VS_M4_E16, VREDMAXU_VS, 0x2, 0x10 }, // 6695
|
|
{ PseudoVREDMAXU_VS_M4_E16_MASK, VREDMAXU_VS, 0x2, 0x10 }, // 6696
|
|
{ PseudoVREDMAXU_VS_M4_E32, VREDMAXU_VS, 0x2, 0x20 }, // 6697
|
|
{ PseudoVREDMAXU_VS_M4_E32_MASK, VREDMAXU_VS, 0x2, 0x20 }, // 6698
|
|
{ PseudoVREDMAXU_VS_M4_E64, VREDMAXU_VS, 0x2, 0x40 }, // 6699
|
|
{ PseudoVREDMAXU_VS_M4_E64_MASK, VREDMAXU_VS, 0x2, 0x40 }, // 6700
|
|
{ PseudoVREDMAXU_VS_M8_E8, VREDMAXU_VS, 0x3, 0x8 }, // 6701
|
|
{ PseudoVREDMAXU_VS_M8_E8_MASK, VREDMAXU_VS, 0x3, 0x8 }, // 6702
|
|
{ PseudoVREDMAXU_VS_M8_E16, VREDMAXU_VS, 0x3, 0x10 }, // 6703
|
|
{ PseudoVREDMAXU_VS_M8_E16_MASK, VREDMAXU_VS, 0x3, 0x10 }, // 6704
|
|
{ PseudoVREDMAXU_VS_M8_E32, VREDMAXU_VS, 0x3, 0x20 }, // 6705
|
|
{ PseudoVREDMAXU_VS_M8_E32_MASK, VREDMAXU_VS, 0x3, 0x20 }, // 6706
|
|
{ PseudoVREDMAXU_VS_M8_E64, VREDMAXU_VS, 0x3, 0x40 }, // 6707
|
|
{ PseudoVREDMAXU_VS_M8_E64_MASK, VREDMAXU_VS, 0x3, 0x40 }, // 6708
|
|
{ PseudoVREDMAXU_VS_MF8_E8, VREDMAXU_VS, 0x5, 0x8 }, // 6709
|
|
{ PseudoVREDMAXU_VS_MF8_E8_MASK, VREDMAXU_VS, 0x5, 0x8 }, // 6710
|
|
{ PseudoVREDMAXU_VS_MF4_E8, VREDMAXU_VS, 0x6, 0x8 }, // 6711
|
|
{ PseudoVREDMAXU_VS_MF4_E8_MASK, VREDMAXU_VS, 0x6, 0x8 }, // 6712
|
|
{ PseudoVREDMAXU_VS_MF4_E16, VREDMAXU_VS, 0x6, 0x10 }, // 6713
|
|
{ PseudoVREDMAXU_VS_MF4_E16_MASK, VREDMAXU_VS, 0x6, 0x10 }, // 6714
|
|
{ PseudoVREDMAXU_VS_MF2_E8, VREDMAXU_VS, 0x7, 0x8 }, // 6715
|
|
{ PseudoVREDMAXU_VS_MF2_E8_MASK, VREDMAXU_VS, 0x7, 0x8 }, // 6716
|
|
{ PseudoVREDMAXU_VS_MF2_E16, VREDMAXU_VS, 0x7, 0x10 }, // 6717
|
|
{ PseudoVREDMAXU_VS_MF2_E16_MASK, VREDMAXU_VS, 0x7, 0x10 }, // 6718
|
|
{ PseudoVREDMAXU_VS_MF2_E32, VREDMAXU_VS, 0x7, 0x20 }, // 6719
|
|
{ PseudoVREDMAXU_VS_MF2_E32_MASK, VREDMAXU_VS, 0x7, 0x20 }, // 6720
|
|
{ PseudoVREDMAX_VS_M1_E8, VREDMAX_VS, 0x0, 0x8 }, // 6721
|
|
{ PseudoVREDMAX_VS_M1_E8_MASK, VREDMAX_VS, 0x0, 0x8 }, // 6722
|
|
{ PseudoVREDMAX_VS_M1_E16, VREDMAX_VS, 0x0, 0x10 }, // 6723
|
|
{ PseudoVREDMAX_VS_M1_E16_MASK, VREDMAX_VS, 0x0, 0x10 }, // 6724
|
|
{ PseudoVREDMAX_VS_M1_E32, VREDMAX_VS, 0x0, 0x20 }, // 6725
|
|
{ PseudoVREDMAX_VS_M1_E32_MASK, VREDMAX_VS, 0x0, 0x20 }, // 6726
|
|
{ PseudoVREDMAX_VS_M1_E64, VREDMAX_VS, 0x0, 0x40 }, // 6727
|
|
{ PseudoVREDMAX_VS_M1_E64_MASK, VREDMAX_VS, 0x0, 0x40 }, // 6728
|
|
{ PseudoVREDMAX_VS_M2_E8, VREDMAX_VS, 0x1, 0x8 }, // 6729
|
|
{ PseudoVREDMAX_VS_M2_E8_MASK, VREDMAX_VS, 0x1, 0x8 }, // 6730
|
|
{ PseudoVREDMAX_VS_M2_E16, VREDMAX_VS, 0x1, 0x10 }, // 6731
|
|
{ PseudoVREDMAX_VS_M2_E16_MASK, VREDMAX_VS, 0x1, 0x10 }, // 6732
|
|
{ PseudoVREDMAX_VS_M2_E32, VREDMAX_VS, 0x1, 0x20 }, // 6733
|
|
{ PseudoVREDMAX_VS_M2_E32_MASK, VREDMAX_VS, 0x1, 0x20 }, // 6734
|
|
{ PseudoVREDMAX_VS_M2_E64, VREDMAX_VS, 0x1, 0x40 }, // 6735
|
|
{ PseudoVREDMAX_VS_M2_E64_MASK, VREDMAX_VS, 0x1, 0x40 }, // 6736
|
|
{ PseudoVREDMAX_VS_M4_E8, VREDMAX_VS, 0x2, 0x8 }, // 6737
|
|
{ PseudoVREDMAX_VS_M4_E8_MASK, VREDMAX_VS, 0x2, 0x8 }, // 6738
|
|
{ PseudoVREDMAX_VS_M4_E16, VREDMAX_VS, 0x2, 0x10 }, // 6739
|
|
{ PseudoVREDMAX_VS_M4_E16_MASK, VREDMAX_VS, 0x2, 0x10 }, // 6740
|
|
{ PseudoVREDMAX_VS_M4_E32, VREDMAX_VS, 0x2, 0x20 }, // 6741
|
|
{ PseudoVREDMAX_VS_M4_E32_MASK, VREDMAX_VS, 0x2, 0x20 }, // 6742
|
|
{ PseudoVREDMAX_VS_M4_E64, VREDMAX_VS, 0x2, 0x40 }, // 6743
|
|
{ PseudoVREDMAX_VS_M4_E64_MASK, VREDMAX_VS, 0x2, 0x40 }, // 6744
|
|
{ PseudoVREDMAX_VS_M8_E8, VREDMAX_VS, 0x3, 0x8 }, // 6745
|
|
{ PseudoVREDMAX_VS_M8_E8_MASK, VREDMAX_VS, 0x3, 0x8 }, // 6746
|
|
{ PseudoVREDMAX_VS_M8_E16, VREDMAX_VS, 0x3, 0x10 }, // 6747
|
|
{ PseudoVREDMAX_VS_M8_E16_MASK, VREDMAX_VS, 0x3, 0x10 }, // 6748
|
|
{ PseudoVREDMAX_VS_M8_E32, VREDMAX_VS, 0x3, 0x20 }, // 6749
|
|
{ PseudoVREDMAX_VS_M8_E32_MASK, VREDMAX_VS, 0x3, 0x20 }, // 6750
|
|
{ PseudoVREDMAX_VS_M8_E64, VREDMAX_VS, 0x3, 0x40 }, // 6751
|
|
{ PseudoVREDMAX_VS_M8_E64_MASK, VREDMAX_VS, 0x3, 0x40 }, // 6752
|
|
{ PseudoVREDMAX_VS_MF8_E8, VREDMAX_VS, 0x5, 0x8 }, // 6753
|
|
{ PseudoVREDMAX_VS_MF8_E8_MASK, VREDMAX_VS, 0x5, 0x8 }, // 6754
|
|
{ PseudoVREDMAX_VS_MF4_E8, VREDMAX_VS, 0x6, 0x8 }, // 6755
|
|
{ PseudoVREDMAX_VS_MF4_E8_MASK, VREDMAX_VS, 0x6, 0x8 }, // 6756
|
|
{ PseudoVREDMAX_VS_MF4_E16, VREDMAX_VS, 0x6, 0x10 }, // 6757
|
|
{ PseudoVREDMAX_VS_MF4_E16_MASK, VREDMAX_VS, 0x6, 0x10 }, // 6758
|
|
{ PseudoVREDMAX_VS_MF2_E8, VREDMAX_VS, 0x7, 0x8 }, // 6759
|
|
{ PseudoVREDMAX_VS_MF2_E8_MASK, VREDMAX_VS, 0x7, 0x8 }, // 6760
|
|
{ PseudoVREDMAX_VS_MF2_E16, VREDMAX_VS, 0x7, 0x10 }, // 6761
|
|
{ PseudoVREDMAX_VS_MF2_E16_MASK, VREDMAX_VS, 0x7, 0x10 }, // 6762
|
|
{ PseudoVREDMAX_VS_MF2_E32, VREDMAX_VS, 0x7, 0x20 }, // 6763
|
|
{ PseudoVREDMAX_VS_MF2_E32_MASK, VREDMAX_VS, 0x7, 0x20 }, // 6764
|
|
{ PseudoVREDMINU_VS_M1_E8, VREDMINU_VS, 0x0, 0x8 }, // 6765
|
|
{ PseudoVREDMINU_VS_M1_E8_MASK, VREDMINU_VS, 0x0, 0x8 }, // 6766
|
|
{ PseudoVREDMINU_VS_M1_E16, VREDMINU_VS, 0x0, 0x10 }, // 6767
|
|
{ PseudoVREDMINU_VS_M1_E16_MASK, VREDMINU_VS, 0x0, 0x10 }, // 6768
|
|
{ PseudoVREDMINU_VS_M1_E32, VREDMINU_VS, 0x0, 0x20 }, // 6769
|
|
{ PseudoVREDMINU_VS_M1_E32_MASK, VREDMINU_VS, 0x0, 0x20 }, // 6770
|
|
{ PseudoVREDMINU_VS_M1_E64, VREDMINU_VS, 0x0, 0x40 }, // 6771
|
|
{ PseudoVREDMINU_VS_M1_E64_MASK, VREDMINU_VS, 0x0, 0x40 }, // 6772
|
|
{ PseudoVREDMINU_VS_M2_E8, VREDMINU_VS, 0x1, 0x8 }, // 6773
|
|
{ PseudoVREDMINU_VS_M2_E8_MASK, VREDMINU_VS, 0x1, 0x8 }, // 6774
|
|
{ PseudoVREDMINU_VS_M2_E16, VREDMINU_VS, 0x1, 0x10 }, // 6775
|
|
{ PseudoVREDMINU_VS_M2_E16_MASK, VREDMINU_VS, 0x1, 0x10 }, // 6776
|
|
{ PseudoVREDMINU_VS_M2_E32, VREDMINU_VS, 0x1, 0x20 }, // 6777
|
|
{ PseudoVREDMINU_VS_M2_E32_MASK, VREDMINU_VS, 0x1, 0x20 }, // 6778
|
|
{ PseudoVREDMINU_VS_M2_E64, VREDMINU_VS, 0x1, 0x40 }, // 6779
|
|
{ PseudoVREDMINU_VS_M2_E64_MASK, VREDMINU_VS, 0x1, 0x40 }, // 6780
|
|
{ PseudoVREDMINU_VS_M4_E8, VREDMINU_VS, 0x2, 0x8 }, // 6781
|
|
{ PseudoVREDMINU_VS_M4_E8_MASK, VREDMINU_VS, 0x2, 0x8 }, // 6782
|
|
{ PseudoVREDMINU_VS_M4_E16, VREDMINU_VS, 0x2, 0x10 }, // 6783
|
|
{ PseudoVREDMINU_VS_M4_E16_MASK, VREDMINU_VS, 0x2, 0x10 }, // 6784
|
|
{ PseudoVREDMINU_VS_M4_E32, VREDMINU_VS, 0x2, 0x20 }, // 6785
|
|
{ PseudoVREDMINU_VS_M4_E32_MASK, VREDMINU_VS, 0x2, 0x20 }, // 6786
|
|
{ PseudoVREDMINU_VS_M4_E64, VREDMINU_VS, 0x2, 0x40 }, // 6787
|
|
{ PseudoVREDMINU_VS_M4_E64_MASK, VREDMINU_VS, 0x2, 0x40 }, // 6788
|
|
{ PseudoVREDMINU_VS_M8_E8, VREDMINU_VS, 0x3, 0x8 }, // 6789
|
|
{ PseudoVREDMINU_VS_M8_E8_MASK, VREDMINU_VS, 0x3, 0x8 }, // 6790
|
|
{ PseudoVREDMINU_VS_M8_E16, VREDMINU_VS, 0x3, 0x10 }, // 6791
|
|
{ PseudoVREDMINU_VS_M8_E16_MASK, VREDMINU_VS, 0x3, 0x10 }, // 6792
|
|
{ PseudoVREDMINU_VS_M8_E32, VREDMINU_VS, 0x3, 0x20 }, // 6793
|
|
{ PseudoVREDMINU_VS_M8_E32_MASK, VREDMINU_VS, 0x3, 0x20 }, // 6794
|
|
{ PseudoVREDMINU_VS_M8_E64, VREDMINU_VS, 0x3, 0x40 }, // 6795
|
|
{ PseudoVREDMINU_VS_M8_E64_MASK, VREDMINU_VS, 0x3, 0x40 }, // 6796
|
|
{ PseudoVREDMINU_VS_MF8_E8, VREDMINU_VS, 0x5, 0x8 }, // 6797
|
|
{ PseudoVREDMINU_VS_MF8_E8_MASK, VREDMINU_VS, 0x5, 0x8 }, // 6798
|
|
{ PseudoVREDMINU_VS_MF4_E8, VREDMINU_VS, 0x6, 0x8 }, // 6799
|
|
{ PseudoVREDMINU_VS_MF4_E8_MASK, VREDMINU_VS, 0x6, 0x8 }, // 6800
|
|
{ PseudoVREDMINU_VS_MF4_E16, VREDMINU_VS, 0x6, 0x10 }, // 6801
|
|
{ PseudoVREDMINU_VS_MF4_E16_MASK, VREDMINU_VS, 0x6, 0x10 }, // 6802
|
|
{ PseudoVREDMINU_VS_MF2_E8, VREDMINU_VS, 0x7, 0x8 }, // 6803
|
|
{ PseudoVREDMINU_VS_MF2_E8_MASK, VREDMINU_VS, 0x7, 0x8 }, // 6804
|
|
{ PseudoVREDMINU_VS_MF2_E16, VREDMINU_VS, 0x7, 0x10 }, // 6805
|
|
{ PseudoVREDMINU_VS_MF2_E16_MASK, VREDMINU_VS, 0x7, 0x10 }, // 6806
|
|
{ PseudoVREDMINU_VS_MF2_E32, VREDMINU_VS, 0x7, 0x20 }, // 6807
|
|
{ PseudoVREDMINU_VS_MF2_E32_MASK, VREDMINU_VS, 0x7, 0x20 }, // 6808
|
|
{ PseudoVREDMIN_VS_M1_E8, VREDMIN_VS, 0x0, 0x8 }, // 6809
|
|
{ PseudoVREDMIN_VS_M1_E8_MASK, VREDMIN_VS, 0x0, 0x8 }, // 6810
|
|
{ PseudoVREDMIN_VS_M1_E16, VREDMIN_VS, 0x0, 0x10 }, // 6811
|
|
{ PseudoVREDMIN_VS_M1_E16_MASK, VREDMIN_VS, 0x0, 0x10 }, // 6812
|
|
{ PseudoVREDMIN_VS_M1_E32, VREDMIN_VS, 0x0, 0x20 }, // 6813
|
|
{ PseudoVREDMIN_VS_M1_E32_MASK, VREDMIN_VS, 0x0, 0x20 }, // 6814
|
|
{ PseudoVREDMIN_VS_M1_E64, VREDMIN_VS, 0x0, 0x40 }, // 6815
|
|
{ PseudoVREDMIN_VS_M1_E64_MASK, VREDMIN_VS, 0x0, 0x40 }, // 6816
|
|
{ PseudoVREDMIN_VS_M2_E8, VREDMIN_VS, 0x1, 0x8 }, // 6817
|
|
{ PseudoVREDMIN_VS_M2_E8_MASK, VREDMIN_VS, 0x1, 0x8 }, // 6818
|
|
{ PseudoVREDMIN_VS_M2_E16, VREDMIN_VS, 0x1, 0x10 }, // 6819
|
|
{ PseudoVREDMIN_VS_M2_E16_MASK, VREDMIN_VS, 0x1, 0x10 }, // 6820
|
|
{ PseudoVREDMIN_VS_M2_E32, VREDMIN_VS, 0x1, 0x20 }, // 6821
|
|
{ PseudoVREDMIN_VS_M2_E32_MASK, VREDMIN_VS, 0x1, 0x20 }, // 6822
|
|
{ PseudoVREDMIN_VS_M2_E64, VREDMIN_VS, 0x1, 0x40 }, // 6823
|
|
{ PseudoVREDMIN_VS_M2_E64_MASK, VREDMIN_VS, 0x1, 0x40 }, // 6824
|
|
{ PseudoVREDMIN_VS_M4_E8, VREDMIN_VS, 0x2, 0x8 }, // 6825
|
|
{ PseudoVREDMIN_VS_M4_E8_MASK, VREDMIN_VS, 0x2, 0x8 }, // 6826
|
|
{ PseudoVREDMIN_VS_M4_E16, VREDMIN_VS, 0x2, 0x10 }, // 6827
|
|
{ PseudoVREDMIN_VS_M4_E16_MASK, VREDMIN_VS, 0x2, 0x10 }, // 6828
|
|
{ PseudoVREDMIN_VS_M4_E32, VREDMIN_VS, 0x2, 0x20 }, // 6829
|
|
{ PseudoVREDMIN_VS_M4_E32_MASK, VREDMIN_VS, 0x2, 0x20 }, // 6830
|
|
{ PseudoVREDMIN_VS_M4_E64, VREDMIN_VS, 0x2, 0x40 }, // 6831
|
|
{ PseudoVREDMIN_VS_M4_E64_MASK, VREDMIN_VS, 0x2, 0x40 }, // 6832
|
|
{ PseudoVREDMIN_VS_M8_E8, VREDMIN_VS, 0x3, 0x8 }, // 6833
|
|
{ PseudoVREDMIN_VS_M8_E8_MASK, VREDMIN_VS, 0x3, 0x8 }, // 6834
|
|
{ PseudoVREDMIN_VS_M8_E16, VREDMIN_VS, 0x3, 0x10 }, // 6835
|
|
{ PseudoVREDMIN_VS_M8_E16_MASK, VREDMIN_VS, 0x3, 0x10 }, // 6836
|
|
{ PseudoVREDMIN_VS_M8_E32, VREDMIN_VS, 0x3, 0x20 }, // 6837
|
|
{ PseudoVREDMIN_VS_M8_E32_MASK, VREDMIN_VS, 0x3, 0x20 }, // 6838
|
|
{ PseudoVREDMIN_VS_M8_E64, VREDMIN_VS, 0x3, 0x40 }, // 6839
|
|
{ PseudoVREDMIN_VS_M8_E64_MASK, VREDMIN_VS, 0x3, 0x40 }, // 6840
|
|
{ PseudoVREDMIN_VS_MF8_E8, VREDMIN_VS, 0x5, 0x8 }, // 6841
|
|
{ PseudoVREDMIN_VS_MF8_E8_MASK, VREDMIN_VS, 0x5, 0x8 }, // 6842
|
|
{ PseudoVREDMIN_VS_MF4_E8, VREDMIN_VS, 0x6, 0x8 }, // 6843
|
|
{ PseudoVREDMIN_VS_MF4_E8_MASK, VREDMIN_VS, 0x6, 0x8 }, // 6844
|
|
{ PseudoVREDMIN_VS_MF4_E16, VREDMIN_VS, 0x6, 0x10 }, // 6845
|
|
{ PseudoVREDMIN_VS_MF4_E16_MASK, VREDMIN_VS, 0x6, 0x10 }, // 6846
|
|
{ PseudoVREDMIN_VS_MF2_E8, VREDMIN_VS, 0x7, 0x8 }, // 6847
|
|
{ PseudoVREDMIN_VS_MF2_E8_MASK, VREDMIN_VS, 0x7, 0x8 }, // 6848
|
|
{ PseudoVREDMIN_VS_MF2_E16, VREDMIN_VS, 0x7, 0x10 }, // 6849
|
|
{ PseudoVREDMIN_VS_MF2_E16_MASK, VREDMIN_VS, 0x7, 0x10 }, // 6850
|
|
{ PseudoVREDMIN_VS_MF2_E32, VREDMIN_VS, 0x7, 0x20 }, // 6851
|
|
{ PseudoVREDMIN_VS_MF2_E32_MASK, VREDMIN_VS, 0x7, 0x20 }, // 6852
|
|
{ PseudoVREDOR_VS_M1_E8, VREDOR_VS, 0x0, 0x8 }, // 6853
|
|
{ PseudoVREDOR_VS_M1_E8_MASK, VREDOR_VS, 0x0, 0x8 }, // 6854
|
|
{ PseudoVREDOR_VS_M1_E16, VREDOR_VS, 0x0, 0x10 }, // 6855
|
|
{ PseudoVREDOR_VS_M1_E16_MASK, VREDOR_VS, 0x0, 0x10 }, // 6856
|
|
{ PseudoVREDOR_VS_M1_E32, VREDOR_VS, 0x0, 0x20 }, // 6857
|
|
{ PseudoVREDOR_VS_M1_E32_MASK, VREDOR_VS, 0x0, 0x20 }, // 6858
|
|
{ PseudoVREDOR_VS_M1_E64, VREDOR_VS, 0x0, 0x40 }, // 6859
|
|
{ PseudoVREDOR_VS_M1_E64_MASK, VREDOR_VS, 0x0, 0x40 }, // 6860
|
|
{ PseudoVREDOR_VS_M2_E8, VREDOR_VS, 0x1, 0x8 }, // 6861
|
|
{ PseudoVREDOR_VS_M2_E8_MASK, VREDOR_VS, 0x1, 0x8 }, // 6862
|
|
{ PseudoVREDOR_VS_M2_E16, VREDOR_VS, 0x1, 0x10 }, // 6863
|
|
{ PseudoVREDOR_VS_M2_E16_MASK, VREDOR_VS, 0x1, 0x10 }, // 6864
|
|
{ PseudoVREDOR_VS_M2_E32, VREDOR_VS, 0x1, 0x20 }, // 6865
|
|
{ PseudoVREDOR_VS_M2_E32_MASK, VREDOR_VS, 0x1, 0x20 }, // 6866
|
|
{ PseudoVREDOR_VS_M2_E64, VREDOR_VS, 0x1, 0x40 }, // 6867
|
|
{ PseudoVREDOR_VS_M2_E64_MASK, VREDOR_VS, 0x1, 0x40 }, // 6868
|
|
{ PseudoVREDOR_VS_M4_E8, VREDOR_VS, 0x2, 0x8 }, // 6869
|
|
{ PseudoVREDOR_VS_M4_E8_MASK, VREDOR_VS, 0x2, 0x8 }, // 6870
|
|
{ PseudoVREDOR_VS_M4_E16, VREDOR_VS, 0x2, 0x10 }, // 6871
|
|
{ PseudoVREDOR_VS_M4_E16_MASK, VREDOR_VS, 0x2, 0x10 }, // 6872
|
|
{ PseudoVREDOR_VS_M4_E32, VREDOR_VS, 0x2, 0x20 }, // 6873
|
|
{ PseudoVREDOR_VS_M4_E32_MASK, VREDOR_VS, 0x2, 0x20 }, // 6874
|
|
{ PseudoVREDOR_VS_M4_E64, VREDOR_VS, 0x2, 0x40 }, // 6875
|
|
{ PseudoVREDOR_VS_M4_E64_MASK, VREDOR_VS, 0x2, 0x40 }, // 6876
|
|
{ PseudoVREDOR_VS_M8_E8, VREDOR_VS, 0x3, 0x8 }, // 6877
|
|
{ PseudoVREDOR_VS_M8_E8_MASK, VREDOR_VS, 0x3, 0x8 }, // 6878
|
|
{ PseudoVREDOR_VS_M8_E16, VREDOR_VS, 0x3, 0x10 }, // 6879
|
|
{ PseudoVREDOR_VS_M8_E16_MASK, VREDOR_VS, 0x3, 0x10 }, // 6880
|
|
{ PseudoVREDOR_VS_M8_E32, VREDOR_VS, 0x3, 0x20 }, // 6881
|
|
{ PseudoVREDOR_VS_M8_E32_MASK, VREDOR_VS, 0x3, 0x20 }, // 6882
|
|
{ PseudoVREDOR_VS_M8_E64, VREDOR_VS, 0x3, 0x40 }, // 6883
|
|
{ PseudoVREDOR_VS_M8_E64_MASK, VREDOR_VS, 0x3, 0x40 }, // 6884
|
|
{ PseudoVREDOR_VS_MF8_E8, VREDOR_VS, 0x5, 0x8 }, // 6885
|
|
{ PseudoVREDOR_VS_MF8_E8_MASK, VREDOR_VS, 0x5, 0x8 }, // 6886
|
|
{ PseudoVREDOR_VS_MF4_E8, VREDOR_VS, 0x6, 0x8 }, // 6887
|
|
{ PseudoVREDOR_VS_MF4_E8_MASK, VREDOR_VS, 0x6, 0x8 }, // 6888
|
|
{ PseudoVREDOR_VS_MF4_E16, VREDOR_VS, 0x6, 0x10 }, // 6889
|
|
{ PseudoVREDOR_VS_MF4_E16_MASK, VREDOR_VS, 0x6, 0x10 }, // 6890
|
|
{ PseudoVREDOR_VS_MF2_E8, VREDOR_VS, 0x7, 0x8 }, // 6891
|
|
{ PseudoVREDOR_VS_MF2_E8_MASK, VREDOR_VS, 0x7, 0x8 }, // 6892
|
|
{ PseudoVREDOR_VS_MF2_E16, VREDOR_VS, 0x7, 0x10 }, // 6893
|
|
{ PseudoVREDOR_VS_MF2_E16_MASK, VREDOR_VS, 0x7, 0x10 }, // 6894
|
|
{ PseudoVREDOR_VS_MF2_E32, VREDOR_VS, 0x7, 0x20 }, // 6895
|
|
{ PseudoVREDOR_VS_MF2_E32_MASK, VREDOR_VS, 0x7, 0x20 }, // 6896
|
|
{ PseudoVREDSUM_VS_M1_E8, VREDSUM_VS, 0x0, 0x8 }, // 6897
|
|
{ PseudoVREDSUM_VS_M1_E8_MASK, VREDSUM_VS, 0x0, 0x8 }, // 6898
|
|
{ PseudoVREDSUM_VS_M1_E16, VREDSUM_VS, 0x0, 0x10 }, // 6899
|
|
{ PseudoVREDSUM_VS_M1_E16_MASK, VREDSUM_VS, 0x0, 0x10 }, // 6900
|
|
{ PseudoVREDSUM_VS_M1_E32, VREDSUM_VS, 0x0, 0x20 }, // 6901
|
|
{ PseudoVREDSUM_VS_M1_E32_MASK, VREDSUM_VS, 0x0, 0x20 }, // 6902
|
|
{ PseudoVREDSUM_VS_M1_E64, VREDSUM_VS, 0x0, 0x40 }, // 6903
|
|
{ PseudoVREDSUM_VS_M1_E64_MASK, VREDSUM_VS, 0x0, 0x40 }, // 6904
|
|
{ PseudoVREDSUM_VS_M2_E8, VREDSUM_VS, 0x1, 0x8 }, // 6905
|
|
{ PseudoVREDSUM_VS_M2_E8_MASK, VREDSUM_VS, 0x1, 0x8 }, // 6906
|
|
{ PseudoVREDSUM_VS_M2_E16, VREDSUM_VS, 0x1, 0x10 }, // 6907
|
|
{ PseudoVREDSUM_VS_M2_E16_MASK, VREDSUM_VS, 0x1, 0x10 }, // 6908
|
|
{ PseudoVREDSUM_VS_M2_E32, VREDSUM_VS, 0x1, 0x20 }, // 6909
|
|
{ PseudoVREDSUM_VS_M2_E32_MASK, VREDSUM_VS, 0x1, 0x20 }, // 6910
|
|
{ PseudoVREDSUM_VS_M2_E64, VREDSUM_VS, 0x1, 0x40 }, // 6911
|
|
{ PseudoVREDSUM_VS_M2_E64_MASK, VREDSUM_VS, 0x1, 0x40 }, // 6912
|
|
{ PseudoVREDSUM_VS_M4_E8, VREDSUM_VS, 0x2, 0x8 }, // 6913
|
|
{ PseudoVREDSUM_VS_M4_E8_MASK, VREDSUM_VS, 0x2, 0x8 }, // 6914
|
|
{ PseudoVREDSUM_VS_M4_E16, VREDSUM_VS, 0x2, 0x10 }, // 6915
|
|
{ PseudoVREDSUM_VS_M4_E16_MASK, VREDSUM_VS, 0x2, 0x10 }, // 6916
|
|
{ PseudoVREDSUM_VS_M4_E32, VREDSUM_VS, 0x2, 0x20 }, // 6917
|
|
{ PseudoVREDSUM_VS_M4_E32_MASK, VREDSUM_VS, 0x2, 0x20 }, // 6918
|
|
{ PseudoVREDSUM_VS_M4_E64, VREDSUM_VS, 0x2, 0x40 }, // 6919
|
|
{ PseudoVREDSUM_VS_M4_E64_MASK, VREDSUM_VS, 0x2, 0x40 }, // 6920
|
|
{ PseudoVREDSUM_VS_M8_E8, VREDSUM_VS, 0x3, 0x8 }, // 6921
|
|
{ PseudoVREDSUM_VS_M8_E8_MASK, VREDSUM_VS, 0x3, 0x8 }, // 6922
|
|
{ PseudoVREDSUM_VS_M8_E16, VREDSUM_VS, 0x3, 0x10 }, // 6923
|
|
{ PseudoVREDSUM_VS_M8_E16_MASK, VREDSUM_VS, 0x3, 0x10 }, // 6924
|
|
{ PseudoVREDSUM_VS_M8_E32, VREDSUM_VS, 0x3, 0x20 }, // 6925
|
|
{ PseudoVREDSUM_VS_M8_E32_MASK, VREDSUM_VS, 0x3, 0x20 }, // 6926
|
|
{ PseudoVREDSUM_VS_M8_E64, VREDSUM_VS, 0x3, 0x40 }, // 6927
|
|
{ PseudoVREDSUM_VS_M8_E64_MASK, VREDSUM_VS, 0x3, 0x40 }, // 6928
|
|
{ PseudoVREDSUM_VS_MF8_E8, VREDSUM_VS, 0x5, 0x8 }, // 6929
|
|
{ PseudoVREDSUM_VS_MF8_E8_MASK, VREDSUM_VS, 0x5, 0x8 }, // 6930
|
|
{ PseudoVREDSUM_VS_MF4_E8, VREDSUM_VS, 0x6, 0x8 }, // 6931
|
|
{ PseudoVREDSUM_VS_MF4_E8_MASK, VREDSUM_VS, 0x6, 0x8 }, // 6932
|
|
{ PseudoVREDSUM_VS_MF4_E16, VREDSUM_VS, 0x6, 0x10 }, // 6933
|
|
{ PseudoVREDSUM_VS_MF4_E16_MASK, VREDSUM_VS, 0x6, 0x10 }, // 6934
|
|
{ PseudoVREDSUM_VS_MF2_E8, VREDSUM_VS, 0x7, 0x8 }, // 6935
|
|
{ PseudoVREDSUM_VS_MF2_E8_MASK, VREDSUM_VS, 0x7, 0x8 }, // 6936
|
|
{ PseudoVREDSUM_VS_MF2_E16, VREDSUM_VS, 0x7, 0x10 }, // 6937
|
|
{ PseudoVREDSUM_VS_MF2_E16_MASK, VREDSUM_VS, 0x7, 0x10 }, // 6938
|
|
{ PseudoVREDSUM_VS_MF2_E32, VREDSUM_VS, 0x7, 0x20 }, // 6939
|
|
{ PseudoVREDSUM_VS_MF2_E32_MASK, VREDSUM_VS, 0x7, 0x20 }, // 6940
|
|
{ PseudoVREDXOR_VS_M1_E8, VREDXOR_VS, 0x0, 0x8 }, // 6941
|
|
{ PseudoVREDXOR_VS_M1_E8_MASK, VREDXOR_VS, 0x0, 0x8 }, // 6942
|
|
{ PseudoVREDXOR_VS_M1_E16, VREDXOR_VS, 0x0, 0x10 }, // 6943
|
|
{ PseudoVREDXOR_VS_M1_E16_MASK, VREDXOR_VS, 0x0, 0x10 }, // 6944
|
|
{ PseudoVREDXOR_VS_M1_E32, VREDXOR_VS, 0x0, 0x20 }, // 6945
|
|
{ PseudoVREDXOR_VS_M1_E32_MASK, VREDXOR_VS, 0x0, 0x20 }, // 6946
|
|
{ PseudoVREDXOR_VS_M1_E64, VREDXOR_VS, 0x0, 0x40 }, // 6947
|
|
{ PseudoVREDXOR_VS_M1_E64_MASK, VREDXOR_VS, 0x0, 0x40 }, // 6948
|
|
{ PseudoVREDXOR_VS_M2_E8, VREDXOR_VS, 0x1, 0x8 }, // 6949
|
|
{ PseudoVREDXOR_VS_M2_E8_MASK, VREDXOR_VS, 0x1, 0x8 }, // 6950
|
|
{ PseudoVREDXOR_VS_M2_E16, VREDXOR_VS, 0x1, 0x10 }, // 6951
|
|
{ PseudoVREDXOR_VS_M2_E16_MASK, VREDXOR_VS, 0x1, 0x10 }, // 6952
|
|
{ PseudoVREDXOR_VS_M2_E32, VREDXOR_VS, 0x1, 0x20 }, // 6953
|
|
{ PseudoVREDXOR_VS_M2_E32_MASK, VREDXOR_VS, 0x1, 0x20 }, // 6954
|
|
{ PseudoVREDXOR_VS_M2_E64, VREDXOR_VS, 0x1, 0x40 }, // 6955
|
|
{ PseudoVREDXOR_VS_M2_E64_MASK, VREDXOR_VS, 0x1, 0x40 }, // 6956
|
|
{ PseudoVREDXOR_VS_M4_E8, VREDXOR_VS, 0x2, 0x8 }, // 6957
|
|
{ PseudoVREDXOR_VS_M4_E8_MASK, VREDXOR_VS, 0x2, 0x8 }, // 6958
|
|
{ PseudoVREDXOR_VS_M4_E16, VREDXOR_VS, 0x2, 0x10 }, // 6959
|
|
{ PseudoVREDXOR_VS_M4_E16_MASK, VREDXOR_VS, 0x2, 0x10 }, // 6960
|
|
{ PseudoVREDXOR_VS_M4_E32, VREDXOR_VS, 0x2, 0x20 }, // 6961
|
|
{ PseudoVREDXOR_VS_M4_E32_MASK, VREDXOR_VS, 0x2, 0x20 }, // 6962
|
|
{ PseudoVREDXOR_VS_M4_E64, VREDXOR_VS, 0x2, 0x40 }, // 6963
|
|
{ PseudoVREDXOR_VS_M4_E64_MASK, VREDXOR_VS, 0x2, 0x40 }, // 6964
|
|
{ PseudoVREDXOR_VS_M8_E8, VREDXOR_VS, 0x3, 0x8 }, // 6965
|
|
{ PseudoVREDXOR_VS_M8_E8_MASK, VREDXOR_VS, 0x3, 0x8 }, // 6966
|
|
{ PseudoVREDXOR_VS_M8_E16, VREDXOR_VS, 0x3, 0x10 }, // 6967
|
|
{ PseudoVREDXOR_VS_M8_E16_MASK, VREDXOR_VS, 0x3, 0x10 }, // 6968
|
|
{ PseudoVREDXOR_VS_M8_E32, VREDXOR_VS, 0x3, 0x20 }, // 6969
|
|
{ PseudoVREDXOR_VS_M8_E32_MASK, VREDXOR_VS, 0x3, 0x20 }, // 6970
|
|
{ PseudoVREDXOR_VS_M8_E64, VREDXOR_VS, 0x3, 0x40 }, // 6971
|
|
{ PseudoVREDXOR_VS_M8_E64_MASK, VREDXOR_VS, 0x3, 0x40 }, // 6972
|
|
{ PseudoVREDXOR_VS_MF8_E8, VREDXOR_VS, 0x5, 0x8 }, // 6973
|
|
{ PseudoVREDXOR_VS_MF8_E8_MASK, VREDXOR_VS, 0x5, 0x8 }, // 6974
|
|
{ PseudoVREDXOR_VS_MF4_E8, VREDXOR_VS, 0x6, 0x8 }, // 6975
|
|
{ PseudoVREDXOR_VS_MF4_E8_MASK, VREDXOR_VS, 0x6, 0x8 }, // 6976
|
|
{ PseudoVREDXOR_VS_MF4_E16, VREDXOR_VS, 0x6, 0x10 }, // 6977
|
|
{ PseudoVREDXOR_VS_MF4_E16_MASK, VREDXOR_VS, 0x6, 0x10 }, // 6978
|
|
{ PseudoVREDXOR_VS_MF2_E8, VREDXOR_VS, 0x7, 0x8 }, // 6979
|
|
{ PseudoVREDXOR_VS_MF2_E8_MASK, VREDXOR_VS, 0x7, 0x8 }, // 6980
|
|
{ PseudoVREDXOR_VS_MF2_E16, VREDXOR_VS, 0x7, 0x10 }, // 6981
|
|
{ PseudoVREDXOR_VS_MF2_E16_MASK, VREDXOR_VS, 0x7, 0x10 }, // 6982
|
|
{ PseudoVREDXOR_VS_MF2_E32, VREDXOR_VS, 0x7, 0x20 }, // 6983
|
|
{ PseudoVREDXOR_VS_MF2_E32_MASK, VREDXOR_VS, 0x7, 0x20 }, // 6984
|
|
{ PseudoVREMU_VV_M1_E8, VREMU_VV, 0x0, 0x8 }, // 6985
|
|
{ PseudoVREMU_VV_M1_E8_MASK, VREMU_VV, 0x0, 0x8 }, // 6986
|
|
{ PseudoVREMU_VV_M1_E16, VREMU_VV, 0x0, 0x10 }, // 6987
|
|
{ PseudoVREMU_VV_M1_E16_MASK, VREMU_VV, 0x0, 0x10 }, // 6988
|
|
{ PseudoVREMU_VV_M1_E32, VREMU_VV, 0x0, 0x20 }, // 6989
|
|
{ PseudoVREMU_VV_M1_E32_MASK, VREMU_VV, 0x0, 0x20 }, // 6990
|
|
{ PseudoVREMU_VV_M1_E64, VREMU_VV, 0x0, 0x40 }, // 6991
|
|
{ PseudoVREMU_VV_M1_E64_MASK, VREMU_VV, 0x0, 0x40 }, // 6992
|
|
{ PseudoVREMU_VV_M2_E8, VREMU_VV, 0x1, 0x8 }, // 6993
|
|
{ PseudoVREMU_VV_M2_E8_MASK, VREMU_VV, 0x1, 0x8 }, // 6994
|
|
{ PseudoVREMU_VV_M2_E16, VREMU_VV, 0x1, 0x10 }, // 6995
|
|
{ PseudoVREMU_VV_M2_E16_MASK, VREMU_VV, 0x1, 0x10 }, // 6996
|
|
{ PseudoVREMU_VV_M2_E32, VREMU_VV, 0x1, 0x20 }, // 6997
|
|
{ PseudoVREMU_VV_M2_E32_MASK, VREMU_VV, 0x1, 0x20 }, // 6998
|
|
{ PseudoVREMU_VV_M2_E64, VREMU_VV, 0x1, 0x40 }, // 6999
|
|
{ PseudoVREMU_VV_M2_E64_MASK, VREMU_VV, 0x1, 0x40 }, // 7000
|
|
{ PseudoVREMU_VV_M4_E8, VREMU_VV, 0x2, 0x8 }, // 7001
|
|
{ PseudoVREMU_VV_M4_E8_MASK, VREMU_VV, 0x2, 0x8 }, // 7002
|
|
{ PseudoVREMU_VV_M4_E16, VREMU_VV, 0x2, 0x10 }, // 7003
|
|
{ PseudoVREMU_VV_M4_E16_MASK, VREMU_VV, 0x2, 0x10 }, // 7004
|
|
{ PseudoVREMU_VV_M4_E32, VREMU_VV, 0x2, 0x20 }, // 7005
|
|
{ PseudoVREMU_VV_M4_E32_MASK, VREMU_VV, 0x2, 0x20 }, // 7006
|
|
{ PseudoVREMU_VV_M4_E64, VREMU_VV, 0x2, 0x40 }, // 7007
|
|
{ PseudoVREMU_VV_M4_E64_MASK, VREMU_VV, 0x2, 0x40 }, // 7008
|
|
{ PseudoVREMU_VV_M8_E8, VREMU_VV, 0x3, 0x8 }, // 7009
|
|
{ PseudoVREMU_VV_M8_E8_MASK, VREMU_VV, 0x3, 0x8 }, // 7010
|
|
{ PseudoVREMU_VV_M8_E16, VREMU_VV, 0x3, 0x10 }, // 7011
|
|
{ PseudoVREMU_VV_M8_E16_MASK, VREMU_VV, 0x3, 0x10 }, // 7012
|
|
{ PseudoVREMU_VV_M8_E32, VREMU_VV, 0x3, 0x20 }, // 7013
|
|
{ PseudoVREMU_VV_M8_E32_MASK, VREMU_VV, 0x3, 0x20 }, // 7014
|
|
{ PseudoVREMU_VV_M8_E64, VREMU_VV, 0x3, 0x40 }, // 7015
|
|
{ PseudoVREMU_VV_M8_E64_MASK, VREMU_VV, 0x3, 0x40 }, // 7016
|
|
{ PseudoVREMU_VV_MF8_E8, VREMU_VV, 0x5, 0x8 }, // 7017
|
|
{ PseudoVREMU_VV_MF8_E8_MASK, VREMU_VV, 0x5, 0x8 }, // 7018
|
|
{ PseudoVREMU_VV_MF4_E8, VREMU_VV, 0x6, 0x8 }, // 7019
|
|
{ PseudoVREMU_VV_MF4_E8_MASK, VREMU_VV, 0x6, 0x8 }, // 7020
|
|
{ PseudoVREMU_VV_MF4_E16, VREMU_VV, 0x6, 0x10 }, // 7021
|
|
{ PseudoVREMU_VV_MF4_E16_MASK, VREMU_VV, 0x6, 0x10 }, // 7022
|
|
{ PseudoVREMU_VV_MF2_E8, VREMU_VV, 0x7, 0x8 }, // 7023
|
|
{ PseudoVREMU_VV_MF2_E8_MASK, VREMU_VV, 0x7, 0x8 }, // 7024
|
|
{ PseudoVREMU_VV_MF2_E16, VREMU_VV, 0x7, 0x10 }, // 7025
|
|
{ PseudoVREMU_VV_MF2_E16_MASK, VREMU_VV, 0x7, 0x10 }, // 7026
|
|
{ PseudoVREMU_VV_MF2_E32, VREMU_VV, 0x7, 0x20 }, // 7027
|
|
{ PseudoVREMU_VV_MF2_E32_MASK, VREMU_VV, 0x7, 0x20 }, // 7028
|
|
{ PseudoVREMU_VX_M1_E8, VREMU_VX, 0x0, 0x8 }, // 7029
|
|
{ PseudoVREMU_VX_M1_E8_MASK, VREMU_VX, 0x0, 0x8 }, // 7030
|
|
{ PseudoVREMU_VX_M1_E16, VREMU_VX, 0x0, 0x10 }, // 7031
|
|
{ PseudoVREMU_VX_M1_E16_MASK, VREMU_VX, 0x0, 0x10 }, // 7032
|
|
{ PseudoVREMU_VX_M1_E32, VREMU_VX, 0x0, 0x20 }, // 7033
|
|
{ PseudoVREMU_VX_M1_E32_MASK, VREMU_VX, 0x0, 0x20 }, // 7034
|
|
{ PseudoVREMU_VX_M1_E64, VREMU_VX, 0x0, 0x40 }, // 7035
|
|
{ PseudoVREMU_VX_M1_E64_MASK, VREMU_VX, 0x0, 0x40 }, // 7036
|
|
{ PseudoVREMU_VX_M2_E8, VREMU_VX, 0x1, 0x8 }, // 7037
|
|
{ PseudoVREMU_VX_M2_E8_MASK, VREMU_VX, 0x1, 0x8 }, // 7038
|
|
{ PseudoVREMU_VX_M2_E16, VREMU_VX, 0x1, 0x10 }, // 7039
|
|
{ PseudoVREMU_VX_M2_E16_MASK, VREMU_VX, 0x1, 0x10 }, // 7040
|
|
{ PseudoVREMU_VX_M2_E32, VREMU_VX, 0x1, 0x20 }, // 7041
|
|
{ PseudoVREMU_VX_M2_E32_MASK, VREMU_VX, 0x1, 0x20 }, // 7042
|
|
{ PseudoVREMU_VX_M2_E64, VREMU_VX, 0x1, 0x40 }, // 7043
|
|
{ PseudoVREMU_VX_M2_E64_MASK, VREMU_VX, 0x1, 0x40 }, // 7044
|
|
{ PseudoVREMU_VX_M4_E8, VREMU_VX, 0x2, 0x8 }, // 7045
|
|
{ PseudoVREMU_VX_M4_E8_MASK, VREMU_VX, 0x2, 0x8 }, // 7046
|
|
{ PseudoVREMU_VX_M4_E16, VREMU_VX, 0x2, 0x10 }, // 7047
|
|
{ PseudoVREMU_VX_M4_E16_MASK, VREMU_VX, 0x2, 0x10 }, // 7048
|
|
{ PseudoVREMU_VX_M4_E32, VREMU_VX, 0x2, 0x20 }, // 7049
|
|
{ PseudoVREMU_VX_M4_E32_MASK, VREMU_VX, 0x2, 0x20 }, // 7050
|
|
{ PseudoVREMU_VX_M4_E64, VREMU_VX, 0x2, 0x40 }, // 7051
|
|
{ PseudoVREMU_VX_M4_E64_MASK, VREMU_VX, 0x2, 0x40 }, // 7052
|
|
{ PseudoVREMU_VX_M8_E8, VREMU_VX, 0x3, 0x8 }, // 7053
|
|
{ PseudoVREMU_VX_M8_E8_MASK, VREMU_VX, 0x3, 0x8 }, // 7054
|
|
{ PseudoVREMU_VX_M8_E16, VREMU_VX, 0x3, 0x10 }, // 7055
|
|
{ PseudoVREMU_VX_M8_E16_MASK, VREMU_VX, 0x3, 0x10 }, // 7056
|
|
{ PseudoVREMU_VX_M8_E32, VREMU_VX, 0x3, 0x20 }, // 7057
|
|
{ PseudoVREMU_VX_M8_E32_MASK, VREMU_VX, 0x3, 0x20 }, // 7058
|
|
{ PseudoVREMU_VX_M8_E64, VREMU_VX, 0x3, 0x40 }, // 7059
|
|
{ PseudoVREMU_VX_M8_E64_MASK, VREMU_VX, 0x3, 0x40 }, // 7060
|
|
{ PseudoVREMU_VX_MF8_E8, VREMU_VX, 0x5, 0x8 }, // 7061
|
|
{ PseudoVREMU_VX_MF8_E8_MASK, VREMU_VX, 0x5, 0x8 }, // 7062
|
|
{ PseudoVREMU_VX_MF4_E8, VREMU_VX, 0x6, 0x8 }, // 7063
|
|
{ PseudoVREMU_VX_MF4_E8_MASK, VREMU_VX, 0x6, 0x8 }, // 7064
|
|
{ PseudoVREMU_VX_MF4_E16, VREMU_VX, 0x6, 0x10 }, // 7065
|
|
{ PseudoVREMU_VX_MF4_E16_MASK, VREMU_VX, 0x6, 0x10 }, // 7066
|
|
{ PseudoVREMU_VX_MF2_E8, VREMU_VX, 0x7, 0x8 }, // 7067
|
|
{ PseudoVREMU_VX_MF2_E8_MASK, VREMU_VX, 0x7, 0x8 }, // 7068
|
|
{ PseudoVREMU_VX_MF2_E16, VREMU_VX, 0x7, 0x10 }, // 7069
|
|
{ PseudoVREMU_VX_MF2_E16_MASK, VREMU_VX, 0x7, 0x10 }, // 7070
|
|
{ PseudoVREMU_VX_MF2_E32, VREMU_VX, 0x7, 0x20 }, // 7071
|
|
{ PseudoVREMU_VX_MF2_E32_MASK, VREMU_VX, 0x7, 0x20 }, // 7072
|
|
{ PseudoVREM_VV_M1_E8, VREM_VV, 0x0, 0x8 }, // 7073
|
|
{ PseudoVREM_VV_M1_E8_MASK, VREM_VV, 0x0, 0x8 }, // 7074
|
|
{ PseudoVREM_VV_M1_E16, VREM_VV, 0x0, 0x10 }, // 7075
|
|
{ PseudoVREM_VV_M1_E16_MASK, VREM_VV, 0x0, 0x10 }, // 7076
|
|
{ PseudoVREM_VV_M1_E32, VREM_VV, 0x0, 0x20 }, // 7077
|
|
{ PseudoVREM_VV_M1_E32_MASK, VREM_VV, 0x0, 0x20 }, // 7078
|
|
{ PseudoVREM_VV_M1_E64, VREM_VV, 0x0, 0x40 }, // 7079
|
|
{ PseudoVREM_VV_M1_E64_MASK, VREM_VV, 0x0, 0x40 }, // 7080
|
|
{ PseudoVREM_VV_M2_E8, VREM_VV, 0x1, 0x8 }, // 7081
|
|
{ PseudoVREM_VV_M2_E8_MASK, VREM_VV, 0x1, 0x8 }, // 7082
|
|
{ PseudoVREM_VV_M2_E16, VREM_VV, 0x1, 0x10 }, // 7083
|
|
{ PseudoVREM_VV_M2_E16_MASK, VREM_VV, 0x1, 0x10 }, // 7084
|
|
{ PseudoVREM_VV_M2_E32, VREM_VV, 0x1, 0x20 }, // 7085
|
|
{ PseudoVREM_VV_M2_E32_MASK, VREM_VV, 0x1, 0x20 }, // 7086
|
|
{ PseudoVREM_VV_M2_E64, VREM_VV, 0x1, 0x40 }, // 7087
|
|
{ PseudoVREM_VV_M2_E64_MASK, VREM_VV, 0x1, 0x40 }, // 7088
|
|
{ PseudoVREM_VV_M4_E8, VREM_VV, 0x2, 0x8 }, // 7089
|
|
{ PseudoVREM_VV_M4_E8_MASK, VREM_VV, 0x2, 0x8 }, // 7090
|
|
{ PseudoVREM_VV_M4_E16, VREM_VV, 0x2, 0x10 }, // 7091
|
|
{ PseudoVREM_VV_M4_E16_MASK, VREM_VV, 0x2, 0x10 }, // 7092
|
|
{ PseudoVREM_VV_M4_E32, VREM_VV, 0x2, 0x20 }, // 7093
|
|
{ PseudoVREM_VV_M4_E32_MASK, VREM_VV, 0x2, 0x20 }, // 7094
|
|
{ PseudoVREM_VV_M4_E64, VREM_VV, 0x2, 0x40 }, // 7095
|
|
{ PseudoVREM_VV_M4_E64_MASK, VREM_VV, 0x2, 0x40 }, // 7096
|
|
{ PseudoVREM_VV_M8_E8, VREM_VV, 0x3, 0x8 }, // 7097
|
|
{ PseudoVREM_VV_M8_E8_MASK, VREM_VV, 0x3, 0x8 }, // 7098
|
|
{ PseudoVREM_VV_M8_E16, VREM_VV, 0x3, 0x10 }, // 7099
|
|
{ PseudoVREM_VV_M8_E16_MASK, VREM_VV, 0x3, 0x10 }, // 7100
|
|
{ PseudoVREM_VV_M8_E32, VREM_VV, 0x3, 0x20 }, // 7101
|
|
{ PseudoVREM_VV_M8_E32_MASK, VREM_VV, 0x3, 0x20 }, // 7102
|
|
{ PseudoVREM_VV_M8_E64, VREM_VV, 0x3, 0x40 }, // 7103
|
|
{ PseudoVREM_VV_M8_E64_MASK, VREM_VV, 0x3, 0x40 }, // 7104
|
|
{ PseudoVREM_VV_MF8_E8, VREM_VV, 0x5, 0x8 }, // 7105
|
|
{ PseudoVREM_VV_MF8_E8_MASK, VREM_VV, 0x5, 0x8 }, // 7106
|
|
{ PseudoVREM_VV_MF4_E8, VREM_VV, 0x6, 0x8 }, // 7107
|
|
{ PseudoVREM_VV_MF4_E8_MASK, VREM_VV, 0x6, 0x8 }, // 7108
|
|
{ PseudoVREM_VV_MF4_E16, VREM_VV, 0x6, 0x10 }, // 7109
|
|
{ PseudoVREM_VV_MF4_E16_MASK, VREM_VV, 0x6, 0x10 }, // 7110
|
|
{ PseudoVREM_VV_MF2_E8, VREM_VV, 0x7, 0x8 }, // 7111
|
|
{ PseudoVREM_VV_MF2_E8_MASK, VREM_VV, 0x7, 0x8 }, // 7112
|
|
{ PseudoVREM_VV_MF2_E16, VREM_VV, 0x7, 0x10 }, // 7113
|
|
{ PseudoVREM_VV_MF2_E16_MASK, VREM_VV, 0x7, 0x10 }, // 7114
|
|
{ PseudoVREM_VV_MF2_E32, VREM_VV, 0x7, 0x20 }, // 7115
|
|
{ PseudoVREM_VV_MF2_E32_MASK, VREM_VV, 0x7, 0x20 }, // 7116
|
|
{ PseudoVREM_VX_M1_E8, VREM_VX, 0x0, 0x8 }, // 7117
|
|
{ PseudoVREM_VX_M1_E8_MASK, VREM_VX, 0x0, 0x8 }, // 7118
|
|
{ PseudoVREM_VX_M1_E16, VREM_VX, 0x0, 0x10 }, // 7119
|
|
{ PseudoVREM_VX_M1_E16_MASK, VREM_VX, 0x0, 0x10 }, // 7120
|
|
{ PseudoVREM_VX_M1_E32, VREM_VX, 0x0, 0x20 }, // 7121
|
|
{ PseudoVREM_VX_M1_E32_MASK, VREM_VX, 0x0, 0x20 }, // 7122
|
|
{ PseudoVREM_VX_M1_E64, VREM_VX, 0x0, 0x40 }, // 7123
|
|
{ PseudoVREM_VX_M1_E64_MASK, VREM_VX, 0x0, 0x40 }, // 7124
|
|
{ PseudoVREM_VX_M2_E8, VREM_VX, 0x1, 0x8 }, // 7125
|
|
{ PseudoVREM_VX_M2_E8_MASK, VREM_VX, 0x1, 0x8 }, // 7126
|
|
{ PseudoVREM_VX_M2_E16, VREM_VX, 0x1, 0x10 }, // 7127
|
|
{ PseudoVREM_VX_M2_E16_MASK, VREM_VX, 0x1, 0x10 }, // 7128
|
|
{ PseudoVREM_VX_M2_E32, VREM_VX, 0x1, 0x20 }, // 7129
|
|
{ PseudoVREM_VX_M2_E32_MASK, VREM_VX, 0x1, 0x20 }, // 7130
|
|
{ PseudoVREM_VX_M2_E64, VREM_VX, 0x1, 0x40 }, // 7131
|
|
{ PseudoVREM_VX_M2_E64_MASK, VREM_VX, 0x1, 0x40 }, // 7132
|
|
{ PseudoVREM_VX_M4_E8, VREM_VX, 0x2, 0x8 }, // 7133
|
|
{ PseudoVREM_VX_M4_E8_MASK, VREM_VX, 0x2, 0x8 }, // 7134
|
|
{ PseudoVREM_VX_M4_E16, VREM_VX, 0x2, 0x10 }, // 7135
|
|
{ PseudoVREM_VX_M4_E16_MASK, VREM_VX, 0x2, 0x10 }, // 7136
|
|
{ PseudoVREM_VX_M4_E32, VREM_VX, 0x2, 0x20 }, // 7137
|
|
{ PseudoVREM_VX_M4_E32_MASK, VREM_VX, 0x2, 0x20 }, // 7138
|
|
{ PseudoVREM_VX_M4_E64, VREM_VX, 0x2, 0x40 }, // 7139
|
|
{ PseudoVREM_VX_M4_E64_MASK, VREM_VX, 0x2, 0x40 }, // 7140
|
|
{ PseudoVREM_VX_M8_E8, VREM_VX, 0x3, 0x8 }, // 7141
|
|
{ PseudoVREM_VX_M8_E8_MASK, VREM_VX, 0x3, 0x8 }, // 7142
|
|
{ PseudoVREM_VX_M8_E16, VREM_VX, 0x3, 0x10 }, // 7143
|
|
{ PseudoVREM_VX_M8_E16_MASK, VREM_VX, 0x3, 0x10 }, // 7144
|
|
{ PseudoVREM_VX_M8_E32, VREM_VX, 0x3, 0x20 }, // 7145
|
|
{ PseudoVREM_VX_M8_E32_MASK, VREM_VX, 0x3, 0x20 }, // 7146
|
|
{ PseudoVREM_VX_M8_E64, VREM_VX, 0x3, 0x40 }, // 7147
|
|
{ PseudoVREM_VX_M8_E64_MASK, VREM_VX, 0x3, 0x40 }, // 7148
|
|
{ PseudoVREM_VX_MF8_E8, VREM_VX, 0x5, 0x8 }, // 7149
|
|
{ PseudoVREM_VX_MF8_E8_MASK, VREM_VX, 0x5, 0x8 }, // 7150
|
|
{ PseudoVREM_VX_MF4_E8, VREM_VX, 0x6, 0x8 }, // 7151
|
|
{ PseudoVREM_VX_MF4_E8_MASK, VREM_VX, 0x6, 0x8 }, // 7152
|
|
{ PseudoVREM_VX_MF4_E16, VREM_VX, 0x6, 0x10 }, // 7153
|
|
{ PseudoVREM_VX_MF4_E16_MASK, VREM_VX, 0x6, 0x10 }, // 7154
|
|
{ PseudoVREM_VX_MF2_E8, VREM_VX, 0x7, 0x8 }, // 7155
|
|
{ PseudoVREM_VX_MF2_E8_MASK, VREM_VX, 0x7, 0x8 }, // 7156
|
|
{ PseudoVREM_VX_MF2_E16, VREM_VX, 0x7, 0x10 }, // 7157
|
|
{ PseudoVREM_VX_MF2_E16_MASK, VREM_VX, 0x7, 0x10 }, // 7158
|
|
{ PseudoVREM_VX_MF2_E32, VREM_VX, 0x7, 0x20 }, // 7159
|
|
{ PseudoVREM_VX_MF2_E32_MASK, VREM_VX, 0x7, 0x20 }, // 7160
|
|
{ PseudoVREV8_V_M1, VREV8_V, 0x0, 0x0 }, // 7161
|
|
{ PseudoVREV8_V_M1_MASK, VREV8_V, 0x0, 0x0 }, // 7162
|
|
{ PseudoVREV8_V_M2, VREV8_V, 0x1, 0x0 }, // 7163
|
|
{ PseudoVREV8_V_M2_MASK, VREV8_V, 0x1, 0x0 }, // 7164
|
|
{ PseudoVREV8_V_M4, VREV8_V, 0x2, 0x0 }, // 7165
|
|
{ PseudoVREV8_V_M4_MASK, VREV8_V, 0x2, 0x0 }, // 7166
|
|
{ PseudoVREV8_V_M8, VREV8_V, 0x3, 0x0 }, // 7167
|
|
{ PseudoVREV8_V_M8_MASK, VREV8_V, 0x3, 0x0 }, // 7168
|
|
{ PseudoVREV8_V_MF8, VREV8_V, 0x5, 0x0 }, // 7169
|
|
{ PseudoVREV8_V_MF8_MASK, VREV8_V, 0x5, 0x0 }, // 7170
|
|
{ PseudoVREV8_V_MF4, VREV8_V, 0x6, 0x0 }, // 7171
|
|
{ PseudoVREV8_V_MF4_MASK, VREV8_V, 0x6, 0x0 }, // 7172
|
|
{ PseudoVREV8_V_MF2, VREV8_V, 0x7, 0x0 }, // 7173
|
|
{ PseudoVREV8_V_MF2_MASK, VREV8_V, 0x7, 0x0 }, // 7174
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M1, VRGATHEREI16_VV, 0x0, 0x8 }, // 7175
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7176
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M2, VRGATHEREI16_VV, 0x0, 0x8 }, // 7177
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7178
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF2, VRGATHEREI16_VV, 0x0, 0x8 }, // 7179
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7180
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF4, VRGATHEREI16_VV, 0x0, 0x8 }, // 7181
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7182
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M1, VRGATHEREI16_VV, 0x0, 0x10 }, // 7183
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7184
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M2, VRGATHEREI16_VV, 0x0, 0x10 }, // 7185
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7186
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF2, VRGATHEREI16_VV, 0x0, 0x10 }, // 7187
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7188
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF4, VRGATHEREI16_VV, 0x0, 0x10 }, // 7189
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7190
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M1, VRGATHEREI16_VV, 0x0, 0x20 }, // 7191
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7192
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M2, VRGATHEREI16_VV, 0x0, 0x20 }, // 7193
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7194
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF2, VRGATHEREI16_VV, 0x0, 0x20 }, // 7195
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7196
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF4, VRGATHEREI16_VV, 0x0, 0x20 }, // 7197
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7198
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M1, VRGATHEREI16_VV, 0x0, 0x40 }, // 7199
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7200
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M2, VRGATHEREI16_VV, 0x0, 0x40 }, // 7201
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7202
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF2, VRGATHEREI16_VV, 0x0, 0x40 }, // 7203
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7204
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF4, VRGATHEREI16_VV, 0x0, 0x40 }, // 7205
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7206
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M1, VRGATHEREI16_VV, 0x1, 0x8 }, // 7207
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7208
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M2, VRGATHEREI16_VV, 0x1, 0x8 }, // 7209
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7210
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M4, VRGATHEREI16_VV, 0x1, 0x8 }, // 7211
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7212
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_MF2, VRGATHEREI16_VV, 0x1, 0x8 }, // 7213
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7214
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M1, VRGATHEREI16_VV, 0x1, 0x10 }, // 7215
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7216
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M2, VRGATHEREI16_VV, 0x1, 0x10 }, // 7217
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7218
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M4, VRGATHEREI16_VV, 0x1, 0x10 }, // 7219
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7220
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_MF2, VRGATHEREI16_VV, 0x1, 0x10 }, // 7221
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7222
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M1, VRGATHEREI16_VV, 0x1, 0x20 }, // 7223
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7224
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M2, VRGATHEREI16_VV, 0x1, 0x20 }, // 7225
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7226
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M4, VRGATHEREI16_VV, 0x1, 0x20 }, // 7227
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7228
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_MF2, VRGATHEREI16_VV, 0x1, 0x20 }, // 7229
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7230
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M1, VRGATHEREI16_VV, 0x1, 0x40 }, // 7231
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7232
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M2, VRGATHEREI16_VV, 0x1, 0x40 }, // 7233
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7234
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M4, VRGATHEREI16_VV, 0x1, 0x40 }, // 7235
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7236
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_MF2, VRGATHEREI16_VV, 0x1, 0x40 }, // 7237
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7238
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M1, VRGATHEREI16_VV, 0x2, 0x8 }, // 7239
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7240
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M2, VRGATHEREI16_VV, 0x2, 0x8 }, // 7241
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7242
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M4, VRGATHEREI16_VV, 0x2, 0x8 }, // 7243
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7244
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M8, VRGATHEREI16_VV, 0x2, 0x8 }, // 7245
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7246
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M1, VRGATHEREI16_VV, 0x2, 0x10 }, // 7247
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7248
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M2, VRGATHEREI16_VV, 0x2, 0x10 }, // 7249
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7250
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M4, VRGATHEREI16_VV, 0x2, 0x10 }, // 7251
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7252
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M8, VRGATHEREI16_VV, 0x2, 0x10 }, // 7253
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7254
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M1, VRGATHEREI16_VV, 0x2, 0x20 }, // 7255
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7256
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M2, VRGATHEREI16_VV, 0x2, 0x20 }, // 7257
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7258
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M4, VRGATHEREI16_VV, 0x2, 0x20 }, // 7259
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7260
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M8, VRGATHEREI16_VV, 0x2, 0x20 }, // 7261
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7262
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M1, VRGATHEREI16_VV, 0x2, 0x40 }, // 7263
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7264
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M2, VRGATHEREI16_VV, 0x2, 0x40 }, // 7265
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7266
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M4, VRGATHEREI16_VV, 0x2, 0x40 }, // 7267
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7268
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M8, VRGATHEREI16_VV, 0x2, 0x40 }, // 7269
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7270
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M2, VRGATHEREI16_VV, 0x3, 0x8 }, // 7271
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7272
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M4, VRGATHEREI16_VV, 0x3, 0x8 }, // 7273
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7274
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M8, VRGATHEREI16_VV, 0x3, 0x8 }, // 7275
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7276
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M2, VRGATHEREI16_VV, 0x3, 0x10 }, // 7277
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7278
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M4, VRGATHEREI16_VV, 0x3, 0x10 }, // 7279
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7280
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M8, VRGATHEREI16_VV, 0x3, 0x10 }, // 7281
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7282
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M2, VRGATHEREI16_VV, 0x3, 0x20 }, // 7283
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7284
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M4, VRGATHEREI16_VV, 0x3, 0x20 }, // 7285
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7286
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M8, VRGATHEREI16_VV, 0x3, 0x20 }, // 7287
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7288
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M2, VRGATHEREI16_VV, 0x3, 0x40 }, // 7289
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7290
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M4, VRGATHEREI16_VV, 0x3, 0x40 }, // 7291
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7292
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M8, VRGATHEREI16_VV, 0x3, 0x40 }, // 7293
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7294
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF4, VRGATHEREI16_VV, 0x5, 0x8 }, // 7295
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, VRGATHEREI16_VV, 0x5, 0x8 }, // 7296
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF8, VRGATHEREI16_VV, 0x5, 0x8 }, // 7297
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, VRGATHEREI16_VV, 0x5, 0x8 }, // 7298
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF2, VRGATHEREI16_VV, 0x6, 0x8 }, // 7299
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7300
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF4, VRGATHEREI16_VV, 0x6, 0x8 }, // 7301
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7302
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF8, VRGATHEREI16_VV, 0x6, 0x8 }, // 7303
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7304
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF2, VRGATHEREI16_VV, 0x6, 0x10 }, // 7305
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7306
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF4, VRGATHEREI16_VV, 0x6, 0x10 }, // 7307
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7308
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF8, VRGATHEREI16_VV, 0x6, 0x10 }, // 7309
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7310
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_M1, VRGATHEREI16_VV, 0x7, 0x8 }, // 7311
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7312
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF2, VRGATHEREI16_VV, 0x7, 0x8 }, // 7313
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7314
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF4, VRGATHEREI16_VV, 0x7, 0x8 }, // 7315
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7316
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF8, VRGATHEREI16_VV, 0x7, 0x8 }, // 7317
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7318
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_M1, VRGATHEREI16_VV, 0x7, 0x10 }, // 7319
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7320
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF2, VRGATHEREI16_VV, 0x7, 0x10 }, // 7321
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7322
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF4, VRGATHEREI16_VV, 0x7, 0x10 }, // 7323
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7324
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF8, VRGATHEREI16_VV, 0x7, 0x10 }, // 7325
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7326
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_M1, VRGATHEREI16_VV, 0x7, 0x20 }, // 7327
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7328
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF2, VRGATHEREI16_VV, 0x7, 0x20 }, // 7329
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7330
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF4, VRGATHEREI16_VV, 0x7, 0x20 }, // 7331
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7332
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF8, VRGATHEREI16_VV, 0x7, 0x20 }, // 7333
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7334
|
|
{ PseudoVRGATHER_VI_M1, VRGATHER_VI, 0x0, 0x0 }, // 7335
|
|
{ PseudoVRGATHER_VI_M1_MASK, VRGATHER_VI, 0x0, 0x0 }, // 7336
|
|
{ PseudoVRGATHER_VI_M2, VRGATHER_VI, 0x1, 0x0 }, // 7337
|
|
{ PseudoVRGATHER_VI_M2_MASK, VRGATHER_VI, 0x1, 0x0 }, // 7338
|
|
{ PseudoVRGATHER_VI_M4, VRGATHER_VI, 0x2, 0x0 }, // 7339
|
|
{ PseudoVRGATHER_VI_M4_MASK, VRGATHER_VI, 0x2, 0x0 }, // 7340
|
|
{ PseudoVRGATHER_VI_M8, VRGATHER_VI, 0x3, 0x0 }, // 7341
|
|
{ PseudoVRGATHER_VI_M8_MASK, VRGATHER_VI, 0x3, 0x0 }, // 7342
|
|
{ PseudoVRGATHER_VI_MF8, VRGATHER_VI, 0x5, 0x0 }, // 7343
|
|
{ PseudoVRGATHER_VI_MF8_MASK, VRGATHER_VI, 0x5, 0x0 }, // 7344
|
|
{ PseudoVRGATHER_VI_MF4, VRGATHER_VI, 0x6, 0x0 }, // 7345
|
|
{ PseudoVRGATHER_VI_MF4_MASK, VRGATHER_VI, 0x6, 0x0 }, // 7346
|
|
{ PseudoVRGATHER_VI_MF2, VRGATHER_VI, 0x7, 0x0 }, // 7347
|
|
{ PseudoVRGATHER_VI_MF2_MASK, VRGATHER_VI, 0x7, 0x0 }, // 7348
|
|
{ PseudoVRGATHER_VV_M1_E8, VRGATHER_VV, 0x0, 0x8 }, // 7349
|
|
{ PseudoVRGATHER_VV_M1_E8_MASK, VRGATHER_VV, 0x0, 0x8 }, // 7350
|
|
{ PseudoVRGATHER_VV_M1_E16, VRGATHER_VV, 0x0, 0x10 }, // 7351
|
|
{ PseudoVRGATHER_VV_M1_E16_MASK, VRGATHER_VV, 0x0, 0x10 }, // 7352
|
|
{ PseudoVRGATHER_VV_M1_E32, VRGATHER_VV, 0x0, 0x20 }, // 7353
|
|
{ PseudoVRGATHER_VV_M1_E32_MASK, VRGATHER_VV, 0x0, 0x20 }, // 7354
|
|
{ PseudoVRGATHER_VV_M1_E64, VRGATHER_VV, 0x0, 0x40 }, // 7355
|
|
{ PseudoVRGATHER_VV_M1_E64_MASK, VRGATHER_VV, 0x0, 0x40 }, // 7356
|
|
{ PseudoVRGATHER_VV_M2_E8, VRGATHER_VV, 0x1, 0x8 }, // 7357
|
|
{ PseudoVRGATHER_VV_M2_E8_MASK, VRGATHER_VV, 0x1, 0x8 }, // 7358
|
|
{ PseudoVRGATHER_VV_M2_E16, VRGATHER_VV, 0x1, 0x10 }, // 7359
|
|
{ PseudoVRGATHER_VV_M2_E16_MASK, VRGATHER_VV, 0x1, 0x10 }, // 7360
|
|
{ PseudoVRGATHER_VV_M2_E32, VRGATHER_VV, 0x1, 0x20 }, // 7361
|
|
{ PseudoVRGATHER_VV_M2_E32_MASK, VRGATHER_VV, 0x1, 0x20 }, // 7362
|
|
{ PseudoVRGATHER_VV_M2_E64, VRGATHER_VV, 0x1, 0x40 }, // 7363
|
|
{ PseudoVRGATHER_VV_M2_E64_MASK, VRGATHER_VV, 0x1, 0x40 }, // 7364
|
|
{ PseudoVRGATHER_VV_M4_E8, VRGATHER_VV, 0x2, 0x8 }, // 7365
|
|
{ PseudoVRGATHER_VV_M4_E8_MASK, VRGATHER_VV, 0x2, 0x8 }, // 7366
|
|
{ PseudoVRGATHER_VV_M4_E16, VRGATHER_VV, 0x2, 0x10 }, // 7367
|
|
{ PseudoVRGATHER_VV_M4_E16_MASK, VRGATHER_VV, 0x2, 0x10 }, // 7368
|
|
{ PseudoVRGATHER_VV_M4_E32, VRGATHER_VV, 0x2, 0x20 }, // 7369
|
|
{ PseudoVRGATHER_VV_M4_E32_MASK, VRGATHER_VV, 0x2, 0x20 }, // 7370
|
|
{ PseudoVRGATHER_VV_M4_E64, VRGATHER_VV, 0x2, 0x40 }, // 7371
|
|
{ PseudoVRGATHER_VV_M4_E64_MASK, VRGATHER_VV, 0x2, 0x40 }, // 7372
|
|
{ PseudoVRGATHER_VV_M8_E8, VRGATHER_VV, 0x3, 0x8 }, // 7373
|
|
{ PseudoVRGATHER_VV_M8_E8_MASK, VRGATHER_VV, 0x3, 0x8 }, // 7374
|
|
{ PseudoVRGATHER_VV_M8_E16, VRGATHER_VV, 0x3, 0x10 }, // 7375
|
|
{ PseudoVRGATHER_VV_M8_E16_MASK, VRGATHER_VV, 0x3, 0x10 }, // 7376
|
|
{ PseudoVRGATHER_VV_M8_E32, VRGATHER_VV, 0x3, 0x20 }, // 7377
|
|
{ PseudoVRGATHER_VV_M8_E32_MASK, VRGATHER_VV, 0x3, 0x20 }, // 7378
|
|
{ PseudoVRGATHER_VV_M8_E64, VRGATHER_VV, 0x3, 0x40 }, // 7379
|
|
{ PseudoVRGATHER_VV_M8_E64_MASK, VRGATHER_VV, 0x3, 0x40 }, // 7380
|
|
{ PseudoVRGATHER_VV_MF8_E8, VRGATHER_VV, 0x5, 0x8 }, // 7381
|
|
{ PseudoVRGATHER_VV_MF8_E8_MASK, VRGATHER_VV, 0x5, 0x8 }, // 7382
|
|
{ PseudoVRGATHER_VV_MF4_E8, VRGATHER_VV, 0x6, 0x8 }, // 7383
|
|
{ PseudoVRGATHER_VV_MF4_E8_MASK, VRGATHER_VV, 0x6, 0x8 }, // 7384
|
|
{ PseudoVRGATHER_VV_MF4_E16, VRGATHER_VV, 0x6, 0x10 }, // 7385
|
|
{ PseudoVRGATHER_VV_MF4_E16_MASK, VRGATHER_VV, 0x6, 0x10 }, // 7386
|
|
{ PseudoVRGATHER_VV_MF2_E8, VRGATHER_VV, 0x7, 0x8 }, // 7387
|
|
{ PseudoVRGATHER_VV_MF2_E8_MASK, VRGATHER_VV, 0x7, 0x8 }, // 7388
|
|
{ PseudoVRGATHER_VV_MF2_E16, VRGATHER_VV, 0x7, 0x10 }, // 7389
|
|
{ PseudoVRGATHER_VV_MF2_E16_MASK, VRGATHER_VV, 0x7, 0x10 }, // 7390
|
|
{ PseudoVRGATHER_VV_MF2_E32, VRGATHER_VV, 0x7, 0x20 }, // 7391
|
|
{ PseudoVRGATHER_VV_MF2_E32_MASK, VRGATHER_VV, 0x7, 0x20 }, // 7392
|
|
{ PseudoVRGATHER_VX_M1, VRGATHER_VX, 0x0, 0x0 }, // 7393
|
|
{ PseudoVRGATHER_VX_M1_MASK, VRGATHER_VX, 0x0, 0x0 }, // 7394
|
|
{ PseudoVRGATHER_VX_M2, VRGATHER_VX, 0x1, 0x0 }, // 7395
|
|
{ PseudoVRGATHER_VX_M2_MASK, VRGATHER_VX, 0x1, 0x0 }, // 7396
|
|
{ PseudoVRGATHER_VX_M4, VRGATHER_VX, 0x2, 0x0 }, // 7397
|
|
{ PseudoVRGATHER_VX_M4_MASK, VRGATHER_VX, 0x2, 0x0 }, // 7398
|
|
{ PseudoVRGATHER_VX_M8, VRGATHER_VX, 0x3, 0x0 }, // 7399
|
|
{ PseudoVRGATHER_VX_M8_MASK, VRGATHER_VX, 0x3, 0x0 }, // 7400
|
|
{ PseudoVRGATHER_VX_MF8, VRGATHER_VX, 0x5, 0x0 }, // 7401
|
|
{ PseudoVRGATHER_VX_MF8_MASK, VRGATHER_VX, 0x5, 0x0 }, // 7402
|
|
{ PseudoVRGATHER_VX_MF4, VRGATHER_VX, 0x6, 0x0 }, // 7403
|
|
{ PseudoVRGATHER_VX_MF4_MASK, VRGATHER_VX, 0x6, 0x0 }, // 7404
|
|
{ PseudoVRGATHER_VX_MF2, VRGATHER_VX, 0x7, 0x0 }, // 7405
|
|
{ PseudoVRGATHER_VX_MF2_MASK, VRGATHER_VX, 0x7, 0x0 }, // 7406
|
|
{ PseudoVROL_VV_M1, VROL_VV, 0x0, 0x0 }, // 7407
|
|
{ PseudoVROL_VV_M1_MASK, VROL_VV, 0x0, 0x0 }, // 7408
|
|
{ PseudoVROL_VV_M2, VROL_VV, 0x1, 0x0 }, // 7409
|
|
{ PseudoVROL_VV_M2_MASK, VROL_VV, 0x1, 0x0 }, // 7410
|
|
{ PseudoVROL_VV_M4, VROL_VV, 0x2, 0x0 }, // 7411
|
|
{ PseudoVROL_VV_M4_MASK, VROL_VV, 0x2, 0x0 }, // 7412
|
|
{ PseudoVROL_VV_M8, VROL_VV, 0x3, 0x0 }, // 7413
|
|
{ PseudoVROL_VV_M8_MASK, VROL_VV, 0x3, 0x0 }, // 7414
|
|
{ PseudoVROL_VV_MF8, VROL_VV, 0x5, 0x0 }, // 7415
|
|
{ PseudoVROL_VV_MF8_MASK, VROL_VV, 0x5, 0x0 }, // 7416
|
|
{ PseudoVROL_VV_MF4, VROL_VV, 0x6, 0x0 }, // 7417
|
|
{ PseudoVROL_VV_MF4_MASK, VROL_VV, 0x6, 0x0 }, // 7418
|
|
{ PseudoVROL_VV_MF2, VROL_VV, 0x7, 0x0 }, // 7419
|
|
{ PseudoVROL_VV_MF2_MASK, VROL_VV, 0x7, 0x0 }, // 7420
|
|
{ PseudoVROL_VX_M1, VROL_VX, 0x0, 0x0 }, // 7421
|
|
{ PseudoVROL_VX_M1_MASK, VROL_VX, 0x0, 0x0 }, // 7422
|
|
{ PseudoVROL_VX_M2, VROL_VX, 0x1, 0x0 }, // 7423
|
|
{ PseudoVROL_VX_M2_MASK, VROL_VX, 0x1, 0x0 }, // 7424
|
|
{ PseudoVROL_VX_M4, VROL_VX, 0x2, 0x0 }, // 7425
|
|
{ PseudoVROL_VX_M4_MASK, VROL_VX, 0x2, 0x0 }, // 7426
|
|
{ PseudoVROL_VX_M8, VROL_VX, 0x3, 0x0 }, // 7427
|
|
{ PseudoVROL_VX_M8_MASK, VROL_VX, 0x3, 0x0 }, // 7428
|
|
{ PseudoVROL_VX_MF8, VROL_VX, 0x5, 0x0 }, // 7429
|
|
{ PseudoVROL_VX_MF8_MASK, VROL_VX, 0x5, 0x0 }, // 7430
|
|
{ PseudoVROL_VX_MF4, VROL_VX, 0x6, 0x0 }, // 7431
|
|
{ PseudoVROL_VX_MF4_MASK, VROL_VX, 0x6, 0x0 }, // 7432
|
|
{ PseudoVROL_VX_MF2, VROL_VX, 0x7, 0x0 }, // 7433
|
|
{ PseudoVROL_VX_MF2_MASK, VROL_VX, 0x7, 0x0 }, // 7434
|
|
{ PseudoVROR_VI_M1, VROR_VI, 0x0, 0x0 }, // 7435
|
|
{ PseudoVROR_VI_M1_MASK, VROR_VI, 0x0, 0x0 }, // 7436
|
|
{ PseudoVROR_VI_M2, VROR_VI, 0x1, 0x0 }, // 7437
|
|
{ PseudoVROR_VI_M2_MASK, VROR_VI, 0x1, 0x0 }, // 7438
|
|
{ PseudoVROR_VI_M4, VROR_VI, 0x2, 0x0 }, // 7439
|
|
{ PseudoVROR_VI_M4_MASK, VROR_VI, 0x2, 0x0 }, // 7440
|
|
{ PseudoVROR_VI_M8, VROR_VI, 0x3, 0x0 }, // 7441
|
|
{ PseudoVROR_VI_M8_MASK, VROR_VI, 0x3, 0x0 }, // 7442
|
|
{ PseudoVROR_VI_MF8, VROR_VI, 0x5, 0x0 }, // 7443
|
|
{ PseudoVROR_VI_MF8_MASK, VROR_VI, 0x5, 0x0 }, // 7444
|
|
{ PseudoVROR_VI_MF4, VROR_VI, 0x6, 0x0 }, // 7445
|
|
{ PseudoVROR_VI_MF4_MASK, VROR_VI, 0x6, 0x0 }, // 7446
|
|
{ PseudoVROR_VI_MF2, VROR_VI, 0x7, 0x0 }, // 7447
|
|
{ PseudoVROR_VI_MF2_MASK, VROR_VI, 0x7, 0x0 }, // 7448
|
|
{ PseudoVROR_VV_M1, VROR_VV, 0x0, 0x0 }, // 7449
|
|
{ PseudoVROR_VV_M1_MASK, VROR_VV, 0x0, 0x0 }, // 7450
|
|
{ PseudoVROR_VV_M2, VROR_VV, 0x1, 0x0 }, // 7451
|
|
{ PseudoVROR_VV_M2_MASK, VROR_VV, 0x1, 0x0 }, // 7452
|
|
{ PseudoVROR_VV_M4, VROR_VV, 0x2, 0x0 }, // 7453
|
|
{ PseudoVROR_VV_M4_MASK, VROR_VV, 0x2, 0x0 }, // 7454
|
|
{ PseudoVROR_VV_M8, VROR_VV, 0x3, 0x0 }, // 7455
|
|
{ PseudoVROR_VV_M8_MASK, VROR_VV, 0x3, 0x0 }, // 7456
|
|
{ PseudoVROR_VV_MF8, VROR_VV, 0x5, 0x0 }, // 7457
|
|
{ PseudoVROR_VV_MF8_MASK, VROR_VV, 0x5, 0x0 }, // 7458
|
|
{ PseudoVROR_VV_MF4, VROR_VV, 0x6, 0x0 }, // 7459
|
|
{ PseudoVROR_VV_MF4_MASK, VROR_VV, 0x6, 0x0 }, // 7460
|
|
{ PseudoVROR_VV_MF2, VROR_VV, 0x7, 0x0 }, // 7461
|
|
{ PseudoVROR_VV_MF2_MASK, VROR_VV, 0x7, 0x0 }, // 7462
|
|
{ PseudoVROR_VX_M1, VROR_VX, 0x0, 0x0 }, // 7463
|
|
{ PseudoVROR_VX_M1_MASK, VROR_VX, 0x0, 0x0 }, // 7464
|
|
{ PseudoVROR_VX_M2, VROR_VX, 0x1, 0x0 }, // 7465
|
|
{ PseudoVROR_VX_M2_MASK, VROR_VX, 0x1, 0x0 }, // 7466
|
|
{ PseudoVROR_VX_M4, VROR_VX, 0x2, 0x0 }, // 7467
|
|
{ PseudoVROR_VX_M4_MASK, VROR_VX, 0x2, 0x0 }, // 7468
|
|
{ PseudoVROR_VX_M8, VROR_VX, 0x3, 0x0 }, // 7469
|
|
{ PseudoVROR_VX_M8_MASK, VROR_VX, 0x3, 0x0 }, // 7470
|
|
{ PseudoVROR_VX_MF8, VROR_VX, 0x5, 0x0 }, // 7471
|
|
{ PseudoVROR_VX_MF8_MASK, VROR_VX, 0x5, 0x0 }, // 7472
|
|
{ PseudoVROR_VX_MF4, VROR_VX, 0x6, 0x0 }, // 7473
|
|
{ PseudoVROR_VX_MF4_MASK, VROR_VX, 0x6, 0x0 }, // 7474
|
|
{ PseudoVROR_VX_MF2, VROR_VX, 0x7, 0x0 }, // 7475
|
|
{ PseudoVROR_VX_MF2_MASK, VROR_VX, 0x7, 0x0 }, // 7476
|
|
{ PseudoVRSUB_VI_M1, VRSUB_VI, 0x0, 0x0 }, // 7477
|
|
{ PseudoVRSUB_VI_M1_MASK, VRSUB_VI, 0x0, 0x0 }, // 7478
|
|
{ PseudoVRSUB_VI_M2, VRSUB_VI, 0x1, 0x0 }, // 7479
|
|
{ PseudoVRSUB_VI_M2_MASK, VRSUB_VI, 0x1, 0x0 }, // 7480
|
|
{ PseudoVRSUB_VI_M4, VRSUB_VI, 0x2, 0x0 }, // 7481
|
|
{ PseudoVRSUB_VI_M4_MASK, VRSUB_VI, 0x2, 0x0 }, // 7482
|
|
{ PseudoVRSUB_VI_M8, VRSUB_VI, 0x3, 0x0 }, // 7483
|
|
{ PseudoVRSUB_VI_M8_MASK, VRSUB_VI, 0x3, 0x0 }, // 7484
|
|
{ PseudoVRSUB_VI_MF8, VRSUB_VI, 0x5, 0x0 }, // 7485
|
|
{ PseudoVRSUB_VI_MF8_MASK, VRSUB_VI, 0x5, 0x0 }, // 7486
|
|
{ PseudoVRSUB_VI_MF4, VRSUB_VI, 0x6, 0x0 }, // 7487
|
|
{ PseudoVRSUB_VI_MF4_MASK, VRSUB_VI, 0x6, 0x0 }, // 7488
|
|
{ PseudoVRSUB_VI_MF2, VRSUB_VI, 0x7, 0x0 }, // 7489
|
|
{ PseudoVRSUB_VI_MF2_MASK, VRSUB_VI, 0x7, 0x0 }, // 7490
|
|
{ PseudoVRSUB_VX_M1, VRSUB_VX, 0x0, 0x0 }, // 7491
|
|
{ PseudoVRSUB_VX_M1_MASK, VRSUB_VX, 0x0, 0x0 }, // 7492
|
|
{ PseudoVRSUB_VX_M2, VRSUB_VX, 0x1, 0x0 }, // 7493
|
|
{ PseudoVRSUB_VX_M2_MASK, VRSUB_VX, 0x1, 0x0 }, // 7494
|
|
{ PseudoVRSUB_VX_M4, VRSUB_VX, 0x2, 0x0 }, // 7495
|
|
{ PseudoVRSUB_VX_M4_MASK, VRSUB_VX, 0x2, 0x0 }, // 7496
|
|
{ PseudoVRSUB_VX_M8, VRSUB_VX, 0x3, 0x0 }, // 7497
|
|
{ PseudoVRSUB_VX_M8_MASK, VRSUB_VX, 0x3, 0x0 }, // 7498
|
|
{ PseudoVRSUB_VX_MF8, VRSUB_VX, 0x5, 0x0 }, // 7499
|
|
{ PseudoVRSUB_VX_MF8_MASK, VRSUB_VX, 0x5, 0x0 }, // 7500
|
|
{ PseudoVRSUB_VX_MF4, VRSUB_VX, 0x6, 0x0 }, // 7501
|
|
{ PseudoVRSUB_VX_MF4_MASK, VRSUB_VX, 0x6, 0x0 }, // 7502
|
|
{ PseudoVRSUB_VX_MF2, VRSUB_VX, 0x7, 0x0 }, // 7503
|
|
{ PseudoVRSUB_VX_MF2_MASK, VRSUB_VX, 0x7, 0x0 }, // 7504
|
|
{ PseudoVSADDU_VI_M1, VSADDU_VI, 0x0, 0x0 }, // 7505
|
|
{ PseudoVSADDU_VI_M1_MASK, VSADDU_VI, 0x0, 0x0 }, // 7506
|
|
{ PseudoVSADDU_VI_M2, VSADDU_VI, 0x1, 0x0 }, // 7507
|
|
{ PseudoVSADDU_VI_M2_MASK, VSADDU_VI, 0x1, 0x0 }, // 7508
|
|
{ PseudoVSADDU_VI_M4, VSADDU_VI, 0x2, 0x0 }, // 7509
|
|
{ PseudoVSADDU_VI_M4_MASK, VSADDU_VI, 0x2, 0x0 }, // 7510
|
|
{ PseudoVSADDU_VI_M8, VSADDU_VI, 0x3, 0x0 }, // 7511
|
|
{ PseudoVSADDU_VI_M8_MASK, VSADDU_VI, 0x3, 0x0 }, // 7512
|
|
{ PseudoVSADDU_VI_MF8, VSADDU_VI, 0x5, 0x0 }, // 7513
|
|
{ PseudoVSADDU_VI_MF8_MASK, VSADDU_VI, 0x5, 0x0 }, // 7514
|
|
{ PseudoVSADDU_VI_MF4, VSADDU_VI, 0x6, 0x0 }, // 7515
|
|
{ PseudoVSADDU_VI_MF4_MASK, VSADDU_VI, 0x6, 0x0 }, // 7516
|
|
{ PseudoVSADDU_VI_MF2, VSADDU_VI, 0x7, 0x0 }, // 7517
|
|
{ PseudoVSADDU_VI_MF2_MASK, VSADDU_VI, 0x7, 0x0 }, // 7518
|
|
{ PseudoVSADDU_VV_M1, VSADDU_VV, 0x0, 0x0 }, // 7519
|
|
{ PseudoVSADDU_VV_M1_MASK, VSADDU_VV, 0x0, 0x0 }, // 7520
|
|
{ PseudoVSADDU_VV_M2, VSADDU_VV, 0x1, 0x0 }, // 7521
|
|
{ PseudoVSADDU_VV_M2_MASK, VSADDU_VV, 0x1, 0x0 }, // 7522
|
|
{ PseudoVSADDU_VV_M4, VSADDU_VV, 0x2, 0x0 }, // 7523
|
|
{ PseudoVSADDU_VV_M4_MASK, VSADDU_VV, 0x2, 0x0 }, // 7524
|
|
{ PseudoVSADDU_VV_M8, VSADDU_VV, 0x3, 0x0 }, // 7525
|
|
{ PseudoVSADDU_VV_M8_MASK, VSADDU_VV, 0x3, 0x0 }, // 7526
|
|
{ PseudoVSADDU_VV_MF8, VSADDU_VV, 0x5, 0x0 }, // 7527
|
|
{ PseudoVSADDU_VV_MF8_MASK, VSADDU_VV, 0x5, 0x0 }, // 7528
|
|
{ PseudoVSADDU_VV_MF4, VSADDU_VV, 0x6, 0x0 }, // 7529
|
|
{ PseudoVSADDU_VV_MF4_MASK, VSADDU_VV, 0x6, 0x0 }, // 7530
|
|
{ PseudoVSADDU_VV_MF2, VSADDU_VV, 0x7, 0x0 }, // 7531
|
|
{ PseudoVSADDU_VV_MF2_MASK, VSADDU_VV, 0x7, 0x0 }, // 7532
|
|
{ PseudoVSADDU_VX_M1, VSADDU_VX, 0x0, 0x0 }, // 7533
|
|
{ PseudoVSADDU_VX_M1_MASK, VSADDU_VX, 0x0, 0x0 }, // 7534
|
|
{ PseudoVSADDU_VX_M2, VSADDU_VX, 0x1, 0x0 }, // 7535
|
|
{ PseudoVSADDU_VX_M2_MASK, VSADDU_VX, 0x1, 0x0 }, // 7536
|
|
{ PseudoVSADDU_VX_M4, VSADDU_VX, 0x2, 0x0 }, // 7537
|
|
{ PseudoVSADDU_VX_M4_MASK, VSADDU_VX, 0x2, 0x0 }, // 7538
|
|
{ PseudoVSADDU_VX_M8, VSADDU_VX, 0x3, 0x0 }, // 7539
|
|
{ PseudoVSADDU_VX_M8_MASK, VSADDU_VX, 0x3, 0x0 }, // 7540
|
|
{ PseudoVSADDU_VX_MF8, VSADDU_VX, 0x5, 0x0 }, // 7541
|
|
{ PseudoVSADDU_VX_MF8_MASK, VSADDU_VX, 0x5, 0x0 }, // 7542
|
|
{ PseudoVSADDU_VX_MF4, VSADDU_VX, 0x6, 0x0 }, // 7543
|
|
{ PseudoVSADDU_VX_MF4_MASK, VSADDU_VX, 0x6, 0x0 }, // 7544
|
|
{ PseudoVSADDU_VX_MF2, VSADDU_VX, 0x7, 0x0 }, // 7545
|
|
{ PseudoVSADDU_VX_MF2_MASK, VSADDU_VX, 0x7, 0x0 }, // 7546
|
|
{ PseudoVSADD_VI_M1, VSADD_VI, 0x0, 0x0 }, // 7547
|
|
{ PseudoVSADD_VI_M1_MASK, VSADD_VI, 0x0, 0x0 }, // 7548
|
|
{ PseudoVSADD_VI_M2, VSADD_VI, 0x1, 0x0 }, // 7549
|
|
{ PseudoVSADD_VI_M2_MASK, VSADD_VI, 0x1, 0x0 }, // 7550
|
|
{ PseudoVSADD_VI_M4, VSADD_VI, 0x2, 0x0 }, // 7551
|
|
{ PseudoVSADD_VI_M4_MASK, VSADD_VI, 0x2, 0x0 }, // 7552
|
|
{ PseudoVSADD_VI_M8, VSADD_VI, 0x3, 0x0 }, // 7553
|
|
{ PseudoVSADD_VI_M8_MASK, VSADD_VI, 0x3, 0x0 }, // 7554
|
|
{ PseudoVSADD_VI_MF8, VSADD_VI, 0x5, 0x0 }, // 7555
|
|
{ PseudoVSADD_VI_MF8_MASK, VSADD_VI, 0x5, 0x0 }, // 7556
|
|
{ PseudoVSADD_VI_MF4, VSADD_VI, 0x6, 0x0 }, // 7557
|
|
{ PseudoVSADD_VI_MF4_MASK, VSADD_VI, 0x6, 0x0 }, // 7558
|
|
{ PseudoVSADD_VI_MF2, VSADD_VI, 0x7, 0x0 }, // 7559
|
|
{ PseudoVSADD_VI_MF2_MASK, VSADD_VI, 0x7, 0x0 }, // 7560
|
|
{ PseudoVSADD_VV_M1, VSADD_VV, 0x0, 0x0 }, // 7561
|
|
{ PseudoVSADD_VV_M1_MASK, VSADD_VV, 0x0, 0x0 }, // 7562
|
|
{ PseudoVSADD_VV_M2, VSADD_VV, 0x1, 0x0 }, // 7563
|
|
{ PseudoVSADD_VV_M2_MASK, VSADD_VV, 0x1, 0x0 }, // 7564
|
|
{ PseudoVSADD_VV_M4, VSADD_VV, 0x2, 0x0 }, // 7565
|
|
{ PseudoVSADD_VV_M4_MASK, VSADD_VV, 0x2, 0x0 }, // 7566
|
|
{ PseudoVSADD_VV_M8, VSADD_VV, 0x3, 0x0 }, // 7567
|
|
{ PseudoVSADD_VV_M8_MASK, VSADD_VV, 0x3, 0x0 }, // 7568
|
|
{ PseudoVSADD_VV_MF8, VSADD_VV, 0x5, 0x0 }, // 7569
|
|
{ PseudoVSADD_VV_MF8_MASK, VSADD_VV, 0x5, 0x0 }, // 7570
|
|
{ PseudoVSADD_VV_MF4, VSADD_VV, 0x6, 0x0 }, // 7571
|
|
{ PseudoVSADD_VV_MF4_MASK, VSADD_VV, 0x6, 0x0 }, // 7572
|
|
{ PseudoVSADD_VV_MF2, VSADD_VV, 0x7, 0x0 }, // 7573
|
|
{ PseudoVSADD_VV_MF2_MASK, VSADD_VV, 0x7, 0x0 }, // 7574
|
|
{ PseudoVSADD_VX_M1, VSADD_VX, 0x0, 0x0 }, // 7575
|
|
{ PseudoVSADD_VX_M1_MASK, VSADD_VX, 0x0, 0x0 }, // 7576
|
|
{ PseudoVSADD_VX_M2, VSADD_VX, 0x1, 0x0 }, // 7577
|
|
{ PseudoVSADD_VX_M2_MASK, VSADD_VX, 0x1, 0x0 }, // 7578
|
|
{ PseudoVSADD_VX_M4, VSADD_VX, 0x2, 0x0 }, // 7579
|
|
{ PseudoVSADD_VX_M4_MASK, VSADD_VX, 0x2, 0x0 }, // 7580
|
|
{ PseudoVSADD_VX_M8, VSADD_VX, 0x3, 0x0 }, // 7581
|
|
{ PseudoVSADD_VX_M8_MASK, VSADD_VX, 0x3, 0x0 }, // 7582
|
|
{ PseudoVSADD_VX_MF8, VSADD_VX, 0x5, 0x0 }, // 7583
|
|
{ PseudoVSADD_VX_MF8_MASK, VSADD_VX, 0x5, 0x0 }, // 7584
|
|
{ PseudoVSADD_VX_MF4, VSADD_VX, 0x6, 0x0 }, // 7585
|
|
{ PseudoVSADD_VX_MF4_MASK, VSADD_VX, 0x6, 0x0 }, // 7586
|
|
{ PseudoVSADD_VX_MF2, VSADD_VX, 0x7, 0x0 }, // 7587
|
|
{ PseudoVSADD_VX_MF2_MASK, VSADD_VX, 0x7, 0x0 }, // 7588
|
|
{ PseudoVSBC_VVM_M1, VSBC_VVM, 0x0, 0x0 }, // 7589
|
|
{ PseudoVSBC_VVM_M2, VSBC_VVM, 0x1, 0x0 }, // 7590
|
|
{ PseudoVSBC_VVM_M4, VSBC_VVM, 0x2, 0x0 }, // 7591
|
|
{ PseudoVSBC_VVM_M8, VSBC_VVM, 0x3, 0x0 }, // 7592
|
|
{ PseudoVSBC_VVM_MF8, VSBC_VVM, 0x5, 0x0 }, // 7593
|
|
{ PseudoVSBC_VVM_MF4, VSBC_VVM, 0x6, 0x0 }, // 7594
|
|
{ PseudoVSBC_VVM_MF2, VSBC_VVM, 0x7, 0x0 }, // 7595
|
|
{ PseudoVSBC_VXM_M1, VSBC_VXM, 0x0, 0x0 }, // 7596
|
|
{ PseudoVSBC_VXM_M2, VSBC_VXM, 0x1, 0x0 }, // 7597
|
|
{ PseudoVSBC_VXM_M4, VSBC_VXM, 0x2, 0x0 }, // 7598
|
|
{ PseudoVSBC_VXM_M8, VSBC_VXM, 0x3, 0x0 }, // 7599
|
|
{ PseudoVSBC_VXM_MF8, VSBC_VXM, 0x5, 0x0 }, // 7600
|
|
{ PseudoVSBC_VXM_MF4, VSBC_VXM, 0x6, 0x0 }, // 7601
|
|
{ PseudoVSBC_VXM_MF2, VSBC_VXM, 0x7, 0x0 }, // 7602
|
|
{ PseudoVSE16_V_M1, VSE16_V, 0x0, 0x10 }, // 7603
|
|
{ PseudoVSE16_V_M1_MASK, VSE16_V, 0x0, 0x10 }, // 7604
|
|
{ PseudoVSE16_V_M2, VSE16_V, 0x1, 0x10 }, // 7605
|
|
{ PseudoVSE16_V_M2_MASK, VSE16_V, 0x1, 0x10 }, // 7606
|
|
{ PseudoVSE16_V_M4, VSE16_V, 0x2, 0x10 }, // 7607
|
|
{ PseudoVSE16_V_M4_MASK, VSE16_V, 0x2, 0x10 }, // 7608
|
|
{ PseudoVSE16_V_M8, VSE16_V, 0x3, 0x10 }, // 7609
|
|
{ PseudoVSE16_V_M8_MASK, VSE16_V, 0x3, 0x10 }, // 7610
|
|
{ PseudoVSE16_V_MF4, VSE16_V, 0x6, 0x10 }, // 7611
|
|
{ PseudoVSE16_V_MF4_MASK, VSE16_V, 0x6, 0x10 }, // 7612
|
|
{ PseudoVSE16_V_MF2, VSE16_V, 0x7, 0x10 }, // 7613
|
|
{ PseudoVSE16_V_MF2_MASK, VSE16_V, 0x7, 0x10 }, // 7614
|
|
{ PseudoVSE32_V_M1, VSE32_V, 0x0, 0x20 }, // 7615
|
|
{ PseudoVSE32_V_M1_MASK, VSE32_V, 0x0, 0x20 }, // 7616
|
|
{ PseudoVSE32_V_M2, VSE32_V, 0x1, 0x20 }, // 7617
|
|
{ PseudoVSE32_V_M2_MASK, VSE32_V, 0x1, 0x20 }, // 7618
|
|
{ PseudoVSE32_V_M4, VSE32_V, 0x2, 0x20 }, // 7619
|
|
{ PseudoVSE32_V_M4_MASK, VSE32_V, 0x2, 0x20 }, // 7620
|
|
{ PseudoVSE32_V_M8, VSE32_V, 0x3, 0x20 }, // 7621
|
|
{ PseudoVSE32_V_M8_MASK, VSE32_V, 0x3, 0x20 }, // 7622
|
|
{ PseudoVSE32_V_MF2, VSE32_V, 0x7, 0x20 }, // 7623
|
|
{ PseudoVSE32_V_MF2_MASK, VSE32_V, 0x7, 0x20 }, // 7624
|
|
{ PseudoVSE64_V_M1, VSE64_V, 0x0, 0x40 }, // 7625
|
|
{ PseudoVSE64_V_M1_MASK, VSE64_V, 0x0, 0x40 }, // 7626
|
|
{ PseudoVSE64_V_M2, VSE64_V, 0x1, 0x40 }, // 7627
|
|
{ PseudoVSE64_V_M2_MASK, VSE64_V, 0x1, 0x40 }, // 7628
|
|
{ PseudoVSE64_V_M4, VSE64_V, 0x2, 0x40 }, // 7629
|
|
{ PseudoVSE64_V_M4_MASK, VSE64_V, 0x2, 0x40 }, // 7630
|
|
{ PseudoVSE64_V_M8, VSE64_V, 0x3, 0x40 }, // 7631
|
|
{ PseudoVSE64_V_M8_MASK, VSE64_V, 0x3, 0x40 }, // 7632
|
|
{ PseudoVSE8_V_M1, VSE8_V, 0x0, 0x8 }, // 7633
|
|
{ PseudoVSE8_V_M1_MASK, VSE8_V, 0x0, 0x8 }, // 7634
|
|
{ PseudoVSE8_V_M2, VSE8_V, 0x1, 0x8 }, // 7635
|
|
{ PseudoVSE8_V_M2_MASK, VSE8_V, 0x1, 0x8 }, // 7636
|
|
{ PseudoVSE8_V_M4, VSE8_V, 0x2, 0x8 }, // 7637
|
|
{ PseudoVSE8_V_M4_MASK, VSE8_V, 0x2, 0x8 }, // 7638
|
|
{ PseudoVSE8_V_M8, VSE8_V, 0x3, 0x8 }, // 7639
|
|
{ PseudoVSE8_V_M8_MASK, VSE8_V, 0x3, 0x8 }, // 7640
|
|
{ PseudoVSE8_V_MF8, VSE8_V, 0x5, 0x8 }, // 7641
|
|
{ PseudoVSE8_V_MF8_MASK, VSE8_V, 0x5, 0x8 }, // 7642
|
|
{ PseudoVSE8_V_MF4, VSE8_V, 0x6, 0x8 }, // 7643
|
|
{ PseudoVSE8_V_MF4_MASK, VSE8_V, 0x6, 0x8 }, // 7644
|
|
{ PseudoVSE8_V_MF2, VSE8_V, 0x7, 0x8 }, // 7645
|
|
{ PseudoVSE8_V_MF2_MASK, VSE8_V, 0x7, 0x8 }, // 7646
|
|
{ PseudoVSEXT_VF2_M1, VSEXT_VF2, 0x0, 0x0 }, // 7647
|
|
{ PseudoVSEXT_VF2_M1_MASK, VSEXT_VF2, 0x0, 0x0 }, // 7648
|
|
{ PseudoVSEXT_VF2_M2, VSEXT_VF2, 0x1, 0x0 }, // 7649
|
|
{ PseudoVSEXT_VF2_M2_MASK, VSEXT_VF2, 0x1, 0x0 }, // 7650
|
|
{ PseudoVSEXT_VF2_M4, VSEXT_VF2, 0x2, 0x0 }, // 7651
|
|
{ PseudoVSEXT_VF2_M4_MASK, VSEXT_VF2, 0x2, 0x0 }, // 7652
|
|
{ PseudoVSEXT_VF2_M8, VSEXT_VF2, 0x3, 0x0 }, // 7653
|
|
{ PseudoVSEXT_VF2_M8_MASK, VSEXT_VF2, 0x3, 0x0 }, // 7654
|
|
{ PseudoVSEXT_VF2_MF4, VSEXT_VF2, 0x6, 0x0 }, // 7655
|
|
{ PseudoVSEXT_VF2_MF4_MASK, VSEXT_VF2, 0x6, 0x0 }, // 7656
|
|
{ PseudoVSEXT_VF2_MF2, VSEXT_VF2, 0x7, 0x0 }, // 7657
|
|
{ PseudoVSEXT_VF2_MF2_MASK, VSEXT_VF2, 0x7, 0x0 }, // 7658
|
|
{ PseudoVSEXT_VF4_M1, VSEXT_VF4, 0x0, 0x0 }, // 7659
|
|
{ PseudoVSEXT_VF4_M1_MASK, VSEXT_VF4, 0x0, 0x0 }, // 7660
|
|
{ PseudoVSEXT_VF4_M2, VSEXT_VF4, 0x1, 0x0 }, // 7661
|
|
{ PseudoVSEXT_VF4_M2_MASK, VSEXT_VF4, 0x1, 0x0 }, // 7662
|
|
{ PseudoVSEXT_VF4_M4, VSEXT_VF4, 0x2, 0x0 }, // 7663
|
|
{ PseudoVSEXT_VF4_M4_MASK, VSEXT_VF4, 0x2, 0x0 }, // 7664
|
|
{ PseudoVSEXT_VF4_M8, VSEXT_VF4, 0x3, 0x0 }, // 7665
|
|
{ PseudoVSEXT_VF4_M8_MASK, VSEXT_VF4, 0x3, 0x0 }, // 7666
|
|
{ PseudoVSEXT_VF4_MF2, VSEXT_VF4, 0x7, 0x0 }, // 7667
|
|
{ PseudoVSEXT_VF4_MF2_MASK, VSEXT_VF4, 0x7, 0x0 }, // 7668
|
|
{ PseudoVSEXT_VF8_M1, VSEXT_VF8, 0x0, 0x0 }, // 7669
|
|
{ PseudoVSEXT_VF8_M1_MASK, VSEXT_VF8, 0x0, 0x0 }, // 7670
|
|
{ PseudoVSEXT_VF8_M2, VSEXT_VF8, 0x1, 0x0 }, // 7671
|
|
{ PseudoVSEXT_VF8_M2_MASK, VSEXT_VF8, 0x1, 0x0 }, // 7672
|
|
{ PseudoVSEXT_VF8_M4, VSEXT_VF8, 0x2, 0x0 }, // 7673
|
|
{ PseudoVSEXT_VF8_M4_MASK, VSEXT_VF8, 0x2, 0x0 }, // 7674
|
|
{ PseudoVSEXT_VF8_M8, VSEXT_VF8, 0x3, 0x0 }, // 7675
|
|
{ PseudoVSEXT_VF8_M8_MASK, VSEXT_VF8, 0x3, 0x0 }, // 7676
|
|
{ PseudoVSHA2CH_VV_M1, VSHA2CH_VV, 0x0, 0x0 }, // 7677
|
|
{ PseudoVSHA2CH_VV_M2, VSHA2CH_VV, 0x1, 0x0 }, // 7678
|
|
{ PseudoVSHA2CH_VV_M4, VSHA2CH_VV, 0x2, 0x0 }, // 7679
|
|
{ PseudoVSHA2CH_VV_M8, VSHA2CH_VV, 0x3, 0x0 }, // 7680
|
|
{ PseudoVSHA2CH_VV_MF2, VSHA2CH_VV, 0x7, 0x0 }, // 7681
|
|
{ PseudoVSHA2CL_VV_M1, VSHA2CL_VV, 0x0, 0x0 }, // 7682
|
|
{ PseudoVSHA2CL_VV_M2, VSHA2CL_VV, 0x1, 0x0 }, // 7683
|
|
{ PseudoVSHA2CL_VV_M4, VSHA2CL_VV, 0x2, 0x0 }, // 7684
|
|
{ PseudoVSHA2CL_VV_M8, VSHA2CL_VV, 0x3, 0x0 }, // 7685
|
|
{ PseudoVSHA2CL_VV_MF2, VSHA2CL_VV, 0x7, 0x0 }, // 7686
|
|
{ PseudoVSHA2MS_VV_M1, VSHA2MS_VV, 0x0, 0x0 }, // 7687
|
|
{ PseudoVSHA2MS_VV_M2, VSHA2MS_VV, 0x1, 0x0 }, // 7688
|
|
{ PseudoVSHA2MS_VV_M4, VSHA2MS_VV, 0x2, 0x0 }, // 7689
|
|
{ PseudoVSHA2MS_VV_M8, VSHA2MS_VV, 0x3, 0x0 }, // 7690
|
|
{ PseudoVSHA2MS_VV_MF2, VSHA2MS_VV, 0x7, 0x0 }, // 7691
|
|
{ PseudoVSLIDE1DOWN_VX_M1, VSLIDE1DOWN_VX, 0x0, 0x0 }, // 7692
|
|
{ PseudoVSLIDE1DOWN_VX_M1_MASK, VSLIDE1DOWN_VX, 0x0, 0x0 }, // 7693
|
|
{ PseudoVSLIDE1DOWN_VX_M2, VSLIDE1DOWN_VX, 0x1, 0x0 }, // 7694
|
|
{ PseudoVSLIDE1DOWN_VX_M2_MASK, VSLIDE1DOWN_VX, 0x1, 0x0 }, // 7695
|
|
{ PseudoVSLIDE1DOWN_VX_M4, VSLIDE1DOWN_VX, 0x2, 0x0 }, // 7696
|
|
{ PseudoVSLIDE1DOWN_VX_M4_MASK, VSLIDE1DOWN_VX, 0x2, 0x0 }, // 7697
|
|
{ PseudoVSLIDE1DOWN_VX_M8, VSLIDE1DOWN_VX, 0x3, 0x0 }, // 7698
|
|
{ PseudoVSLIDE1DOWN_VX_M8_MASK, VSLIDE1DOWN_VX, 0x3, 0x0 }, // 7699
|
|
{ PseudoVSLIDE1DOWN_VX_MF8, VSLIDE1DOWN_VX, 0x5, 0x0 }, // 7700
|
|
{ PseudoVSLIDE1DOWN_VX_MF8_MASK, VSLIDE1DOWN_VX, 0x5, 0x0 }, // 7701
|
|
{ PseudoVSLIDE1DOWN_VX_MF4, VSLIDE1DOWN_VX, 0x6, 0x0 }, // 7702
|
|
{ PseudoVSLIDE1DOWN_VX_MF4_MASK, VSLIDE1DOWN_VX, 0x6, 0x0 }, // 7703
|
|
{ PseudoVSLIDE1DOWN_VX_MF2, VSLIDE1DOWN_VX, 0x7, 0x0 }, // 7704
|
|
{ PseudoVSLIDE1DOWN_VX_MF2_MASK, VSLIDE1DOWN_VX, 0x7, 0x0 }, // 7705
|
|
{ PseudoVSLIDE1UP_VX_M1, VSLIDE1UP_VX, 0x0, 0x0 }, // 7706
|
|
{ PseudoVSLIDE1UP_VX_M1_MASK, VSLIDE1UP_VX, 0x0, 0x0 }, // 7707
|
|
{ PseudoVSLIDE1UP_VX_M2, VSLIDE1UP_VX, 0x1, 0x0 }, // 7708
|
|
{ PseudoVSLIDE1UP_VX_M2_MASK, VSLIDE1UP_VX, 0x1, 0x0 }, // 7709
|
|
{ PseudoVSLIDE1UP_VX_M4, VSLIDE1UP_VX, 0x2, 0x0 }, // 7710
|
|
{ PseudoVSLIDE1UP_VX_M4_MASK, VSLIDE1UP_VX, 0x2, 0x0 }, // 7711
|
|
{ PseudoVSLIDE1UP_VX_M8, VSLIDE1UP_VX, 0x3, 0x0 }, // 7712
|
|
{ PseudoVSLIDE1UP_VX_M8_MASK, VSLIDE1UP_VX, 0x3, 0x0 }, // 7713
|
|
{ PseudoVSLIDE1UP_VX_MF8, VSLIDE1UP_VX, 0x5, 0x0 }, // 7714
|
|
{ PseudoVSLIDE1UP_VX_MF8_MASK, VSLIDE1UP_VX, 0x5, 0x0 }, // 7715
|
|
{ PseudoVSLIDE1UP_VX_MF4, VSLIDE1UP_VX, 0x6, 0x0 }, // 7716
|
|
{ PseudoVSLIDE1UP_VX_MF4_MASK, VSLIDE1UP_VX, 0x6, 0x0 }, // 7717
|
|
{ PseudoVSLIDE1UP_VX_MF2, VSLIDE1UP_VX, 0x7, 0x0 }, // 7718
|
|
{ PseudoVSLIDE1UP_VX_MF2_MASK, VSLIDE1UP_VX, 0x7, 0x0 }, // 7719
|
|
{ PseudoVSLIDEDOWN_VI_M1, VSLIDEDOWN_VI, 0x0, 0x0 }, // 7720
|
|
{ PseudoVSLIDEDOWN_VI_M1_MASK, VSLIDEDOWN_VI, 0x0, 0x0 }, // 7721
|
|
{ PseudoVSLIDEDOWN_VI_M2, VSLIDEDOWN_VI, 0x1, 0x0 }, // 7722
|
|
{ PseudoVSLIDEDOWN_VI_M2_MASK, VSLIDEDOWN_VI, 0x1, 0x0 }, // 7723
|
|
{ PseudoVSLIDEDOWN_VI_M4, VSLIDEDOWN_VI, 0x2, 0x0 }, // 7724
|
|
{ PseudoVSLIDEDOWN_VI_M4_MASK, VSLIDEDOWN_VI, 0x2, 0x0 }, // 7725
|
|
{ PseudoVSLIDEDOWN_VI_M8, VSLIDEDOWN_VI, 0x3, 0x0 }, // 7726
|
|
{ PseudoVSLIDEDOWN_VI_M8_MASK, VSLIDEDOWN_VI, 0x3, 0x0 }, // 7727
|
|
{ PseudoVSLIDEDOWN_VI_MF8, VSLIDEDOWN_VI, 0x5, 0x0 }, // 7728
|
|
{ PseudoVSLIDEDOWN_VI_MF8_MASK, VSLIDEDOWN_VI, 0x5, 0x0 }, // 7729
|
|
{ PseudoVSLIDEDOWN_VI_MF4, VSLIDEDOWN_VI, 0x6, 0x0 }, // 7730
|
|
{ PseudoVSLIDEDOWN_VI_MF4_MASK, VSLIDEDOWN_VI, 0x6, 0x0 }, // 7731
|
|
{ PseudoVSLIDEDOWN_VI_MF2, VSLIDEDOWN_VI, 0x7, 0x0 }, // 7732
|
|
{ PseudoVSLIDEDOWN_VI_MF2_MASK, VSLIDEDOWN_VI, 0x7, 0x0 }, // 7733
|
|
{ PseudoVSLIDEDOWN_VX_M1, VSLIDEDOWN_VX, 0x0, 0x0 }, // 7734
|
|
{ PseudoVSLIDEDOWN_VX_M1_MASK, VSLIDEDOWN_VX, 0x0, 0x0 }, // 7735
|
|
{ PseudoVSLIDEDOWN_VX_M2, VSLIDEDOWN_VX, 0x1, 0x0 }, // 7736
|
|
{ PseudoVSLIDEDOWN_VX_M2_MASK, VSLIDEDOWN_VX, 0x1, 0x0 }, // 7737
|
|
{ PseudoVSLIDEDOWN_VX_M4, VSLIDEDOWN_VX, 0x2, 0x0 }, // 7738
|
|
{ PseudoVSLIDEDOWN_VX_M4_MASK, VSLIDEDOWN_VX, 0x2, 0x0 }, // 7739
|
|
{ PseudoVSLIDEDOWN_VX_M8, VSLIDEDOWN_VX, 0x3, 0x0 }, // 7740
|
|
{ PseudoVSLIDEDOWN_VX_M8_MASK, VSLIDEDOWN_VX, 0x3, 0x0 }, // 7741
|
|
{ PseudoVSLIDEDOWN_VX_MF8, VSLIDEDOWN_VX, 0x5, 0x0 }, // 7742
|
|
{ PseudoVSLIDEDOWN_VX_MF8_MASK, VSLIDEDOWN_VX, 0x5, 0x0 }, // 7743
|
|
{ PseudoVSLIDEDOWN_VX_MF4, VSLIDEDOWN_VX, 0x6, 0x0 }, // 7744
|
|
{ PseudoVSLIDEDOWN_VX_MF4_MASK, VSLIDEDOWN_VX, 0x6, 0x0 }, // 7745
|
|
{ PseudoVSLIDEDOWN_VX_MF2, VSLIDEDOWN_VX, 0x7, 0x0 }, // 7746
|
|
{ PseudoVSLIDEDOWN_VX_MF2_MASK, VSLIDEDOWN_VX, 0x7, 0x0 }, // 7747
|
|
{ PseudoVSLIDEUP_VI_M1, VSLIDEUP_VI, 0x0, 0x0 }, // 7748
|
|
{ PseudoVSLIDEUP_VI_M1_MASK, VSLIDEUP_VI, 0x0, 0x0 }, // 7749
|
|
{ PseudoVSLIDEUP_VI_M2, VSLIDEUP_VI, 0x1, 0x0 }, // 7750
|
|
{ PseudoVSLIDEUP_VI_M2_MASK, VSLIDEUP_VI, 0x1, 0x0 }, // 7751
|
|
{ PseudoVSLIDEUP_VI_M4, VSLIDEUP_VI, 0x2, 0x0 }, // 7752
|
|
{ PseudoVSLIDEUP_VI_M4_MASK, VSLIDEUP_VI, 0x2, 0x0 }, // 7753
|
|
{ PseudoVSLIDEUP_VI_M8, VSLIDEUP_VI, 0x3, 0x0 }, // 7754
|
|
{ PseudoVSLIDEUP_VI_M8_MASK, VSLIDEUP_VI, 0x3, 0x0 }, // 7755
|
|
{ PseudoVSLIDEUP_VI_MF8, VSLIDEUP_VI, 0x5, 0x0 }, // 7756
|
|
{ PseudoVSLIDEUP_VI_MF8_MASK, VSLIDEUP_VI, 0x5, 0x0 }, // 7757
|
|
{ PseudoVSLIDEUP_VI_MF4, VSLIDEUP_VI, 0x6, 0x0 }, // 7758
|
|
{ PseudoVSLIDEUP_VI_MF4_MASK, VSLIDEUP_VI, 0x6, 0x0 }, // 7759
|
|
{ PseudoVSLIDEUP_VI_MF2, VSLIDEUP_VI, 0x7, 0x0 }, // 7760
|
|
{ PseudoVSLIDEUP_VI_MF2_MASK, VSLIDEUP_VI, 0x7, 0x0 }, // 7761
|
|
{ PseudoVSLIDEUP_VX_M1, VSLIDEUP_VX, 0x0, 0x0 }, // 7762
|
|
{ PseudoVSLIDEUP_VX_M1_MASK, VSLIDEUP_VX, 0x0, 0x0 }, // 7763
|
|
{ PseudoVSLIDEUP_VX_M2, VSLIDEUP_VX, 0x1, 0x0 }, // 7764
|
|
{ PseudoVSLIDEUP_VX_M2_MASK, VSLIDEUP_VX, 0x1, 0x0 }, // 7765
|
|
{ PseudoVSLIDEUP_VX_M4, VSLIDEUP_VX, 0x2, 0x0 }, // 7766
|
|
{ PseudoVSLIDEUP_VX_M4_MASK, VSLIDEUP_VX, 0x2, 0x0 }, // 7767
|
|
{ PseudoVSLIDEUP_VX_M8, VSLIDEUP_VX, 0x3, 0x0 }, // 7768
|
|
{ PseudoVSLIDEUP_VX_M8_MASK, VSLIDEUP_VX, 0x3, 0x0 }, // 7769
|
|
{ PseudoVSLIDEUP_VX_MF8, VSLIDEUP_VX, 0x5, 0x0 }, // 7770
|
|
{ PseudoVSLIDEUP_VX_MF8_MASK, VSLIDEUP_VX, 0x5, 0x0 }, // 7771
|
|
{ PseudoVSLIDEUP_VX_MF4, VSLIDEUP_VX, 0x6, 0x0 }, // 7772
|
|
{ PseudoVSLIDEUP_VX_MF4_MASK, VSLIDEUP_VX, 0x6, 0x0 }, // 7773
|
|
{ PseudoVSLIDEUP_VX_MF2, VSLIDEUP_VX, 0x7, 0x0 }, // 7774
|
|
{ PseudoVSLIDEUP_VX_MF2_MASK, VSLIDEUP_VX, 0x7, 0x0 }, // 7775
|
|
{ PseudoVSLL_VI_M1, VSLL_VI, 0x0, 0x0 }, // 7776
|
|
{ PseudoVSLL_VI_M1_MASK, VSLL_VI, 0x0, 0x0 }, // 7777
|
|
{ PseudoVSLL_VI_M2, VSLL_VI, 0x1, 0x0 }, // 7778
|
|
{ PseudoVSLL_VI_M2_MASK, VSLL_VI, 0x1, 0x0 }, // 7779
|
|
{ PseudoVSLL_VI_M4, VSLL_VI, 0x2, 0x0 }, // 7780
|
|
{ PseudoVSLL_VI_M4_MASK, VSLL_VI, 0x2, 0x0 }, // 7781
|
|
{ PseudoVSLL_VI_M8, VSLL_VI, 0x3, 0x0 }, // 7782
|
|
{ PseudoVSLL_VI_M8_MASK, VSLL_VI, 0x3, 0x0 }, // 7783
|
|
{ PseudoVSLL_VI_MF8, VSLL_VI, 0x5, 0x0 }, // 7784
|
|
{ PseudoVSLL_VI_MF8_MASK, VSLL_VI, 0x5, 0x0 }, // 7785
|
|
{ PseudoVSLL_VI_MF4, VSLL_VI, 0x6, 0x0 }, // 7786
|
|
{ PseudoVSLL_VI_MF4_MASK, VSLL_VI, 0x6, 0x0 }, // 7787
|
|
{ PseudoVSLL_VI_MF2, VSLL_VI, 0x7, 0x0 }, // 7788
|
|
{ PseudoVSLL_VI_MF2_MASK, VSLL_VI, 0x7, 0x0 }, // 7789
|
|
{ PseudoVSLL_VV_M1, VSLL_VV, 0x0, 0x0 }, // 7790
|
|
{ PseudoVSLL_VV_M1_MASK, VSLL_VV, 0x0, 0x0 }, // 7791
|
|
{ PseudoVSLL_VV_M2, VSLL_VV, 0x1, 0x0 }, // 7792
|
|
{ PseudoVSLL_VV_M2_MASK, VSLL_VV, 0x1, 0x0 }, // 7793
|
|
{ PseudoVSLL_VV_M4, VSLL_VV, 0x2, 0x0 }, // 7794
|
|
{ PseudoVSLL_VV_M4_MASK, VSLL_VV, 0x2, 0x0 }, // 7795
|
|
{ PseudoVSLL_VV_M8, VSLL_VV, 0x3, 0x0 }, // 7796
|
|
{ PseudoVSLL_VV_M8_MASK, VSLL_VV, 0x3, 0x0 }, // 7797
|
|
{ PseudoVSLL_VV_MF8, VSLL_VV, 0x5, 0x0 }, // 7798
|
|
{ PseudoVSLL_VV_MF8_MASK, VSLL_VV, 0x5, 0x0 }, // 7799
|
|
{ PseudoVSLL_VV_MF4, VSLL_VV, 0x6, 0x0 }, // 7800
|
|
{ PseudoVSLL_VV_MF4_MASK, VSLL_VV, 0x6, 0x0 }, // 7801
|
|
{ PseudoVSLL_VV_MF2, VSLL_VV, 0x7, 0x0 }, // 7802
|
|
{ PseudoVSLL_VV_MF2_MASK, VSLL_VV, 0x7, 0x0 }, // 7803
|
|
{ PseudoVSLL_VX_M1, VSLL_VX, 0x0, 0x0 }, // 7804
|
|
{ PseudoVSLL_VX_M1_MASK, VSLL_VX, 0x0, 0x0 }, // 7805
|
|
{ PseudoVSLL_VX_M2, VSLL_VX, 0x1, 0x0 }, // 7806
|
|
{ PseudoVSLL_VX_M2_MASK, VSLL_VX, 0x1, 0x0 }, // 7807
|
|
{ PseudoVSLL_VX_M4, VSLL_VX, 0x2, 0x0 }, // 7808
|
|
{ PseudoVSLL_VX_M4_MASK, VSLL_VX, 0x2, 0x0 }, // 7809
|
|
{ PseudoVSLL_VX_M8, VSLL_VX, 0x3, 0x0 }, // 7810
|
|
{ PseudoVSLL_VX_M8_MASK, VSLL_VX, 0x3, 0x0 }, // 7811
|
|
{ PseudoVSLL_VX_MF8, VSLL_VX, 0x5, 0x0 }, // 7812
|
|
{ PseudoVSLL_VX_MF8_MASK, VSLL_VX, 0x5, 0x0 }, // 7813
|
|
{ PseudoVSLL_VX_MF4, VSLL_VX, 0x6, 0x0 }, // 7814
|
|
{ PseudoVSLL_VX_MF4_MASK, VSLL_VX, 0x6, 0x0 }, // 7815
|
|
{ PseudoVSLL_VX_MF2, VSLL_VX, 0x7, 0x0 }, // 7816
|
|
{ PseudoVSLL_VX_MF2_MASK, VSLL_VX, 0x7, 0x0 }, // 7817
|
|
{ PseudoVSM3C_VI_M1, VSM3C_VI, 0x0, 0x0 }, // 7818
|
|
{ PseudoVSM3C_VI_M2, VSM3C_VI, 0x1, 0x0 }, // 7819
|
|
{ PseudoVSM3C_VI_M4, VSM3C_VI, 0x2, 0x0 }, // 7820
|
|
{ PseudoVSM3C_VI_M8, VSM3C_VI, 0x3, 0x0 }, // 7821
|
|
{ PseudoVSM3C_VI_MF2, VSM3C_VI, 0x7, 0x0 }, // 7822
|
|
{ PseudoVSM3ME_VV_M1, VSM3ME_VV, 0x0, 0x0 }, // 7823
|
|
{ PseudoVSM3ME_VV_M2, VSM3ME_VV, 0x1, 0x0 }, // 7824
|
|
{ PseudoVSM3ME_VV_M4, VSM3ME_VV, 0x2, 0x0 }, // 7825
|
|
{ PseudoVSM3ME_VV_M8, VSM3ME_VV, 0x3, 0x0 }, // 7826
|
|
{ PseudoVSM3ME_VV_MF2, VSM3ME_VV, 0x7, 0x0 }, // 7827
|
|
{ PseudoVSM4K_VI_M1, VSM4K_VI, 0x0, 0x0 }, // 7828
|
|
{ PseudoVSM4K_VI_M2, VSM4K_VI, 0x1, 0x0 }, // 7829
|
|
{ PseudoVSM4K_VI_M4, VSM4K_VI, 0x2, 0x0 }, // 7830
|
|
{ PseudoVSM4K_VI_M8, VSM4K_VI, 0x3, 0x0 }, // 7831
|
|
{ PseudoVSM4K_VI_MF2, VSM4K_VI, 0x7, 0x0 }, // 7832
|
|
{ PseudoVSM4R_VS_M1_M1, VSM4R_VS, 0x0, 0x0 }, // 7833
|
|
{ PseudoVSM4R_VS_M1_MF2, VSM4R_VS, 0x0, 0x0 }, // 7834
|
|
{ PseudoVSM4R_VS_M1_MF4, VSM4R_VS, 0x0, 0x0 }, // 7835
|
|
{ PseudoVSM4R_VS_M1_MF8, VSM4R_VS, 0x0, 0x0 }, // 7836
|
|
{ PseudoVSM4R_VS_M2_M1, VSM4R_VS, 0x1, 0x0 }, // 7837
|
|
{ PseudoVSM4R_VS_M2_M2, VSM4R_VS, 0x1, 0x0 }, // 7838
|
|
{ PseudoVSM4R_VS_M2_MF2, VSM4R_VS, 0x1, 0x0 }, // 7839
|
|
{ PseudoVSM4R_VS_M2_MF4, VSM4R_VS, 0x1, 0x0 }, // 7840
|
|
{ PseudoVSM4R_VS_M2_MF8, VSM4R_VS, 0x1, 0x0 }, // 7841
|
|
{ PseudoVSM4R_VS_M4_M1, VSM4R_VS, 0x2, 0x0 }, // 7842
|
|
{ PseudoVSM4R_VS_M4_M2, VSM4R_VS, 0x2, 0x0 }, // 7843
|
|
{ PseudoVSM4R_VS_M4_M4, VSM4R_VS, 0x2, 0x0 }, // 7844
|
|
{ PseudoVSM4R_VS_M4_MF2, VSM4R_VS, 0x2, 0x0 }, // 7845
|
|
{ PseudoVSM4R_VS_M4_MF4, VSM4R_VS, 0x2, 0x0 }, // 7846
|
|
{ PseudoVSM4R_VS_M4_MF8, VSM4R_VS, 0x2, 0x0 }, // 7847
|
|
{ PseudoVSM4R_VS_M8_M1, VSM4R_VS, 0x3, 0x0 }, // 7848
|
|
{ PseudoVSM4R_VS_M8_M2, VSM4R_VS, 0x3, 0x0 }, // 7849
|
|
{ PseudoVSM4R_VS_M8_M4, VSM4R_VS, 0x3, 0x0 }, // 7850
|
|
{ PseudoVSM4R_VS_M8_MF2, VSM4R_VS, 0x3, 0x0 }, // 7851
|
|
{ PseudoVSM4R_VS_M8_MF4, VSM4R_VS, 0x3, 0x0 }, // 7852
|
|
{ PseudoVSM4R_VS_M8_MF8, VSM4R_VS, 0x3, 0x0 }, // 7853
|
|
{ PseudoVSM4R_VS_MF2_MF2, VSM4R_VS, 0x7, 0x0 }, // 7854
|
|
{ PseudoVSM4R_VS_MF2_MF4, VSM4R_VS, 0x7, 0x0 }, // 7855
|
|
{ PseudoVSM4R_VS_MF2_MF8, VSM4R_VS, 0x7, 0x0 }, // 7856
|
|
{ PseudoVSM4R_VV_M1, VSM4R_VV, 0x0, 0x0 }, // 7857
|
|
{ PseudoVSM4R_VV_M2, VSM4R_VV, 0x1, 0x0 }, // 7858
|
|
{ PseudoVSM4R_VV_M4, VSM4R_VV, 0x2, 0x0 }, // 7859
|
|
{ PseudoVSM4R_VV_M8, VSM4R_VV, 0x3, 0x0 }, // 7860
|
|
{ PseudoVSM4R_VV_MF2, VSM4R_VV, 0x7, 0x0 }, // 7861
|
|
{ PseudoVSMUL_VV_M1, VSMUL_VV, 0x0, 0x0 }, // 7862
|
|
{ PseudoVSMUL_VV_M1_MASK, VSMUL_VV, 0x0, 0x0 }, // 7863
|
|
{ PseudoVSMUL_VV_M2, VSMUL_VV, 0x1, 0x0 }, // 7864
|
|
{ PseudoVSMUL_VV_M2_MASK, VSMUL_VV, 0x1, 0x0 }, // 7865
|
|
{ PseudoVSMUL_VV_M4, VSMUL_VV, 0x2, 0x0 }, // 7866
|
|
{ PseudoVSMUL_VV_M4_MASK, VSMUL_VV, 0x2, 0x0 }, // 7867
|
|
{ PseudoVSMUL_VV_M8, VSMUL_VV, 0x3, 0x0 }, // 7868
|
|
{ PseudoVSMUL_VV_M8_MASK, VSMUL_VV, 0x3, 0x0 }, // 7869
|
|
{ PseudoVSMUL_VV_MF8, VSMUL_VV, 0x5, 0x0 }, // 7870
|
|
{ PseudoVSMUL_VV_MF8_MASK, VSMUL_VV, 0x5, 0x0 }, // 7871
|
|
{ PseudoVSMUL_VV_MF4, VSMUL_VV, 0x6, 0x0 }, // 7872
|
|
{ PseudoVSMUL_VV_MF4_MASK, VSMUL_VV, 0x6, 0x0 }, // 7873
|
|
{ PseudoVSMUL_VV_MF2, VSMUL_VV, 0x7, 0x0 }, // 7874
|
|
{ PseudoVSMUL_VV_MF2_MASK, VSMUL_VV, 0x7, 0x0 }, // 7875
|
|
{ PseudoVSMUL_VX_M1, VSMUL_VX, 0x0, 0x0 }, // 7876
|
|
{ PseudoVSMUL_VX_M1_MASK, VSMUL_VX, 0x0, 0x0 }, // 7877
|
|
{ PseudoVSMUL_VX_M2, VSMUL_VX, 0x1, 0x0 }, // 7878
|
|
{ PseudoVSMUL_VX_M2_MASK, VSMUL_VX, 0x1, 0x0 }, // 7879
|
|
{ PseudoVSMUL_VX_M4, VSMUL_VX, 0x2, 0x0 }, // 7880
|
|
{ PseudoVSMUL_VX_M4_MASK, VSMUL_VX, 0x2, 0x0 }, // 7881
|
|
{ PseudoVSMUL_VX_M8, VSMUL_VX, 0x3, 0x0 }, // 7882
|
|
{ PseudoVSMUL_VX_M8_MASK, VSMUL_VX, 0x3, 0x0 }, // 7883
|
|
{ PseudoVSMUL_VX_MF8, VSMUL_VX, 0x5, 0x0 }, // 7884
|
|
{ PseudoVSMUL_VX_MF8_MASK, VSMUL_VX, 0x5, 0x0 }, // 7885
|
|
{ PseudoVSMUL_VX_MF4, VSMUL_VX, 0x6, 0x0 }, // 7886
|
|
{ PseudoVSMUL_VX_MF4_MASK, VSMUL_VX, 0x6, 0x0 }, // 7887
|
|
{ PseudoVSMUL_VX_MF2, VSMUL_VX, 0x7, 0x0 }, // 7888
|
|
{ PseudoVSMUL_VX_MF2_MASK, VSMUL_VX, 0x7, 0x0 }, // 7889
|
|
{ PseudoVSM_V_B8, VSM_V, 0x0, 0x0 }, // 7890
|
|
{ PseudoVSM_V_B16, VSM_V, 0x1, 0x0 }, // 7891
|
|
{ PseudoVSM_V_B32, VSM_V, 0x2, 0x0 }, // 7892
|
|
{ PseudoVSM_V_B64, VSM_V, 0x3, 0x0 }, // 7893
|
|
{ PseudoVSM_V_B1, VSM_V, 0x5, 0x0 }, // 7894
|
|
{ PseudoVSM_V_B2, VSM_V, 0x6, 0x0 }, // 7895
|
|
{ PseudoVSM_V_B4, VSM_V, 0x7, 0x0 }, // 7896
|
|
{ PseudoVSOXEI16_V_M1_M1, VSOXEI16_V, 0x0, 0x0 }, // 7897
|
|
{ PseudoVSOXEI16_V_M1_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7898
|
|
{ PseudoVSOXEI16_V_M2_M1, VSOXEI16_V, 0x0, 0x0 }, // 7899
|
|
{ PseudoVSOXEI16_V_M2_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7900
|
|
{ PseudoVSOXEI16_V_MF2_M1, VSOXEI16_V, 0x0, 0x0 }, // 7901
|
|
{ PseudoVSOXEI16_V_MF2_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7902
|
|
{ PseudoVSOXEI16_V_MF4_M1, VSOXEI16_V, 0x0, 0x0 }, // 7903
|
|
{ PseudoVSOXEI16_V_MF4_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7904
|
|
{ PseudoVSOXEI16_V_M1_M2, VSOXEI16_V, 0x1, 0x0 }, // 7905
|
|
{ PseudoVSOXEI16_V_M1_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7906
|
|
{ PseudoVSOXEI16_V_M2_M2, VSOXEI16_V, 0x1, 0x0 }, // 7907
|
|
{ PseudoVSOXEI16_V_M2_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7908
|
|
{ PseudoVSOXEI16_V_M4_M2, VSOXEI16_V, 0x1, 0x0 }, // 7909
|
|
{ PseudoVSOXEI16_V_M4_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7910
|
|
{ PseudoVSOXEI16_V_MF2_M2, VSOXEI16_V, 0x1, 0x0 }, // 7911
|
|
{ PseudoVSOXEI16_V_MF2_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7912
|
|
{ PseudoVSOXEI16_V_M1_M4, VSOXEI16_V, 0x2, 0x0 }, // 7913
|
|
{ PseudoVSOXEI16_V_M1_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7914
|
|
{ PseudoVSOXEI16_V_M2_M4, VSOXEI16_V, 0x2, 0x0 }, // 7915
|
|
{ PseudoVSOXEI16_V_M2_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7916
|
|
{ PseudoVSOXEI16_V_M4_M4, VSOXEI16_V, 0x2, 0x0 }, // 7917
|
|
{ PseudoVSOXEI16_V_M4_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7918
|
|
{ PseudoVSOXEI16_V_M8_M4, VSOXEI16_V, 0x2, 0x0 }, // 7919
|
|
{ PseudoVSOXEI16_V_M8_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7920
|
|
{ PseudoVSOXEI16_V_M2_M8, VSOXEI16_V, 0x3, 0x0 }, // 7921
|
|
{ PseudoVSOXEI16_V_M2_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 7922
|
|
{ PseudoVSOXEI16_V_M4_M8, VSOXEI16_V, 0x3, 0x0 }, // 7923
|
|
{ PseudoVSOXEI16_V_M4_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 7924
|
|
{ PseudoVSOXEI16_V_M8_M8, VSOXEI16_V, 0x3, 0x0 }, // 7925
|
|
{ PseudoVSOXEI16_V_M8_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 7926
|
|
{ PseudoVSOXEI16_V_MF4_MF8, VSOXEI16_V, 0x5, 0x0 }, // 7927
|
|
{ PseudoVSOXEI16_V_MF4_MF8_MASK, VSOXEI16_V, 0x5, 0x0 }, // 7928
|
|
{ PseudoVSOXEI16_V_MF2_MF4, VSOXEI16_V, 0x6, 0x0 }, // 7929
|
|
{ PseudoVSOXEI16_V_MF2_MF4_MASK, VSOXEI16_V, 0x6, 0x0 }, // 7930
|
|
{ PseudoVSOXEI16_V_MF4_MF4, VSOXEI16_V, 0x6, 0x0 }, // 7931
|
|
{ PseudoVSOXEI16_V_MF4_MF4_MASK, VSOXEI16_V, 0x6, 0x0 }, // 7932
|
|
{ PseudoVSOXEI16_V_M1_MF2, VSOXEI16_V, 0x7, 0x0 }, // 7933
|
|
{ PseudoVSOXEI16_V_M1_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 7934
|
|
{ PseudoVSOXEI16_V_MF2_MF2, VSOXEI16_V, 0x7, 0x0 }, // 7935
|
|
{ PseudoVSOXEI16_V_MF2_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 7936
|
|
{ PseudoVSOXEI16_V_MF4_MF2, VSOXEI16_V, 0x7, 0x0 }, // 7937
|
|
{ PseudoVSOXEI16_V_MF4_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 7938
|
|
{ PseudoVSOXEI32_V_M1_M1, VSOXEI32_V, 0x0, 0x0 }, // 7939
|
|
{ PseudoVSOXEI32_V_M1_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7940
|
|
{ PseudoVSOXEI32_V_M2_M1, VSOXEI32_V, 0x0, 0x0 }, // 7941
|
|
{ PseudoVSOXEI32_V_M2_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7942
|
|
{ PseudoVSOXEI32_V_M4_M1, VSOXEI32_V, 0x0, 0x0 }, // 7943
|
|
{ PseudoVSOXEI32_V_M4_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7944
|
|
{ PseudoVSOXEI32_V_MF2_M1, VSOXEI32_V, 0x0, 0x0 }, // 7945
|
|
{ PseudoVSOXEI32_V_MF2_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7946
|
|
{ PseudoVSOXEI32_V_M1_M2, VSOXEI32_V, 0x1, 0x0 }, // 7947
|
|
{ PseudoVSOXEI32_V_M1_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7948
|
|
{ PseudoVSOXEI32_V_M2_M2, VSOXEI32_V, 0x1, 0x0 }, // 7949
|
|
{ PseudoVSOXEI32_V_M2_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7950
|
|
{ PseudoVSOXEI32_V_M4_M2, VSOXEI32_V, 0x1, 0x0 }, // 7951
|
|
{ PseudoVSOXEI32_V_M4_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7952
|
|
{ PseudoVSOXEI32_V_M8_M2, VSOXEI32_V, 0x1, 0x0 }, // 7953
|
|
{ PseudoVSOXEI32_V_M8_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7954
|
|
{ PseudoVSOXEI32_V_M2_M4, VSOXEI32_V, 0x2, 0x0 }, // 7955
|
|
{ PseudoVSOXEI32_V_M2_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 7956
|
|
{ PseudoVSOXEI32_V_M4_M4, VSOXEI32_V, 0x2, 0x0 }, // 7957
|
|
{ PseudoVSOXEI32_V_M4_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 7958
|
|
{ PseudoVSOXEI32_V_M8_M4, VSOXEI32_V, 0x2, 0x0 }, // 7959
|
|
{ PseudoVSOXEI32_V_M8_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 7960
|
|
{ PseudoVSOXEI32_V_M4_M8, VSOXEI32_V, 0x3, 0x0 }, // 7961
|
|
{ PseudoVSOXEI32_V_M4_M8_MASK, VSOXEI32_V, 0x3, 0x0 }, // 7962
|
|
{ PseudoVSOXEI32_V_M8_M8, VSOXEI32_V, 0x3, 0x0 }, // 7963
|
|
{ PseudoVSOXEI32_V_M8_M8_MASK, VSOXEI32_V, 0x3, 0x0 }, // 7964
|
|
{ PseudoVSOXEI32_V_MF2_MF8, VSOXEI32_V, 0x5, 0x0 }, // 7965
|
|
{ PseudoVSOXEI32_V_MF2_MF8_MASK, VSOXEI32_V, 0x5, 0x0 }, // 7966
|
|
{ PseudoVSOXEI32_V_M1_MF4, VSOXEI32_V, 0x6, 0x0 }, // 7967
|
|
{ PseudoVSOXEI32_V_M1_MF4_MASK, VSOXEI32_V, 0x6, 0x0 }, // 7968
|
|
{ PseudoVSOXEI32_V_MF2_MF4, VSOXEI32_V, 0x6, 0x0 }, // 7969
|
|
{ PseudoVSOXEI32_V_MF2_MF4_MASK, VSOXEI32_V, 0x6, 0x0 }, // 7970
|
|
{ PseudoVSOXEI32_V_M1_MF2, VSOXEI32_V, 0x7, 0x0 }, // 7971
|
|
{ PseudoVSOXEI32_V_M1_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 7972
|
|
{ PseudoVSOXEI32_V_M2_MF2, VSOXEI32_V, 0x7, 0x0 }, // 7973
|
|
{ PseudoVSOXEI32_V_M2_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 7974
|
|
{ PseudoVSOXEI32_V_MF2_MF2, VSOXEI32_V, 0x7, 0x0 }, // 7975
|
|
{ PseudoVSOXEI32_V_MF2_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 7976
|
|
{ PseudoVSOXEI64_V_M1_M1, VSOXEI64_V, 0x0, 0x0 }, // 7977
|
|
{ PseudoVSOXEI64_V_M1_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7978
|
|
{ PseudoVSOXEI64_V_M2_M1, VSOXEI64_V, 0x0, 0x0 }, // 7979
|
|
{ PseudoVSOXEI64_V_M2_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7980
|
|
{ PseudoVSOXEI64_V_M4_M1, VSOXEI64_V, 0x0, 0x0 }, // 7981
|
|
{ PseudoVSOXEI64_V_M4_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7982
|
|
{ PseudoVSOXEI64_V_M8_M1, VSOXEI64_V, 0x0, 0x0 }, // 7983
|
|
{ PseudoVSOXEI64_V_M8_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7984
|
|
{ PseudoVSOXEI64_V_M2_M2, VSOXEI64_V, 0x1, 0x0 }, // 7985
|
|
{ PseudoVSOXEI64_V_M2_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 7986
|
|
{ PseudoVSOXEI64_V_M4_M2, VSOXEI64_V, 0x1, 0x0 }, // 7987
|
|
{ PseudoVSOXEI64_V_M4_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 7988
|
|
{ PseudoVSOXEI64_V_M8_M2, VSOXEI64_V, 0x1, 0x0 }, // 7989
|
|
{ PseudoVSOXEI64_V_M8_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 7990
|
|
{ PseudoVSOXEI64_V_M4_M4, VSOXEI64_V, 0x2, 0x0 }, // 7991
|
|
{ PseudoVSOXEI64_V_M4_M4_MASK, VSOXEI64_V, 0x2, 0x0 }, // 7992
|
|
{ PseudoVSOXEI64_V_M8_M4, VSOXEI64_V, 0x2, 0x0 }, // 7993
|
|
{ PseudoVSOXEI64_V_M8_M4_MASK, VSOXEI64_V, 0x2, 0x0 }, // 7994
|
|
{ PseudoVSOXEI64_V_M8_M8, VSOXEI64_V, 0x3, 0x0 }, // 7995
|
|
{ PseudoVSOXEI64_V_M8_M8_MASK, VSOXEI64_V, 0x3, 0x0 }, // 7996
|
|
{ PseudoVSOXEI64_V_M1_MF8, VSOXEI64_V, 0x5, 0x0 }, // 7997
|
|
{ PseudoVSOXEI64_V_M1_MF8_MASK, VSOXEI64_V, 0x5, 0x0 }, // 7998
|
|
{ PseudoVSOXEI64_V_M1_MF4, VSOXEI64_V, 0x6, 0x0 }, // 7999
|
|
{ PseudoVSOXEI64_V_M1_MF4_MASK, VSOXEI64_V, 0x6, 0x0 }, // 8000
|
|
{ PseudoVSOXEI64_V_M2_MF4, VSOXEI64_V, 0x6, 0x0 }, // 8001
|
|
{ PseudoVSOXEI64_V_M2_MF4_MASK, VSOXEI64_V, 0x6, 0x0 }, // 8002
|
|
{ PseudoVSOXEI64_V_M1_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8003
|
|
{ PseudoVSOXEI64_V_M1_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8004
|
|
{ PseudoVSOXEI64_V_M2_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8005
|
|
{ PseudoVSOXEI64_V_M2_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8006
|
|
{ PseudoVSOXEI64_V_M4_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8007
|
|
{ PseudoVSOXEI64_V_M4_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8008
|
|
{ PseudoVSOXEI8_V_M1_M1, VSOXEI8_V, 0x0, 0x0 }, // 8009
|
|
{ PseudoVSOXEI8_V_M1_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8010
|
|
{ PseudoVSOXEI8_V_MF2_M1, VSOXEI8_V, 0x0, 0x0 }, // 8011
|
|
{ PseudoVSOXEI8_V_MF2_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8012
|
|
{ PseudoVSOXEI8_V_MF4_M1, VSOXEI8_V, 0x0, 0x0 }, // 8013
|
|
{ PseudoVSOXEI8_V_MF4_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8014
|
|
{ PseudoVSOXEI8_V_MF8_M1, VSOXEI8_V, 0x0, 0x0 }, // 8015
|
|
{ PseudoVSOXEI8_V_MF8_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8016
|
|
{ PseudoVSOXEI8_V_M1_M2, VSOXEI8_V, 0x1, 0x0 }, // 8017
|
|
{ PseudoVSOXEI8_V_M1_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8018
|
|
{ PseudoVSOXEI8_V_M2_M2, VSOXEI8_V, 0x1, 0x0 }, // 8019
|
|
{ PseudoVSOXEI8_V_M2_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8020
|
|
{ PseudoVSOXEI8_V_MF2_M2, VSOXEI8_V, 0x1, 0x0 }, // 8021
|
|
{ PseudoVSOXEI8_V_MF2_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8022
|
|
{ PseudoVSOXEI8_V_MF4_M2, VSOXEI8_V, 0x1, 0x0 }, // 8023
|
|
{ PseudoVSOXEI8_V_MF4_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8024
|
|
{ PseudoVSOXEI8_V_M1_M4, VSOXEI8_V, 0x2, 0x0 }, // 8025
|
|
{ PseudoVSOXEI8_V_M1_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8026
|
|
{ PseudoVSOXEI8_V_M2_M4, VSOXEI8_V, 0x2, 0x0 }, // 8027
|
|
{ PseudoVSOXEI8_V_M2_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8028
|
|
{ PseudoVSOXEI8_V_M4_M4, VSOXEI8_V, 0x2, 0x0 }, // 8029
|
|
{ PseudoVSOXEI8_V_M4_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8030
|
|
{ PseudoVSOXEI8_V_MF2_M4, VSOXEI8_V, 0x2, 0x0 }, // 8031
|
|
{ PseudoVSOXEI8_V_MF2_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8032
|
|
{ PseudoVSOXEI8_V_M1_M8, VSOXEI8_V, 0x3, 0x0 }, // 8033
|
|
{ PseudoVSOXEI8_V_M1_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8034
|
|
{ PseudoVSOXEI8_V_M2_M8, VSOXEI8_V, 0x3, 0x0 }, // 8035
|
|
{ PseudoVSOXEI8_V_M2_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8036
|
|
{ PseudoVSOXEI8_V_M4_M8, VSOXEI8_V, 0x3, 0x0 }, // 8037
|
|
{ PseudoVSOXEI8_V_M4_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8038
|
|
{ PseudoVSOXEI8_V_M8_M8, VSOXEI8_V, 0x3, 0x0 }, // 8039
|
|
{ PseudoVSOXEI8_V_M8_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8040
|
|
{ PseudoVSOXEI8_V_MF8_MF8, VSOXEI8_V, 0x5, 0x0 }, // 8041
|
|
{ PseudoVSOXEI8_V_MF8_MF8_MASK, VSOXEI8_V, 0x5, 0x0 }, // 8042
|
|
{ PseudoVSOXEI8_V_MF4_MF4, VSOXEI8_V, 0x6, 0x0 }, // 8043
|
|
{ PseudoVSOXEI8_V_MF4_MF4_MASK, VSOXEI8_V, 0x6, 0x0 }, // 8044
|
|
{ PseudoVSOXEI8_V_MF8_MF4, VSOXEI8_V, 0x6, 0x0 }, // 8045
|
|
{ PseudoVSOXEI8_V_MF8_MF4_MASK, VSOXEI8_V, 0x6, 0x0 }, // 8046
|
|
{ PseudoVSOXEI8_V_MF2_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8047
|
|
{ PseudoVSOXEI8_V_MF2_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8048
|
|
{ PseudoVSOXEI8_V_MF4_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8049
|
|
{ PseudoVSOXEI8_V_MF4_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8050
|
|
{ PseudoVSOXEI8_V_MF8_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8051
|
|
{ PseudoVSOXEI8_V_MF8_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8052
|
|
{ PseudoVSOXSEG2EI16_V_M1_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8053
|
|
{ PseudoVSOXSEG2EI16_V_M1_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8054
|
|
{ PseudoVSOXSEG2EI16_V_M2_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8055
|
|
{ PseudoVSOXSEG2EI16_V_M2_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8056
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8057
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8058
|
|
{ PseudoVSOXSEG2EI16_V_MF4_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8059
|
|
{ PseudoVSOXSEG2EI16_V_MF4_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8060
|
|
{ PseudoVSOXSEG2EI16_V_M1_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8061
|
|
{ PseudoVSOXSEG2EI16_V_M1_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8062
|
|
{ PseudoVSOXSEG2EI16_V_M2_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8063
|
|
{ PseudoVSOXSEG2EI16_V_M2_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8064
|
|
{ PseudoVSOXSEG2EI16_V_M4_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8065
|
|
{ PseudoVSOXSEG2EI16_V_M4_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8066
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8067
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8068
|
|
{ PseudoVSOXSEG2EI16_V_M1_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8069
|
|
{ PseudoVSOXSEG2EI16_V_M1_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8070
|
|
{ PseudoVSOXSEG2EI16_V_M2_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8071
|
|
{ PseudoVSOXSEG2EI16_V_M2_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8072
|
|
{ PseudoVSOXSEG2EI16_V_M4_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8073
|
|
{ PseudoVSOXSEG2EI16_V_M4_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8074
|
|
{ PseudoVSOXSEG2EI16_V_M8_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8075
|
|
{ PseudoVSOXSEG2EI16_V_M8_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8076
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF8, VSOXSEG2EI16_V, 0x5, 0x0 }, // 8077
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, VSOXSEG2EI16_V, 0x5, 0x0 }, // 8078
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF4, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8079
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8080
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF4, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8081
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8082
|
|
{ PseudoVSOXSEG2EI16_V_M1_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8083
|
|
{ PseudoVSOXSEG2EI16_V_M1_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8084
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8085
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8086
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8087
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8088
|
|
{ PseudoVSOXSEG2EI32_V_M1_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8089
|
|
{ PseudoVSOXSEG2EI32_V_M1_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8090
|
|
{ PseudoVSOXSEG2EI32_V_M2_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8091
|
|
{ PseudoVSOXSEG2EI32_V_M2_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8092
|
|
{ PseudoVSOXSEG2EI32_V_M4_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8093
|
|
{ PseudoVSOXSEG2EI32_V_M4_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8094
|
|
{ PseudoVSOXSEG2EI32_V_MF2_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8095
|
|
{ PseudoVSOXSEG2EI32_V_MF2_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8096
|
|
{ PseudoVSOXSEG2EI32_V_M1_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8097
|
|
{ PseudoVSOXSEG2EI32_V_M1_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8098
|
|
{ PseudoVSOXSEG2EI32_V_M2_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8099
|
|
{ PseudoVSOXSEG2EI32_V_M2_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8100
|
|
{ PseudoVSOXSEG2EI32_V_M4_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8101
|
|
{ PseudoVSOXSEG2EI32_V_M4_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8102
|
|
{ PseudoVSOXSEG2EI32_V_M8_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8103
|
|
{ PseudoVSOXSEG2EI32_V_M8_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8104
|
|
{ PseudoVSOXSEG2EI32_V_M2_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8105
|
|
{ PseudoVSOXSEG2EI32_V_M2_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8106
|
|
{ PseudoVSOXSEG2EI32_V_M4_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8107
|
|
{ PseudoVSOXSEG2EI32_V_M4_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8108
|
|
{ PseudoVSOXSEG2EI32_V_M8_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8109
|
|
{ PseudoVSOXSEG2EI32_V_M8_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8110
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF8, VSOXSEG2EI32_V, 0x5, 0x0 }, // 8111
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, VSOXSEG2EI32_V, 0x5, 0x0 }, // 8112
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF4, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8113
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF4_MASK, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8114
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF4, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8115
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8116
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8117
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8118
|
|
{ PseudoVSOXSEG2EI32_V_M2_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8119
|
|
{ PseudoVSOXSEG2EI32_V_M2_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8120
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8121
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8122
|
|
{ PseudoVSOXSEG2EI64_V_M1_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8123
|
|
{ PseudoVSOXSEG2EI64_V_M1_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8124
|
|
{ PseudoVSOXSEG2EI64_V_M2_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8125
|
|
{ PseudoVSOXSEG2EI64_V_M2_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8126
|
|
{ PseudoVSOXSEG2EI64_V_M4_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8127
|
|
{ PseudoVSOXSEG2EI64_V_M4_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8128
|
|
{ PseudoVSOXSEG2EI64_V_M8_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8129
|
|
{ PseudoVSOXSEG2EI64_V_M8_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8130
|
|
{ PseudoVSOXSEG2EI64_V_M2_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8131
|
|
{ PseudoVSOXSEG2EI64_V_M2_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8132
|
|
{ PseudoVSOXSEG2EI64_V_M4_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8133
|
|
{ PseudoVSOXSEG2EI64_V_M4_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8134
|
|
{ PseudoVSOXSEG2EI64_V_M8_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8135
|
|
{ PseudoVSOXSEG2EI64_V_M8_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8136
|
|
{ PseudoVSOXSEG2EI64_V_M4_M4, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8137
|
|
{ PseudoVSOXSEG2EI64_V_M4_M4_MASK, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8138
|
|
{ PseudoVSOXSEG2EI64_V_M8_M4, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8139
|
|
{ PseudoVSOXSEG2EI64_V_M8_M4_MASK, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8140
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF8, VSOXSEG2EI64_V, 0x5, 0x0 }, // 8141
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF8_MASK, VSOXSEG2EI64_V, 0x5, 0x0 }, // 8142
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF4, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8143
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF4_MASK, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8144
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF4, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8145
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF4_MASK, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8146
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8147
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8148
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8149
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8150
|
|
{ PseudoVSOXSEG2EI64_V_M4_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8151
|
|
{ PseudoVSOXSEG2EI64_V_M4_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8152
|
|
{ PseudoVSOXSEG2EI8_V_M1_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8153
|
|
{ PseudoVSOXSEG2EI8_V_M1_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8154
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8155
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8156
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8157
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8158
|
|
{ PseudoVSOXSEG2EI8_V_MF8_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8159
|
|
{ PseudoVSOXSEG2EI8_V_MF8_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8160
|
|
{ PseudoVSOXSEG2EI8_V_M1_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8161
|
|
{ PseudoVSOXSEG2EI8_V_M1_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8162
|
|
{ PseudoVSOXSEG2EI8_V_M2_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8163
|
|
{ PseudoVSOXSEG2EI8_V_M2_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8164
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8165
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8166
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8167
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8168
|
|
{ PseudoVSOXSEG2EI8_V_M1_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8169
|
|
{ PseudoVSOXSEG2EI8_V_M1_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8170
|
|
{ PseudoVSOXSEG2EI8_V_M2_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8171
|
|
{ PseudoVSOXSEG2EI8_V_M2_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8172
|
|
{ PseudoVSOXSEG2EI8_V_M4_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8173
|
|
{ PseudoVSOXSEG2EI8_V_M4_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8174
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8175
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8176
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF8, VSOXSEG2EI8_V, 0x5, 0x0 }, // 8177
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, VSOXSEG2EI8_V, 0x5, 0x0 }, // 8178
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF4, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8179
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8180
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF4, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8181
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8182
|
|
{ PseudoVSOXSEG2EI8_V_MF2_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8183
|
|
{ PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8184
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8185
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8186
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8187
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8188
|
|
{ PseudoVSOXSEG3EI16_V_M1_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8189
|
|
{ PseudoVSOXSEG3EI16_V_M1_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8190
|
|
{ PseudoVSOXSEG3EI16_V_M2_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8191
|
|
{ PseudoVSOXSEG3EI16_V_M2_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8192
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8193
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8194
|
|
{ PseudoVSOXSEG3EI16_V_MF4_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8195
|
|
{ PseudoVSOXSEG3EI16_V_MF4_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8196
|
|
{ PseudoVSOXSEG3EI16_V_M1_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8197
|
|
{ PseudoVSOXSEG3EI16_V_M1_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8198
|
|
{ PseudoVSOXSEG3EI16_V_M2_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8199
|
|
{ PseudoVSOXSEG3EI16_V_M2_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8200
|
|
{ PseudoVSOXSEG3EI16_V_M4_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8201
|
|
{ PseudoVSOXSEG3EI16_V_M4_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8202
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8203
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8204
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF8, VSOXSEG3EI16_V, 0x5, 0x0 }, // 8205
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, VSOXSEG3EI16_V, 0x5, 0x0 }, // 8206
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF4, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8207
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8208
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF4, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8209
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8210
|
|
{ PseudoVSOXSEG3EI16_V_M1_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8211
|
|
{ PseudoVSOXSEG3EI16_V_M1_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8212
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8213
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8214
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8215
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8216
|
|
{ PseudoVSOXSEG3EI32_V_M1_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8217
|
|
{ PseudoVSOXSEG3EI32_V_M1_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8218
|
|
{ PseudoVSOXSEG3EI32_V_M2_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8219
|
|
{ PseudoVSOXSEG3EI32_V_M2_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8220
|
|
{ PseudoVSOXSEG3EI32_V_M4_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8221
|
|
{ PseudoVSOXSEG3EI32_V_M4_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8222
|
|
{ PseudoVSOXSEG3EI32_V_MF2_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8223
|
|
{ PseudoVSOXSEG3EI32_V_MF2_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8224
|
|
{ PseudoVSOXSEG3EI32_V_M1_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8225
|
|
{ PseudoVSOXSEG3EI32_V_M1_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8226
|
|
{ PseudoVSOXSEG3EI32_V_M2_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8227
|
|
{ PseudoVSOXSEG3EI32_V_M2_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8228
|
|
{ PseudoVSOXSEG3EI32_V_M4_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8229
|
|
{ PseudoVSOXSEG3EI32_V_M4_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8230
|
|
{ PseudoVSOXSEG3EI32_V_M8_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8231
|
|
{ PseudoVSOXSEG3EI32_V_M8_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8232
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF8, VSOXSEG3EI32_V, 0x5, 0x0 }, // 8233
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, VSOXSEG3EI32_V, 0x5, 0x0 }, // 8234
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF4, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8235
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF4_MASK, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8236
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF4, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8237
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8238
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8239
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8240
|
|
{ PseudoVSOXSEG3EI32_V_M2_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8241
|
|
{ PseudoVSOXSEG3EI32_V_M2_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8242
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8243
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8244
|
|
{ PseudoVSOXSEG3EI64_V_M1_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8245
|
|
{ PseudoVSOXSEG3EI64_V_M1_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8246
|
|
{ PseudoVSOXSEG3EI64_V_M2_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8247
|
|
{ PseudoVSOXSEG3EI64_V_M2_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8248
|
|
{ PseudoVSOXSEG3EI64_V_M4_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8249
|
|
{ PseudoVSOXSEG3EI64_V_M4_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8250
|
|
{ PseudoVSOXSEG3EI64_V_M8_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8251
|
|
{ PseudoVSOXSEG3EI64_V_M8_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8252
|
|
{ PseudoVSOXSEG3EI64_V_M2_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8253
|
|
{ PseudoVSOXSEG3EI64_V_M2_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8254
|
|
{ PseudoVSOXSEG3EI64_V_M4_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8255
|
|
{ PseudoVSOXSEG3EI64_V_M4_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8256
|
|
{ PseudoVSOXSEG3EI64_V_M8_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8257
|
|
{ PseudoVSOXSEG3EI64_V_M8_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8258
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF8, VSOXSEG3EI64_V, 0x5, 0x0 }, // 8259
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF8_MASK, VSOXSEG3EI64_V, 0x5, 0x0 }, // 8260
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF4, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8261
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF4_MASK, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8262
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF4, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8263
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF4_MASK, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8264
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8265
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8266
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8267
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8268
|
|
{ PseudoVSOXSEG3EI64_V_M4_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8269
|
|
{ PseudoVSOXSEG3EI64_V_M4_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8270
|
|
{ PseudoVSOXSEG3EI8_V_M1_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8271
|
|
{ PseudoVSOXSEG3EI8_V_M1_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8272
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8273
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8274
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8275
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8276
|
|
{ PseudoVSOXSEG3EI8_V_MF8_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8277
|
|
{ PseudoVSOXSEG3EI8_V_MF8_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8278
|
|
{ PseudoVSOXSEG3EI8_V_M1_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8279
|
|
{ PseudoVSOXSEG3EI8_V_M1_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8280
|
|
{ PseudoVSOXSEG3EI8_V_M2_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8281
|
|
{ PseudoVSOXSEG3EI8_V_M2_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8282
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8283
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8284
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8285
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8286
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF8, VSOXSEG3EI8_V, 0x5, 0x0 }, // 8287
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, VSOXSEG3EI8_V, 0x5, 0x0 }, // 8288
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF4, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8289
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8290
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF4, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8291
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8292
|
|
{ PseudoVSOXSEG3EI8_V_MF2_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8293
|
|
{ PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8294
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8295
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8296
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8297
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8298
|
|
{ PseudoVSOXSEG4EI16_V_M1_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8299
|
|
{ PseudoVSOXSEG4EI16_V_M1_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8300
|
|
{ PseudoVSOXSEG4EI16_V_M2_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8301
|
|
{ PseudoVSOXSEG4EI16_V_M2_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8302
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8303
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8304
|
|
{ PseudoVSOXSEG4EI16_V_MF4_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8305
|
|
{ PseudoVSOXSEG4EI16_V_MF4_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8306
|
|
{ PseudoVSOXSEG4EI16_V_M1_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8307
|
|
{ PseudoVSOXSEG4EI16_V_M1_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8308
|
|
{ PseudoVSOXSEG4EI16_V_M2_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8309
|
|
{ PseudoVSOXSEG4EI16_V_M2_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8310
|
|
{ PseudoVSOXSEG4EI16_V_M4_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8311
|
|
{ PseudoVSOXSEG4EI16_V_M4_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8312
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8313
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8314
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF8, VSOXSEG4EI16_V, 0x5, 0x0 }, // 8315
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, VSOXSEG4EI16_V, 0x5, 0x0 }, // 8316
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF4, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8317
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8318
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF4, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8319
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8320
|
|
{ PseudoVSOXSEG4EI16_V_M1_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8321
|
|
{ PseudoVSOXSEG4EI16_V_M1_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8322
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8323
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8324
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8325
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8326
|
|
{ PseudoVSOXSEG4EI32_V_M1_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8327
|
|
{ PseudoVSOXSEG4EI32_V_M1_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8328
|
|
{ PseudoVSOXSEG4EI32_V_M2_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8329
|
|
{ PseudoVSOXSEG4EI32_V_M2_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8330
|
|
{ PseudoVSOXSEG4EI32_V_M4_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8331
|
|
{ PseudoVSOXSEG4EI32_V_M4_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8332
|
|
{ PseudoVSOXSEG4EI32_V_MF2_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8333
|
|
{ PseudoVSOXSEG4EI32_V_MF2_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8334
|
|
{ PseudoVSOXSEG4EI32_V_M1_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8335
|
|
{ PseudoVSOXSEG4EI32_V_M1_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8336
|
|
{ PseudoVSOXSEG4EI32_V_M2_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8337
|
|
{ PseudoVSOXSEG4EI32_V_M2_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8338
|
|
{ PseudoVSOXSEG4EI32_V_M4_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8339
|
|
{ PseudoVSOXSEG4EI32_V_M4_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8340
|
|
{ PseudoVSOXSEG4EI32_V_M8_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8341
|
|
{ PseudoVSOXSEG4EI32_V_M8_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8342
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF8, VSOXSEG4EI32_V, 0x5, 0x0 }, // 8343
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, VSOXSEG4EI32_V, 0x5, 0x0 }, // 8344
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF4, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8345
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF4_MASK, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8346
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF4, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8347
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8348
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8349
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8350
|
|
{ PseudoVSOXSEG4EI32_V_M2_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8351
|
|
{ PseudoVSOXSEG4EI32_V_M2_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8352
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8353
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8354
|
|
{ PseudoVSOXSEG4EI64_V_M1_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8355
|
|
{ PseudoVSOXSEG4EI64_V_M1_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8356
|
|
{ PseudoVSOXSEG4EI64_V_M2_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8357
|
|
{ PseudoVSOXSEG4EI64_V_M2_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8358
|
|
{ PseudoVSOXSEG4EI64_V_M4_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8359
|
|
{ PseudoVSOXSEG4EI64_V_M4_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8360
|
|
{ PseudoVSOXSEG4EI64_V_M8_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8361
|
|
{ PseudoVSOXSEG4EI64_V_M8_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8362
|
|
{ PseudoVSOXSEG4EI64_V_M2_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8363
|
|
{ PseudoVSOXSEG4EI64_V_M2_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8364
|
|
{ PseudoVSOXSEG4EI64_V_M4_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8365
|
|
{ PseudoVSOXSEG4EI64_V_M4_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8366
|
|
{ PseudoVSOXSEG4EI64_V_M8_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8367
|
|
{ PseudoVSOXSEG4EI64_V_M8_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8368
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF8, VSOXSEG4EI64_V, 0x5, 0x0 }, // 8369
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF8_MASK, VSOXSEG4EI64_V, 0x5, 0x0 }, // 8370
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF4, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8371
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF4_MASK, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8372
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF4, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8373
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF4_MASK, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8374
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8375
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8376
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8377
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8378
|
|
{ PseudoVSOXSEG4EI64_V_M4_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8379
|
|
{ PseudoVSOXSEG4EI64_V_M4_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8380
|
|
{ PseudoVSOXSEG4EI8_V_M1_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8381
|
|
{ PseudoVSOXSEG4EI8_V_M1_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8382
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8383
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8384
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8385
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8386
|
|
{ PseudoVSOXSEG4EI8_V_MF8_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8387
|
|
{ PseudoVSOXSEG4EI8_V_MF8_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8388
|
|
{ PseudoVSOXSEG4EI8_V_M1_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8389
|
|
{ PseudoVSOXSEG4EI8_V_M1_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8390
|
|
{ PseudoVSOXSEG4EI8_V_M2_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8391
|
|
{ PseudoVSOXSEG4EI8_V_M2_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8392
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8393
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8394
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8395
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8396
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF8, VSOXSEG4EI8_V, 0x5, 0x0 }, // 8397
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, VSOXSEG4EI8_V, 0x5, 0x0 }, // 8398
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF4, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8399
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8400
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF4, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8401
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8402
|
|
{ PseudoVSOXSEG4EI8_V_MF2_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8403
|
|
{ PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8404
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8405
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8406
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8407
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8408
|
|
{ PseudoVSOXSEG5EI16_V_M1_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8409
|
|
{ PseudoVSOXSEG5EI16_V_M1_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8410
|
|
{ PseudoVSOXSEG5EI16_V_M2_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8411
|
|
{ PseudoVSOXSEG5EI16_V_M2_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8412
|
|
{ PseudoVSOXSEG5EI16_V_MF2_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8413
|
|
{ PseudoVSOXSEG5EI16_V_MF2_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8414
|
|
{ PseudoVSOXSEG5EI16_V_MF4_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8415
|
|
{ PseudoVSOXSEG5EI16_V_MF4_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8416
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF8, VSOXSEG5EI16_V, 0x5, 0x0 }, // 8417
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, VSOXSEG5EI16_V, 0x5, 0x0 }, // 8418
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF4, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8419
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8420
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF4, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8421
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8422
|
|
{ PseudoVSOXSEG5EI16_V_M1_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8423
|
|
{ PseudoVSOXSEG5EI16_V_M1_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8424
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8425
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8426
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8427
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8428
|
|
{ PseudoVSOXSEG5EI32_V_M1_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8429
|
|
{ PseudoVSOXSEG5EI32_V_M1_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8430
|
|
{ PseudoVSOXSEG5EI32_V_M2_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8431
|
|
{ PseudoVSOXSEG5EI32_V_M2_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8432
|
|
{ PseudoVSOXSEG5EI32_V_M4_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8433
|
|
{ PseudoVSOXSEG5EI32_V_M4_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8434
|
|
{ PseudoVSOXSEG5EI32_V_MF2_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8435
|
|
{ PseudoVSOXSEG5EI32_V_MF2_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8436
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF8, VSOXSEG5EI32_V, 0x5, 0x0 }, // 8437
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, VSOXSEG5EI32_V, 0x5, 0x0 }, // 8438
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF4, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8439
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF4_MASK, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8440
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF4, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8441
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8442
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8443
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8444
|
|
{ PseudoVSOXSEG5EI32_V_M2_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8445
|
|
{ PseudoVSOXSEG5EI32_V_M2_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8446
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8447
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8448
|
|
{ PseudoVSOXSEG5EI64_V_M1_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8449
|
|
{ PseudoVSOXSEG5EI64_V_M1_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8450
|
|
{ PseudoVSOXSEG5EI64_V_M2_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8451
|
|
{ PseudoVSOXSEG5EI64_V_M2_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8452
|
|
{ PseudoVSOXSEG5EI64_V_M4_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8453
|
|
{ PseudoVSOXSEG5EI64_V_M4_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8454
|
|
{ PseudoVSOXSEG5EI64_V_M8_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8455
|
|
{ PseudoVSOXSEG5EI64_V_M8_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8456
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF8, VSOXSEG5EI64_V, 0x5, 0x0 }, // 8457
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF8_MASK, VSOXSEG5EI64_V, 0x5, 0x0 }, // 8458
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF4, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8459
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF4_MASK, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8460
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF4, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8461
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF4_MASK, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8462
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8463
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8464
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8465
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8466
|
|
{ PseudoVSOXSEG5EI64_V_M4_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8467
|
|
{ PseudoVSOXSEG5EI64_V_M4_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8468
|
|
{ PseudoVSOXSEG5EI8_V_M1_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8469
|
|
{ PseudoVSOXSEG5EI8_V_M1_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8470
|
|
{ PseudoVSOXSEG5EI8_V_MF2_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8471
|
|
{ PseudoVSOXSEG5EI8_V_MF2_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8472
|
|
{ PseudoVSOXSEG5EI8_V_MF4_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8473
|
|
{ PseudoVSOXSEG5EI8_V_MF4_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8474
|
|
{ PseudoVSOXSEG5EI8_V_MF8_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8475
|
|
{ PseudoVSOXSEG5EI8_V_MF8_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8476
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF8, VSOXSEG5EI8_V, 0x5, 0x0 }, // 8477
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, VSOXSEG5EI8_V, 0x5, 0x0 }, // 8478
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF4, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8479
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8480
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF4, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8481
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8482
|
|
{ PseudoVSOXSEG5EI8_V_MF2_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8483
|
|
{ PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8484
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8485
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8486
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8487
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8488
|
|
{ PseudoVSOXSEG6EI16_V_M1_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8489
|
|
{ PseudoVSOXSEG6EI16_V_M1_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8490
|
|
{ PseudoVSOXSEG6EI16_V_M2_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8491
|
|
{ PseudoVSOXSEG6EI16_V_M2_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8492
|
|
{ PseudoVSOXSEG6EI16_V_MF2_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8493
|
|
{ PseudoVSOXSEG6EI16_V_MF2_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8494
|
|
{ PseudoVSOXSEG6EI16_V_MF4_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8495
|
|
{ PseudoVSOXSEG6EI16_V_MF4_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8496
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF8, VSOXSEG6EI16_V, 0x5, 0x0 }, // 8497
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, VSOXSEG6EI16_V, 0x5, 0x0 }, // 8498
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF4, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8499
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8500
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF4, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8501
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8502
|
|
{ PseudoVSOXSEG6EI16_V_M1_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8503
|
|
{ PseudoVSOXSEG6EI16_V_M1_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8504
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8505
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8506
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8507
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8508
|
|
{ PseudoVSOXSEG6EI32_V_M1_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8509
|
|
{ PseudoVSOXSEG6EI32_V_M1_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8510
|
|
{ PseudoVSOXSEG6EI32_V_M2_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8511
|
|
{ PseudoVSOXSEG6EI32_V_M2_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8512
|
|
{ PseudoVSOXSEG6EI32_V_M4_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8513
|
|
{ PseudoVSOXSEG6EI32_V_M4_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8514
|
|
{ PseudoVSOXSEG6EI32_V_MF2_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8515
|
|
{ PseudoVSOXSEG6EI32_V_MF2_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8516
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF8, VSOXSEG6EI32_V, 0x5, 0x0 }, // 8517
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, VSOXSEG6EI32_V, 0x5, 0x0 }, // 8518
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF4, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8519
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF4_MASK, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8520
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF4, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8521
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8522
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8523
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8524
|
|
{ PseudoVSOXSEG6EI32_V_M2_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8525
|
|
{ PseudoVSOXSEG6EI32_V_M2_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8526
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8527
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8528
|
|
{ PseudoVSOXSEG6EI64_V_M1_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8529
|
|
{ PseudoVSOXSEG6EI64_V_M1_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8530
|
|
{ PseudoVSOXSEG6EI64_V_M2_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8531
|
|
{ PseudoVSOXSEG6EI64_V_M2_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8532
|
|
{ PseudoVSOXSEG6EI64_V_M4_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8533
|
|
{ PseudoVSOXSEG6EI64_V_M4_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8534
|
|
{ PseudoVSOXSEG6EI64_V_M8_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8535
|
|
{ PseudoVSOXSEG6EI64_V_M8_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8536
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF8, VSOXSEG6EI64_V, 0x5, 0x0 }, // 8537
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF8_MASK, VSOXSEG6EI64_V, 0x5, 0x0 }, // 8538
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF4, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8539
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF4_MASK, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8540
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF4, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8541
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF4_MASK, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8542
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8543
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8544
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8545
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8546
|
|
{ PseudoVSOXSEG6EI64_V_M4_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8547
|
|
{ PseudoVSOXSEG6EI64_V_M4_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8548
|
|
{ PseudoVSOXSEG6EI8_V_M1_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8549
|
|
{ PseudoVSOXSEG6EI8_V_M1_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8550
|
|
{ PseudoVSOXSEG6EI8_V_MF2_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8551
|
|
{ PseudoVSOXSEG6EI8_V_MF2_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8552
|
|
{ PseudoVSOXSEG6EI8_V_MF4_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8553
|
|
{ PseudoVSOXSEG6EI8_V_MF4_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8554
|
|
{ PseudoVSOXSEG6EI8_V_MF8_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8555
|
|
{ PseudoVSOXSEG6EI8_V_MF8_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8556
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF8, VSOXSEG6EI8_V, 0x5, 0x0 }, // 8557
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, VSOXSEG6EI8_V, 0x5, 0x0 }, // 8558
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF4, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8559
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8560
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF4, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8561
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8562
|
|
{ PseudoVSOXSEG6EI8_V_MF2_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8563
|
|
{ PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8564
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8565
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8566
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8567
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8568
|
|
{ PseudoVSOXSEG7EI16_V_M1_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8569
|
|
{ PseudoVSOXSEG7EI16_V_M1_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8570
|
|
{ PseudoVSOXSEG7EI16_V_M2_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8571
|
|
{ PseudoVSOXSEG7EI16_V_M2_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8572
|
|
{ PseudoVSOXSEG7EI16_V_MF2_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8573
|
|
{ PseudoVSOXSEG7EI16_V_MF2_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8574
|
|
{ PseudoVSOXSEG7EI16_V_MF4_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8575
|
|
{ PseudoVSOXSEG7EI16_V_MF4_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8576
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF8, VSOXSEG7EI16_V, 0x5, 0x0 }, // 8577
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, VSOXSEG7EI16_V, 0x5, 0x0 }, // 8578
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF4, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8579
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8580
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF4, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8581
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8582
|
|
{ PseudoVSOXSEG7EI16_V_M1_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8583
|
|
{ PseudoVSOXSEG7EI16_V_M1_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8584
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8585
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8586
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8587
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8588
|
|
{ PseudoVSOXSEG7EI32_V_M1_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8589
|
|
{ PseudoVSOXSEG7EI32_V_M1_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8590
|
|
{ PseudoVSOXSEG7EI32_V_M2_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8591
|
|
{ PseudoVSOXSEG7EI32_V_M2_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8592
|
|
{ PseudoVSOXSEG7EI32_V_M4_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8593
|
|
{ PseudoVSOXSEG7EI32_V_M4_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8594
|
|
{ PseudoVSOXSEG7EI32_V_MF2_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8595
|
|
{ PseudoVSOXSEG7EI32_V_MF2_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8596
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF8, VSOXSEG7EI32_V, 0x5, 0x0 }, // 8597
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, VSOXSEG7EI32_V, 0x5, 0x0 }, // 8598
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF4, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8599
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF4_MASK, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8600
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF4, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8601
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8602
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8603
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8604
|
|
{ PseudoVSOXSEG7EI32_V_M2_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8605
|
|
{ PseudoVSOXSEG7EI32_V_M2_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8606
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8607
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8608
|
|
{ PseudoVSOXSEG7EI64_V_M1_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8609
|
|
{ PseudoVSOXSEG7EI64_V_M1_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8610
|
|
{ PseudoVSOXSEG7EI64_V_M2_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8611
|
|
{ PseudoVSOXSEG7EI64_V_M2_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8612
|
|
{ PseudoVSOXSEG7EI64_V_M4_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8613
|
|
{ PseudoVSOXSEG7EI64_V_M4_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8614
|
|
{ PseudoVSOXSEG7EI64_V_M8_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8615
|
|
{ PseudoVSOXSEG7EI64_V_M8_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8616
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF8, VSOXSEG7EI64_V, 0x5, 0x0 }, // 8617
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF8_MASK, VSOXSEG7EI64_V, 0x5, 0x0 }, // 8618
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF4, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8619
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF4_MASK, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8620
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF4, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8621
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF4_MASK, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8622
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8623
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8624
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8625
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8626
|
|
{ PseudoVSOXSEG7EI64_V_M4_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8627
|
|
{ PseudoVSOXSEG7EI64_V_M4_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8628
|
|
{ PseudoVSOXSEG7EI8_V_M1_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8629
|
|
{ PseudoVSOXSEG7EI8_V_M1_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8630
|
|
{ PseudoVSOXSEG7EI8_V_MF2_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8631
|
|
{ PseudoVSOXSEG7EI8_V_MF2_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8632
|
|
{ PseudoVSOXSEG7EI8_V_MF4_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8633
|
|
{ PseudoVSOXSEG7EI8_V_MF4_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8634
|
|
{ PseudoVSOXSEG7EI8_V_MF8_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8635
|
|
{ PseudoVSOXSEG7EI8_V_MF8_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8636
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF8, VSOXSEG7EI8_V, 0x5, 0x0 }, // 8637
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, VSOXSEG7EI8_V, 0x5, 0x0 }, // 8638
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF4, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8639
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8640
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF4, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8641
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8642
|
|
{ PseudoVSOXSEG7EI8_V_MF2_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8643
|
|
{ PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8644
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8645
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8646
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8647
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8648
|
|
{ PseudoVSOXSEG8EI16_V_M1_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8649
|
|
{ PseudoVSOXSEG8EI16_V_M1_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8650
|
|
{ PseudoVSOXSEG8EI16_V_M2_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8651
|
|
{ PseudoVSOXSEG8EI16_V_M2_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8652
|
|
{ PseudoVSOXSEG8EI16_V_MF2_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8653
|
|
{ PseudoVSOXSEG8EI16_V_MF2_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8654
|
|
{ PseudoVSOXSEG8EI16_V_MF4_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8655
|
|
{ PseudoVSOXSEG8EI16_V_MF4_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8656
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF8, VSOXSEG8EI16_V, 0x5, 0x0 }, // 8657
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, VSOXSEG8EI16_V, 0x5, 0x0 }, // 8658
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF4, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8659
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8660
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF4, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8661
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8662
|
|
{ PseudoVSOXSEG8EI16_V_M1_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8663
|
|
{ PseudoVSOXSEG8EI16_V_M1_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8664
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8665
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8666
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8667
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8668
|
|
{ PseudoVSOXSEG8EI32_V_M1_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8669
|
|
{ PseudoVSOXSEG8EI32_V_M1_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8670
|
|
{ PseudoVSOXSEG8EI32_V_M2_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8671
|
|
{ PseudoVSOXSEG8EI32_V_M2_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8672
|
|
{ PseudoVSOXSEG8EI32_V_M4_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8673
|
|
{ PseudoVSOXSEG8EI32_V_M4_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8674
|
|
{ PseudoVSOXSEG8EI32_V_MF2_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8675
|
|
{ PseudoVSOXSEG8EI32_V_MF2_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8676
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF8, VSOXSEG8EI32_V, 0x5, 0x0 }, // 8677
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, VSOXSEG8EI32_V, 0x5, 0x0 }, // 8678
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF4, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8679
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF4_MASK, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8680
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF4, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8681
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8682
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8683
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8684
|
|
{ PseudoVSOXSEG8EI32_V_M2_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8685
|
|
{ PseudoVSOXSEG8EI32_V_M2_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8686
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8687
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8688
|
|
{ PseudoVSOXSEG8EI64_V_M1_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8689
|
|
{ PseudoVSOXSEG8EI64_V_M1_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8690
|
|
{ PseudoVSOXSEG8EI64_V_M2_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8691
|
|
{ PseudoVSOXSEG8EI64_V_M2_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8692
|
|
{ PseudoVSOXSEG8EI64_V_M4_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8693
|
|
{ PseudoVSOXSEG8EI64_V_M4_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8694
|
|
{ PseudoVSOXSEG8EI64_V_M8_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8695
|
|
{ PseudoVSOXSEG8EI64_V_M8_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8696
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF8, VSOXSEG8EI64_V, 0x5, 0x0 }, // 8697
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF8_MASK, VSOXSEG8EI64_V, 0x5, 0x0 }, // 8698
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF4, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8699
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF4_MASK, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8700
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF4, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8701
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF4_MASK, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8702
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8703
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8704
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8705
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8706
|
|
{ PseudoVSOXSEG8EI64_V_M4_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8707
|
|
{ PseudoVSOXSEG8EI64_V_M4_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8708
|
|
{ PseudoVSOXSEG8EI8_V_M1_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8709
|
|
{ PseudoVSOXSEG8EI8_V_M1_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8710
|
|
{ PseudoVSOXSEG8EI8_V_MF2_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8711
|
|
{ PseudoVSOXSEG8EI8_V_MF2_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8712
|
|
{ PseudoVSOXSEG8EI8_V_MF4_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8713
|
|
{ PseudoVSOXSEG8EI8_V_MF4_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8714
|
|
{ PseudoVSOXSEG8EI8_V_MF8_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8715
|
|
{ PseudoVSOXSEG8EI8_V_MF8_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8716
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF8, VSOXSEG8EI8_V, 0x5, 0x0 }, // 8717
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, VSOXSEG8EI8_V, 0x5, 0x0 }, // 8718
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF4, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8719
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8720
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF4, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8721
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8722
|
|
{ PseudoVSOXSEG8EI8_V_MF2_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8723
|
|
{ PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8724
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8725
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8726
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8727
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8728
|
|
{ PseudoVSRA_VI_M1, VSRA_VI, 0x0, 0x0 }, // 8729
|
|
{ PseudoVSRA_VI_M1_MASK, VSRA_VI, 0x0, 0x0 }, // 8730
|
|
{ PseudoVSRA_VI_M2, VSRA_VI, 0x1, 0x0 }, // 8731
|
|
{ PseudoVSRA_VI_M2_MASK, VSRA_VI, 0x1, 0x0 }, // 8732
|
|
{ PseudoVSRA_VI_M4, VSRA_VI, 0x2, 0x0 }, // 8733
|
|
{ PseudoVSRA_VI_M4_MASK, VSRA_VI, 0x2, 0x0 }, // 8734
|
|
{ PseudoVSRA_VI_M8, VSRA_VI, 0x3, 0x0 }, // 8735
|
|
{ PseudoVSRA_VI_M8_MASK, VSRA_VI, 0x3, 0x0 }, // 8736
|
|
{ PseudoVSRA_VI_MF8, VSRA_VI, 0x5, 0x0 }, // 8737
|
|
{ PseudoVSRA_VI_MF8_MASK, VSRA_VI, 0x5, 0x0 }, // 8738
|
|
{ PseudoVSRA_VI_MF4, VSRA_VI, 0x6, 0x0 }, // 8739
|
|
{ PseudoVSRA_VI_MF4_MASK, VSRA_VI, 0x6, 0x0 }, // 8740
|
|
{ PseudoVSRA_VI_MF2, VSRA_VI, 0x7, 0x0 }, // 8741
|
|
{ PseudoVSRA_VI_MF2_MASK, VSRA_VI, 0x7, 0x0 }, // 8742
|
|
{ PseudoVSRA_VV_M1, VSRA_VV, 0x0, 0x0 }, // 8743
|
|
{ PseudoVSRA_VV_M1_MASK, VSRA_VV, 0x0, 0x0 }, // 8744
|
|
{ PseudoVSRA_VV_M2, VSRA_VV, 0x1, 0x0 }, // 8745
|
|
{ PseudoVSRA_VV_M2_MASK, VSRA_VV, 0x1, 0x0 }, // 8746
|
|
{ PseudoVSRA_VV_M4, VSRA_VV, 0x2, 0x0 }, // 8747
|
|
{ PseudoVSRA_VV_M4_MASK, VSRA_VV, 0x2, 0x0 }, // 8748
|
|
{ PseudoVSRA_VV_M8, VSRA_VV, 0x3, 0x0 }, // 8749
|
|
{ PseudoVSRA_VV_M8_MASK, VSRA_VV, 0x3, 0x0 }, // 8750
|
|
{ PseudoVSRA_VV_MF8, VSRA_VV, 0x5, 0x0 }, // 8751
|
|
{ PseudoVSRA_VV_MF8_MASK, VSRA_VV, 0x5, 0x0 }, // 8752
|
|
{ PseudoVSRA_VV_MF4, VSRA_VV, 0x6, 0x0 }, // 8753
|
|
{ PseudoVSRA_VV_MF4_MASK, VSRA_VV, 0x6, 0x0 }, // 8754
|
|
{ PseudoVSRA_VV_MF2, VSRA_VV, 0x7, 0x0 }, // 8755
|
|
{ PseudoVSRA_VV_MF2_MASK, VSRA_VV, 0x7, 0x0 }, // 8756
|
|
{ PseudoVSRA_VX_M1, VSRA_VX, 0x0, 0x0 }, // 8757
|
|
{ PseudoVSRA_VX_M1_MASK, VSRA_VX, 0x0, 0x0 }, // 8758
|
|
{ PseudoVSRA_VX_M2, VSRA_VX, 0x1, 0x0 }, // 8759
|
|
{ PseudoVSRA_VX_M2_MASK, VSRA_VX, 0x1, 0x0 }, // 8760
|
|
{ PseudoVSRA_VX_M4, VSRA_VX, 0x2, 0x0 }, // 8761
|
|
{ PseudoVSRA_VX_M4_MASK, VSRA_VX, 0x2, 0x0 }, // 8762
|
|
{ PseudoVSRA_VX_M8, VSRA_VX, 0x3, 0x0 }, // 8763
|
|
{ PseudoVSRA_VX_M8_MASK, VSRA_VX, 0x3, 0x0 }, // 8764
|
|
{ PseudoVSRA_VX_MF8, VSRA_VX, 0x5, 0x0 }, // 8765
|
|
{ PseudoVSRA_VX_MF8_MASK, VSRA_VX, 0x5, 0x0 }, // 8766
|
|
{ PseudoVSRA_VX_MF4, VSRA_VX, 0x6, 0x0 }, // 8767
|
|
{ PseudoVSRA_VX_MF4_MASK, VSRA_VX, 0x6, 0x0 }, // 8768
|
|
{ PseudoVSRA_VX_MF2, VSRA_VX, 0x7, 0x0 }, // 8769
|
|
{ PseudoVSRA_VX_MF2_MASK, VSRA_VX, 0x7, 0x0 }, // 8770
|
|
{ PseudoVSRL_VI_M1, VSRL_VI, 0x0, 0x0 }, // 8771
|
|
{ PseudoVSRL_VI_M1_MASK, VSRL_VI, 0x0, 0x0 }, // 8772
|
|
{ PseudoVSRL_VI_M2, VSRL_VI, 0x1, 0x0 }, // 8773
|
|
{ PseudoVSRL_VI_M2_MASK, VSRL_VI, 0x1, 0x0 }, // 8774
|
|
{ PseudoVSRL_VI_M4, VSRL_VI, 0x2, 0x0 }, // 8775
|
|
{ PseudoVSRL_VI_M4_MASK, VSRL_VI, 0x2, 0x0 }, // 8776
|
|
{ PseudoVSRL_VI_M8, VSRL_VI, 0x3, 0x0 }, // 8777
|
|
{ PseudoVSRL_VI_M8_MASK, VSRL_VI, 0x3, 0x0 }, // 8778
|
|
{ PseudoVSRL_VI_MF8, VSRL_VI, 0x5, 0x0 }, // 8779
|
|
{ PseudoVSRL_VI_MF8_MASK, VSRL_VI, 0x5, 0x0 }, // 8780
|
|
{ PseudoVSRL_VI_MF4, VSRL_VI, 0x6, 0x0 }, // 8781
|
|
{ PseudoVSRL_VI_MF4_MASK, VSRL_VI, 0x6, 0x0 }, // 8782
|
|
{ PseudoVSRL_VI_MF2, VSRL_VI, 0x7, 0x0 }, // 8783
|
|
{ PseudoVSRL_VI_MF2_MASK, VSRL_VI, 0x7, 0x0 }, // 8784
|
|
{ PseudoVSRL_VV_M1, VSRL_VV, 0x0, 0x0 }, // 8785
|
|
{ PseudoVSRL_VV_M1_MASK, VSRL_VV, 0x0, 0x0 }, // 8786
|
|
{ PseudoVSRL_VV_M2, VSRL_VV, 0x1, 0x0 }, // 8787
|
|
{ PseudoVSRL_VV_M2_MASK, VSRL_VV, 0x1, 0x0 }, // 8788
|
|
{ PseudoVSRL_VV_M4, VSRL_VV, 0x2, 0x0 }, // 8789
|
|
{ PseudoVSRL_VV_M4_MASK, VSRL_VV, 0x2, 0x0 }, // 8790
|
|
{ PseudoVSRL_VV_M8, VSRL_VV, 0x3, 0x0 }, // 8791
|
|
{ PseudoVSRL_VV_M8_MASK, VSRL_VV, 0x3, 0x0 }, // 8792
|
|
{ PseudoVSRL_VV_MF8, VSRL_VV, 0x5, 0x0 }, // 8793
|
|
{ PseudoVSRL_VV_MF8_MASK, VSRL_VV, 0x5, 0x0 }, // 8794
|
|
{ PseudoVSRL_VV_MF4, VSRL_VV, 0x6, 0x0 }, // 8795
|
|
{ PseudoVSRL_VV_MF4_MASK, VSRL_VV, 0x6, 0x0 }, // 8796
|
|
{ PseudoVSRL_VV_MF2, VSRL_VV, 0x7, 0x0 }, // 8797
|
|
{ PseudoVSRL_VV_MF2_MASK, VSRL_VV, 0x7, 0x0 }, // 8798
|
|
{ PseudoVSRL_VX_M1, VSRL_VX, 0x0, 0x0 }, // 8799
|
|
{ PseudoVSRL_VX_M1_MASK, VSRL_VX, 0x0, 0x0 }, // 8800
|
|
{ PseudoVSRL_VX_M2, VSRL_VX, 0x1, 0x0 }, // 8801
|
|
{ PseudoVSRL_VX_M2_MASK, VSRL_VX, 0x1, 0x0 }, // 8802
|
|
{ PseudoVSRL_VX_M4, VSRL_VX, 0x2, 0x0 }, // 8803
|
|
{ PseudoVSRL_VX_M4_MASK, VSRL_VX, 0x2, 0x0 }, // 8804
|
|
{ PseudoVSRL_VX_M8, VSRL_VX, 0x3, 0x0 }, // 8805
|
|
{ PseudoVSRL_VX_M8_MASK, VSRL_VX, 0x3, 0x0 }, // 8806
|
|
{ PseudoVSRL_VX_MF8, VSRL_VX, 0x5, 0x0 }, // 8807
|
|
{ PseudoVSRL_VX_MF8_MASK, VSRL_VX, 0x5, 0x0 }, // 8808
|
|
{ PseudoVSRL_VX_MF4, VSRL_VX, 0x6, 0x0 }, // 8809
|
|
{ PseudoVSRL_VX_MF4_MASK, VSRL_VX, 0x6, 0x0 }, // 8810
|
|
{ PseudoVSRL_VX_MF2, VSRL_VX, 0x7, 0x0 }, // 8811
|
|
{ PseudoVSRL_VX_MF2_MASK, VSRL_VX, 0x7, 0x0 }, // 8812
|
|
{ PseudoVSSE16_V_M1, VSSE16_V, 0x0, 0x10 }, // 8813
|
|
{ PseudoVSSE16_V_M1_MASK, VSSE16_V, 0x0, 0x10 }, // 8814
|
|
{ PseudoVSSE16_V_M2, VSSE16_V, 0x1, 0x10 }, // 8815
|
|
{ PseudoVSSE16_V_M2_MASK, VSSE16_V, 0x1, 0x10 }, // 8816
|
|
{ PseudoVSSE16_V_M4, VSSE16_V, 0x2, 0x10 }, // 8817
|
|
{ PseudoVSSE16_V_M4_MASK, VSSE16_V, 0x2, 0x10 }, // 8818
|
|
{ PseudoVSSE16_V_M8, VSSE16_V, 0x3, 0x10 }, // 8819
|
|
{ PseudoVSSE16_V_M8_MASK, VSSE16_V, 0x3, 0x10 }, // 8820
|
|
{ PseudoVSSE16_V_MF4, VSSE16_V, 0x6, 0x10 }, // 8821
|
|
{ PseudoVSSE16_V_MF4_MASK, VSSE16_V, 0x6, 0x10 }, // 8822
|
|
{ PseudoVSSE16_V_MF2, VSSE16_V, 0x7, 0x10 }, // 8823
|
|
{ PseudoVSSE16_V_MF2_MASK, VSSE16_V, 0x7, 0x10 }, // 8824
|
|
{ PseudoVSSE32_V_M1, VSSE32_V, 0x0, 0x20 }, // 8825
|
|
{ PseudoVSSE32_V_M1_MASK, VSSE32_V, 0x0, 0x20 }, // 8826
|
|
{ PseudoVSSE32_V_M2, VSSE32_V, 0x1, 0x20 }, // 8827
|
|
{ PseudoVSSE32_V_M2_MASK, VSSE32_V, 0x1, 0x20 }, // 8828
|
|
{ PseudoVSSE32_V_M4, VSSE32_V, 0x2, 0x20 }, // 8829
|
|
{ PseudoVSSE32_V_M4_MASK, VSSE32_V, 0x2, 0x20 }, // 8830
|
|
{ PseudoVSSE32_V_M8, VSSE32_V, 0x3, 0x20 }, // 8831
|
|
{ PseudoVSSE32_V_M8_MASK, VSSE32_V, 0x3, 0x20 }, // 8832
|
|
{ PseudoVSSE32_V_MF2, VSSE32_V, 0x7, 0x20 }, // 8833
|
|
{ PseudoVSSE32_V_MF2_MASK, VSSE32_V, 0x7, 0x20 }, // 8834
|
|
{ PseudoVSSE64_V_M1, VSSE64_V, 0x0, 0x40 }, // 8835
|
|
{ PseudoVSSE64_V_M1_MASK, VSSE64_V, 0x0, 0x40 }, // 8836
|
|
{ PseudoVSSE64_V_M2, VSSE64_V, 0x1, 0x40 }, // 8837
|
|
{ PseudoVSSE64_V_M2_MASK, VSSE64_V, 0x1, 0x40 }, // 8838
|
|
{ PseudoVSSE64_V_M4, VSSE64_V, 0x2, 0x40 }, // 8839
|
|
{ PseudoVSSE64_V_M4_MASK, VSSE64_V, 0x2, 0x40 }, // 8840
|
|
{ PseudoVSSE64_V_M8, VSSE64_V, 0x3, 0x40 }, // 8841
|
|
{ PseudoVSSE64_V_M8_MASK, VSSE64_V, 0x3, 0x40 }, // 8842
|
|
{ PseudoVSSE8_V_M1, VSSE8_V, 0x0, 0x8 }, // 8843
|
|
{ PseudoVSSE8_V_M1_MASK, VSSE8_V, 0x0, 0x8 }, // 8844
|
|
{ PseudoVSSE8_V_M2, VSSE8_V, 0x1, 0x8 }, // 8845
|
|
{ PseudoVSSE8_V_M2_MASK, VSSE8_V, 0x1, 0x8 }, // 8846
|
|
{ PseudoVSSE8_V_M4, VSSE8_V, 0x2, 0x8 }, // 8847
|
|
{ PseudoVSSE8_V_M4_MASK, VSSE8_V, 0x2, 0x8 }, // 8848
|
|
{ PseudoVSSE8_V_M8, VSSE8_V, 0x3, 0x8 }, // 8849
|
|
{ PseudoVSSE8_V_M8_MASK, VSSE8_V, 0x3, 0x8 }, // 8850
|
|
{ PseudoVSSE8_V_MF8, VSSE8_V, 0x5, 0x8 }, // 8851
|
|
{ PseudoVSSE8_V_MF8_MASK, VSSE8_V, 0x5, 0x8 }, // 8852
|
|
{ PseudoVSSE8_V_MF4, VSSE8_V, 0x6, 0x8 }, // 8853
|
|
{ PseudoVSSE8_V_MF4_MASK, VSSE8_V, 0x6, 0x8 }, // 8854
|
|
{ PseudoVSSE8_V_MF2, VSSE8_V, 0x7, 0x8 }, // 8855
|
|
{ PseudoVSSE8_V_MF2_MASK, VSSE8_V, 0x7, 0x8 }, // 8856
|
|
{ PseudoVSSEG2E16_V_M1, VSSEG2E16_V, 0x0, 0x10 }, // 8857
|
|
{ PseudoVSSEG2E16_V_M1_MASK, VSSEG2E16_V, 0x0, 0x10 }, // 8858
|
|
{ PseudoVSSEG2E16_V_M2, VSSEG2E16_V, 0x1, 0x10 }, // 8859
|
|
{ PseudoVSSEG2E16_V_M2_MASK, VSSEG2E16_V, 0x1, 0x10 }, // 8860
|
|
{ PseudoVSSEG2E16_V_M4, VSSEG2E16_V, 0x2, 0x10 }, // 8861
|
|
{ PseudoVSSEG2E16_V_M4_MASK, VSSEG2E16_V, 0x2, 0x10 }, // 8862
|
|
{ PseudoVSSEG2E16_V_MF4, VSSEG2E16_V, 0x6, 0x10 }, // 8863
|
|
{ PseudoVSSEG2E16_V_MF4_MASK, VSSEG2E16_V, 0x6, 0x10 }, // 8864
|
|
{ PseudoVSSEG2E16_V_MF2, VSSEG2E16_V, 0x7, 0x10 }, // 8865
|
|
{ PseudoVSSEG2E16_V_MF2_MASK, VSSEG2E16_V, 0x7, 0x10 }, // 8866
|
|
{ PseudoVSSEG2E32_V_M1, VSSEG2E32_V, 0x0, 0x20 }, // 8867
|
|
{ PseudoVSSEG2E32_V_M1_MASK, VSSEG2E32_V, 0x0, 0x20 }, // 8868
|
|
{ PseudoVSSEG2E32_V_M2, VSSEG2E32_V, 0x1, 0x20 }, // 8869
|
|
{ PseudoVSSEG2E32_V_M2_MASK, VSSEG2E32_V, 0x1, 0x20 }, // 8870
|
|
{ PseudoVSSEG2E32_V_M4, VSSEG2E32_V, 0x2, 0x20 }, // 8871
|
|
{ PseudoVSSEG2E32_V_M4_MASK, VSSEG2E32_V, 0x2, 0x20 }, // 8872
|
|
{ PseudoVSSEG2E32_V_MF2, VSSEG2E32_V, 0x7, 0x20 }, // 8873
|
|
{ PseudoVSSEG2E32_V_MF2_MASK, VSSEG2E32_V, 0x7, 0x20 }, // 8874
|
|
{ PseudoVSSEG2E64_V_M1, VSSEG2E64_V, 0x0, 0x40 }, // 8875
|
|
{ PseudoVSSEG2E64_V_M1_MASK, VSSEG2E64_V, 0x0, 0x40 }, // 8876
|
|
{ PseudoVSSEG2E64_V_M2, VSSEG2E64_V, 0x1, 0x40 }, // 8877
|
|
{ PseudoVSSEG2E64_V_M2_MASK, VSSEG2E64_V, 0x1, 0x40 }, // 8878
|
|
{ PseudoVSSEG2E64_V_M4, VSSEG2E64_V, 0x2, 0x40 }, // 8879
|
|
{ PseudoVSSEG2E64_V_M4_MASK, VSSEG2E64_V, 0x2, 0x40 }, // 8880
|
|
{ PseudoVSSEG2E8_V_M1, VSSEG2E8_V, 0x0, 0x8 }, // 8881
|
|
{ PseudoVSSEG2E8_V_M1_MASK, VSSEG2E8_V, 0x0, 0x8 }, // 8882
|
|
{ PseudoVSSEG2E8_V_M2, VSSEG2E8_V, 0x1, 0x8 }, // 8883
|
|
{ PseudoVSSEG2E8_V_M2_MASK, VSSEG2E8_V, 0x1, 0x8 }, // 8884
|
|
{ PseudoVSSEG2E8_V_M4, VSSEG2E8_V, 0x2, 0x8 }, // 8885
|
|
{ PseudoVSSEG2E8_V_M4_MASK, VSSEG2E8_V, 0x2, 0x8 }, // 8886
|
|
{ PseudoVSSEG2E8_V_MF8, VSSEG2E8_V, 0x5, 0x8 }, // 8887
|
|
{ PseudoVSSEG2E8_V_MF8_MASK, VSSEG2E8_V, 0x5, 0x8 }, // 8888
|
|
{ PseudoVSSEG2E8_V_MF4, VSSEG2E8_V, 0x6, 0x8 }, // 8889
|
|
{ PseudoVSSEG2E8_V_MF4_MASK, VSSEG2E8_V, 0x6, 0x8 }, // 8890
|
|
{ PseudoVSSEG2E8_V_MF2, VSSEG2E8_V, 0x7, 0x8 }, // 8891
|
|
{ PseudoVSSEG2E8_V_MF2_MASK, VSSEG2E8_V, 0x7, 0x8 }, // 8892
|
|
{ PseudoVSSEG3E16_V_M1, VSSEG3E16_V, 0x0, 0x10 }, // 8893
|
|
{ PseudoVSSEG3E16_V_M1_MASK, VSSEG3E16_V, 0x0, 0x10 }, // 8894
|
|
{ PseudoVSSEG3E16_V_M2, VSSEG3E16_V, 0x1, 0x10 }, // 8895
|
|
{ PseudoVSSEG3E16_V_M2_MASK, VSSEG3E16_V, 0x1, 0x10 }, // 8896
|
|
{ PseudoVSSEG3E16_V_MF4, VSSEG3E16_V, 0x6, 0x10 }, // 8897
|
|
{ PseudoVSSEG3E16_V_MF4_MASK, VSSEG3E16_V, 0x6, 0x10 }, // 8898
|
|
{ PseudoVSSEG3E16_V_MF2, VSSEG3E16_V, 0x7, 0x10 }, // 8899
|
|
{ PseudoVSSEG3E16_V_MF2_MASK, VSSEG3E16_V, 0x7, 0x10 }, // 8900
|
|
{ PseudoVSSEG3E32_V_M1, VSSEG3E32_V, 0x0, 0x20 }, // 8901
|
|
{ PseudoVSSEG3E32_V_M1_MASK, VSSEG3E32_V, 0x0, 0x20 }, // 8902
|
|
{ PseudoVSSEG3E32_V_M2, VSSEG3E32_V, 0x1, 0x20 }, // 8903
|
|
{ PseudoVSSEG3E32_V_M2_MASK, VSSEG3E32_V, 0x1, 0x20 }, // 8904
|
|
{ PseudoVSSEG3E32_V_MF2, VSSEG3E32_V, 0x7, 0x20 }, // 8905
|
|
{ PseudoVSSEG3E32_V_MF2_MASK, VSSEG3E32_V, 0x7, 0x20 }, // 8906
|
|
{ PseudoVSSEG3E64_V_M1, VSSEG3E64_V, 0x0, 0x40 }, // 8907
|
|
{ PseudoVSSEG3E64_V_M1_MASK, VSSEG3E64_V, 0x0, 0x40 }, // 8908
|
|
{ PseudoVSSEG3E64_V_M2, VSSEG3E64_V, 0x1, 0x40 }, // 8909
|
|
{ PseudoVSSEG3E64_V_M2_MASK, VSSEG3E64_V, 0x1, 0x40 }, // 8910
|
|
{ PseudoVSSEG3E8_V_M1, VSSEG3E8_V, 0x0, 0x8 }, // 8911
|
|
{ PseudoVSSEG3E8_V_M1_MASK, VSSEG3E8_V, 0x0, 0x8 }, // 8912
|
|
{ PseudoVSSEG3E8_V_M2, VSSEG3E8_V, 0x1, 0x8 }, // 8913
|
|
{ PseudoVSSEG3E8_V_M2_MASK, VSSEG3E8_V, 0x1, 0x8 }, // 8914
|
|
{ PseudoVSSEG3E8_V_MF8, VSSEG3E8_V, 0x5, 0x8 }, // 8915
|
|
{ PseudoVSSEG3E8_V_MF8_MASK, VSSEG3E8_V, 0x5, 0x8 }, // 8916
|
|
{ PseudoVSSEG3E8_V_MF4, VSSEG3E8_V, 0x6, 0x8 }, // 8917
|
|
{ PseudoVSSEG3E8_V_MF4_MASK, VSSEG3E8_V, 0x6, 0x8 }, // 8918
|
|
{ PseudoVSSEG3E8_V_MF2, VSSEG3E8_V, 0x7, 0x8 }, // 8919
|
|
{ PseudoVSSEG3E8_V_MF2_MASK, VSSEG3E8_V, 0x7, 0x8 }, // 8920
|
|
{ PseudoVSSEG4E16_V_M1, VSSEG4E16_V, 0x0, 0x10 }, // 8921
|
|
{ PseudoVSSEG4E16_V_M1_MASK, VSSEG4E16_V, 0x0, 0x10 }, // 8922
|
|
{ PseudoVSSEG4E16_V_M2, VSSEG4E16_V, 0x1, 0x10 }, // 8923
|
|
{ PseudoVSSEG4E16_V_M2_MASK, VSSEG4E16_V, 0x1, 0x10 }, // 8924
|
|
{ PseudoVSSEG4E16_V_MF4, VSSEG4E16_V, 0x6, 0x10 }, // 8925
|
|
{ PseudoVSSEG4E16_V_MF4_MASK, VSSEG4E16_V, 0x6, 0x10 }, // 8926
|
|
{ PseudoVSSEG4E16_V_MF2, VSSEG4E16_V, 0x7, 0x10 }, // 8927
|
|
{ PseudoVSSEG4E16_V_MF2_MASK, VSSEG4E16_V, 0x7, 0x10 }, // 8928
|
|
{ PseudoVSSEG4E32_V_M1, VSSEG4E32_V, 0x0, 0x20 }, // 8929
|
|
{ PseudoVSSEG4E32_V_M1_MASK, VSSEG4E32_V, 0x0, 0x20 }, // 8930
|
|
{ PseudoVSSEG4E32_V_M2, VSSEG4E32_V, 0x1, 0x20 }, // 8931
|
|
{ PseudoVSSEG4E32_V_M2_MASK, VSSEG4E32_V, 0x1, 0x20 }, // 8932
|
|
{ PseudoVSSEG4E32_V_MF2, VSSEG4E32_V, 0x7, 0x20 }, // 8933
|
|
{ PseudoVSSEG4E32_V_MF2_MASK, VSSEG4E32_V, 0x7, 0x20 }, // 8934
|
|
{ PseudoVSSEG4E64_V_M1, VSSEG4E64_V, 0x0, 0x40 }, // 8935
|
|
{ PseudoVSSEG4E64_V_M1_MASK, VSSEG4E64_V, 0x0, 0x40 }, // 8936
|
|
{ PseudoVSSEG4E64_V_M2, VSSEG4E64_V, 0x1, 0x40 }, // 8937
|
|
{ PseudoVSSEG4E64_V_M2_MASK, VSSEG4E64_V, 0x1, 0x40 }, // 8938
|
|
{ PseudoVSSEG4E8_V_M1, VSSEG4E8_V, 0x0, 0x8 }, // 8939
|
|
{ PseudoVSSEG4E8_V_M1_MASK, VSSEG4E8_V, 0x0, 0x8 }, // 8940
|
|
{ PseudoVSSEG4E8_V_M2, VSSEG4E8_V, 0x1, 0x8 }, // 8941
|
|
{ PseudoVSSEG4E8_V_M2_MASK, VSSEG4E8_V, 0x1, 0x8 }, // 8942
|
|
{ PseudoVSSEG4E8_V_MF8, VSSEG4E8_V, 0x5, 0x8 }, // 8943
|
|
{ PseudoVSSEG4E8_V_MF8_MASK, VSSEG4E8_V, 0x5, 0x8 }, // 8944
|
|
{ PseudoVSSEG4E8_V_MF4, VSSEG4E8_V, 0x6, 0x8 }, // 8945
|
|
{ PseudoVSSEG4E8_V_MF4_MASK, VSSEG4E8_V, 0x6, 0x8 }, // 8946
|
|
{ PseudoVSSEG4E8_V_MF2, VSSEG4E8_V, 0x7, 0x8 }, // 8947
|
|
{ PseudoVSSEG4E8_V_MF2_MASK, VSSEG4E8_V, 0x7, 0x8 }, // 8948
|
|
{ PseudoVSSEG5E16_V_M1, VSSEG5E16_V, 0x0, 0x10 }, // 8949
|
|
{ PseudoVSSEG5E16_V_M1_MASK, VSSEG5E16_V, 0x0, 0x10 }, // 8950
|
|
{ PseudoVSSEG5E16_V_MF4, VSSEG5E16_V, 0x6, 0x10 }, // 8951
|
|
{ PseudoVSSEG5E16_V_MF4_MASK, VSSEG5E16_V, 0x6, 0x10 }, // 8952
|
|
{ PseudoVSSEG5E16_V_MF2, VSSEG5E16_V, 0x7, 0x10 }, // 8953
|
|
{ PseudoVSSEG5E16_V_MF2_MASK, VSSEG5E16_V, 0x7, 0x10 }, // 8954
|
|
{ PseudoVSSEG5E32_V_M1, VSSEG5E32_V, 0x0, 0x20 }, // 8955
|
|
{ PseudoVSSEG5E32_V_M1_MASK, VSSEG5E32_V, 0x0, 0x20 }, // 8956
|
|
{ PseudoVSSEG5E32_V_MF2, VSSEG5E32_V, 0x7, 0x20 }, // 8957
|
|
{ PseudoVSSEG5E32_V_MF2_MASK, VSSEG5E32_V, 0x7, 0x20 }, // 8958
|
|
{ PseudoVSSEG5E64_V_M1, VSSEG5E64_V, 0x0, 0x40 }, // 8959
|
|
{ PseudoVSSEG5E64_V_M1_MASK, VSSEG5E64_V, 0x0, 0x40 }, // 8960
|
|
{ PseudoVSSEG5E8_V_M1, VSSEG5E8_V, 0x0, 0x8 }, // 8961
|
|
{ PseudoVSSEG5E8_V_M1_MASK, VSSEG5E8_V, 0x0, 0x8 }, // 8962
|
|
{ PseudoVSSEG5E8_V_MF8, VSSEG5E8_V, 0x5, 0x8 }, // 8963
|
|
{ PseudoVSSEG5E8_V_MF8_MASK, VSSEG5E8_V, 0x5, 0x8 }, // 8964
|
|
{ PseudoVSSEG5E8_V_MF4, VSSEG5E8_V, 0x6, 0x8 }, // 8965
|
|
{ PseudoVSSEG5E8_V_MF4_MASK, VSSEG5E8_V, 0x6, 0x8 }, // 8966
|
|
{ PseudoVSSEG5E8_V_MF2, VSSEG5E8_V, 0x7, 0x8 }, // 8967
|
|
{ PseudoVSSEG5E8_V_MF2_MASK, VSSEG5E8_V, 0x7, 0x8 }, // 8968
|
|
{ PseudoVSSEG6E16_V_M1, VSSEG6E16_V, 0x0, 0x10 }, // 8969
|
|
{ PseudoVSSEG6E16_V_M1_MASK, VSSEG6E16_V, 0x0, 0x10 }, // 8970
|
|
{ PseudoVSSEG6E16_V_MF4, VSSEG6E16_V, 0x6, 0x10 }, // 8971
|
|
{ PseudoVSSEG6E16_V_MF4_MASK, VSSEG6E16_V, 0x6, 0x10 }, // 8972
|
|
{ PseudoVSSEG6E16_V_MF2, VSSEG6E16_V, 0x7, 0x10 }, // 8973
|
|
{ PseudoVSSEG6E16_V_MF2_MASK, VSSEG6E16_V, 0x7, 0x10 }, // 8974
|
|
{ PseudoVSSEG6E32_V_M1, VSSEG6E32_V, 0x0, 0x20 }, // 8975
|
|
{ PseudoVSSEG6E32_V_M1_MASK, VSSEG6E32_V, 0x0, 0x20 }, // 8976
|
|
{ PseudoVSSEG6E32_V_MF2, VSSEG6E32_V, 0x7, 0x20 }, // 8977
|
|
{ PseudoVSSEG6E32_V_MF2_MASK, VSSEG6E32_V, 0x7, 0x20 }, // 8978
|
|
{ PseudoVSSEG6E64_V_M1, VSSEG6E64_V, 0x0, 0x40 }, // 8979
|
|
{ PseudoVSSEG6E64_V_M1_MASK, VSSEG6E64_V, 0x0, 0x40 }, // 8980
|
|
{ PseudoVSSEG6E8_V_M1, VSSEG6E8_V, 0x0, 0x8 }, // 8981
|
|
{ PseudoVSSEG6E8_V_M1_MASK, VSSEG6E8_V, 0x0, 0x8 }, // 8982
|
|
{ PseudoVSSEG6E8_V_MF8, VSSEG6E8_V, 0x5, 0x8 }, // 8983
|
|
{ PseudoVSSEG6E8_V_MF8_MASK, VSSEG6E8_V, 0x5, 0x8 }, // 8984
|
|
{ PseudoVSSEG6E8_V_MF4, VSSEG6E8_V, 0x6, 0x8 }, // 8985
|
|
{ PseudoVSSEG6E8_V_MF4_MASK, VSSEG6E8_V, 0x6, 0x8 }, // 8986
|
|
{ PseudoVSSEG6E8_V_MF2, VSSEG6E8_V, 0x7, 0x8 }, // 8987
|
|
{ PseudoVSSEG6E8_V_MF2_MASK, VSSEG6E8_V, 0x7, 0x8 }, // 8988
|
|
{ PseudoVSSEG7E16_V_M1, VSSEG7E16_V, 0x0, 0x10 }, // 8989
|
|
{ PseudoVSSEG7E16_V_M1_MASK, VSSEG7E16_V, 0x0, 0x10 }, // 8990
|
|
{ PseudoVSSEG7E16_V_MF4, VSSEG7E16_V, 0x6, 0x10 }, // 8991
|
|
{ PseudoVSSEG7E16_V_MF4_MASK, VSSEG7E16_V, 0x6, 0x10 }, // 8992
|
|
{ PseudoVSSEG7E16_V_MF2, VSSEG7E16_V, 0x7, 0x10 }, // 8993
|
|
{ PseudoVSSEG7E16_V_MF2_MASK, VSSEG7E16_V, 0x7, 0x10 }, // 8994
|
|
{ PseudoVSSEG7E32_V_M1, VSSEG7E32_V, 0x0, 0x20 }, // 8995
|
|
{ PseudoVSSEG7E32_V_M1_MASK, VSSEG7E32_V, 0x0, 0x20 }, // 8996
|
|
{ PseudoVSSEG7E32_V_MF2, VSSEG7E32_V, 0x7, 0x20 }, // 8997
|
|
{ PseudoVSSEG7E32_V_MF2_MASK, VSSEG7E32_V, 0x7, 0x20 }, // 8998
|
|
{ PseudoVSSEG7E64_V_M1, VSSEG7E64_V, 0x0, 0x40 }, // 8999
|
|
{ PseudoVSSEG7E64_V_M1_MASK, VSSEG7E64_V, 0x0, 0x40 }, // 9000
|
|
{ PseudoVSSEG7E8_V_M1, VSSEG7E8_V, 0x0, 0x8 }, // 9001
|
|
{ PseudoVSSEG7E8_V_M1_MASK, VSSEG7E8_V, 0x0, 0x8 }, // 9002
|
|
{ PseudoVSSEG7E8_V_MF8, VSSEG7E8_V, 0x5, 0x8 }, // 9003
|
|
{ PseudoVSSEG7E8_V_MF8_MASK, VSSEG7E8_V, 0x5, 0x8 }, // 9004
|
|
{ PseudoVSSEG7E8_V_MF4, VSSEG7E8_V, 0x6, 0x8 }, // 9005
|
|
{ PseudoVSSEG7E8_V_MF4_MASK, VSSEG7E8_V, 0x6, 0x8 }, // 9006
|
|
{ PseudoVSSEG7E8_V_MF2, VSSEG7E8_V, 0x7, 0x8 }, // 9007
|
|
{ PseudoVSSEG7E8_V_MF2_MASK, VSSEG7E8_V, 0x7, 0x8 }, // 9008
|
|
{ PseudoVSSEG8E16_V_M1, VSSEG8E16_V, 0x0, 0x10 }, // 9009
|
|
{ PseudoVSSEG8E16_V_M1_MASK, VSSEG8E16_V, 0x0, 0x10 }, // 9010
|
|
{ PseudoVSSEG8E16_V_MF4, VSSEG8E16_V, 0x6, 0x10 }, // 9011
|
|
{ PseudoVSSEG8E16_V_MF4_MASK, VSSEG8E16_V, 0x6, 0x10 }, // 9012
|
|
{ PseudoVSSEG8E16_V_MF2, VSSEG8E16_V, 0x7, 0x10 }, // 9013
|
|
{ PseudoVSSEG8E16_V_MF2_MASK, VSSEG8E16_V, 0x7, 0x10 }, // 9014
|
|
{ PseudoVSSEG8E32_V_M1, VSSEG8E32_V, 0x0, 0x20 }, // 9015
|
|
{ PseudoVSSEG8E32_V_M1_MASK, VSSEG8E32_V, 0x0, 0x20 }, // 9016
|
|
{ PseudoVSSEG8E32_V_MF2, VSSEG8E32_V, 0x7, 0x20 }, // 9017
|
|
{ PseudoVSSEG8E32_V_MF2_MASK, VSSEG8E32_V, 0x7, 0x20 }, // 9018
|
|
{ PseudoVSSEG8E64_V_M1, VSSEG8E64_V, 0x0, 0x40 }, // 9019
|
|
{ PseudoVSSEG8E64_V_M1_MASK, VSSEG8E64_V, 0x0, 0x40 }, // 9020
|
|
{ PseudoVSSEG8E8_V_M1, VSSEG8E8_V, 0x0, 0x8 }, // 9021
|
|
{ PseudoVSSEG8E8_V_M1_MASK, VSSEG8E8_V, 0x0, 0x8 }, // 9022
|
|
{ PseudoVSSEG8E8_V_MF8, VSSEG8E8_V, 0x5, 0x8 }, // 9023
|
|
{ PseudoVSSEG8E8_V_MF8_MASK, VSSEG8E8_V, 0x5, 0x8 }, // 9024
|
|
{ PseudoVSSEG8E8_V_MF4, VSSEG8E8_V, 0x6, 0x8 }, // 9025
|
|
{ PseudoVSSEG8E8_V_MF4_MASK, VSSEG8E8_V, 0x6, 0x8 }, // 9026
|
|
{ PseudoVSSEG8E8_V_MF2, VSSEG8E8_V, 0x7, 0x8 }, // 9027
|
|
{ PseudoVSSEG8E8_V_MF2_MASK, VSSEG8E8_V, 0x7, 0x8 }, // 9028
|
|
{ PseudoVSSRA_VI_M1, VSSRA_VI, 0x0, 0x0 }, // 9029
|
|
{ PseudoVSSRA_VI_M1_MASK, VSSRA_VI, 0x0, 0x0 }, // 9030
|
|
{ PseudoVSSRA_VI_M2, VSSRA_VI, 0x1, 0x0 }, // 9031
|
|
{ PseudoVSSRA_VI_M2_MASK, VSSRA_VI, 0x1, 0x0 }, // 9032
|
|
{ PseudoVSSRA_VI_M4, VSSRA_VI, 0x2, 0x0 }, // 9033
|
|
{ PseudoVSSRA_VI_M4_MASK, VSSRA_VI, 0x2, 0x0 }, // 9034
|
|
{ PseudoVSSRA_VI_M8, VSSRA_VI, 0x3, 0x0 }, // 9035
|
|
{ PseudoVSSRA_VI_M8_MASK, VSSRA_VI, 0x3, 0x0 }, // 9036
|
|
{ PseudoVSSRA_VI_MF8, VSSRA_VI, 0x5, 0x0 }, // 9037
|
|
{ PseudoVSSRA_VI_MF8_MASK, VSSRA_VI, 0x5, 0x0 }, // 9038
|
|
{ PseudoVSSRA_VI_MF4, VSSRA_VI, 0x6, 0x0 }, // 9039
|
|
{ PseudoVSSRA_VI_MF4_MASK, VSSRA_VI, 0x6, 0x0 }, // 9040
|
|
{ PseudoVSSRA_VI_MF2, VSSRA_VI, 0x7, 0x0 }, // 9041
|
|
{ PseudoVSSRA_VI_MF2_MASK, VSSRA_VI, 0x7, 0x0 }, // 9042
|
|
{ PseudoVSSRA_VV_M1, VSSRA_VV, 0x0, 0x0 }, // 9043
|
|
{ PseudoVSSRA_VV_M1_MASK, VSSRA_VV, 0x0, 0x0 }, // 9044
|
|
{ PseudoVSSRA_VV_M2, VSSRA_VV, 0x1, 0x0 }, // 9045
|
|
{ PseudoVSSRA_VV_M2_MASK, VSSRA_VV, 0x1, 0x0 }, // 9046
|
|
{ PseudoVSSRA_VV_M4, VSSRA_VV, 0x2, 0x0 }, // 9047
|
|
{ PseudoVSSRA_VV_M4_MASK, VSSRA_VV, 0x2, 0x0 }, // 9048
|
|
{ PseudoVSSRA_VV_M8, VSSRA_VV, 0x3, 0x0 }, // 9049
|
|
{ PseudoVSSRA_VV_M8_MASK, VSSRA_VV, 0x3, 0x0 }, // 9050
|
|
{ PseudoVSSRA_VV_MF8, VSSRA_VV, 0x5, 0x0 }, // 9051
|
|
{ PseudoVSSRA_VV_MF8_MASK, VSSRA_VV, 0x5, 0x0 }, // 9052
|
|
{ PseudoVSSRA_VV_MF4, VSSRA_VV, 0x6, 0x0 }, // 9053
|
|
{ PseudoVSSRA_VV_MF4_MASK, VSSRA_VV, 0x6, 0x0 }, // 9054
|
|
{ PseudoVSSRA_VV_MF2, VSSRA_VV, 0x7, 0x0 }, // 9055
|
|
{ PseudoVSSRA_VV_MF2_MASK, VSSRA_VV, 0x7, 0x0 }, // 9056
|
|
{ PseudoVSSRA_VX_M1, VSSRA_VX, 0x0, 0x0 }, // 9057
|
|
{ PseudoVSSRA_VX_M1_MASK, VSSRA_VX, 0x0, 0x0 }, // 9058
|
|
{ PseudoVSSRA_VX_M2, VSSRA_VX, 0x1, 0x0 }, // 9059
|
|
{ PseudoVSSRA_VX_M2_MASK, VSSRA_VX, 0x1, 0x0 }, // 9060
|
|
{ PseudoVSSRA_VX_M4, VSSRA_VX, 0x2, 0x0 }, // 9061
|
|
{ PseudoVSSRA_VX_M4_MASK, VSSRA_VX, 0x2, 0x0 }, // 9062
|
|
{ PseudoVSSRA_VX_M8, VSSRA_VX, 0x3, 0x0 }, // 9063
|
|
{ PseudoVSSRA_VX_M8_MASK, VSSRA_VX, 0x3, 0x0 }, // 9064
|
|
{ PseudoVSSRA_VX_MF8, VSSRA_VX, 0x5, 0x0 }, // 9065
|
|
{ PseudoVSSRA_VX_MF8_MASK, VSSRA_VX, 0x5, 0x0 }, // 9066
|
|
{ PseudoVSSRA_VX_MF4, VSSRA_VX, 0x6, 0x0 }, // 9067
|
|
{ PseudoVSSRA_VX_MF4_MASK, VSSRA_VX, 0x6, 0x0 }, // 9068
|
|
{ PseudoVSSRA_VX_MF2, VSSRA_VX, 0x7, 0x0 }, // 9069
|
|
{ PseudoVSSRA_VX_MF2_MASK, VSSRA_VX, 0x7, 0x0 }, // 9070
|
|
{ PseudoVSSRL_VI_M1, VSSRL_VI, 0x0, 0x0 }, // 9071
|
|
{ PseudoVSSRL_VI_M1_MASK, VSSRL_VI, 0x0, 0x0 }, // 9072
|
|
{ PseudoVSSRL_VI_M2, VSSRL_VI, 0x1, 0x0 }, // 9073
|
|
{ PseudoVSSRL_VI_M2_MASK, VSSRL_VI, 0x1, 0x0 }, // 9074
|
|
{ PseudoVSSRL_VI_M4, VSSRL_VI, 0x2, 0x0 }, // 9075
|
|
{ PseudoVSSRL_VI_M4_MASK, VSSRL_VI, 0x2, 0x0 }, // 9076
|
|
{ PseudoVSSRL_VI_M8, VSSRL_VI, 0x3, 0x0 }, // 9077
|
|
{ PseudoVSSRL_VI_M8_MASK, VSSRL_VI, 0x3, 0x0 }, // 9078
|
|
{ PseudoVSSRL_VI_MF8, VSSRL_VI, 0x5, 0x0 }, // 9079
|
|
{ PseudoVSSRL_VI_MF8_MASK, VSSRL_VI, 0x5, 0x0 }, // 9080
|
|
{ PseudoVSSRL_VI_MF4, VSSRL_VI, 0x6, 0x0 }, // 9081
|
|
{ PseudoVSSRL_VI_MF4_MASK, VSSRL_VI, 0x6, 0x0 }, // 9082
|
|
{ PseudoVSSRL_VI_MF2, VSSRL_VI, 0x7, 0x0 }, // 9083
|
|
{ PseudoVSSRL_VI_MF2_MASK, VSSRL_VI, 0x7, 0x0 }, // 9084
|
|
{ PseudoVSSRL_VV_M1, VSSRL_VV, 0x0, 0x0 }, // 9085
|
|
{ PseudoVSSRL_VV_M1_MASK, VSSRL_VV, 0x0, 0x0 }, // 9086
|
|
{ PseudoVSSRL_VV_M2, VSSRL_VV, 0x1, 0x0 }, // 9087
|
|
{ PseudoVSSRL_VV_M2_MASK, VSSRL_VV, 0x1, 0x0 }, // 9088
|
|
{ PseudoVSSRL_VV_M4, VSSRL_VV, 0x2, 0x0 }, // 9089
|
|
{ PseudoVSSRL_VV_M4_MASK, VSSRL_VV, 0x2, 0x0 }, // 9090
|
|
{ PseudoVSSRL_VV_M8, VSSRL_VV, 0x3, 0x0 }, // 9091
|
|
{ PseudoVSSRL_VV_M8_MASK, VSSRL_VV, 0x3, 0x0 }, // 9092
|
|
{ PseudoVSSRL_VV_MF8, VSSRL_VV, 0x5, 0x0 }, // 9093
|
|
{ PseudoVSSRL_VV_MF8_MASK, VSSRL_VV, 0x5, 0x0 }, // 9094
|
|
{ PseudoVSSRL_VV_MF4, VSSRL_VV, 0x6, 0x0 }, // 9095
|
|
{ PseudoVSSRL_VV_MF4_MASK, VSSRL_VV, 0x6, 0x0 }, // 9096
|
|
{ PseudoVSSRL_VV_MF2, VSSRL_VV, 0x7, 0x0 }, // 9097
|
|
{ PseudoVSSRL_VV_MF2_MASK, VSSRL_VV, 0x7, 0x0 }, // 9098
|
|
{ PseudoVSSRL_VX_M1, VSSRL_VX, 0x0, 0x0 }, // 9099
|
|
{ PseudoVSSRL_VX_M1_MASK, VSSRL_VX, 0x0, 0x0 }, // 9100
|
|
{ PseudoVSSRL_VX_M2, VSSRL_VX, 0x1, 0x0 }, // 9101
|
|
{ PseudoVSSRL_VX_M2_MASK, VSSRL_VX, 0x1, 0x0 }, // 9102
|
|
{ PseudoVSSRL_VX_M4, VSSRL_VX, 0x2, 0x0 }, // 9103
|
|
{ PseudoVSSRL_VX_M4_MASK, VSSRL_VX, 0x2, 0x0 }, // 9104
|
|
{ PseudoVSSRL_VX_M8, VSSRL_VX, 0x3, 0x0 }, // 9105
|
|
{ PseudoVSSRL_VX_M8_MASK, VSSRL_VX, 0x3, 0x0 }, // 9106
|
|
{ PseudoVSSRL_VX_MF8, VSSRL_VX, 0x5, 0x0 }, // 9107
|
|
{ PseudoVSSRL_VX_MF8_MASK, VSSRL_VX, 0x5, 0x0 }, // 9108
|
|
{ PseudoVSSRL_VX_MF4, VSSRL_VX, 0x6, 0x0 }, // 9109
|
|
{ PseudoVSSRL_VX_MF4_MASK, VSSRL_VX, 0x6, 0x0 }, // 9110
|
|
{ PseudoVSSRL_VX_MF2, VSSRL_VX, 0x7, 0x0 }, // 9111
|
|
{ PseudoVSSRL_VX_MF2_MASK, VSSRL_VX, 0x7, 0x0 }, // 9112
|
|
{ PseudoVSSSEG2E16_V_M1, VSSSEG2E16_V, 0x0, 0x10 }, // 9113
|
|
{ PseudoVSSSEG2E16_V_M1_MASK, VSSSEG2E16_V, 0x0, 0x10 }, // 9114
|
|
{ PseudoVSSSEG2E16_V_M2, VSSSEG2E16_V, 0x1, 0x10 }, // 9115
|
|
{ PseudoVSSSEG2E16_V_M2_MASK, VSSSEG2E16_V, 0x1, 0x10 }, // 9116
|
|
{ PseudoVSSSEG2E16_V_M4, VSSSEG2E16_V, 0x2, 0x10 }, // 9117
|
|
{ PseudoVSSSEG2E16_V_M4_MASK, VSSSEG2E16_V, 0x2, 0x10 }, // 9118
|
|
{ PseudoVSSSEG2E16_V_MF4, VSSSEG2E16_V, 0x6, 0x10 }, // 9119
|
|
{ PseudoVSSSEG2E16_V_MF4_MASK, VSSSEG2E16_V, 0x6, 0x10 }, // 9120
|
|
{ PseudoVSSSEG2E16_V_MF2, VSSSEG2E16_V, 0x7, 0x10 }, // 9121
|
|
{ PseudoVSSSEG2E16_V_MF2_MASK, VSSSEG2E16_V, 0x7, 0x10 }, // 9122
|
|
{ PseudoVSSSEG2E32_V_M1, VSSSEG2E32_V, 0x0, 0x20 }, // 9123
|
|
{ PseudoVSSSEG2E32_V_M1_MASK, VSSSEG2E32_V, 0x0, 0x20 }, // 9124
|
|
{ PseudoVSSSEG2E32_V_M2, VSSSEG2E32_V, 0x1, 0x20 }, // 9125
|
|
{ PseudoVSSSEG2E32_V_M2_MASK, VSSSEG2E32_V, 0x1, 0x20 }, // 9126
|
|
{ PseudoVSSSEG2E32_V_M4, VSSSEG2E32_V, 0x2, 0x20 }, // 9127
|
|
{ PseudoVSSSEG2E32_V_M4_MASK, VSSSEG2E32_V, 0x2, 0x20 }, // 9128
|
|
{ PseudoVSSSEG2E32_V_MF2, VSSSEG2E32_V, 0x7, 0x20 }, // 9129
|
|
{ PseudoVSSSEG2E32_V_MF2_MASK, VSSSEG2E32_V, 0x7, 0x20 }, // 9130
|
|
{ PseudoVSSSEG2E64_V_M1, VSSSEG2E64_V, 0x0, 0x40 }, // 9131
|
|
{ PseudoVSSSEG2E64_V_M1_MASK, VSSSEG2E64_V, 0x0, 0x40 }, // 9132
|
|
{ PseudoVSSSEG2E64_V_M2, VSSSEG2E64_V, 0x1, 0x40 }, // 9133
|
|
{ PseudoVSSSEG2E64_V_M2_MASK, VSSSEG2E64_V, 0x1, 0x40 }, // 9134
|
|
{ PseudoVSSSEG2E64_V_M4, VSSSEG2E64_V, 0x2, 0x40 }, // 9135
|
|
{ PseudoVSSSEG2E64_V_M4_MASK, VSSSEG2E64_V, 0x2, 0x40 }, // 9136
|
|
{ PseudoVSSSEG2E8_V_M1, VSSSEG2E8_V, 0x0, 0x8 }, // 9137
|
|
{ PseudoVSSSEG2E8_V_M1_MASK, VSSSEG2E8_V, 0x0, 0x8 }, // 9138
|
|
{ PseudoVSSSEG2E8_V_M2, VSSSEG2E8_V, 0x1, 0x8 }, // 9139
|
|
{ PseudoVSSSEG2E8_V_M2_MASK, VSSSEG2E8_V, 0x1, 0x8 }, // 9140
|
|
{ PseudoVSSSEG2E8_V_M4, VSSSEG2E8_V, 0x2, 0x8 }, // 9141
|
|
{ PseudoVSSSEG2E8_V_M4_MASK, VSSSEG2E8_V, 0x2, 0x8 }, // 9142
|
|
{ PseudoVSSSEG2E8_V_MF8, VSSSEG2E8_V, 0x5, 0x8 }, // 9143
|
|
{ PseudoVSSSEG2E8_V_MF8_MASK, VSSSEG2E8_V, 0x5, 0x8 }, // 9144
|
|
{ PseudoVSSSEG2E8_V_MF4, VSSSEG2E8_V, 0x6, 0x8 }, // 9145
|
|
{ PseudoVSSSEG2E8_V_MF4_MASK, VSSSEG2E8_V, 0x6, 0x8 }, // 9146
|
|
{ PseudoVSSSEG2E8_V_MF2, VSSSEG2E8_V, 0x7, 0x8 }, // 9147
|
|
{ PseudoVSSSEG2E8_V_MF2_MASK, VSSSEG2E8_V, 0x7, 0x8 }, // 9148
|
|
{ PseudoVSSSEG3E16_V_M1, VSSSEG3E16_V, 0x0, 0x10 }, // 9149
|
|
{ PseudoVSSSEG3E16_V_M1_MASK, VSSSEG3E16_V, 0x0, 0x10 }, // 9150
|
|
{ PseudoVSSSEG3E16_V_M2, VSSSEG3E16_V, 0x1, 0x10 }, // 9151
|
|
{ PseudoVSSSEG3E16_V_M2_MASK, VSSSEG3E16_V, 0x1, 0x10 }, // 9152
|
|
{ PseudoVSSSEG3E16_V_MF4, VSSSEG3E16_V, 0x6, 0x10 }, // 9153
|
|
{ PseudoVSSSEG3E16_V_MF4_MASK, VSSSEG3E16_V, 0x6, 0x10 }, // 9154
|
|
{ PseudoVSSSEG3E16_V_MF2, VSSSEG3E16_V, 0x7, 0x10 }, // 9155
|
|
{ PseudoVSSSEG3E16_V_MF2_MASK, VSSSEG3E16_V, 0x7, 0x10 }, // 9156
|
|
{ PseudoVSSSEG3E32_V_M1, VSSSEG3E32_V, 0x0, 0x20 }, // 9157
|
|
{ PseudoVSSSEG3E32_V_M1_MASK, VSSSEG3E32_V, 0x0, 0x20 }, // 9158
|
|
{ PseudoVSSSEG3E32_V_M2, VSSSEG3E32_V, 0x1, 0x20 }, // 9159
|
|
{ PseudoVSSSEG3E32_V_M2_MASK, VSSSEG3E32_V, 0x1, 0x20 }, // 9160
|
|
{ PseudoVSSSEG3E32_V_MF2, VSSSEG3E32_V, 0x7, 0x20 }, // 9161
|
|
{ PseudoVSSSEG3E32_V_MF2_MASK, VSSSEG3E32_V, 0x7, 0x20 }, // 9162
|
|
{ PseudoVSSSEG3E64_V_M1, VSSSEG3E64_V, 0x0, 0x40 }, // 9163
|
|
{ PseudoVSSSEG3E64_V_M1_MASK, VSSSEG3E64_V, 0x0, 0x40 }, // 9164
|
|
{ PseudoVSSSEG3E64_V_M2, VSSSEG3E64_V, 0x1, 0x40 }, // 9165
|
|
{ PseudoVSSSEG3E64_V_M2_MASK, VSSSEG3E64_V, 0x1, 0x40 }, // 9166
|
|
{ PseudoVSSSEG3E8_V_M1, VSSSEG3E8_V, 0x0, 0x8 }, // 9167
|
|
{ PseudoVSSSEG3E8_V_M1_MASK, VSSSEG3E8_V, 0x0, 0x8 }, // 9168
|
|
{ PseudoVSSSEG3E8_V_M2, VSSSEG3E8_V, 0x1, 0x8 }, // 9169
|
|
{ PseudoVSSSEG3E8_V_M2_MASK, VSSSEG3E8_V, 0x1, 0x8 }, // 9170
|
|
{ PseudoVSSSEG3E8_V_MF8, VSSSEG3E8_V, 0x5, 0x8 }, // 9171
|
|
{ PseudoVSSSEG3E8_V_MF8_MASK, VSSSEG3E8_V, 0x5, 0x8 }, // 9172
|
|
{ PseudoVSSSEG3E8_V_MF4, VSSSEG3E8_V, 0x6, 0x8 }, // 9173
|
|
{ PseudoVSSSEG3E8_V_MF4_MASK, VSSSEG3E8_V, 0x6, 0x8 }, // 9174
|
|
{ PseudoVSSSEG3E8_V_MF2, VSSSEG3E8_V, 0x7, 0x8 }, // 9175
|
|
{ PseudoVSSSEG3E8_V_MF2_MASK, VSSSEG3E8_V, 0x7, 0x8 }, // 9176
|
|
{ PseudoVSSSEG4E16_V_M1, VSSSEG4E16_V, 0x0, 0x10 }, // 9177
|
|
{ PseudoVSSSEG4E16_V_M1_MASK, VSSSEG4E16_V, 0x0, 0x10 }, // 9178
|
|
{ PseudoVSSSEG4E16_V_M2, VSSSEG4E16_V, 0x1, 0x10 }, // 9179
|
|
{ PseudoVSSSEG4E16_V_M2_MASK, VSSSEG4E16_V, 0x1, 0x10 }, // 9180
|
|
{ PseudoVSSSEG4E16_V_MF4, VSSSEG4E16_V, 0x6, 0x10 }, // 9181
|
|
{ PseudoVSSSEG4E16_V_MF4_MASK, VSSSEG4E16_V, 0x6, 0x10 }, // 9182
|
|
{ PseudoVSSSEG4E16_V_MF2, VSSSEG4E16_V, 0x7, 0x10 }, // 9183
|
|
{ PseudoVSSSEG4E16_V_MF2_MASK, VSSSEG4E16_V, 0x7, 0x10 }, // 9184
|
|
{ PseudoVSSSEG4E32_V_M1, VSSSEG4E32_V, 0x0, 0x20 }, // 9185
|
|
{ PseudoVSSSEG4E32_V_M1_MASK, VSSSEG4E32_V, 0x0, 0x20 }, // 9186
|
|
{ PseudoVSSSEG4E32_V_M2, VSSSEG4E32_V, 0x1, 0x20 }, // 9187
|
|
{ PseudoVSSSEG4E32_V_M2_MASK, VSSSEG4E32_V, 0x1, 0x20 }, // 9188
|
|
{ PseudoVSSSEG4E32_V_MF2, VSSSEG4E32_V, 0x7, 0x20 }, // 9189
|
|
{ PseudoVSSSEG4E32_V_MF2_MASK, VSSSEG4E32_V, 0x7, 0x20 }, // 9190
|
|
{ PseudoVSSSEG4E64_V_M1, VSSSEG4E64_V, 0x0, 0x40 }, // 9191
|
|
{ PseudoVSSSEG4E64_V_M1_MASK, VSSSEG4E64_V, 0x0, 0x40 }, // 9192
|
|
{ PseudoVSSSEG4E64_V_M2, VSSSEG4E64_V, 0x1, 0x40 }, // 9193
|
|
{ PseudoVSSSEG4E64_V_M2_MASK, VSSSEG4E64_V, 0x1, 0x40 }, // 9194
|
|
{ PseudoVSSSEG4E8_V_M1, VSSSEG4E8_V, 0x0, 0x8 }, // 9195
|
|
{ PseudoVSSSEG4E8_V_M1_MASK, VSSSEG4E8_V, 0x0, 0x8 }, // 9196
|
|
{ PseudoVSSSEG4E8_V_M2, VSSSEG4E8_V, 0x1, 0x8 }, // 9197
|
|
{ PseudoVSSSEG4E8_V_M2_MASK, VSSSEG4E8_V, 0x1, 0x8 }, // 9198
|
|
{ PseudoVSSSEG4E8_V_MF8, VSSSEG4E8_V, 0x5, 0x8 }, // 9199
|
|
{ PseudoVSSSEG4E8_V_MF8_MASK, VSSSEG4E8_V, 0x5, 0x8 }, // 9200
|
|
{ PseudoVSSSEG4E8_V_MF4, VSSSEG4E8_V, 0x6, 0x8 }, // 9201
|
|
{ PseudoVSSSEG4E8_V_MF4_MASK, VSSSEG4E8_V, 0x6, 0x8 }, // 9202
|
|
{ PseudoVSSSEG4E8_V_MF2, VSSSEG4E8_V, 0x7, 0x8 }, // 9203
|
|
{ PseudoVSSSEG4E8_V_MF2_MASK, VSSSEG4E8_V, 0x7, 0x8 }, // 9204
|
|
{ PseudoVSSSEG5E16_V_M1, VSSSEG5E16_V, 0x0, 0x10 }, // 9205
|
|
{ PseudoVSSSEG5E16_V_M1_MASK, VSSSEG5E16_V, 0x0, 0x10 }, // 9206
|
|
{ PseudoVSSSEG5E16_V_MF4, VSSSEG5E16_V, 0x6, 0x10 }, // 9207
|
|
{ PseudoVSSSEG5E16_V_MF4_MASK, VSSSEG5E16_V, 0x6, 0x10 }, // 9208
|
|
{ PseudoVSSSEG5E16_V_MF2, VSSSEG5E16_V, 0x7, 0x10 }, // 9209
|
|
{ PseudoVSSSEG5E16_V_MF2_MASK, VSSSEG5E16_V, 0x7, 0x10 }, // 9210
|
|
{ PseudoVSSSEG5E32_V_M1, VSSSEG5E32_V, 0x0, 0x20 }, // 9211
|
|
{ PseudoVSSSEG5E32_V_M1_MASK, VSSSEG5E32_V, 0x0, 0x20 }, // 9212
|
|
{ PseudoVSSSEG5E32_V_MF2, VSSSEG5E32_V, 0x7, 0x20 }, // 9213
|
|
{ PseudoVSSSEG5E32_V_MF2_MASK, VSSSEG5E32_V, 0x7, 0x20 }, // 9214
|
|
{ PseudoVSSSEG5E64_V_M1, VSSSEG5E64_V, 0x0, 0x40 }, // 9215
|
|
{ PseudoVSSSEG5E64_V_M1_MASK, VSSSEG5E64_V, 0x0, 0x40 }, // 9216
|
|
{ PseudoVSSSEG5E8_V_M1, VSSSEG5E8_V, 0x0, 0x8 }, // 9217
|
|
{ PseudoVSSSEG5E8_V_M1_MASK, VSSSEG5E8_V, 0x0, 0x8 }, // 9218
|
|
{ PseudoVSSSEG5E8_V_MF8, VSSSEG5E8_V, 0x5, 0x8 }, // 9219
|
|
{ PseudoVSSSEG5E8_V_MF8_MASK, VSSSEG5E8_V, 0x5, 0x8 }, // 9220
|
|
{ PseudoVSSSEG5E8_V_MF4, VSSSEG5E8_V, 0x6, 0x8 }, // 9221
|
|
{ PseudoVSSSEG5E8_V_MF4_MASK, VSSSEG5E8_V, 0x6, 0x8 }, // 9222
|
|
{ PseudoVSSSEG5E8_V_MF2, VSSSEG5E8_V, 0x7, 0x8 }, // 9223
|
|
{ PseudoVSSSEG5E8_V_MF2_MASK, VSSSEG5E8_V, 0x7, 0x8 }, // 9224
|
|
{ PseudoVSSSEG6E16_V_M1, VSSSEG6E16_V, 0x0, 0x10 }, // 9225
|
|
{ PseudoVSSSEG6E16_V_M1_MASK, VSSSEG6E16_V, 0x0, 0x10 }, // 9226
|
|
{ PseudoVSSSEG6E16_V_MF4, VSSSEG6E16_V, 0x6, 0x10 }, // 9227
|
|
{ PseudoVSSSEG6E16_V_MF4_MASK, VSSSEG6E16_V, 0x6, 0x10 }, // 9228
|
|
{ PseudoVSSSEG6E16_V_MF2, VSSSEG6E16_V, 0x7, 0x10 }, // 9229
|
|
{ PseudoVSSSEG6E16_V_MF2_MASK, VSSSEG6E16_V, 0x7, 0x10 }, // 9230
|
|
{ PseudoVSSSEG6E32_V_M1, VSSSEG6E32_V, 0x0, 0x20 }, // 9231
|
|
{ PseudoVSSSEG6E32_V_M1_MASK, VSSSEG6E32_V, 0x0, 0x20 }, // 9232
|
|
{ PseudoVSSSEG6E32_V_MF2, VSSSEG6E32_V, 0x7, 0x20 }, // 9233
|
|
{ PseudoVSSSEG6E32_V_MF2_MASK, VSSSEG6E32_V, 0x7, 0x20 }, // 9234
|
|
{ PseudoVSSSEG6E64_V_M1, VSSSEG6E64_V, 0x0, 0x40 }, // 9235
|
|
{ PseudoVSSSEG6E64_V_M1_MASK, VSSSEG6E64_V, 0x0, 0x40 }, // 9236
|
|
{ PseudoVSSSEG6E8_V_M1, VSSSEG6E8_V, 0x0, 0x8 }, // 9237
|
|
{ PseudoVSSSEG6E8_V_M1_MASK, VSSSEG6E8_V, 0x0, 0x8 }, // 9238
|
|
{ PseudoVSSSEG6E8_V_MF8, VSSSEG6E8_V, 0x5, 0x8 }, // 9239
|
|
{ PseudoVSSSEG6E8_V_MF8_MASK, VSSSEG6E8_V, 0x5, 0x8 }, // 9240
|
|
{ PseudoVSSSEG6E8_V_MF4, VSSSEG6E8_V, 0x6, 0x8 }, // 9241
|
|
{ PseudoVSSSEG6E8_V_MF4_MASK, VSSSEG6E8_V, 0x6, 0x8 }, // 9242
|
|
{ PseudoVSSSEG6E8_V_MF2, VSSSEG6E8_V, 0x7, 0x8 }, // 9243
|
|
{ PseudoVSSSEG6E8_V_MF2_MASK, VSSSEG6E8_V, 0x7, 0x8 }, // 9244
|
|
{ PseudoVSSSEG7E16_V_M1, VSSSEG7E16_V, 0x0, 0x10 }, // 9245
|
|
{ PseudoVSSSEG7E16_V_M1_MASK, VSSSEG7E16_V, 0x0, 0x10 }, // 9246
|
|
{ PseudoVSSSEG7E16_V_MF4, VSSSEG7E16_V, 0x6, 0x10 }, // 9247
|
|
{ PseudoVSSSEG7E16_V_MF4_MASK, VSSSEG7E16_V, 0x6, 0x10 }, // 9248
|
|
{ PseudoVSSSEG7E16_V_MF2, VSSSEG7E16_V, 0x7, 0x10 }, // 9249
|
|
{ PseudoVSSSEG7E16_V_MF2_MASK, VSSSEG7E16_V, 0x7, 0x10 }, // 9250
|
|
{ PseudoVSSSEG7E32_V_M1, VSSSEG7E32_V, 0x0, 0x20 }, // 9251
|
|
{ PseudoVSSSEG7E32_V_M1_MASK, VSSSEG7E32_V, 0x0, 0x20 }, // 9252
|
|
{ PseudoVSSSEG7E32_V_MF2, VSSSEG7E32_V, 0x7, 0x20 }, // 9253
|
|
{ PseudoVSSSEG7E32_V_MF2_MASK, VSSSEG7E32_V, 0x7, 0x20 }, // 9254
|
|
{ PseudoVSSSEG7E64_V_M1, VSSSEG7E64_V, 0x0, 0x40 }, // 9255
|
|
{ PseudoVSSSEG7E64_V_M1_MASK, VSSSEG7E64_V, 0x0, 0x40 }, // 9256
|
|
{ PseudoVSSSEG7E8_V_M1, VSSSEG7E8_V, 0x0, 0x8 }, // 9257
|
|
{ PseudoVSSSEG7E8_V_M1_MASK, VSSSEG7E8_V, 0x0, 0x8 }, // 9258
|
|
{ PseudoVSSSEG7E8_V_MF8, VSSSEG7E8_V, 0x5, 0x8 }, // 9259
|
|
{ PseudoVSSSEG7E8_V_MF8_MASK, VSSSEG7E8_V, 0x5, 0x8 }, // 9260
|
|
{ PseudoVSSSEG7E8_V_MF4, VSSSEG7E8_V, 0x6, 0x8 }, // 9261
|
|
{ PseudoVSSSEG7E8_V_MF4_MASK, VSSSEG7E8_V, 0x6, 0x8 }, // 9262
|
|
{ PseudoVSSSEG7E8_V_MF2, VSSSEG7E8_V, 0x7, 0x8 }, // 9263
|
|
{ PseudoVSSSEG7E8_V_MF2_MASK, VSSSEG7E8_V, 0x7, 0x8 }, // 9264
|
|
{ PseudoVSSSEG8E16_V_M1, VSSSEG8E16_V, 0x0, 0x10 }, // 9265
|
|
{ PseudoVSSSEG8E16_V_M1_MASK, VSSSEG8E16_V, 0x0, 0x10 }, // 9266
|
|
{ PseudoVSSSEG8E16_V_MF4, VSSSEG8E16_V, 0x6, 0x10 }, // 9267
|
|
{ PseudoVSSSEG8E16_V_MF4_MASK, VSSSEG8E16_V, 0x6, 0x10 }, // 9268
|
|
{ PseudoVSSSEG8E16_V_MF2, VSSSEG8E16_V, 0x7, 0x10 }, // 9269
|
|
{ PseudoVSSSEG8E16_V_MF2_MASK, VSSSEG8E16_V, 0x7, 0x10 }, // 9270
|
|
{ PseudoVSSSEG8E32_V_M1, VSSSEG8E32_V, 0x0, 0x20 }, // 9271
|
|
{ PseudoVSSSEG8E32_V_M1_MASK, VSSSEG8E32_V, 0x0, 0x20 }, // 9272
|
|
{ PseudoVSSSEG8E32_V_MF2, VSSSEG8E32_V, 0x7, 0x20 }, // 9273
|
|
{ PseudoVSSSEG8E32_V_MF2_MASK, VSSSEG8E32_V, 0x7, 0x20 }, // 9274
|
|
{ PseudoVSSSEG8E64_V_M1, VSSSEG8E64_V, 0x0, 0x40 }, // 9275
|
|
{ PseudoVSSSEG8E64_V_M1_MASK, VSSSEG8E64_V, 0x0, 0x40 }, // 9276
|
|
{ PseudoVSSSEG8E8_V_M1, VSSSEG8E8_V, 0x0, 0x8 }, // 9277
|
|
{ PseudoVSSSEG8E8_V_M1_MASK, VSSSEG8E8_V, 0x0, 0x8 }, // 9278
|
|
{ PseudoVSSSEG8E8_V_MF8, VSSSEG8E8_V, 0x5, 0x8 }, // 9279
|
|
{ PseudoVSSSEG8E8_V_MF8_MASK, VSSSEG8E8_V, 0x5, 0x8 }, // 9280
|
|
{ PseudoVSSSEG8E8_V_MF4, VSSSEG8E8_V, 0x6, 0x8 }, // 9281
|
|
{ PseudoVSSSEG8E8_V_MF4_MASK, VSSSEG8E8_V, 0x6, 0x8 }, // 9282
|
|
{ PseudoVSSSEG8E8_V_MF2, VSSSEG8E8_V, 0x7, 0x8 }, // 9283
|
|
{ PseudoVSSSEG8E8_V_MF2_MASK, VSSSEG8E8_V, 0x7, 0x8 }, // 9284
|
|
{ PseudoVSSUBU_VV_M1, VSSUBU_VV, 0x0, 0x0 }, // 9285
|
|
{ PseudoVSSUBU_VV_M1_MASK, VSSUBU_VV, 0x0, 0x0 }, // 9286
|
|
{ PseudoVSSUBU_VV_M2, VSSUBU_VV, 0x1, 0x0 }, // 9287
|
|
{ PseudoVSSUBU_VV_M2_MASK, VSSUBU_VV, 0x1, 0x0 }, // 9288
|
|
{ PseudoVSSUBU_VV_M4, VSSUBU_VV, 0x2, 0x0 }, // 9289
|
|
{ PseudoVSSUBU_VV_M4_MASK, VSSUBU_VV, 0x2, 0x0 }, // 9290
|
|
{ PseudoVSSUBU_VV_M8, VSSUBU_VV, 0x3, 0x0 }, // 9291
|
|
{ PseudoVSSUBU_VV_M8_MASK, VSSUBU_VV, 0x3, 0x0 }, // 9292
|
|
{ PseudoVSSUBU_VV_MF8, VSSUBU_VV, 0x5, 0x0 }, // 9293
|
|
{ PseudoVSSUBU_VV_MF8_MASK, VSSUBU_VV, 0x5, 0x0 }, // 9294
|
|
{ PseudoVSSUBU_VV_MF4, VSSUBU_VV, 0x6, 0x0 }, // 9295
|
|
{ PseudoVSSUBU_VV_MF4_MASK, VSSUBU_VV, 0x6, 0x0 }, // 9296
|
|
{ PseudoVSSUBU_VV_MF2, VSSUBU_VV, 0x7, 0x0 }, // 9297
|
|
{ PseudoVSSUBU_VV_MF2_MASK, VSSUBU_VV, 0x7, 0x0 }, // 9298
|
|
{ PseudoVSSUBU_VX_M1, VSSUBU_VX, 0x0, 0x0 }, // 9299
|
|
{ PseudoVSSUBU_VX_M1_MASK, VSSUBU_VX, 0x0, 0x0 }, // 9300
|
|
{ PseudoVSSUBU_VX_M2, VSSUBU_VX, 0x1, 0x0 }, // 9301
|
|
{ PseudoVSSUBU_VX_M2_MASK, VSSUBU_VX, 0x1, 0x0 }, // 9302
|
|
{ PseudoVSSUBU_VX_M4, VSSUBU_VX, 0x2, 0x0 }, // 9303
|
|
{ PseudoVSSUBU_VX_M4_MASK, VSSUBU_VX, 0x2, 0x0 }, // 9304
|
|
{ PseudoVSSUBU_VX_M8, VSSUBU_VX, 0x3, 0x0 }, // 9305
|
|
{ PseudoVSSUBU_VX_M8_MASK, VSSUBU_VX, 0x3, 0x0 }, // 9306
|
|
{ PseudoVSSUBU_VX_MF8, VSSUBU_VX, 0x5, 0x0 }, // 9307
|
|
{ PseudoVSSUBU_VX_MF8_MASK, VSSUBU_VX, 0x5, 0x0 }, // 9308
|
|
{ PseudoVSSUBU_VX_MF4, VSSUBU_VX, 0x6, 0x0 }, // 9309
|
|
{ PseudoVSSUBU_VX_MF4_MASK, VSSUBU_VX, 0x6, 0x0 }, // 9310
|
|
{ PseudoVSSUBU_VX_MF2, VSSUBU_VX, 0x7, 0x0 }, // 9311
|
|
{ PseudoVSSUBU_VX_MF2_MASK, VSSUBU_VX, 0x7, 0x0 }, // 9312
|
|
{ PseudoVSSUB_VV_M1, VSSUB_VV, 0x0, 0x0 }, // 9313
|
|
{ PseudoVSSUB_VV_M1_MASK, VSSUB_VV, 0x0, 0x0 }, // 9314
|
|
{ PseudoVSSUB_VV_M2, VSSUB_VV, 0x1, 0x0 }, // 9315
|
|
{ PseudoVSSUB_VV_M2_MASK, VSSUB_VV, 0x1, 0x0 }, // 9316
|
|
{ PseudoVSSUB_VV_M4, VSSUB_VV, 0x2, 0x0 }, // 9317
|
|
{ PseudoVSSUB_VV_M4_MASK, VSSUB_VV, 0x2, 0x0 }, // 9318
|
|
{ PseudoVSSUB_VV_M8, VSSUB_VV, 0x3, 0x0 }, // 9319
|
|
{ PseudoVSSUB_VV_M8_MASK, VSSUB_VV, 0x3, 0x0 }, // 9320
|
|
{ PseudoVSSUB_VV_MF8, VSSUB_VV, 0x5, 0x0 }, // 9321
|
|
{ PseudoVSSUB_VV_MF8_MASK, VSSUB_VV, 0x5, 0x0 }, // 9322
|
|
{ PseudoVSSUB_VV_MF4, VSSUB_VV, 0x6, 0x0 }, // 9323
|
|
{ PseudoVSSUB_VV_MF4_MASK, VSSUB_VV, 0x6, 0x0 }, // 9324
|
|
{ PseudoVSSUB_VV_MF2, VSSUB_VV, 0x7, 0x0 }, // 9325
|
|
{ PseudoVSSUB_VV_MF2_MASK, VSSUB_VV, 0x7, 0x0 }, // 9326
|
|
{ PseudoVSSUB_VX_M1, VSSUB_VX, 0x0, 0x0 }, // 9327
|
|
{ PseudoVSSUB_VX_M1_MASK, VSSUB_VX, 0x0, 0x0 }, // 9328
|
|
{ PseudoVSSUB_VX_M2, VSSUB_VX, 0x1, 0x0 }, // 9329
|
|
{ PseudoVSSUB_VX_M2_MASK, VSSUB_VX, 0x1, 0x0 }, // 9330
|
|
{ PseudoVSSUB_VX_M4, VSSUB_VX, 0x2, 0x0 }, // 9331
|
|
{ PseudoVSSUB_VX_M4_MASK, VSSUB_VX, 0x2, 0x0 }, // 9332
|
|
{ PseudoVSSUB_VX_M8, VSSUB_VX, 0x3, 0x0 }, // 9333
|
|
{ PseudoVSSUB_VX_M8_MASK, VSSUB_VX, 0x3, 0x0 }, // 9334
|
|
{ PseudoVSSUB_VX_MF8, VSSUB_VX, 0x5, 0x0 }, // 9335
|
|
{ PseudoVSSUB_VX_MF8_MASK, VSSUB_VX, 0x5, 0x0 }, // 9336
|
|
{ PseudoVSSUB_VX_MF4, VSSUB_VX, 0x6, 0x0 }, // 9337
|
|
{ PseudoVSSUB_VX_MF4_MASK, VSSUB_VX, 0x6, 0x0 }, // 9338
|
|
{ PseudoVSSUB_VX_MF2, VSSUB_VX, 0x7, 0x0 }, // 9339
|
|
{ PseudoVSSUB_VX_MF2_MASK, VSSUB_VX, 0x7, 0x0 }, // 9340
|
|
{ PseudoVSUB_VV_M1, VSUB_VV, 0x0, 0x0 }, // 9341
|
|
{ PseudoVSUB_VV_M1_MASK, VSUB_VV, 0x0, 0x0 }, // 9342
|
|
{ PseudoVSUB_VV_M2, VSUB_VV, 0x1, 0x0 }, // 9343
|
|
{ PseudoVSUB_VV_M2_MASK, VSUB_VV, 0x1, 0x0 }, // 9344
|
|
{ PseudoVSUB_VV_M4, VSUB_VV, 0x2, 0x0 }, // 9345
|
|
{ PseudoVSUB_VV_M4_MASK, VSUB_VV, 0x2, 0x0 }, // 9346
|
|
{ PseudoVSUB_VV_M8, VSUB_VV, 0x3, 0x0 }, // 9347
|
|
{ PseudoVSUB_VV_M8_MASK, VSUB_VV, 0x3, 0x0 }, // 9348
|
|
{ PseudoVSUB_VV_MF8, VSUB_VV, 0x5, 0x0 }, // 9349
|
|
{ PseudoVSUB_VV_MF8_MASK, VSUB_VV, 0x5, 0x0 }, // 9350
|
|
{ PseudoVSUB_VV_MF4, VSUB_VV, 0x6, 0x0 }, // 9351
|
|
{ PseudoVSUB_VV_MF4_MASK, VSUB_VV, 0x6, 0x0 }, // 9352
|
|
{ PseudoVSUB_VV_MF2, VSUB_VV, 0x7, 0x0 }, // 9353
|
|
{ PseudoVSUB_VV_MF2_MASK, VSUB_VV, 0x7, 0x0 }, // 9354
|
|
{ PseudoVSUB_VX_M1, VSUB_VX, 0x0, 0x0 }, // 9355
|
|
{ PseudoVSUB_VX_M1_MASK, VSUB_VX, 0x0, 0x0 }, // 9356
|
|
{ PseudoVSUB_VX_M2, VSUB_VX, 0x1, 0x0 }, // 9357
|
|
{ PseudoVSUB_VX_M2_MASK, VSUB_VX, 0x1, 0x0 }, // 9358
|
|
{ PseudoVSUB_VX_M4, VSUB_VX, 0x2, 0x0 }, // 9359
|
|
{ PseudoVSUB_VX_M4_MASK, VSUB_VX, 0x2, 0x0 }, // 9360
|
|
{ PseudoVSUB_VX_M8, VSUB_VX, 0x3, 0x0 }, // 9361
|
|
{ PseudoVSUB_VX_M8_MASK, VSUB_VX, 0x3, 0x0 }, // 9362
|
|
{ PseudoVSUB_VX_MF8, VSUB_VX, 0x5, 0x0 }, // 9363
|
|
{ PseudoVSUB_VX_MF8_MASK, VSUB_VX, 0x5, 0x0 }, // 9364
|
|
{ PseudoVSUB_VX_MF4, VSUB_VX, 0x6, 0x0 }, // 9365
|
|
{ PseudoVSUB_VX_MF4_MASK, VSUB_VX, 0x6, 0x0 }, // 9366
|
|
{ PseudoVSUB_VX_MF2, VSUB_VX, 0x7, 0x0 }, // 9367
|
|
{ PseudoVSUB_VX_MF2_MASK, VSUB_VX, 0x7, 0x0 }, // 9368
|
|
{ PseudoVSUXEI16_V_M1_M1, VSUXEI16_V, 0x0, 0x0 }, // 9369
|
|
{ PseudoVSUXEI16_V_M1_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9370
|
|
{ PseudoVSUXEI16_V_M2_M1, VSUXEI16_V, 0x0, 0x0 }, // 9371
|
|
{ PseudoVSUXEI16_V_M2_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9372
|
|
{ PseudoVSUXEI16_V_MF2_M1, VSUXEI16_V, 0x0, 0x0 }, // 9373
|
|
{ PseudoVSUXEI16_V_MF2_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9374
|
|
{ PseudoVSUXEI16_V_MF4_M1, VSUXEI16_V, 0x0, 0x0 }, // 9375
|
|
{ PseudoVSUXEI16_V_MF4_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9376
|
|
{ PseudoVSUXEI16_V_M1_M2, VSUXEI16_V, 0x1, 0x0 }, // 9377
|
|
{ PseudoVSUXEI16_V_M1_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9378
|
|
{ PseudoVSUXEI16_V_M2_M2, VSUXEI16_V, 0x1, 0x0 }, // 9379
|
|
{ PseudoVSUXEI16_V_M2_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9380
|
|
{ PseudoVSUXEI16_V_M4_M2, VSUXEI16_V, 0x1, 0x0 }, // 9381
|
|
{ PseudoVSUXEI16_V_M4_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9382
|
|
{ PseudoVSUXEI16_V_MF2_M2, VSUXEI16_V, 0x1, 0x0 }, // 9383
|
|
{ PseudoVSUXEI16_V_MF2_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9384
|
|
{ PseudoVSUXEI16_V_M1_M4, VSUXEI16_V, 0x2, 0x0 }, // 9385
|
|
{ PseudoVSUXEI16_V_M1_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9386
|
|
{ PseudoVSUXEI16_V_M2_M4, VSUXEI16_V, 0x2, 0x0 }, // 9387
|
|
{ PseudoVSUXEI16_V_M2_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9388
|
|
{ PseudoVSUXEI16_V_M4_M4, VSUXEI16_V, 0x2, 0x0 }, // 9389
|
|
{ PseudoVSUXEI16_V_M4_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9390
|
|
{ PseudoVSUXEI16_V_M8_M4, VSUXEI16_V, 0x2, 0x0 }, // 9391
|
|
{ PseudoVSUXEI16_V_M8_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9392
|
|
{ PseudoVSUXEI16_V_M2_M8, VSUXEI16_V, 0x3, 0x0 }, // 9393
|
|
{ PseudoVSUXEI16_V_M2_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9394
|
|
{ PseudoVSUXEI16_V_M4_M8, VSUXEI16_V, 0x3, 0x0 }, // 9395
|
|
{ PseudoVSUXEI16_V_M4_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9396
|
|
{ PseudoVSUXEI16_V_M8_M8, VSUXEI16_V, 0x3, 0x0 }, // 9397
|
|
{ PseudoVSUXEI16_V_M8_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9398
|
|
{ PseudoVSUXEI16_V_MF4_MF8, VSUXEI16_V, 0x5, 0x0 }, // 9399
|
|
{ PseudoVSUXEI16_V_MF4_MF8_MASK, VSUXEI16_V, 0x5, 0x0 }, // 9400
|
|
{ PseudoVSUXEI16_V_MF2_MF4, VSUXEI16_V, 0x6, 0x0 }, // 9401
|
|
{ PseudoVSUXEI16_V_MF2_MF4_MASK, VSUXEI16_V, 0x6, 0x0 }, // 9402
|
|
{ PseudoVSUXEI16_V_MF4_MF4, VSUXEI16_V, 0x6, 0x0 }, // 9403
|
|
{ PseudoVSUXEI16_V_MF4_MF4_MASK, VSUXEI16_V, 0x6, 0x0 }, // 9404
|
|
{ PseudoVSUXEI16_V_M1_MF2, VSUXEI16_V, 0x7, 0x0 }, // 9405
|
|
{ PseudoVSUXEI16_V_M1_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 9406
|
|
{ PseudoVSUXEI16_V_MF2_MF2, VSUXEI16_V, 0x7, 0x0 }, // 9407
|
|
{ PseudoVSUXEI16_V_MF2_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 9408
|
|
{ PseudoVSUXEI16_V_MF4_MF2, VSUXEI16_V, 0x7, 0x0 }, // 9409
|
|
{ PseudoVSUXEI16_V_MF4_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 9410
|
|
{ PseudoVSUXEI32_V_M1_M1, VSUXEI32_V, 0x0, 0x0 }, // 9411
|
|
{ PseudoVSUXEI32_V_M1_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9412
|
|
{ PseudoVSUXEI32_V_M2_M1, VSUXEI32_V, 0x0, 0x0 }, // 9413
|
|
{ PseudoVSUXEI32_V_M2_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9414
|
|
{ PseudoVSUXEI32_V_M4_M1, VSUXEI32_V, 0x0, 0x0 }, // 9415
|
|
{ PseudoVSUXEI32_V_M4_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9416
|
|
{ PseudoVSUXEI32_V_MF2_M1, VSUXEI32_V, 0x0, 0x0 }, // 9417
|
|
{ PseudoVSUXEI32_V_MF2_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9418
|
|
{ PseudoVSUXEI32_V_M1_M2, VSUXEI32_V, 0x1, 0x0 }, // 9419
|
|
{ PseudoVSUXEI32_V_M1_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9420
|
|
{ PseudoVSUXEI32_V_M2_M2, VSUXEI32_V, 0x1, 0x0 }, // 9421
|
|
{ PseudoVSUXEI32_V_M2_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9422
|
|
{ PseudoVSUXEI32_V_M4_M2, VSUXEI32_V, 0x1, 0x0 }, // 9423
|
|
{ PseudoVSUXEI32_V_M4_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9424
|
|
{ PseudoVSUXEI32_V_M8_M2, VSUXEI32_V, 0x1, 0x0 }, // 9425
|
|
{ PseudoVSUXEI32_V_M8_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9426
|
|
{ PseudoVSUXEI32_V_M2_M4, VSUXEI32_V, 0x2, 0x0 }, // 9427
|
|
{ PseudoVSUXEI32_V_M2_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 9428
|
|
{ PseudoVSUXEI32_V_M4_M4, VSUXEI32_V, 0x2, 0x0 }, // 9429
|
|
{ PseudoVSUXEI32_V_M4_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 9430
|
|
{ PseudoVSUXEI32_V_M8_M4, VSUXEI32_V, 0x2, 0x0 }, // 9431
|
|
{ PseudoVSUXEI32_V_M8_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 9432
|
|
{ PseudoVSUXEI32_V_M4_M8, VSUXEI32_V, 0x3, 0x0 }, // 9433
|
|
{ PseudoVSUXEI32_V_M4_M8_MASK, VSUXEI32_V, 0x3, 0x0 }, // 9434
|
|
{ PseudoVSUXEI32_V_M8_M8, VSUXEI32_V, 0x3, 0x0 }, // 9435
|
|
{ PseudoVSUXEI32_V_M8_M8_MASK, VSUXEI32_V, 0x3, 0x0 }, // 9436
|
|
{ PseudoVSUXEI32_V_MF2_MF8, VSUXEI32_V, 0x5, 0x0 }, // 9437
|
|
{ PseudoVSUXEI32_V_MF2_MF8_MASK, VSUXEI32_V, 0x5, 0x0 }, // 9438
|
|
{ PseudoVSUXEI32_V_M1_MF4, VSUXEI32_V, 0x6, 0x0 }, // 9439
|
|
{ PseudoVSUXEI32_V_M1_MF4_MASK, VSUXEI32_V, 0x6, 0x0 }, // 9440
|
|
{ PseudoVSUXEI32_V_MF2_MF4, VSUXEI32_V, 0x6, 0x0 }, // 9441
|
|
{ PseudoVSUXEI32_V_MF2_MF4_MASK, VSUXEI32_V, 0x6, 0x0 }, // 9442
|
|
{ PseudoVSUXEI32_V_M1_MF2, VSUXEI32_V, 0x7, 0x0 }, // 9443
|
|
{ PseudoVSUXEI32_V_M1_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 9444
|
|
{ PseudoVSUXEI32_V_M2_MF2, VSUXEI32_V, 0x7, 0x0 }, // 9445
|
|
{ PseudoVSUXEI32_V_M2_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 9446
|
|
{ PseudoVSUXEI32_V_MF2_MF2, VSUXEI32_V, 0x7, 0x0 }, // 9447
|
|
{ PseudoVSUXEI32_V_MF2_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 9448
|
|
{ PseudoVSUXEI64_V_M1_M1, VSUXEI64_V, 0x0, 0x0 }, // 9449
|
|
{ PseudoVSUXEI64_V_M1_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9450
|
|
{ PseudoVSUXEI64_V_M2_M1, VSUXEI64_V, 0x0, 0x0 }, // 9451
|
|
{ PseudoVSUXEI64_V_M2_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9452
|
|
{ PseudoVSUXEI64_V_M4_M1, VSUXEI64_V, 0x0, 0x0 }, // 9453
|
|
{ PseudoVSUXEI64_V_M4_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9454
|
|
{ PseudoVSUXEI64_V_M8_M1, VSUXEI64_V, 0x0, 0x0 }, // 9455
|
|
{ PseudoVSUXEI64_V_M8_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9456
|
|
{ PseudoVSUXEI64_V_M2_M2, VSUXEI64_V, 0x1, 0x0 }, // 9457
|
|
{ PseudoVSUXEI64_V_M2_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 9458
|
|
{ PseudoVSUXEI64_V_M4_M2, VSUXEI64_V, 0x1, 0x0 }, // 9459
|
|
{ PseudoVSUXEI64_V_M4_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 9460
|
|
{ PseudoVSUXEI64_V_M8_M2, VSUXEI64_V, 0x1, 0x0 }, // 9461
|
|
{ PseudoVSUXEI64_V_M8_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 9462
|
|
{ PseudoVSUXEI64_V_M4_M4, VSUXEI64_V, 0x2, 0x0 }, // 9463
|
|
{ PseudoVSUXEI64_V_M4_M4_MASK, VSUXEI64_V, 0x2, 0x0 }, // 9464
|
|
{ PseudoVSUXEI64_V_M8_M4, VSUXEI64_V, 0x2, 0x0 }, // 9465
|
|
{ PseudoVSUXEI64_V_M8_M4_MASK, VSUXEI64_V, 0x2, 0x0 }, // 9466
|
|
{ PseudoVSUXEI64_V_M8_M8, VSUXEI64_V, 0x3, 0x0 }, // 9467
|
|
{ PseudoVSUXEI64_V_M8_M8_MASK, VSUXEI64_V, 0x3, 0x0 }, // 9468
|
|
{ PseudoVSUXEI64_V_M1_MF8, VSUXEI64_V, 0x5, 0x0 }, // 9469
|
|
{ PseudoVSUXEI64_V_M1_MF8_MASK, VSUXEI64_V, 0x5, 0x0 }, // 9470
|
|
{ PseudoVSUXEI64_V_M1_MF4, VSUXEI64_V, 0x6, 0x0 }, // 9471
|
|
{ PseudoVSUXEI64_V_M1_MF4_MASK, VSUXEI64_V, 0x6, 0x0 }, // 9472
|
|
{ PseudoVSUXEI64_V_M2_MF4, VSUXEI64_V, 0x6, 0x0 }, // 9473
|
|
{ PseudoVSUXEI64_V_M2_MF4_MASK, VSUXEI64_V, 0x6, 0x0 }, // 9474
|
|
{ PseudoVSUXEI64_V_M1_MF2, VSUXEI64_V, 0x7, 0x0 }, // 9475
|
|
{ PseudoVSUXEI64_V_M1_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 9476
|
|
{ PseudoVSUXEI64_V_M2_MF2, VSUXEI64_V, 0x7, 0x0 }, // 9477
|
|
{ PseudoVSUXEI64_V_M2_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 9478
|
|
{ PseudoVSUXEI64_V_M4_MF2, VSUXEI64_V, 0x7, 0x0 }, // 9479
|
|
{ PseudoVSUXEI64_V_M4_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 9480
|
|
{ PseudoVSUXEI8_V_M1_M1, VSUXEI8_V, 0x0, 0x0 }, // 9481
|
|
{ PseudoVSUXEI8_V_M1_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9482
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|
{ PseudoVSUXEI8_V_MF2_M1, VSUXEI8_V, 0x0, 0x0 }, // 9483
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|
{ PseudoVSUXEI8_V_MF2_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9484
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|
{ PseudoVSUXEI8_V_MF4_M1, VSUXEI8_V, 0x0, 0x0 }, // 9485
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|
{ PseudoVSUXEI8_V_MF4_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9486
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|
{ PseudoVSUXEI8_V_MF8_M1, VSUXEI8_V, 0x0, 0x0 }, // 9487
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|
{ PseudoVSUXEI8_V_MF8_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9488
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|
{ PseudoVSUXEI8_V_M1_M2, VSUXEI8_V, 0x1, 0x0 }, // 9489
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|
{ PseudoVSUXEI8_V_M1_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9490
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|
{ PseudoVSUXEI8_V_M2_M2, VSUXEI8_V, 0x1, 0x0 }, // 9491
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|
{ PseudoVSUXEI8_V_M2_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9492
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|
{ PseudoVSUXEI8_V_MF2_M2, VSUXEI8_V, 0x1, 0x0 }, // 9493
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|
{ PseudoVSUXEI8_V_MF2_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9494
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|
{ PseudoVSUXEI8_V_MF4_M2, VSUXEI8_V, 0x1, 0x0 }, // 9495
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|
{ PseudoVSUXEI8_V_MF4_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9496
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|
{ PseudoVSUXEI8_V_M1_M4, VSUXEI8_V, 0x2, 0x0 }, // 9497
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|
{ PseudoVSUXEI8_V_M1_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9498
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|
{ PseudoVSUXEI8_V_M2_M4, VSUXEI8_V, 0x2, 0x0 }, // 9499
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|
{ PseudoVSUXEI8_V_M2_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9500
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|
{ PseudoVSUXEI8_V_M4_M4, VSUXEI8_V, 0x2, 0x0 }, // 9501
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|
{ PseudoVSUXEI8_V_M4_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9502
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|
{ PseudoVSUXEI8_V_MF2_M4, VSUXEI8_V, 0x2, 0x0 }, // 9503
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|
{ PseudoVSUXEI8_V_MF2_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9504
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|
{ PseudoVSUXEI8_V_M1_M8, VSUXEI8_V, 0x3, 0x0 }, // 9505
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|
{ PseudoVSUXEI8_V_M1_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9506
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|
{ PseudoVSUXEI8_V_M2_M8, VSUXEI8_V, 0x3, 0x0 }, // 9507
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|
{ PseudoVSUXEI8_V_M2_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9508
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|
{ PseudoVSUXEI8_V_M4_M8, VSUXEI8_V, 0x3, 0x0 }, // 9509
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|
{ PseudoVSUXEI8_V_M4_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9510
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|
{ PseudoVSUXEI8_V_M8_M8, VSUXEI8_V, 0x3, 0x0 }, // 9511
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|
{ PseudoVSUXEI8_V_M8_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9512
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|
{ PseudoVSUXEI8_V_MF8_MF8, VSUXEI8_V, 0x5, 0x0 }, // 9513
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|
{ PseudoVSUXEI8_V_MF8_MF8_MASK, VSUXEI8_V, 0x5, 0x0 }, // 9514
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|
{ PseudoVSUXEI8_V_MF4_MF4, VSUXEI8_V, 0x6, 0x0 }, // 9515
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|
{ PseudoVSUXEI8_V_MF4_MF4_MASK, VSUXEI8_V, 0x6, 0x0 }, // 9516
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|
{ PseudoVSUXEI8_V_MF8_MF4, VSUXEI8_V, 0x6, 0x0 }, // 9517
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|
{ PseudoVSUXEI8_V_MF8_MF4_MASK, VSUXEI8_V, 0x6, 0x0 }, // 9518
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|
{ PseudoVSUXEI8_V_MF2_MF2, VSUXEI8_V, 0x7, 0x0 }, // 9519
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|
{ PseudoVSUXEI8_V_MF2_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 9520
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|
{ PseudoVSUXEI8_V_MF4_MF2, VSUXEI8_V, 0x7, 0x0 }, // 9521
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|
{ PseudoVSUXEI8_V_MF4_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 9522
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|
{ PseudoVSUXEI8_V_MF8_MF2, VSUXEI8_V, 0x7, 0x0 }, // 9523
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|
{ PseudoVSUXEI8_V_MF8_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 9524
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|
{ PseudoVSUXSEG2EI16_V_M1_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9525
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|
{ PseudoVSUXSEG2EI16_V_M1_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9526
|
|
{ PseudoVSUXSEG2EI16_V_M2_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9527
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|
{ PseudoVSUXSEG2EI16_V_M2_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9528
|
|
{ PseudoVSUXSEG2EI16_V_MF2_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9529
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|
{ PseudoVSUXSEG2EI16_V_MF2_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9530
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|
{ PseudoVSUXSEG2EI16_V_MF4_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9531
|
|
{ PseudoVSUXSEG2EI16_V_MF4_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9532
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|
{ PseudoVSUXSEG2EI16_V_M1_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9533
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|
{ PseudoVSUXSEG2EI16_V_M1_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9534
|
|
{ PseudoVSUXSEG2EI16_V_M2_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9535
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|
{ PseudoVSUXSEG2EI16_V_M2_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9536
|
|
{ PseudoVSUXSEG2EI16_V_M4_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9537
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|
{ PseudoVSUXSEG2EI16_V_M4_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9538
|
|
{ PseudoVSUXSEG2EI16_V_MF2_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9539
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|
{ PseudoVSUXSEG2EI16_V_MF2_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9540
|
|
{ PseudoVSUXSEG2EI16_V_M1_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9541
|
|
{ PseudoVSUXSEG2EI16_V_M1_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9542
|
|
{ PseudoVSUXSEG2EI16_V_M2_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9543
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|
{ PseudoVSUXSEG2EI16_V_M2_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9544
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|
{ PseudoVSUXSEG2EI16_V_M4_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9545
|
|
{ PseudoVSUXSEG2EI16_V_M4_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9546
|
|
{ PseudoVSUXSEG2EI16_V_M8_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9547
|
|
{ PseudoVSUXSEG2EI16_V_M8_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9548
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF8, VSUXSEG2EI16_V, 0x5, 0x0 }, // 9549
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|
{ PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, VSUXSEG2EI16_V, 0x5, 0x0 }, // 9550
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|
{ PseudoVSUXSEG2EI16_V_MF2_MF4, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9551
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|
{ PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9552
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|
{ PseudoVSUXSEG2EI16_V_MF4_MF4, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9553
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|
{ PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9554
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|
{ PseudoVSUXSEG2EI16_V_M1_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9555
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|
{ PseudoVSUXSEG2EI16_V_M1_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9556
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|
{ PseudoVSUXSEG2EI16_V_MF2_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9557
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|
{ PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9558
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|
{ PseudoVSUXSEG2EI16_V_MF4_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9559
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|
{ PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9560
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|
{ PseudoVSUXSEG2EI32_V_M1_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9561
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|
{ PseudoVSUXSEG2EI32_V_M1_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9562
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|
{ PseudoVSUXSEG2EI32_V_M2_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9563
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|
{ PseudoVSUXSEG2EI32_V_M2_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9564
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|
{ PseudoVSUXSEG2EI32_V_M4_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9565
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|
{ PseudoVSUXSEG2EI32_V_M4_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9566
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|
{ PseudoVSUXSEG2EI32_V_MF2_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9567
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|
{ PseudoVSUXSEG2EI32_V_MF2_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9568
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|
{ PseudoVSUXSEG2EI32_V_M1_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9569
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|
{ PseudoVSUXSEG2EI32_V_M1_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9570
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|
{ PseudoVSUXSEG2EI32_V_M2_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9571
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|
{ PseudoVSUXSEG2EI32_V_M2_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9572
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|
{ PseudoVSUXSEG2EI32_V_M4_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9573
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|
{ PseudoVSUXSEG2EI32_V_M4_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9574
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|
{ PseudoVSUXSEG2EI32_V_M8_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9575
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|
{ PseudoVSUXSEG2EI32_V_M8_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9576
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|
{ PseudoVSUXSEG2EI32_V_M2_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9577
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|
{ PseudoVSUXSEG2EI32_V_M2_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9578
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|
{ PseudoVSUXSEG2EI32_V_M4_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9579
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|
{ PseudoVSUXSEG2EI32_V_M4_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9580
|
|
{ PseudoVSUXSEG2EI32_V_M8_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9581
|
|
{ PseudoVSUXSEG2EI32_V_M8_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9582
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF8, VSUXSEG2EI32_V, 0x5, 0x0 }, // 9583
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, VSUXSEG2EI32_V, 0x5, 0x0 }, // 9584
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|
{ PseudoVSUXSEG2EI32_V_M1_MF4, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9585
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|
{ PseudoVSUXSEG2EI32_V_M1_MF4_MASK, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9586
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF4, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9587
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|
{ PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9588
|
|
{ PseudoVSUXSEG2EI32_V_M1_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9589
|
|
{ PseudoVSUXSEG2EI32_V_M1_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9590
|
|
{ PseudoVSUXSEG2EI32_V_M2_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9591
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|
{ PseudoVSUXSEG2EI32_V_M2_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9592
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|
{ PseudoVSUXSEG2EI32_V_MF2_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9593
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|
{ PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9594
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|
{ PseudoVSUXSEG2EI64_V_M1_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9595
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|
{ PseudoVSUXSEG2EI64_V_M1_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9596
|
|
{ PseudoVSUXSEG2EI64_V_M2_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9597
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|
{ PseudoVSUXSEG2EI64_V_M2_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9598
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|
{ PseudoVSUXSEG2EI64_V_M4_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9599
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|
{ PseudoVSUXSEG2EI64_V_M4_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9600
|
|
{ PseudoVSUXSEG2EI64_V_M8_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9601
|
|
{ PseudoVSUXSEG2EI64_V_M8_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9602
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|
{ PseudoVSUXSEG2EI64_V_M2_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9603
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|
{ PseudoVSUXSEG2EI64_V_M2_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9604
|
|
{ PseudoVSUXSEG2EI64_V_M4_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9605
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|
{ PseudoVSUXSEG2EI64_V_M4_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9606
|
|
{ PseudoVSUXSEG2EI64_V_M8_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9607
|
|
{ PseudoVSUXSEG2EI64_V_M8_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9608
|
|
{ PseudoVSUXSEG2EI64_V_M4_M4, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9609
|
|
{ PseudoVSUXSEG2EI64_V_M4_M4_MASK, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9610
|
|
{ PseudoVSUXSEG2EI64_V_M8_M4, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9611
|
|
{ PseudoVSUXSEG2EI64_V_M8_M4_MASK, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9612
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF8, VSUXSEG2EI64_V, 0x5, 0x0 }, // 9613
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF8_MASK, VSUXSEG2EI64_V, 0x5, 0x0 }, // 9614
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF4, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9615
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF4_MASK, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9616
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF4, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9617
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF4_MASK, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9618
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9619
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9620
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9621
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9622
|
|
{ PseudoVSUXSEG2EI64_V_M4_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9623
|
|
{ PseudoVSUXSEG2EI64_V_M4_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9624
|
|
{ PseudoVSUXSEG2EI8_V_M1_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9625
|
|
{ PseudoVSUXSEG2EI8_V_M1_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9626
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9627
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9628
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9629
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9630
|
|
{ PseudoVSUXSEG2EI8_V_MF8_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9631
|
|
{ PseudoVSUXSEG2EI8_V_MF8_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9632
|
|
{ PseudoVSUXSEG2EI8_V_M1_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9633
|
|
{ PseudoVSUXSEG2EI8_V_M1_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9634
|
|
{ PseudoVSUXSEG2EI8_V_M2_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9635
|
|
{ PseudoVSUXSEG2EI8_V_M2_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9636
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9637
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9638
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9639
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9640
|
|
{ PseudoVSUXSEG2EI8_V_M1_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9641
|
|
{ PseudoVSUXSEG2EI8_V_M1_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9642
|
|
{ PseudoVSUXSEG2EI8_V_M2_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9643
|
|
{ PseudoVSUXSEG2EI8_V_M2_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9644
|
|
{ PseudoVSUXSEG2EI8_V_M4_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9645
|
|
{ PseudoVSUXSEG2EI8_V_M4_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9646
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9647
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9648
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF8, VSUXSEG2EI8_V, 0x5, 0x0 }, // 9649
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, VSUXSEG2EI8_V, 0x5, 0x0 }, // 9650
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF4, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9651
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9652
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF4, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9653
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9654
|
|
{ PseudoVSUXSEG2EI8_V_MF2_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9655
|
|
{ PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9656
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9657
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9658
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9659
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9660
|
|
{ PseudoVSUXSEG3EI16_V_M1_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9661
|
|
{ PseudoVSUXSEG3EI16_V_M1_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9662
|
|
{ PseudoVSUXSEG3EI16_V_M2_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9663
|
|
{ PseudoVSUXSEG3EI16_V_M2_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9664
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9665
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9666
|
|
{ PseudoVSUXSEG3EI16_V_MF4_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9667
|
|
{ PseudoVSUXSEG3EI16_V_MF4_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9668
|
|
{ PseudoVSUXSEG3EI16_V_M1_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9669
|
|
{ PseudoVSUXSEG3EI16_V_M1_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9670
|
|
{ PseudoVSUXSEG3EI16_V_M2_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9671
|
|
{ PseudoVSUXSEG3EI16_V_M2_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9672
|
|
{ PseudoVSUXSEG3EI16_V_M4_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9673
|
|
{ PseudoVSUXSEG3EI16_V_M4_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9674
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9675
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9676
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF8, VSUXSEG3EI16_V, 0x5, 0x0 }, // 9677
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, VSUXSEG3EI16_V, 0x5, 0x0 }, // 9678
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF4, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9679
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9680
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF4, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9681
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9682
|
|
{ PseudoVSUXSEG3EI16_V_M1_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9683
|
|
{ PseudoVSUXSEG3EI16_V_M1_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9684
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9685
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9686
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9687
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9688
|
|
{ PseudoVSUXSEG3EI32_V_M1_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9689
|
|
{ PseudoVSUXSEG3EI32_V_M1_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9690
|
|
{ PseudoVSUXSEG3EI32_V_M2_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9691
|
|
{ PseudoVSUXSEG3EI32_V_M2_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9692
|
|
{ PseudoVSUXSEG3EI32_V_M4_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9693
|
|
{ PseudoVSUXSEG3EI32_V_M4_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9694
|
|
{ PseudoVSUXSEG3EI32_V_MF2_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9695
|
|
{ PseudoVSUXSEG3EI32_V_MF2_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9696
|
|
{ PseudoVSUXSEG3EI32_V_M1_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9697
|
|
{ PseudoVSUXSEG3EI32_V_M1_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9698
|
|
{ PseudoVSUXSEG3EI32_V_M2_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9699
|
|
{ PseudoVSUXSEG3EI32_V_M2_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9700
|
|
{ PseudoVSUXSEG3EI32_V_M4_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9701
|
|
{ PseudoVSUXSEG3EI32_V_M4_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9702
|
|
{ PseudoVSUXSEG3EI32_V_M8_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9703
|
|
{ PseudoVSUXSEG3EI32_V_M8_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9704
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF8, VSUXSEG3EI32_V, 0x5, 0x0 }, // 9705
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, VSUXSEG3EI32_V, 0x5, 0x0 }, // 9706
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF4, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9707
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF4_MASK, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9708
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF4, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9709
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9710
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9711
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9712
|
|
{ PseudoVSUXSEG3EI32_V_M2_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9713
|
|
{ PseudoVSUXSEG3EI32_V_M2_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9714
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9715
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9716
|
|
{ PseudoVSUXSEG3EI64_V_M1_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9717
|
|
{ PseudoVSUXSEG3EI64_V_M1_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9718
|
|
{ PseudoVSUXSEG3EI64_V_M2_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9719
|
|
{ PseudoVSUXSEG3EI64_V_M2_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9720
|
|
{ PseudoVSUXSEG3EI64_V_M4_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9721
|
|
{ PseudoVSUXSEG3EI64_V_M4_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9722
|
|
{ PseudoVSUXSEG3EI64_V_M8_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9723
|
|
{ PseudoVSUXSEG3EI64_V_M8_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9724
|
|
{ PseudoVSUXSEG3EI64_V_M2_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9725
|
|
{ PseudoVSUXSEG3EI64_V_M2_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9726
|
|
{ PseudoVSUXSEG3EI64_V_M4_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9727
|
|
{ PseudoVSUXSEG3EI64_V_M4_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9728
|
|
{ PseudoVSUXSEG3EI64_V_M8_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9729
|
|
{ PseudoVSUXSEG3EI64_V_M8_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9730
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF8, VSUXSEG3EI64_V, 0x5, 0x0 }, // 9731
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF8_MASK, VSUXSEG3EI64_V, 0x5, 0x0 }, // 9732
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF4, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9733
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF4_MASK, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9734
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF4, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9735
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF4_MASK, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9736
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9737
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9738
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9739
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9740
|
|
{ PseudoVSUXSEG3EI64_V_M4_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9741
|
|
{ PseudoVSUXSEG3EI64_V_M4_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9742
|
|
{ PseudoVSUXSEG3EI8_V_M1_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9743
|
|
{ PseudoVSUXSEG3EI8_V_M1_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9744
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9745
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9746
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9747
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9748
|
|
{ PseudoVSUXSEG3EI8_V_MF8_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9749
|
|
{ PseudoVSUXSEG3EI8_V_MF8_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9750
|
|
{ PseudoVSUXSEG3EI8_V_M1_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9751
|
|
{ PseudoVSUXSEG3EI8_V_M1_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9752
|
|
{ PseudoVSUXSEG3EI8_V_M2_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9753
|
|
{ PseudoVSUXSEG3EI8_V_M2_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9754
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9755
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9756
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9757
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9758
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF8, VSUXSEG3EI8_V, 0x5, 0x0 }, // 9759
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, VSUXSEG3EI8_V, 0x5, 0x0 }, // 9760
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF4, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9761
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9762
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF4, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9763
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9764
|
|
{ PseudoVSUXSEG3EI8_V_MF2_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9765
|
|
{ PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9766
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9767
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9768
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9769
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9770
|
|
{ PseudoVSUXSEG4EI16_V_M1_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9771
|
|
{ PseudoVSUXSEG4EI16_V_M1_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9772
|
|
{ PseudoVSUXSEG4EI16_V_M2_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9773
|
|
{ PseudoVSUXSEG4EI16_V_M2_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9774
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9775
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9776
|
|
{ PseudoVSUXSEG4EI16_V_MF4_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9777
|
|
{ PseudoVSUXSEG4EI16_V_MF4_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9778
|
|
{ PseudoVSUXSEG4EI16_V_M1_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9779
|
|
{ PseudoVSUXSEG4EI16_V_M1_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9780
|
|
{ PseudoVSUXSEG4EI16_V_M2_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9781
|
|
{ PseudoVSUXSEG4EI16_V_M2_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9782
|
|
{ PseudoVSUXSEG4EI16_V_M4_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9783
|
|
{ PseudoVSUXSEG4EI16_V_M4_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9784
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9785
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9786
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF8, VSUXSEG4EI16_V, 0x5, 0x0 }, // 9787
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, VSUXSEG4EI16_V, 0x5, 0x0 }, // 9788
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF4, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9789
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9790
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF4, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9791
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9792
|
|
{ PseudoVSUXSEG4EI16_V_M1_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9793
|
|
{ PseudoVSUXSEG4EI16_V_M1_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9794
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9795
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9796
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9797
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9798
|
|
{ PseudoVSUXSEG4EI32_V_M1_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9799
|
|
{ PseudoVSUXSEG4EI32_V_M1_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9800
|
|
{ PseudoVSUXSEG4EI32_V_M2_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9801
|
|
{ PseudoVSUXSEG4EI32_V_M2_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9802
|
|
{ PseudoVSUXSEG4EI32_V_M4_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9803
|
|
{ PseudoVSUXSEG4EI32_V_M4_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9804
|
|
{ PseudoVSUXSEG4EI32_V_MF2_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9805
|
|
{ PseudoVSUXSEG4EI32_V_MF2_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9806
|
|
{ PseudoVSUXSEG4EI32_V_M1_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9807
|
|
{ PseudoVSUXSEG4EI32_V_M1_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9808
|
|
{ PseudoVSUXSEG4EI32_V_M2_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9809
|
|
{ PseudoVSUXSEG4EI32_V_M2_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9810
|
|
{ PseudoVSUXSEG4EI32_V_M4_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9811
|
|
{ PseudoVSUXSEG4EI32_V_M4_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9812
|
|
{ PseudoVSUXSEG4EI32_V_M8_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9813
|
|
{ PseudoVSUXSEG4EI32_V_M8_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9814
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF8, VSUXSEG4EI32_V, 0x5, 0x0 }, // 9815
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, VSUXSEG4EI32_V, 0x5, 0x0 }, // 9816
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF4, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9817
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF4_MASK, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9818
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF4, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9819
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9820
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9821
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9822
|
|
{ PseudoVSUXSEG4EI32_V_M2_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9823
|
|
{ PseudoVSUXSEG4EI32_V_M2_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9824
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9825
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9826
|
|
{ PseudoVSUXSEG4EI64_V_M1_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9827
|
|
{ PseudoVSUXSEG4EI64_V_M1_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9828
|
|
{ PseudoVSUXSEG4EI64_V_M2_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9829
|
|
{ PseudoVSUXSEG4EI64_V_M2_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9830
|
|
{ PseudoVSUXSEG4EI64_V_M4_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9831
|
|
{ PseudoVSUXSEG4EI64_V_M4_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9832
|
|
{ PseudoVSUXSEG4EI64_V_M8_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9833
|
|
{ PseudoVSUXSEG4EI64_V_M8_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9834
|
|
{ PseudoVSUXSEG4EI64_V_M2_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9835
|
|
{ PseudoVSUXSEG4EI64_V_M2_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9836
|
|
{ PseudoVSUXSEG4EI64_V_M4_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9837
|
|
{ PseudoVSUXSEG4EI64_V_M4_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9838
|
|
{ PseudoVSUXSEG4EI64_V_M8_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9839
|
|
{ PseudoVSUXSEG4EI64_V_M8_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9840
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF8, VSUXSEG4EI64_V, 0x5, 0x0 }, // 9841
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF8_MASK, VSUXSEG4EI64_V, 0x5, 0x0 }, // 9842
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF4, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9843
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF4_MASK, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9844
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF4, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9845
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF4_MASK, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9846
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9847
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9848
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9849
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9850
|
|
{ PseudoVSUXSEG4EI64_V_M4_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9851
|
|
{ PseudoVSUXSEG4EI64_V_M4_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9852
|
|
{ PseudoVSUXSEG4EI8_V_M1_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9853
|
|
{ PseudoVSUXSEG4EI8_V_M1_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9854
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9855
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9856
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9857
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9858
|
|
{ PseudoVSUXSEG4EI8_V_MF8_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9859
|
|
{ PseudoVSUXSEG4EI8_V_MF8_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9860
|
|
{ PseudoVSUXSEG4EI8_V_M1_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9861
|
|
{ PseudoVSUXSEG4EI8_V_M1_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9862
|
|
{ PseudoVSUXSEG4EI8_V_M2_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9863
|
|
{ PseudoVSUXSEG4EI8_V_M2_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9864
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9865
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9866
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9867
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9868
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF8, VSUXSEG4EI8_V, 0x5, 0x0 }, // 9869
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, VSUXSEG4EI8_V, 0x5, 0x0 }, // 9870
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF4, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9871
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9872
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF4, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9873
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9874
|
|
{ PseudoVSUXSEG4EI8_V_MF2_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9875
|
|
{ PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9876
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9877
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9878
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9879
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9880
|
|
{ PseudoVSUXSEG5EI16_V_M1_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9881
|
|
{ PseudoVSUXSEG5EI16_V_M1_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9882
|
|
{ PseudoVSUXSEG5EI16_V_M2_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9883
|
|
{ PseudoVSUXSEG5EI16_V_M2_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9884
|
|
{ PseudoVSUXSEG5EI16_V_MF2_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9885
|
|
{ PseudoVSUXSEG5EI16_V_MF2_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9886
|
|
{ PseudoVSUXSEG5EI16_V_MF4_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9887
|
|
{ PseudoVSUXSEG5EI16_V_MF4_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9888
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF8, VSUXSEG5EI16_V, 0x5, 0x0 }, // 9889
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, VSUXSEG5EI16_V, 0x5, 0x0 }, // 9890
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF4, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9891
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9892
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF4, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9893
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9894
|
|
{ PseudoVSUXSEG5EI16_V_M1_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9895
|
|
{ PseudoVSUXSEG5EI16_V_M1_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9896
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9897
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9898
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9899
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9900
|
|
{ PseudoVSUXSEG5EI32_V_M1_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9901
|
|
{ PseudoVSUXSEG5EI32_V_M1_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9902
|
|
{ PseudoVSUXSEG5EI32_V_M2_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9903
|
|
{ PseudoVSUXSEG5EI32_V_M2_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9904
|
|
{ PseudoVSUXSEG5EI32_V_M4_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9905
|
|
{ PseudoVSUXSEG5EI32_V_M4_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9906
|
|
{ PseudoVSUXSEG5EI32_V_MF2_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9907
|
|
{ PseudoVSUXSEG5EI32_V_MF2_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9908
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF8, VSUXSEG5EI32_V, 0x5, 0x0 }, // 9909
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, VSUXSEG5EI32_V, 0x5, 0x0 }, // 9910
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF4, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9911
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF4_MASK, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9912
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF4, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9913
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9914
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9915
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9916
|
|
{ PseudoVSUXSEG5EI32_V_M2_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9917
|
|
{ PseudoVSUXSEG5EI32_V_M2_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9918
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9919
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9920
|
|
{ PseudoVSUXSEG5EI64_V_M1_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9921
|
|
{ PseudoVSUXSEG5EI64_V_M1_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9922
|
|
{ PseudoVSUXSEG5EI64_V_M2_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9923
|
|
{ PseudoVSUXSEG5EI64_V_M2_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9924
|
|
{ PseudoVSUXSEG5EI64_V_M4_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9925
|
|
{ PseudoVSUXSEG5EI64_V_M4_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9926
|
|
{ PseudoVSUXSEG5EI64_V_M8_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9927
|
|
{ PseudoVSUXSEG5EI64_V_M8_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9928
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF8, VSUXSEG5EI64_V, 0x5, 0x0 }, // 9929
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF8_MASK, VSUXSEG5EI64_V, 0x5, 0x0 }, // 9930
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF4, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9931
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF4_MASK, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9932
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF4, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9933
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF4_MASK, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9934
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9935
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9936
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9937
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9938
|
|
{ PseudoVSUXSEG5EI64_V_M4_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9939
|
|
{ PseudoVSUXSEG5EI64_V_M4_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9940
|
|
{ PseudoVSUXSEG5EI8_V_M1_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9941
|
|
{ PseudoVSUXSEG5EI8_V_M1_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9942
|
|
{ PseudoVSUXSEG5EI8_V_MF2_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9943
|
|
{ PseudoVSUXSEG5EI8_V_MF2_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9944
|
|
{ PseudoVSUXSEG5EI8_V_MF4_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9945
|
|
{ PseudoVSUXSEG5EI8_V_MF4_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9946
|
|
{ PseudoVSUXSEG5EI8_V_MF8_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9947
|
|
{ PseudoVSUXSEG5EI8_V_MF8_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9948
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF8, VSUXSEG5EI8_V, 0x5, 0x0 }, // 9949
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, VSUXSEG5EI8_V, 0x5, 0x0 }, // 9950
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF4, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9951
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9952
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF4, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9953
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9954
|
|
{ PseudoVSUXSEG5EI8_V_MF2_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9955
|
|
{ PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9956
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9957
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9958
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9959
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9960
|
|
{ PseudoVSUXSEG6EI16_V_M1_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9961
|
|
{ PseudoVSUXSEG6EI16_V_M1_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9962
|
|
{ PseudoVSUXSEG6EI16_V_M2_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9963
|
|
{ PseudoVSUXSEG6EI16_V_M2_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9964
|
|
{ PseudoVSUXSEG6EI16_V_MF2_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9965
|
|
{ PseudoVSUXSEG6EI16_V_MF2_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9966
|
|
{ PseudoVSUXSEG6EI16_V_MF4_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9967
|
|
{ PseudoVSUXSEG6EI16_V_MF4_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9968
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF8, VSUXSEG6EI16_V, 0x5, 0x0 }, // 9969
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, VSUXSEG6EI16_V, 0x5, 0x0 }, // 9970
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF4, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9971
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9972
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF4, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9973
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9974
|
|
{ PseudoVSUXSEG6EI16_V_M1_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9975
|
|
{ PseudoVSUXSEG6EI16_V_M1_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9976
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9977
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9978
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9979
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9980
|
|
{ PseudoVSUXSEG6EI32_V_M1_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9981
|
|
{ PseudoVSUXSEG6EI32_V_M1_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9982
|
|
{ PseudoVSUXSEG6EI32_V_M2_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9983
|
|
{ PseudoVSUXSEG6EI32_V_M2_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9984
|
|
{ PseudoVSUXSEG6EI32_V_M4_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9985
|
|
{ PseudoVSUXSEG6EI32_V_M4_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9986
|
|
{ PseudoVSUXSEG6EI32_V_MF2_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9987
|
|
{ PseudoVSUXSEG6EI32_V_MF2_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9988
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF8, VSUXSEG6EI32_V, 0x5, 0x0 }, // 9989
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, VSUXSEG6EI32_V, 0x5, 0x0 }, // 9990
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF4, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9991
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF4_MASK, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9992
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF4, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9993
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9994
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9995
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9996
|
|
{ PseudoVSUXSEG6EI32_V_M2_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9997
|
|
{ PseudoVSUXSEG6EI32_V_M2_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9998
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9999
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10000
|
|
{ PseudoVSUXSEG6EI64_V_M1_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10001
|
|
{ PseudoVSUXSEG6EI64_V_M1_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10002
|
|
{ PseudoVSUXSEG6EI64_V_M2_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10003
|
|
{ PseudoVSUXSEG6EI64_V_M2_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10004
|
|
{ PseudoVSUXSEG6EI64_V_M4_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10005
|
|
{ PseudoVSUXSEG6EI64_V_M4_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10006
|
|
{ PseudoVSUXSEG6EI64_V_M8_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10007
|
|
{ PseudoVSUXSEG6EI64_V_M8_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10008
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF8, VSUXSEG6EI64_V, 0x5, 0x0 }, // 10009
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF8_MASK, VSUXSEG6EI64_V, 0x5, 0x0 }, // 10010
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF4, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10011
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF4_MASK, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10012
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF4, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10013
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF4_MASK, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10014
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10015
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10016
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10017
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10018
|
|
{ PseudoVSUXSEG6EI64_V_M4_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10019
|
|
{ PseudoVSUXSEG6EI64_V_M4_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10020
|
|
{ PseudoVSUXSEG6EI8_V_M1_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10021
|
|
{ PseudoVSUXSEG6EI8_V_M1_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10022
|
|
{ PseudoVSUXSEG6EI8_V_MF2_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10023
|
|
{ PseudoVSUXSEG6EI8_V_MF2_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10024
|
|
{ PseudoVSUXSEG6EI8_V_MF4_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10025
|
|
{ PseudoVSUXSEG6EI8_V_MF4_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10026
|
|
{ PseudoVSUXSEG6EI8_V_MF8_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10027
|
|
{ PseudoVSUXSEG6EI8_V_MF8_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10028
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF8, VSUXSEG6EI8_V, 0x5, 0x0 }, // 10029
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, VSUXSEG6EI8_V, 0x5, 0x0 }, // 10030
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF4, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10031
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10032
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF4, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10033
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10034
|
|
{ PseudoVSUXSEG6EI8_V_MF2_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10035
|
|
{ PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10036
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10037
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10038
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10039
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10040
|
|
{ PseudoVSUXSEG7EI16_V_M1_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10041
|
|
{ PseudoVSUXSEG7EI16_V_M1_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10042
|
|
{ PseudoVSUXSEG7EI16_V_M2_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10043
|
|
{ PseudoVSUXSEG7EI16_V_M2_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10044
|
|
{ PseudoVSUXSEG7EI16_V_MF2_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10045
|
|
{ PseudoVSUXSEG7EI16_V_MF2_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10046
|
|
{ PseudoVSUXSEG7EI16_V_MF4_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10047
|
|
{ PseudoVSUXSEG7EI16_V_MF4_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10048
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF8, VSUXSEG7EI16_V, 0x5, 0x0 }, // 10049
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, VSUXSEG7EI16_V, 0x5, 0x0 }, // 10050
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF4, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10051
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10052
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF4, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10053
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10054
|
|
{ PseudoVSUXSEG7EI16_V_M1_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10055
|
|
{ PseudoVSUXSEG7EI16_V_M1_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10056
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10057
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10058
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10059
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10060
|
|
{ PseudoVSUXSEG7EI32_V_M1_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10061
|
|
{ PseudoVSUXSEG7EI32_V_M1_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10062
|
|
{ PseudoVSUXSEG7EI32_V_M2_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10063
|
|
{ PseudoVSUXSEG7EI32_V_M2_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10064
|
|
{ PseudoVSUXSEG7EI32_V_M4_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10065
|
|
{ PseudoVSUXSEG7EI32_V_M4_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10066
|
|
{ PseudoVSUXSEG7EI32_V_MF2_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10067
|
|
{ PseudoVSUXSEG7EI32_V_MF2_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10068
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF8, VSUXSEG7EI32_V, 0x5, 0x0 }, // 10069
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, VSUXSEG7EI32_V, 0x5, 0x0 }, // 10070
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF4, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10071
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF4_MASK, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10072
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF4, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10073
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10074
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10075
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10076
|
|
{ PseudoVSUXSEG7EI32_V_M2_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10077
|
|
{ PseudoVSUXSEG7EI32_V_M2_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10078
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10079
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10080
|
|
{ PseudoVSUXSEG7EI64_V_M1_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10081
|
|
{ PseudoVSUXSEG7EI64_V_M1_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10082
|
|
{ PseudoVSUXSEG7EI64_V_M2_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10083
|
|
{ PseudoVSUXSEG7EI64_V_M2_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10084
|
|
{ PseudoVSUXSEG7EI64_V_M4_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10085
|
|
{ PseudoVSUXSEG7EI64_V_M4_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10086
|
|
{ PseudoVSUXSEG7EI64_V_M8_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10087
|
|
{ PseudoVSUXSEG7EI64_V_M8_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10088
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF8, VSUXSEG7EI64_V, 0x5, 0x0 }, // 10089
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF8_MASK, VSUXSEG7EI64_V, 0x5, 0x0 }, // 10090
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF4, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10091
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF4_MASK, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10092
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF4, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10093
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF4_MASK, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10094
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10095
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10096
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10097
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10098
|
|
{ PseudoVSUXSEG7EI64_V_M4_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10099
|
|
{ PseudoVSUXSEG7EI64_V_M4_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10100
|
|
{ PseudoVSUXSEG7EI8_V_M1_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10101
|
|
{ PseudoVSUXSEG7EI8_V_M1_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10102
|
|
{ PseudoVSUXSEG7EI8_V_MF2_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10103
|
|
{ PseudoVSUXSEG7EI8_V_MF2_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10104
|
|
{ PseudoVSUXSEG7EI8_V_MF4_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10105
|
|
{ PseudoVSUXSEG7EI8_V_MF4_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10106
|
|
{ PseudoVSUXSEG7EI8_V_MF8_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10107
|
|
{ PseudoVSUXSEG7EI8_V_MF8_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10108
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF8, VSUXSEG7EI8_V, 0x5, 0x0 }, // 10109
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, VSUXSEG7EI8_V, 0x5, 0x0 }, // 10110
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF4, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10111
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10112
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF4, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10113
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10114
|
|
{ PseudoVSUXSEG7EI8_V_MF2_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10115
|
|
{ PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10116
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10117
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10118
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10119
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10120
|
|
{ PseudoVSUXSEG8EI16_V_M1_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10121
|
|
{ PseudoVSUXSEG8EI16_V_M1_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10122
|
|
{ PseudoVSUXSEG8EI16_V_M2_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10123
|
|
{ PseudoVSUXSEG8EI16_V_M2_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10124
|
|
{ PseudoVSUXSEG8EI16_V_MF2_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10125
|
|
{ PseudoVSUXSEG8EI16_V_MF2_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10126
|
|
{ PseudoVSUXSEG8EI16_V_MF4_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10127
|
|
{ PseudoVSUXSEG8EI16_V_MF4_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10128
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF8, VSUXSEG8EI16_V, 0x5, 0x0 }, // 10129
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, VSUXSEG8EI16_V, 0x5, 0x0 }, // 10130
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF4, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10131
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10132
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF4, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10133
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10134
|
|
{ PseudoVSUXSEG8EI16_V_M1_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10135
|
|
{ PseudoVSUXSEG8EI16_V_M1_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10136
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10137
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10138
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10139
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10140
|
|
{ PseudoVSUXSEG8EI32_V_M1_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10141
|
|
{ PseudoVSUXSEG8EI32_V_M1_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10142
|
|
{ PseudoVSUXSEG8EI32_V_M2_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10143
|
|
{ PseudoVSUXSEG8EI32_V_M2_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10144
|
|
{ PseudoVSUXSEG8EI32_V_M4_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10145
|
|
{ PseudoVSUXSEG8EI32_V_M4_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10146
|
|
{ PseudoVSUXSEG8EI32_V_MF2_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10147
|
|
{ PseudoVSUXSEG8EI32_V_MF2_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10148
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF8, VSUXSEG8EI32_V, 0x5, 0x0 }, // 10149
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, VSUXSEG8EI32_V, 0x5, 0x0 }, // 10150
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF4, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10151
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF4_MASK, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10152
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF4, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10153
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10154
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10155
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10156
|
|
{ PseudoVSUXSEG8EI32_V_M2_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10157
|
|
{ PseudoVSUXSEG8EI32_V_M2_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10158
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10159
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10160
|
|
{ PseudoVSUXSEG8EI64_V_M1_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10161
|
|
{ PseudoVSUXSEG8EI64_V_M1_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10162
|
|
{ PseudoVSUXSEG8EI64_V_M2_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10163
|
|
{ PseudoVSUXSEG8EI64_V_M2_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10164
|
|
{ PseudoVSUXSEG8EI64_V_M4_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10165
|
|
{ PseudoVSUXSEG8EI64_V_M4_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10166
|
|
{ PseudoVSUXSEG8EI64_V_M8_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10167
|
|
{ PseudoVSUXSEG8EI64_V_M8_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10168
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF8, VSUXSEG8EI64_V, 0x5, 0x0 }, // 10169
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF8_MASK, VSUXSEG8EI64_V, 0x5, 0x0 }, // 10170
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF4, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10171
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF4_MASK, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10172
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF4, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10173
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF4_MASK, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10174
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10175
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10176
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10177
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10178
|
|
{ PseudoVSUXSEG8EI64_V_M4_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10179
|
|
{ PseudoVSUXSEG8EI64_V_M4_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10180
|
|
{ PseudoVSUXSEG8EI8_V_M1_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10181
|
|
{ PseudoVSUXSEG8EI8_V_M1_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10182
|
|
{ PseudoVSUXSEG8EI8_V_MF2_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10183
|
|
{ PseudoVSUXSEG8EI8_V_MF2_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10184
|
|
{ PseudoVSUXSEG8EI8_V_MF4_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10185
|
|
{ PseudoVSUXSEG8EI8_V_MF4_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10186
|
|
{ PseudoVSUXSEG8EI8_V_MF8_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10187
|
|
{ PseudoVSUXSEG8EI8_V_MF8_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10188
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF8, VSUXSEG8EI8_V, 0x5, 0x0 }, // 10189
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, VSUXSEG8EI8_V, 0x5, 0x0 }, // 10190
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF4, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10191
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10192
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF4, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10193
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10194
|
|
{ PseudoVSUXSEG8EI8_V_MF2_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10195
|
|
{ PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10196
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10197
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10198
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10199
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10200
|
|
{ PseudoVWADDU_VV_M1, VWADDU_VV, 0x0, 0x0 }, // 10201
|
|
{ PseudoVWADDU_VV_M1_MASK, VWADDU_VV, 0x0, 0x0 }, // 10202
|
|
{ PseudoVWADDU_VV_M2, VWADDU_VV, 0x1, 0x0 }, // 10203
|
|
{ PseudoVWADDU_VV_M2_MASK, VWADDU_VV, 0x1, 0x0 }, // 10204
|
|
{ PseudoVWADDU_VV_M4, VWADDU_VV, 0x2, 0x0 }, // 10205
|
|
{ PseudoVWADDU_VV_M4_MASK, VWADDU_VV, 0x2, 0x0 }, // 10206
|
|
{ PseudoVWADDU_VV_MF8, VWADDU_VV, 0x5, 0x0 }, // 10207
|
|
{ PseudoVWADDU_VV_MF8_MASK, VWADDU_VV, 0x5, 0x0 }, // 10208
|
|
{ PseudoVWADDU_VV_MF4, VWADDU_VV, 0x6, 0x0 }, // 10209
|
|
{ PseudoVWADDU_VV_MF4_MASK, VWADDU_VV, 0x6, 0x0 }, // 10210
|
|
{ PseudoVWADDU_VV_MF2, VWADDU_VV, 0x7, 0x0 }, // 10211
|
|
{ PseudoVWADDU_VV_MF2_MASK, VWADDU_VV, 0x7, 0x0 }, // 10212
|
|
{ PseudoVWADDU_VX_M1, VWADDU_VX, 0x0, 0x0 }, // 10213
|
|
{ PseudoVWADDU_VX_M1_MASK, VWADDU_VX, 0x0, 0x0 }, // 10214
|
|
{ PseudoVWADDU_VX_M2, VWADDU_VX, 0x1, 0x0 }, // 10215
|
|
{ PseudoVWADDU_VX_M2_MASK, VWADDU_VX, 0x1, 0x0 }, // 10216
|
|
{ PseudoVWADDU_VX_M4, VWADDU_VX, 0x2, 0x0 }, // 10217
|
|
{ PseudoVWADDU_VX_M4_MASK, VWADDU_VX, 0x2, 0x0 }, // 10218
|
|
{ PseudoVWADDU_VX_MF8, VWADDU_VX, 0x5, 0x0 }, // 10219
|
|
{ PseudoVWADDU_VX_MF8_MASK, VWADDU_VX, 0x5, 0x0 }, // 10220
|
|
{ PseudoVWADDU_VX_MF4, VWADDU_VX, 0x6, 0x0 }, // 10221
|
|
{ PseudoVWADDU_VX_MF4_MASK, VWADDU_VX, 0x6, 0x0 }, // 10222
|
|
{ PseudoVWADDU_VX_MF2, VWADDU_VX, 0x7, 0x0 }, // 10223
|
|
{ PseudoVWADDU_VX_MF2_MASK, VWADDU_VX, 0x7, 0x0 }, // 10224
|
|
{ PseudoVWADDU_WV_M1, VWADDU_WV, 0x0, 0x0 }, // 10225
|
|
{ PseudoVWADDU_WV_M1_MASK, VWADDU_WV, 0x0, 0x0 }, // 10226
|
|
{ PseudoVWADDU_WV_M1_MASK_TIED, VWADDU_WV, 0x0, 0x0 }, // 10227
|
|
{ PseudoVWADDU_WV_M1_TIED, VWADDU_WV, 0x0, 0x0 }, // 10228
|
|
{ PseudoVWADDU_WV_M2, VWADDU_WV, 0x1, 0x0 }, // 10229
|
|
{ PseudoVWADDU_WV_M2_MASK, VWADDU_WV, 0x1, 0x0 }, // 10230
|
|
{ PseudoVWADDU_WV_M2_MASK_TIED, VWADDU_WV, 0x1, 0x0 }, // 10231
|
|
{ PseudoVWADDU_WV_M2_TIED, VWADDU_WV, 0x1, 0x0 }, // 10232
|
|
{ PseudoVWADDU_WV_M4, VWADDU_WV, 0x2, 0x0 }, // 10233
|
|
{ PseudoVWADDU_WV_M4_MASK, VWADDU_WV, 0x2, 0x0 }, // 10234
|
|
{ PseudoVWADDU_WV_M4_MASK_TIED, VWADDU_WV, 0x2, 0x0 }, // 10235
|
|
{ PseudoVWADDU_WV_M4_TIED, VWADDU_WV, 0x2, 0x0 }, // 10236
|
|
{ PseudoVWADDU_WV_MF8, VWADDU_WV, 0x5, 0x0 }, // 10237
|
|
{ PseudoVWADDU_WV_MF8_MASK, VWADDU_WV, 0x5, 0x0 }, // 10238
|
|
{ PseudoVWADDU_WV_MF8_MASK_TIED, VWADDU_WV, 0x5, 0x0 }, // 10239
|
|
{ PseudoVWADDU_WV_MF8_TIED, VWADDU_WV, 0x5, 0x0 }, // 10240
|
|
{ PseudoVWADDU_WV_MF4, VWADDU_WV, 0x6, 0x0 }, // 10241
|
|
{ PseudoVWADDU_WV_MF4_MASK, VWADDU_WV, 0x6, 0x0 }, // 10242
|
|
{ PseudoVWADDU_WV_MF4_MASK_TIED, VWADDU_WV, 0x6, 0x0 }, // 10243
|
|
{ PseudoVWADDU_WV_MF4_TIED, VWADDU_WV, 0x6, 0x0 }, // 10244
|
|
{ PseudoVWADDU_WV_MF2, VWADDU_WV, 0x7, 0x0 }, // 10245
|
|
{ PseudoVWADDU_WV_MF2_MASK, VWADDU_WV, 0x7, 0x0 }, // 10246
|
|
{ PseudoVWADDU_WV_MF2_MASK_TIED, VWADDU_WV, 0x7, 0x0 }, // 10247
|
|
{ PseudoVWADDU_WV_MF2_TIED, VWADDU_WV, 0x7, 0x0 }, // 10248
|
|
{ PseudoVWADDU_WX_M1, VWADDU_WX, 0x0, 0x0 }, // 10249
|
|
{ PseudoVWADDU_WX_M1_MASK, VWADDU_WX, 0x0, 0x0 }, // 10250
|
|
{ PseudoVWADDU_WX_M2, VWADDU_WX, 0x1, 0x0 }, // 10251
|
|
{ PseudoVWADDU_WX_M2_MASK, VWADDU_WX, 0x1, 0x0 }, // 10252
|
|
{ PseudoVWADDU_WX_M4, VWADDU_WX, 0x2, 0x0 }, // 10253
|
|
{ PseudoVWADDU_WX_M4_MASK, VWADDU_WX, 0x2, 0x0 }, // 10254
|
|
{ PseudoVWADDU_WX_MF8, VWADDU_WX, 0x5, 0x0 }, // 10255
|
|
{ PseudoVWADDU_WX_MF8_MASK, VWADDU_WX, 0x5, 0x0 }, // 10256
|
|
{ PseudoVWADDU_WX_MF4, VWADDU_WX, 0x6, 0x0 }, // 10257
|
|
{ PseudoVWADDU_WX_MF4_MASK, VWADDU_WX, 0x6, 0x0 }, // 10258
|
|
{ PseudoVWADDU_WX_MF2, VWADDU_WX, 0x7, 0x0 }, // 10259
|
|
{ PseudoVWADDU_WX_MF2_MASK, VWADDU_WX, 0x7, 0x0 }, // 10260
|
|
{ PseudoVWADD_VV_M1, VWADD_VV, 0x0, 0x0 }, // 10261
|
|
{ PseudoVWADD_VV_M1_MASK, VWADD_VV, 0x0, 0x0 }, // 10262
|
|
{ PseudoVWADD_VV_M2, VWADD_VV, 0x1, 0x0 }, // 10263
|
|
{ PseudoVWADD_VV_M2_MASK, VWADD_VV, 0x1, 0x0 }, // 10264
|
|
{ PseudoVWADD_VV_M4, VWADD_VV, 0x2, 0x0 }, // 10265
|
|
{ PseudoVWADD_VV_M4_MASK, VWADD_VV, 0x2, 0x0 }, // 10266
|
|
{ PseudoVWADD_VV_MF8, VWADD_VV, 0x5, 0x0 }, // 10267
|
|
{ PseudoVWADD_VV_MF8_MASK, VWADD_VV, 0x5, 0x0 }, // 10268
|
|
{ PseudoVWADD_VV_MF4, VWADD_VV, 0x6, 0x0 }, // 10269
|
|
{ PseudoVWADD_VV_MF4_MASK, VWADD_VV, 0x6, 0x0 }, // 10270
|
|
{ PseudoVWADD_VV_MF2, VWADD_VV, 0x7, 0x0 }, // 10271
|
|
{ PseudoVWADD_VV_MF2_MASK, VWADD_VV, 0x7, 0x0 }, // 10272
|
|
{ PseudoVWADD_VX_M1, VWADD_VX, 0x0, 0x0 }, // 10273
|
|
{ PseudoVWADD_VX_M1_MASK, VWADD_VX, 0x0, 0x0 }, // 10274
|
|
{ PseudoVWADD_VX_M2, VWADD_VX, 0x1, 0x0 }, // 10275
|
|
{ PseudoVWADD_VX_M2_MASK, VWADD_VX, 0x1, 0x0 }, // 10276
|
|
{ PseudoVWADD_VX_M4, VWADD_VX, 0x2, 0x0 }, // 10277
|
|
{ PseudoVWADD_VX_M4_MASK, VWADD_VX, 0x2, 0x0 }, // 10278
|
|
{ PseudoVWADD_VX_MF8, VWADD_VX, 0x5, 0x0 }, // 10279
|
|
{ PseudoVWADD_VX_MF8_MASK, VWADD_VX, 0x5, 0x0 }, // 10280
|
|
{ PseudoVWADD_VX_MF4, VWADD_VX, 0x6, 0x0 }, // 10281
|
|
{ PseudoVWADD_VX_MF4_MASK, VWADD_VX, 0x6, 0x0 }, // 10282
|
|
{ PseudoVWADD_VX_MF2, VWADD_VX, 0x7, 0x0 }, // 10283
|
|
{ PseudoVWADD_VX_MF2_MASK, VWADD_VX, 0x7, 0x0 }, // 10284
|
|
{ PseudoVWADD_WV_M1, VWADD_WV, 0x0, 0x0 }, // 10285
|
|
{ PseudoVWADD_WV_M1_MASK, VWADD_WV, 0x0, 0x0 }, // 10286
|
|
{ PseudoVWADD_WV_M1_MASK_TIED, VWADD_WV, 0x0, 0x0 }, // 10287
|
|
{ PseudoVWADD_WV_M1_TIED, VWADD_WV, 0x0, 0x0 }, // 10288
|
|
{ PseudoVWADD_WV_M2, VWADD_WV, 0x1, 0x0 }, // 10289
|
|
{ PseudoVWADD_WV_M2_MASK, VWADD_WV, 0x1, 0x0 }, // 10290
|
|
{ PseudoVWADD_WV_M2_MASK_TIED, VWADD_WV, 0x1, 0x0 }, // 10291
|
|
{ PseudoVWADD_WV_M2_TIED, VWADD_WV, 0x1, 0x0 }, // 10292
|
|
{ PseudoVWADD_WV_M4, VWADD_WV, 0x2, 0x0 }, // 10293
|
|
{ PseudoVWADD_WV_M4_MASK, VWADD_WV, 0x2, 0x0 }, // 10294
|
|
{ PseudoVWADD_WV_M4_MASK_TIED, VWADD_WV, 0x2, 0x0 }, // 10295
|
|
{ PseudoVWADD_WV_M4_TIED, VWADD_WV, 0x2, 0x0 }, // 10296
|
|
{ PseudoVWADD_WV_MF8, VWADD_WV, 0x5, 0x0 }, // 10297
|
|
{ PseudoVWADD_WV_MF8_MASK, VWADD_WV, 0x5, 0x0 }, // 10298
|
|
{ PseudoVWADD_WV_MF8_MASK_TIED, VWADD_WV, 0x5, 0x0 }, // 10299
|
|
{ PseudoVWADD_WV_MF8_TIED, VWADD_WV, 0x5, 0x0 }, // 10300
|
|
{ PseudoVWADD_WV_MF4, VWADD_WV, 0x6, 0x0 }, // 10301
|
|
{ PseudoVWADD_WV_MF4_MASK, VWADD_WV, 0x6, 0x0 }, // 10302
|
|
{ PseudoVWADD_WV_MF4_MASK_TIED, VWADD_WV, 0x6, 0x0 }, // 10303
|
|
{ PseudoVWADD_WV_MF4_TIED, VWADD_WV, 0x6, 0x0 }, // 10304
|
|
{ PseudoVWADD_WV_MF2, VWADD_WV, 0x7, 0x0 }, // 10305
|
|
{ PseudoVWADD_WV_MF2_MASK, VWADD_WV, 0x7, 0x0 }, // 10306
|
|
{ PseudoVWADD_WV_MF2_MASK_TIED, VWADD_WV, 0x7, 0x0 }, // 10307
|
|
{ PseudoVWADD_WV_MF2_TIED, VWADD_WV, 0x7, 0x0 }, // 10308
|
|
{ PseudoVWADD_WX_M1, VWADD_WX, 0x0, 0x0 }, // 10309
|
|
{ PseudoVWADD_WX_M1_MASK, VWADD_WX, 0x0, 0x0 }, // 10310
|
|
{ PseudoVWADD_WX_M2, VWADD_WX, 0x1, 0x0 }, // 10311
|
|
{ PseudoVWADD_WX_M2_MASK, VWADD_WX, 0x1, 0x0 }, // 10312
|
|
{ PseudoVWADD_WX_M4, VWADD_WX, 0x2, 0x0 }, // 10313
|
|
{ PseudoVWADD_WX_M4_MASK, VWADD_WX, 0x2, 0x0 }, // 10314
|
|
{ PseudoVWADD_WX_MF8, VWADD_WX, 0x5, 0x0 }, // 10315
|
|
{ PseudoVWADD_WX_MF8_MASK, VWADD_WX, 0x5, 0x0 }, // 10316
|
|
{ PseudoVWADD_WX_MF4, VWADD_WX, 0x6, 0x0 }, // 10317
|
|
{ PseudoVWADD_WX_MF4_MASK, VWADD_WX, 0x6, 0x0 }, // 10318
|
|
{ PseudoVWADD_WX_MF2, VWADD_WX, 0x7, 0x0 }, // 10319
|
|
{ PseudoVWADD_WX_MF2_MASK, VWADD_WX, 0x7, 0x0 }, // 10320
|
|
{ PseudoVWMACCSU_VV_M1, VWMACCSU_VV, 0x0, 0x0 }, // 10321
|
|
{ PseudoVWMACCSU_VV_M1_MASK, VWMACCSU_VV, 0x0, 0x0 }, // 10322
|
|
{ PseudoVWMACCSU_VV_M2, VWMACCSU_VV, 0x1, 0x0 }, // 10323
|
|
{ PseudoVWMACCSU_VV_M2_MASK, VWMACCSU_VV, 0x1, 0x0 }, // 10324
|
|
{ PseudoVWMACCSU_VV_M4, VWMACCSU_VV, 0x2, 0x0 }, // 10325
|
|
{ PseudoVWMACCSU_VV_M4_MASK, VWMACCSU_VV, 0x2, 0x0 }, // 10326
|
|
{ PseudoVWMACCSU_VV_MF8, VWMACCSU_VV, 0x5, 0x0 }, // 10327
|
|
{ PseudoVWMACCSU_VV_MF8_MASK, VWMACCSU_VV, 0x5, 0x0 }, // 10328
|
|
{ PseudoVWMACCSU_VV_MF4, VWMACCSU_VV, 0x6, 0x0 }, // 10329
|
|
{ PseudoVWMACCSU_VV_MF4_MASK, VWMACCSU_VV, 0x6, 0x0 }, // 10330
|
|
{ PseudoVWMACCSU_VV_MF2, VWMACCSU_VV, 0x7, 0x0 }, // 10331
|
|
{ PseudoVWMACCSU_VV_MF2_MASK, VWMACCSU_VV, 0x7, 0x0 }, // 10332
|
|
{ PseudoVWMACCSU_VX_M1, VWMACCSU_VX, 0x0, 0x0 }, // 10333
|
|
{ PseudoVWMACCSU_VX_M1_MASK, VWMACCSU_VX, 0x0, 0x0 }, // 10334
|
|
{ PseudoVWMACCSU_VX_M2, VWMACCSU_VX, 0x1, 0x0 }, // 10335
|
|
{ PseudoVWMACCSU_VX_M2_MASK, VWMACCSU_VX, 0x1, 0x0 }, // 10336
|
|
{ PseudoVWMACCSU_VX_M4, VWMACCSU_VX, 0x2, 0x0 }, // 10337
|
|
{ PseudoVWMACCSU_VX_M4_MASK, VWMACCSU_VX, 0x2, 0x0 }, // 10338
|
|
{ PseudoVWMACCSU_VX_MF8, VWMACCSU_VX, 0x5, 0x0 }, // 10339
|
|
{ PseudoVWMACCSU_VX_MF8_MASK, VWMACCSU_VX, 0x5, 0x0 }, // 10340
|
|
{ PseudoVWMACCSU_VX_MF4, VWMACCSU_VX, 0x6, 0x0 }, // 10341
|
|
{ PseudoVWMACCSU_VX_MF4_MASK, VWMACCSU_VX, 0x6, 0x0 }, // 10342
|
|
{ PseudoVWMACCSU_VX_MF2, VWMACCSU_VX, 0x7, 0x0 }, // 10343
|
|
{ PseudoVWMACCSU_VX_MF2_MASK, VWMACCSU_VX, 0x7, 0x0 }, // 10344
|
|
{ PseudoVWMACCUS_VX_M1, VWMACCUS_VX, 0x0, 0x0 }, // 10345
|
|
{ PseudoVWMACCUS_VX_M1_MASK, VWMACCUS_VX, 0x0, 0x0 }, // 10346
|
|
{ PseudoVWMACCUS_VX_M2, VWMACCUS_VX, 0x1, 0x0 }, // 10347
|
|
{ PseudoVWMACCUS_VX_M2_MASK, VWMACCUS_VX, 0x1, 0x0 }, // 10348
|
|
{ PseudoVWMACCUS_VX_M4, VWMACCUS_VX, 0x2, 0x0 }, // 10349
|
|
{ PseudoVWMACCUS_VX_M4_MASK, VWMACCUS_VX, 0x2, 0x0 }, // 10350
|
|
{ PseudoVWMACCUS_VX_MF8, VWMACCUS_VX, 0x5, 0x0 }, // 10351
|
|
{ PseudoVWMACCUS_VX_MF8_MASK, VWMACCUS_VX, 0x5, 0x0 }, // 10352
|
|
{ PseudoVWMACCUS_VX_MF4, VWMACCUS_VX, 0x6, 0x0 }, // 10353
|
|
{ PseudoVWMACCUS_VX_MF4_MASK, VWMACCUS_VX, 0x6, 0x0 }, // 10354
|
|
{ PseudoVWMACCUS_VX_MF2, VWMACCUS_VX, 0x7, 0x0 }, // 10355
|
|
{ PseudoVWMACCUS_VX_MF2_MASK, VWMACCUS_VX, 0x7, 0x0 }, // 10356
|
|
{ PseudoVWMACCU_VV_M1, VWMACCU_VV, 0x0, 0x0 }, // 10357
|
|
{ PseudoVWMACCU_VV_M1_MASK, VWMACCU_VV, 0x0, 0x0 }, // 10358
|
|
{ PseudoVWMACCU_VV_M2, VWMACCU_VV, 0x1, 0x0 }, // 10359
|
|
{ PseudoVWMACCU_VV_M2_MASK, VWMACCU_VV, 0x1, 0x0 }, // 10360
|
|
{ PseudoVWMACCU_VV_M4, VWMACCU_VV, 0x2, 0x0 }, // 10361
|
|
{ PseudoVWMACCU_VV_M4_MASK, VWMACCU_VV, 0x2, 0x0 }, // 10362
|
|
{ PseudoVWMACCU_VV_MF8, VWMACCU_VV, 0x5, 0x0 }, // 10363
|
|
{ PseudoVWMACCU_VV_MF8_MASK, VWMACCU_VV, 0x5, 0x0 }, // 10364
|
|
{ PseudoVWMACCU_VV_MF4, VWMACCU_VV, 0x6, 0x0 }, // 10365
|
|
{ PseudoVWMACCU_VV_MF4_MASK, VWMACCU_VV, 0x6, 0x0 }, // 10366
|
|
{ PseudoVWMACCU_VV_MF2, VWMACCU_VV, 0x7, 0x0 }, // 10367
|
|
{ PseudoVWMACCU_VV_MF2_MASK, VWMACCU_VV, 0x7, 0x0 }, // 10368
|
|
{ PseudoVWMACCU_VX_M1, VWMACCU_VX, 0x0, 0x0 }, // 10369
|
|
{ PseudoVWMACCU_VX_M1_MASK, VWMACCU_VX, 0x0, 0x0 }, // 10370
|
|
{ PseudoVWMACCU_VX_M2, VWMACCU_VX, 0x1, 0x0 }, // 10371
|
|
{ PseudoVWMACCU_VX_M2_MASK, VWMACCU_VX, 0x1, 0x0 }, // 10372
|
|
{ PseudoVWMACCU_VX_M4, VWMACCU_VX, 0x2, 0x0 }, // 10373
|
|
{ PseudoVWMACCU_VX_M4_MASK, VWMACCU_VX, 0x2, 0x0 }, // 10374
|
|
{ PseudoVWMACCU_VX_MF8, VWMACCU_VX, 0x5, 0x0 }, // 10375
|
|
{ PseudoVWMACCU_VX_MF8_MASK, VWMACCU_VX, 0x5, 0x0 }, // 10376
|
|
{ PseudoVWMACCU_VX_MF4, VWMACCU_VX, 0x6, 0x0 }, // 10377
|
|
{ PseudoVWMACCU_VX_MF4_MASK, VWMACCU_VX, 0x6, 0x0 }, // 10378
|
|
{ PseudoVWMACCU_VX_MF2, VWMACCU_VX, 0x7, 0x0 }, // 10379
|
|
{ PseudoVWMACCU_VX_MF2_MASK, VWMACCU_VX, 0x7, 0x0 }, // 10380
|
|
{ PseudoVWMACC_VV_M1, VWMACC_VV, 0x0, 0x0 }, // 10381
|
|
{ PseudoVWMACC_VV_M1_MASK, VWMACC_VV, 0x0, 0x0 }, // 10382
|
|
{ PseudoVWMACC_VV_M2, VWMACC_VV, 0x1, 0x0 }, // 10383
|
|
{ PseudoVWMACC_VV_M2_MASK, VWMACC_VV, 0x1, 0x0 }, // 10384
|
|
{ PseudoVWMACC_VV_M4, VWMACC_VV, 0x2, 0x0 }, // 10385
|
|
{ PseudoVWMACC_VV_M4_MASK, VWMACC_VV, 0x2, 0x0 }, // 10386
|
|
{ PseudoVWMACC_VV_MF8, VWMACC_VV, 0x5, 0x0 }, // 10387
|
|
{ PseudoVWMACC_VV_MF8_MASK, VWMACC_VV, 0x5, 0x0 }, // 10388
|
|
{ PseudoVWMACC_VV_MF4, VWMACC_VV, 0x6, 0x0 }, // 10389
|
|
{ PseudoVWMACC_VV_MF4_MASK, VWMACC_VV, 0x6, 0x0 }, // 10390
|
|
{ PseudoVWMACC_VV_MF2, VWMACC_VV, 0x7, 0x0 }, // 10391
|
|
{ PseudoVWMACC_VV_MF2_MASK, VWMACC_VV, 0x7, 0x0 }, // 10392
|
|
{ PseudoVWMACC_VX_M1, VWMACC_VX, 0x0, 0x0 }, // 10393
|
|
{ PseudoVWMACC_VX_M1_MASK, VWMACC_VX, 0x0, 0x0 }, // 10394
|
|
{ PseudoVWMACC_VX_M2, VWMACC_VX, 0x1, 0x0 }, // 10395
|
|
{ PseudoVWMACC_VX_M2_MASK, VWMACC_VX, 0x1, 0x0 }, // 10396
|
|
{ PseudoVWMACC_VX_M4, VWMACC_VX, 0x2, 0x0 }, // 10397
|
|
{ PseudoVWMACC_VX_M4_MASK, VWMACC_VX, 0x2, 0x0 }, // 10398
|
|
{ PseudoVWMACC_VX_MF8, VWMACC_VX, 0x5, 0x0 }, // 10399
|
|
{ PseudoVWMACC_VX_MF8_MASK, VWMACC_VX, 0x5, 0x0 }, // 10400
|
|
{ PseudoVWMACC_VX_MF4, VWMACC_VX, 0x6, 0x0 }, // 10401
|
|
{ PseudoVWMACC_VX_MF4_MASK, VWMACC_VX, 0x6, 0x0 }, // 10402
|
|
{ PseudoVWMACC_VX_MF2, VWMACC_VX, 0x7, 0x0 }, // 10403
|
|
{ PseudoVWMACC_VX_MF2_MASK, VWMACC_VX, 0x7, 0x0 }, // 10404
|
|
{ PseudoVWMULSU_VV_M1, VWMULSU_VV, 0x0, 0x0 }, // 10405
|
|
{ PseudoVWMULSU_VV_M1_MASK, VWMULSU_VV, 0x0, 0x0 }, // 10406
|
|
{ PseudoVWMULSU_VV_M2, VWMULSU_VV, 0x1, 0x0 }, // 10407
|
|
{ PseudoVWMULSU_VV_M2_MASK, VWMULSU_VV, 0x1, 0x0 }, // 10408
|
|
{ PseudoVWMULSU_VV_M4, VWMULSU_VV, 0x2, 0x0 }, // 10409
|
|
{ PseudoVWMULSU_VV_M4_MASK, VWMULSU_VV, 0x2, 0x0 }, // 10410
|
|
{ PseudoVWMULSU_VV_MF8, VWMULSU_VV, 0x5, 0x0 }, // 10411
|
|
{ PseudoVWMULSU_VV_MF8_MASK, VWMULSU_VV, 0x5, 0x0 }, // 10412
|
|
{ PseudoVWMULSU_VV_MF4, VWMULSU_VV, 0x6, 0x0 }, // 10413
|
|
{ PseudoVWMULSU_VV_MF4_MASK, VWMULSU_VV, 0x6, 0x0 }, // 10414
|
|
{ PseudoVWMULSU_VV_MF2, VWMULSU_VV, 0x7, 0x0 }, // 10415
|
|
{ PseudoVWMULSU_VV_MF2_MASK, VWMULSU_VV, 0x7, 0x0 }, // 10416
|
|
{ PseudoVWMULSU_VX_M1, VWMULSU_VX, 0x0, 0x0 }, // 10417
|
|
{ PseudoVWMULSU_VX_M1_MASK, VWMULSU_VX, 0x0, 0x0 }, // 10418
|
|
{ PseudoVWMULSU_VX_M2, VWMULSU_VX, 0x1, 0x0 }, // 10419
|
|
{ PseudoVWMULSU_VX_M2_MASK, VWMULSU_VX, 0x1, 0x0 }, // 10420
|
|
{ PseudoVWMULSU_VX_M4, VWMULSU_VX, 0x2, 0x0 }, // 10421
|
|
{ PseudoVWMULSU_VX_M4_MASK, VWMULSU_VX, 0x2, 0x0 }, // 10422
|
|
{ PseudoVWMULSU_VX_MF8, VWMULSU_VX, 0x5, 0x0 }, // 10423
|
|
{ PseudoVWMULSU_VX_MF8_MASK, VWMULSU_VX, 0x5, 0x0 }, // 10424
|
|
{ PseudoVWMULSU_VX_MF4, VWMULSU_VX, 0x6, 0x0 }, // 10425
|
|
{ PseudoVWMULSU_VX_MF4_MASK, VWMULSU_VX, 0x6, 0x0 }, // 10426
|
|
{ PseudoVWMULSU_VX_MF2, VWMULSU_VX, 0x7, 0x0 }, // 10427
|
|
{ PseudoVWMULSU_VX_MF2_MASK, VWMULSU_VX, 0x7, 0x0 }, // 10428
|
|
{ PseudoVWMULU_VV_M1, VWMULU_VV, 0x0, 0x0 }, // 10429
|
|
{ PseudoVWMULU_VV_M1_MASK, VWMULU_VV, 0x0, 0x0 }, // 10430
|
|
{ PseudoVWMULU_VV_M2, VWMULU_VV, 0x1, 0x0 }, // 10431
|
|
{ PseudoVWMULU_VV_M2_MASK, VWMULU_VV, 0x1, 0x0 }, // 10432
|
|
{ PseudoVWMULU_VV_M4, VWMULU_VV, 0x2, 0x0 }, // 10433
|
|
{ PseudoVWMULU_VV_M4_MASK, VWMULU_VV, 0x2, 0x0 }, // 10434
|
|
{ PseudoVWMULU_VV_MF8, VWMULU_VV, 0x5, 0x0 }, // 10435
|
|
{ PseudoVWMULU_VV_MF8_MASK, VWMULU_VV, 0x5, 0x0 }, // 10436
|
|
{ PseudoVWMULU_VV_MF4, VWMULU_VV, 0x6, 0x0 }, // 10437
|
|
{ PseudoVWMULU_VV_MF4_MASK, VWMULU_VV, 0x6, 0x0 }, // 10438
|
|
{ PseudoVWMULU_VV_MF2, VWMULU_VV, 0x7, 0x0 }, // 10439
|
|
{ PseudoVWMULU_VV_MF2_MASK, VWMULU_VV, 0x7, 0x0 }, // 10440
|
|
{ PseudoVWMULU_VX_M1, VWMULU_VX, 0x0, 0x0 }, // 10441
|
|
{ PseudoVWMULU_VX_M1_MASK, VWMULU_VX, 0x0, 0x0 }, // 10442
|
|
{ PseudoVWMULU_VX_M2, VWMULU_VX, 0x1, 0x0 }, // 10443
|
|
{ PseudoVWMULU_VX_M2_MASK, VWMULU_VX, 0x1, 0x0 }, // 10444
|
|
{ PseudoVWMULU_VX_M4, VWMULU_VX, 0x2, 0x0 }, // 10445
|
|
{ PseudoVWMULU_VX_M4_MASK, VWMULU_VX, 0x2, 0x0 }, // 10446
|
|
{ PseudoVWMULU_VX_MF8, VWMULU_VX, 0x5, 0x0 }, // 10447
|
|
{ PseudoVWMULU_VX_MF8_MASK, VWMULU_VX, 0x5, 0x0 }, // 10448
|
|
{ PseudoVWMULU_VX_MF4, VWMULU_VX, 0x6, 0x0 }, // 10449
|
|
{ PseudoVWMULU_VX_MF4_MASK, VWMULU_VX, 0x6, 0x0 }, // 10450
|
|
{ PseudoVWMULU_VX_MF2, VWMULU_VX, 0x7, 0x0 }, // 10451
|
|
{ PseudoVWMULU_VX_MF2_MASK, VWMULU_VX, 0x7, 0x0 }, // 10452
|
|
{ PseudoVWMUL_VV_M1, VWMUL_VV, 0x0, 0x0 }, // 10453
|
|
{ PseudoVWMUL_VV_M1_MASK, VWMUL_VV, 0x0, 0x0 }, // 10454
|
|
{ PseudoVWMUL_VV_M2, VWMUL_VV, 0x1, 0x0 }, // 10455
|
|
{ PseudoVWMUL_VV_M2_MASK, VWMUL_VV, 0x1, 0x0 }, // 10456
|
|
{ PseudoVWMUL_VV_M4, VWMUL_VV, 0x2, 0x0 }, // 10457
|
|
{ PseudoVWMUL_VV_M4_MASK, VWMUL_VV, 0x2, 0x0 }, // 10458
|
|
{ PseudoVWMUL_VV_MF8, VWMUL_VV, 0x5, 0x0 }, // 10459
|
|
{ PseudoVWMUL_VV_MF8_MASK, VWMUL_VV, 0x5, 0x0 }, // 10460
|
|
{ PseudoVWMUL_VV_MF4, VWMUL_VV, 0x6, 0x0 }, // 10461
|
|
{ PseudoVWMUL_VV_MF4_MASK, VWMUL_VV, 0x6, 0x0 }, // 10462
|
|
{ PseudoVWMUL_VV_MF2, VWMUL_VV, 0x7, 0x0 }, // 10463
|
|
{ PseudoVWMUL_VV_MF2_MASK, VWMUL_VV, 0x7, 0x0 }, // 10464
|
|
{ PseudoVWMUL_VX_M1, VWMUL_VX, 0x0, 0x0 }, // 10465
|
|
{ PseudoVWMUL_VX_M1_MASK, VWMUL_VX, 0x0, 0x0 }, // 10466
|
|
{ PseudoVWMUL_VX_M2, VWMUL_VX, 0x1, 0x0 }, // 10467
|
|
{ PseudoVWMUL_VX_M2_MASK, VWMUL_VX, 0x1, 0x0 }, // 10468
|
|
{ PseudoVWMUL_VX_M4, VWMUL_VX, 0x2, 0x0 }, // 10469
|
|
{ PseudoVWMUL_VX_M4_MASK, VWMUL_VX, 0x2, 0x0 }, // 10470
|
|
{ PseudoVWMUL_VX_MF8, VWMUL_VX, 0x5, 0x0 }, // 10471
|
|
{ PseudoVWMUL_VX_MF8_MASK, VWMUL_VX, 0x5, 0x0 }, // 10472
|
|
{ PseudoVWMUL_VX_MF4, VWMUL_VX, 0x6, 0x0 }, // 10473
|
|
{ PseudoVWMUL_VX_MF4_MASK, VWMUL_VX, 0x6, 0x0 }, // 10474
|
|
{ PseudoVWMUL_VX_MF2, VWMUL_VX, 0x7, 0x0 }, // 10475
|
|
{ PseudoVWMUL_VX_MF2_MASK, VWMUL_VX, 0x7, 0x0 }, // 10476
|
|
{ PseudoVWREDSUMU_VS_M1_E8, VWREDSUMU_VS, 0x0, 0x8 }, // 10477
|
|
{ PseudoVWREDSUMU_VS_M1_E8_MASK, VWREDSUMU_VS, 0x0, 0x8 }, // 10478
|
|
{ PseudoVWREDSUMU_VS_M1_E16, VWREDSUMU_VS, 0x0, 0x10 }, // 10479
|
|
{ PseudoVWREDSUMU_VS_M1_E16_MASK, VWREDSUMU_VS, 0x0, 0x10 }, // 10480
|
|
{ PseudoVWREDSUMU_VS_M1_E32, VWREDSUMU_VS, 0x0, 0x20 }, // 10481
|
|
{ PseudoVWREDSUMU_VS_M1_E32_MASK, VWREDSUMU_VS, 0x0, 0x20 }, // 10482
|
|
{ PseudoVWREDSUMU_VS_M2_E8, VWREDSUMU_VS, 0x1, 0x8 }, // 10483
|
|
{ PseudoVWREDSUMU_VS_M2_E8_MASK, VWREDSUMU_VS, 0x1, 0x8 }, // 10484
|
|
{ PseudoVWREDSUMU_VS_M2_E16, VWREDSUMU_VS, 0x1, 0x10 }, // 10485
|
|
{ PseudoVWREDSUMU_VS_M2_E16_MASK, VWREDSUMU_VS, 0x1, 0x10 }, // 10486
|
|
{ PseudoVWREDSUMU_VS_M2_E32, VWREDSUMU_VS, 0x1, 0x20 }, // 10487
|
|
{ PseudoVWREDSUMU_VS_M2_E32_MASK, VWREDSUMU_VS, 0x1, 0x20 }, // 10488
|
|
{ PseudoVWREDSUMU_VS_M4_E8, VWREDSUMU_VS, 0x2, 0x8 }, // 10489
|
|
{ PseudoVWREDSUMU_VS_M4_E8_MASK, VWREDSUMU_VS, 0x2, 0x8 }, // 10490
|
|
{ PseudoVWREDSUMU_VS_M4_E16, VWREDSUMU_VS, 0x2, 0x10 }, // 10491
|
|
{ PseudoVWREDSUMU_VS_M4_E16_MASK, VWREDSUMU_VS, 0x2, 0x10 }, // 10492
|
|
{ PseudoVWREDSUMU_VS_M4_E32, VWREDSUMU_VS, 0x2, 0x20 }, // 10493
|
|
{ PseudoVWREDSUMU_VS_M4_E32_MASK, VWREDSUMU_VS, 0x2, 0x20 }, // 10494
|
|
{ PseudoVWREDSUMU_VS_M8_E8, VWREDSUMU_VS, 0x3, 0x8 }, // 10495
|
|
{ PseudoVWREDSUMU_VS_M8_E8_MASK, VWREDSUMU_VS, 0x3, 0x8 }, // 10496
|
|
{ PseudoVWREDSUMU_VS_M8_E16, VWREDSUMU_VS, 0x3, 0x10 }, // 10497
|
|
{ PseudoVWREDSUMU_VS_M8_E16_MASK, VWREDSUMU_VS, 0x3, 0x10 }, // 10498
|
|
{ PseudoVWREDSUMU_VS_M8_E32, VWREDSUMU_VS, 0x3, 0x20 }, // 10499
|
|
{ PseudoVWREDSUMU_VS_M8_E32_MASK, VWREDSUMU_VS, 0x3, 0x20 }, // 10500
|
|
{ PseudoVWREDSUMU_VS_MF8_E8, VWREDSUMU_VS, 0x5, 0x8 }, // 10501
|
|
{ PseudoVWREDSUMU_VS_MF8_E8_MASK, VWREDSUMU_VS, 0x5, 0x8 }, // 10502
|
|
{ PseudoVWREDSUMU_VS_MF4_E8, VWREDSUMU_VS, 0x6, 0x8 }, // 10503
|
|
{ PseudoVWREDSUMU_VS_MF4_E8_MASK, VWREDSUMU_VS, 0x6, 0x8 }, // 10504
|
|
{ PseudoVWREDSUMU_VS_MF4_E16, VWREDSUMU_VS, 0x6, 0x10 }, // 10505
|
|
{ PseudoVWREDSUMU_VS_MF4_E16_MASK, VWREDSUMU_VS, 0x6, 0x10 }, // 10506
|
|
{ PseudoVWREDSUMU_VS_MF2_E8, VWREDSUMU_VS, 0x7, 0x8 }, // 10507
|
|
{ PseudoVWREDSUMU_VS_MF2_E8_MASK, VWREDSUMU_VS, 0x7, 0x8 }, // 10508
|
|
{ PseudoVWREDSUMU_VS_MF2_E16, VWREDSUMU_VS, 0x7, 0x10 }, // 10509
|
|
{ PseudoVWREDSUMU_VS_MF2_E16_MASK, VWREDSUMU_VS, 0x7, 0x10 }, // 10510
|
|
{ PseudoVWREDSUMU_VS_MF2_E32, VWREDSUMU_VS, 0x7, 0x20 }, // 10511
|
|
{ PseudoVWREDSUMU_VS_MF2_E32_MASK, VWREDSUMU_VS, 0x7, 0x20 }, // 10512
|
|
{ PseudoVWREDSUM_VS_M1_E8, VWREDSUM_VS, 0x0, 0x8 }, // 10513
|
|
{ PseudoVWREDSUM_VS_M1_E8_MASK, VWREDSUM_VS, 0x0, 0x8 }, // 10514
|
|
{ PseudoVWREDSUM_VS_M1_E16, VWREDSUM_VS, 0x0, 0x10 }, // 10515
|
|
{ PseudoVWREDSUM_VS_M1_E16_MASK, VWREDSUM_VS, 0x0, 0x10 }, // 10516
|
|
{ PseudoVWREDSUM_VS_M1_E32, VWREDSUM_VS, 0x0, 0x20 }, // 10517
|
|
{ PseudoVWREDSUM_VS_M1_E32_MASK, VWREDSUM_VS, 0x0, 0x20 }, // 10518
|
|
{ PseudoVWREDSUM_VS_M2_E8, VWREDSUM_VS, 0x1, 0x8 }, // 10519
|
|
{ PseudoVWREDSUM_VS_M2_E8_MASK, VWREDSUM_VS, 0x1, 0x8 }, // 10520
|
|
{ PseudoVWREDSUM_VS_M2_E16, VWREDSUM_VS, 0x1, 0x10 }, // 10521
|
|
{ PseudoVWREDSUM_VS_M2_E16_MASK, VWREDSUM_VS, 0x1, 0x10 }, // 10522
|
|
{ PseudoVWREDSUM_VS_M2_E32, VWREDSUM_VS, 0x1, 0x20 }, // 10523
|
|
{ PseudoVWREDSUM_VS_M2_E32_MASK, VWREDSUM_VS, 0x1, 0x20 }, // 10524
|
|
{ PseudoVWREDSUM_VS_M4_E8, VWREDSUM_VS, 0x2, 0x8 }, // 10525
|
|
{ PseudoVWREDSUM_VS_M4_E8_MASK, VWREDSUM_VS, 0x2, 0x8 }, // 10526
|
|
{ PseudoVWREDSUM_VS_M4_E16, VWREDSUM_VS, 0x2, 0x10 }, // 10527
|
|
{ PseudoVWREDSUM_VS_M4_E16_MASK, VWREDSUM_VS, 0x2, 0x10 }, // 10528
|
|
{ PseudoVWREDSUM_VS_M4_E32, VWREDSUM_VS, 0x2, 0x20 }, // 10529
|
|
{ PseudoVWREDSUM_VS_M4_E32_MASK, VWREDSUM_VS, 0x2, 0x20 }, // 10530
|
|
{ PseudoVWREDSUM_VS_M8_E8, VWREDSUM_VS, 0x3, 0x8 }, // 10531
|
|
{ PseudoVWREDSUM_VS_M8_E8_MASK, VWREDSUM_VS, 0x3, 0x8 }, // 10532
|
|
{ PseudoVWREDSUM_VS_M8_E16, VWREDSUM_VS, 0x3, 0x10 }, // 10533
|
|
{ PseudoVWREDSUM_VS_M8_E16_MASK, VWREDSUM_VS, 0x3, 0x10 }, // 10534
|
|
{ PseudoVWREDSUM_VS_M8_E32, VWREDSUM_VS, 0x3, 0x20 }, // 10535
|
|
{ PseudoVWREDSUM_VS_M8_E32_MASK, VWREDSUM_VS, 0x3, 0x20 }, // 10536
|
|
{ PseudoVWREDSUM_VS_MF8_E8, VWREDSUM_VS, 0x5, 0x8 }, // 10537
|
|
{ PseudoVWREDSUM_VS_MF8_E8_MASK, VWREDSUM_VS, 0x5, 0x8 }, // 10538
|
|
{ PseudoVWREDSUM_VS_MF4_E8, VWREDSUM_VS, 0x6, 0x8 }, // 10539
|
|
{ PseudoVWREDSUM_VS_MF4_E8_MASK, VWREDSUM_VS, 0x6, 0x8 }, // 10540
|
|
{ PseudoVWREDSUM_VS_MF4_E16, VWREDSUM_VS, 0x6, 0x10 }, // 10541
|
|
{ PseudoVWREDSUM_VS_MF4_E16_MASK, VWREDSUM_VS, 0x6, 0x10 }, // 10542
|
|
{ PseudoVWREDSUM_VS_MF2_E8, VWREDSUM_VS, 0x7, 0x8 }, // 10543
|
|
{ PseudoVWREDSUM_VS_MF2_E8_MASK, VWREDSUM_VS, 0x7, 0x8 }, // 10544
|
|
{ PseudoVWREDSUM_VS_MF2_E16, VWREDSUM_VS, 0x7, 0x10 }, // 10545
|
|
{ PseudoVWREDSUM_VS_MF2_E16_MASK, VWREDSUM_VS, 0x7, 0x10 }, // 10546
|
|
{ PseudoVWREDSUM_VS_MF2_E32, VWREDSUM_VS, 0x7, 0x20 }, // 10547
|
|
{ PseudoVWREDSUM_VS_MF2_E32_MASK, VWREDSUM_VS, 0x7, 0x20 }, // 10548
|
|
{ PseudoVWSLL_VI_M1, VWSLL_VI, 0x0, 0x0 }, // 10549
|
|
{ PseudoVWSLL_VI_M1_MASK, VWSLL_VI, 0x0, 0x0 }, // 10550
|
|
{ PseudoVWSLL_VI_M2, VWSLL_VI, 0x1, 0x0 }, // 10551
|
|
{ PseudoVWSLL_VI_M2_MASK, VWSLL_VI, 0x1, 0x0 }, // 10552
|
|
{ PseudoVWSLL_VI_M4, VWSLL_VI, 0x2, 0x0 }, // 10553
|
|
{ PseudoVWSLL_VI_M4_MASK, VWSLL_VI, 0x2, 0x0 }, // 10554
|
|
{ PseudoVWSLL_VI_MF8, VWSLL_VI, 0x5, 0x0 }, // 10555
|
|
{ PseudoVWSLL_VI_MF8_MASK, VWSLL_VI, 0x5, 0x0 }, // 10556
|
|
{ PseudoVWSLL_VI_MF4, VWSLL_VI, 0x6, 0x0 }, // 10557
|
|
{ PseudoVWSLL_VI_MF4_MASK, VWSLL_VI, 0x6, 0x0 }, // 10558
|
|
{ PseudoVWSLL_VI_MF2, VWSLL_VI, 0x7, 0x0 }, // 10559
|
|
{ PseudoVWSLL_VI_MF2_MASK, VWSLL_VI, 0x7, 0x0 }, // 10560
|
|
{ PseudoVWSLL_VV_M1, VWSLL_VV, 0x0, 0x0 }, // 10561
|
|
{ PseudoVWSLL_VV_M1_MASK, VWSLL_VV, 0x0, 0x0 }, // 10562
|
|
{ PseudoVWSLL_VV_M2, VWSLL_VV, 0x1, 0x0 }, // 10563
|
|
{ PseudoVWSLL_VV_M2_MASK, VWSLL_VV, 0x1, 0x0 }, // 10564
|
|
{ PseudoVWSLL_VV_M4, VWSLL_VV, 0x2, 0x0 }, // 10565
|
|
{ PseudoVWSLL_VV_M4_MASK, VWSLL_VV, 0x2, 0x0 }, // 10566
|
|
{ PseudoVWSLL_VV_MF8, VWSLL_VV, 0x5, 0x0 }, // 10567
|
|
{ PseudoVWSLL_VV_MF8_MASK, VWSLL_VV, 0x5, 0x0 }, // 10568
|
|
{ PseudoVWSLL_VV_MF4, VWSLL_VV, 0x6, 0x0 }, // 10569
|
|
{ PseudoVWSLL_VV_MF4_MASK, VWSLL_VV, 0x6, 0x0 }, // 10570
|
|
{ PseudoVWSLL_VV_MF2, VWSLL_VV, 0x7, 0x0 }, // 10571
|
|
{ PseudoVWSLL_VV_MF2_MASK, VWSLL_VV, 0x7, 0x0 }, // 10572
|
|
{ PseudoVWSLL_VX_M1, VWSLL_VX, 0x0, 0x0 }, // 10573
|
|
{ PseudoVWSLL_VX_M1_MASK, VWSLL_VX, 0x0, 0x0 }, // 10574
|
|
{ PseudoVWSLL_VX_M2, VWSLL_VX, 0x1, 0x0 }, // 10575
|
|
{ PseudoVWSLL_VX_M2_MASK, VWSLL_VX, 0x1, 0x0 }, // 10576
|
|
{ PseudoVWSLL_VX_M4, VWSLL_VX, 0x2, 0x0 }, // 10577
|
|
{ PseudoVWSLL_VX_M4_MASK, VWSLL_VX, 0x2, 0x0 }, // 10578
|
|
{ PseudoVWSLL_VX_MF8, VWSLL_VX, 0x5, 0x0 }, // 10579
|
|
{ PseudoVWSLL_VX_MF8_MASK, VWSLL_VX, 0x5, 0x0 }, // 10580
|
|
{ PseudoVWSLL_VX_MF4, VWSLL_VX, 0x6, 0x0 }, // 10581
|
|
{ PseudoVWSLL_VX_MF4_MASK, VWSLL_VX, 0x6, 0x0 }, // 10582
|
|
{ PseudoVWSLL_VX_MF2, VWSLL_VX, 0x7, 0x0 }, // 10583
|
|
{ PseudoVWSLL_VX_MF2_MASK, VWSLL_VX, 0x7, 0x0 }, // 10584
|
|
{ PseudoVWSUBU_VV_M1, VWSUBU_VV, 0x0, 0x0 }, // 10585
|
|
{ PseudoVWSUBU_VV_M1_MASK, VWSUBU_VV, 0x0, 0x0 }, // 10586
|
|
{ PseudoVWSUBU_VV_M2, VWSUBU_VV, 0x1, 0x0 }, // 10587
|
|
{ PseudoVWSUBU_VV_M2_MASK, VWSUBU_VV, 0x1, 0x0 }, // 10588
|
|
{ PseudoVWSUBU_VV_M4, VWSUBU_VV, 0x2, 0x0 }, // 10589
|
|
{ PseudoVWSUBU_VV_M4_MASK, VWSUBU_VV, 0x2, 0x0 }, // 10590
|
|
{ PseudoVWSUBU_VV_MF8, VWSUBU_VV, 0x5, 0x0 }, // 10591
|
|
{ PseudoVWSUBU_VV_MF8_MASK, VWSUBU_VV, 0x5, 0x0 }, // 10592
|
|
{ PseudoVWSUBU_VV_MF4, VWSUBU_VV, 0x6, 0x0 }, // 10593
|
|
{ PseudoVWSUBU_VV_MF4_MASK, VWSUBU_VV, 0x6, 0x0 }, // 10594
|
|
{ PseudoVWSUBU_VV_MF2, VWSUBU_VV, 0x7, 0x0 }, // 10595
|
|
{ PseudoVWSUBU_VV_MF2_MASK, VWSUBU_VV, 0x7, 0x0 }, // 10596
|
|
{ PseudoVWSUBU_VX_M1, VWSUBU_VX, 0x0, 0x0 }, // 10597
|
|
{ PseudoVWSUBU_VX_M1_MASK, VWSUBU_VX, 0x0, 0x0 }, // 10598
|
|
{ PseudoVWSUBU_VX_M2, VWSUBU_VX, 0x1, 0x0 }, // 10599
|
|
{ PseudoVWSUBU_VX_M2_MASK, VWSUBU_VX, 0x1, 0x0 }, // 10600
|
|
{ PseudoVWSUBU_VX_M4, VWSUBU_VX, 0x2, 0x0 }, // 10601
|
|
{ PseudoVWSUBU_VX_M4_MASK, VWSUBU_VX, 0x2, 0x0 }, // 10602
|
|
{ PseudoVWSUBU_VX_MF8, VWSUBU_VX, 0x5, 0x0 }, // 10603
|
|
{ PseudoVWSUBU_VX_MF8_MASK, VWSUBU_VX, 0x5, 0x0 }, // 10604
|
|
{ PseudoVWSUBU_VX_MF4, VWSUBU_VX, 0x6, 0x0 }, // 10605
|
|
{ PseudoVWSUBU_VX_MF4_MASK, VWSUBU_VX, 0x6, 0x0 }, // 10606
|
|
{ PseudoVWSUBU_VX_MF2, VWSUBU_VX, 0x7, 0x0 }, // 10607
|
|
{ PseudoVWSUBU_VX_MF2_MASK, VWSUBU_VX, 0x7, 0x0 }, // 10608
|
|
{ PseudoVWSUBU_WV_M1, VWSUBU_WV, 0x0, 0x0 }, // 10609
|
|
{ PseudoVWSUBU_WV_M1_MASK, VWSUBU_WV, 0x0, 0x0 }, // 10610
|
|
{ PseudoVWSUBU_WV_M1_MASK_TIED, VWSUBU_WV, 0x0, 0x0 }, // 10611
|
|
{ PseudoVWSUBU_WV_M1_TIED, VWSUBU_WV, 0x0, 0x0 }, // 10612
|
|
{ PseudoVWSUBU_WV_M2, VWSUBU_WV, 0x1, 0x0 }, // 10613
|
|
{ PseudoVWSUBU_WV_M2_MASK, VWSUBU_WV, 0x1, 0x0 }, // 10614
|
|
{ PseudoVWSUBU_WV_M2_MASK_TIED, VWSUBU_WV, 0x1, 0x0 }, // 10615
|
|
{ PseudoVWSUBU_WV_M2_TIED, VWSUBU_WV, 0x1, 0x0 }, // 10616
|
|
{ PseudoVWSUBU_WV_M4, VWSUBU_WV, 0x2, 0x0 }, // 10617
|
|
{ PseudoVWSUBU_WV_M4_MASK, VWSUBU_WV, 0x2, 0x0 }, // 10618
|
|
{ PseudoVWSUBU_WV_M4_MASK_TIED, VWSUBU_WV, 0x2, 0x0 }, // 10619
|
|
{ PseudoVWSUBU_WV_M4_TIED, VWSUBU_WV, 0x2, 0x0 }, // 10620
|
|
{ PseudoVWSUBU_WV_MF8, VWSUBU_WV, 0x5, 0x0 }, // 10621
|
|
{ PseudoVWSUBU_WV_MF8_MASK, VWSUBU_WV, 0x5, 0x0 }, // 10622
|
|
{ PseudoVWSUBU_WV_MF8_MASK_TIED, VWSUBU_WV, 0x5, 0x0 }, // 10623
|
|
{ PseudoVWSUBU_WV_MF8_TIED, VWSUBU_WV, 0x5, 0x0 }, // 10624
|
|
{ PseudoVWSUBU_WV_MF4, VWSUBU_WV, 0x6, 0x0 }, // 10625
|
|
{ PseudoVWSUBU_WV_MF4_MASK, VWSUBU_WV, 0x6, 0x0 }, // 10626
|
|
{ PseudoVWSUBU_WV_MF4_MASK_TIED, VWSUBU_WV, 0x6, 0x0 }, // 10627
|
|
{ PseudoVWSUBU_WV_MF4_TIED, VWSUBU_WV, 0x6, 0x0 }, // 10628
|
|
{ PseudoVWSUBU_WV_MF2, VWSUBU_WV, 0x7, 0x0 }, // 10629
|
|
{ PseudoVWSUBU_WV_MF2_MASK, VWSUBU_WV, 0x7, 0x0 }, // 10630
|
|
{ PseudoVWSUBU_WV_MF2_MASK_TIED, VWSUBU_WV, 0x7, 0x0 }, // 10631
|
|
{ PseudoVWSUBU_WV_MF2_TIED, VWSUBU_WV, 0x7, 0x0 }, // 10632
|
|
{ PseudoVWSUBU_WX_M1, VWSUBU_WX, 0x0, 0x0 }, // 10633
|
|
{ PseudoVWSUBU_WX_M1_MASK, VWSUBU_WX, 0x0, 0x0 }, // 10634
|
|
{ PseudoVWSUBU_WX_M2, VWSUBU_WX, 0x1, 0x0 }, // 10635
|
|
{ PseudoVWSUBU_WX_M2_MASK, VWSUBU_WX, 0x1, 0x0 }, // 10636
|
|
{ PseudoVWSUBU_WX_M4, VWSUBU_WX, 0x2, 0x0 }, // 10637
|
|
{ PseudoVWSUBU_WX_M4_MASK, VWSUBU_WX, 0x2, 0x0 }, // 10638
|
|
{ PseudoVWSUBU_WX_MF8, VWSUBU_WX, 0x5, 0x0 }, // 10639
|
|
{ PseudoVWSUBU_WX_MF8_MASK, VWSUBU_WX, 0x5, 0x0 }, // 10640
|
|
{ PseudoVWSUBU_WX_MF4, VWSUBU_WX, 0x6, 0x0 }, // 10641
|
|
{ PseudoVWSUBU_WX_MF4_MASK, VWSUBU_WX, 0x6, 0x0 }, // 10642
|
|
{ PseudoVWSUBU_WX_MF2, VWSUBU_WX, 0x7, 0x0 }, // 10643
|
|
{ PseudoVWSUBU_WX_MF2_MASK, VWSUBU_WX, 0x7, 0x0 }, // 10644
|
|
{ PseudoVWSUB_VV_M1, VWSUB_VV, 0x0, 0x0 }, // 10645
|
|
{ PseudoVWSUB_VV_M1_MASK, VWSUB_VV, 0x0, 0x0 }, // 10646
|
|
{ PseudoVWSUB_VV_M2, VWSUB_VV, 0x1, 0x0 }, // 10647
|
|
{ PseudoVWSUB_VV_M2_MASK, VWSUB_VV, 0x1, 0x0 }, // 10648
|
|
{ PseudoVWSUB_VV_M4, VWSUB_VV, 0x2, 0x0 }, // 10649
|
|
{ PseudoVWSUB_VV_M4_MASK, VWSUB_VV, 0x2, 0x0 }, // 10650
|
|
{ PseudoVWSUB_VV_MF8, VWSUB_VV, 0x5, 0x0 }, // 10651
|
|
{ PseudoVWSUB_VV_MF8_MASK, VWSUB_VV, 0x5, 0x0 }, // 10652
|
|
{ PseudoVWSUB_VV_MF4, VWSUB_VV, 0x6, 0x0 }, // 10653
|
|
{ PseudoVWSUB_VV_MF4_MASK, VWSUB_VV, 0x6, 0x0 }, // 10654
|
|
{ PseudoVWSUB_VV_MF2, VWSUB_VV, 0x7, 0x0 }, // 10655
|
|
{ PseudoVWSUB_VV_MF2_MASK, VWSUB_VV, 0x7, 0x0 }, // 10656
|
|
{ PseudoVWSUB_VX_M1, VWSUB_VX, 0x0, 0x0 }, // 10657
|
|
{ PseudoVWSUB_VX_M1_MASK, VWSUB_VX, 0x0, 0x0 }, // 10658
|
|
{ PseudoVWSUB_VX_M2, VWSUB_VX, 0x1, 0x0 }, // 10659
|
|
{ PseudoVWSUB_VX_M2_MASK, VWSUB_VX, 0x1, 0x0 }, // 10660
|
|
{ PseudoVWSUB_VX_M4, VWSUB_VX, 0x2, 0x0 }, // 10661
|
|
{ PseudoVWSUB_VX_M4_MASK, VWSUB_VX, 0x2, 0x0 }, // 10662
|
|
{ PseudoVWSUB_VX_MF8, VWSUB_VX, 0x5, 0x0 }, // 10663
|
|
{ PseudoVWSUB_VX_MF8_MASK, VWSUB_VX, 0x5, 0x0 }, // 10664
|
|
{ PseudoVWSUB_VX_MF4, VWSUB_VX, 0x6, 0x0 }, // 10665
|
|
{ PseudoVWSUB_VX_MF4_MASK, VWSUB_VX, 0x6, 0x0 }, // 10666
|
|
{ PseudoVWSUB_VX_MF2, VWSUB_VX, 0x7, 0x0 }, // 10667
|
|
{ PseudoVWSUB_VX_MF2_MASK, VWSUB_VX, 0x7, 0x0 }, // 10668
|
|
{ PseudoVWSUB_WV_M1, VWSUB_WV, 0x0, 0x0 }, // 10669
|
|
{ PseudoVWSUB_WV_M1_MASK, VWSUB_WV, 0x0, 0x0 }, // 10670
|
|
{ PseudoVWSUB_WV_M1_MASK_TIED, VWSUB_WV, 0x0, 0x0 }, // 10671
|
|
{ PseudoVWSUB_WV_M1_TIED, VWSUB_WV, 0x0, 0x0 }, // 10672
|
|
{ PseudoVWSUB_WV_M2, VWSUB_WV, 0x1, 0x0 }, // 10673
|
|
{ PseudoVWSUB_WV_M2_MASK, VWSUB_WV, 0x1, 0x0 }, // 10674
|
|
{ PseudoVWSUB_WV_M2_MASK_TIED, VWSUB_WV, 0x1, 0x0 }, // 10675
|
|
{ PseudoVWSUB_WV_M2_TIED, VWSUB_WV, 0x1, 0x0 }, // 10676
|
|
{ PseudoVWSUB_WV_M4, VWSUB_WV, 0x2, 0x0 }, // 10677
|
|
{ PseudoVWSUB_WV_M4_MASK, VWSUB_WV, 0x2, 0x0 }, // 10678
|
|
{ PseudoVWSUB_WV_M4_MASK_TIED, VWSUB_WV, 0x2, 0x0 }, // 10679
|
|
{ PseudoVWSUB_WV_M4_TIED, VWSUB_WV, 0x2, 0x0 }, // 10680
|
|
{ PseudoVWSUB_WV_MF8, VWSUB_WV, 0x5, 0x0 }, // 10681
|
|
{ PseudoVWSUB_WV_MF8_MASK, VWSUB_WV, 0x5, 0x0 }, // 10682
|
|
{ PseudoVWSUB_WV_MF8_MASK_TIED, VWSUB_WV, 0x5, 0x0 }, // 10683
|
|
{ PseudoVWSUB_WV_MF8_TIED, VWSUB_WV, 0x5, 0x0 }, // 10684
|
|
{ PseudoVWSUB_WV_MF4, VWSUB_WV, 0x6, 0x0 }, // 10685
|
|
{ PseudoVWSUB_WV_MF4_MASK, VWSUB_WV, 0x6, 0x0 }, // 10686
|
|
{ PseudoVWSUB_WV_MF4_MASK_TIED, VWSUB_WV, 0x6, 0x0 }, // 10687
|
|
{ PseudoVWSUB_WV_MF4_TIED, VWSUB_WV, 0x6, 0x0 }, // 10688
|
|
{ PseudoVWSUB_WV_MF2, VWSUB_WV, 0x7, 0x0 }, // 10689
|
|
{ PseudoVWSUB_WV_MF2_MASK, VWSUB_WV, 0x7, 0x0 }, // 10690
|
|
{ PseudoVWSUB_WV_MF2_MASK_TIED, VWSUB_WV, 0x7, 0x0 }, // 10691
|
|
{ PseudoVWSUB_WV_MF2_TIED, VWSUB_WV, 0x7, 0x0 }, // 10692
|
|
{ PseudoVWSUB_WX_M1, VWSUB_WX, 0x0, 0x0 }, // 10693
|
|
{ PseudoVWSUB_WX_M1_MASK, VWSUB_WX, 0x0, 0x0 }, // 10694
|
|
{ PseudoVWSUB_WX_M2, VWSUB_WX, 0x1, 0x0 }, // 10695
|
|
{ PseudoVWSUB_WX_M2_MASK, VWSUB_WX, 0x1, 0x0 }, // 10696
|
|
{ PseudoVWSUB_WX_M4, VWSUB_WX, 0x2, 0x0 }, // 10697
|
|
{ PseudoVWSUB_WX_M4_MASK, VWSUB_WX, 0x2, 0x0 }, // 10698
|
|
{ PseudoVWSUB_WX_MF8, VWSUB_WX, 0x5, 0x0 }, // 10699
|
|
{ PseudoVWSUB_WX_MF8_MASK, VWSUB_WX, 0x5, 0x0 }, // 10700
|
|
{ PseudoVWSUB_WX_MF4, VWSUB_WX, 0x6, 0x0 }, // 10701
|
|
{ PseudoVWSUB_WX_MF4_MASK, VWSUB_WX, 0x6, 0x0 }, // 10702
|
|
{ PseudoVWSUB_WX_MF2, VWSUB_WX, 0x7, 0x0 }, // 10703
|
|
{ PseudoVWSUB_WX_MF2_MASK, VWSUB_WX, 0x7, 0x0 }, // 10704
|
|
{ PseudoVXOR_VI_M1, VXOR_VI, 0x0, 0x0 }, // 10705
|
|
{ PseudoVXOR_VI_M1_MASK, VXOR_VI, 0x0, 0x0 }, // 10706
|
|
{ PseudoVXOR_VI_M2, VXOR_VI, 0x1, 0x0 }, // 10707
|
|
{ PseudoVXOR_VI_M2_MASK, VXOR_VI, 0x1, 0x0 }, // 10708
|
|
{ PseudoVXOR_VI_M4, VXOR_VI, 0x2, 0x0 }, // 10709
|
|
{ PseudoVXOR_VI_M4_MASK, VXOR_VI, 0x2, 0x0 }, // 10710
|
|
{ PseudoVXOR_VI_M8, VXOR_VI, 0x3, 0x0 }, // 10711
|
|
{ PseudoVXOR_VI_M8_MASK, VXOR_VI, 0x3, 0x0 }, // 10712
|
|
{ PseudoVXOR_VI_MF8, VXOR_VI, 0x5, 0x0 }, // 10713
|
|
{ PseudoVXOR_VI_MF8_MASK, VXOR_VI, 0x5, 0x0 }, // 10714
|
|
{ PseudoVXOR_VI_MF4, VXOR_VI, 0x6, 0x0 }, // 10715
|
|
{ PseudoVXOR_VI_MF4_MASK, VXOR_VI, 0x6, 0x0 }, // 10716
|
|
{ PseudoVXOR_VI_MF2, VXOR_VI, 0x7, 0x0 }, // 10717
|
|
{ PseudoVXOR_VI_MF2_MASK, VXOR_VI, 0x7, 0x0 }, // 10718
|
|
{ PseudoVXOR_VV_M1, VXOR_VV, 0x0, 0x0 }, // 10719
|
|
{ PseudoVXOR_VV_M1_MASK, VXOR_VV, 0x0, 0x0 }, // 10720
|
|
{ PseudoVXOR_VV_M2, VXOR_VV, 0x1, 0x0 }, // 10721
|
|
{ PseudoVXOR_VV_M2_MASK, VXOR_VV, 0x1, 0x0 }, // 10722
|
|
{ PseudoVXOR_VV_M4, VXOR_VV, 0x2, 0x0 }, // 10723
|
|
{ PseudoVXOR_VV_M4_MASK, VXOR_VV, 0x2, 0x0 }, // 10724
|
|
{ PseudoVXOR_VV_M8, VXOR_VV, 0x3, 0x0 }, // 10725
|
|
{ PseudoVXOR_VV_M8_MASK, VXOR_VV, 0x3, 0x0 }, // 10726
|
|
{ PseudoVXOR_VV_MF8, VXOR_VV, 0x5, 0x0 }, // 10727
|
|
{ PseudoVXOR_VV_MF8_MASK, VXOR_VV, 0x5, 0x0 }, // 10728
|
|
{ PseudoVXOR_VV_MF4, VXOR_VV, 0x6, 0x0 }, // 10729
|
|
{ PseudoVXOR_VV_MF4_MASK, VXOR_VV, 0x6, 0x0 }, // 10730
|
|
{ PseudoVXOR_VV_MF2, VXOR_VV, 0x7, 0x0 }, // 10731
|
|
{ PseudoVXOR_VV_MF2_MASK, VXOR_VV, 0x7, 0x0 }, // 10732
|
|
{ PseudoVXOR_VX_M1, VXOR_VX, 0x0, 0x0 }, // 10733
|
|
{ PseudoVXOR_VX_M1_MASK, VXOR_VX, 0x0, 0x0 }, // 10734
|
|
{ PseudoVXOR_VX_M2, VXOR_VX, 0x1, 0x0 }, // 10735
|
|
{ PseudoVXOR_VX_M2_MASK, VXOR_VX, 0x1, 0x0 }, // 10736
|
|
{ PseudoVXOR_VX_M4, VXOR_VX, 0x2, 0x0 }, // 10737
|
|
{ PseudoVXOR_VX_M4_MASK, VXOR_VX, 0x2, 0x0 }, // 10738
|
|
{ PseudoVXOR_VX_M8, VXOR_VX, 0x3, 0x0 }, // 10739
|
|
{ PseudoVXOR_VX_M8_MASK, VXOR_VX, 0x3, 0x0 }, // 10740
|
|
{ PseudoVXOR_VX_MF8, VXOR_VX, 0x5, 0x0 }, // 10741
|
|
{ PseudoVXOR_VX_MF8_MASK, VXOR_VX, 0x5, 0x0 }, // 10742
|
|
{ PseudoVXOR_VX_MF4, VXOR_VX, 0x6, 0x0 }, // 10743
|
|
{ PseudoVXOR_VX_MF4_MASK, VXOR_VX, 0x6, 0x0 }, // 10744
|
|
{ PseudoVXOR_VX_MF2, VXOR_VX, 0x7, 0x0 }, // 10745
|
|
{ PseudoVXOR_VX_MF2_MASK, VXOR_VX, 0x7, 0x0 }, // 10746
|
|
{ PseudoVZEXT_VF2_M1, VZEXT_VF2, 0x0, 0x0 }, // 10747
|
|
{ PseudoVZEXT_VF2_M1_MASK, VZEXT_VF2, 0x0, 0x0 }, // 10748
|
|
{ PseudoVZEXT_VF2_M2, VZEXT_VF2, 0x1, 0x0 }, // 10749
|
|
{ PseudoVZEXT_VF2_M2_MASK, VZEXT_VF2, 0x1, 0x0 }, // 10750
|
|
{ PseudoVZEXT_VF2_M4, VZEXT_VF2, 0x2, 0x0 }, // 10751
|
|
{ PseudoVZEXT_VF2_M4_MASK, VZEXT_VF2, 0x2, 0x0 }, // 10752
|
|
{ PseudoVZEXT_VF2_M8, VZEXT_VF2, 0x3, 0x0 }, // 10753
|
|
{ PseudoVZEXT_VF2_M8_MASK, VZEXT_VF2, 0x3, 0x0 }, // 10754
|
|
{ PseudoVZEXT_VF2_MF4, VZEXT_VF2, 0x6, 0x0 }, // 10755
|
|
{ PseudoVZEXT_VF2_MF4_MASK, VZEXT_VF2, 0x6, 0x0 }, // 10756
|
|
{ PseudoVZEXT_VF2_MF2, VZEXT_VF2, 0x7, 0x0 }, // 10757
|
|
{ PseudoVZEXT_VF2_MF2_MASK, VZEXT_VF2, 0x7, 0x0 }, // 10758
|
|
{ PseudoVZEXT_VF4_M1, VZEXT_VF4, 0x0, 0x0 }, // 10759
|
|
{ PseudoVZEXT_VF4_M1_MASK, VZEXT_VF4, 0x0, 0x0 }, // 10760
|
|
{ PseudoVZEXT_VF4_M2, VZEXT_VF4, 0x1, 0x0 }, // 10761
|
|
{ PseudoVZEXT_VF4_M2_MASK, VZEXT_VF4, 0x1, 0x0 }, // 10762
|
|
{ PseudoVZEXT_VF4_M4, VZEXT_VF4, 0x2, 0x0 }, // 10763
|
|
{ PseudoVZEXT_VF4_M4_MASK, VZEXT_VF4, 0x2, 0x0 }, // 10764
|
|
{ PseudoVZEXT_VF4_M8, VZEXT_VF4, 0x3, 0x0 }, // 10765
|
|
{ PseudoVZEXT_VF4_M8_MASK, VZEXT_VF4, 0x3, 0x0 }, // 10766
|
|
{ PseudoVZEXT_VF4_MF2, VZEXT_VF4, 0x7, 0x0 }, // 10767
|
|
{ PseudoVZEXT_VF4_MF2_MASK, VZEXT_VF4, 0x7, 0x0 }, // 10768
|
|
{ PseudoVZEXT_VF8_M1, VZEXT_VF8, 0x0, 0x0 }, // 10769
|
|
{ PseudoVZEXT_VF8_M1_MASK, VZEXT_VF8, 0x0, 0x0 }, // 10770
|
|
{ PseudoVZEXT_VF8_M2, VZEXT_VF8, 0x1, 0x0 }, // 10771
|
|
{ PseudoVZEXT_VF8_M2_MASK, VZEXT_VF8, 0x1, 0x0 }, // 10772
|
|
{ PseudoVZEXT_VF8_M4, VZEXT_VF8, 0x2, 0x0 }, // 10773
|
|
{ PseudoVZEXT_VF8_M4_MASK, VZEXT_VF8, 0x2, 0x0 }, // 10774
|
|
{ PseudoVZEXT_VF8_M8, VZEXT_VF8, 0x3, 0x0 }, // 10775
|
|
{ PseudoVZEXT_VF8_M8_MASK, VZEXT_VF8, 0x3, 0x0 }, // 10776
|
|
};
|
|
|
|
const RISCV_PseudoInfo *RISCV_getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), BaseInstrVLMulSEW);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVInversePseudosTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVLETable_IMPL
|
|
static const RISCV_VLEPseudo RISCVVLETable[] = {
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x0, PseudoVLM_V_B8 }, // 0
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x1, PseudoVLM_V_B16 }, // 1
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x2, PseudoVLM_V_B32 }, // 2
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x3, PseudoVLM_V_B64 }, // 3
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x5, PseudoVLM_V_B1 }, // 4
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x6, PseudoVLM_V_B2 }, // 5
|
|
{ 0x0, 0x0, 0x0, 0x0, 0x7, PseudoVLM_V_B4 }, // 6
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLE8_V_M1 }, // 7
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLE8_V_M2 }, // 8
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x2, PseudoVLE8_V_M4 }, // 9
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x3, PseudoVLE8_V_M8 }, // 10
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLE8_V_MF8 }, // 11
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLE8_V_MF4 }, // 12
|
|
{ 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLE8_V_MF2 }, // 13
|
|
{ 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLE16_V_M1 }, // 14
|
|
{ 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLE16_V_M2 }, // 15
|
|
{ 0x0, 0x0, 0x0, 0x4, 0x2, PseudoVLE16_V_M4 }, // 16
|
|
{ 0x0, 0x0, 0x0, 0x4, 0x3, PseudoVLE16_V_M8 }, // 17
|
|
{ 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLE16_V_MF4 }, // 18
|
|
{ 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLE16_V_MF2 }, // 19
|
|
{ 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLE32_V_M1 }, // 20
|
|
{ 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLE32_V_M2 }, // 21
|
|
{ 0x0, 0x0, 0x0, 0x5, 0x2, PseudoVLE32_V_M4 }, // 22
|
|
{ 0x0, 0x0, 0x0, 0x5, 0x3, PseudoVLE32_V_M8 }, // 23
|
|
{ 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLE32_V_MF2 }, // 24
|
|
{ 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLE64_V_M1 }, // 25
|
|
{ 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLE64_V_M2 }, // 26
|
|
{ 0x0, 0x0, 0x0, 0x6, 0x2, PseudoVLE64_V_M4 }, // 27
|
|
{ 0x0, 0x0, 0x0, 0x6, 0x3, PseudoVLE64_V_M8 }, // 28
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLE8FF_V_M1 }, // 29
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLE8FF_V_M2 }, // 30
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x2, PseudoVLE8FF_V_M4 }, // 31
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x3, PseudoVLE8FF_V_M8 }, // 32
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLE8FF_V_MF8 }, // 33
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLE8FF_V_MF4 }, // 34
|
|
{ 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLE8FF_V_MF2 }, // 35
|
|
{ 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLE16FF_V_M1 }, // 36
|
|
{ 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLE16FF_V_M2 }, // 37
|
|
{ 0x0, 0x0, 0x1, 0x4, 0x2, PseudoVLE16FF_V_M4 }, // 38
|
|
{ 0x0, 0x0, 0x1, 0x4, 0x3, PseudoVLE16FF_V_M8 }, // 39
|
|
{ 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLE16FF_V_MF4 }, // 40
|
|
{ 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLE16FF_V_MF2 }, // 41
|
|
{ 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLE32FF_V_M1 }, // 42
|
|
{ 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLE32FF_V_M2 }, // 43
|
|
{ 0x0, 0x0, 0x1, 0x5, 0x2, PseudoVLE32FF_V_M4 }, // 44
|
|
{ 0x0, 0x0, 0x1, 0x5, 0x3, PseudoVLE32FF_V_M8 }, // 45
|
|
{ 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLE32FF_V_MF2 }, // 46
|
|
{ 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLE64FF_V_M1 }, // 47
|
|
{ 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLE64FF_V_M2 }, // 48
|
|
{ 0x0, 0x0, 0x1, 0x6, 0x2, PseudoVLE64FF_V_M4 }, // 49
|
|
{ 0x0, 0x0, 0x1, 0x6, 0x3, PseudoVLE64FF_V_M8 }, // 50
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSE8_V_M1 }, // 51
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSE8_V_M2 }, // 52
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x2, PseudoVLSE8_V_M4 }, // 53
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x3, PseudoVLSE8_V_M8 }, // 54
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSE8_V_MF8 }, // 55
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSE8_V_MF4 }, // 56
|
|
{ 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSE8_V_MF2 }, // 57
|
|
{ 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSE16_V_M1 }, // 58
|
|
{ 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSE16_V_M2 }, // 59
|
|
{ 0x0, 0x1, 0x0, 0x4, 0x2, PseudoVLSE16_V_M4 }, // 60
|
|
{ 0x0, 0x1, 0x0, 0x4, 0x3, PseudoVLSE16_V_M8 }, // 61
|
|
{ 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSE16_V_MF4 }, // 62
|
|
{ 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSE16_V_MF2 }, // 63
|
|
{ 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSE32_V_M1 }, // 64
|
|
{ 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSE32_V_M2 }, // 65
|
|
{ 0x0, 0x1, 0x0, 0x5, 0x2, PseudoVLSE32_V_M4 }, // 66
|
|
{ 0x0, 0x1, 0x0, 0x5, 0x3, PseudoVLSE32_V_M8 }, // 67
|
|
{ 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSE32_V_MF2 }, // 68
|
|
{ 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSE64_V_M1 }, // 69
|
|
{ 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSE64_V_M2 }, // 70
|
|
{ 0x0, 0x1, 0x0, 0x6, 0x2, PseudoVLSE64_V_M4 }, // 71
|
|
{ 0x0, 0x1, 0x0, 0x6, 0x3, PseudoVLSE64_V_M8 }, // 72
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLE8_V_M1_MASK }, // 73
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLE8_V_M2_MASK }, // 74
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x2, PseudoVLE8_V_M4_MASK }, // 75
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x3, PseudoVLE8_V_M8_MASK }, // 76
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLE8_V_MF8_MASK }, // 77
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLE8_V_MF4_MASK }, // 78
|
|
{ 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLE8_V_MF2_MASK }, // 79
|
|
{ 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLE16_V_M1_MASK }, // 80
|
|
{ 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLE16_V_M2_MASK }, // 81
|
|
{ 0x1, 0x0, 0x0, 0x4, 0x2, PseudoVLE16_V_M4_MASK }, // 82
|
|
{ 0x1, 0x0, 0x0, 0x4, 0x3, PseudoVLE16_V_M8_MASK }, // 83
|
|
{ 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLE16_V_MF4_MASK }, // 84
|
|
{ 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLE16_V_MF2_MASK }, // 85
|
|
{ 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLE32_V_M1_MASK }, // 86
|
|
{ 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLE32_V_M2_MASK }, // 87
|
|
{ 0x1, 0x0, 0x0, 0x5, 0x2, PseudoVLE32_V_M4_MASK }, // 88
|
|
{ 0x1, 0x0, 0x0, 0x5, 0x3, PseudoVLE32_V_M8_MASK }, // 89
|
|
{ 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLE32_V_MF2_MASK }, // 90
|
|
{ 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLE64_V_M1_MASK }, // 91
|
|
{ 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLE64_V_M2_MASK }, // 92
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|
{ 0x1, 0x0, 0x0, 0x6, 0x2, PseudoVLE64_V_M4_MASK }, // 93
|
|
{ 0x1, 0x0, 0x0, 0x6, 0x3, PseudoVLE64_V_M8_MASK }, // 94
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|
{ 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLE8FF_V_M1_MASK }, // 95
|
|
{ 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLE8FF_V_M2_MASK }, // 96
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|
{ 0x1, 0x0, 0x1, 0x3, 0x2, PseudoVLE8FF_V_M4_MASK }, // 97
|
|
{ 0x1, 0x0, 0x1, 0x3, 0x3, PseudoVLE8FF_V_M8_MASK }, // 98
|
|
{ 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLE8FF_V_MF8_MASK }, // 99
|
|
{ 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLE8FF_V_MF4_MASK }, // 100
|
|
{ 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLE8FF_V_MF2_MASK }, // 101
|
|
{ 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLE16FF_V_M1_MASK }, // 102
|
|
{ 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLE16FF_V_M2_MASK }, // 103
|
|
{ 0x1, 0x0, 0x1, 0x4, 0x2, PseudoVLE16FF_V_M4_MASK }, // 104
|
|
{ 0x1, 0x0, 0x1, 0x4, 0x3, PseudoVLE16FF_V_M8_MASK }, // 105
|
|
{ 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLE16FF_V_MF4_MASK }, // 106
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|
{ 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLE16FF_V_MF2_MASK }, // 107
|
|
{ 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLE32FF_V_M1_MASK }, // 108
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|
{ 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLE32FF_V_M2_MASK }, // 109
|
|
{ 0x1, 0x0, 0x1, 0x5, 0x2, PseudoVLE32FF_V_M4_MASK }, // 110
|
|
{ 0x1, 0x0, 0x1, 0x5, 0x3, PseudoVLE32FF_V_M8_MASK }, // 111
|
|
{ 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLE32FF_V_MF2_MASK }, // 112
|
|
{ 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLE64FF_V_M1_MASK }, // 113
|
|
{ 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLE64FF_V_M2_MASK }, // 114
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|
{ 0x1, 0x0, 0x1, 0x6, 0x2, PseudoVLE64FF_V_M4_MASK }, // 115
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|
{ 0x1, 0x0, 0x1, 0x6, 0x3, PseudoVLE64FF_V_M8_MASK }, // 116
|
|
{ 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSE8_V_M1_MASK }, // 117
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|
{ 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSE8_V_M2_MASK }, // 118
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|
{ 0x1, 0x1, 0x0, 0x3, 0x2, PseudoVLSE8_V_M4_MASK }, // 119
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|
{ 0x1, 0x1, 0x0, 0x3, 0x3, PseudoVLSE8_V_M8_MASK }, // 120
|
|
{ 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSE8_V_MF8_MASK }, // 121
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|
{ 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSE8_V_MF4_MASK }, // 122
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|
{ 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSE8_V_MF2_MASK }, // 123
|
|
{ 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSE16_V_M1_MASK }, // 124
|
|
{ 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSE16_V_M2_MASK }, // 125
|
|
{ 0x1, 0x1, 0x0, 0x4, 0x2, PseudoVLSE16_V_M4_MASK }, // 126
|
|
{ 0x1, 0x1, 0x0, 0x4, 0x3, PseudoVLSE16_V_M8_MASK }, // 127
|
|
{ 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSE16_V_MF4_MASK }, // 128
|
|
{ 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSE16_V_MF2_MASK }, // 129
|
|
{ 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSE32_V_M1_MASK }, // 130
|
|
{ 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSE32_V_M2_MASK }, // 131
|
|
{ 0x1, 0x1, 0x0, 0x5, 0x2, PseudoVLSE32_V_M4_MASK }, // 132
|
|
{ 0x1, 0x1, 0x0, 0x5, 0x3, PseudoVLSE32_V_M8_MASK }, // 133
|
|
{ 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSE32_V_MF2_MASK }, // 134
|
|
{ 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSE64_V_M1_MASK }, // 135
|
|
{ 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSE64_V_M2_MASK }, // 136
|
|
{ 0x1, 0x1, 0x0, 0x6, 0x2, PseudoVLSE64_V_M4_MASK }, // 137
|
|
{ 0x1, 0x1, 0x0, 0x6, 0x3, PseudoVLSE64_V_M8_MASK }, // 138
|
|
};
|
|
|
|
const RISCV_VLEPseudo *RISCV_getVLEPseudo(uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedStridedFFLog2SEWLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVLETable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVLSEGTable_IMPL
|
|
static const RISCV_VLSEGPseudo RISCVVLSEGTable[] = {
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG2E8_V_M1 }, // 0
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG2E8_V_M2 }, // 1
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x3, 0x2, PseudoVLSEG2E8_V_M4 }, // 2
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG2E8_V_MF8 }, // 3
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG2E8_V_MF4 }, // 4
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG2E8_V_MF2 }, // 5
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG2E16_V_M1 }, // 6
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG2E16_V_M2 }, // 7
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x4, 0x2, PseudoVLSEG2E16_V_M4 }, // 8
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG2E16_V_MF4 }, // 9
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG2E16_V_MF2 }, // 10
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG2E32_V_M1 }, // 11
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG2E32_V_M2 }, // 12
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x5, 0x2, PseudoVLSEG2E32_V_M4 }, // 13
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG2E32_V_MF2 }, // 14
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG2E64_V_M1 }, // 15
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG2E64_V_M2 }, // 16
|
|
{ 0x2, 0x0, 0x0, 0x0, 0x6, 0x2, PseudoVLSEG2E64_V_M4 }, // 17
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG2E8FF_V_M1 }, // 18
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG2E8FF_V_M2 }, // 19
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x3, 0x2, PseudoVLSEG2E8FF_V_M4 }, // 20
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG2E8FF_V_MF8 }, // 21
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG2E8FF_V_MF4 }, // 22
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG2E8FF_V_MF2 }, // 23
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG2E16FF_V_M1 }, // 24
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG2E16FF_V_M2 }, // 25
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x4, 0x2, PseudoVLSEG2E16FF_V_M4 }, // 26
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG2E16FF_V_MF4 }, // 27
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG2E16FF_V_MF2 }, // 28
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG2E32FF_V_M1 }, // 29
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG2E32FF_V_M2 }, // 30
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x5, 0x2, PseudoVLSEG2E32FF_V_M4 }, // 31
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG2E32FF_V_MF2 }, // 32
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG2E64FF_V_M1 }, // 33
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG2E64FF_V_M2 }, // 34
|
|
{ 0x2, 0x0, 0x0, 0x1, 0x6, 0x2, PseudoVLSEG2E64FF_V_M4 }, // 35
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG2E8_V_M1 }, // 36
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG2E8_V_M2 }, // 37
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x3, 0x2, PseudoVLSSEG2E8_V_M4 }, // 38
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG2E8_V_MF8 }, // 39
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG2E8_V_MF4 }, // 40
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG2E8_V_MF2 }, // 41
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG2E16_V_M1 }, // 42
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG2E16_V_M2 }, // 43
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x4, 0x2, PseudoVLSSEG2E16_V_M4 }, // 44
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG2E16_V_MF4 }, // 45
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG2E16_V_MF2 }, // 46
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG2E32_V_M1 }, // 47
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG2E32_V_M2 }, // 48
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x5, 0x2, PseudoVLSSEG2E32_V_M4 }, // 49
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG2E32_V_MF2 }, // 50
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG2E64_V_M1 }, // 51
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG2E64_V_M2 }, // 52
|
|
{ 0x2, 0x0, 0x1, 0x0, 0x6, 0x2, PseudoVLSSEG2E64_V_M4 }, // 53
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG2E8_V_M1_MASK }, // 54
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG2E8_V_M2_MASK }, // 55
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x3, 0x2, PseudoVLSEG2E8_V_M4_MASK }, // 56
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG2E8_V_MF8_MASK }, // 57
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG2E8_V_MF4_MASK }, // 58
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG2E8_V_MF2_MASK }, // 59
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG2E16_V_M1_MASK }, // 60
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG2E16_V_M2_MASK }, // 61
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x4, 0x2, PseudoVLSEG2E16_V_M4_MASK }, // 62
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG2E16_V_MF4_MASK }, // 63
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG2E16_V_MF2_MASK }, // 64
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG2E32_V_M1_MASK }, // 65
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG2E32_V_M2_MASK }, // 66
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x5, 0x2, PseudoVLSEG2E32_V_M4_MASK }, // 67
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG2E32_V_MF2_MASK }, // 68
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG2E64_V_M1_MASK }, // 69
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG2E64_V_M2_MASK }, // 70
|
|
{ 0x2, 0x1, 0x0, 0x0, 0x6, 0x2, PseudoVLSEG2E64_V_M4_MASK }, // 71
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG2E8FF_V_M1_MASK }, // 72
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG2E8FF_V_M2_MASK }, // 73
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x3, 0x2, PseudoVLSEG2E8FF_V_M4_MASK }, // 74
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG2E8FF_V_MF8_MASK }, // 75
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG2E8FF_V_MF4_MASK }, // 76
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG2E8FF_V_MF2_MASK }, // 77
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG2E16FF_V_M1_MASK }, // 78
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG2E16FF_V_M2_MASK }, // 79
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x4, 0x2, PseudoVLSEG2E16FF_V_M4_MASK }, // 80
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG2E16FF_V_MF4_MASK }, // 81
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG2E16FF_V_MF2_MASK }, // 82
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG2E32FF_V_M1_MASK }, // 83
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG2E32FF_V_M2_MASK }, // 84
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x5, 0x2, PseudoVLSEG2E32FF_V_M4_MASK }, // 85
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG2E32FF_V_MF2_MASK }, // 86
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG2E64FF_V_M1_MASK }, // 87
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG2E64FF_V_M2_MASK }, // 88
|
|
{ 0x2, 0x1, 0x0, 0x1, 0x6, 0x2, PseudoVLSEG2E64FF_V_M4_MASK }, // 89
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG2E8_V_M1_MASK }, // 90
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG2E8_V_M2_MASK }, // 91
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x3, 0x2, PseudoVLSSEG2E8_V_M4_MASK }, // 92
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG2E8_V_MF8_MASK }, // 93
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG2E8_V_MF4_MASK }, // 94
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG2E8_V_MF2_MASK }, // 95
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG2E16_V_M1_MASK }, // 96
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG2E16_V_M2_MASK }, // 97
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x4, 0x2, PseudoVLSSEG2E16_V_M4_MASK }, // 98
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG2E16_V_MF4_MASK }, // 99
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG2E16_V_MF2_MASK }, // 100
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG2E32_V_M1_MASK }, // 101
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG2E32_V_M2_MASK }, // 102
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x5, 0x2, PseudoVLSSEG2E32_V_M4_MASK }, // 103
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG2E32_V_MF2_MASK }, // 104
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG2E64_V_M1_MASK }, // 105
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG2E64_V_M2_MASK }, // 106
|
|
{ 0x2, 0x1, 0x1, 0x0, 0x6, 0x2, PseudoVLSSEG2E64_V_M4_MASK }, // 107
|
|
{ 0x3, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG3E8_V_M1 }, // 108
|
|
{ 0x3, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG3E8_V_M2 }, // 109
|
|
{ 0x3, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG3E8_V_MF8 }, // 110
|
|
{ 0x3, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG3E8_V_MF4 }, // 111
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{ 0x3, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG3E8_V_MF2 }, // 112
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{ 0x3, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG3E16_V_M1 }, // 113
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{ 0x3, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG3E16_V_M2 }, // 114
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{ 0x3, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG3E16_V_MF4 }, // 115
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{ 0x3, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG3E16_V_MF2 }, // 116
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{ 0x3, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG3E32_V_M1 }, // 117
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{ 0x3, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG3E32_V_M2 }, // 118
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{ 0x3, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG3E32_V_MF2 }, // 119
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{ 0x3, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG3E64_V_M1 }, // 120
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{ 0x3, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG3E64_V_M2 }, // 121
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{ 0x3, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG3E8FF_V_M1 }, // 122
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{ 0x3, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG3E8FF_V_M2 }, // 123
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{ 0x3, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG3E8FF_V_MF8 }, // 124
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{ 0x3, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG3E8FF_V_MF4 }, // 125
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{ 0x3, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG3E8FF_V_MF2 }, // 126
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{ 0x3, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG3E16FF_V_M1 }, // 127
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{ 0x3, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG3E16FF_V_M2 }, // 128
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{ 0x3, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG3E16FF_V_MF4 }, // 129
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{ 0x3, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG3E16FF_V_MF2 }, // 130
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{ 0x3, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG3E32FF_V_M1 }, // 131
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{ 0x3, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG3E32FF_V_M2 }, // 132
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{ 0x3, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG3E32FF_V_MF2 }, // 133
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{ 0x3, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG3E64FF_V_M1 }, // 134
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{ 0x3, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG3E64FF_V_M2 }, // 135
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{ 0x3, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG3E8_V_M1 }, // 136
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{ 0x3, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG3E8_V_M2 }, // 137
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{ 0x3, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG3E8_V_MF8 }, // 138
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{ 0x3, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG3E8_V_MF4 }, // 139
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{ 0x3, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG3E8_V_MF2 }, // 140
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{ 0x3, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG3E16_V_M1 }, // 141
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{ 0x3, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG3E16_V_M2 }, // 142
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{ 0x3, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG3E16_V_MF4 }, // 143
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{ 0x3, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG3E16_V_MF2 }, // 144
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{ 0x3, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG3E32_V_M1 }, // 145
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{ 0x3, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG3E32_V_M2 }, // 146
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{ 0x3, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG3E32_V_MF2 }, // 147
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{ 0x3, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG3E64_V_M1 }, // 148
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{ 0x3, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG3E64_V_M2 }, // 149
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{ 0x3, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG3E8_V_M1_MASK }, // 150
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{ 0x3, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG3E8_V_M2_MASK }, // 151
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{ 0x3, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG3E8_V_MF8_MASK }, // 152
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{ 0x3, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG3E8_V_MF4_MASK }, // 153
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{ 0x3, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG3E8_V_MF2_MASK }, // 154
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{ 0x3, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG3E16_V_M1_MASK }, // 155
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{ 0x3, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG3E16_V_M2_MASK }, // 156
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{ 0x3, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG3E16_V_MF4_MASK }, // 157
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{ 0x3, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG3E16_V_MF2_MASK }, // 158
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{ 0x3, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG3E32_V_M1_MASK }, // 159
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{ 0x3, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG3E32_V_M2_MASK }, // 160
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{ 0x3, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG3E32_V_MF2_MASK }, // 161
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{ 0x3, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG3E64_V_M1_MASK }, // 162
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{ 0x3, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG3E64_V_M2_MASK }, // 163
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{ 0x3, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG3E8FF_V_M1_MASK }, // 164
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{ 0x3, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG3E8FF_V_M2_MASK }, // 165
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{ 0x3, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG3E8FF_V_MF8_MASK }, // 166
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{ 0x3, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG3E8FF_V_MF4_MASK }, // 167
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{ 0x3, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG3E8FF_V_MF2_MASK }, // 168
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{ 0x3, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG3E16FF_V_M1_MASK }, // 169
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{ 0x3, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG3E16FF_V_M2_MASK }, // 170
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{ 0x3, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG3E16FF_V_MF4_MASK }, // 171
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{ 0x3, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG3E16FF_V_MF2_MASK }, // 172
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{ 0x3, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG3E32FF_V_M1_MASK }, // 173
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{ 0x3, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG3E32FF_V_M2_MASK }, // 174
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{ 0x3, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG3E32FF_V_MF2_MASK }, // 175
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{ 0x3, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG3E64FF_V_M1_MASK }, // 176
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{ 0x3, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG3E64FF_V_M2_MASK }, // 177
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{ 0x3, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG3E8_V_M1_MASK }, // 178
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{ 0x3, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG3E8_V_M2_MASK }, // 179
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{ 0x3, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG3E8_V_MF8_MASK }, // 180
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{ 0x3, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG3E8_V_MF4_MASK }, // 181
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{ 0x3, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG3E8_V_MF2_MASK }, // 182
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{ 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG3E16_V_M1_MASK }, // 183
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{ 0x3, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG3E16_V_M2_MASK }, // 184
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{ 0x3, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG3E16_V_MF4_MASK }, // 185
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{ 0x3, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG3E16_V_MF2_MASK }, // 186
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{ 0x3, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG3E32_V_M1_MASK }, // 187
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{ 0x3, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG3E32_V_M2_MASK }, // 188
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{ 0x3, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG3E32_V_MF2_MASK }, // 189
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{ 0x3, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG3E64_V_M1_MASK }, // 190
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{ 0x3, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG3E64_V_M2_MASK }, // 191
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{ 0x4, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG4E8_V_M1 }, // 192
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{ 0x4, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG4E8_V_M2 }, // 193
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|
{ 0x4, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG4E8_V_MF8 }, // 194
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{ 0x4, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG4E8_V_MF4 }, // 195
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{ 0x4, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG4E8_V_MF2 }, // 196
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|
{ 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG4E16_V_M1 }, // 197
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{ 0x4, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG4E16_V_M2 }, // 198
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|
{ 0x4, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG4E16_V_MF4 }, // 199
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|
{ 0x4, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG4E16_V_MF2 }, // 200
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|
{ 0x4, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG4E32_V_M1 }, // 201
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|
{ 0x4, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG4E32_V_M2 }, // 202
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|
{ 0x4, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG4E32_V_MF2 }, // 203
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|
{ 0x4, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG4E64_V_M1 }, // 204
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|
{ 0x4, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG4E64_V_M2 }, // 205
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|
{ 0x4, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG4E8FF_V_M1 }, // 206
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|
{ 0x4, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG4E8FF_V_M2 }, // 207
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|
{ 0x4, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG4E8FF_V_MF8 }, // 208
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|
{ 0x4, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG4E8FF_V_MF4 }, // 209
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|
{ 0x4, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG4E8FF_V_MF2 }, // 210
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|
{ 0x4, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG4E16FF_V_M1 }, // 211
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|
{ 0x4, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG4E16FF_V_M2 }, // 212
|
|
{ 0x4, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG4E16FF_V_MF4 }, // 213
|
|
{ 0x4, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG4E16FF_V_MF2 }, // 214
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|
{ 0x4, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG4E32FF_V_M1 }, // 215
|
|
{ 0x4, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG4E32FF_V_M2 }, // 216
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|
{ 0x4, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG4E32FF_V_MF2 }, // 217
|
|
{ 0x4, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG4E64FF_V_M1 }, // 218
|
|
{ 0x4, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG4E64FF_V_M2 }, // 219
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG4E8_V_M1 }, // 220
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG4E8_V_M2 }, // 221
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG4E8_V_MF8 }, // 222
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG4E8_V_MF4 }, // 223
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG4E8_V_MF2 }, // 224
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG4E16_V_M1 }, // 225
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG4E16_V_M2 }, // 226
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG4E16_V_MF4 }, // 227
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG4E16_V_MF2 }, // 228
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG4E32_V_M1 }, // 229
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG4E32_V_M2 }, // 230
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG4E32_V_MF2 }, // 231
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG4E64_V_M1 }, // 232
|
|
{ 0x4, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG4E64_V_M2 }, // 233
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG4E8_V_M1_MASK }, // 234
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG4E8_V_M2_MASK }, // 235
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG4E8_V_MF8_MASK }, // 236
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG4E8_V_MF4_MASK }, // 237
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG4E8_V_MF2_MASK }, // 238
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG4E16_V_M1_MASK }, // 239
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG4E16_V_M2_MASK }, // 240
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG4E16_V_MF4_MASK }, // 241
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG4E16_V_MF2_MASK }, // 242
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG4E32_V_M1_MASK }, // 243
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG4E32_V_M2_MASK }, // 244
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG4E32_V_MF2_MASK }, // 245
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG4E64_V_M1_MASK }, // 246
|
|
{ 0x4, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG4E64_V_M2_MASK }, // 247
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG4E8FF_V_M1_MASK }, // 248
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG4E8FF_V_M2_MASK }, // 249
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG4E8FF_V_MF8_MASK }, // 250
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG4E8FF_V_MF4_MASK }, // 251
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG4E8FF_V_MF2_MASK }, // 252
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG4E16FF_V_M1_MASK }, // 253
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG4E16FF_V_M2_MASK }, // 254
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG4E16FF_V_MF4_MASK }, // 255
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG4E16FF_V_MF2_MASK }, // 256
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG4E32FF_V_M1_MASK }, // 257
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG4E32FF_V_M2_MASK }, // 258
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG4E32FF_V_MF2_MASK }, // 259
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG4E64FF_V_M1_MASK }, // 260
|
|
{ 0x4, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG4E64FF_V_M2_MASK }, // 261
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG4E8_V_M1_MASK }, // 262
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG4E8_V_M2_MASK }, // 263
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG4E8_V_MF8_MASK }, // 264
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG4E8_V_MF4_MASK }, // 265
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG4E8_V_MF2_MASK }, // 266
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG4E16_V_M1_MASK }, // 267
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG4E16_V_M2_MASK }, // 268
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG4E16_V_MF4_MASK }, // 269
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG4E16_V_MF2_MASK }, // 270
|
|
{ 0x4, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG4E32_V_M1_MASK }, // 271
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|
{ 0x4, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG4E32_V_M2_MASK }, // 272
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{ 0x4, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG4E32_V_MF2_MASK }, // 273
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{ 0x4, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG4E64_V_M1_MASK }, // 274
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{ 0x4, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG4E64_V_M2_MASK }, // 275
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{ 0x5, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG5E8_V_M1 }, // 276
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{ 0x5, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG5E8_V_MF8 }, // 277
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{ 0x5, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG5E8_V_MF4 }, // 278
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{ 0x5, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG5E8_V_MF2 }, // 279
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{ 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG5E16_V_M1 }, // 280
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{ 0x5, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG5E16_V_MF4 }, // 281
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{ 0x5, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG5E16_V_MF2 }, // 282
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{ 0x5, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG5E32_V_M1 }, // 283
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{ 0x5, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG5E32_V_MF2 }, // 284
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{ 0x5, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG5E64_V_M1 }, // 285
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{ 0x5, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG5E8FF_V_M1 }, // 286
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{ 0x5, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG5E8FF_V_MF8 }, // 287
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{ 0x5, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG5E8FF_V_MF4 }, // 288
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{ 0x5, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG5E8FF_V_MF2 }, // 289
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{ 0x5, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG5E16FF_V_M1 }, // 290
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{ 0x5, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG5E16FF_V_MF4 }, // 291
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{ 0x5, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG5E16FF_V_MF2 }, // 292
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{ 0x5, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG5E32FF_V_M1 }, // 293
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{ 0x5, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG5E32FF_V_MF2 }, // 294
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{ 0x5, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG5E64FF_V_M1 }, // 295
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{ 0x5, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG5E8_V_M1 }, // 296
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{ 0x5, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG5E8_V_MF8 }, // 297
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{ 0x5, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG5E8_V_MF4 }, // 298
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{ 0x5, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG5E8_V_MF2 }, // 299
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{ 0x5, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG5E16_V_M1 }, // 300
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{ 0x5, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG5E16_V_MF4 }, // 301
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{ 0x5, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG5E16_V_MF2 }, // 302
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{ 0x5, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG5E32_V_M1 }, // 303
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{ 0x5, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG5E32_V_MF2 }, // 304
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{ 0x5, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG5E64_V_M1 }, // 305
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{ 0x5, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG5E8_V_M1_MASK }, // 306
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|
{ 0x5, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG5E8_V_MF8_MASK }, // 307
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{ 0x5, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG5E8_V_MF4_MASK }, // 308
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|
{ 0x5, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG5E8_V_MF2_MASK }, // 309
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{ 0x5, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG5E16_V_M1_MASK }, // 310
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|
{ 0x5, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG5E16_V_MF4_MASK }, // 311
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|
{ 0x5, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG5E16_V_MF2_MASK }, // 312
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|
{ 0x5, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG5E32_V_M1_MASK }, // 313
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{ 0x5, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG5E32_V_MF2_MASK }, // 314
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|
{ 0x5, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG5E64_V_M1_MASK }, // 315
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|
{ 0x5, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG5E8FF_V_M1_MASK }, // 316
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|
{ 0x5, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG5E8FF_V_MF8_MASK }, // 317
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{ 0x5, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG5E8FF_V_MF4_MASK }, // 318
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|
{ 0x5, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG5E8FF_V_MF2_MASK }, // 319
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|
{ 0x5, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG5E16FF_V_M1_MASK }, // 320
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|
{ 0x5, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG5E16FF_V_MF4_MASK }, // 321
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|
{ 0x5, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG5E16FF_V_MF2_MASK }, // 322
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|
{ 0x5, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG5E32FF_V_M1_MASK }, // 323
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|
{ 0x5, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG5E32FF_V_MF2_MASK }, // 324
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|
{ 0x5, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG5E64FF_V_M1_MASK }, // 325
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|
{ 0x5, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG5E8_V_M1_MASK }, // 326
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|
{ 0x5, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG5E8_V_MF8_MASK }, // 327
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|
{ 0x5, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG5E8_V_MF4_MASK }, // 328
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|
{ 0x5, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG5E8_V_MF2_MASK }, // 329
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|
{ 0x5, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG5E16_V_M1_MASK }, // 330
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|
{ 0x5, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG5E16_V_MF4_MASK }, // 331
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|
{ 0x5, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG5E16_V_MF2_MASK }, // 332
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|
{ 0x5, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG5E32_V_M1_MASK }, // 333
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|
{ 0x5, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG5E32_V_MF2_MASK }, // 334
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|
{ 0x5, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG5E64_V_M1_MASK }, // 335
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|
{ 0x6, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG6E8_V_M1 }, // 336
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|
{ 0x6, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG6E8_V_MF8 }, // 337
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|
{ 0x6, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG6E8_V_MF4 }, // 338
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|
{ 0x6, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG6E8_V_MF2 }, // 339
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|
{ 0x6, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG6E16_V_M1 }, // 340
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|
{ 0x6, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG6E16_V_MF4 }, // 341
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|
{ 0x6, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG6E16_V_MF2 }, // 342
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|
{ 0x6, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG6E32_V_M1 }, // 343
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|
{ 0x6, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG6E32_V_MF2 }, // 344
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|
{ 0x6, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG6E64_V_M1 }, // 345
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|
{ 0x6, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG6E8FF_V_M1 }, // 346
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|
{ 0x6, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG6E8FF_V_MF8 }, // 347
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|
{ 0x6, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG6E8FF_V_MF4 }, // 348
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|
{ 0x6, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG6E8FF_V_MF2 }, // 349
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|
{ 0x6, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG6E16FF_V_M1 }, // 350
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|
{ 0x6, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG6E16FF_V_MF4 }, // 351
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|
{ 0x6, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG6E16FF_V_MF2 }, // 352
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|
{ 0x6, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG6E32FF_V_M1 }, // 353
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|
{ 0x6, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG6E32FF_V_MF2 }, // 354
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|
{ 0x6, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG6E64FF_V_M1 }, // 355
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|
{ 0x6, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG6E8_V_M1 }, // 356
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|
{ 0x6, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG6E8_V_MF8 }, // 357
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG6E8_V_MF4 }, // 358
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|
{ 0x6, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG6E8_V_MF2 }, // 359
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG6E16_V_M1 }, // 360
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG6E16_V_MF4 }, // 361
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG6E16_V_MF2 }, // 362
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG6E32_V_M1 }, // 363
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG6E32_V_MF2 }, // 364
|
|
{ 0x6, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG6E64_V_M1 }, // 365
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG6E8_V_M1_MASK }, // 366
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG6E8_V_MF8_MASK }, // 367
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG6E8_V_MF4_MASK }, // 368
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG6E8_V_MF2_MASK }, // 369
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG6E16_V_M1_MASK }, // 370
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG6E16_V_MF4_MASK }, // 371
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG6E16_V_MF2_MASK }, // 372
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG6E32_V_M1_MASK }, // 373
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG6E32_V_MF2_MASK }, // 374
|
|
{ 0x6, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG6E64_V_M1_MASK }, // 375
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG6E8FF_V_M1_MASK }, // 376
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG6E8FF_V_MF8_MASK }, // 377
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG6E8FF_V_MF4_MASK }, // 378
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG6E8FF_V_MF2_MASK }, // 379
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG6E16FF_V_M1_MASK }, // 380
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG6E16FF_V_MF4_MASK }, // 381
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG6E16FF_V_MF2_MASK }, // 382
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG6E32FF_V_M1_MASK }, // 383
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG6E32FF_V_MF2_MASK }, // 384
|
|
{ 0x6, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG6E64FF_V_M1_MASK }, // 385
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG6E8_V_M1_MASK }, // 386
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG6E8_V_MF8_MASK }, // 387
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG6E8_V_MF4_MASK }, // 388
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG6E8_V_MF2_MASK }, // 389
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG6E16_V_M1_MASK }, // 390
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG6E16_V_MF4_MASK }, // 391
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG6E16_V_MF2_MASK }, // 392
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG6E32_V_M1_MASK }, // 393
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG6E32_V_MF2_MASK }, // 394
|
|
{ 0x6, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG6E64_V_M1_MASK }, // 395
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG7E8_V_M1 }, // 396
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG7E8_V_MF8 }, // 397
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG7E8_V_MF4 }, // 398
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG7E8_V_MF2 }, // 399
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG7E16_V_M1 }, // 400
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG7E16_V_MF4 }, // 401
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG7E16_V_MF2 }, // 402
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG7E32_V_M1 }, // 403
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG7E32_V_MF2 }, // 404
|
|
{ 0x7, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG7E64_V_M1 }, // 405
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG7E8FF_V_M1 }, // 406
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG7E8FF_V_MF8 }, // 407
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG7E8FF_V_MF4 }, // 408
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG7E8FF_V_MF2 }, // 409
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG7E16FF_V_M1 }, // 410
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG7E16FF_V_MF4 }, // 411
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG7E16FF_V_MF2 }, // 412
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG7E32FF_V_M1 }, // 413
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG7E32FF_V_MF2 }, // 414
|
|
{ 0x7, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG7E64FF_V_M1 }, // 415
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG7E8_V_M1 }, // 416
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG7E8_V_MF8 }, // 417
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG7E8_V_MF4 }, // 418
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG7E8_V_MF2 }, // 419
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG7E16_V_M1 }, // 420
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG7E16_V_MF4 }, // 421
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG7E16_V_MF2 }, // 422
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG7E32_V_M1 }, // 423
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG7E32_V_MF2 }, // 424
|
|
{ 0x7, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG7E64_V_M1 }, // 425
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG7E8_V_M1_MASK }, // 426
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG7E8_V_MF8_MASK }, // 427
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG7E8_V_MF4_MASK }, // 428
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG7E8_V_MF2_MASK }, // 429
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG7E16_V_M1_MASK }, // 430
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG7E16_V_MF4_MASK }, // 431
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG7E16_V_MF2_MASK }, // 432
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG7E32_V_M1_MASK }, // 433
|
|
{ 0x7, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG7E32_V_MF2_MASK }, // 434
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|
{ 0x7, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG7E64_V_M1_MASK }, // 435
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|
{ 0x7, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG7E8FF_V_M1_MASK }, // 436
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|
{ 0x7, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG7E8FF_V_MF8_MASK }, // 437
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|
{ 0x7, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG7E8FF_V_MF4_MASK }, // 438
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{ 0x7, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG7E8FF_V_MF2_MASK }, // 439
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{ 0x7, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG7E16FF_V_M1_MASK }, // 440
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{ 0x7, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG7E16FF_V_MF4_MASK }, // 441
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{ 0x7, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG7E16FF_V_MF2_MASK }, // 442
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{ 0x7, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG7E32FF_V_M1_MASK }, // 443
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{ 0x7, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG7E32FF_V_MF2_MASK }, // 444
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{ 0x7, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG7E64FF_V_M1_MASK }, // 445
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{ 0x7, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG7E8_V_M1_MASK }, // 446
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{ 0x7, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG7E8_V_MF8_MASK }, // 447
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{ 0x7, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG7E8_V_MF4_MASK }, // 448
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{ 0x7, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG7E8_V_MF2_MASK }, // 449
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{ 0x7, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG7E16_V_M1_MASK }, // 450
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{ 0x7, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG7E16_V_MF4_MASK }, // 451
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{ 0x7, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG7E16_V_MF2_MASK }, // 452
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|
{ 0x7, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG7E32_V_M1_MASK }, // 453
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|
{ 0x7, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG7E32_V_MF2_MASK }, // 454
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|
{ 0x7, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG7E64_V_M1_MASK }, // 455
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|
{ 0x8, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG8E8_V_M1 }, // 456
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{ 0x8, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG8E8_V_MF8 }, // 457
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{ 0x8, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG8E8_V_MF4 }, // 458
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{ 0x8, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG8E8_V_MF2 }, // 459
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{ 0x8, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG8E16_V_M1 }, // 460
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{ 0x8, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG8E16_V_MF4 }, // 461
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{ 0x8, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG8E16_V_MF2 }, // 462
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|
{ 0x8, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG8E32_V_M1 }, // 463
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|
{ 0x8, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG8E32_V_MF2 }, // 464
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|
{ 0x8, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG8E64_V_M1 }, // 465
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|
{ 0x8, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG8E8FF_V_M1 }, // 466
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|
{ 0x8, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG8E8FF_V_MF8 }, // 467
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|
{ 0x8, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG8E8FF_V_MF4 }, // 468
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|
{ 0x8, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG8E8FF_V_MF2 }, // 469
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|
{ 0x8, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG8E16FF_V_M1 }, // 470
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|
{ 0x8, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG8E16FF_V_MF4 }, // 471
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|
{ 0x8, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG8E16FF_V_MF2 }, // 472
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|
{ 0x8, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG8E32FF_V_M1 }, // 473
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|
{ 0x8, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG8E32FF_V_MF2 }, // 474
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|
{ 0x8, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG8E64FF_V_M1 }, // 475
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|
{ 0x8, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG8E8_V_M1 }, // 476
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|
{ 0x8, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG8E8_V_MF8 }, // 477
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|
{ 0x8, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG8E8_V_MF4 }, // 478
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|
{ 0x8, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG8E8_V_MF2 }, // 479
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|
{ 0x8, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG8E16_V_M1 }, // 480
|
|
{ 0x8, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG8E16_V_MF4 }, // 481
|
|
{ 0x8, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG8E16_V_MF2 }, // 482
|
|
{ 0x8, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG8E32_V_M1 }, // 483
|
|
{ 0x8, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG8E32_V_MF2 }, // 484
|
|
{ 0x8, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG8E64_V_M1 }, // 485
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG8E8_V_M1_MASK }, // 486
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG8E8_V_MF8_MASK }, // 487
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG8E8_V_MF4_MASK }, // 488
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG8E8_V_MF2_MASK }, // 489
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG8E16_V_M1_MASK }, // 490
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG8E16_V_MF4_MASK }, // 491
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG8E16_V_MF2_MASK }, // 492
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG8E32_V_M1_MASK }, // 493
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG8E32_V_MF2_MASK }, // 494
|
|
{ 0x8, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG8E64_V_M1_MASK }, // 495
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG8E8FF_V_M1_MASK }, // 496
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG8E8FF_V_MF8_MASK }, // 497
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG8E8FF_V_MF4_MASK }, // 498
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG8E8FF_V_MF2_MASK }, // 499
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG8E16FF_V_M1_MASK }, // 500
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG8E16FF_V_MF4_MASK }, // 501
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG8E16FF_V_MF2_MASK }, // 502
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG8E32FF_V_M1_MASK }, // 503
|
|
{ 0x8, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG8E32FF_V_MF2_MASK }, // 504
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|
{ 0x8, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG8E64FF_V_M1_MASK }, // 505
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|
{ 0x8, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG8E8_V_M1_MASK }, // 506
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|
{ 0x8, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG8E8_V_MF8_MASK }, // 507
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|
{ 0x8, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG8E8_V_MF4_MASK }, // 508
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|
{ 0x8, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG8E8_V_MF2_MASK }, // 509
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|
{ 0x8, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG8E16_V_M1_MASK }, // 510
|
|
{ 0x8, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG8E16_V_MF4_MASK }, // 511
|
|
{ 0x8, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG8E16_V_MF2_MASK }, // 512
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|
{ 0x8, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG8E32_V_M1_MASK }, // 513
|
|
{ 0x8, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG8E32_V_MF2_MASK }, // 514
|
|
{ 0x8, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG8E64_V_M1_MASK }, // 515
|
|
};
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|
const RISCV_VLSEGPseudo *RISCV_getVLSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedStridedFFLog2SEWLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVLSEGTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVLXSEGTable_IMPL
|
|
static const RISCV_VLXSEGPseudo RISCVVLXSEGTable[] = {
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|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG2EI8_V_M1_M1 }, // 0
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG2EI8_V_MF8_M1 }, // 1
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG2EI8_V_MF4_M1 }, // 2
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG2EI8_V_MF2_M1 }, // 3
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG2EI8_V_M1_M2 }, // 4
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG2EI8_V_M2_M2 }, // 5
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG2EI8_V_MF4_M2 }, // 6
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG2EI8_V_MF2_M2 }, // 7
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVLUXSEG2EI8_V_M1_M4 }, // 8
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVLUXSEG2EI8_V_M2_M4 }, // 9
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVLUXSEG2EI8_V_M4_M4 }, // 10
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVLUXSEG2EI8_V_MF2_M4 }, // 11
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF8 }, // 12
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF4 }, // 13
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF4 }, // 14
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF2 }, // 15
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF2 }, // 16
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG2EI8_V_MF2_MF2 }, // 17
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG2EI16_V_M1_M1 }, // 18
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG2EI16_V_M2_M1 }, // 19
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG2EI16_V_MF4_M1 }, // 20
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG2EI16_V_MF2_M1 }, // 21
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG2EI16_V_M1_M2 }, // 22
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG2EI16_V_M2_M2 }, // 23
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG2EI16_V_M4_M2 }, // 24
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG2EI16_V_MF2_M2 }, // 25
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVLUXSEG2EI16_V_M1_M4 }, // 26
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVLUXSEG2EI16_V_M2_M4 }, // 27
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVLUXSEG2EI16_V_M4_M4 }, // 28
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVLUXSEG2EI16_V_M8_M4 }, // 29
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF8 }, // 30
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF4 }, // 31
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF4 }, // 32
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG2EI16_V_M1_MF2 }, // 33
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF2 }, // 34
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF2 }, // 35
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG2EI32_V_M1_M1 }, // 36
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG2EI32_V_M2_M1 }, // 37
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG2EI32_V_M4_M1 }, // 38
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG2EI32_V_MF2_M1 }, // 39
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG2EI32_V_M1_M2 }, // 40
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG2EI32_V_M2_M2 }, // 41
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG2EI32_V_M4_M2 }, // 42
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG2EI32_V_M8_M2 }, // 43
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVLUXSEG2EI32_V_M2_M4 }, // 44
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVLUXSEG2EI32_V_M4_M4 }, // 45
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVLUXSEG2EI32_V_M8_M4 }, // 46
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF8 }, // 47
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG2EI32_V_M1_MF4 }, // 48
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF4 }, // 49
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG2EI32_V_M1_MF2 }, // 50
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG2EI32_V_M2_MF2 }, // 51
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF2 }, // 52
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG2EI64_V_M1_M1 }, // 53
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG2EI64_V_M2_M1 }, // 54
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG2EI64_V_M4_M1 }, // 55
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG2EI64_V_M8_M1 }, // 56
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG2EI64_V_M2_M2 }, // 57
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG2EI64_V_M4_M2 }, // 58
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG2EI64_V_M8_M2 }, // 59
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVLUXSEG2EI64_V_M4_M4 }, // 60
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVLUXSEG2EI64_V_M8_M4 }, // 61
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG2EI64_V_M1_MF8 }, // 62
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG2EI64_V_M1_MF4 }, // 63
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG2EI64_V_M2_MF4 }, // 64
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG2EI64_V_M1_MF2 }, // 65
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG2EI64_V_M2_MF2 }, // 66
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG2EI64_V_M4_MF2 }, // 67
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG2EI8_V_M1_M1 }, // 68
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{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG2EI8_V_MF8_M1 }, // 69
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{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG2EI8_V_MF4_M1 }, // 70
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{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG2EI8_V_MF2_M1 }, // 71
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{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG2EI8_V_M1_M2 }, // 72
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{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG2EI8_V_M2_M2 }, // 73
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{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG2EI8_V_MF4_M2 }, // 74
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{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG2EI8_V_MF2_M2 }, // 75
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{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVLOXSEG2EI8_V_M1_M4 }, // 76
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{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVLOXSEG2EI8_V_M2_M4 }, // 77
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{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVLOXSEG2EI8_V_M4_M4 }, // 78
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{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVLOXSEG2EI8_V_MF2_M4 }, // 79
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{ 0x2, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF8 }, // 80
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{ 0x2, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF4 }, // 81
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{ 0x2, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF4 }, // 82
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{ 0x2, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF2 }, // 83
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{ 0x2, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF2 }, // 84
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{ 0x2, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG2EI8_V_MF2_MF2 }, // 85
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{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG2EI16_V_M1_M1 }, // 86
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{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG2EI16_V_M2_M1 }, // 87
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{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG2EI16_V_MF4_M1 }, // 88
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{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG2EI16_V_MF2_M1 }, // 89
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{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG2EI16_V_M1_M2 }, // 90
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{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG2EI16_V_M2_M2 }, // 91
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{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG2EI16_V_M4_M2 }, // 92
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{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG2EI16_V_MF2_M2 }, // 93
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{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVLOXSEG2EI16_V_M1_M4 }, // 94
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{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVLOXSEG2EI16_V_M2_M4 }, // 95
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{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVLOXSEG2EI16_V_M4_M4 }, // 96
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{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVLOXSEG2EI16_V_M8_M4 }, // 97
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{ 0x2, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF8 }, // 98
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{ 0x2, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF4 }, // 99
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{ 0x2, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF4 }, // 100
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{ 0x2, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG2EI16_V_M1_MF2 }, // 101
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{ 0x2, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF2 }, // 102
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{ 0x2, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF2 }, // 103
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{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG2EI32_V_M1_M1 }, // 104
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{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG2EI32_V_M2_M1 }, // 105
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{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG2EI32_V_M4_M1 }, // 106
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{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG2EI32_V_MF2_M1 }, // 107
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG2EI32_V_M1_M2 }, // 108
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG2EI32_V_M2_M2 }, // 109
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG2EI32_V_M4_M2 }, // 110
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG2EI32_V_M8_M2 }, // 111
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{ 0x2, 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVLOXSEG2EI32_V_M2_M4 }, // 112
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{ 0x2, 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVLOXSEG2EI32_V_M4_M4 }, // 113
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{ 0x2, 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVLOXSEG2EI32_V_M8_M4 }, // 114
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{ 0x2, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF8 }, // 115
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{ 0x2, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG2EI32_V_M1_MF4 }, // 116
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{ 0x2, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF4 }, // 117
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{ 0x2, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG2EI32_V_M1_MF2 }, // 118
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{ 0x2, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG2EI32_V_M2_MF2 }, // 119
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{ 0x2, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF2 }, // 120
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG2EI64_V_M1_M1 }, // 121
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG2EI64_V_M2_M1 }, // 122
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG2EI64_V_M4_M1 }, // 123
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG2EI64_V_M8_M1 }, // 124
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{ 0x2, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG2EI64_V_M2_M2 }, // 125
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{ 0x2, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG2EI64_V_M4_M2 }, // 126
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{ 0x2, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG2EI64_V_M8_M2 }, // 127
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{ 0x2, 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVLOXSEG2EI64_V_M4_M4 }, // 128
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|
{ 0x2, 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVLOXSEG2EI64_V_M8_M4 }, // 129
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{ 0x2, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG2EI64_V_M1_MF8 }, // 130
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{ 0x2, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG2EI64_V_M1_MF4 }, // 131
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{ 0x2, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG2EI64_V_M2_MF4 }, // 132
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{ 0x2, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG2EI64_V_M1_MF2 }, // 133
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{ 0x2, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG2EI64_V_M2_MF2 }, // 134
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{ 0x2, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG2EI64_V_M4_MF2 }, // 135
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG2EI8_V_M1_M1_MASK }, // 136
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG2EI8_V_MF8_M1_MASK }, // 137
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG2EI8_V_MF4_M1_MASK }, // 138
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG2EI8_V_MF2_M1_MASK }, // 139
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG2EI8_V_M1_M2_MASK }, // 140
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG2EI8_V_M2_M2_MASK }, // 141
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG2EI8_V_MF4_M2_MASK }, // 142
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG2EI8_V_MF2_M2_MASK }, // 143
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVLUXSEG2EI8_V_M1_M4_MASK }, // 144
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVLUXSEG2EI8_V_M2_M4_MASK }, // 145
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVLUXSEG2EI8_V_M4_M4_MASK }, // 146
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVLUXSEG2EI8_V_MF2_M4_MASK }, // 147
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{ 0x2, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF8_MASK }, // 148
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{ 0x2, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF4_MASK }, // 149
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{ 0x2, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF4_MASK }, // 150
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{ 0x2, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF2_MASK }, // 151
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{ 0x2, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF2_MASK }, // 152
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{ 0x2, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG2EI8_V_MF2_MF2_MASK }, // 153
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG2EI16_V_M1_M1_MASK }, // 154
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG2EI16_V_M2_M1_MASK }, // 155
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG2EI16_V_MF4_M1_MASK }, // 156
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG2EI16_V_MF2_M1_MASK }, // 157
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG2EI16_V_M1_M2_MASK }, // 158
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG2EI16_V_M2_M2_MASK }, // 159
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG2EI16_V_M4_M2_MASK }, // 160
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG2EI16_V_MF2_M2_MASK }, // 161
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVLUXSEG2EI16_V_M1_M4_MASK }, // 162
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVLUXSEG2EI16_V_M2_M4_MASK }, // 163
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVLUXSEG2EI16_V_M4_M4_MASK }, // 164
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVLUXSEG2EI16_V_M8_M4_MASK }, // 165
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{ 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF8_MASK }, // 166
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{ 0x2, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF4_MASK }, // 167
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{ 0x2, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF4_MASK }, // 168
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{ 0x2, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG2EI16_V_M1_MF2_MASK }, // 169
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{ 0x2, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF2_MASK }, // 170
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{ 0x2, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF2_MASK }, // 171
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG2EI32_V_M1_M1_MASK }, // 172
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG2EI32_V_M2_M1_MASK }, // 173
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG2EI32_V_M4_M1_MASK }, // 174
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|
{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG2EI32_V_MF2_M1_MASK }, // 175
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|
{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG2EI32_V_M1_M2_MASK }, // 176
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG2EI32_V_M2_M2_MASK }, // 177
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG2EI32_V_M4_M2_MASK }, // 178
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG2EI32_V_M8_M2_MASK }, // 179
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{ 0x2, 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVLUXSEG2EI32_V_M2_M4_MASK }, // 180
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{ 0x2, 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVLUXSEG2EI32_V_M4_M4_MASK }, // 181
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{ 0x2, 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVLUXSEG2EI32_V_M8_M4_MASK }, // 182
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{ 0x2, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF8_MASK }, // 183
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{ 0x2, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG2EI32_V_M1_MF4_MASK }, // 184
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{ 0x2, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF4_MASK }, // 185
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{ 0x2, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG2EI32_V_M1_MF2_MASK }, // 186
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|
{ 0x2, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG2EI32_V_M2_MF2_MASK }, // 187
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{ 0x2, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF2_MASK }, // 188
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|
{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG2EI64_V_M1_M1_MASK }, // 189
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|
{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG2EI64_V_M2_M1_MASK }, // 190
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|
{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG2EI64_V_M4_M1_MASK }, // 191
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|
{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG2EI64_V_M8_M1_MASK }, // 192
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|
{ 0x2, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG2EI64_V_M2_M2_MASK }, // 193
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|
{ 0x2, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG2EI64_V_M4_M2_MASK }, // 194
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|
{ 0x2, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG2EI64_V_M8_M2_MASK }, // 195
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|
{ 0x2, 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVLUXSEG2EI64_V_M4_M4_MASK }, // 196
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|
{ 0x2, 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVLUXSEG2EI64_V_M8_M4_MASK }, // 197
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|
{ 0x2, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG2EI64_V_M1_MF8_MASK }, // 198
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|
{ 0x2, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG2EI64_V_M1_MF4_MASK }, // 199
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|
{ 0x2, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG2EI64_V_M2_MF4_MASK }, // 200
|
|
{ 0x2, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG2EI64_V_M1_MF2_MASK }, // 201
|
|
{ 0x2, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG2EI64_V_M2_MF2_MASK }, // 202
|
|
{ 0x2, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG2EI64_V_M4_MF2_MASK }, // 203
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|
{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG2EI8_V_M1_M1_MASK }, // 204
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|
{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG2EI8_V_MF8_M1_MASK }, // 205
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|
{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG2EI8_V_MF4_M1_MASK }, // 206
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|
{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG2EI8_V_MF2_M1_MASK }, // 207
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|
{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG2EI8_V_M1_M2_MASK }, // 208
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|
{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG2EI8_V_M2_M2_MASK }, // 209
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG2EI8_V_MF4_M2_MASK }, // 210
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG2EI8_V_MF2_M2_MASK }, // 211
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|
{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVLOXSEG2EI8_V_M1_M4_MASK }, // 212
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|
{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVLOXSEG2EI8_V_M2_M4_MASK }, // 213
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|
{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVLOXSEG2EI8_V_M4_M4_MASK }, // 214
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{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVLOXSEG2EI8_V_MF2_M4_MASK }, // 215
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{ 0x2, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF8_MASK }, // 216
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{ 0x2, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF4_MASK }, // 217
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{ 0x2, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF4_MASK }, // 218
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{ 0x2, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF2_MASK }, // 219
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{ 0x2, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF2_MASK }, // 220
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{ 0x2, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG2EI8_V_MF2_MF2_MASK }, // 221
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG2EI16_V_M1_M1_MASK }, // 222
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG2EI16_V_M2_M1_MASK }, // 223
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG2EI16_V_MF4_M1_MASK }, // 224
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG2EI16_V_MF2_M1_MASK }, // 225
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG2EI16_V_M1_M2_MASK }, // 226
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG2EI16_V_M2_M2_MASK }, // 227
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG2EI16_V_M4_M2_MASK }, // 228
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG2EI16_V_MF2_M2_MASK }, // 229
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVLOXSEG2EI16_V_M1_M4_MASK }, // 230
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVLOXSEG2EI16_V_M2_M4_MASK }, // 231
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVLOXSEG2EI16_V_M4_M4_MASK }, // 232
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVLOXSEG2EI16_V_M8_M4_MASK }, // 233
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{ 0x2, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF8_MASK }, // 234
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{ 0x2, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF4_MASK }, // 235
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{ 0x2, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF4_MASK }, // 236
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{ 0x2, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG2EI16_V_M1_MF2_MASK }, // 237
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{ 0x2, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF2_MASK }, // 238
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{ 0x2, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF2_MASK }, // 239
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{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG2EI32_V_M1_M1_MASK }, // 240
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{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG2EI32_V_M2_M1_MASK }, // 241
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{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG2EI32_V_M4_M1_MASK }, // 242
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{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG2EI32_V_MF2_M1_MASK }, // 243
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{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG2EI32_V_M1_M2_MASK }, // 244
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{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG2EI32_V_M2_M2_MASK }, // 245
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{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG2EI32_V_M4_M2_MASK }, // 246
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{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG2EI32_V_M8_M2_MASK }, // 247
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{ 0x2, 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVLOXSEG2EI32_V_M2_M4_MASK }, // 248
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{ 0x2, 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVLOXSEG2EI32_V_M4_M4_MASK }, // 249
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{ 0x2, 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVLOXSEG2EI32_V_M8_M4_MASK }, // 250
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{ 0x2, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF8_MASK }, // 251
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{ 0x2, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG2EI32_V_M1_MF4_MASK }, // 252
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{ 0x2, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF4_MASK }, // 253
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{ 0x2, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG2EI32_V_M1_MF2_MASK }, // 254
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{ 0x2, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG2EI32_V_M2_MF2_MASK }, // 255
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{ 0x2, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF2_MASK }, // 256
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG2EI64_V_M1_M1_MASK }, // 257
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG2EI64_V_M2_M1_MASK }, // 258
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG2EI64_V_M4_M1_MASK }, // 259
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG2EI64_V_M8_M1_MASK }, // 260
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{ 0x2, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG2EI64_V_M2_M2_MASK }, // 261
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{ 0x2, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG2EI64_V_M4_M2_MASK }, // 262
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{ 0x2, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG2EI64_V_M8_M2_MASK }, // 263
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{ 0x2, 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVLOXSEG2EI64_V_M4_M4_MASK }, // 264
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{ 0x2, 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVLOXSEG2EI64_V_M8_M4_MASK }, // 265
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{ 0x2, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG2EI64_V_M1_MF8_MASK }, // 266
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{ 0x2, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG2EI64_V_M1_MF4_MASK }, // 267
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{ 0x2, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG2EI64_V_M2_MF4_MASK }, // 268
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{ 0x2, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG2EI64_V_M1_MF2_MASK }, // 269
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{ 0x2, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG2EI64_V_M2_MF2_MASK }, // 270
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{ 0x2, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG2EI64_V_M4_MF2_MASK }, // 271
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG3EI8_V_M1_M1 }, // 272
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG3EI8_V_MF8_M1 }, // 273
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG3EI8_V_MF4_M1 }, // 274
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG3EI8_V_MF2_M1 }, // 275
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG3EI8_V_M1_M2 }, // 276
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG3EI8_V_M2_M2 }, // 277
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG3EI8_V_MF4_M2 }, // 278
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG3EI8_V_MF2_M2 }, // 279
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{ 0x3, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF8 }, // 280
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{ 0x3, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF4 }, // 281
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{ 0x3, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF4 }, // 282
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{ 0x3, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF2 }, // 283
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{ 0x3, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF2 }, // 284
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{ 0x3, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG3EI8_V_MF2_MF2 }, // 285
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG3EI16_V_M1_M1 }, // 286
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG3EI16_V_M2_M1 }, // 287
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG3EI16_V_MF4_M1 }, // 288
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG3EI16_V_MF2_M1 }, // 289
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG3EI16_V_M1_M2 }, // 290
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG3EI16_V_M2_M2 }, // 291
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG3EI16_V_M4_M2 }, // 292
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG3EI16_V_MF2_M2 }, // 293
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{ 0x3, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF8 }, // 294
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{ 0x3, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF4 }, // 295
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{ 0x3, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF4 }, // 296
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{ 0x3, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG3EI16_V_M1_MF2 }, // 297
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{ 0x3, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF2 }, // 298
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{ 0x3, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF2 }, // 299
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{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG3EI32_V_M1_M1 }, // 300
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{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG3EI32_V_M2_M1 }, // 301
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{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG3EI32_V_M4_M1 }, // 302
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{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG3EI32_V_MF2_M1 }, // 303
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{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG3EI32_V_M1_M2 }, // 304
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|
{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG3EI32_V_M2_M2 }, // 305
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{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG3EI32_V_M4_M2 }, // 306
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|
{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG3EI32_V_M8_M2 }, // 307
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|
{ 0x3, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF8 }, // 308
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|
{ 0x3, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG3EI32_V_M1_MF4 }, // 309
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|
{ 0x3, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF4 }, // 310
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{ 0x3, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG3EI32_V_M1_MF2 }, // 311
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{ 0x3, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG3EI32_V_M2_MF2 }, // 312
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|
{ 0x3, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF2 }, // 313
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|
{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG3EI64_V_M1_M1 }, // 314
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{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG3EI64_V_M2_M1 }, // 315
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{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG3EI64_V_M4_M1 }, // 316
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|
{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG3EI64_V_M8_M1 }, // 317
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{ 0x3, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG3EI64_V_M2_M2 }, // 318
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|
{ 0x3, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG3EI64_V_M4_M2 }, // 319
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|
{ 0x3, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG3EI64_V_M8_M2 }, // 320
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|
{ 0x3, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG3EI64_V_M1_MF8 }, // 321
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|
{ 0x3, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG3EI64_V_M1_MF4 }, // 322
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|
{ 0x3, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG3EI64_V_M2_MF4 }, // 323
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|
{ 0x3, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG3EI64_V_M1_MF2 }, // 324
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|
{ 0x3, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG3EI64_V_M2_MF2 }, // 325
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{ 0x3, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG3EI64_V_M4_MF2 }, // 326
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG3EI8_V_M1_M1 }, // 327
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG3EI8_V_MF8_M1 }, // 328
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG3EI8_V_MF4_M1 }, // 329
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG3EI8_V_MF2_M1 }, // 330
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG3EI8_V_M1_M2 }, // 331
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG3EI8_V_M2_M2 }, // 332
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG3EI8_V_MF4_M2 }, // 333
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG3EI8_V_MF2_M2 }, // 334
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF8 }, // 335
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|
{ 0x3, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF4 }, // 336
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|
{ 0x3, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF4 }, // 337
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|
{ 0x3, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF2 }, // 338
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|
{ 0x3, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF2 }, // 339
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|
{ 0x3, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG3EI8_V_MF2_MF2 }, // 340
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|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG3EI16_V_M1_M1 }, // 341
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|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG3EI16_V_M2_M1 }, // 342
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG3EI16_V_MF4_M1 }, // 343
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG3EI16_V_MF2_M1 }, // 344
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG3EI16_V_M1_M2 }, // 345
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG3EI16_V_M2_M2 }, // 346
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG3EI16_V_M4_M2 }, // 347
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG3EI16_V_MF2_M2 }, // 348
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF8 }, // 349
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF4 }, // 350
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|
{ 0x3, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF4 }, // 351
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|
{ 0x3, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG3EI16_V_M1_MF2 }, // 352
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF2 }, // 353
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF2 }, // 354
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|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG3EI32_V_M1_M1 }, // 355
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|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG3EI32_V_M2_M1 }, // 356
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG3EI32_V_M4_M1 }, // 357
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG3EI32_V_MF2_M1 }, // 358
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG3EI32_V_M1_M2 }, // 359
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG3EI32_V_M2_M2 }, // 360
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG3EI32_V_M4_M2 }, // 361
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{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG3EI32_V_M8_M2 }, // 362
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{ 0x3, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF8 }, // 363
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{ 0x3, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG3EI32_V_M1_MF4 }, // 364
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{ 0x3, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF4 }, // 365
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{ 0x3, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG3EI32_V_M1_MF2 }, // 366
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{ 0x3, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG3EI32_V_M2_MF2 }, // 367
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{ 0x3, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF2 }, // 368
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{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG3EI64_V_M1_M1 }, // 369
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{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG3EI64_V_M2_M1 }, // 370
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{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG3EI64_V_M4_M1 }, // 371
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{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG3EI64_V_M8_M1 }, // 372
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{ 0x3, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG3EI64_V_M2_M2 }, // 373
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{ 0x3, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG3EI64_V_M4_M2 }, // 374
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{ 0x3, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG3EI64_V_M8_M2 }, // 375
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{ 0x3, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG3EI64_V_M1_MF8 }, // 376
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{ 0x3, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG3EI64_V_M1_MF4 }, // 377
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{ 0x3, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG3EI64_V_M2_MF4 }, // 378
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{ 0x3, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG3EI64_V_M1_MF2 }, // 379
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{ 0x3, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG3EI64_V_M2_MF2 }, // 380
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{ 0x3, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG3EI64_V_M4_MF2 }, // 381
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{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG3EI8_V_M1_M1_MASK }, // 382
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{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG3EI8_V_MF8_M1_MASK }, // 383
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{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG3EI8_V_MF4_M1_MASK }, // 384
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{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG3EI8_V_MF2_M1_MASK }, // 385
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{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG3EI8_V_M1_M2_MASK }, // 386
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{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG3EI8_V_M2_M2_MASK }, // 387
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{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG3EI8_V_MF4_M2_MASK }, // 388
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{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG3EI8_V_MF2_M2_MASK }, // 389
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{ 0x3, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF8_MASK }, // 390
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{ 0x3, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF4_MASK }, // 391
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{ 0x3, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF4_MASK }, // 392
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{ 0x3, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF2_MASK }, // 393
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{ 0x3, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF2_MASK }, // 394
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{ 0x3, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG3EI8_V_MF2_MF2_MASK }, // 395
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{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG3EI16_V_M1_M1_MASK }, // 396
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{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG3EI16_V_M2_M1_MASK }, // 397
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{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG3EI16_V_MF4_M1_MASK }, // 398
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{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG3EI16_V_MF2_M1_MASK }, // 399
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG3EI16_V_M1_M2_MASK }, // 400
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG3EI16_V_M2_M2_MASK }, // 401
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG3EI16_V_M4_M2_MASK }, // 402
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG3EI16_V_MF2_M2_MASK }, // 403
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{ 0x3, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF8_MASK }, // 404
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{ 0x3, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF4_MASK }, // 405
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{ 0x3, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF4_MASK }, // 406
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{ 0x3, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG3EI16_V_M1_MF2_MASK }, // 407
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|
{ 0x3, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF2_MASK }, // 408
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|
{ 0x3, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF2_MASK }, // 409
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|
{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG3EI32_V_M1_M1_MASK }, // 410
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|
{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG3EI32_V_M2_M1_MASK }, // 411
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|
{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG3EI32_V_M4_M1_MASK }, // 412
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|
{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG3EI32_V_MF2_M1_MASK }, // 413
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|
{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG3EI32_V_M1_M2_MASK }, // 414
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|
{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG3EI32_V_M2_M2_MASK }, // 415
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|
{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG3EI32_V_M4_M2_MASK }, // 416
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|
{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG3EI32_V_M8_M2_MASK }, // 417
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|
{ 0x3, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF8_MASK }, // 418
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|
{ 0x3, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG3EI32_V_M1_MF4_MASK }, // 419
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|
{ 0x3, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF4_MASK }, // 420
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|
{ 0x3, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG3EI32_V_M1_MF2_MASK }, // 421
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{ 0x3, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG3EI32_V_M2_MF2_MASK }, // 422
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|
{ 0x3, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF2_MASK }, // 423
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|
{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG3EI64_V_M1_M1_MASK }, // 424
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|
{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG3EI64_V_M2_M1_MASK }, // 425
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{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG3EI64_V_M4_M1_MASK }, // 426
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{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG3EI64_V_M8_M1_MASK }, // 427
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|
{ 0x3, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG3EI64_V_M2_M2_MASK }, // 428
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|
{ 0x3, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG3EI64_V_M4_M2_MASK }, // 429
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{ 0x3, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG3EI64_V_M8_M2_MASK }, // 430
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{ 0x3, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG3EI64_V_M1_MF8_MASK }, // 431
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{ 0x3, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG3EI64_V_M1_MF4_MASK }, // 432
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{ 0x3, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG3EI64_V_M2_MF4_MASK }, // 433
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{ 0x3, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG3EI64_V_M1_MF2_MASK }, // 434
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{ 0x3, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG3EI64_V_M2_MF2_MASK }, // 435
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|
{ 0x3, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG3EI64_V_M4_MF2_MASK }, // 436
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|
{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG3EI8_V_M1_M1_MASK }, // 437
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{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG3EI8_V_MF8_M1_MASK }, // 438
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{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG3EI8_V_MF4_M1_MASK }, // 439
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|
{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG3EI8_V_MF2_M1_MASK }, // 440
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{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG3EI8_V_M1_M2_MASK }, // 441
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{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG3EI8_V_M2_M2_MASK }, // 442
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|
{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG3EI8_V_MF4_M2_MASK }, // 443
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|
{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG3EI8_V_MF2_M2_MASK }, // 444
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|
{ 0x3, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF8_MASK }, // 445
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|
{ 0x3, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF4_MASK }, // 446
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|
{ 0x3, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF4_MASK }, // 447
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|
{ 0x3, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF2_MASK }, // 448
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|
{ 0x3, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF2_MASK }, // 449
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|
{ 0x3, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG3EI8_V_MF2_MF2_MASK }, // 450
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|
{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG3EI16_V_M1_M1_MASK }, // 451
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|
{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG3EI16_V_M2_M1_MASK }, // 452
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|
{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG3EI16_V_MF4_M1_MASK }, // 453
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|
{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG3EI16_V_MF2_M1_MASK }, // 454
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|
{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG3EI16_V_M1_M2_MASK }, // 455
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|
{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG3EI16_V_M2_M2_MASK }, // 456
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|
{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG3EI16_V_M4_M2_MASK }, // 457
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|
{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG3EI16_V_MF2_M2_MASK }, // 458
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|
{ 0x3, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF8_MASK }, // 459
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|
{ 0x3, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF4_MASK }, // 460
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|
{ 0x3, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF4_MASK }, // 461
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|
{ 0x3, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG3EI16_V_M1_MF2_MASK }, // 462
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|
{ 0x3, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF2_MASK }, // 463
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|
{ 0x3, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF2_MASK }, // 464
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|
{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG3EI32_V_M1_M1_MASK }, // 465
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|
{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG3EI32_V_M2_M1_MASK }, // 466
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG3EI32_V_M4_M1_MASK }, // 467
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG3EI32_V_MF2_M1_MASK }, // 468
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG3EI32_V_M1_M2_MASK }, // 469
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG3EI32_V_M2_M2_MASK }, // 470
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG3EI32_V_M4_M2_MASK }, // 471
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|
{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG3EI32_V_M8_M2_MASK }, // 472
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF8_MASK }, // 473
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG3EI32_V_M1_MF4_MASK }, // 474
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|
{ 0x3, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF4_MASK }, // 475
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG3EI32_V_M1_MF2_MASK }, // 476
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG3EI32_V_M2_MF2_MASK }, // 477
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF2_MASK }, // 478
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG3EI64_V_M1_M1_MASK }, // 479
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG3EI64_V_M2_M1_MASK }, // 480
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG3EI64_V_M4_M1_MASK }, // 481
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG3EI64_V_M8_M1_MASK }, // 482
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG3EI64_V_M2_M2_MASK }, // 483
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG3EI64_V_M4_M2_MASK }, // 484
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG3EI64_V_M8_M2_MASK }, // 485
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG3EI64_V_M1_MF8_MASK }, // 486
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG3EI64_V_M1_MF4_MASK }, // 487
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG3EI64_V_M2_MF4_MASK }, // 488
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG3EI64_V_M1_MF2_MASK }, // 489
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG3EI64_V_M2_MF2_MASK }, // 490
|
|
{ 0x3, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG3EI64_V_M4_MF2_MASK }, // 491
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG4EI8_V_M1_M1 }, // 492
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG4EI8_V_MF8_M1 }, // 493
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG4EI8_V_MF4_M1 }, // 494
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG4EI8_V_MF2_M1 }, // 495
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG4EI8_V_M1_M2 }, // 496
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG4EI8_V_M2_M2 }, // 497
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG4EI8_V_MF4_M2 }, // 498
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG4EI8_V_MF2_M2 }, // 499
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF8 }, // 500
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF4 }, // 501
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF4 }, // 502
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF2 }, // 503
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF2 }, // 504
|
|
{ 0x4, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG4EI8_V_MF2_MF2 }, // 505
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG4EI16_V_M1_M1 }, // 506
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG4EI16_V_M2_M1 }, // 507
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG4EI16_V_MF4_M1 }, // 508
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|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG4EI16_V_MF2_M1 }, // 509
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|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG4EI16_V_M1_M2 }, // 510
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG4EI16_V_M2_M2 }, // 511
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG4EI16_V_M4_M2 }, // 512
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG4EI16_V_MF2_M2 }, // 513
|
|
{ 0x4, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF8 }, // 514
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|
{ 0x4, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF4 }, // 515
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|
{ 0x4, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF4 }, // 516
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|
{ 0x4, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG4EI16_V_M1_MF2 }, // 517
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|
{ 0x4, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF2 }, // 518
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|
{ 0x4, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF2 }, // 519
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|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG4EI32_V_M1_M1 }, // 520
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG4EI32_V_M2_M1 }, // 521
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG4EI32_V_M4_M1 }, // 522
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG4EI32_V_MF2_M1 }, // 523
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG4EI32_V_M1_M2 }, // 524
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG4EI32_V_M2_M2 }, // 525
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG4EI32_V_M4_M2 }, // 526
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG4EI32_V_M8_M2 }, // 527
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF8 }, // 528
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG4EI32_V_M1_MF4 }, // 529
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF4 }, // 530
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|
{ 0x4, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG4EI32_V_M1_MF2 }, // 531
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG4EI32_V_M2_MF2 }, // 532
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|
{ 0x4, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF2 }, // 533
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|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG4EI64_V_M1_M1 }, // 534
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|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG4EI64_V_M2_M1 }, // 535
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG4EI64_V_M4_M1 }, // 536
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|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG4EI64_V_M8_M1 }, // 537
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|
{ 0x4, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG4EI64_V_M2_M2 }, // 538
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|
{ 0x4, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG4EI64_V_M4_M2 }, // 539
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|
{ 0x4, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG4EI64_V_M8_M2 }, // 540
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|
{ 0x4, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG4EI64_V_M1_MF8 }, // 541
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG4EI64_V_M1_MF4 }, // 542
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG4EI64_V_M2_MF4 }, // 543
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG4EI64_V_M1_MF2 }, // 544
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG4EI64_V_M2_MF2 }, // 545
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG4EI64_V_M4_MF2 }, // 546
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG4EI8_V_M1_M1 }, // 547
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG4EI8_V_MF8_M1 }, // 548
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG4EI8_V_MF4_M1 }, // 549
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG4EI8_V_MF2_M1 }, // 550
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG4EI8_V_M1_M2 }, // 551
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG4EI8_V_M2_M2 }, // 552
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG4EI8_V_MF4_M2 }, // 553
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG4EI8_V_MF2_M2 }, // 554
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF8 }, // 555
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF4 }, // 556
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF4 }, // 557
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF2 }, // 558
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF2 }, // 559
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG4EI8_V_MF2_MF2 }, // 560
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG4EI16_V_M1_M1 }, // 561
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG4EI16_V_M2_M1 }, // 562
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG4EI16_V_MF4_M1 }, // 563
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG4EI16_V_MF2_M1 }, // 564
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG4EI16_V_M1_M2 }, // 565
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG4EI16_V_M2_M2 }, // 566
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG4EI16_V_M4_M2 }, // 567
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG4EI16_V_MF2_M2 }, // 568
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF8 }, // 569
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF4 }, // 570
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF4 }, // 571
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG4EI16_V_M1_MF2 }, // 572
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF2 }, // 573
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF2 }, // 574
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG4EI32_V_M1_M1 }, // 575
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG4EI32_V_M2_M1 }, // 576
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG4EI32_V_M4_M1 }, // 577
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG4EI32_V_MF2_M1 }, // 578
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG4EI32_V_M1_M2 }, // 579
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG4EI32_V_M2_M2 }, // 580
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG4EI32_V_M4_M2 }, // 581
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG4EI32_V_M8_M2 }, // 582
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF8 }, // 583
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG4EI32_V_M1_MF4 }, // 584
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF4 }, // 585
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG4EI32_V_M1_MF2 }, // 586
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG4EI32_V_M2_MF2 }, // 587
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF2 }, // 588
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG4EI64_V_M1_M1 }, // 589
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG4EI64_V_M2_M1 }, // 590
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG4EI64_V_M4_M1 }, // 591
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG4EI64_V_M8_M1 }, // 592
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG4EI64_V_M2_M2 }, // 593
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG4EI64_V_M4_M2 }, // 594
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG4EI64_V_M8_M2 }, // 595
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG4EI64_V_M1_MF8 }, // 596
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG4EI64_V_M1_MF4 }, // 597
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG4EI64_V_M2_MF4 }, // 598
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG4EI64_V_M1_MF2 }, // 599
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG4EI64_V_M2_MF2 }, // 600
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG4EI64_V_M4_MF2 }, // 601
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG4EI8_V_M1_M1_MASK }, // 602
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG4EI8_V_MF8_M1_MASK }, // 603
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG4EI8_V_MF4_M1_MASK }, // 604
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG4EI8_V_MF2_M1_MASK }, // 605
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG4EI8_V_M1_M2_MASK }, // 606
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG4EI8_V_M2_M2_MASK }, // 607
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG4EI8_V_MF4_M2_MASK }, // 608
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG4EI8_V_MF2_M2_MASK }, // 609
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF8_MASK }, // 610
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF4_MASK }, // 611
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF4_MASK }, // 612
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF2_MASK }, // 613
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF2_MASK }, // 614
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG4EI8_V_MF2_MF2_MASK }, // 615
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG4EI16_V_M1_M1_MASK }, // 616
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG4EI16_V_M2_M1_MASK }, // 617
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG4EI16_V_MF4_M1_MASK }, // 618
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG4EI16_V_MF2_M1_MASK }, // 619
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG4EI16_V_M1_M2_MASK }, // 620
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG4EI16_V_M2_M2_MASK }, // 621
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG4EI16_V_M4_M2_MASK }, // 622
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG4EI16_V_MF2_M2_MASK }, // 623
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF8_MASK }, // 624
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF4_MASK }, // 625
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF4_MASK }, // 626
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG4EI16_V_M1_MF2_MASK }, // 627
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF2_MASK }, // 628
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF2_MASK }, // 629
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG4EI32_V_M1_M1_MASK }, // 630
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG4EI32_V_M2_M1_MASK }, // 631
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG4EI32_V_M4_M1_MASK }, // 632
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG4EI32_V_MF2_M1_MASK }, // 633
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG4EI32_V_M1_M2_MASK }, // 634
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG4EI32_V_M2_M2_MASK }, // 635
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG4EI32_V_M4_M2_MASK }, // 636
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG4EI32_V_M8_M2_MASK }, // 637
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF8_MASK }, // 638
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG4EI32_V_M1_MF4_MASK }, // 639
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF4_MASK }, // 640
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG4EI32_V_M1_MF2_MASK }, // 641
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG4EI32_V_M2_MF2_MASK }, // 642
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF2_MASK }, // 643
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG4EI64_V_M1_M1_MASK }, // 644
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG4EI64_V_M2_M1_MASK }, // 645
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG4EI64_V_M4_M1_MASK }, // 646
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG4EI64_V_M8_M1_MASK }, // 647
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG4EI64_V_M2_M2_MASK }, // 648
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG4EI64_V_M4_M2_MASK }, // 649
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG4EI64_V_M8_M2_MASK }, // 650
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG4EI64_V_M1_MF8_MASK }, // 651
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG4EI64_V_M1_MF4_MASK }, // 652
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG4EI64_V_M2_MF4_MASK }, // 653
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG4EI64_V_M1_MF2_MASK }, // 654
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG4EI64_V_M2_MF2_MASK }, // 655
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG4EI64_V_M4_MF2_MASK }, // 656
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG4EI8_V_M1_M1_MASK }, // 657
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG4EI8_V_MF8_M1_MASK }, // 658
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG4EI8_V_MF4_M1_MASK }, // 659
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG4EI8_V_MF2_M1_MASK }, // 660
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG4EI8_V_M1_M2_MASK }, // 661
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG4EI8_V_M2_M2_MASK }, // 662
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG4EI8_V_MF4_M2_MASK }, // 663
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG4EI8_V_MF2_M2_MASK }, // 664
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF8_MASK }, // 665
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF4_MASK }, // 666
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF4_MASK }, // 667
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF2_MASK }, // 668
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF2_MASK }, // 669
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG4EI8_V_MF2_MF2_MASK }, // 670
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG4EI16_V_M1_M1_MASK }, // 671
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG4EI16_V_M2_M1_MASK }, // 672
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG4EI16_V_MF4_M1_MASK }, // 673
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG4EI16_V_MF2_M1_MASK }, // 674
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG4EI16_V_M1_M2_MASK }, // 675
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG4EI16_V_M2_M2_MASK }, // 676
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG4EI16_V_M4_M2_MASK }, // 677
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG4EI16_V_MF2_M2_MASK }, // 678
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF8_MASK }, // 679
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF4_MASK }, // 680
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF4_MASK }, // 681
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG4EI16_V_M1_MF2_MASK }, // 682
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF2_MASK }, // 683
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF2_MASK }, // 684
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG4EI32_V_M1_M1_MASK }, // 685
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG4EI32_V_M2_M1_MASK }, // 686
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG4EI32_V_M4_M1_MASK }, // 687
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG4EI32_V_MF2_M1_MASK }, // 688
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG4EI32_V_M1_M2_MASK }, // 689
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG4EI32_V_M2_M2_MASK }, // 690
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG4EI32_V_M4_M2_MASK }, // 691
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG4EI32_V_M8_M2_MASK }, // 692
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF8_MASK }, // 693
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG4EI32_V_M1_MF4_MASK }, // 694
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF4_MASK }, // 695
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG4EI32_V_M1_MF2_MASK }, // 696
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG4EI32_V_M2_MF2_MASK }, // 697
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF2_MASK }, // 698
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG4EI64_V_M1_M1_MASK }, // 699
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG4EI64_V_M2_M1_MASK }, // 700
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG4EI64_V_M4_M1_MASK }, // 701
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG4EI64_V_M8_M1_MASK }, // 702
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG4EI64_V_M2_M2_MASK }, // 703
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG4EI64_V_M4_M2_MASK }, // 704
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG4EI64_V_M8_M2_MASK }, // 705
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG4EI64_V_M1_MF8_MASK }, // 706
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG4EI64_V_M1_MF4_MASK }, // 707
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG4EI64_V_M2_MF4_MASK }, // 708
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG4EI64_V_M1_MF2_MASK }, // 709
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG4EI64_V_M2_MF2_MASK }, // 710
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG4EI64_V_M4_MF2_MASK }, // 711
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG5EI8_V_M1_M1 }, // 712
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG5EI8_V_MF8_M1 }, // 713
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG5EI8_V_MF4_M1 }, // 714
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG5EI8_V_MF2_M1 }, // 715
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF8 }, // 716
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF4 }, // 717
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF4 }, // 718
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF2 }, // 719
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF2 }, // 720
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG5EI8_V_MF2_MF2 }, // 721
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG5EI16_V_M1_M1 }, // 722
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG5EI16_V_M2_M1 }, // 723
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG5EI16_V_MF4_M1 }, // 724
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG5EI16_V_MF2_M1 }, // 725
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF8 }, // 726
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF4 }, // 727
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF4 }, // 728
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG5EI16_V_M1_MF2 }, // 729
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF2 }, // 730
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF2 }, // 731
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG5EI32_V_M1_M1 }, // 732
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG5EI32_V_M2_M1 }, // 733
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG5EI32_V_M4_M1 }, // 734
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG5EI32_V_MF2_M1 }, // 735
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF8 }, // 736
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG5EI32_V_M1_MF4 }, // 737
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF4 }, // 738
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG5EI32_V_M1_MF2 }, // 739
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG5EI32_V_M2_MF2 }, // 740
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF2 }, // 741
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG5EI64_V_M1_M1 }, // 742
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG5EI64_V_M2_M1 }, // 743
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG5EI64_V_M4_M1 }, // 744
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG5EI64_V_M8_M1 }, // 745
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG5EI64_V_M1_MF8 }, // 746
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG5EI64_V_M1_MF4 }, // 747
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG5EI64_V_M2_MF4 }, // 748
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG5EI64_V_M1_MF2 }, // 749
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG5EI64_V_M2_MF2 }, // 750
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG5EI64_V_M4_MF2 }, // 751
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG5EI8_V_M1_M1 }, // 752
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG5EI8_V_MF8_M1 }, // 753
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG5EI8_V_MF4_M1 }, // 754
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG5EI8_V_MF2_M1 }, // 755
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF8 }, // 756
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF4 }, // 757
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF4 }, // 758
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF2 }, // 759
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF2 }, // 760
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG5EI8_V_MF2_MF2 }, // 761
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG5EI16_V_M1_M1 }, // 762
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG5EI16_V_M2_M1 }, // 763
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG5EI16_V_MF4_M1 }, // 764
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG5EI16_V_MF2_M1 }, // 765
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF8 }, // 766
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF4 }, // 767
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF4 }, // 768
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG5EI16_V_M1_MF2 }, // 769
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF2 }, // 770
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF2 }, // 771
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG5EI32_V_M1_M1 }, // 772
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG5EI32_V_M2_M1 }, // 773
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG5EI32_V_M4_M1 }, // 774
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG5EI32_V_MF2_M1 }, // 775
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF8 }, // 776
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG5EI32_V_M1_MF4 }, // 777
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF4 }, // 778
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG5EI32_V_M1_MF2 }, // 779
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG5EI32_V_M2_MF2 }, // 780
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF2 }, // 781
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG5EI64_V_M1_M1 }, // 782
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG5EI64_V_M2_M1 }, // 783
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG5EI64_V_M4_M1 }, // 784
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG5EI64_V_M8_M1 }, // 785
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG5EI64_V_M1_MF8 }, // 786
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG5EI64_V_M1_MF4 }, // 787
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG5EI64_V_M2_MF4 }, // 788
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG5EI64_V_M1_MF2 }, // 789
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG5EI64_V_M2_MF2 }, // 790
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG5EI64_V_M4_MF2 }, // 791
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG5EI8_V_M1_M1_MASK }, // 792
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG5EI8_V_MF8_M1_MASK }, // 793
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG5EI8_V_MF4_M1_MASK }, // 794
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG5EI8_V_MF2_M1_MASK }, // 795
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF8_MASK }, // 796
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF4_MASK }, // 797
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF4_MASK }, // 798
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF2_MASK }, // 799
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF2_MASK }, // 800
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG5EI8_V_MF2_MF2_MASK }, // 801
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG5EI16_V_M1_M1_MASK }, // 802
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG5EI16_V_M2_M1_MASK }, // 803
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG5EI16_V_MF4_M1_MASK }, // 804
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG5EI16_V_MF2_M1_MASK }, // 805
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF8_MASK }, // 806
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF4_MASK }, // 807
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF4_MASK }, // 808
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG5EI16_V_M1_MF2_MASK }, // 809
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF2_MASK }, // 810
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF2_MASK }, // 811
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG5EI32_V_M1_M1_MASK }, // 812
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG5EI32_V_M2_M1_MASK }, // 813
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG5EI32_V_M4_M1_MASK }, // 814
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG5EI32_V_MF2_M1_MASK }, // 815
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF8_MASK }, // 816
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG5EI32_V_M1_MF4_MASK }, // 817
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF4_MASK }, // 818
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG5EI32_V_M1_MF2_MASK }, // 819
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG5EI32_V_M2_MF2_MASK }, // 820
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF2_MASK }, // 821
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG5EI64_V_M1_M1_MASK }, // 822
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG5EI64_V_M2_M1_MASK }, // 823
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG5EI64_V_M4_M1_MASK }, // 824
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG5EI64_V_M8_M1_MASK }, // 825
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG5EI64_V_M1_MF8_MASK }, // 826
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG5EI64_V_M1_MF4_MASK }, // 827
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG5EI64_V_M2_MF4_MASK }, // 828
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG5EI64_V_M1_MF2_MASK }, // 829
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG5EI64_V_M2_MF2_MASK }, // 830
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG5EI64_V_M4_MF2_MASK }, // 831
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG5EI8_V_M1_M1_MASK }, // 832
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG5EI8_V_MF8_M1_MASK }, // 833
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG5EI8_V_MF4_M1_MASK }, // 834
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG5EI8_V_MF2_M1_MASK }, // 835
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF8_MASK }, // 836
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF4_MASK }, // 837
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF4_MASK }, // 838
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF2_MASK }, // 839
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF2_MASK }, // 840
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG5EI8_V_MF2_MF2_MASK }, // 841
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG5EI16_V_M1_M1_MASK }, // 842
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG5EI16_V_M2_M1_MASK }, // 843
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG5EI16_V_MF4_M1_MASK }, // 844
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG5EI16_V_MF2_M1_MASK }, // 845
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF8_MASK }, // 846
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF4_MASK }, // 847
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF4_MASK }, // 848
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG5EI16_V_M1_MF2_MASK }, // 849
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF2_MASK }, // 850
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF2_MASK }, // 851
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG5EI32_V_M1_M1_MASK }, // 852
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG5EI32_V_M2_M1_MASK }, // 853
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG5EI32_V_M4_M1_MASK }, // 854
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG5EI32_V_MF2_M1_MASK }, // 855
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF8_MASK }, // 856
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG5EI32_V_M1_MF4_MASK }, // 857
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF4_MASK }, // 858
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG5EI32_V_M1_MF2_MASK }, // 859
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG5EI32_V_M2_MF2_MASK }, // 860
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF2_MASK }, // 861
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG5EI64_V_M1_M1_MASK }, // 862
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG5EI64_V_M2_M1_MASK }, // 863
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG5EI64_V_M4_M1_MASK }, // 864
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG5EI64_V_M8_M1_MASK }, // 865
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG5EI64_V_M1_MF8_MASK }, // 866
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG5EI64_V_M1_MF4_MASK }, // 867
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG5EI64_V_M2_MF4_MASK }, // 868
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG5EI64_V_M1_MF2_MASK }, // 869
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG5EI64_V_M2_MF2_MASK }, // 870
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG5EI64_V_M4_MF2_MASK }, // 871
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG6EI8_V_M1_M1 }, // 872
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG6EI8_V_MF8_M1 }, // 873
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG6EI8_V_MF4_M1 }, // 874
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG6EI8_V_MF2_M1 }, // 875
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF8 }, // 876
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF4 }, // 877
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF4 }, // 878
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF2 }, // 879
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF2 }, // 880
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG6EI8_V_MF2_MF2 }, // 881
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG6EI16_V_M1_M1 }, // 882
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG6EI16_V_M2_M1 }, // 883
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG6EI16_V_MF4_M1 }, // 884
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG6EI16_V_MF2_M1 }, // 885
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF8 }, // 886
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF4 }, // 887
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF4 }, // 888
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG6EI16_V_M1_MF2 }, // 889
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF2 }, // 890
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF2 }, // 891
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG6EI32_V_M1_M1 }, // 892
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG6EI32_V_M2_M1 }, // 893
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG6EI32_V_M4_M1 }, // 894
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG6EI32_V_MF2_M1 }, // 895
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF8 }, // 896
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG6EI32_V_M1_MF4 }, // 897
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF4 }, // 898
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG6EI32_V_M1_MF2 }, // 899
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG6EI32_V_M2_MF2 }, // 900
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF2 }, // 901
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG6EI64_V_M1_M1 }, // 902
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG6EI64_V_M2_M1 }, // 903
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG6EI64_V_M4_M1 }, // 904
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG6EI64_V_M8_M1 }, // 905
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG6EI64_V_M1_MF8 }, // 906
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG6EI64_V_M1_MF4 }, // 907
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG6EI64_V_M2_MF4 }, // 908
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG6EI64_V_M1_MF2 }, // 909
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG6EI64_V_M2_MF2 }, // 910
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG6EI64_V_M4_MF2 }, // 911
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG6EI8_V_M1_M1 }, // 912
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG6EI8_V_MF8_M1 }, // 913
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG6EI8_V_MF4_M1 }, // 914
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG6EI8_V_MF2_M1 }, // 915
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF8 }, // 916
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF4 }, // 917
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF4 }, // 918
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF2 }, // 919
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF2 }, // 920
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG6EI8_V_MF2_MF2 }, // 921
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG6EI16_V_M1_M1 }, // 922
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG6EI16_V_M2_M1 }, // 923
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG6EI16_V_MF4_M1 }, // 924
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG6EI16_V_MF2_M1 }, // 925
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF8 }, // 926
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF4 }, // 927
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF4 }, // 928
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG6EI16_V_M1_MF2 }, // 929
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF2 }, // 930
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF2 }, // 931
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG6EI32_V_M1_M1 }, // 932
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG6EI32_V_M2_M1 }, // 933
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG6EI32_V_M4_M1 }, // 934
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG6EI32_V_MF2_M1 }, // 935
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF8 }, // 936
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG6EI32_V_M1_MF4 }, // 937
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF4 }, // 938
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG6EI32_V_M1_MF2 }, // 939
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG6EI32_V_M2_MF2 }, // 940
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF2 }, // 941
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG6EI64_V_M1_M1 }, // 942
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG6EI64_V_M2_M1 }, // 943
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG6EI64_V_M4_M1 }, // 944
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG6EI64_V_M8_M1 }, // 945
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG6EI64_V_M1_MF8 }, // 946
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG6EI64_V_M1_MF4 }, // 947
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG6EI64_V_M2_MF4 }, // 948
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG6EI64_V_M1_MF2 }, // 949
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG6EI64_V_M2_MF2 }, // 950
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG6EI64_V_M4_MF2 }, // 951
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG6EI8_V_M1_M1_MASK }, // 952
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG6EI8_V_MF8_M1_MASK }, // 953
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG6EI8_V_MF4_M1_MASK }, // 954
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG6EI8_V_MF2_M1_MASK }, // 955
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF8_MASK }, // 956
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF4_MASK }, // 957
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF4_MASK }, // 958
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF2_MASK }, // 959
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF2_MASK }, // 960
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG6EI8_V_MF2_MF2_MASK }, // 961
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG6EI16_V_M1_M1_MASK }, // 962
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG6EI16_V_M2_M1_MASK }, // 963
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG6EI16_V_MF4_M1_MASK }, // 964
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG6EI16_V_MF2_M1_MASK }, // 965
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF8_MASK }, // 966
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF4_MASK }, // 967
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF4_MASK }, // 968
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG6EI16_V_M1_MF2_MASK }, // 969
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF2_MASK }, // 970
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF2_MASK }, // 971
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG6EI32_V_M1_M1_MASK }, // 972
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG6EI32_V_M2_M1_MASK }, // 973
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG6EI32_V_M4_M1_MASK }, // 974
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG6EI32_V_MF2_M1_MASK }, // 975
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF8_MASK }, // 976
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG6EI32_V_M1_MF4_MASK }, // 977
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF4_MASK }, // 978
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG6EI32_V_M1_MF2_MASK }, // 979
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG6EI32_V_M2_MF2_MASK }, // 980
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF2_MASK }, // 981
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG6EI64_V_M1_M1_MASK }, // 982
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG6EI64_V_M2_M1_MASK }, // 983
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG6EI64_V_M4_M1_MASK }, // 984
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG6EI64_V_M8_M1_MASK }, // 985
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG6EI64_V_M1_MF8_MASK }, // 986
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG6EI64_V_M1_MF4_MASK }, // 987
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG6EI64_V_M2_MF4_MASK }, // 988
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG6EI64_V_M1_MF2_MASK }, // 989
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG6EI64_V_M2_MF2_MASK }, // 990
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG6EI64_V_M4_MF2_MASK }, // 991
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG6EI8_V_M1_M1_MASK }, // 992
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG6EI8_V_MF8_M1_MASK }, // 993
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG6EI8_V_MF4_M1_MASK }, // 994
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG6EI8_V_MF2_M1_MASK }, // 995
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF8_MASK }, // 996
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF4_MASK }, // 997
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF4_MASK }, // 998
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF2_MASK }, // 999
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF2_MASK }, // 1000
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG6EI8_V_MF2_MF2_MASK }, // 1001
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG6EI16_V_M1_M1_MASK }, // 1002
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG6EI16_V_M2_M1_MASK }, // 1003
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG6EI16_V_MF4_M1_MASK }, // 1004
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG6EI16_V_MF2_M1_MASK }, // 1005
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF8_MASK }, // 1006
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF4_MASK }, // 1007
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF4_MASK }, // 1008
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG6EI16_V_M1_MF2_MASK }, // 1009
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF2_MASK }, // 1010
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF2_MASK }, // 1011
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG6EI32_V_M1_M1_MASK }, // 1012
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG6EI32_V_M2_M1_MASK }, // 1013
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG6EI32_V_M4_M1_MASK }, // 1014
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG6EI32_V_MF2_M1_MASK }, // 1015
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF8_MASK }, // 1016
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG6EI32_V_M1_MF4_MASK }, // 1017
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF4_MASK }, // 1018
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG6EI32_V_M1_MF2_MASK }, // 1019
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG6EI32_V_M2_MF2_MASK }, // 1020
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF2_MASK }, // 1021
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG6EI64_V_M1_M1_MASK }, // 1022
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG6EI64_V_M2_M1_MASK }, // 1023
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG6EI64_V_M4_M1_MASK }, // 1024
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG6EI64_V_M8_M1_MASK }, // 1025
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG6EI64_V_M1_MF8_MASK }, // 1026
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG6EI64_V_M1_MF4_MASK }, // 1027
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG6EI64_V_M2_MF4_MASK }, // 1028
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG6EI64_V_M1_MF2_MASK }, // 1029
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG6EI64_V_M2_MF2_MASK }, // 1030
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG6EI64_V_M4_MF2_MASK }, // 1031
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG7EI8_V_M1_M1 }, // 1032
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG7EI8_V_MF8_M1 }, // 1033
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG7EI8_V_MF4_M1 }, // 1034
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG7EI8_V_MF2_M1 }, // 1035
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF8 }, // 1036
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF4 }, // 1037
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF4 }, // 1038
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF2 }, // 1039
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF2 }, // 1040
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG7EI8_V_MF2_MF2 }, // 1041
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG7EI16_V_M1_M1 }, // 1042
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG7EI16_V_M2_M1 }, // 1043
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG7EI16_V_MF4_M1 }, // 1044
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG7EI16_V_MF2_M1 }, // 1045
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF8 }, // 1046
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF4 }, // 1047
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF4 }, // 1048
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG7EI16_V_M1_MF2 }, // 1049
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF2 }, // 1050
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF2 }, // 1051
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG7EI32_V_M1_M1 }, // 1052
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG7EI32_V_M2_M1 }, // 1053
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG7EI32_V_M4_M1 }, // 1054
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG7EI32_V_MF2_M1 }, // 1055
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF8 }, // 1056
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG7EI32_V_M1_MF4 }, // 1057
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF4 }, // 1058
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG7EI32_V_M1_MF2 }, // 1059
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG7EI32_V_M2_MF2 }, // 1060
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF2 }, // 1061
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG7EI64_V_M1_M1 }, // 1062
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG7EI64_V_M2_M1 }, // 1063
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG7EI64_V_M4_M1 }, // 1064
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG7EI64_V_M8_M1 }, // 1065
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG7EI64_V_M1_MF8 }, // 1066
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG7EI64_V_M1_MF4 }, // 1067
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG7EI64_V_M2_MF4 }, // 1068
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG7EI64_V_M1_MF2 }, // 1069
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG7EI64_V_M2_MF2 }, // 1070
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG7EI64_V_M4_MF2 }, // 1071
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG7EI8_V_M1_M1 }, // 1072
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG7EI8_V_MF8_M1 }, // 1073
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG7EI8_V_MF4_M1 }, // 1074
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG7EI8_V_MF2_M1 }, // 1075
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF8 }, // 1076
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF4 }, // 1077
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF4 }, // 1078
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF2 }, // 1079
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF2 }, // 1080
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG7EI8_V_MF2_MF2 }, // 1081
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG7EI16_V_M1_M1 }, // 1082
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG7EI16_V_M2_M1 }, // 1083
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG7EI16_V_MF4_M1 }, // 1084
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG7EI16_V_MF2_M1 }, // 1085
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF8 }, // 1086
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF4 }, // 1087
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF4 }, // 1088
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG7EI16_V_M1_MF2 }, // 1089
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{ 0x7, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF2 }, // 1090
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{ 0x7, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF2 }, // 1091
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{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG7EI32_V_M1_M1 }, // 1092
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{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG7EI32_V_M2_M1 }, // 1093
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{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG7EI32_V_M4_M1 }, // 1094
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{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG7EI32_V_MF2_M1 }, // 1095
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{ 0x7, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF8 }, // 1096
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|
{ 0x7, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG7EI32_V_M1_MF4 }, // 1097
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{ 0x7, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF4 }, // 1098
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{ 0x7, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG7EI32_V_M1_MF2 }, // 1099
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{ 0x7, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG7EI32_V_M2_MF2 }, // 1100
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{ 0x7, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF2 }, // 1101
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{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG7EI64_V_M1_M1 }, // 1102
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{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG7EI64_V_M2_M1 }, // 1103
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{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG7EI64_V_M4_M1 }, // 1104
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{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG7EI64_V_M8_M1 }, // 1105
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{ 0x7, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG7EI64_V_M1_MF8 }, // 1106
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{ 0x7, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG7EI64_V_M1_MF4 }, // 1107
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{ 0x7, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG7EI64_V_M2_MF4 }, // 1108
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{ 0x7, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG7EI64_V_M1_MF2 }, // 1109
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{ 0x7, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG7EI64_V_M2_MF2 }, // 1110
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{ 0x7, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG7EI64_V_M4_MF2 }, // 1111
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{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG7EI8_V_M1_M1_MASK }, // 1112
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{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG7EI8_V_MF8_M1_MASK }, // 1113
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{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG7EI8_V_MF4_M1_MASK }, // 1114
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{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG7EI8_V_MF2_M1_MASK }, // 1115
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{ 0x7, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF8_MASK }, // 1116
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|
{ 0x7, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF4_MASK }, // 1117
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|
{ 0x7, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF4_MASK }, // 1118
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF2_MASK }, // 1119
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{ 0x7, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF2_MASK }, // 1120
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{ 0x7, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG7EI8_V_MF2_MF2_MASK }, // 1121
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{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG7EI16_V_M1_M1_MASK }, // 1122
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{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG7EI16_V_M2_M1_MASK }, // 1123
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|
{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG7EI16_V_MF4_M1_MASK }, // 1124
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|
{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG7EI16_V_MF2_M1_MASK }, // 1125
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|
{ 0x7, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF8_MASK }, // 1126
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{ 0x7, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF4_MASK }, // 1127
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|
{ 0x7, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF4_MASK }, // 1128
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|
{ 0x7, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG7EI16_V_M1_MF2_MASK }, // 1129
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{ 0x7, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF2_MASK }, // 1130
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{ 0x7, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF2_MASK }, // 1131
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG7EI32_V_M1_M1_MASK }, // 1132
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG7EI32_V_M2_M1_MASK }, // 1133
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG7EI32_V_M4_M1_MASK }, // 1134
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG7EI32_V_MF2_M1_MASK }, // 1135
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{ 0x7, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF8_MASK }, // 1136
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|
{ 0x7, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG7EI32_V_M1_MF4_MASK }, // 1137
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{ 0x7, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF4_MASK }, // 1138
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{ 0x7, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG7EI32_V_M1_MF2_MASK }, // 1139
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|
{ 0x7, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG7EI32_V_M2_MF2_MASK }, // 1140
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|
{ 0x7, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF2_MASK }, // 1141
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|
{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG7EI64_V_M1_M1_MASK }, // 1142
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|
{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG7EI64_V_M2_M1_MASK }, // 1143
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|
{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG7EI64_V_M4_M1_MASK }, // 1144
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|
{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG7EI64_V_M8_M1_MASK }, // 1145
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|
{ 0x7, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG7EI64_V_M1_MF8_MASK }, // 1146
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|
{ 0x7, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG7EI64_V_M1_MF4_MASK }, // 1147
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|
{ 0x7, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG7EI64_V_M2_MF4_MASK }, // 1148
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|
{ 0x7, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG7EI64_V_M1_MF2_MASK }, // 1149
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|
{ 0x7, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG7EI64_V_M2_MF2_MASK }, // 1150
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|
{ 0x7, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG7EI64_V_M4_MF2_MASK }, // 1151
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|
{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG7EI8_V_M1_M1_MASK }, // 1152
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|
{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG7EI8_V_MF8_M1_MASK }, // 1153
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|
{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG7EI8_V_MF4_M1_MASK }, // 1154
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|
{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG7EI8_V_MF2_M1_MASK }, // 1155
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|
{ 0x7, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF8_MASK }, // 1156
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|
{ 0x7, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF4_MASK }, // 1157
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|
{ 0x7, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF4_MASK }, // 1158
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|
{ 0x7, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF2_MASK }, // 1159
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|
{ 0x7, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF2_MASK }, // 1160
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|
{ 0x7, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG7EI8_V_MF2_MF2_MASK }, // 1161
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|
{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG7EI16_V_M1_M1_MASK }, // 1162
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|
{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG7EI16_V_M2_M1_MASK }, // 1163
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|
{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG7EI16_V_MF4_M1_MASK }, // 1164
|
|
{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG7EI16_V_MF2_M1_MASK }, // 1165
|
|
{ 0x7, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF8_MASK }, // 1166
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|
{ 0x7, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF4_MASK }, // 1167
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|
{ 0x7, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF4_MASK }, // 1168
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|
{ 0x7, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG7EI16_V_M1_MF2_MASK }, // 1169
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|
{ 0x7, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF2_MASK }, // 1170
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|
{ 0x7, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF2_MASK }, // 1171
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|
{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG7EI32_V_M1_M1_MASK }, // 1172
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|
{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG7EI32_V_M2_M1_MASK }, // 1173
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{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG7EI32_V_M4_M1_MASK }, // 1174
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|
{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG7EI32_V_MF2_M1_MASK }, // 1175
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|
{ 0x7, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF8_MASK }, // 1176
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|
{ 0x7, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG7EI32_V_M1_MF4_MASK }, // 1177
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|
{ 0x7, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF4_MASK }, // 1178
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|
{ 0x7, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG7EI32_V_M1_MF2_MASK }, // 1179
|
|
{ 0x7, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG7EI32_V_M2_MF2_MASK }, // 1180
|
|
{ 0x7, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF2_MASK }, // 1181
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG7EI64_V_M1_M1_MASK }, // 1182
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG7EI64_V_M2_M1_MASK }, // 1183
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG7EI64_V_M4_M1_MASK }, // 1184
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG7EI64_V_M8_M1_MASK }, // 1185
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG7EI64_V_M1_MF8_MASK }, // 1186
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG7EI64_V_M1_MF4_MASK }, // 1187
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG7EI64_V_M2_MF4_MASK }, // 1188
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG7EI64_V_M1_MF2_MASK }, // 1189
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG7EI64_V_M2_MF2_MASK }, // 1190
|
|
{ 0x7, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG7EI64_V_M4_MF2_MASK }, // 1191
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG8EI8_V_M1_M1 }, // 1192
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG8EI8_V_MF8_M1 }, // 1193
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG8EI8_V_MF4_M1 }, // 1194
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG8EI8_V_MF2_M1 }, // 1195
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF8 }, // 1196
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF4 }, // 1197
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF4 }, // 1198
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF2 }, // 1199
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF2 }, // 1200
|
|
{ 0x8, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG8EI8_V_MF2_MF2 }, // 1201
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG8EI16_V_M1_M1 }, // 1202
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG8EI16_V_M2_M1 }, // 1203
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG8EI16_V_MF4_M1 }, // 1204
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG8EI16_V_MF2_M1 }, // 1205
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF8 }, // 1206
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF4 }, // 1207
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF4 }, // 1208
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG8EI16_V_M1_MF2 }, // 1209
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF2 }, // 1210
|
|
{ 0x8, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF2 }, // 1211
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG8EI32_V_M1_M1 }, // 1212
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG8EI32_V_M2_M1 }, // 1213
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG8EI32_V_M4_M1 }, // 1214
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG8EI32_V_MF2_M1 }, // 1215
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF8 }, // 1216
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG8EI32_V_M1_MF4 }, // 1217
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF4 }, // 1218
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG8EI32_V_M1_MF2 }, // 1219
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG8EI32_V_M2_MF2 }, // 1220
|
|
{ 0x8, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF2 }, // 1221
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG8EI64_V_M1_M1 }, // 1222
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG8EI64_V_M2_M1 }, // 1223
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG8EI64_V_M4_M1 }, // 1224
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG8EI64_V_M8_M1 }, // 1225
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG8EI64_V_M1_MF8 }, // 1226
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG8EI64_V_M1_MF4 }, // 1227
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG8EI64_V_M2_MF4 }, // 1228
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG8EI64_V_M1_MF2 }, // 1229
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG8EI64_V_M2_MF2 }, // 1230
|
|
{ 0x8, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG8EI64_V_M4_MF2 }, // 1231
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG8EI8_V_M1_M1 }, // 1232
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG8EI8_V_MF8_M1 }, // 1233
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG8EI8_V_MF4_M1 }, // 1234
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG8EI8_V_MF2_M1 }, // 1235
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF8 }, // 1236
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF4 }, // 1237
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF4 }, // 1238
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF2 }, // 1239
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF2 }, // 1240
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG8EI8_V_MF2_MF2 }, // 1241
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG8EI16_V_M1_M1 }, // 1242
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG8EI16_V_M2_M1 }, // 1243
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG8EI16_V_MF4_M1 }, // 1244
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG8EI16_V_MF2_M1 }, // 1245
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF8 }, // 1246
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF4 }, // 1247
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF4 }, // 1248
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG8EI16_V_M1_MF2 }, // 1249
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF2 }, // 1250
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF2 }, // 1251
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG8EI32_V_M1_M1 }, // 1252
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG8EI32_V_M2_M1 }, // 1253
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG8EI32_V_M4_M1 }, // 1254
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG8EI32_V_MF2_M1 }, // 1255
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF8 }, // 1256
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG8EI32_V_M1_MF4 }, // 1257
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF4 }, // 1258
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG8EI32_V_M1_MF2 }, // 1259
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG8EI32_V_M2_MF2 }, // 1260
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF2 }, // 1261
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG8EI64_V_M1_M1 }, // 1262
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG8EI64_V_M2_M1 }, // 1263
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG8EI64_V_M4_M1 }, // 1264
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG8EI64_V_M8_M1 }, // 1265
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG8EI64_V_M1_MF8 }, // 1266
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG8EI64_V_M1_MF4 }, // 1267
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG8EI64_V_M2_MF4 }, // 1268
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG8EI64_V_M1_MF2 }, // 1269
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG8EI64_V_M2_MF2 }, // 1270
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG8EI64_V_M4_MF2 }, // 1271
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG8EI8_V_M1_M1_MASK }, // 1272
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG8EI8_V_MF8_M1_MASK }, // 1273
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG8EI8_V_MF4_M1_MASK }, // 1274
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG8EI8_V_MF2_M1_MASK }, // 1275
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF8_MASK }, // 1276
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF4_MASK }, // 1277
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF4_MASK }, // 1278
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF2_MASK }, // 1279
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF2_MASK }, // 1280
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG8EI8_V_MF2_MF2_MASK }, // 1281
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG8EI16_V_M1_M1_MASK }, // 1282
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG8EI16_V_M2_M1_MASK }, // 1283
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG8EI16_V_MF4_M1_MASK }, // 1284
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG8EI16_V_MF2_M1_MASK }, // 1285
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF8_MASK }, // 1286
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF4_MASK }, // 1287
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF4_MASK }, // 1288
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG8EI16_V_M1_MF2_MASK }, // 1289
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF2_MASK }, // 1290
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF2_MASK }, // 1291
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG8EI32_V_M1_M1_MASK }, // 1292
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG8EI32_V_M2_M1_MASK }, // 1293
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG8EI32_V_M4_M1_MASK }, // 1294
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG8EI32_V_MF2_M1_MASK }, // 1295
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF8_MASK }, // 1296
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG8EI32_V_M1_MF4_MASK }, // 1297
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF4_MASK }, // 1298
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG8EI32_V_M1_MF2_MASK }, // 1299
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG8EI32_V_M2_MF2_MASK }, // 1300
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF2_MASK }, // 1301
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG8EI64_V_M1_M1_MASK }, // 1302
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG8EI64_V_M2_M1_MASK }, // 1303
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG8EI64_V_M4_M1_MASK }, // 1304
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG8EI64_V_M8_M1_MASK }, // 1305
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG8EI64_V_M1_MF8_MASK }, // 1306
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG8EI64_V_M1_MF4_MASK }, // 1307
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG8EI64_V_M2_MF4_MASK }, // 1308
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG8EI64_V_M1_MF2_MASK }, // 1309
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG8EI64_V_M2_MF2_MASK }, // 1310
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG8EI64_V_M4_MF2_MASK }, // 1311
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG8EI8_V_M1_M1_MASK }, // 1312
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG8EI8_V_MF8_M1_MASK }, // 1313
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG8EI8_V_MF4_M1_MASK }, // 1314
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG8EI8_V_MF2_M1_MASK }, // 1315
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF8_MASK }, // 1316
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF4_MASK }, // 1317
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF4_MASK }, // 1318
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF2_MASK }, // 1319
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF2_MASK }, // 1320
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG8EI8_V_MF2_MF2_MASK }, // 1321
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG8EI16_V_M1_M1_MASK }, // 1322
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG8EI16_V_M2_M1_MASK }, // 1323
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG8EI16_V_MF4_M1_MASK }, // 1324
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG8EI16_V_MF2_M1_MASK }, // 1325
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF8_MASK }, // 1326
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF4_MASK }, // 1327
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF4_MASK }, // 1328
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG8EI16_V_M1_MF2_MASK }, // 1329
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF2_MASK }, // 1330
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF2_MASK }, // 1331
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG8EI32_V_M1_M1_MASK }, // 1332
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG8EI32_V_M2_M1_MASK }, // 1333
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG8EI32_V_M4_M1_MASK }, // 1334
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG8EI32_V_MF2_M1_MASK }, // 1335
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF8_MASK }, // 1336
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG8EI32_V_M1_MF4_MASK }, // 1337
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF4_MASK }, // 1338
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG8EI32_V_M1_MF2_MASK }, // 1339
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG8EI32_V_M2_MF2_MASK }, // 1340
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF2_MASK }, // 1341
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG8EI64_V_M1_M1_MASK }, // 1342
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG8EI64_V_M2_M1_MASK }, // 1343
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG8EI64_V_M4_M1_MASK }, // 1344
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG8EI64_V_M8_M1_MASK }, // 1345
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG8EI64_V_M1_MF8_MASK }, // 1346
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG8EI64_V_M1_MF4_MASK }, // 1347
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG8EI64_V_M2_MF4_MASK }, // 1348
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG8EI64_V_M1_MF2_MASK }, // 1349
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG8EI64_V_M2_MF2_MASK }, // 1350
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG8EI64_V_M4_MF2_MASK }, // 1351
|
|
};
|
|
|
|
const RISCV_VLXSEGPseudo *RISCV_getVLXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedOrderedLog2SEWLMULIndexLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVLXSEGTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVLXTable_IMPL
|
|
static const RISCV_VLX_VSXPseudo RISCVVLXTable[] = {
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXEI8_V_M1_M1 }, // 0
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXEI8_V_MF8_M1 }, // 1
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXEI8_V_MF4_M1 }, // 2
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXEI8_V_MF2_M1 }, // 3
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXEI8_V_M1_M2 }, // 4
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXEI8_V_M2_M2 }, // 5
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXEI8_V_MF4_M2 }, // 6
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXEI8_V_MF2_M2 }, // 7
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVLUXEI8_V_M1_M4 }, // 8
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVLUXEI8_V_M2_M4 }, // 9
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVLUXEI8_V_M4_M4 }, // 10
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVLUXEI8_V_MF2_M4 }, // 11
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x0, PseudoVLUXEI8_V_M1_M8 }, // 12
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x1, PseudoVLUXEI8_V_M2_M8 }, // 13
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x2, PseudoVLUXEI8_V_M4_M8 }, // 14
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x3, PseudoVLUXEI8_V_M8_M8 }, // 15
|
|
{ 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXEI8_V_MF8_MF8 }, // 16
|
|
{ 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXEI8_V_MF8_MF4 }, // 17
|
|
{ 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXEI8_V_MF4_MF4 }, // 18
|
|
{ 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXEI8_V_MF8_MF2 }, // 19
|
|
{ 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXEI8_V_MF4_MF2 }, // 20
|
|
{ 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXEI8_V_MF2_MF2 }, // 21
|
|
{ 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXEI16_V_M1_M1 }, // 22
|
|
{ 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXEI16_V_M2_M1 }, // 23
|
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{ 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXEI16_V_MF4_M1 }, // 24
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{ 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXEI16_V_MF2_M1 }, // 25
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{ 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXEI16_V_M1_M2 }, // 26
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{ 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXEI16_V_M2_M2 }, // 27
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{ 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXEI16_V_M4_M2 }, // 28
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{ 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXEI16_V_MF2_M2 }, // 29
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{ 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVLUXEI16_V_M1_M4 }, // 30
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{ 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVLUXEI16_V_M2_M4 }, // 31
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{ 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVLUXEI16_V_M4_M4 }, // 32
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{ 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVLUXEI16_V_M8_M4 }, // 33
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{ 0x0, 0x0, 0x4, 0x3, 0x1, PseudoVLUXEI16_V_M2_M8 }, // 34
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{ 0x0, 0x0, 0x4, 0x3, 0x2, PseudoVLUXEI16_V_M4_M8 }, // 35
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{ 0x0, 0x0, 0x4, 0x3, 0x3, PseudoVLUXEI16_V_M8_M8 }, // 36
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{ 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXEI16_V_MF4_MF8 }, // 37
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{ 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXEI16_V_MF4_MF4 }, // 38
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{ 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXEI16_V_MF2_MF4 }, // 39
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{ 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXEI16_V_M1_MF2 }, // 40
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{ 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXEI16_V_MF4_MF2 }, // 41
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{ 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXEI16_V_MF2_MF2 }, // 42
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{ 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXEI32_V_M1_M1 }, // 43
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{ 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXEI32_V_M2_M1 }, // 44
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{ 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXEI32_V_M4_M1 }, // 45
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{ 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXEI32_V_MF2_M1 }, // 46
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{ 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXEI32_V_M1_M2 }, // 47
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{ 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXEI32_V_M2_M2 }, // 48
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{ 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXEI32_V_M4_M2 }, // 49
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{ 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXEI32_V_M8_M2 }, // 50
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{ 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVLUXEI32_V_M2_M4 }, // 51
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{ 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVLUXEI32_V_M4_M4 }, // 52
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{ 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVLUXEI32_V_M8_M4 }, // 53
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{ 0x0, 0x0, 0x5, 0x3, 0x2, PseudoVLUXEI32_V_M4_M8 }, // 54
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{ 0x0, 0x0, 0x5, 0x3, 0x3, PseudoVLUXEI32_V_M8_M8 }, // 55
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{ 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXEI32_V_MF2_MF8 }, // 56
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{ 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXEI32_V_M1_MF4 }, // 57
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{ 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXEI32_V_MF2_MF4 }, // 58
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{ 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXEI32_V_M1_MF2 }, // 59
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{ 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXEI32_V_M2_MF2 }, // 60
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{ 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXEI32_V_MF2_MF2 }, // 61
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{ 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXEI64_V_M1_M1 }, // 62
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{ 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXEI64_V_M2_M1 }, // 63
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{ 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXEI64_V_M4_M1 }, // 64
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{ 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXEI64_V_M8_M1 }, // 65
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{ 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXEI64_V_M2_M2 }, // 66
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{ 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXEI64_V_M4_M2 }, // 67
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{ 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXEI64_V_M8_M2 }, // 68
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{ 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVLUXEI64_V_M4_M4 }, // 69
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{ 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVLUXEI64_V_M8_M4 }, // 70
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{ 0x0, 0x0, 0x6, 0x3, 0x3, PseudoVLUXEI64_V_M8_M8 }, // 71
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{ 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXEI64_V_M1_MF8 }, // 72
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{ 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXEI64_V_M1_MF4 }, // 73
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{ 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXEI64_V_M2_MF4 }, // 74
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{ 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXEI64_V_M1_MF2 }, // 75
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{ 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXEI64_V_M2_MF2 }, // 76
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{ 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXEI64_V_M4_MF2 }, // 77
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{ 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXEI8_V_M1_M1 }, // 78
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{ 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXEI8_V_MF8_M1 }, // 79
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{ 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXEI8_V_MF4_M1 }, // 80
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{ 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXEI8_V_MF2_M1 }, // 81
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{ 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXEI8_V_M1_M2 }, // 82
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{ 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXEI8_V_M2_M2 }, // 83
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{ 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXEI8_V_MF4_M2 }, // 84
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{ 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXEI8_V_MF2_M2 }, // 85
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{ 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVLOXEI8_V_M1_M4 }, // 86
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{ 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVLOXEI8_V_M2_M4 }, // 87
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{ 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVLOXEI8_V_M4_M4 }, // 88
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{ 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVLOXEI8_V_MF2_M4 }, // 89
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{ 0x0, 0x1, 0x3, 0x3, 0x0, PseudoVLOXEI8_V_M1_M8 }, // 90
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{ 0x0, 0x1, 0x3, 0x3, 0x1, PseudoVLOXEI8_V_M2_M8 }, // 91
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{ 0x0, 0x1, 0x3, 0x3, 0x2, PseudoVLOXEI8_V_M4_M8 }, // 92
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{ 0x0, 0x1, 0x3, 0x3, 0x3, PseudoVLOXEI8_V_M8_M8 }, // 93
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{ 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXEI8_V_MF8_MF8 }, // 94
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{ 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXEI8_V_MF8_MF4 }, // 95
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{ 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXEI8_V_MF4_MF4 }, // 96
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{ 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXEI8_V_MF8_MF2 }, // 97
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{ 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXEI8_V_MF4_MF2 }, // 98
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{ 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXEI8_V_MF2_MF2 }, // 99
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{ 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXEI16_V_M1_M1 }, // 100
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{ 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXEI16_V_M2_M1 }, // 101
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{ 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXEI16_V_MF4_M1 }, // 102
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{ 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXEI16_V_MF2_M1 }, // 103
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{ 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXEI16_V_M1_M2 }, // 104
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{ 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXEI16_V_M2_M2 }, // 105
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{ 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXEI16_V_M4_M2 }, // 106
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{ 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXEI16_V_MF2_M2 }, // 107
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{ 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVLOXEI16_V_M1_M4 }, // 108
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{ 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVLOXEI16_V_M2_M4 }, // 109
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{ 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVLOXEI16_V_M4_M4 }, // 110
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{ 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVLOXEI16_V_M8_M4 }, // 111
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{ 0x0, 0x1, 0x4, 0x3, 0x1, PseudoVLOXEI16_V_M2_M8 }, // 112
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{ 0x0, 0x1, 0x4, 0x3, 0x2, PseudoVLOXEI16_V_M4_M8 }, // 113
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{ 0x0, 0x1, 0x4, 0x3, 0x3, PseudoVLOXEI16_V_M8_M8 }, // 114
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{ 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXEI16_V_MF4_MF8 }, // 115
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{ 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXEI16_V_MF4_MF4 }, // 116
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{ 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXEI16_V_MF2_MF4 }, // 117
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{ 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXEI16_V_M1_MF2 }, // 118
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{ 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXEI16_V_MF4_MF2 }, // 119
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{ 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXEI16_V_MF2_MF2 }, // 120
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{ 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXEI32_V_M1_M1 }, // 121
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{ 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXEI32_V_M2_M1 }, // 122
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{ 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXEI32_V_M4_M1 }, // 123
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{ 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXEI32_V_MF2_M1 }, // 124
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{ 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXEI32_V_M1_M2 }, // 125
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{ 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXEI32_V_M2_M2 }, // 126
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{ 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXEI32_V_M4_M2 }, // 127
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{ 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXEI32_V_M8_M2 }, // 128
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|
{ 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVLOXEI32_V_M2_M4 }, // 129
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{ 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVLOXEI32_V_M4_M4 }, // 130
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{ 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVLOXEI32_V_M8_M4 }, // 131
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{ 0x0, 0x1, 0x5, 0x3, 0x2, PseudoVLOXEI32_V_M4_M8 }, // 132
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|
{ 0x0, 0x1, 0x5, 0x3, 0x3, PseudoVLOXEI32_V_M8_M8 }, // 133
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{ 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXEI32_V_MF2_MF8 }, // 134
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{ 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXEI32_V_M1_MF4 }, // 135
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|
{ 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXEI32_V_MF2_MF4 }, // 136
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|
{ 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXEI32_V_M1_MF2 }, // 137
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|
{ 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXEI32_V_M2_MF2 }, // 138
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|
{ 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXEI32_V_MF2_MF2 }, // 139
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|
{ 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXEI64_V_M1_M1 }, // 140
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|
{ 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXEI64_V_M2_M1 }, // 141
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{ 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXEI64_V_M4_M1 }, // 142
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|
{ 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXEI64_V_M8_M1 }, // 143
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{ 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXEI64_V_M2_M2 }, // 144
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{ 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXEI64_V_M4_M2 }, // 145
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|
{ 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXEI64_V_M8_M2 }, // 146
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|
{ 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVLOXEI64_V_M4_M4 }, // 147
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|
{ 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVLOXEI64_V_M8_M4 }, // 148
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|
{ 0x0, 0x1, 0x6, 0x3, 0x3, PseudoVLOXEI64_V_M8_M8 }, // 149
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|
{ 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXEI64_V_M1_MF8 }, // 150
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|
{ 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXEI64_V_M1_MF4 }, // 151
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|
{ 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXEI64_V_M2_MF4 }, // 152
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|
{ 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXEI64_V_M1_MF2 }, // 153
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|
{ 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXEI64_V_M2_MF2 }, // 154
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|
{ 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXEI64_V_M4_MF2 }, // 155
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|
{ 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXEI8_V_M1_M1_MASK }, // 156
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|
{ 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXEI8_V_MF8_M1_MASK }, // 157
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|
{ 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXEI8_V_MF4_M1_MASK }, // 158
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|
{ 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXEI8_V_MF2_M1_MASK }, // 159
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|
{ 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXEI8_V_M1_M2_MASK }, // 160
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|
{ 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXEI8_V_M2_M2_MASK }, // 161
|
|
{ 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXEI8_V_MF4_M2_MASK }, // 162
|
|
{ 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXEI8_V_MF2_M2_MASK }, // 163
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVLUXEI8_V_M1_M4_MASK }, // 164
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVLUXEI8_V_M2_M4_MASK }, // 165
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVLUXEI8_V_M4_M4_MASK }, // 166
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVLUXEI8_V_MF2_M4_MASK }, // 167
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x0, PseudoVLUXEI8_V_M1_M8_MASK }, // 168
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x1, PseudoVLUXEI8_V_M2_M8_MASK }, // 169
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x2, PseudoVLUXEI8_V_M4_M8_MASK }, // 170
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x3, PseudoVLUXEI8_V_M8_M8_MASK }, // 171
|
|
{ 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXEI8_V_MF8_MF8_MASK }, // 172
|
|
{ 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXEI8_V_MF8_MF4_MASK }, // 173
|
|
{ 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXEI8_V_MF4_MF4_MASK }, // 174
|
|
{ 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXEI8_V_MF8_MF2_MASK }, // 175
|
|
{ 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXEI8_V_MF4_MF2_MASK }, // 176
|
|
{ 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXEI8_V_MF2_MF2_MASK }, // 177
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXEI16_V_M1_M1_MASK }, // 178
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXEI16_V_M2_M1_MASK }, // 179
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXEI16_V_MF4_M1_MASK }, // 180
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXEI16_V_MF2_M1_MASK }, // 181
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXEI16_V_M1_M2_MASK }, // 182
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXEI16_V_M2_M2_MASK }, // 183
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXEI16_V_M4_M2_MASK }, // 184
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXEI16_V_MF2_M2_MASK }, // 185
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVLUXEI16_V_M1_M4_MASK }, // 186
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVLUXEI16_V_M2_M4_MASK }, // 187
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVLUXEI16_V_M4_M4_MASK }, // 188
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVLUXEI16_V_M8_M4_MASK }, // 189
|
|
{ 0x1, 0x0, 0x4, 0x3, 0x1, PseudoVLUXEI16_V_M2_M8_MASK }, // 190
|
|
{ 0x1, 0x0, 0x4, 0x3, 0x2, PseudoVLUXEI16_V_M4_M8_MASK }, // 191
|
|
{ 0x1, 0x0, 0x4, 0x3, 0x3, PseudoVLUXEI16_V_M8_M8_MASK }, // 192
|
|
{ 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXEI16_V_MF4_MF8_MASK }, // 193
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{ 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXEI16_V_MF4_MF4_MASK }, // 194
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{ 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXEI16_V_MF2_MF4_MASK }, // 195
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{ 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXEI16_V_M1_MF2_MASK }, // 196
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{ 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXEI16_V_MF4_MF2_MASK }, // 197
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{ 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXEI16_V_MF2_MF2_MASK }, // 198
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{ 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXEI32_V_M1_M1_MASK }, // 199
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{ 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXEI32_V_M2_M1_MASK }, // 200
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{ 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXEI32_V_M4_M1_MASK }, // 201
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|
{ 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXEI32_V_MF2_M1_MASK }, // 202
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{ 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXEI32_V_M1_M2_MASK }, // 203
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{ 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXEI32_V_M2_M2_MASK }, // 204
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{ 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXEI32_V_M4_M2_MASK }, // 205
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{ 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXEI32_V_M8_M2_MASK }, // 206
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{ 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVLUXEI32_V_M2_M4_MASK }, // 207
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{ 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVLUXEI32_V_M4_M4_MASK }, // 208
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{ 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVLUXEI32_V_M8_M4_MASK }, // 209
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{ 0x1, 0x0, 0x5, 0x3, 0x2, PseudoVLUXEI32_V_M4_M8_MASK }, // 210
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|
{ 0x1, 0x0, 0x5, 0x3, 0x3, PseudoVLUXEI32_V_M8_M8_MASK }, // 211
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{ 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXEI32_V_MF2_MF8_MASK }, // 212
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|
{ 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXEI32_V_M1_MF4_MASK }, // 213
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{ 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXEI32_V_MF2_MF4_MASK }, // 214
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{ 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXEI32_V_M1_MF2_MASK }, // 215
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{ 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXEI32_V_M2_MF2_MASK }, // 216
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{ 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXEI32_V_MF2_MF2_MASK }, // 217
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{ 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXEI64_V_M1_M1_MASK }, // 218
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{ 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXEI64_V_M2_M1_MASK }, // 219
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{ 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXEI64_V_M4_M1_MASK }, // 220
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{ 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXEI64_V_M8_M1_MASK }, // 221
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{ 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXEI64_V_M2_M2_MASK }, // 222
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{ 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXEI64_V_M4_M2_MASK }, // 223
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{ 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXEI64_V_M8_M2_MASK }, // 224
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{ 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVLUXEI64_V_M4_M4_MASK }, // 225
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|
{ 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVLUXEI64_V_M8_M4_MASK }, // 226
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|
{ 0x1, 0x0, 0x6, 0x3, 0x3, PseudoVLUXEI64_V_M8_M8_MASK }, // 227
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|
{ 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXEI64_V_M1_MF8_MASK }, // 228
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|
{ 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXEI64_V_M1_MF4_MASK }, // 229
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|
{ 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXEI64_V_M2_MF4_MASK }, // 230
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{ 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXEI64_V_M1_MF2_MASK }, // 231
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|
{ 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXEI64_V_M2_MF2_MASK }, // 232
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|
{ 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXEI64_V_M4_MF2_MASK }, // 233
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|
{ 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXEI8_V_M1_M1_MASK }, // 234
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|
{ 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXEI8_V_MF8_M1_MASK }, // 235
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|
{ 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXEI8_V_MF4_M1_MASK }, // 236
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|
{ 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXEI8_V_MF2_M1_MASK }, // 237
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|
{ 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXEI8_V_M1_M2_MASK }, // 238
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|
{ 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXEI8_V_M2_M2_MASK }, // 239
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|
{ 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXEI8_V_MF4_M2_MASK }, // 240
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|
{ 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXEI8_V_MF2_M2_MASK }, // 241
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|
{ 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVLOXEI8_V_M1_M4_MASK }, // 242
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|
{ 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVLOXEI8_V_M2_M4_MASK }, // 243
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|
{ 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVLOXEI8_V_M4_M4_MASK }, // 244
|
|
{ 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVLOXEI8_V_MF2_M4_MASK }, // 245
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x0, PseudoVLOXEI8_V_M1_M8_MASK }, // 246
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x1, PseudoVLOXEI8_V_M2_M8_MASK }, // 247
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x2, PseudoVLOXEI8_V_M4_M8_MASK }, // 248
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x3, PseudoVLOXEI8_V_M8_M8_MASK }, // 249
|
|
{ 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXEI8_V_MF8_MF8_MASK }, // 250
|
|
{ 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXEI8_V_MF8_MF4_MASK }, // 251
|
|
{ 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXEI8_V_MF4_MF4_MASK }, // 252
|
|
{ 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXEI8_V_MF8_MF2_MASK }, // 253
|
|
{ 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXEI8_V_MF4_MF2_MASK }, // 254
|
|
{ 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXEI8_V_MF2_MF2_MASK }, // 255
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXEI16_V_M1_M1_MASK }, // 256
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXEI16_V_M2_M1_MASK }, // 257
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXEI16_V_MF4_M1_MASK }, // 258
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|
{ 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXEI16_V_MF2_M1_MASK }, // 259
|
|
{ 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXEI16_V_M1_M2_MASK }, // 260
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|
{ 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXEI16_V_M2_M2_MASK }, // 261
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|
{ 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXEI16_V_M4_M2_MASK }, // 262
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|
{ 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXEI16_V_MF2_M2_MASK }, // 263
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|
{ 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVLOXEI16_V_M1_M4_MASK }, // 264
|
|
{ 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVLOXEI16_V_M2_M4_MASK }, // 265
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|
{ 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVLOXEI16_V_M4_M4_MASK }, // 266
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|
{ 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVLOXEI16_V_M8_M4_MASK }, // 267
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|
{ 0x1, 0x1, 0x4, 0x3, 0x1, PseudoVLOXEI16_V_M2_M8_MASK }, // 268
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|
{ 0x1, 0x1, 0x4, 0x3, 0x2, PseudoVLOXEI16_V_M4_M8_MASK }, // 269
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|
{ 0x1, 0x1, 0x4, 0x3, 0x3, PseudoVLOXEI16_V_M8_M8_MASK }, // 270
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|
{ 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXEI16_V_MF4_MF8_MASK }, // 271
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|
{ 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXEI16_V_MF4_MF4_MASK }, // 272
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|
{ 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXEI16_V_MF2_MF4_MASK }, // 273
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|
{ 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXEI16_V_M1_MF2_MASK }, // 274
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|
{ 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXEI16_V_MF4_MF2_MASK }, // 275
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|
{ 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXEI16_V_MF2_MF2_MASK }, // 276
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|
{ 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXEI32_V_M1_M1_MASK }, // 277
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|
{ 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXEI32_V_M2_M1_MASK }, // 278
|
|
{ 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXEI32_V_M4_M1_MASK }, // 279
|
|
{ 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXEI32_V_MF2_M1_MASK }, // 280
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|
{ 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXEI32_V_M1_M2_MASK }, // 281
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXEI32_V_M2_M2_MASK }, // 282
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXEI32_V_M4_M2_MASK }, // 283
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXEI32_V_M8_M2_MASK }, // 284
|
|
{ 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVLOXEI32_V_M2_M4_MASK }, // 285
|
|
{ 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVLOXEI32_V_M4_M4_MASK }, // 286
|
|
{ 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVLOXEI32_V_M8_M4_MASK }, // 287
|
|
{ 0x1, 0x1, 0x5, 0x3, 0x2, PseudoVLOXEI32_V_M4_M8_MASK }, // 288
|
|
{ 0x1, 0x1, 0x5, 0x3, 0x3, PseudoVLOXEI32_V_M8_M8_MASK }, // 289
|
|
{ 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXEI32_V_MF2_MF8_MASK }, // 290
|
|
{ 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXEI32_V_M1_MF4_MASK }, // 291
|
|
{ 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXEI32_V_MF2_MF4_MASK }, // 292
|
|
{ 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXEI32_V_M1_MF2_MASK }, // 293
|
|
{ 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXEI32_V_M2_MF2_MASK }, // 294
|
|
{ 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXEI32_V_MF2_MF2_MASK }, // 295
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXEI64_V_M1_M1_MASK }, // 296
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXEI64_V_M2_M1_MASK }, // 297
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXEI64_V_M4_M1_MASK }, // 298
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXEI64_V_M8_M1_MASK }, // 299
|
|
{ 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXEI64_V_M2_M2_MASK }, // 300
|
|
{ 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXEI64_V_M4_M2_MASK }, // 301
|
|
{ 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXEI64_V_M8_M2_MASK }, // 302
|
|
{ 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVLOXEI64_V_M4_M4_MASK }, // 303
|
|
{ 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVLOXEI64_V_M8_M4_MASK }, // 304
|
|
{ 0x1, 0x1, 0x6, 0x3, 0x3, PseudoVLOXEI64_V_M8_M8_MASK }, // 305
|
|
{ 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXEI64_V_M1_MF8_MASK }, // 306
|
|
{ 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXEI64_V_M1_MF4_MASK }, // 307
|
|
{ 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXEI64_V_M2_MF4_MASK }, // 308
|
|
{ 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXEI64_V_M1_MF2_MASK }, // 309
|
|
{ 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXEI64_V_M2_MF2_MASK }, // 310
|
|
{ 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXEI64_V_M4_MF2_MASK }, // 311
|
|
};
|
|
|
|
const RISCV_VLX_VSXPseudo *RISCV_getVLXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedOrderedLog2SEWLMULIndexLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVLXTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVPseudosTable_IMPL
|
|
static const RISCV_PseudoInfo RISCVVPseudosTable[] = {
|
|
{ PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV }, // 0
|
|
{ PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV }, // 1
|
|
{ PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV }, // 2
|
|
{ PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV }, // 3
|
|
{ PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV }, // 4
|
|
{ PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV }, // 5
|
|
{ PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV }, // 6
|
|
{ PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV }, // 7
|
|
{ PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV }, // 8
|
|
{ PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV }, // 9
|
|
{ PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX }, // 10
|
|
{ PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX }, // 11
|
|
{ PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX }, // 12
|
|
{ PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX }, // 13
|
|
{ PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX }, // 14
|
|
{ PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX }, // 15
|
|
{ PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX }, // 16
|
|
{ PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX }, // 17
|
|
{ PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX }, // 18
|
|
{ PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX }, // 19
|
|
{ PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX }, // 20
|
|
{ PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX }, // 21
|
|
{ PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX }, // 22
|
|
{ PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX }, // 23
|
|
{ PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX }, // 24
|
|
{ PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX }, // 25
|
|
{ PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX }, // 26
|
|
{ PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX }, // 27
|
|
{ PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX }, // 28
|
|
{ PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX }, // 29
|
|
{ PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV }, // 30
|
|
{ PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV }, // 31
|
|
{ PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV }, // 32
|
|
{ PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV }, // 33
|
|
{ PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV }, // 34
|
|
{ PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV }, // 35
|
|
{ PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV }, // 36
|
|
{ PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV }, // 37
|
|
{ PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV }, // 38
|
|
{ PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV }, // 39
|
|
{ PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX }, // 40
|
|
{ PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX }, // 41
|
|
{ PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX }, // 42
|
|
{ PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX }, // 43
|
|
{ PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX }, // 44
|
|
{ PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX }, // 45
|
|
{ PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX }, // 46
|
|
{ PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX }, // 47
|
|
{ PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX }, // 48
|
|
{ PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX }, // 49
|
|
{ PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV }, // 50
|
|
{ PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV }, // 51
|
|
{ PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV }, // 52
|
|
{ PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV }, // 53
|
|
{ PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV }, // 54
|
|
{ PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV }, // 55
|
|
{ PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV }, // 56
|
|
{ PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV }, // 57
|
|
{ PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV }, // 58
|
|
{ PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV }, // 59
|
|
{ PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX }, // 60
|
|
{ PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX }, // 61
|
|
{ PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX }, // 62
|
|
{ PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX }, // 63
|
|
{ PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX }, // 64
|
|
{ PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX }, // 65
|
|
{ PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX }, // 66
|
|
{ PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX }, // 67
|
|
{ PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX }, // 68
|
|
{ PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX }, // 69
|
|
{ PseudoVAADDU_VV_M1, VAADDU_VV }, // 70
|
|
{ PseudoVAADDU_VV_M1_MASK, VAADDU_VV }, // 71
|
|
{ PseudoVAADDU_VV_M2, VAADDU_VV }, // 72
|
|
{ PseudoVAADDU_VV_M2_MASK, VAADDU_VV }, // 73
|
|
{ PseudoVAADDU_VV_M4, VAADDU_VV }, // 74
|
|
{ PseudoVAADDU_VV_M4_MASK, VAADDU_VV }, // 75
|
|
{ PseudoVAADDU_VV_M8, VAADDU_VV }, // 76
|
|
{ PseudoVAADDU_VV_M8_MASK, VAADDU_VV }, // 77
|
|
{ PseudoVAADDU_VV_MF2, VAADDU_VV }, // 78
|
|
{ PseudoVAADDU_VV_MF2_MASK, VAADDU_VV }, // 79
|
|
{ PseudoVAADDU_VV_MF4, VAADDU_VV }, // 80
|
|
{ PseudoVAADDU_VV_MF4_MASK, VAADDU_VV }, // 81
|
|
{ PseudoVAADDU_VV_MF8, VAADDU_VV }, // 82
|
|
{ PseudoVAADDU_VV_MF8_MASK, VAADDU_VV }, // 83
|
|
{ PseudoVAADDU_VX_M1, VAADDU_VX }, // 84
|
|
{ PseudoVAADDU_VX_M1_MASK, VAADDU_VX }, // 85
|
|
{ PseudoVAADDU_VX_M2, VAADDU_VX }, // 86
|
|
{ PseudoVAADDU_VX_M2_MASK, VAADDU_VX }, // 87
|
|
{ PseudoVAADDU_VX_M4, VAADDU_VX }, // 88
|
|
{ PseudoVAADDU_VX_M4_MASK, VAADDU_VX }, // 89
|
|
{ PseudoVAADDU_VX_M8, VAADDU_VX }, // 90
|
|
{ PseudoVAADDU_VX_M8_MASK, VAADDU_VX }, // 91
|
|
{ PseudoVAADDU_VX_MF2, VAADDU_VX }, // 92
|
|
{ PseudoVAADDU_VX_MF2_MASK, VAADDU_VX }, // 93
|
|
{ PseudoVAADDU_VX_MF4, VAADDU_VX }, // 94
|
|
{ PseudoVAADDU_VX_MF4_MASK, VAADDU_VX }, // 95
|
|
{ PseudoVAADDU_VX_MF8, VAADDU_VX }, // 96
|
|
{ PseudoVAADDU_VX_MF8_MASK, VAADDU_VX }, // 97
|
|
{ PseudoVAADD_VV_M1, VAADD_VV }, // 98
|
|
{ PseudoVAADD_VV_M1_MASK, VAADD_VV }, // 99
|
|
{ PseudoVAADD_VV_M2, VAADD_VV }, // 100
|
|
{ PseudoVAADD_VV_M2_MASK, VAADD_VV }, // 101
|
|
{ PseudoVAADD_VV_M4, VAADD_VV }, // 102
|
|
{ PseudoVAADD_VV_M4_MASK, VAADD_VV }, // 103
|
|
{ PseudoVAADD_VV_M8, VAADD_VV }, // 104
|
|
{ PseudoVAADD_VV_M8_MASK, VAADD_VV }, // 105
|
|
{ PseudoVAADD_VV_MF2, VAADD_VV }, // 106
|
|
{ PseudoVAADD_VV_MF2_MASK, VAADD_VV }, // 107
|
|
{ PseudoVAADD_VV_MF4, VAADD_VV }, // 108
|
|
{ PseudoVAADD_VV_MF4_MASK, VAADD_VV }, // 109
|
|
{ PseudoVAADD_VV_MF8, VAADD_VV }, // 110
|
|
{ PseudoVAADD_VV_MF8_MASK, VAADD_VV }, // 111
|
|
{ PseudoVAADD_VX_M1, VAADD_VX }, // 112
|
|
{ PseudoVAADD_VX_M1_MASK, VAADD_VX }, // 113
|
|
{ PseudoVAADD_VX_M2, VAADD_VX }, // 114
|
|
{ PseudoVAADD_VX_M2_MASK, VAADD_VX }, // 115
|
|
{ PseudoVAADD_VX_M4, VAADD_VX }, // 116
|
|
{ PseudoVAADD_VX_M4_MASK, VAADD_VX }, // 117
|
|
{ PseudoVAADD_VX_M8, VAADD_VX }, // 118
|
|
{ PseudoVAADD_VX_M8_MASK, VAADD_VX }, // 119
|
|
{ PseudoVAADD_VX_MF2, VAADD_VX }, // 120
|
|
{ PseudoVAADD_VX_MF2_MASK, VAADD_VX }, // 121
|
|
{ PseudoVAADD_VX_MF4, VAADD_VX }, // 122
|
|
{ PseudoVAADD_VX_MF4_MASK, VAADD_VX }, // 123
|
|
{ PseudoVAADD_VX_MF8, VAADD_VX }, // 124
|
|
{ PseudoVAADD_VX_MF8_MASK, VAADD_VX }, // 125
|
|
{ PseudoVADC_VIM_M1, VADC_VIM }, // 126
|
|
{ PseudoVADC_VIM_M2, VADC_VIM }, // 127
|
|
{ PseudoVADC_VIM_M4, VADC_VIM }, // 128
|
|
{ PseudoVADC_VIM_M8, VADC_VIM }, // 129
|
|
{ PseudoVADC_VIM_MF2, VADC_VIM }, // 130
|
|
{ PseudoVADC_VIM_MF4, VADC_VIM }, // 131
|
|
{ PseudoVADC_VIM_MF8, VADC_VIM }, // 132
|
|
{ PseudoVADC_VVM_M1, VADC_VVM }, // 133
|
|
{ PseudoVADC_VVM_M2, VADC_VVM }, // 134
|
|
{ PseudoVADC_VVM_M4, VADC_VVM }, // 135
|
|
{ PseudoVADC_VVM_M8, VADC_VVM }, // 136
|
|
{ PseudoVADC_VVM_MF2, VADC_VVM }, // 137
|
|
{ PseudoVADC_VVM_MF4, VADC_VVM }, // 138
|
|
{ PseudoVADC_VVM_MF8, VADC_VVM }, // 139
|
|
{ PseudoVADC_VXM_M1, VADC_VXM }, // 140
|
|
{ PseudoVADC_VXM_M2, VADC_VXM }, // 141
|
|
{ PseudoVADC_VXM_M4, VADC_VXM }, // 142
|
|
{ PseudoVADC_VXM_M8, VADC_VXM }, // 143
|
|
{ PseudoVADC_VXM_MF2, VADC_VXM }, // 144
|
|
{ PseudoVADC_VXM_MF4, VADC_VXM }, // 145
|
|
{ PseudoVADC_VXM_MF8, VADC_VXM }, // 146
|
|
{ PseudoVADD_VI_M1, VADD_VI }, // 147
|
|
{ PseudoVADD_VI_M1_MASK, VADD_VI }, // 148
|
|
{ PseudoVADD_VI_M2, VADD_VI }, // 149
|
|
{ PseudoVADD_VI_M2_MASK, VADD_VI }, // 150
|
|
{ PseudoVADD_VI_M4, VADD_VI }, // 151
|
|
{ PseudoVADD_VI_M4_MASK, VADD_VI }, // 152
|
|
{ PseudoVADD_VI_M8, VADD_VI }, // 153
|
|
{ PseudoVADD_VI_M8_MASK, VADD_VI }, // 154
|
|
{ PseudoVADD_VI_MF2, VADD_VI }, // 155
|
|
{ PseudoVADD_VI_MF2_MASK, VADD_VI }, // 156
|
|
{ PseudoVADD_VI_MF4, VADD_VI }, // 157
|
|
{ PseudoVADD_VI_MF4_MASK, VADD_VI }, // 158
|
|
{ PseudoVADD_VI_MF8, VADD_VI }, // 159
|
|
{ PseudoVADD_VI_MF8_MASK, VADD_VI }, // 160
|
|
{ PseudoVADD_VV_M1, VADD_VV }, // 161
|
|
{ PseudoVADD_VV_M1_MASK, VADD_VV }, // 162
|
|
{ PseudoVADD_VV_M2, VADD_VV }, // 163
|
|
{ PseudoVADD_VV_M2_MASK, VADD_VV }, // 164
|
|
{ PseudoVADD_VV_M4, VADD_VV }, // 165
|
|
{ PseudoVADD_VV_M4_MASK, VADD_VV }, // 166
|
|
{ PseudoVADD_VV_M8, VADD_VV }, // 167
|
|
{ PseudoVADD_VV_M8_MASK, VADD_VV }, // 168
|
|
{ PseudoVADD_VV_MF2, VADD_VV }, // 169
|
|
{ PseudoVADD_VV_MF2_MASK, VADD_VV }, // 170
|
|
{ PseudoVADD_VV_MF4, VADD_VV }, // 171
|
|
{ PseudoVADD_VV_MF4_MASK, VADD_VV }, // 172
|
|
{ PseudoVADD_VV_MF8, VADD_VV }, // 173
|
|
{ PseudoVADD_VV_MF8_MASK, VADD_VV }, // 174
|
|
{ PseudoVADD_VX_M1, VADD_VX }, // 175
|
|
{ PseudoVADD_VX_M1_MASK, VADD_VX }, // 176
|
|
{ PseudoVADD_VX_M2, VADD_VX }, // 177
|
|
{ PseudoVADD_VX_M2_MASK, VADD_VX }, // 178
|
|
{ PseudoVADD_VX_M4, VADD_VX }, // 179
|
|
{ PseudoVADD_VX_M4_MASK, VADD_VX }, // 180
|
|
{ PseudoVADD_VX_M8, VADD_VX }, // 181
|
|
{ PseudoVADD_VX_M8_MASK, VADD_VX }, // 182
|
|
{ PseudoVADD_VX_MF2, VADD_VX }, // 183
|
|
{ PseudoVADD_VX_MF2_MASK, VADD_VX }, // 184
|
|
{ PseudoVADD_VX_MF4, VADD_VX }, // 185
|
|
{ PseudoVADD_VX_MF4_MASK, VADD_VX }, // 186
|
|
{ PseudoVADD_VX_MF8, VADD_VX }, // 187
|
|
{ PseudoVADD_VX_MF8_MASK, VADD_VX }, // 188
|
|
{ PseudoVAESDF_VS_M1_M1, VAESDF_VS }, // 189
|
|
{ PseudoVAESDF_VS_M1_MF2, VAESDF_VS }, // 190
|
|
{ PseudoVAESDF_VS_M1_MF4, VAESDF_VS }, // 191
|
|
{ PseudoVAESDF_VS_M1_MF8, VAESDF_VS }, // 192
|
|
{ PseudoVAESDF_VS_M2_M1, VAESDF_VS }, // 193
|
|
{ PseudoVAESDF_VS_M2_M2, VAESDF_VS }, // 194
|
|
{ PseudoVAESDF_VS_M2_MF2, VAESDF_VS }, // 195
|
|
{ PseudoVAESDF_VS_M2_MF4, VAESDF_VS }, // 196
|
|
{ PseudoVAESDF_VS_M2_MF8, VAESDF_VS }, // 197
|
|
{ PseudoVAESDF_VS_M4_M1, VAESDF_VS }, // 198
|
|
{ PseudoVAESDF_VS_M4_M2, VAESDF_VS }, // 199
|
|
{ PseudoVAESDF_VS_M4_M4, VAESDF_VS }, // 200
|
|
{ PseudoVAESDF_VS_M4_MF2, VAESDF_VS }, // 201
|
|
{ PseudoVAESDF_VS_M4_MF4, VAESDF_VS }, // 202
|
|
{ PseudoVAESDF_VS_M4_MF8, VAESDF_VS }, // 203
|
|
{ PseudoVAESDF_VS_M8_M1, VAESDF_VS }, // 204
|
|
{ PseudoVAESDF_VS_M8_M2, VAESDF_VS }, // 205
|
|
{ PseudoVAESDF_VS_M8_M4, VAESDF_VS }, // 206
|
|
{ PseudoVAESDF_VS_M8_MF2, VAESDF_VS }, // 207
|
|
{ PseudoVAESDF_VS_M8_MF4, VAESDF_VS }, // 208
|
|
{ PseudoVAESDF_VS_M8_MF8, VAESDF_VS }, // 209
|
|
{ PseudoVAESDF_VS_MF2_MF2, VAESDF_VS }, // 210
|
|
{ PseudoVAESDF_VS_MF2_MF4, VAESDF_VS }, // 211
|
|
{ PseudoVAESDF_VS_MF2_MF8, VAESDF_VS }, // 212
|
|
{ PseudoVAESDF_VV_M1, VAESDF_VV }, // 213
|
|
{ PseudoVAESDF_VV_M2, VAESDF_VV }, // 214
|
|
{ PseudoVAESDF_VV_M4, VAESDF_VV }, // 215
|
|
{ PseudoVAESDF_VV_M8, VAESDF_VV }, // 216
|
|
{ PseudoVAESDF_VV_MF2, VAESDF_VV }, // 217
|
|
{ PseudoVAESDM_VS_M1_M1, VAESDM_VS }, // 218
|
|
{ PseudoVAESDM_VS_M1_MF2, VAESDM_VS }, // 219
|
|
{ PseudoVAESDM_VS_M1_MF4, VAESDM_VS }, // 220
|
|
{ PseudoVAESDM_VS_M1_MF8, VAESDM_VS }, // 221
|
|
{ PseudoVAESDM_VS_M2_M1, VAESDM_VS }, // 222
|
|
{ PseudoVAESDM_VS_M2_M2, VAESDM_VS }, // 223
|
|
{ PseudoVAESDM_VS_M2_MF2, VAESDM_VS }, // 224
|
|
{ PseudoVAESDM_VS_M2_MF4, VAESDM_VS }, // 225
|
|
{ PseudoVAESDM_VS_M2_MF8, VAESDM_VS }, // 226
|
|
{ PseudoVAESDM_VS_M4_M1, VAESDM_VS }, // 227
|
|
{ PseudoVAESDM_VS_M4_M2, VAESDM_VS }, // 228
|
|
{ PseudoVAESDM_VS_M4_M4, VAESDM_VS }, // 229
|
|
{ PseudoVAESDM_VS_M4_MF2, VAESDM_VS }, // 230
|
|
{ PseudoVAESDM_VS_M4_MF4, VAESDM_VS }, // 231
|
|
{ PseudoVAESDM_VS_M4_MF8, VAESDM_VS }, // 232
|
|
{ PseudoVAESDM_VS_M8_M1, VAESDM_VS }, // 233
|
|
{ PseudoVAESDM_VS_M8_M2, VAESDM_VS }, // 234
|
|
{ PseudoVAESDM_VS_M8_M4, VAESDM_VS }, // 235
|
|
{ PseudoVAESDM_VS_M8_MF2, VAESDM_VS }, // 236
|
|
{ PseudoVAESDM_VS_M8_MF4, VAESDM_VS }, // 237
|
|
{ PseudoVAESDM_VS_M8_MF8, VAESDM_VS }, // 238
|
|
{ PseudoVAESDM_VS_MF2_MF2, VAESDM_VS }, // 239
|
|
{ PseudoVAESDM_VS_MF2_MF4, VAESDM_VS }, // 240
|
|
{ PseudoVAESDM_VS_MF2_MF8, VAESDM_VS }, // 241
|
|
{ PseudoVAESDM_VV_M1, VAESDM_VV }, // 242
|
|
{ PseudoVAESDM_VV_M2, VAESDM_VV }, // 243
|
|
{ PseudoVAESDM_VV_M4, VAESDM_VV }, // 244
|
|
{ PseudoVAESDM_VV_M8, VAESDM_VV }, // 245
|
|
{ PseudoVAESDM_VV_MF2, VAESDM_VV }, // 246
|
|
{ PseudoVAESEF_VS_M1_M1, VAESEF_VS }, // 247
|
|
{ PseudoVAESEF_VS_M1_MF2, VAESEF_VS }, // 248
|
|
{ PseudoVAESEF_VS_M1_MF4, VAESEF_VS }, // 249
|
|
{ PseudoVAESEF_VS_M1_MF8, VAESEF_VS }, // 250
|
|
{ PseudoVAESEF_VS_M2_M1, VAESEF_VS }, // 251
|
|
{ PseudoVAESEF_VS_M2_M2, VAESEF_VS }, // 252
|
|
{ PseudoVAESEF_VS_M2_MF2, VAESEF_VS }, // 253
|
|
{ PseudoVAESEF_VS_M2_MF4, VAESEF_VS }, // 254
|
|
{ PseudoVAESEF_VS_M2_MF8, VAESEF_VS }, // 255
|
|
{ PseudoVAESEF_VS_M4_M1, VAESEF_VS }, // 256
|
|
{ PseudoVAESEF_VS_M4_M2, VAESEF_VS }, // 257
|
|
{ PseudoVAESEF_VS_M4_M4, VAESEF_VS }, // 258
|
|
{ PseudoVAESEF_VS_M4_MF2, VAESEF_VS }, // 259
|
|
{ PseudoVAESEF_VS_M4_MF4, VAESEF_VS }, // 260
|
|
{ PseudoVAESEF_VS_M4_MF8, VAESEF_VS }, // 261
|
|
{ PseudoVAESEF_VS_M8_M1, VAESEF_VS }, // 262
|
|
{ PseudoVAESEF_VS_M8_M2, VAESEF_VS }, // 263
|
|
{ PseudoVAESEF_VS_M8_M4, VAESEF_VS }, // 264
|
|
{ PseudoVAESEF_VS_M8_MF2, VAESEF_VS }, // 265
|
|
{ PseudoVAESEF_VS_M8_MF4, VAESEF_VS }, // 266
|
|
{ PseudoVAESEF_VS_M8_MF8, VAESEF_VS }, // 267
|
|
{ PseudoVAESEF_VS_MF2_MF2, VAESEF_VS }, // 268
|
|
{ PseudoVAESEF_VS_MF2_MF4, VAESEF_VS }, // 269
|
|
{ PseudoVAESEF_VS_MF2_MF8, VAESEF_VS }, // 270
|
|
{ PseudoVAESEF_VV_M1, VAESEF_VV }, // 271
|
|
{ PseudoVAESEF_VV_M2, VAESEF_VV }, // 272
|
|
{ PseudoVAESEF_VV_M4, VAESEF_VV }, // 273
|
|
{ PseudoVAESEF_VV_M8, VAESEF_VV }, // 274
|
|
{ PseudoVAESEF_VV_MF2, VAESEF_VV }, // 275
|
|
{ PseudoVAESEM_VS_M1_M1, VAESEM_VS }, // 276
|
|
{ PseudoVAESEM_VS_M1_MF2, VAESEM_VS }, // 277
|
|
{ PseudoVAESEM_VS_M1_MF4, VAESEM_VS }, // 278
|
|
{ PseudoVAESEM_VS_M1_MF8, VAESEM_VS }, // 279
|
|
{ PseudoVAESEM_VS_M2_M1, VAESEM_VS }, // 280
|
|
{ PseudoVAESEM_VS_M2_M2, VAESEM_VS }, // 281
|
|
{ PseudoVAESEM_VS_M2_MF2, VAESEM_VS }, // 282
|
|
{ PseudoVAESEM_VS_M2_MF4, VAESEM_VS }, // 283
|
|
{ PseudoVAESEM_VS_M2_MF8, VAESEM_VS }, // 284
|
|
{ PseudoVAESEM_VS_M4_M1, VAESEM_VS }, // 285
|
|
{ PseudoVAESEM_VS_M4_M2, VAESEM_VS }, // 286
|
|
{ PseudoVAESEM_VS_M4_M4, VAESEM_VS }, // 287
|
|
{ PseudoVAESEM_VS_M4_MF2, VAESEM_VS }, // 288
|
|
{ PseudoVAESEM_VS_M4_MF4, VAESEM_VS }, // 289
|
|
{ PseudoVAESEM_VS_M4_MF8, VAESEM_VS }, // 290
|
|
{ PseudoVAESEM_VS_M8_M1, VAESEM_VS }, // 291
|
|
{ PseudoVAESEM_VS_M8_M2, VAESEM_VS }, // 292
|
|
{ PseudoVAESEM_VS_M8_M4, VAESEM_VS }, // 293
|
|
{ PseudoVAESEM_VS_M8_MF2, VAESEM_VS }, // 294
|
|
{ PseudoVAESEM_VS_M8_MF4, VAESEM_VS }, // 295
|
|
{ PseudoVAESEM_VS_M8_MF8, VAESEM_VS }, // 296
|
|
{ PseudoVAESEM_VS_MF2_MF2, VAESEM_VS }, // 297
|
|
{ PseudoVAESEM_VS_MF2_MF4, VAESEM_VS }, // 298
|
|
{ PseudoVAESEM_VS_MF2_MF8, VAESEM_VS }, // 299
|
|
{ PseudoVAESEM_VV_M1, VAESEM_VV }, // 300
|
|
{ PseudoVAESEM_VV_M2, VAESEM_VV }, // 301
|
|
{ PseudoVAESEM_VV_M4, VAESEM_VV }, // 302
|
|
{ PseudoVAESEM_VV_M8, VAESEM_VV }, // 303
|
|
{ PseudoVAESEM_VV_MF2, VAESEM_VV }, // 304
|
|
{ PseudoVAESKF1_VI_M1, VAESKF1_VI }, // 305
|
|
{ PseudoVAESKF1_VI_M2, VAESKF1_VI }, // 306
|
|
{ PseudoVAESKF1_VI_M4, VAESKF1_VI }, // 307
|
|
{ PseudoVAESKF1_VI_M8, VAESKF1_VI }, // 308
|
|
{ PseudoVAESKF1_VI_MF2, VAESKF1_VI }, // 309
|
|
{ PseudoVAESKF2_VI_M1, VAESKF2_VI }, // 310
|
|
{ PseudoVAESKF2_VI_M2, VAESKF2_VI }, // 311
|
|
{ PseudoVAESKF2_VI_M4, VAESKF2_VI }, // 312
|
|
{ PseudoVAESKF2_VI_M8, VAESKF2_VI }, // 313
|
|
{ PseudoVAESKF2_VI_MF2, VAESKF2_VI }, // 314
|
|
{ PseudoVAESZ_VS_M1_M1, VAESZ_VS }, // 315
|
|
{ PseudoVAESZ_VS_M1_MF2, VAESZ_VS }, // 316
|
|
{ PseudoVAESZ_VS_M1_MF4, VAESZ_VS }, // 317
|
|
{ PseudoVAESZ_VS_M1_MF8, VAESZ_VS }, // 318
|
|
{ PseudoVAESZ_VS_M2_M1, VAESZ_VS }, // 319
|
|
{ PseudoVAESZ_VS_M2_M2, VAESZ_VS }, // 320
|
|
{ PseudoVAESZ_VS_M2_MF2, VAESZ_VS }, // 321
|
|
{ PseudoVAESZ_VS_M2_MF4, VAESZ_VS }, // 322
|
|
{ PseudoVAESZ_VS_M2_MF8, VAESZ_VS }, // 323
|
|
{ PseudoVAESZ_VS_M4_M1, VAESZ_VS }, // 324
|
|
{ PseudoVAESZ_VS_M4_M2, VAESZ_VS }, // 325
|
|
{ PseudoVAESZ_VS_M4_M4, VAESZ_VS }, // 326
|
|
{ PseudoVAESZ_VS_M4_MF2, VAESZ_VS }, // 327
|
|
{ PseudoVAESZ_VS_M4_MF4, VAESZ_VS }, // 328
|
|
{ PseudoVAESZ_VS_M4_MF8, VAESZ_VS }, // 329
|
|
{ PseudoVAESZ_VS_M8_M1, VAESZ_VS }, // 330
|
|
{ PseudoVAESZ_VS_M8_M2, VAESZ_VS }, // 331
|
|
{ PseudoVAESZ_VS_M8_M4, VAESZ_VS }, // 332
|
|
{ PseudoVAESZ_VS_M8_MF2, VAESZ_VS }, // 333
|
|
{ PseudoVAESZ_VS_M8_MF4, VAESZ_VS }, // 334
|
|
{ PseudoVAESZ_VS_M8_MF8, VAESZ_VS }, // 335
|
|
{ PseudoVAESZ_VS_MF2_MF2, VAESZ_VS }, // 336
|
|
{ PseudoVAESZ_VS_MF2_MF4, VAESZ_VS }, // 337
|
|
{ PseudoVAESZ_VS_MF2_MF8, VAESZ_VS }, // 338
|
|
{ PseudoVANDN_VV_M1, VANDN_VV }, // 339
|
|
{ PseudoVANDN_VV_M1_MASK, VANDN_VV }, // 340
|
|
{ PseudoVANDN_VV_M2, VANDN_VV }, // 341
|
|
{ PseudoVANDN_VV_M2_MASK, VANDN_VV }, // 342
|
|
{ PseudoVANDN_VV_M4, VANDN_VV }, // 343
|
|
{ PseudoVANDN_VV_M4_MASK, VANDN_VV }, // 344
|
|
{ PseudoVANDN_VV_M8, VANDN_VV }, // 345
|
|
{ PseudoVANDN_VV_M8_MASK, VANDN_VV }, // 346
|
|
{ PseudoVANDN_VV_MF2, VANDN_VV }, // 347
|
|
{ PseudoVANDN_VV_MF2_MASK, VANDN_VV }, // 348
|
|
{ PseudoVANDN_VV_MF4, VANDN_VV }, // 349
|
|
{ PseudoVANDN_VV_MF4_MASK, VANDN_VV }, // 350
|
|
{ PseudoVANDN_VV_MF8, VANDN_VV }, // 351
|
|
{ PseudoVANDN_VV_MF8_MASK, VANDN_VV }, // 352
|
|
{ PseudoVANDN_VX_M1, VANDN_VX }, // 353
|
|
{ PseudoVANDN_VX_M1_MASK, VANDN_VX }, // 354
|
|
{ PseudoVANDN_VX_M2, VANDN_VX }, // 355
|
|
{ PseudoVANDN_VX_M2_MASK, VANDN_VX }, // 356
|
|
{ PseudoVANDN_VX_M4, VANDN_VX }, // 357
|
|
{ PseudoVANDN_VX_M4_MASK, VANDN_VX }, // 358
|
|
{ PseudoVANDN_VX_M8, VANDN_VX }, // 359
|
|
{ PseudoVANDN_VX_M8_MASK, VANDN_VX }, // 360
|
|
{ PseudoVANDN_VX_MF2, VANDN_VX }, // 361
|
|
{ PseudoVANDN_VX_MF2_MASK, VANDN_VX }, // 362
|
|
{ PseudoVANDN_VX_MF4, VANDN_VX }, // 363
|
|
{ PseudoVANDN_VX_MF4_MASK, VANDN_VX }, // 364
|
|
{ PseudoVANDN_VX_MF8, VANDN_VX }, // 365
|
|
{ PseudoVANDN_VX_MF8_MASK, VANDN_VX }, // 366
|
|
{ PseudoVAND_VI_M1, VAND_VI }, // 367
|
|
{ PseudoVAND_VI_M1_MASK, VAND_VI }, // 368
|
|
{ PseudoVAND_VI_M2, VAND_VI }, // 369
|
|
{ PseudoVAND_VI_M2_MASK, VAND_VI }, // 370
|
|
{ PseudoVAND_VI_M4, VAND_VI }, // 371
|
|
{ PseudoVAND_VI_M4_MASK, VAND_VI }, // 372
|
|
{ PseudoVAND_VI_M8, VAND_VI }, // 373
|
|
{ PseudoVAND_VI_M8_MASK, VAND_VI }, // 374
|
|
{ PseudoVAND_VI_MF2, VAND_VI }, // 375
|
|
{ PseudoVAND_VI_MF2_MASK, VAND_VI }, // 376
|
|
{ PseudoVAND_VI_MF4, VAND_VI }, // 377
|
|
{ PseudoVAND_VI_MF4_MASK, VAND_VI }, // 378
|
|
{ PseudoVAND_VI_MF8, VAND_VI }, // 379
|
|
{ PseudoVAND_VI_MF8_MASK, VAND_VI }, // 380
|
|
{ PseudoVAND_VV_M1, VAND_VV }, // 381
|
|
{ PseudoVAND_VV_M1_MASK, VAND_VV }, // 382
|
|
{ PseudoVAND_VV_M2, VAND_VV }, // 383
|
|
{ PseudoVAND_VV_M2_MASK, VAND_VV }, // 384
|
|
{ PseudoVAND_VV_M4, VAND_VV }, // 385
|
|
{ PseudoVAND_VV_M4_MASK, VAND_VV }, // 386
|
|
{ PseudoVAND_VV_M8, VAND_VV }, // 387
|
|
{ PseudoVAND_VV_M8_MASK, VAND_VV }, // 388
|
|
{ PseudoVAND_VV_MF2, VAND_VV }, // 389
|
|
{ PseudoVAND_VV_MF2_MASK, VAND_VV }, // 390
|
|
{ PseudoVAND_VV_MF4, VAND_VV }, // 391
|
|
{ PseudoVAND_VV_MF4_MASK, VAND_VV }, // 392
|
|
{ PseudoVAND_VV_MF8, VAND_VV }, // 393
|
|
{ PseudoVAND_VV_MF8_MASK, VAND_VV }, // 394
|
|
{ PseudoVAND_VX_M1, VAND_VX }, // 395
|
|
{ PseudoVAND_VX_M1_MASK, VAND_VX }, // 396
|
|
{ PseudoVAND_VX_M2, VAND_VX }, // 397
|
|
{ PseudoVAND_VX_M2_MASK, VAND_VX }, // 398
|
|
{ PseudoVAND_VX_M4, VAND_VX }, // 399
|
|
{ PseudoVAND_VX_M4_MASK, VAND_VX }, // 400
|
|
{ PseudoVAND_VX_M8, VAND_VX }, // 401
|
|
{ PseudoVAND_VX_M8_MASK, VAND_VX }, // 402
|
|
{ PseudoVAND_VX_MF2, VAND_VX }, // 403
|
|
{ PseudoVAND_VX_MF2_MASK, VAND_VX }, // 404
|
|
{ PseudoVAND_VX_MF4, VAND_VX }, // 405
|
|
{ PseudoVAND_VX_MF4_MASK, VAND_VX }, // 406
|
|
{ PseudoVAND_VX_MF8, VAND_VX }, // 407
|
|
{ PseudoVAND_VX_MF8_MASK, VAND_VX }, // 408
|
|
{ PseudoVASUBU_VV_M1, VASUBU_VV }, // 409
|
|
{ PseudoVASUBU_VV_M1_MASK, VASUBU_VV }, // 410
|
|
{ PseudoVASUBU_VV_M2, VASUBU_VV }, // 411
|
|
{ PseudoVASUBU_VV_M2_MASK, VASUBU_VV }, // 412
|
|
{ PseudoVASUBU_VV_M4, VASUBU_VV }, // 413
|
|
{ PseudoVASUBU_VV_M4_MASK, VASUBU_VV }, // 414
|
|
{ PseudoVASUBU_VV_M8, VASUBU_VV }, // 415
|
|
{ PseudoVASUBU_VV_M8_MASK, VASUBU_VV }, // 416
|
|
{ PseudoVASUBU_VV_MF2, VASUBU_VV }, // 417
|
|
{ PseudoVASUBU_VV_MF2_MASK, VASUBU_VV }, // 418
|
|
{ PseudoVASUBU_VV_MF4, VASUBU_VV }, // 419
|
|
{ PseudoVASUBU_VV_MF4_MASK, VASUBU_VV }, // 420
|
|
{ PseudoVASUBU_VV_MF8, VASUBU_VV }, // 421
|
|
{ PseudoVASUBU_VV_MF8_MASK, VASUBU_VV }, // 422
|
|
{ PseudoVASUBU_VX_M1, VASUBU_VX }, // 423
|
|
{ PseudoVASUBU_VX_M1_MASK, VASUBU_VX }, // 424
|
|
{ PseudoVASUBU_VX_M2, VASUBU_VX }, // 425
|
|
{ PseudoVASUBU_VX_M2_MASK, VASUBU_VX }, // 426
|
|
{ PseudoVASUBU_VX_M4, VASUBU_VX }, // 427
|
|
{ PseudoVASUBU_VX_M4_MASK, VASUBU_VX }, // 428
|
|
{ PseudoVASUBU_VX_M8, VASUBU_VX }, // 429
|
|
{ PseudoVASUBU_VX_M8_MASK, VASUBU_VX }, // 430
|
|
{ PseudoVASUBU_VX_MF2, VASUBU_VX }, // 431
|
|
{ PseudoVASUBU_VX_MF2_MASK, VASUBU_VX }, // 432
|
|
{ PseudoVASUBU_VX_MF4, VASUBU_VX }, // 433
|
|
{ PseudoVASUBU_VX_MF4_MASK, VASUBU_VX }, // 434
|
|
{ PseudoVASUBU_VX_MF8, VASUBU_VX }, // 435
|
|
{ PseudoVASUBU_VX_MF8_MASK, VASUBU_VX }, // 436
|
|
{ PseudoVASUB_VV_M1, VASUB_VV }, // 437
|
|
{ PseudoVASUB_VV_M1_MASK, VASUB_VV }, // 438
|
|
{ PseudoVASUB_VV_M2, VASUB_VV }, // 439
|
|
{ PseudoVASUB_VV_M2_MASK, VASUB_VV }, // 440
|
|
{ PseudoVASUB_VV_M4, VASUB_VV }, // 441
|
|
{ PseudoVASUB_VV_M4_MASK, VASUB_VV }, // 442
|
|
{ PseudoVASUB_VV_M8, VASUB_VV }, // 443
|
|
{ PseudoVASUB_VV_M8_MASK, VASUB_VV }, // 444
|
|
{ PseudoVASUB_VV_MF2, VASUB_VV }, // 445
|
|
{ PseudoVASUB_VV_MF2_MASK, VASUB_VV }, // 446
|
|
{ PseudoVASUB_VV_MF4, VASUB_VV }, // 447
|
|
{ PseudoVASUB_VV_MF4_MASK, VASUB_VV }, // 448
|
|
{ PseudoVASUB_VV_MF8, VASUB_VV }, // 449
|
|
{ PseudoVASUB_VV_MF8_MASK, VASUB_VV }, // 450
|
|
{ PseudoVASUB_VX_M1, VASUB_VX }, // 451
|
|
{ PseudoVASUB_VX_M1_MASK, VASUB_VX }, // 452
|
|
{ PseudoVASUB_VX_M2, VASUB_VX }, // 453
|
|
{ PseudoVASUB_VX_M2_MASK, VASUB_VX }, // 454
|
|
{ PseudoVASUB_VX_M4, VASUB_VX }, // 455
|
|
{ PseudoVASUB_VX_M4_MASK, VASUB_VX }, // 456
|
|
{ PseudoVASUB_VX_M8, VASUB_VX }, // 457
|
|
{ PseudoVASUB_VX_M8_MASK, VASUB_VX }, // 458
|
|
{ PseudoVASUB_VX_MF2, VASUB_VX }, // 459
|
|
{ PseudoVASUB_VX_MF2_MASK, VASUB_VX }, // 460
|
|
{ PseudoVASUB_VX_MF4, VASUB_VX }, // 461
|
|
{ PseudoVASUB_VX_MF4_MASK, VASUB_VX }, // 462
|
|
{ PseudoVASUB_VX_MF8, VASUB_VX }, // 463
|
|
{ PseudoVASUB_VX_MF8_MASK, VASUB_VX }, // 464
|
|
{ PseudoVBREV8_V_M1, VBREV8_V }, // 465
|
|
{ PseudoVBREV8_V_M1_MASK, VBREV8_V }, // 466
|
|
{ PseudoVBREV8_V_M2, VBREV8_V }, // 467
|
|
{ PseudoVBREV8_V_M2_MASK, VBREV8_V }, // 468
|
|
{ PseudoVBREV8_V_M4, VBREV8_V }, // 469
|
|
{ PseudoVBREV8_V_M4_MASK, VBREV8_V }, // 470
|
|
{ PseudoVBREV8_V_M8, VBREV8_V }, // 471
|
|
{ PseudoVBREV8_V_M8_MASK, VBREV8_V }, // 472
|
|
{ PseudoVBREV8_V_MF2, VBREV8_V }, // 473
|
|
{ PseudoVBREV8_V_MF2_MASK, VBREV8_V }, // 474
|
|
{ PseudoVBREV8_V_MF4, VBREV8_V }, // 475
|
|
{ PseudoVBREV8_V_MF4_MASK, VBREV8_V }, // 476
|
|
{ PseudoVBREV8_V_MF8, VBREV8_V }, // 477
|
|
{ PseudoVBREV8_V_MF8_MASK, VBREV8_V }, // 478
|
|
{ PseudoVBREV_V_M1, VBREV_V }, // 479
|
|
{ PseudoVBREV_V_M1_MASK, VBREV_V }, // 480
|
|
{ PseudoVBREV_V_M2, VBREV_V }, // 481
|
|
{ PseudoVBREV_V_M2_MASK, VBREV_V }, // 482
|
|
{ PseudoVBREV_V_M4, VBREV_V }, // 483
|
|
{ PseudoVBREV_V_M4_MASK, VBREV_V }, // 484
|
|
{ PseudoVBREV_V_M8, VBREV_V }, // 485
|
|
{ PseudoVBREV_V_M8_MASK, VBREV_V }, // 486
|
|
{ PseudoVBREV_V_MF2, VBREV_V }, // 487
|
|
{ PseudoVBREV_V_MF2_MASK, VBREV_V }, // 488
|
|
{ PseudoVBREV_V_MF4, VBREV_V }, // 489
|
|
{ PseudoVBREV_V_MF4_MASK, VBREV_V }, // 490
|
|
{ PseudoVBREV_V_MF8, VBREV_V }, // 491
|
|
{ PseudoVBREV_V_MF8_MASK, VBREV_V }, // 492
|
|
{ PseudoVCLMULH_VV_M1, VCLMULH_VV }, // 493
|
|
{ PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV }, // 494
|
|
{ PseudoVCLMULH_VV_M2, VCLMULH_VV }, // 495
|
|
{ PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV }, // 496
|
|
{ PseudoVCLMULH_VV_M4, VCLMULH_VV }, // 497
|
|
{ PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV }, // 498
|
|
{ PseudoVCLMULH_VV_M8, VCLMULH_VV }, // 499
|
|
{ PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV }, // 500
|
|
{ PseudoVCLMULH_VV_MF2, VCLMULH_VV }, // 501
|
|
{ PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV }, // 502
|
|
{ PseudoVCLMULH_VV_MF4, VCLMULH_VV }, // 503
|
|
{ PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV }, // 504
|
|
{ PseudoVCLMULH_VV_MF8, VCLMULH_VV }, // 505
|
|
{ PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV }, // 506
|
|
{ PseudoVCLMULH_VX_M1, VCLMULH_VX }, // 507
|
|
{ PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX }, // 508
|
|
{ PseudoVCLMULH_VX_M2, VCLMULH_VX }, // 509
|
|
{ PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX }, // 510
|
|
{ PseudoVCLMULH_VX_M4, VCLMULH_VX }, // 511
|
|
{ PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX }, // 512
|
|
{ PseudoVCLMULH_VX_M8, VCLMULH_VX }, // 513
|
|
{ PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX }, // 514
|
|
{ PseudoVCLMULH_VX_MF2, VCLMULH_VX }, // 515
|
|
{ PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX }, // 516
|
|
{ PseudoVCLMULH_VX_MF4, VCLMULH_VX }, // 517
|
|
{ PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX }, // 518
|
|
{ PseudoVCLMULH_VX_MF8, VCLMULH_VX }, // 519
|
|
{ PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX }, // 520
|
|
{ PseudoVCLMUL_VV_M1, VCLMUL_VV }, // 521
|
|
{ PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV }, // 522
|
|
{ PseudoVCLMUL_VV_M2, VCLMUL_VV }, // 523
|
|
{ PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV }, // 524
|
|
{ PseudoVCLMUL_VV_M4, VCLMUL_VV }, // 525
|
|
{ PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV }, // 526
|
|
{ PseudoVCLMUL_VV_M8, VCLMUL_VV }, // 527
|
|
{ PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV }, // 528
|
|
{ PseudoVCLMUL_VV_MF2, VCLMUL_VV }, // 529
|
|
{ PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV }, // 530
|
|
{ PseudoVCLMUL_VV_MF4, VCLMUL_VV }, // 531
|
|
{ PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV }, // 532
|
|
{ PseudoVCLMUL_VV_MF8, VCLMUL_VV }, // 533
|
|
{ PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV }, // 534
|
|
{ PseudoVCLMUL_VX_M1, VCLMUL_VX }, // 535
|
|
{ PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX }, // 536
|
|
{ PseudoVCLMUL_VX_M2, VCLMUL_VX }, // 537
|
|
{ PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX }, // 538
|
|
{ PseudoVCLMUL_VX_M4, VCLMUL_VX }, // 539
|
|
{ PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX }, // 540
|
|
{ PseudoVCLMUL_VX_M8, VCLMUL_VX }, // 541
|
|
{ PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX }, // 542
|
|
{ PseudoVCLMUL_VX_MF2, VCLMUL_VX }, // 543
|
|
{ PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX }, // 544
|
|
{ PseudoVCLMUL_VX_MF4, VCLMUL_VX }, // 545
|
|
{ PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX }, // 546
|
|
{ PseudoVCLMUL_VX_MF8, VCLMUL_VX }, // 547
|
|
{ PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX }, // 548
|
|
{ PseudoVCLZ_V_M1, VCLZ_V }, // 549
|
|
{ PseudoVCLZ_V_M1_MASK, VCLZ_V }, // 550
|
|
{ PseudoVCLZ_V_M2, VCLZ_V }, // 551
|
|
{ PseudoVCLZ_V_M2_MASK, VCLZ_V }, // 552
|
|
{ PseudoVCLZ_V_M4, VCLZ_V }, // 553
|
|
{ PseudoVCLZ_V_M4_MASK, VCLZ_V }, // 554
|
|
{ PseudoVCLZ_V_M8, VCLZ_V }, // 555
|
|
{ PseudoVCLZ_V_M8_MASK, VCLZ_V }, // 556
|
|
{ PseudoVCLZ_V_MF2, VCLZ_V }, // 557
|
|
{ PseudoVCLZ_V_MF2_MASK, VCLZ_V }, // 558
|
|
{ PseudoVCLZ_V_MF4, VCLZ_V }, // 559
|
|
{ PseudoVCLZ_V_MF4_MASK, VCLZ_V }, // 560
|
|
{ PseudoVCLZ_V_MF8, VCLZ_V }, // 561
|
|
{ PseudoVCLZ_V_MF8_MASK, VCLZ_V }, // 562
|
|
{ PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM }, // 563
|
|
{ PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM }, // 564
|
|
{ PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM }, // 565
|
|
{ PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM }, // 566
|
|
{ PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM }, // 567
|
|
{ PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM }, // 568
|
|
{ PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM }, // 569
|
|
{ PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM }, // 570
|
|
{ PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM }, // 571
|
|
{ PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM }, // 572
|
|
{ PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM }, // 573
|
|
{ PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM }, // 574
|
|
{ PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM }, // 575
|
|
{ PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM }, // 576
|
|
{ PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM }, // 577
|
|
{ PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM }, // 578
|
|
{ PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM }, // 579
|
|
{ PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM }, // 580
|
|
{ PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM }, // 581
|
|
{ PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM }, // 582
|
|
{ PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM }, // 583
|
|
{ PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM }, // 584
|
|
{ PseudoVCPOP_M_B1, VCPOP_M }, // 585
|
|
{ PseudoVCPOP_M_B16, VCPOP_M }, // 586
|
|
{ PseudoVCPOP_M_B16_MASK, VCPOP_M }, // 587
|
|
{ PseudoVCPOP_M_B1_MASK, VCPOP_M }, // 588
|
|
{ PseudoVCPOP_M_B2, VCPOP_M }, // 589
|
|
{ PseudoVCPOP_M_B2_MASK, VCPOP_M }, // 590
|
|
{ PseudoVCPOP_M_B32, VCPOP_M }, // 591
|
|
{ PseudoVCPOP_M_B32_MASK, VCPOP_M }, // 592
|
|
{ PseudoVCPOP_M_B4, VCPOP_M }, // 593
|
|
{ PseudoVCPOP_M_B4_MASK, VCPOP_M }, // 594
|
|
{ PseudoVCPOP_M_B64, VCPOP_M }, // 595
|
|
{ PseudoVCPOP_M_B64_MASK, VCPOP_M }, // 596
|
|
{ PseudoVCPOP_M_B8, VCPOP_M }, // 597
|
|
{ PseudoVCPOP_M_B8_MASK, VCPOP_M }, // 598
|
|
{ PseudoVCPOP_V_M1, VCPOP_V }, // 599
|
|
{ PseudoVCPOP_V_M1_MASK, VCPOP_V }, // 600
|
|
{ PseudoVCPOP_V_M2, VCPOP_V }, // 601
|
|
{ PseudoVCPOP_V_M2_MASK, VCPOP_V }, // 602
|
|
{ PseudoVCPOP_V_M4, VCPOP_V }, // 603
|
|
{ PseudoVCPOP_V_M4_MASK, VCPOP_V }, // 604
|
|
{ PseudoVCPOP_V_M8, VCPOP_V }, // 605
|
|
{ PseudoVCPOP_V_M8_MASK, VCPOP_V }, // 606
|
|
{ PseudoVCPOP_V_MF2, VCPOP_V }, // 607
|
|
{ PseudoVCPOP_V_MF2_MASK, VCPOP_V }, // 608
|
|
{ PseudoVCPOP_V_MF4, VCPOP_V }, // 609
|
|
{ PseudoVCPOP_V_MF4_MASK, VCPOP_V }, // 610
|
|
{ PseudoVCPOP_V_MF8, VCPOP_V }, // 611
|
|
{ PseudoVCPOP_V_MF8_MASK, VCPOP_V }, // 612
|
|
{ PseudoVCTZ_V_M1, VCTZ_V }, // 613
|
|
{ PseudoVCTZ_V_M1_MASK, VCTZ_V }, // 614
|
|
{ PseudoVCTZ_V_M2, VCTZ_V }, // 615
|
|
{ PseudoVCTZ_V_M2_MASK, VCTZ_V }, // 616
|
|
{ PseudoVCTZ_V_M4, VCTZ_V }, // 617
|
|
{ PseudoVCTZ_V_M4_MASK, VCTZ_V }, // 618
|
|
{ PseudoVCTZ_V_M8, VCTZ_V }, // 619
|
|
{ PseudoVCTZ_V_M8_MASK, VCTZ_V }, // 620
|
|
{ PseudoVCTZ_V_MF2, VCTZ_V }, // 621
|
|
{ PseudoVCTZ_V_MF2_MASK, VCTZ_V }, // 622
|
|
{ PseudoVCTZ_V_MF4, VCTZ_V }, // 623
|
|
{ PseudoVCTZ_V_MF4_MASK, VCTZ_V }, // 624
|
|
{ PseudoVCTZ_V_MF8, VCTZ_V }, // 625
|
|
{ PseudoVCTZ_V_MF8_MASK, VCTZ_V }, // 626
|
|
{ PseudoVC_FPR16VV_SE_M1, VC_FVV }, // 627
|
|
{ PseudoVC_FPR16VV_SE_M2, VC_FVV }, // 628
|
|
{ PseudoVC_FPR16VV_SE_M4, VC_FVV }, // 629
|
|
{ PseudoVC_FPR16VV_SE_M8, VC_FVV }, // 630
|
|
{ PseudoVC_FPR16VV_SE_MF2, VC_FVV }, // 631
|
|
{ PseudoVC_FPR16VV_SE_MF4, VC_FVV }, // 632
|
|
{ PseudoVC_FPR16VW_SE_M1, VC_FVW }, // 633
|
|
{ PseudoVC_FPR16VW_SE_M2, VC_FVW }, // 634
|
|
{ PseudoVC_FPR16VW_SE_M4, VC_FVW }, // 635
|
|
{ PseudoVC_FPR16VW_SE_M8, VC_FVW }, // 636
|
|
{ PseudoVC_FPR16VW_SE_MF2, VC_FVW }, // 637
|
|
{ PseudoVC_FPR16VW_SE_MF4, VC_FVW }, // 638
|
|
{ PseudoVC_FPR16V_SE_M1, VC_FV }, // 639
|
|
{ PseudoVC_FPR16V_SE_M2, VC_FV }, // 640
|
|
{ PseudoVC_FPR16V_SE_M4, VC_FV }, // 641
|
|
{ PseudoVC_FPR16V_SE_M8, VC_FV }, // 642
|
|
{ PseudoVC_FPR16V_SE_MF2, VC_FV }, // 643
|
|
{ PseudoVC_FPR16V_SE_MF4, VC_FV }, // 644
|
|
{ PseudoVC_FPR32VV_SE_M1, VC_FVV }, // 645
|
|
{ PseudoVC_FPR32VV_SE_M2, VC_FVV }, // 646
|
|
{ PseudoVC_FPR32VV_SE_M4, VC_FVV }, // 647
|
|
{ PseudoVC_FPR32VV_SE_M8, VC_FVV }, // 648
|
|
{ PseudoVC_FPR32VV_SE_MF2, VC_FVV }, // 649
|
|
{ PseudoVC_FPR32VW_SE_M1, VC_FVW }, // 650
|
|
{ PseudoVC_FPR32VW_SE_M2, VC_FVW }, // 651
|
|
{ PseudoVC_FPR32VW_SE_M4, VC_FVW }, // 652
|
|
{ PseudoVC_FPR32VW_SE_M8, VC_FVW }, // 653
|
|
{ PseudoVC_FPR32VW_SE_MF2, VC_FVW }, // 654
|
|
{ PseudoVC_FPR32V_SE_M1, VC_FV }, // 655
|
|
{ PseudoVC_FPR32V_SE_M2, VC_FV }, // 656
|
|
{ PseudoVC_FPR32V_SE_M4, VC_FV }, // 657
|
|
{ PseudoVC_FPR32V_SE_M8, VC_FV }, // 658
|
|
{ PseudoVC_FPR32V_SE_MF2, VC_FV }, // 659
|
|
{ PseudoVC_FPR64VV_SE_M1, VC_FVV }, // 660
|
|
{ PseudoVC_FPR64VV_SE_M2, VC_FVV }, // 661
|
|
{ PseudoVC_FPR64VV_SE_M4, VC_FVV }, // 662
|
|
{ PseudoVC_FPR64VV_SE_M8, VC_FVV }, // 663
|
|
{ PseudoVC_FPR64V_SE_M1, VC_FV }, // 664
|
|
{ PseudoVC_FPR64V_SE_M2, VC_FV }, // 665
|
|
{ PseudoVC_FPR64V_SE_M4, VC_FV }, // 666
|
|
{ PseudoVC_FPR64V_SE_M8, VC_FV }, // 667
|
|
{ PseudoVC_IVV_SE_M1, VC_IVV }, // 668
|
|
{ PseudoVC_IVV_SE_M2, VC_IVV }, // 669
|
|
{ PseudoVC_IVV_SE_M4, VC_IVV }, // 670
|
|
{ PseudoVC_IVV_SE_M8, VC_IVV }, // 671
|
|
{ PseudoVC_IVV_SE_MF2, VC_IVV }, // 672
|
|
{ PseudoVC_IVV_SE_MF4, VC_IVV }, // 673
|
|
{ PseudoVC_IVV_SE_MF8, VC_IVV }, // 674
|
|
{ PseudoVC_IVW_SE_M1, VC_IVW }, // 675
|
|
{ PseudoVC_IVW_SE_M2, VC_IVW }, // 676
|
|
{ PseudoVC_IVW_SE_M4, VC_IVW }, // 677
|
|
{ PseudoVC_IVW_SE_MF2, VC_IVW }, // 678
|
|
{ PseudoVC_IVW_SE_MF4, VC_IVW }, // 679
|
|
{ PseudoVC_IVW_SE_MF8, VC_IVW }, // 680
|
|
{ PseudoVC_IV_SE_M1, VC_IV }, // 681
|
|
{ PseudoVC_IV_SE_M2, VC_IV }, // 682
|
|
{ PseudoVC_IV_SE_M4, VC_IV }, // 683
|
|
{ PseudoVC_IV_SE_M8, VC_IV }, // 684
|
|
{ PseudoVC_IV_SE_MF2, VC_IV }, // 685
|
|
{ PseudoVC_IV_SE_MF4, VC_IV }, // 686
|
|
{ PseudoVC_IV_SE_MF8, VC_IV }, // 687
|
|
{ PseudoVC_I_SE_M1, VC_I }, // 688
|
|
{ PseudoVC_I_SE_M2, VC_I }, // 689
|
|
{ PseudoVC_I_SE_M4, VC_I }, // 690
|
|
{ PseudoVC_I_SE_M8, VC_I }, // 691
|
|
{ PseudoVC_I_SE_MF2, VC_I }, // 692
|
|
{ PseudoVC_I_SE_MF4, VC_I }, // 693
|
|
{ PseudoVC_I_SE_MF8, VC_I }, // 694
|
|
{ PseudoVC_VVV_SE_M1, VC_VVV }, // 695
|
|
{ PseudoVC_VVV_SE_M2, VC_VVV }, // 696
|
|
{ PseudoVC_VVV_SE_M4, VC_VVV }, // 697
|
|
{ PseudoVC_VVV_SE_M8, VC_VVV }, // 698
|
|
{ PseudoVC_VVV_SE_MF2, VC_VVV }, // 699
|
|
{ PseudoVC_VVV_SE_MF4, VC_VVV }, // 700
|
|
{ PseudoVC_VVV_SE_MF8, VC_VVV }, // 701
|
|
{ PseudoVC_VVW_SE_M1, VC_VVW }, // 702
|
|
{ PseudoVC_VVW_SE_M2, VC_VVW }, // 703
|
|
{ PseudoVC_VVW_SE_M4, VC_VVW }, // 704
|
|
{ PseudoVC_VVW_SE_MF2, VC_VVW }, // 705
|
|
{ PseudoVC_VVW_SE_MF4, VC_VVW }, // 706
|
|
{ PseudoVC_VVW_SE_MF8, VC_VVW }, // 707
|
|
{ PseudoVC_VV_SE_M1, VC_VV }, // 708
|
|
{ PseudoVC_VV_SE_M2, VC_VV }, // 709
|
|
{ PseudoVC_VV_SE_M4, VC_VV }, // 710
|
|
{ PseudoVC_VV_SE_M8, VC_VV }, // 711
|
|
{ PseudoVC_VV_SE_MF2, VC_VV }, // 712
|
|
{ PseudoVC_VV_SE_MF4, VC_VV }, // 713
|
|
{ PseudoVC_VV_SE_MF8, VC_VV }, // 714
|
|
{ PseudoVC_V_FPR16VV_M1, VC_V_FVV }, // 715
|
|
{ PseudoVC_V_FPR16VV_M2, VC_V_FVV }, // 716
|
|
{ PseudoVC_V_FPR16VV_M4, VC_V_FVV }, // 717
|
|
{ PseudoVC_V_FPR16VV_M8, VC_V_FVV }, // 718
|
|
{ PseudoVC_V_FPR16VV_MF2, VC_V_FVV }, // 719
|
|
{ PseudoVC_V_FPR16VV_MF4, VC_V_FVV }, // 720
|
|
{ PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV }, // 721
|
|
{ PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV }, // 722
|
|
{ PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV }, // 723
|
|
{ PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV }, // 724
|
|
{ PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV }, // 725
|
|
{ PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV }, // 726
|
|
{ PseudoVC_V_FPR16VW_M1, VC_V_FVW }, // 727
|
|
{ PseudoVC_V_FPR16VW_M2, VC_V_FVW }, // 728
|
|
{ PseudoVC_V_FPR16VW_M4, VC_V_FVW }, // 729
|
|
{ PseudoVC_V_FPR16VW_M8, VC_V_FVW }, // 730
|
|
{ PseudoVC_V_FPR16VW_MF2, VC_V_FVW }, // 731
|
|
{ PseudoVC_V_FPR16VW_MF4, VC_V_FVW }, // 732
|
|
{ PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW }, // 733
|
|
{ PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW }, // 734
|
|
{ PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW }, // 735
|
|
{ PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW }, // 736
|
|
{ PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW }, // 737
|
|
{ PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW }, // 738
|
|
{ PseudoVC_V_FPR16V_M1, VC_V_FV }, // 739
|
|
{ PseudoVC_V_FPR16V_M2, VC_V_FV }, // 740
|
|
{ PseudoVC_V_FPR16V_M4, VC_V_FV }, // 741
|
|
{ PseudoVC_V_FPR16V_M8, VC_V_FV }, // 742
|
|
{ PseudoVC_V_FPR16V_MF2, VC_V_FV }, // 743
|
|
{ PseudoVC_V_FPR16V_MF4, VC_V_FV }, // 744
|
|
{ PseudoVC_V_FPR16V_SE_M1, VC_V_FV }, // 745
|
|
{ PseudoVC_V_FPR16V_SE_M2, VC_V_FV }, // 746
|
|
{ PseudoVC_V_FPR16V_SE_M4, VC_V_FV }, // 747
|
|
{ PseudoVC_V_FPR16V_SE_M8, VC_V_FV }, // 748
|
|
{ PseudoVC_V_FPR16V_SE_MF2, VC_V_FV }, // 749
|
|
{ PseudoVC_V_FPR16V_SE_MF4, VC_V_FV }, // 750
|
|
{ PseudoVC_V_FPR32VV_M1, VC_V_FVV }, // 751
|
|
{ PseudoVC_V_FPR32VV_M2, VC_V_FVV }, // 752
|
|
{ PseudoVC_V_FPR32VV_M4, VC_V_FVV }, // 753
|
|
{ PseudoVC_V_FPR32VV_M8, VC_V_FVV }, // 754
|
|
{ PseudoVC_V_FPR32VV_MF2, VC_V_FVV }, // 755
|
|
{ PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV }, // 756
|
|
{ PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV }, // 757
|
|
{ PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV }, // 758
|
|
{ PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV }, // 759
|
|
{ PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV }, // 760
|
|
{ PseudoVC_V_FPR32VW_M1, VC_V_FVW }, // 761
|
|
{ PseudoVC_V_FPR32VW_M2, VC_V_FVW }, // 762
|
|
{ PseudoVC_V_FPR32VW_M4, VC_V_FVW }, // 763
|
|
{ PseudoVC_V_FPR32VW_M8, VC_V_FVW }, // 764
|
|
{ PseudoVC_V_FPR32VW_MF2, VC_V_FVW }, // 765
|
|
{ PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW }, // 766
|
|
{ PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW }, // 767
|
|
{ PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW }, // 768
|
|
{ PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW }, // 769
|
|
{ PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW }, // 770
|
|
{ PseudoVC_V_FPR32V_M1, VC_V_FV }, // 771
|
|
{ PseudoVC_V_FPR32V_M2, VC_V_FV }, // 772
|
|
{ PseudoVC_V_FPR32V_M4, VC_V_FV }, // 773
|
|
{ PseudoVC_V_FPR32V_M8, VC_V_FV }, // 774
|
|
{ PseudoVC_V_FPR32V_MF2, VC_V_FV }, // 775
|
|
{ PseudoVC_V_FPR32V_SE_M1, VC_V_FV }, // 776
|
|
{ PseudoVC_V_FPR32V_SE_M2, VC_V_FV }, // 777
|
|
{ PseudoVC_V_FPR32V_SE_M4, VC_V_FV }, // 778
|
|
{ PseudoVC_V_FPR32V_SE_M8, VC_V_FV }, // 779
|
|
{ PseudoVC_V_FPR32V_SE_MF2, VC_V_FV }, // 780
|
|
{ PseudoVC_V_FPR64VV_M1, VC_V_FVV }, // 781
|
|
{ PseudoVC_V_FPR64VV_M2, VC_V_FVV }, // 782
|
|
{ PseudoVC_V_FPR64VV_M4, VC_V_FVV }, // 783
|
|
{ PseudoVC_V_FPR64VV_M8, VC_V_FVV }, // 784
|
|
{ PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV }, // 785
|
|
{ PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV }, // 786
|
|
{ PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV }, // 787
|
|
{ PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV }, // 788
|
|
{ PseudoVC_V_FPR64V_M1, VC_V_FV }, // 789
|
|
{ PseudoVC_V_FPR64V_M2, VC_V_FV }, // 790
|
|
{ PseudoVC_V_FPR64V_M4, VC_V_FV }, // 791
|
|
{ PseudoVC_V_FPR64V_M8, VC_V_FV }, // 792
|
|
{ PseudoVC_V_FPR64V_SE_M1, VC_V_FV }, // 793
|
|
{ PseudoVC_V_FPR64V_SE_M2, VC_V_FV }, // 794
|
|
{ PseudoVC_V_FPR64V_SE_M4, VC_V_FV }, // 795
|
|
{ PseudoVC_V_FPR64V_SE_M8, VC_V_FV }, // 796
|
|
{ PseudoVC_V_IVV_M1, VC_V_IVV }, // 797
|
|
{ PseudoVC_V_IVV_M2, VC_V_IVV }, // 798
|
|
{ PseudoVC_V_IVV_M4, VC_V_IVV }, // 799
|
|
{ PseudoVC_V_IVV_M8, VC_V_IVV }, // 800
|
|
{ PseudoVC_V_IVV_MF2, VC_V_IVV }, // 801
|
|
{ PseudoVC_V_IVV_MF4, VC_V_IVV }, // 802
|
|
{ PseudoVC_V_IVV_MF8, VC_V_IVV }, // 803
|
|
{ PseudoVC_V_IVV_SE_M1, VC_V_IVV }, // 804
|
|
{ PseudoVC_V_IVV_SE_M2, VC_V_IVV }, // 805
|
|
{ PseudoVC_V_IVV_SE_M4, VC_V_IVV }, // 806
|
|
{ PseudoVC_V_IVV_SE_M8, VC_V_IVV }, // 807
|
|
{ PseudoVC_V_IVV_SE_MF2, VC_V_IVV }, // 808
|
|
{ PseudoVC_V_IVV_SE_MF4, VC_V_IVV }, // 809
|
|
{ PseudoVC_V_IVV_SE_MF8, VC_V_IVV }, // 810
|
|
{ PseudoVC_V_IVW_M1, VC_V_IVW }, // 811
|
|
{ PseudoVC_V_IVW_M2, VC_V_IVW }, // 812
|
|
{ PseudoVC_V_IVW_M4, VC_V_IVW }, // 813
|
|
{ PseudoVC_V_IVW_MF2, VC_V_IVW }, // 814
|
|
{ PseudoVC_V_IVW_MF4, VC_V_IVW }, // 815
|
|
{ PseudoVC_V_IVW_MF8, VC_V_IVW }, // 816
|
|
{ PseudoVC_V_IVW_SE_M1, VC_V_IVW }, // 817
|
|
{ PseudoVC_V_IVW_SE_M2, VC_V_IVW }, // 818
|
|
{ PseudoVC_V_IVW_SE_M4, VC_V_IVW }, // 819
|
|
{ PseudoVC_V_IVW_SE_MF2, VC_V_IVW }, // 820
|
|
{ PseudoVC_V_IVW_SE_MF4, VC_V_IVW }, // 821
|
|
{ PseudoVC_V_IVW_SE_MF8, VC_V_IVW }, // 822
|
|
{ PseudoVC_V_IV_M1, VC_V_IV }, // 823
|
|
{ PseudoVC_V_IV_M2, VC_V_IV }, // 824
|
|
{ PseudoVC_V_IV_M4, VC_V_IV }, // 825
|
|
{ PseudoVC_V_IV_M8, VC_V_IV }, // 826
|
|
{ PseudoVC_V_IV_MF2, VC_V_IV }, // 827
|
|
{ PseudoVC_V_IV_MF4, VC_V_IV }, // 828
|
|
{ PseudoVC_V_IV_MF8, VC_V_IV }, // 829
|
|
{ PseudoVC_V_IV_SE_M1, VC_V_IV }, // 830
|
|
{ PseudoVC_V_IV_SE_M2, VC_V_IV }, // 831
|
|
{ PseudoVC_V_IV_SE_M4, VC_V_IV }, // 832
|
|
{ PseudoVC_V_IV_SE_M8, VC_V_IV }, // 833
|
|
{ PseudoVC_V_IV_SE_MF2, VC_V_IV }, // 834
|
|
{ PseudoVC_V_IV_SE_MF4, VC_V_IV }, // 835
|
|
{ PseudoVC_V_IV_SE_MF8, VC_V_IV }, // 836
|
|
{ PseudoVC_V_I_M1, VC_V_I }, // 837
|
|
{ PseudoVC_V_I_M2, VC_V_I }, // 838
|
|
{ PseudoVC_V_I_M4, VC_V_I }, // 839
|
|
{ PseudoVC_V_I_M8, VC_V_I }, // 840
|
|
{ PseudoVC_V_I_MF2, VC_V_I }, // 841
|
|
{ PseudoVC_V_I_MF4, VC_V_I }, // 842
|
|
{ PseudoVC_V_I_MF8, VC_V_I }, // 843
|
|
{ PseudoVC_V_I_SE_M1, VC_V_I }, // 844
|
|
{ PseudoVC_V_I_SE_M2, VC_V_I }, // 845
|
|
{ PseudoVC_V_I_SE_M4, VC_V_I }, // 846
|
|
{ PseudoVC_V_I_SE_M8, VC_V_I }, // 847
|
|
{ PseudoVC_V_I_SE_MF2, VC_V_I }, // 848
|
|
{ PseudoVC_V_I_SE_MF4, VC_V_I }, // 849
|
|
{ PseudoVC_V_I_SE_MF8, VC_V_I }, // 850
|
|
{ PseudoVC_V_VVV_M1, VC_V_VVV }, // 851
|
|
{ PseudoVC_V_VVV_M2, VC_V_VVV }, // 852
|
|
{ PseudoVC_V_VVV_M4, VC_V_VVV }, // 853
|
|
{ PseudoVC_V_VVV_M8, VC_V_VVV }, // 854
|
|
{ PseudoVC_V_VVV_MF2, VC_V_VVV }, // 855
|
|
{ PseudoVC_V_VVV_MF4, VC_V_VVV }, // 856
|
|
{ PseudoVC_V_VVV_MF8, VC_V_VVV }, // 857
|
|
{ PseudoVC_V_VVV_SE_M1, VC_V_VVV }, // 858
|
|
{ PseudoVC_V_VVV_SE_M2, VC_V_VVV }, // 859
|
|
{ PseudoVC_V_VVV_SE_M4, VC_V_VVV }, // 860
|
|
{ PseudoVC_V_VVV_SE_M8, VC_V_VVV }, // 861
|
|
{ PseudoVC_V_VVV_SE_MF2, VC_V_VVV }, // 862
|
|
{ PseudoVC_V_VVV_SE_MF4, VC_V_VVV }, // 863
|
|
{ PseudoVC_V_VVV_SE_MF8, VC_V_VVV }, // 864
|
|
{ PseudoVC_V_VVW_M1, VC_V_VVW }, // 865
|
|
{ PseudoVC_V_VVW_M2, VC_V_VVW }, // 866
|
|
{ PseudoVC_V_VVW_M4, VC_V_VVW }, // 867
|
|
{ PseudoVC_V_VVW_MF2, VC_V_VVW }, // 868
|
|
{ PseudoVC_V_VVW_MF4, VC_V_VVW }, // 869
|
|
{ PseudoVC_V_VVW_MF8, VC_V_VVW }, // 870
|
|
{ PseudoVC_V_VVW_SE_M1, VC_V_VVW }, // 871
|
|
{ PseudoVC_V_VVW_SE_M2, VC_V_VVW }, // 872
|
|
{ PseudoVC_V_VVW_SE_M4, VC_V_VVW }, // 873
|
|
{ PseudoVC_V_VVW_SE_MF2, VC_V_VVW }, // 874
|
|
{ PseudoVC_V_VVW_SE_MF4, VC_V_VVW }, // 875
|
|
{ PseudoVC_V_VVW_SE_MF8, VC_V_VVW }, // 876
|
|
{ PseudoVC_V_VV_M1, VC_V_VV }, // 877
|
|
{ PseudoVC_V_VV_M2, VC_V_VV }, // 878
|
|
{ PseudoVC_V_VV_M4, VC_V_VV }, // 879
|
|
{ PseudoVC_V_VV_M8, VC_V_VV }, // 880
|
|
{ PseudoVC_V_VV_MF2, VC_V_VV }, // 881
|
|
{ PseudoVC_V_VV_MF4, VC_V_VV }, // 882
|
|
{ PseudoVC_V_VV_MF8, VC_V_VV }, // 883
|
|
{ PseudoVC_V_VV_SE_M1, VC_V_VV }, // 884
|
|
{ PseudoVC_V_VV_SE_M2, VC_V_VV }, // 885
|
|
{ PseudoVC_V_VV_SE_M4, VC_V_VV }, // 886
|
|
{ PseudoVC_V_VV_SE_M8, VC_V_VV }, // 887
|
|
{ PseudoVC_V_VV_SE_MF2, VC_V_VV }, // 888
|
|
{ PseudoVC_V_VV_SE_MF4, VC_V_VV }, // 889
|
|
{ PseudoVC_V_VV_SE_MF8, VC_V_VV }, // 890
|
|
{ PseudoVC_V_XVV_M1, VC_V_XVV }, // 891
|
|
{ PseudoVC_V_XVV_M2, VC_V_XVV }, // 892
|
|
{ PseudoVC_V_XVV_M4, VC_V_XVV }, // 893
|
|
{ PseudoVC_V_XVV_M8, VC_V_XVV }, // 894
|
|
{ PseudoVC_V_XVV_MF2, VC_V_XVV }, // 895
|
|
{ PseudoVC_V_XVV_MF4, VC_V_XVV }, // 896
|
|
{ PseudoVC_V_XVV_MF8, VC_V_XVV }, // 897
|
|
{ PseudoVC_V_XVV_SE_M1, VC_V_XVV }, // 898
|
|
{ PseudoVC_V_XVV_SE_M2, VC_V_XVV }, // 899
|
|
{ PseudoVC_V_XVV_SE_M4, VC_V_XVV }, // 900
|
|
{ PseudoVC_V_XVV_SE_M8, VC_V_XVV }, // 901
|
|
{ PseudoVC_V_XVV_SE_MF2, VC_V_XVV }, // 902
|
|
{ PseudoVC_V_XVV_SE_MF4, VC_V_XVV }, // 903
|
|
{ PseudoVC_V_XVV_SE_MF8, VC_V_XVV }, // 904
|
|
{ PseudoVC_V_XVW_M1, VC_V_XVW }, // 905
|
|
{ PseudoVC_V_XVW_M2, VC_V_XVW }, // 906
|
|
{ PseudoVC_V_XVW_M4, VC_V_XVW }, // 907
|
|
{ PseudoVC_V_XVW_MF2, VC_V_XVW }, // 908
|
|
{ PseudoVC_V_XVW_MF4, VC_V_XVW }, // 909
|
|
{ PseudoVC_V_XVW_MF8, VC_V_XVW }, // 910
|
|
{ PseudoVC_V_XVW_SE_M1, VC_V_XVW }, // 911
|
|
{ PseudoVC_V_XVW_SE_M2, VC_V_XVW }, // 912
|
|
{ PseudoVC_V_XVW_SE_M4, VC_V_XVW }, // 913
|
|
{ PseudoVC_V_XVW_SE_MF2, VC_V_XVW }, // 914
|
|
{ PseudoVC_V_XVW_SE_MF4, VC_V_XVW }, // 915
|
|
{ PseudoVC_V_XVW_SE_MF8, VC_V_XVW }, // 916
|
|
{ PseudoVC_V_XV_M1, VC_V_XV }, // 917
|
|
{ PseudoVC_V_XV_M2, VC_V_XV }, // 918
|
|
{ PseudoVC_V_XV_M4, VC_V_XV }, // 919
|
|
{ PseudoVC_V_XV_M8, VC_V_XV }, // 920
|
|
{ PseudoVC_V_XV_MF2, VC_V_XV }, // 921
|
|
{ PseudoVC_V_XV_MF4, VC_V_XV }, // 922
|
|
{ PseudoVC_V_XV_MF8, VC_V_XV }, // 923
|
|
{ PseudoVC_V_XV_SE_M1, VC_V_XV }, // 924
|
|
{ PseudoVC_V_XV_SE_M2, VC_V_XV }, // 925
|
|
{ PseudoVC_V_XV_SE_M4, VC_V_XV }, // 926
|
|
{ PseudoVC_V_XV_SE_M8, VC_V_XV }, // 927
|
|
{ PseudoVC_V_XV_SE_MF2, VC_V_XV }, // 928
|
|
{ PseudoVC_V_XV_SE_MF4, VC_V_XV }, // 929
|
|
{ PseudoVC_V_XV_SE_MF8, VC_V_XV }, // 930
|
|
{ PseudoVC_V_X_M1, VC_V_X }, // 931
|
|
{ PseudoVC_V_X_M2, VC_V_X }, // 932
|
|
{ PseudoVC_V_X_M4, VC_V_X }, // 933
|
|
{ PseudoVC_V_X_M8, VC_V_X }, // 934
|
|
{ PseudoVC_V_X_MF2, VC_V_X }, // 935
|
|
{ PseudoVC_V_X_MF4, VC_V_X }, // 936
|
|
{ PseudoVC_V_X_MF8, VC_V_X }, // 937
|
|
{ PseudoVC_V_X_SE_M1, VC_V_X }, // 938
|
|
{ PseudoVC_V_X_SE_M2, VC_V_X }, // 939
|
|
{ PseudoVC_V_X_SE_M4, VC_V_X }, // 940
|
|
{ PseudoVC_V_X_SE_M8, VC_V_X }, // 941
|
|
{ PseudoVC_V_X_SE_MF2, VC_V_X }, // 942
|
|
{ PseudoVC_V_X_SE_MF4, VC_V_X }, // 943
|
|
{ PseudoVC_V_X_SE_MF8, VC_V_X }, // 944
|
|
{ PseudoVC_XVV_SE_M1, VC_XVV }, // 945
|
|
{ PseudoVC_XVV_SE_M2, VC_XVV }, // 946
|
|
{ PseudoVC_XVV_SE_M4, VC_XVV }, // 947
|
|
{ PseudoVC_XVV_SE_M8, VC_XVV }, // 948
|
|
{ PseudoVC_XVV_SE_MF2, VC_XVV }, // 949
|
|
{ PseudoVC_XVV_SE_MF4, VC_XVV }, // 950
|
|
{ PseudoVC_XVV_SE_MF8, VC_XVV }, // 951
|
|
{ PseudoVC_XVW_SE_M1, VC_XVW }, // 952
|
|
{ PseudoVC_XVW_SE_M2, VC_XVW }, // 953
|
|
{ PseudoVC_XVW_SE_M4, VC_XVW }, // 954
|
|
{ PseudoVC_XVW_SE_MF2, VC_XVW }, // 955
|
|
{ PseudoVC_XVW_SE_MF4, VC_XVW }, // 956
|
|
{ PseudoVC_XVW_SE_MF8, VC_XVW }, // 957
|
|
{ PseudoVC_XV_SE_M1, VC_XV }, // 958
|
|
{ PseudoVC_XV_SE_M2, VC_XV }, // 959
|
|
{ PseudoVC_XV_SE_M4, VC_XV }, // 960
|
|
{ PseudoVC_XV_SE_M8, VC_XV }, // 961
|
|
{ PseudoVC_XV_SE_MF2, VC_XV }, // 962
|
|
{ PseudoVC_XV_SE_MF4, VC_XV }, // 963
|
|
{ PseudoVC_XV_SE_MF8, VC_XV }, // 964
|
|
{ PseudoVC_X_SE_M1, VC_X }, // 965
|
|
{ PseudoVC_X_SE_M2, VC_X }, // 966
|
|
{ PseudoVC_X_SE_M4, VC_X }, // 967
|
|
{ PseudoVC_X_SE_M8, VC_X }, // 968
|
|
{ PseudoVC_X_SE_MF2, VC_X }, // 969
|
|
{ PseudoVC_X_SE_MF4, VC_X }, // 970
|
|
{ PseudoVC_X_SE_MF8, VC_X }, // 971
|
|
{ PseudoVDIVU_VV_M1_E16, VDIVU_VV }, // 972
|
|
{ PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV }, // 973
|
|
{ PseudoVDIVU_VV_M1_E32, VDIVU_VV }, // 974
|
|
{ PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV }, // 975
|
|
{ PseudoVDIVU_VV_M1_E64, VDIVU_VV }, // 976
|
|
{ PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV }, // 977
|
|
{ PseudoVDIVU_VV_M1_E8, VDIVU_VV }, // 978
|
|
{ PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV }, // 979
|
|
{ PseudoVDIVU_VV_M2_E16, VDIVU_VV }, // 980
|
|
{ PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV }, // 981
|
|
{ PseudoVDIVU_VV_M2_E32, VDIVU_VV }, // 982
|
|
{ PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV }, // 983
|
|
{ PseudoVDIVU_VV_M2_E64, VDIVU_VV }, // 984
|
|
{ PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV }, // 985
|
|
{ PseudoVDIVU_VV_M2_E8, VDIVU_VV }, // 986
|
|
{ PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV }, // 987
|
|
{ PseudoVDIVU_VV_M4_E16, VDIVU_VV }, // 988
|
|
{ PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV }, // 989
|
|
{ PseudoVDIVU_VV_M4_E32, VDIVU_VV }, // 990
|
|
{ PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV }, // 991
|
|
{ PseudoVDIVU_VV_M4_E64, VDIVU_VV }, // 992
|
|
{ PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV }, // 993
|
|
{ PseudoVDIVU_VV_M4_E8, VDIVU_VV }, // 994
|
|
{ PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV }, // 995
|
|
{ PseudoVDIVU_VV_M8_E16, VDIVU_VV }, // 996
|
|
{ PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV }, // 997
|
|
{ PseudoVDIVU_VV_M8_E32, VDIVU_VV }, // 998
|
|
{ PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV }, // 999
|
|
{ PseudoVDIVU_VV_M8_E64, VDIVU_VV }, // 1000
|
|
{ PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV }, // 1001
|
|
{ PseudoVDIVU_VV_M8_E8, VDIVU_VV }, // 1002
|
|
{ PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV }, // 1003
|
|
{ PseudoVDIVU_VV_MF2_E16, VDIVU_VV }, // 1004
|
|
{ PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV }, // 1005
|
|
{ PseudoVDIVU_VV_MF2_E32, VDIVU_VV }, // 1006
|
|
{ PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV }, // 1007
|
|
{ PseudoVDIVU_VV_MF2_E8, VDIVU_VV }, // 1008
|
|
{ PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV }, // 1009
|
|
{ PseudoVDIVU_VV_MF4_E16, VDIVU_VV }, // 1010
|
|
{ PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV }, // 1011
|
|
{ PseudoVDIVU_VV_MF4_E8, VDIVU_VV }, // 1012
|
|
{ PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV }, // 1013
|
|
{ PseudoVDIVU_VV_MF8_E8, VDIVU_VV }, // 1014
|
|
{ PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV }, // 1015
|
|
{ PseudoVDIVU_VX_M1_E16, VDIVU_VX }, // 1016
|
|
{ PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX }, // 1017
|
|
{ PseudoVDIVU_VX_M1_E32, VDIVU_VX }, // 1018
|
|
{ PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX }, // 1019
|
|
{ PseudoVDIVU_VX_M1_E64, VDIVU_VX }, // 1020
|
|
{ PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX }, // 1021
|
|
{ PseudoVDIVU_VX_M1_E8, VDIVU_VX }, // 1022
|
|
{ PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX }, // 1023
|
|
{ PseudoVDIVU_VX_M2_E16, VDIVU_VX }, // 1024
|
|
{ PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX }, // 1025
|
|
{ PseudoVDIVU_VX_M2_E32, VDIVU_VX }, // 1026
|
|
{ PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX }, // 1027
|
|
{ PseudoVDIVU_VX_M2_E64, VDIVU_VX }, // 1028
|
|
{ PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX }, // 1029
|
|
{ PseudoVDIVU_VX_M2_E8, VDIVU_VX }, // 1030
|
|
{ PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX }, // 1031
|
|
{ PseudoVDIVU_VX_M4_E16, VDIVU_VX }, // 1032
|
|
{ PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX }, // 1033
|
|
{ PseudoVDIVU_VX_M4_E32, VDIVU_VX }, // 1034
|
|
{ PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX }, // 1035
|
|
{ PseudoVDIVU_VX_M4_E64, VDIVU_VX }, // 1036
|
|
{ PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX }, // 1037
|
|
{ PseudoVDIVU_VX_M4_E8, VDIVU_VX }, // 1038
|
|
{ PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX }, // 1039
|
|
{ PseudoVDIVU_VX_M8_E16, VDIVU_VX }, // 1040
|
|
{ PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX }, // 1041
|
|
{ PseudoVDIVU_VX_M8_E32, VDIVU_VX }, // 1042
|
|
{ PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX }, // 1043
|
|
{ PseudoVDIVU_VX_M8_E64, VDIVU_VX }, // 1044
|
|
{ PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX }, // 1045
|
|
{ PseudoVDIVU_VX_M8_E8, VDIVU_VX }, // 1046
|
|
{ PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX }, // 1047
|
|
{ PseudoVDIVU_VX_MF2_E16, VDIVU_VX }, // 1048
|
|
{ PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX }, // 1049
|
|
{ PseudoVDIVU_VX_MF2_E32, VDIVU_VX }, // 1050
|
|
{ PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX }, // 1051
|
|
{ PseudoVDIVU_VX_MF2_E8, VDIVU_VX }, // 1052
|
|
{ PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX }, // 1053
|
|
{ PseudoVDIVU_VX_MF4_E16, VDIVU_VX }, // 1054
|
|
{ PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX }, // 1055
|
|
{ PseudoVDIVU_VX_MF4_E8, VDIVU_VX }, // 1056
|
|
{ PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX }, // 1057
|
|
{ PseudoVDIVU_VX_MF8_E8, VDIVU_VX }, // 1058
|
|
{ PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX }, // 1059
|
|
{ PseudoVDIV_VV_M1_E16, VDIV_VV }, // 1060
|
|
{ PseudoVDIV_VV_M1_E16_MASK, VDIV_VV }, // 1061
|
|
{ PseudoVDIV_VV_M1_E32, VDIV_VV }, // 1062
|
|
{ PseudoVDIV_VV_M1_E32_MASK, VDIV_VV }, // 1063
|
|
{ PseudoVDIV_VV_M1_E64, VDIV_VV }, // 1064
|
|
{ PseudoVDIV_VV_M1_E64_MASK, VDIV_VV }, // 1065
|
|
{ PseudoVDIV_VV_M1_E8, VDIV_VV }, // 1066
|
|
{ PseudoVDIV_VV_M1_E8_MASK, VDIV_VV }, // 1067
|
|
{ PseudoVDIV_VV_M2_E16, VDIV_VV }, // 1068
|
|
{ PseudoVDIV_VV_M2_E16_MASK, VDIV_VV }, // 1069
|
|
{ PseudoVDIV_VV_M2_E32, VDIV_VV }, // 1070
|
|
{ PseudoVDIV_VV_M2_E32_MASK, VDIV_VV }, // 1071
|
|
{ PseudoVDIV_VV_M2_E64, VDIV_VV }, // 1072
|
|
{ PseudoVDIV_VV_M2_E64_MASK, VDIV_VV }, // 1073
|
|
{ PseudoVDIV_VV_M2_E8, VDIV_VV }, // 1074
|
|
{ PseudoVDIV_VV_M2_E8_MASK, VDIV_VV }, // 1075
|
|
{ PseudoVDIV_VV_M4_E16, VDIV_VV }, // 1076
|
|
{ PseudoVDIV_VV_M4_E16_MASK, VDIV_VV }, // 1077
|
|
{ PseudoVDIV_VV_M4_E32, VDIV_VV }, // 1078
|
|
{ PseudoVDIV_VV_M4_E32_MASK, VDIV_VV }, // 1079
|
|
{ PseudoVDIV_VV_M4_E64, VDIV_VV }, // 1080
|
|
{ PseudoVDIV_VV_M4_E64_MASK, VDIV_VV }, // 1081
|
|
{ PseudoVDIV_VV_M4_E8, VDIV_VV }, // 1082
|
|
{ PseudoVDIV_VV_M4_E8_MASK, VDIV_VV }, // 1083
|
|
{ PseudoVDIV_VV_M8_E16, VDIV_VV }, // 1084
|
|
{ PseudoVDIV_VV_M8_E16_MASK, VDIV_VV }, // 1085
|
|
{ PseudoVDIV_VV_M8_E32, VDIV_VV }, // 1086
|
|
{ PseudoVDIV_VV_M8_E32_MASK, VDIV_VV }, // 1087
|
|
{ PseudoVDIV_VV_M8_E64, VDIV_VV }, // 1088
|
|
{ PseudoVDIV_VV_M8_E64_MASK, VDIV_VV }, // 1089
|
|
{ PseudoVDIV_VV_M8_E8, VDIV_VV }, // 1090
|
|
{ PseudoVDIV_VV_M8_E8_MASK, VDIV_VV }, // 1091
|
|
{ PseudoVDIV_VV_MF2_E16, VDIV_VV }, // 1092
|
|
{ PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV }, // 1093
|
|
{ PseudoVDIV_VV_MF2_E32, VDIV_VV }, // 1094
|
|
{ PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV }, // 1095
|
|
{ PseudoVDIV_VV_MF2_E8, VDIV_VV }, // 1096
|
|
{ PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV }, // 1097
|
|
{ PseudoVDIV_VV_MF4_E16, VDIV_VV }, // 1098
|
|
{ PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV }, // 1099
|
|
{ PseudoVDIV_VV_MF4_E8, VDIV_VV }, // 1100
|
|
{ PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV }, // 1101
|
|
{ PseudoVDIV_VV_MF8_E8, VDIV_VV }, // 1102
|
|
{ PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV }, // 1103
|
|
{ PseudoVDIV_VX_M1_E16, VDIV_VX }, // 1104
|
|
{ PseudoVDIV_VX_M1_E16_MASK, VDIV_VX }, // 1105
|
|
{ PseudoVDIV_VX_M1_E32, VDIV_VX }, // 1106
|
|
{ PseudoVDIV_VX_M1_E32_MASK, VDIV_VX }, // 1107
|
|
{ PseudoVDIV_VX_M1_E64, VDIV_VX }, // 1108
|
|
{ PseudoVDIV_VX_M1_E64_MASK, VDIV_VX }, // 1109
|
|
{ PseudoVDIV_VX_M1_E8, VDIV_VX }, // 1110
|
|
{ PseudoVDIV_VX_M1_E8_MASK, VDIV_VX }, // 1111
|
|
{ PseudoVDIV_VX_M2_E16, VDIV_VX }, // 1112
|
|
{ PseudoVDIV_VX_M2_E16_MASK, VDIV_VX }, // 1113
|
|
{ PseudoVDIV_VX_M2_E32, VDIV_VX }, // 1114
|
|
{ PseudoVDIV_VX_M2_E32_MASK, VDIV_VX }, // 1115
|
|
{ PseudoVDIV_VX_M2_E64, VDIV_VX }, // 1116
|
|
{ PseudoVDIV_VX_M2_E64_MASK, VDIV_VX }, // 1117
|
|
{ PseudoVDIV_VX_M2_E8, VDIV_VX }, // 1118
|
|
{ PseudoVDIV_VX_M2_E8_MASK, VDIV_VX }, // 1119
|
|
{ PseudoVDIV_VX_M4_E16, VDIV_VX }, // 1120
|
|
{ PseudoVDIV_VX_M4_E16_MASK, VDIV_VX }, // 1121
|
|
{ PseudoVDIV_VX_M4_E32, VDIV_VX }, // 1122
|
|
{ PseudoVDIV_VX_M4_E32_MASK, VDIV_VX }, // 1123
|
|
{ PseudoVDIV_VX_M4_E64, VDIV_VX }, // 1124
|
|
{ PseudoVDIV_VX_M4_E64_MASK, VDIV_VX }, // 1125
|
|
{ PseudoVDIV_VX_M4_E8, VDIV_VX }, // 1126
|
|
{ PseudoVDIV_VX_M4_E8_MASK, VDIV_VX }, // 1127
|
|
{ PseudoVDIV_VX_M8_E16, VDIV_VX }, // 1128
|
|
{ PseudoVDIV_VX_M8_E16_MASK, VDIV_VX }, // 1129
|
|
{ PseudoVDIV_VX_M8_E32, VDIV_VX }, // 1130
|
|
{ PseudoVDIV_VX_M8_E32_MASK, VDIV_VX }, // 1131
|
|
{ PseudoVDIV_VX_M8_E64, VDIV_VX }, // 1132
|
|
{ PseudoVDIV_VX_M8_E64_MASK, VDIV_VX }, // 1133
|
|
{ PseudoVDIV_VX_M8_E8, VDIV_VX }, // 1134
|
|
{ PseudoVDIV_VX_M8_E8_MASK, VDIV_VX }, // 1135
|
|
{ PseudoVDIV_VX_MF2_E16, VDIV_VX }, // 1136
|
|
{ PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX }, // 1137
|
|
{ PseudoVDIV_VX_MF2_E32, VDIV_VX }, // 1138
|
|
{ PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX }, // 1139
|
|
{ PseudoVDIV_VX_MF2_E8, VDIV_VX }, // 1140
|
|
{ PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX }, // 1141
|
|
{ PseudoVDIV_VX_MF4_E16, VDIV_VX }, // 1142
|
|
{ PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX }, // 1143
|
|
{ PseudoVDIV_VX_MF4_E8, VDIV_VX }, // 1144
|
|
{ PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX }, // 1145
|
|
{ PseudoVDIV_VX_MF8_E8, VDIV_VX }, // 1146
|
|
{ PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX }, // 1147
|
|
{ PseudoVFADD_VFPR16_M1, VFADD_VF }, // 1148
|
|
{ PseudoVFADD_VFPR16_M1_MASK, VFADD_VF }, // 1149
|
|
{ PseudoVFADD_VFPR16_M2, VFADD_VF }, // 1150
|
|
{ PseudoVFADD_VFPR16_M2_MASK, VFADD_VF }, // 1151
|
|
{ PseudoVFADD_VFPR16_M4, VFADD_VF }, // 1152
|
|
{ PseudoVFADD_VFPR16_M4_MASK, VFADD_VF }, // 1153
|
|
{ PseudoVFADD_VFPR16_M8, VFADD_VF }, // 1154
|
|
{ PseudoVFADD_VFPR16_M8_MASK, VFADD_VF }, // 1155
|
|
{ PseudoVFADD_VFPR16_MF2, VFADD_VF }, // 1156
|
|
{ PseudoVFADD_VFPR16_MF2_MASK, VFADD_VF }, // 1157
|
|
{ PseudoVFADD_VFPR16_MF4, VFADD_VF }, // 1158
|
|
{ PseudoVFADD_VFPR16_MF4_MASK, VFADD_VF }, // 1159
|
|
{ PseudoVFADD_VFPR32_M1, VFADD_VF }, // 1160
|
|
{ PseudoVFADD_VFPR32_M1_MASK, VFADD_VF }, // 1161
|
|
{ PseudoVFADD_VFPR32_M2, VFADD_VF }, // 1162
|
|
{ PseudoVFADD_VFPR32_M2_MASK, VFADD_VF }, // 1163
|
|
{ PseudoVFADD_VFPR32_M4, VFADD_VF }, // 1164
|
|
{ PseudoVFADD_VFPR32_M4_MASK, VFADD_VF }, // 1165
|
|
{ PseudoVFADD_VFPR32_M8, VFADD_VF }, // 1166
|
|
{ PseudoVFADD_VFPR32_M8_MASK, VFADD_VF }, // 1167
|
|
{ PseudoVFADD_VFPR32_MF2, VFADD_VF }, // 1168
|
|
{ PseudoVFADD_VFPR32_MF2_MASK, VFADD_VF }, // 1169
|
|
{ PseudoVFADD_VFPR64_M1, VFADD_VF }, // 1170
|
|
{ PseudoVFADD_VFPR64_M1_MASK, VFADD_VF }, // 1171
|
|
{ PseudoVFADD_VFPR64_M2, VFADD_VF }, // 1172
|
|
{ PseudoVFADD_VFPR64_M2_MASK, VFADD_VF }, // 1173
|
|
{ PseudoVFADD_VFPR64_M4, VFADD_VF }, // 1174
|
|
{ PseudoVFADD_VFPR64_M4_MASK, VFADD_VF }, // 1175
|
|
{ PseudoVFADD_VFPR64_M8, VFADD_VF }, // 1176
|
|
{ PseudoVFADD_VFPR64_M8_MASK, VFADD_VF }, // 1177
|
|
{ PseudoVFADD_VV_M1, VFADD_VV }, // 1178
|
|
{ PseudoVFADD_VV_M1_MASK, VFADD_VV }, // 1179
|
|
{ PseudoVFADD_VV_M2, VFADD_VV }, // 1180
|
|
{ PseudoVFADD_VV_M2_MASK, VFADD_VV }, // 1181
|
|
{ PseudoVFADD_VV_M4, VFADD_VV }, // 1182
|
|
{ PseudoVFADD_VV_M4_MASK, VFADD_VV }, // 1183
|
|
{ PseudoVFADD_VV_M8, VFADD_VV }, // 1184
|
|
{ PseudoVFADD_VV_M8_MASK, VFADD_VV }, // 1185
|
|
{ PseudoVFADD_VV_MF2, VFADD_VV }, // 1186
|
|
{ PseudoVFADD_VV_MF2_MASK, VFADD_VV }, // 1187
|
|
{ PseudoVFADD_VV_MF4, VFADD_VV }, // 1188
|
|
{ PseudoVFADD_VV_MF4_MASK, VFADD_VV }, // 1189
|
|
{ PseudoVFCLASS_V_M1, VFCLASS_V }, // 1190
|
|
{ PseudoVFCLASS_V_M1_MASK, VFCLASS_V }, // 1191
|
|
{ PseudoVFCLASS_V_M2, VFCLASS_V }, // 1192
|
|
{ PseudoVFCLASS_V_M2_MASK, VFCLASS_V }, // 1193
|
|
{ PseudoVFCLASS_V_M4, VFCLASS_V }, // 1194
|
|
{ PseudoVFCLASS_V_M4_MASK, VFCLASS_V }, // 1195
|
|
{ PseudoVFCLASS_V_M8, VFCLASS_V }, // 1196
|
|
{ PseudoVFCLASS_V_M8_MASK, VFCLASS_V }, // 1197
|
|
{ PseudoVFCLASS_V_MF2, VFCLASS_V }, // 1198
|
|
{ PseudoVFCLASS_V_MF2_MASK, VFCLASS_V }, // 1199
|
|
{ PseudoVFCLASS_V_MF4, VFCLASS_V }, // 1200
|
|
{ PseudoVFCLASS_V_MF4_MASK, VFCLASS_V }, // 1201
|
|
{ PseudoVFCVT_F_XU_V_M1, VFCVT_F_XU_V }, // 1202
|
|
{ PseudoVFCVT_F_XU_V_M1_MASK, VFCVT_F_XU_V }, // 1203
|
|
{ PseudoVFCVT_F_XU_V_M2, VFCVT_F_XU_V }, // 1204
|
|
{ PseudoVFCVT_F_XU_V_M2_MASK, VFCVT_F_XU_V }, // 1205
|
|
{ PseudoVFCVT_F_XU_V_M4, VFCVT_F_XU_V }, // 1206
|
|
{ PseudoVFCVT_F_XU_V_M4_MASK, VFCVT_F_XU_V }, // 1207
|
|
{ PseudoVFCVT_F_XU_V_M8, VFCVT_F_XU_V }, // 1208
|
|
{ PseudoVFCVT_F_XU_V_M8_MASK, VFCVT_F_XU_V }, // 1209
|
|
{ PseudoVFCVT_F_XU_V_MF2, VFCVT_F_XU_V }, // 1210
|
|
{ PseudoVFCVT_F_XU_V_MF2_MASK, VFCVT_F_XU_V }, // 1211
|
|
{ PseudoVFCVT_F_XU_V_MF4, VFCVT_F_XU_V }, // 1212
|
|
{ PseudoVFCVT_F_XU_V_MF4_MASK, VFCVT_F_XU_V }, // 1213
|
|
{ PseudoVFCVT_F_X_V_M1, VFCVT_F_X_V }, // 1214
|
|
{ PseudoVFCVT_F_X_V_M1_MASK, VFCVT_F_X_V }, // 1215
|
|
{ PseudoVFCVT_F_X_V_M2, VFCVT_F_X_V }, // 1216
|
|
{ PseudoVFCVT_F_X_V_M2_MASK, VFCVT_F_X_V }, // 1217
|
|
{ PseudoVFCVT_F_X_V_M4, VFCVT_F_X_V }, // 1218
|
|
{ PseudoVFCVT_F_X_V_M4_MASK, VFCVT_F_X_V }, // 1219
|
|
{ PseudoVFCVT_F_X_V_M8, VFCVT_F_X_V }, // 1220
|
|
{ PseudoVFCVT_F_X_V_M8_MASK, VFCVT_F_X_V }, // 1221
|
|
{ PseudoVFCVT_F_X_V_MF2, VFCVT_F_X_V }, // 1222
|
|
{ PseudoVFCVT_F_X_V_MF2_MASK, VFCVT_F_X_V }, // 1223
|
|
{ PseudoVFCVT_F_X_V_MF4, VFCVT_F_X_V }, // 1224
|
|
{ PseudoVFCVT_F_X_V_MF4_MASK, VFCVT_F_X_V }, // 1225
|
|
{ PseudoVFCVT_RM_F_XU_V_M1, VFCVT_F_XU_V }, // 1226
|
|
{ PseudoVFCVT_RM_F_XU_V_M1_MASK, VFCVT_F_XU_V }, // 1227
|
|
{ PseudoVFCVT_RM_F_XU_V_M2, VFCVT_F_XU_V }, // 1228
|
|
{ PseudoVFCVT_RM_F_XU_V_M2_MASK, VFCVT_F_XU_V }, // 1229
|
|
{ PseudoVFCVT_RM_F_XU_V_M4, VFCVT_F_XU_V }, // 1230
|
|
{ PseudoVFCVT_RM_F_XU_V_M4_MASK, VFCVT_F_XU_V }, // 1231
|
|
{ PseudoVFCVT_RM_F_XU_V_M8, VFCVT_F_XU_V }, // 1232
|
|
{ PseudoVFCVT_RM_F_XU_V_M8_MASK, VFCVT_F_XU_V }, // 1233
|
|
{ PseudoVFCVT_RM_F_XU_V_MF2, VFCVT_F_XU_V }, // 1234
|
|
{ PseudoVFCVT_RM_F_XU_V_MF2_MASK, VFCVT_F_XU_V }, // 1235
|
|
{ PseudoVFCVT_RM_F_XU_V_MF4, VFCVT_F_XU_V }, // 1236
|
|
{ PseudoVFCVT_RM_F_XU_V_MF4_MASK, VFCVT_F_XU_V }, // 1237
|
|
{ PseudoVFCVT_RM_F_X_V_M1, VFCVT_F_X_V }, // 1238
|
|
{ PseudoVFCVT_RM_F_X_V_M1_MASK, VFCVT_F_X_V }, // 1239
|
|
{ PseudoVFCVT_RM_F_X_V_M2, VFCVT_F_X_V }, // 1240
|
|
{ PseudoVFCVT_RM_F_X_V_M2_MASK, VFCVT_F_X_V }, // 1241
|
|
{ PseudoVFCVT_RM_F_X_V_M4, VFCVT_F_X_V }, // 1242
|
|
{ PseudoVFCVT_RM_F_X_V_M4_MASK, VFCVT_F_X_V }, // 1243
|
|
{ PseudoVFCVT_RM_F_X_V_M8, VFCVT_F_X_V }, // 1244
|
|
{ PseudoVFCVT_RM_F_X_V_M8_MASK, VFCVT_F_X_V }, // 1245
|
|
{ PseudoVFCVT_RM_F_X_V_MF2, VFCVT_F_X_V }, // 1246
|
|
{ PseudoVFCVT_RM_F_X_V_MF2_MASK, VFCVT_F_X_V }, // 1247
|
|
{ PseudoVFCVT_RM_F_X_V_MF4, VFCVT_F_X_V }, // 1248
|
|
{ PseudoVFCVT_RM_F_X_V_MF4_MASK, VFCVT_F_X_V }, // 1249
|
|
{ PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V }, // 1250
|
|
{ PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V }, // 1251
|
|
{ PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V }, // 1252
|
|
{ PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V }, // 1253
|
|
{ PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V }, // 1254
|
|
{ PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V }, // 1255
|
|
{ PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V }, // 1256
|
|
{ PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V }, // 1257
|
|
{ PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V }, // 1258
|
|
{ PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V }, // 1259
|
|
{ PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V }, // 1260
|
|
{ PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V }, // 1261
|
|
{ PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V }, // 1262
|
|
{ PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V }, // 1263
|
|
{ PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V }, // 1264
|
|
{ PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V }, // 1265
|
|
{ PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V }, // 1266
|
|
{ PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V }, // 1267
|
|
{ PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V }, // 1268
|
|
{ PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V }, // 1269
|
|
{ PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V }, // 1270
|
|
{ PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V }, // 1271
|
|
{ PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V }, // 1272
|
|
{ PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V }, // 1273
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V }, // 1274
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V }, // 1275
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V }, // 1276
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V }, // 1277
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V }, // 1278
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V }, // 1279
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V }, // 1280
|
|
{ PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V }, // 1281
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V }, // 1282
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V }, // 1283
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V }, // 1284
|
|
{ PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V }, // 1285
|
|
{ PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V }, // 1286
|
|
{ PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V }, // 1287
|
|
{ PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V }, // 1288
|
|
{ PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V }, // 1289
|
|
{ PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V }, // 1290
|
|
{ PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V }, // 1291
|
|
{ PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V }, // 1292
|
|
{ PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V }, // 1293
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V }, // 1294
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V }, // 1295
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V }, // 1296
|
|
{ PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V }, // 1297
|
|
{ PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V }, // 1298
|
|
{ PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V }, // 1299
|
|
{ PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V }, // 1300
|
|
{ PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V }, // 1301
|
|
{ PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V }, // 1302
|
|
{ PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V }, // 1303
|
|
{ PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V }, // 1304
|
|
{ PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V }, // 1305
|
|
{ PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V }, // 1306
|
|
{ PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V }, // 1307
|
|
{ PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V }, // 1308
|
|
{ PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V }, // 1309
|
|
{ PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V }, // 1310
|
|
{ PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V }, // 1311
|
|
{ PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V }, // 1312
|
|
{ PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V }, // 1313
|
|
{ PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V }, // 1314
|
|
{ PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V }, // 1315
|
|
{ PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V }, // 1316
|
|
{ PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V }, // 1317
|
|
{ PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V }, // 1318
|
|
{ PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V }, // 1319
|
|
{ PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V }, // 1320
|
|
{ PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V }, // 1321
|
|
{ PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF }, // 1322
|
|
{ PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF }, // 1323
|
|
{ PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF }, // 1324
|
|
{ PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF }, // 1325
|
|
{ PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF }, // 1326
|
|
{ PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF }, // 1327
|
|
{ PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF }, // 1328
|
|
{ PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF }, // 1329
|
|
{ PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF }, // 1330
|
|
{ PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF }, // 1331
|
|
{ PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF }, // 1332
|
|
{ PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF }, // 1333
|
|
{ PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF }, // 1334
|
|
{ PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF }, // 1335
|
|
{ PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF }, // 1336
|
|
{ PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF }, // 1337
|
|
{ PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF }, // 1338
|
|
{ PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF }, // 1339
|
|
{ PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF }, // 1340
|
|
{ PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF }, // 1341
|
|
{ PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF }, // 1342
|
|
{ PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF }, // 1343
|
|
{ PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF }, // 1344
|
|
{ PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF }, // 1345
|
|
{ PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF }, // 1346
|
|
{ PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF }, // 1347
|
|
{ PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF }, // 1348
|
|
{ PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF }, // 1349
|
|
{ PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF }, // 1350
|
|
{ PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF }, // 1351
|
|
{ PseudoVFDIV_VV_M1_E16, VFDIV_VV }, // 1352
|
|
{ PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV }, // 1353
|
|
{ PseudoVFDIV_VV_M1_E32, VFDIV_VV }, // 1354
|
|
{ PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV }, // 1355
|
|
{ PseudoVFDIV_VV_M1_E64, VFDIV_VV }, // 1356
|
|
{ PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV }, // 1357
|
|
{ PseudoVFDIV_VV_M2_E16, VFDIV_VV }, // 1358
|
|
{ PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV }, // 1359
|
|
{ PseudoVFDIV_VV_M2_E32, VFDIV_VV }, // 1360
|
|
{ PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV }, // 1361
|
|
{ PseudoVFDIV_VV_M2_E64, VFDIV_VV }, // 1362
|
|
{ PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV }, // 1363
|
|
{ PseudoVFDIV_VV_M4_E16, VFDIV_VV }, // 1364
|
|
{ PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV }, // 1365
|
|
{ PseudoVFDIV_VV_M4_E32, VFDIV_VV }, // 1366
|
|
{ PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV }, // 1367
|
|
{ PseudoVFDIV_VV_M4_E64, VFDIV_VV }, // 1368
|
|
{ PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV }, // 1369
|
|
{ PseudoVFDIV_VV_M8_E16, VFDIV_VV }, // 1370
|
|
{ PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV }, // 1371
|
|
{ PseudoVFDIV_VV_M8_E32, VFDIV_VV }, // 1372
|
|
{ PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV }, // 1373
|
|
{ PseudoVFDIV_VV_M8_E64, VFDIV_VV }, // 1374
|
|
{ PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV }, // 1375
|
|
{ PseudoVFDIV_VV_MF2_E16, VFDIV_VV }, // 1376
|
|
{ PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV }, // 1377
|
|
{ PseudoVFDIV_VV_MF2_E32, VFDIV_VV }, // 1378
|
|
{ PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV }, // 1379
|
|
{ PseudoVFDIV_VV_MF4_E16, VFDIV_VV }, // 1380
|
|
{ PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV }, // 1381
|
|
{ PseudoVFIRST_M_B1, VFIRST_M }, // 1382
|
|
{ PseudoVFIRST_M_B16, VFIRST_M }, // 1383
|
|
{ PseudoVFIRST_M_B16_MASK, VFIRST_M }, // 1384
|
|
{ PseudoVFIRST_M_B1_MASK, VFIRST_M }, // 1385
|
|
{ PseudoVFIRST_M_B2, VFIRST_M }, // 1386
|
|
{ PseudoVFIRST_M_B2_MASK, VFIRST_M }, // 1387
|
|
{ PseudoVFIRST_M_B32, VFIRST_M }, // 1388
|
|
{ PseudoVFIRST_M_B32_MASK, VFIRST_M }, // 1389
|
|
{ PseudoVFIRST_M_B4, VFIRST_M }, // 1390
|
|
{ PseudoVFIRST_M_B4_MASK, VFIRST_M }, // 1391
|
|
{ PseudoVFIRST_M_B64, VFIRST_M }, // 1392
|
|
{ PseudoVFIRST_M_B64_MASK, VFIRST_M }, // 1393
|
|
{ PseudoVFIRST_M_B8, VFIRST_M }, // 1394
|
|
{ PseudoVFIRST_M_B8_MASK, VFIRST_M }, // 1395
|
|
{ PseudoVFMACC_VFPR16_M1, VFMACC_VF }, // 1396
|
|
{ PseudoVFMACC_VFPR16_M1_MASK, VFMACC_VF }, // 1397
|
|
{ PseudoVFMACC_VFPR16_M2, VFMACC_VF }, // 1398
|
|
{ PseudoVFMACC_VFPR16_M2_MASK, VFMACC_VF }, // 1399
|
|
{ PseudoVFMACC_VFPR16_M4, VFMACC_VF }, // 1400
|
|
{ PseudoVFMACC_VFPR16_M4_MASK, VFMACC_VF }, // 1401
|
|
{ PseudoVFMACC_VFPR16_M8, VFMACC_VF }, // 1402
|
|
{ PseudoVFMACC_VFPR16_M8_MASK, VFMACC_VF }, // 1403
|
|
{ PseudoVFMACC_VFPR16_MF2, VFMACC_VF }, // 1404
|
|
{ PseudoVFMACC_VFPR16_MF2_MASK, VFMACC_VF }, // 1405
|
|
{ PseudoVFMACC_VFPR16_MF4, VFMACC_VF }, // 1406
|
|
{ PseudoVFMACC_VFPR16_MF4_MASK, VFMACC_VF }, // 1407
|
|
{ PseudoVFMACC_VFPR32_M1, VFMACC_VF }, // 1408
|
|
{ PseudoVFMACC_VFPR32_M1_MASK, VFMACC_VF }, // 1409
|
|
{ PseudoVFMACC_VFPR32_M2, VFMACC_VF }, // 1410
|
|
{ PseudoVFMACC_VFPR32_M2_MASK, VFMACC_VF }, // 1411
|
|
{ PseudoVFMACC_VFPR32_M4, VFMACC_VF }, // 1412
|
|
{ PseudoVFMACC_VFPR32_M4_MASK, VFMACC_VF }, // 1413
|
|
{ PseudoVFMACC_VFPR32_M8, VFMACC_VF }, // 1414
|
|
{ PseudoVFMACC_VFPR32_M8_MASK, VFMACC_VF }, // 1415
|
|
{ PseudoVFMACC_VFPR32_MF2, VFMACC_VF }, // 1416
|
|
{ PseudoVFMACC_VFPR32_MF2_MASK, VFMACC_VF }, // 1417
|
|
{ PseudoVFMACC_VFPR64_M1, VFMACC_VF }, // 1418
|
|
{ PseudoVFMACC_VFPR64_M1_MASK, VFMACC_VF }, // 1419
|
|
{ PseudoVFMACC_VFPR64_M2, VFMACC_VF }, // 1420
|
|
{ PseudoVFMACC_VFPR64_M2_MASK, VFMACC_VF }, // 1421
|
|
{ PseudoVFMACC_VFPR64_M4, VFMACC_VF }, // 1422
|
|
{ PseudoVFMACC_VFPR64_M4_MASK, VFMACC_VF }, // 1423
|
|
{ PseudoVFMACC_VFPR64_M8, VFMACC_VF }, // 1424
|
|
{ PseudoVFMACC_VFPR64_M8_MASK, VFMACC_VF }, // 1425
|
|
{ PseudoVFMACC_VV_M1, VFMACC_VV }, // 1426
|
|
{ PseudoVFMACC_VV_M1_MASK, VFMACC_VV }, // 1427
|
|
{ PseudoVFMACC_VV_M2, VFMACC_VV }, // 1428
|
|
{ PseudoVFMACC_VV_M2_MASK, VFMACC_VV }, // 1429
|
|
{ PseudoVFMACC_VV_M4, VFMACC_VV }, // 1430
|
|
{ PseudoVFMACC_VV_M4_MASK, VFMACC_VV }, // 1431
|
|
{ PseudoVFMACC_VV_M8, VFMACC_VV }, // 1432
|
|
{ PseudoVFMACC_VV_M8_MASK, VFMACC_VV }, // 1433
|
|
{ PseudoVFMACC_VV_MF2, VFMACC_VV }, // 1434
|
|
{ PseudoVFMACC_VV_MF2_MASK, VFMACC_VV }, // 1435
|
|
{ PseudoVFMACC_VV_MF4, VFMACC_VV }, // 1436
|
|
{ PseudoVFMACC_VV_MF4_MASK, VFMACC_VV }, // 1437
|
|
{ PseudoVFMADD_VFPR16_M1, VFMADD_VF }, // 1438
|
|
{ PseudoVFMADD_VFPR16_M1_MASK, VFMADD_VF }, // 1439
|
|
{ PseudoVFMADD_VFPR16_M2, VFMADD_VF }, // 1440
|
|
{ PseudoVFMADD_VFPR16_M2_MASK, VFMADD_VF }, // 1441
|
|
{ PseudoVFMADD_VFPR16_M4, VFMADD_VF }, // 1442
|
|
{ PseudoVFMADD_VFPR16_M4_MASK, VFMADD_VF }, // 1443
|
|
{ PseudoVFMADD_VFPR16_M8, VFMADD_VF }, // 1444
|
|
{ PseudoVFMADD_VFPR16_M8_MASK, VFMADD_VF }, // 1445
|
|
{ PseudoVFMADD_VFPR16_MF2, VFMADD_VF }, // 1446
|
|
{ PseudoVFMADD_VFPR16_MF2_MASK, VFMADD_VF }, // 1447
|
|
{ PseudoVFMADD_VFPR16_MF4, VFMADD_VF }, // 1448
|
|
{ PseudoVFMADD_VFPR16_MF4_MASK, VFMADD_VF }, // 1449
|
|
{ PseudoVFMADD_VFPR32_M1, VFMADD_VF }, // 1450
|
|
{ PseudoVFMADD_VFPR32_M1_MASK, VFMADD_VF }, // 1451
|
|
{ PseudoVFMADD_VFPR32_M2, VFMADD_VF }, // 1452
|
|
{ PseudoVFMADD_VFPR32_M2_MASK, VFMADD_VF }, // 1453
|
|
{ PseudoVFMADD_VFPR32_M4, VFMADD_VF }, // 1454
|
|
{ PseudoVFMADD_VFPR32_M4_MASK, VFMADD_VF }, // 1455
|
|
{ PseudoVFMADD_VFPR32_M8, VFMADD_VF }, // 1456
|
|
{ PseudoVFMADD_VFPR32_M8_MASK, VFMADD_VF }, // 1457
|
|
{ PseudoVFMADD_VFPR32_MF2, VFMADD_VF }, // 1458
|
|
{ PseudoVFMADD_VFPR32_MF2_MASK, VFMADD_VF }, // 1459
|
|
{ PseudoVFMADD_VFPR64_M1, VFMADD_VF }, // 1460
|
|
{ PseudoVFMADD_VFPR64_M1_MASK, VFMADD_VF }, // 1461
|
|
{ PseudoVFMADD_VFPR64_M2, VFMADD_VF }, // 1462
|
|
{ PseudoVFMADD_VFPR64_M2_MASK, VFMADD_VF }, // 1463
|
|
{ PseudoVFMADD_VFPR64_M4, VFMADD_VF }, // 1464
|
|
{ PseudoVFMADD_VFPR64_M4_MASK, VFMADD_VF }, // 1465
|
|
{ PseudoVFMADD_VFPR64_M8, VFMADD_VF }, // 1466
|
|
{ PseudoVFMADD_VFPR64_M8_MASK, VFMADD_VF }, // 1467
|
|
{ PseudoVFMADD_VV_M1, VFMADD_VV }, // 1468
|
|
{ PseudoVFMADD_VV_M1_MASK, VFMADD_VV }, // 1469
|
|
{ PseudoVFMADD_VV_M2, VFMADD_VV }, // 1470
|
|
{ PseudoVFMADD_VV_M2_MASK, VFMADD_VV }, // 1471
|
|
{ PseudoVFMADD_VV_M4, VFMADD_VV }, // 1472
|
|
{ PseudoVFMADD_VV_M4_MASK, VFMADD_VV }, // 1473
|
|
{ PseudoVFMADD_VV_M8, VFMADD_VV }, // 1474
|
|
{ PseudoVFMADD_VV_M8_MASK, VFMADD_VV }, // 1475
|
|
{ PseudoVFMADD_VV_MF2, VFMADD_VV }, // 1476
|
|
{ PseudoVFMADD_VV_MF2_MASK, VFMADD_VV }, // 1477
|
|
{ PseudoVFMADD_VV_MF4, VFMADD_VV }, // 1478
|
|
{ PseudoVFMADD_VV_MF4_MASK, VFMADD_VV }, // 1479
|
|
{ PseudoVFMAX_VFPR16_M1, VFMAX_VF }, // 1480
|
|
{ PseudoVFMAX_VFPR16_M1_MASK, VFMAX_VF }, // 1481
|
|
{ PseudoVFMAX_VFPR16_M2, VFMAX_VF }, // 1482
|
|
{ PseudoVFMAX_VFPR16_M2_MASK, VFMAX_VF }, // 1483
|
|
{ PseudoVFMAX_VFPR16_M4, VFMAX_VF }, // 1484
|
|
{ PseudoVFMAX_VFPR16_M4_MASK, VFMAX_VF }, // 1485
|
|
{ PseudoVFMAX_VFPR16_M8, VFMAX_VF }, // 1486
|
|
{ PseudoVFMAX_VFPR16_M8_MASK, VFMAX_VF }, // 1487
|
|
{ PseudoVFMAX_VFPR16_MF2, VFMAX_VF }, // 1488
|
|
{ PseudoVFMAX_VFPR16_MF2_MASK, VFMAX_VF }, // 1489
|
|
{ PseudoVFMAX_VFPR16_MF4, VFMAX_VF }, // 1490
|
|
{ PseudoVFMAX_VFPR16_MF4_MASK, VFMAX_VF }, // 1491
|
|
{ PseudoVFMAX_VFPR32_M1, VFMAX_VF }, // 1492
|
|
{ PseudoVFMAX_VFPR32_M1_MASK, VFMAX_VF }, // 1493
|
|
{ PseudoVFMAX_VFPR32_M2, VFMAX_VF }, // 1494
|
|
{ PseudoVFMAX_VFPR32_M2_MASK, VFMAX_VF }, // 1495
|
|
{ PseudoVFMAX_VFPR32_M4, VFMAX_VF }, // 1496
|
|
{ PseudoVFMAX_VFPR32_M4_MASK, VFMAX_VF }, // 1497
|
|
{ PseudoVFMAX_VFPR32_M8, VFMAX_VF }, // 1498
|
|
{ PseudoVFMAX_VFPR32_M8_MASK, VFMAX_VF }, // 1499
|
|
{ PseudoVFMAX_VFPR32_MF2, VFMAX_VF }, // 1500
|
|
{ PseudoVFMAX_VFPR32_MF2_MASK, VFMAX_VF }, // 1501
|
|
{ PseudoVFMAX_VFPR64_M1, VFMAX_VF }, // 1502
|
|
{ PseudoVFMAX_VFPR64_M1_MASK, VFMAX_VF }, // 1503
|
|
{ PseudoVFMAX_VFPR64_M2, VFMAX_VF }, // 1504
|
|
{ PseudoVFMAX_VFPR64_M2_MASK, VFMAX_VF }, // 1505
|
|
{ PseudoVFMAX_VFPR64_M4, VFMAX_VF }, // 1506
|
|
{ PseudoVFMAX_VFPR64_M4_MASK, VFMAX_VF }, // 1507
|
|
{ PseudoVFMAX_VFPR64_M8, VFMAX_VF }, // 1508
|
|
{ PseudoVFMAX_VFPR64_M8_MASK, VFMAX_VF }, // 1509
|
|
{ PseudoVFMAX_VV_M1, VFMAX_VV }, // 1510
|
|
{ PseudoVFMAX_VV_M1_MASK, VFMAX_VV }, // 1511
|
|
{ PseudoVFMAX_VV_M2, VFMAX_VV }, // 1512
|
|
{ PseudoVFMAX_VV_M2_MASK, VFMAX_VV }, // 1513
|
|
{ PseudoVFMAX_VV_M4, VFMAX_VV }, // 1514
|
|
{ PseudoVFMAX_VV_M4_MASK, VFMAX_VV }, // 1515
|
|
{ PseudoVFMAX_VV_M8, VFMAX_VV }, // 1516
|
|
{ PseudoVFMAX_VV_M8_MASK, VFMAX_VV }, // 1517
|
|
{ PseudoVFMAX_VV_MF2, VFMAX_VV }, // 1518
|
|
{ PseudoVFMAX_VV_MF2_MASK, VFMAX_VV }, // 1519
|
|
{ PseudoVFMAX_VV_MF4, VFMAX_VV }, // 1520
|
|
{ PseudoVFMAX_VV_MF4_MASK, VFMAX_VV }, // 1521
|
|
{ PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM }, // 1522
|
|
{ PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM }, // 1523
|
|
{ PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM }, // 1524
|
|
{ PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM }, // 1525
|
|
{ PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM }, // 1526
|
|
{ PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM }, // 1527
|
|
{ PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM }, // 1528
|
|
{ PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM }, // 1529
|
|
{ PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM }, // 1530
|
|
{ PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM }, // 1531
|
|
{ PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM }, // 1532
|
|
{ PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM }, // 1533
|
|
{ PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM }, // 1534
|
|
{ PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM }, // 1535
|
|
{ PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM }, // 1536
|
|
{ PseudoVFMIN_VFPR16_M1, VFMIN_VF }, // 1537
|
|
{ PseudoVFMIN_VFPR16_M1_MASK, VFMIN_VF }, // 1538
|
|
{ PseudoVFMIN_VFPR16_M2, VFMIN_VF }, // 1539
|
|
{ PseudoVFMIN_VFPR16_M2_MASK, VFMIN_VF }, // 1540
|
|
{ PseudoVFMIN_VFPR16_M4, VFMIN_VF }, // 1541
|
|
{ PseudoVFMIN_VFPR16_M4_MASK, VFMIN_VF }, // 1542
|
|
{ PseudoVFMIN_VFPR16_M8, VFMIN_VF }, // 1543
|
|
{ PseudoVFMIN_VFPR16_M8_MASK, VFMIN_VF }, // 1544
|
|
{ PseudoVFMIN_VFPR16_MF2, VFMIN_VF }, // 1545
|
|
{ PseudoVFMIN_VFPR16_MF2_MASK, VFMIN_VF }, // 1546
|
|
{ PseudoVFMIN_VFPR16_MF4, VFMIN_VF }, // 1547
|
|
{ PseudoVFMIN_VFPR16_MF4_MASK, VFMIN_VF }, // 1548
|
|
{ PseudoVFMIN_VFPR32_M1, VFMIN_VF }, // 1549
|
|
{ PseudoVFMIN_VFPR32_M1_MASK, VFMIN_VF }, // 1550
|
|
{ PseudoVFMIN_VFPR32_M2, VFMIN_VF }, // 1551
|
|
{ PseudoVFMIN_VFPR32_M2_MASK, VFMIN_VF }, // 1552
|
|
{ PseudoVFMIN_VFPR32_M4, VFMIN_VF }, // 1553
|
|
{ PseudoVFMIN_VFPR32_M4_MASK, VFMIN_VF }, // 1554
|
|
{ PseudoVFMIN_VFPR32_M8, VFMIN_VF }, // 1555
|
|
{ PseudoVFMIN_VFPR32_M8_MASK, VFMIN_VF }, // 1556
|
|
{ PseudoVFMIN_VFPR32_MF2, VFMIN_VF }, // 1557
|
|
{ PseudoVFMIN_VFPR32_MF2_MASK, VFMIN_VF }, // 1558
|
|
{ PseudoVFMIN_VFPR64_M1, VFMIN_VF }, // 1559
|
|
{ PseudoVFMIN_VFPR64_M1_MASK, VFMIN_VF }, // 1560
|
|
{ PseudoVFMIN_VFPR64_M2, VFMIN_VF }, // 1561
|
|
{ PseudoVFMIN_VFPR64_M2_MASK, VFMIN_VF }, // 1562
|
|
{ PseudoVFMIN_VFPR64_M4, VFMIN_VF }, // 1563
|
|
{ PseudoVFMIN_VFPR64_M4_MASK, VFMIN_VF }, // 1564
|
|
{ PseudoVFMIN_VFPR64_M8, VFMIN_VF }, // 1565
|
|
{ PseudoVFMIN_VFPR64_M8_MASK, VFMIN_VF }, // 1566
|
|
{ PseudoVFMIN_VV_M1, VFMIN_VV }, // 1567
|
|
{ PseudoVFMIN_VV_M1_MASK, VFMIN_VV }, // 1568
|
|
{ PseudoVFMIN_VV_M2, VFMIN_VV }, // 1569
|
|
{ PseudoVFMIN_VV_M2_MASK, VFMIN_VV }, // 1570
|
|
{ PseudoVFMIN_VV_M4, VFMIN_VV }, // 1571
|
|
{ PseudoVFMIN_VV_M4_MASK, VFMIN_VV }, // 1572
|
|
{ PseudoVFMIN_VV_M8, VFMIN_VV }, // 1573
|
|
{ PseudoVFMIN_VV_M8_MASK, VFMIN_VV }, // 1574
|
|
{ PseudoVFMIN_VV_MF2, VFMIN_VV }, // 1575
|
|
{ PseudoVFMIN_VV_MF2_MASK, VFMIN_VV }, // 1576
|
|
{ PseudoVFMIN_VV_MF4, VFMIN_VV }, // 1577
|
|
{ PseudoVFMIN_VV_MF4_MASK, VFMIN_VV }, // 1578
|
|
{ PseudoVFMSAC_VFPR16_M1, VFMSAC_VF }, // 1579
|
|
{ PseudoVFMSAC_VFPR16_M1_MASK, VFMSAC_VF }, // 1580
|
|
{ PseudoVFMSAC_VFPR16_M2, VFMSAC_VF }, // 1581
|
|
{ PseudoVFMSAC_VFPR16_M2_MASK, VFMSAC_VF }, // 1582
|
|
{ PseudoVFMSAC_VFPR16_M4, VFMSAC_VF }, // 1583
|
|
{ PseudoVFMSAC_VFPR16_M4_MASK, VFMSAC_VF }, // 1584
|
|
{ PseudoVFMSAC_VFPR16_M8, VFMSAC_VF }, // 1585
|
|
{ PseudoVFMSAC_VFPR16_M8_MASK, VFMSAC_VF }, // 1586
|
|
{ PseudoVFMSAC_VFPR16_MF2, VFMSAC_VF }, // 1587
|
|
{ PseudoVFMSAC_VFPR16_MF2_MASK, VFMSAC_VF }, // 1588
|
|
{ PseudoVFMSAC_VFPR16_MF4, VFMSAC_VF }, // 1589
|
|
{ PseudoVFMSAC_VFPR16_MF4_MASK, VFMSAC_VF }, // 1590
|
|
{ PseudoVFMSAC_VFPR32_M1, VFMSAC_VF }, // 1591
|
|
{ PseudoVFMSAC_VFPR32_M1_MASK, VFMSAC_VF }, // 1592
|
|
{ PseudoVFMSAC_VFPR32_M2, VFMSAC_VF }, // 1593
|
|
{ PseudoVFMSAC_VFPR32_M2_MASK, VFMSAC_VF }, // 1594
|
|
{ PseudoVFMSAC_VFPR32_M4, VFMSAC_VF }, // 1595
|
|
{ PseudoVFMSAC_VFPR32_M4_MASK, VFMSAC_VF }, // 1596
|
|
{ PseudoVFMSAC_VFPR32_M8, VFMSAC_VF }, // 1597
|
|
{ PseudoVFMSAC_VFPR32_M8_MASK, VFMSAC_VF }, // 1598
|
|
{ PseudoVFMSAC_VFPR32_MF2, VFMSAC_VF }, // 1599
|
|
{ PseudoVFMSAC_VFPR32_MF2_MASK, VFMSAC_VF }, // 1600
|
|
{ PseudoVFMSAC_VFPR64_M1, VFMSAC_VF }, // 1601
|
|
{ PseudoVFMSAC_VFPR64_M1_MASK, VFMSAC_VF }, // 1602
|
|
{ PseudoVFMSAC_VFPR64_M2, VFMSAC_VF }, // 1603
|
|
{ PseudoVFMSAC_VFPR64_M2_MASK, VFMSAC_VF }, // 1604
|
|
{ PseudoVFMSAC_VFPR64_M4, VFMSAC_VF }, // 1605
|
|
{ PseudoVFMSAC_VFPR64_M4_MASK, VFMSAC_VF }, // 1606
|
|
{ PseudoVFMSAC_VFPR64_M8, VFMSAC_VF }, // 1607
|
|
{ PseudoVFMSAC_VFPR64_M8_MASK, VFMSAC_VF }, // 1608
|
|
{ PseudoVFMSAC_VV_M1, VFMSAC_VV }, // 1609
|
|
{ PseudoVFMSAC_VV_M1_MASK, VFMSAC_VV }, // 1610
|
|
{ PseudoVFMSAC_VV_M2, VFMSAC_VV }, // 1611
|
|
{ PseudoVFMSAC_VV_M2_MASK, VFMSAC_VV }, // 1612
|
|
{ PseudoVFMSAC_VV_M4, VFMSAC_VV }, // 1613
|
|
{ PseudoVFMSAC_VV_M4_MASK, VFMSAC_VV }, // 1614
|
|
{ PseudoVFMSAC_VV_M8, VFMSAC_VV }, // 1615
|
|
{ PseudoVFMSAC_VV_M8_MASK, VFMSAC_VV }, // 1616
|
|
{ PseudoVFMSAC_VV_MF2, VFMSAC_VV }, // 1617
|
|
{ PseudoVFMSAC_VV_MF2_MASK, VFMSAC_VV }, // 1618
|
|
{ PseudoVFMSAC_VV_MF4, VFMSAC_VV }, // 1619
|
|
{ PseudoVFMSAC_VV_MF4_MASK, VFMSAC_VV }, // 1620
|
|
{ PseudoVFMSUB_VFPR16_M1, VFMSUB_VF }, // 1621
|
|
{ PseudoVFMSUB_VFPR16_M1_MASK, VFMSUB_VF }, // 1622
|
|
{ PseudoVFMSUB_VFPR16_M2, VFMSUB_VF }, // 1623
|
|
{ PseudoVFMSUB_VFPR16_M2_MASK, VFMSUB_VF }, // 1624
|
|
{ PseudoVFMSUB_VFPR16_M4, VFMSUB_VF }, // 1625
|
|
{ PseudoVFMSUB_VFPR16_M4_MASK, VFMSUB_VF }, // 1626
|
|
{ PseudoVFMSUB_VFPR16_M8, VFMSUB_VF }, // 1627
|
|
{ PseudoVFMSUB_VFPR16_M8_MASK, VFMSUB_VF }, // 1628
|
|
{ PseudoVFMSUB_VFPR16_MF2, VFMSUB_VF }, // 1629
|
|
{ PseudoVFMSUB_VFPR16_MF2_MASK, VFMSUB_VF }, // 1630
|
|
{ PseudoVFMSUB_VFPR16_MF4, VFMSUB_VF }, // 1631
|
|
{ PseudoVFMSUB_VFPR16_MF4_MASK, VFMSUB_VF }, // 1632
|
|
{ PseudoVFMSUB_VFPR32_M1, VFMSUB_VF }, // 1633
|
|
{ PseudoVFMSUB_VFPR32_M1_MASK, VFMSUB_VF }, // 1634
|
|
{ PseudoVFMSUB_VFPR32_M2, VFMSUB_VF }, // 1635
|
|
{ PseudoVFMSUB_VFPR32_M2_MASK, VFMSUB_VF }, // 1636
|
|
{ PseudoVFMSUB_VFPR32_M4, VFMSUB_VF }, // 1637
|
|
{ PseudoVFMSUB_VFPR32_M4_MASK, VFMSUB_VF }, // 1638
|
|
{ PseudoVFMSUB_VFPR32_M8, VFMSUB_VF }, // 1639
|
|
{ PseudoVFMSUB_VFPR32_M8_MASK, VFMSUB_VF }, // 1640
|
|
{ PseudoVFMSUB_VFPR32_MF2, VFMSUB_VF }, // 1641
|
|
{ PseudoVFMSUB_VFPR32_MF2_MASK, VFMSUB_VF }, // 1642
|
|
{ PseudoVFMSUB_VFPR64_M1, VFMSUB_VF }, // 1643
|
|
{ PseudoVFMSUB_VFPR64_M1_MASK, VFMSUB_VF }, // 1644
|
|
{ PseudoVFMSUB_VFPR64_M2, VFMSUB_VF }, // 1645
|
|
{ PseudoVFMSUB_VFPR64_M2_MASK, VFMSUB_VF }, // 1646
|
|
{ PseudoVFMSUB_VFPR64_M4, VFMSUB_VF }, // 1647
|
|
{ PseudoVFMSUB_VFPR64_M4_MASK, VFMSUB_VF }, // 1648
|
|
{ PseudoVFMSUB_VFPR64_M8, VFMSUB_VF }, // 1649
|
|
{ PseudoVFMSUB_VFPR64_M8_MASK, VFMSUB_VF }, // 1650
|
|
{ PseudoVFMSUB_VV_M1, VFMSUB_VV }, // 1651
|
|
{ PseudoVFMSUB_VV_M1_MASK, VFMSUB_VV }, // 1652
|
|
{ PseudoVFMSUB_VV_M2, VFMSUB_VV }, // 1653
|
|
{ PseudoVFMSUB_VV_M2_MASK, VFMSUB_VV }, // 1654
|
|
{ PseudoVFMSUB_VV_M4, VFMSUB_VV }, // 1655
|
|
{ PseudoVFMSUB_VV_M4_MASK, VFMSUB_VV }, // 1656
|
|
{ PseudoVFMSUB_VV_M8, VFMSUB_VV }, // 1657
|
|
{ PseudoVFMSUB_VV_M8_MASK, VFMSUB_VV }, // 1658
|
|
{ PseudoVFMSUB_VV_MF2, VFMSUB_VV }, // 1659
|
|
{ PseudoVFMSUB_VV_MF2_MASK, VFMSUB_VV }, // 1660
|
|
{ PseudoVFMSUB_VV_MF4, VFMSUB_VV }, // 1661
|
|
{ PseudoVFMSUB_VV_MF4_MASK, VFMSUB_VV }, // 1662
|
|
{ PseudoVFMUL_VFPR16_M1, VFMUL_VF }, // 1663
|
|
{ PseudoVFMUL_VFPR16_M1_MASK, VFMUL_VF }, // 1664
|
|
{ PseudoVFMUL_VFPR16_M2, VFMUL_VF }, // 1665
|
|
{ PseudoVFMUL_VFPR16_M2_MASK, VFMUL_VF }, // 1666
|
|
{ PseudoVFMUL_VFPR16_M4, VFMUL_VF }, // 1667
|
|
{ PseudoVFMUL_VFPR16_M4_MASK, VFMUL_VF }, // 1668
|
|
{ PseudoVFMUL_VFPR16_M8, VFMUL_VF }, // 1669
|
|
{ PseudoVFMUL_VFPR16_M8_MASK, VFMUL_VF }, // 1670
|
|
{ PseudoVFMUL_VFPR16_MF2, VFMUL_VF }, // 1671
|
|
{ PseudoVFMUL_VFPR16_MF2_MASK, VFMUL_VF }, // 1672
|
|
{ PseudoVFMUL_VFPR16_MF4, VFMUL_VF }, // 1673
|
|
{ PseudoVFMUL_VFPR16_MF4_MASK, VFMUL_VF }, // 1674
|
|
{ PseudoVFMUL_VFPR32_M1, VFMUL_VF }, // 1675
|
|
{ PseudoVFMUL_VFPR32_M1_MASK, VFMUL_VF }, // 1676
|
|
{ PseudoVFMUL_VFPR32_M2, VFMUL_VF }, // 1677
|
|
{ PseudoVFMUL_VFPR32_M2_MASK, VFMUL_VF }, // 1678
|
|
{ PseudoVFMUL_VFPR32_M4, VFMUL_VF }, // 1679
|
|
{ PseudoVFMUL_VFPR32_M4_MASK, VFMUL_VF }, // 1680
|
|
{ PseudoVFMUL_VFPR32_M8, VFMUL_VF }, // 1681
|
|
{ PseudoVFMUL_VFPR32_M8_MASK, VFMUL_VF }, // 1682
|
|
{ PseudoVFMUL_VFPR32_MF2, VFMUL_VF }, // 1683
|
|
{ PseudoVFMUL_VFPR32_MF2_MASK, VFMUL_VF }, // 1684
|
|
{ PseudoVFMUL_VFPR64_M1, VFMUL_VF }, // 1685
|
|
{ PseudoVFMUL_VFPR64_M1_MASK, VFMUL_VF }, // 1686
|
|
{ PseudoVFMUL_VFPR64_M2, VFMUL_VF }, // 1687
|
|
{ PseudoVFMUL_VFPR64_M2_MASK, VFMUL_VF }, // 1688
|
|
{ PseudoVFMUL_VFPR64_M4, VFMUL_VF }, // 1689
|
|
{ PseudoVFMUL_VFPR64_M4_MASK, VFMUL_VF }, // 1690
|
|
{ PseudoVFMUL_VFPR64_M8, VFMUL_VF }, // 1691
|
|
{ PseudoVFMUL_VFPR64_M8_MASK, VFMUL_VF }, // 1692
|
|
{ PseudoVFMUL_VV_M1, VFMUL_VV }, // 1693
|
|
{ PseudoVFMUL_VV_M1_MASK, VFMUL_VV }, // 1694
|
|
{ PseudoVFMUL_VV_M2, VFMUL_VV }, // 1695
|
|
{ PseudoVFMUL_VV_M2_MASK, VFMUL_VV }, // 1696
|
|
{ PseudoVFMUL_VV_M4, VFMUL_VV }, // 1697
|
|
{ PseudoVFMUL_VV_M4_MASK, VFMUL_VV }, // 1698
|
|
{ PseudoVFMUL_VV_M8, VFMUL_VV }, // 1699
|
|
{ PseudoVFMUL_VV_M8_MASK, VFMUL_VV }, // 1700
|
|
{ PseudoVFMUL_VV_MF2, VFMUL_VV }, // 1701
|
|
{ PseudoVFMUL_VV_MF2_MASK, VFMUL_VV }, // 1702
|
|
{ PseudoVFMUL_VV_MF4, VFMUL_VV }, // 1703
|
|
{ PseudoVFMUL_VV_MF4_MASK, VFMUL_VV }, // 1704
|
|
{ PseudoVFMV_FPR16_S_M1, VFMV_F_S }, // 1705
|
|
{ PseudoVFMV_FPR16_S_M2, VFMV_F_S }, // 1706
|
|
{ PseudoVFMV_FPR16_S_M4, VFMV_F_S }, // 1707
|
|
{ PseudoVFMV_FPR16_S_M8, VFMV_F_S }, // 1708
|
|
{ PseudoVFMV_FPR16_S_MF2, VFMV_F_S }, // 1709
|
|
{ PseudoVFMV_FPR16_S_MF4, VFMV_F_S }, // 1710
|
|
{ PseudoVFMV_FPR32_S_M1, VFMV_F_S }, // 1711
|
|
{ PseudoVFMV_FPR32_S_M2, VFMV_F_S }, // 1712
|
|
{ PseudoVFMV_FPR32_S_M4, VFMV_F_S }, // 1713
|
|
{ PseudoVFMV_FPR32_S_M8, VFMV_F_S }, // 1714
|
|
{ PseudoVFMV_FPR32_S_MF2, VFMV_F_S }, // 1715
|
|
{ PseudoVFMV_FPR64_S_M1, VFMV_F_S }, // 1716
|
|
{ PseudoVFMV_FPR64_S_M2, VFMV_F_S }, // 1717
|
|
{ PseudoVFMV_FPR64_S_M4, VFMV_F_S }, // 1718
|
|
{ PseudoVFMV_FPR64_S_M8, VFMV_F_S }, // 1719
|
|
{ PseudoVFMV_S_FPR16_M1, VFMV_S_F }, // 1720
|
|
{ PseudoVFMV_S_FPR16_M2, VFMV_S_F }, // 1721
|
|
{ PseudoVFMV_S_FPR16_M4, VFMV_S_F }, // 1722
|
|
{ PseudoVFMV_S_FPR16_M8, VFMV_S_F }, // 1723
|
|
{ PseudoVFMV_S_FPR16_MF2, VFMV_S_F }, // 1724
|
|
{ PseudoVFMV_S_FPR16_MF4, VFMV_S_F }, // 1725
|
|
{ PseudoVFMV_S_FPR32_M1, VFMV_S_F }, // 1726
|
|
{ PseudoVFMV_S_FPR32_M2, VFMV_S_F }, // 1727
|
|
{ PseudoVFMV_S_FPR32_M4, VFMV_S_F }, // 1728
|
|
{ PseudoVFMV_S_FPR32_M8, VFMV_S_F }, // 1729
|
|
{ PseudoVFMV_S_FPR32_MF2, VFMV_S_F }, // 1730
|
|
{ PseudoVFMV_S_FPR64_M1, VFMV_S_F }, // 1731
|
|
{ PseudoVFMV_S_FPR64_M2, VFMV_S_F }, // 1732
|
|
{ PseudoVFMV_S_FPR64_M4, VFMV_S_F }, // 1733
|
|
{ PseudoVFMV_S_FPR64_M8, VFMV_S_F }, // 1734
|
|
{ PseudoVFMV_V_FPR16_M1, VFMV_V_F }, // 1735
|
|
{ PseudoVFMV_V_FPR16_M2, VFMV_V_F }, // 1736
|
|
{ PseudoVFMV_V_FPR16_M4, VFMV_V_F }, // 1737
|
|
{ PseudoVFMV_V_FPR16_M8, VFMV_V_F }, // 1738
|
|
{ PseudoVFMV_V_FPR16_MF2, VFMV_V_F }, // 1739
|
|
{ PseudoVFMV_V_FPR16_MF4, VFMV_V_F }, // 1740
|
|
{ PseudoVFMV_V_FPR32_M1, VFMV_V_F }, // 1741
|
|
{ PseudoVFMV_V_FPR32_M2, VFMV_V_F }, // 1742
|
|
{ PseudoVFMV_V_FPR32_M4, VFMV_V_F }, // 1743
|
|
{ PseudoVFMV_V_FPR32_M8, VFMV_V_F }, // 1744
|
|
{ PseudoVFMV_V_FPR32_MF2, VFMV_V_F }, // 1745
|
|
{ PseudoVFMV_V_FPR64_M1, VFMV_V_F }, // 1746
|
|
{ PseudoVFMV_V_FPR64_M2, VFMV_V_F }, // 1747
|
|
{ PseudoVFMV_V_FPR64_M4, VFMV_V_F }, // 1748
|
|
{ PseudoVFMV_V_FPR64_M8, VFMV_V_F }, // 1749
|
|
{ PseudoVFNCVTBF16_F_F_W_M1, VFNCVTBF16_F_F_W }, // 1750
|
|
{ PseudoVFNCVTBF16_F_F_W_M1_MASK, VFNCVTBF16_F_F_W }, // 1751
|
|
{ PseudoVFNCVTBF16_F_F_W_M2, VFNCVTBF16_F_F_W }, // 1752
|
|
{ PseudoVFNCVTBF16_F_F_W_M2_MASK, VFNCVTBF16_F_F_W }, // 1753
|
|
{ PseudoVFNCVTBF16_F_F_W_M4, VFNCVTBF16_F_F_W }, // 1754
|
|
{ PseudoVFNCVTBF16_F_F_W_M4_MASK, VFNCVTBF16_F_F_W }, // 1755
|
|
{ PseudoVFNCVTBF16_F_F_W_MF2, VFNCVTBF16_F_F_W }, // 1756
|
|
{ PseudoVFNCVTBF16_F_F_W_MF2_MASK, VFNCVTBF16_F_F_W }, // 1757
|
|
{ PseudoVFNCVTBF16_F_F_W_MF4, VFNCVTBF16_F_F_W }, // 1758
|
|
{ PseudoVFNCVTBF16_F_F_W_MF4_MASK, VFNCVTBF16_F_F_W }, // 1759
|
|
{ PseudoVFNCVT_F_F_W_M1, VFNCVT_F_F_W }, // 1760
|
|
{ PseudoVFNCVT_F_F_W_M1_MASK, VFNCVT_F_F_W }, // 1761
|
|
{ PseudoVFNCVT_F_F_W_M2, VFNCVT_F_F_W }, // 1762
|
|
{ PseudoVFNCVT_F_F_W_M2_MASK, VFNCVT_F_F_W }, // 1763
|
|
{ PseudoVFNCVT_F_F_W_M4, VFNCVT_F_F_W }, // 1764
|
|
{ PseudoVFNCVT_F_F_W_M4_MASK, VFNCVT_F_F_W }, // 1765
|
|
{ PseudoVFNCVT_F_F_W_MF2, VFNCVT_F_F_W }, // 1766
|
|
{ PseudoVFNCVT_F_F_W_MF2_MASK, VFNCVT_F_F_W }, // 1767
|
|
{ PseudoVFNCVT_F_F_W_MF4, VFNCVT_F_F_W }, // 1768
|
|
{ PseudoVFNCVT_F_F_W_MF4_MASK, VFNCVT_F_F_W }, // 1769
|
|
{ PseudoVFNCVT_F_XU_W_M1, VFNCVT_F_XU_W }, // 1770
|
|
{ PseudoVFNCVT_F_XU_W_M1_MASK, VFNCVT_F_XU_W }, // 1771
|
|
{ PseudoVFNCVT_F_XU_W_M2, VFNCVT_F_XU_W }, // 1772
|
|
{ PseudoVFNCVT_F_XU_W_M2_MASK, VFNCVT_F_XU_W }, // 1773
|
|
{ PseudoVFNCVT_F_XU_W_M4, VFNCVT_F_XU_W }, // 1774
|
|
{ PseudoVFNCVT_F_XU_W_M4_MASK, VFNCVT_F_XU_W }, // 1775
|
|
{ PseudoVFNCVT_F_XU_W_MF2, VFNCVT_F_XU_W }, // 1776
|
|
{ PseudoVFNCVT_F_XU_W_MF2_MASK, VFNCVT_F_XU_W }, // 1777
|
|
{ PseudoVFNCVT_F_XU_W_MF4, VFNCVT_F_XU_W }, // 1778
|
|
{ PseudoVFNCVT_F_XU_W_MF4_MASK, VFNCVT_F_XU_W }, // 1779
|
|
{ PseudoVFNCVT_F_X_W_M1, VFNCVT_F_X_W }, // 1780
|
|
{ PseudoVFNCVT_F_X_W_M1_MASK, VFNCVT_F_X_W }, // 1781
|
|
{ PseudoVFNCVT_F_X_W_M2, VFNCVT_F_X_W }, // 1782
|
|
{ PseudoVFNCVT_F_X_W_M2_MASK, VFNCVT_F_X_W }, // 1783
|
|
{ PseudoVFNCVT_F_X_W_M4, VFNCVT_F_X_W }, // 1784
|
|
{ PseudoVFNCVT_F_X_W_M4_MASK, VFNCVT_F_X_W }, // 1785
|
|
{ PseudoVFNCVT_F_X_W_MF2, VFNCVT_F_X_W }, // 1786
|
|
{ PseudoVFNCVT_F_X_W_MF2_MASK, VFNCVT_F_X_W }, // 1787
|
|
{ PseudoVFNCVT_F_X_W_MF4, VFNCVT_F_X_W }, // 1788
|
|
{ PseudoVFNCVT_F_X_W_MF4_MASK, VFNCVT_F_X_W }, // 1789
|
|
{ PseudoVFNCVT_RM_F_XU_W_M1, VFNCVT_F_XU_W }, // 1790
|
|
{ PseudoVFNCVT_RM_F_XU_W_M1_MASK, VFNCVT_F_XU_W }, // 1791
|
|
{ PseudoVFNCVT_RM_F_XU_W_M2, VFNCVT_F_XU_W }, // 1792
|
|
{ PseudoVFNCVT_RM_F_XU_W_M2_MASK, VFNCVT_F_XU_W }, // 1793
|
|
{ PseudoVFNCVT_RM_F_XU_W_M4, VFNCVT_F_XU_W }, // 1794
|
|
{ PseudoVFNCVT_RM_F_XU_W_M4_MASK, VFNCVT_F_XU_W }, // 1795
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF2, VFNCVT_F_XU_W }, // 1796
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF2_MASK, VFNCVT_F_XU_W }, // 1797
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF4, VFNCVT_F_XU_W }, // 1798
|
|
{ PseudoVFNCVT_RM_F_XU_W_MF4_MASK, VFNCVT_F_XU_W }, // 1799
|
|
{ PseudoVFNCVT_RM_F_X_W_M1, VFNCVT_F_X_W }, // 1800
|
|
{ PseudoVFNCVT_RM_F_X_W_M1_MASK, VFNCVT_F_X_W }, // 1801
|
|
{ PseudoVFNCVT_RM_F_X_W_M2, VFNCVT_F_X_W }, // 1802
|
|
{ PseudoVFNCVT_RM_F_X_W_M2_MASK, VFNCVT_F_X_W }, // 1803
|
|
{ PseudoVFNCVT_RM_F_X_W_M4, VFNCVT_F_X_W }, // 1804
|
|
{ PseudoVFNCVT_RM_F_X_W_M4_MASK, VFNCVT_F_X_W }, // 1805
|
|
{ PseudoVFNCVT_RM_F_X_W_MF2, VFNCVT_F_X_W }, // 1806
|
|
{ PseudoVFNCVT_RM_F_X_W_MF2_MASK, VFNCVT_F_X_W }, // 1807
|
|
{ PseudoVFNCVT_RM_F_X_W_MF4, VFNCVT_F_X_W }, // 1808
|
|
{ PseudoVFNCVT_RM_F_X_W_MF4_MASK, VFNCVT_F_X_W }, // 1809
|
|
{ PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W }, // 1810
|
|
{ PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W }, // 1811
|
|
{ PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W }, // 1812
|
|
{ PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W }, // 1813
|
|
{ PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W }, // 1814
|
|
{ PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W }, // 1815
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W }, // 1816
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W }, // 1817
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W }, // 1818
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W }, // 1819
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W }, // 1820
|
|
{ PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W }, // 1821
|
|
{ PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W }, // 1822
|
|
{ PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W }, // 1823
|
|
{ PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W }, // 1824
|
|
{ PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W }, // 1825
|
|
{ PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W }, // 1826
|
|
{ PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W }, // 1827
|
|
{ PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W }, // 1828
|
|
{ PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W }, // 1829
|
|
{ PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W }, // 1830
|
|
{ PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W }, // 1831
|
|
{ PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W }, // 1832
|
|
{ PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W }, // 1833
|
|
{ PseudoVFNCVT_ROD_F_F_W_M1, VFNCVT_ROD_F_F_W }, // 1834
|
|
{ PseudoVFNCVT_ROD_F_F_W_M1_MASK, VFNCVT_ROD_F_F_W }, // 1835
|
|
{ PseudoVFNCVT_ROD_F_F_W_M2, VFNCVT_ROD_F_F_W }, // 1836
|
|
{ PseudoVFNCVT_ROD_F_F_W_M2_MASK, VFNCVT_ROD_F_F_W }, // 1837
|
|
{ PseudoVFNCVT_ROD_F_F_W_M4, VFNCVT_ROD_F_F_W }, // 1838
|
|
{ PseudoVFNCVT_ROD_F_F_W_M4_MASK, VFNCVT_ROD_F_F_W }, // 1839
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF2, VFNCVT_ROD_F_F_W }, // 1840
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF2_MASK, VFNCVT_ROD_F_F_W }, // 1841
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF4, VFNCVT_ROD_F_F_W }, // 1842
|
|
{ PseudoVFNCVT_ROD_F_F_W_MF4_MASK, VFNCVT_ROD_F_F_W }, // 1843
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W }, // 1844
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W }, // 1845
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W }, // 1846
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W }, // 1847
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W }, // 1848
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W }, // 1849
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W }, // 1850
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W }, // 1851
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W }, // 1852
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W }, // 1853
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W }, // 1854
|
|
{ PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W }, // 1855
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W }, // 1856
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W }, // 1857
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W }, // 1858
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W }, // 1859
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W }, // 1860
|
|
{ PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W }, // 1861
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W }, // 1862
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W }, // 1863
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W }, // 1864
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W }, // 1865
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W }, // 1866
|
|
{ PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W }, // 1867
|
|
{ PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W }, // 1868
|
|
{ PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W }, // 1869
|
|
{ PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W }, // 1870
|
|
{ PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W }, // 1871
|
|
{ PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W }, // 1872
|
|
{ PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W }, // 1873
|
|
{ PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W }, // 1874
|
|
{ PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W }, // 1875
|
|
{ PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W }, // 1876
|
|
{ PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W }, // 1877
|
|
{ PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W }, // 1878
|
|
{ PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W }, // 1879
|
|
{ PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W }, // 1880
|
|
{ PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W }, // 1881
|
|
{ PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W }, // 1882
|
|
{ PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W }, // 1883
|
|
{ PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W }, // 1884
|
|
{ PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W }, // 1885
|
|
{ PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W }, // 1886
|
|
{ PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W }, // 1887
|
|
{ PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W }, // 1888
|
|
{ PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W }, // 1889
|
|
{ PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W }, // 1890
|
|
{ PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W }, // 1891
|
|
{ PseudoVFNMACC_VFPR16_M1, VFNMACC_VF }, // 1892
|
|
{ PseudoVFNMACC_VFPR16_M1_MASK, VFNMACC_VF }, // 1893
|
|
{ PseudoVFNMACC_VFPR16_M2, VFNMACC_VF }, // 1894
|
|
{ PseudoVFNMACC_VFPR16_M2_MASK, VFNMACC_VF }, // 1895
|
|
{ PseudoVFNMACC_VFPR16_M4, VFNMACC_VF }, // 1896
|
|
{ PseudoVFNMACC_VFPR16_M4_MASK, VFNMACC_VF }, // 1897
|
|
{ PseudoVFNMACC_VFPR16_M8, VFNMACC_VF }, // 1898
|
|
{ PseudoVFNMACC_VFPR16_M8_MASK, VFNMACC_VF }, // 1899
|
|
{ PseudoVFNMACC_VFPR16_MF2, VFNMACC_VF }, // 1900
|
|
{ PseudoVFNMACC_VFPR16_MF2_MASK, VFNMACC_VF }, // 1901
|
|
{ PseudoVFNMACC_VFPR16_MF4, VFNMACC_VF }, // 1902
|
|
{ PseudoVFNMACC_VFPR16_MF4_MASK, VFNMACC_VF }, // 1903
|
|
{ PseudoVFNMACC_VFPR32_M1, VFNMACC_VF }, // 1904
|
|
{ PseudoVFNMACC_VFPR32_M1_MASK, VFNMACC_VF }, // 1905
|
|
{ PseudoVFNMACC_VFPR32_M2, VFNMACC_VF }, // 1906
|
|
{ PseudoVFNMACC_VFPR32_M2_MASK, VFNMACC_VF }, // 1907
|
|
{ PseudoVFNMACC_VFPR32_M4, VFNMACC_VF }, // 1908
|
|
{ PseudoVFNMACC_VFPR32_M4_MASK, VFNMACC_VF }, // 1909
|
|
{ PseudoVFNMACC_VFPR32_M8, VFNMACC_VF }, // 1910
|
|
{ PseudoVFNMACC_VFPR32_M8_MASK, VFNMACC_VF }, // 1911
|
|
{ PseudoVFNMACC_VFPR32_MF2, VFNMACC_VF }, // 1912
|
|
{ PseudoVFNMACC_VFPR32_MF2_MASK, VFNMACC_VF }, // 1913
|
|
{ PseudoVFNMACC_VFPR64_M1, VFNMACC_VF }, // 1914
|
|
{ PseudoVFNMACC_VFPR64_M1_MASK, VFNMACC_VF }, // 1915
|
|
{ PseudoVFNMACC_VFPR64_M2, VFNMACC_VF }, // 1916
|
|
{ PseudoVFNMACC_VFPR64_M2_MASK, VFNMACC_VF }, // 1917
|
|
{ PseudoVFNMACC_VFPR64_M4, VFNMACC_VF }, // 1918
|
|
{ PseudoVFNMACC_VFPR64_M4_MASK, VFNMACC_VF }, // 1919
|
|
{ PseudoVFNMACC_VFPR64_M8, VFNMACC_VF }, // 1920
|
|
{ PseudoVFNMACC_VFPR64_M8_MASK, VFNMACC_VF }, // 1921
|
|
{ PseudoVFNMACC_VV_M1, VFNMACC_VV }, // 1922
|
|
{ PseudoVFNMACC_VV_M1_MASK, VFNMACC_VV }, // 1923
|
|
{ PseudoVFNMACC_VV_M2, VFNMACC_VV }, // 1924
|
|
{ PseudoVFNMACC_VV_M2_MASK, VFNMACC_VV }, // 1925
|
|
{ PseudoVFNMACC_VV_M4, VFNMACC_VV }, // 1926
|
|
{ PseudoVFNMACC_VV_M4_MASK, VFNMACC_VV }, // 1927
|
|
{ PseudoVFNMACC_VV_M8, VFNMACC_VV }, // 1928
|
|
{ PseudoVFNMACC_VV_M8_MASK, VFNMACC_VV }, // 1929
|
|
{ PseudoVFNMACC_VV_MF2, VFNMACC_VV }, // 1930
|
|
{ PseudoVFNMACC_VV_MF2_MASK, VFNMACC_VV }, // 1931
|
|
{ PseudoVFNMACC_VV_MF4, VFNMACC_VV }, // 1932
|
|
{ PseudoVFNMACC_VV_MF4_MASK, VFNMACC_VV }, // 1933
|
|
{ PseudoVFNMADD_VFPR16_M1, VFNMADD_VF }, // 1934
|
|
{ PseudoVFNMADD_VFPR16_M1_MASK, VFNMADD_VF }, // 1935
|
|
{ PseudoVFNMADD_VFPR16_M2, VFNMADD_VF }, // 1936
|
|
{ PseudoVFNMADD_VFPR16_M2_MASK, VFNMADD_VF }, // 1937
|
|
{ PseudoVFNMADD_VFPR16_M4, VFNMADD_VF }, // 1938
|
|
{ PseudoVFNMADD_VFPR16_M4_MASK, VFNMADD_VF }, // 1939
|
|
{ PseudoVFNMADD_VFPR16_M8, VFNMADD_VF }, // 1940
|
|
{ PseudoVFNMADD_VFPR16_M8_MASK, VFNMADD_VF }, // 1941
|
|
{ PseudoVFNMADD_VFPR16_MF2, VFNMADD_VF }, // 1942
|
|
{ PseudoVFNMADD_VFPR16_MF2_MASK, VFNMADD_VF }, // 1943
|
|
{ PseudoVFNMADD_VFPR16_MF4, VFNMADD_VF }, // 1944
|
|
{ PseudoVFNMADD_VFPR16_MF4_MASK, VFNMADD_VF }, // 1945
|
|
{ PseudoVFNMADD_VFPR32_M1, VFNMADD_VF }, // 1946
|
|
{ PseudoVFNMADD_VFPR32_M1_MASK, VFNMADD_VF }, // 1947
|
|
{ PseudoVFNMADD_VFPR32_M2, VFNMADD_VF }, // 1948
|
|
{ PseudoVFNMADD_VFPR32_M2_MASK, VFNMADD_VF }, // 1949
|
|
{ PseudoVFNMADD_VFPR32_M4, VFNMADD_VF }, // 1950
|
|
{ PseudoVFNMADD_VFPR32_M4_MASK, VFNMADD_VF }, // 1951
|
|
{ PseudoVFNMADD_VFPR32_M8, VFNMADD_VF }, // 1952
|
|
{ PseudoVFNMADD_VFPR32_M8_MASK, VFNMADD_VF }, // 1953
|
|
{ PseudoVFNMADD_VFPR32_MF2, VFNMADD_VF }, // 1954
|
|
{ PseudoVFNMADD_VFPR32_MF2_MASK, VFNMADD_VF }, // 1955
|
|
{ PseudoVFNMADD_VFPR64_M1, VFNMADD_VF }, // 1956
|
|
{ PseudoVFNMADD_VFPR64_M1_MASK, VFNMADD_VF }, // 1957
|
|
{ PseudoVFNMADD_VFPR64_M2, VFNMADD_VF }, // 1958
|
|
{ PseudoVFNMADD_VFPR64_M2_MASK, VFNMADD_VF }, // 1959
|
|
{ PseudoVFNMADD_VFPR64_M4, VFNMADD_VF }, // 1960
|
|
{ PseudoVFNMADD_VFPR64_M4_MASK, VFNMADD_VF }, // 1961
|
|
{ PseudoVFNMADD_VFPR64_M8, VFNMADD_VF }, // 1962
|
|
{ PseudoVFNMADD_VFPR64_M8_MASK, VFNMADD_VF }, // 1963
|
|
{ PseudoVFNMADD_VV_M1, VFNMADD_VV }, // 1964
|
|
{ PseudoVFNMADD_VV_M1_MASK, VFNMADD_VV }, // 1965
|
|
{ PseudoVFNMADD_VV_M2, VFNMADD_VV }, // 1966
|
|
{ PseudoVFNMADD_VV_M2_MASK, VFNMADD_VV }, // 1967
|
|
{ PseudoVFNMADD_VV_M4, VFNMADD_VV }, // 1968
|
|
{ PseudoVFNMADD_VV_M4_MASK, VFNMADD_VV }, // 1969
|
|
{ PseudoVFNMADD_VV_M8, VFNMADD_VV }, // 1970
|
|
{ PseudoVFNMADD_VV_M8_MASK, VFNMADD_VV }, // 1971
|
|
{ PseudoVFNMADD_VV_MF2, VFNMADD_VV }, // 1972
|
|
{ PseudoVFNMADD_VV_MF2_MASK, VFNMADD_VV }, // 1973
|
|
{ PseudoVFNMADD_VV_MF4, VFNMADD_VV }, // 1974
|
|
{ PseudoVFNMADD_VV_MF4_MASK, VFNMADD_VV }, // 1975
|
|
{ PseudoVFNMSAC_VFPR16_M1, VFNMSAC_VF }, // 1976
|
|
{ PseudoVFNMSAC_VFPR16_M1_MASK, VFNMSAC_VF }, // 1977
|
|
{ PseudoVFNMSAC_VFPR16_M2, VFNMSAC_VF }, // 1978
|
|
{ PseudoVFNMSAC_VFPR16_M2_MASK, VFNMSAC_VF }, // 1979
|
|
{ PseudoVFNMSAC_VFPR16_M4, VFNMSAC_VF }, // 1980
|
|
{ PseudoVFNMSAC_VFPR16_M4_MASK, VFNMSAC_VF }, // 1981
|
|
{ PseudoVFNMSAC_VFPR16_M8, VFNMSAC_VF }, // 1982
|
|
{ PseudoVFNMSAC_VFPR16_M8_MASK, VFNMSAC_VF }, // 1983
|
|
{ PseudoVFNMSAC_VFPR16_MF2, VFNMSAC_VF }, // 1984
|
|
{ PseudoVFNMSAC_VFPR16_MF2_MASK, VFNMSAC_VF }, // 1985
|
|
{ PseudoVFNMSAC_VFPR16_MF4, VFNMSAC_VF }, // 1986
|
|
{ PseudoVFNMSAC_VFPR16_MF4_MASK, VFNMSAC_VF }, // 1987
|
|
{ PseudoVFNMSAC_VFPR32_M1, VFNMSAC_VF }, // 1988
|
|
{ PseudoVFNMSAC_VFPR32_M1_MASK, VFNMSAC_VF }, // 1989
|
|
{ PseudoVFNMSAC_VFPR32_M2, VFNMSAC_VF }, // 1990
|
|
{ PseudoVFNMSAC_VFPR32_M2_MASK, VFNMSAC_VF }, // 1991
|
|
{ PseudoVFNMSAC_VFPR32_M4, VFNMSAC_VF }, // 1992
|
|
{ PseudoVFNMSAC_VFPR32_M4_MASK, VFNMSAC_VF }, // 1993
|
|
{ PseudoVFNMSAC_VFPR32_M8, VFNMSAC_VF }, // 1994
|
|
{ PseudoVFNMSAC_VFPR32_M8_MASK, VFNMSAC_VF }, // 1995
|
|
{ PseudoVFNMSAC_VFPR32_MF2, VFNMSAC_VF }, // 1996
|
|
{ PseudoVFNMSAC_VFPR32_MF2_MASK, VFNMSAC_VF }, // 1997
|
|
{ PseudoVFNMSAC_VFPR64_M1, VFNMSAC_VF }, // 1998
|
|
{ PseudoVFNMSAC_VFPR64_M1_MASK, VFNMSAC_VF }, // 1999
|
|
{ PseudoVFNMSAC_VFPR64_M2, VFNMSAC_VF }, // 2000
|
|
{ PseudoVFNMSAC_VFPR64_M2_MASK, VFNMSAC_VF }, // 2001
|
|
{ PseudoVFNMSAC_VFPR64_M4, VFNMSAC_VF }, // 2002
|
|
{ PseudoVFNMSAC_VFPR64_M4_MASK, VFNMSAC_VF }, // 2003
|
|
{ PseudoVFNMSAC_VFPR64_M8, VFNMSAC_VF }, // 2004
|
|
{ PseudoVFNMSAC_VFPR64_M8_MASK, VFNMSAC_VF }, // 2005
|
|
{ PseudoVFNMSAC_VV_M1, VFNMSAC_VV }, // 2006
|
|
{ PseudoVFNMSAC_VV_M1_MASK, VFNMSAC_VV }, // 2007
|
|
{ PseudoVFNMSAC_VV_M2, VFNMSAC_VV }, // 2008
|
|
{ PseudoVFNMSAC_VV_M2_MASK, VFNMSAC_VV }, // 2009
|
|
{ PseudoVFNMSAC_VV_M4, VFNMSAC_VV }, // 2010
|
|
{ PseudoVFNMSAC_VV_M4_MASK, VFNMSAC_VV }, // 2011
|
|
{ PseudoVFNMSAC_VV_M8, VFNMSAC_VV }, // 2012
|
|
{ PseudoVFNMSAC_VV_M8_MASK, VFNMSAC_VV }, // 2013
|
|
{ PseudoVFNMSAC_VV_MF2, VFNMSAC_VV }, // 2014
|
|
{ PseudoVFNMSAC_VV_MF2_MASK, VFNMSAC_VV }, // 2015
|
|
{ PseudoVFNMSAC_VV_MF4, VFNMSAC_VV }, // 2016
|
|
{ PseudoVFNMSAC_VV_MF4_MASK, VFNMSAC_VV }, // 2017
|
|
{ PseudoVFNMSUB_VFPR16_M1, VFNMSUB_VF }, // 2018
|
|
{ PseudoVFNMSUB_VFPR16_M1_MASK, VFNMSUB_VF }, // 2019
|
|
{ PseudoVFNMSUB_VFPR16_M2, VFNMSUB_VF }, // 2020
|
|
{ PseudoVFNMSUB_VFPR16_M2_MASK, VFNMSUB_VF }, // 2021
|
|
{ PseudoVFNMSUB_VFPR16_M4, VFNMSUB_VF }, // 2022
|
|
{ PseudoVFNMSUB_VFPR16_M4_MASK, VFNMSUB_VF }, // 2023
|
|
{ PseudoVFNMSUB_VFPR16_M8, VFNMSUB_VF }, // 2024
|
|
{ PseudoVFNMSUB_VFPR16_M8_MASK, VFNMSUB_VF }, // 2025
|
|
{ PseudoVFNMSUB_VFPR16_MF2, VFNMSUB_VF }, // 2026
|
|
{ PseudoVFNMSUB_VFPR16_MF2_MASK, VFNMSUB_VF }, // 2027
|
|
{ PseudoVFNMSUB_VFPR16_MF4, VFNMSUB_VF }, // 2028
|
|
{ PseudoVFNMSUB_VFPR16_MF4_MASK, VFNMSUB_VF }, // 2029
|
|
{ PseudoVFNMSUB_VFPR32_M1, VFNMSUB_VF }, // 2030
|
|
{ PseudoVFNMSUB_VFPR32_M1_MASK, VFNMSUB_VF }, // 2031
|
|
{ PseudoVFNMSUB_VFPR32_M2, VFNMSUB_VF }, // 2032
|
|
{ PseudoVFNMSUB_VFPR32_M2_MASK, VFNMSUB_VF }, // 2033
|
|
{ PseudoVFNMSUB_VFPR32_M4, VFNMSUB_VF }, // 2034
|
|
{ PseudoVFNMSUB_VFPR32_M4_MASK, VFNMSUB_VF }, // 2035
|
|
{ PseudoVFNMSUB_VFPR32_M8, VFNMSUB_VF }, // 2036
|
|
{ PseudoVFNMSUB_VFPR32_M8_MASK, VFNMSUB_VF }, // 2037
|
|
{ PseudoVFNMSUB_VFPR32_MF2, VFNMSUB_VF }, // 2038
|
|
{ PseudoVFNMSUB_VFPR32_MF2_MASK, VFNMSUB_VF }, // 2039
|
|
{ PseudoVFNMSUB_VFPR64_M1, VFNMSUB_VF }, // 2040
|
|
{ PseudoVFNMSUB_VFPR64_M1_MASK, VFNMSUB_VF }, // 2041
|
|
{ PseudoVFNMSUB_VFPR64_M2, VFNMSUB_VF }, // 2042
|
|
{ PseudoVFNMSUB_VFPR64_M2_MASK, VFNMSUB_VF }, // 2043
|
|
{ PseudoVFNMSUB_VFPR64_M4, VFNMSUB_VF }, // 2044
|
|
{ PseudoVFNMSUB_VFPR64_M4_MASK, VFNMSUB_VF }, // 2045
|
|
{ PseudoVFNMSUB_VFPR64_M8, VFNMSUB_VF }, // 2046
|
|
{ PseudoVFNMSUB_VFPR64_M8_MASK, VFNMSUB_VF }, // 2047
|
|
{ PseudoVFNMSUB_VV_M1, VFNMSUB_VV }, // 2048
|
|
{ PseudoVFNMSUB_VV_M1_MASK, VFNMSUB_VV }, // 2049
|
|
{ PseudoVFNMSUB_VV_M2, VFNMSUB_VV }, // 2050
|
|
{ PseudoVFNMSUB_VV_M2_MASK, VFNMSUB_VV }, // 2051
|
|
{ PseudoVFNMSUB_VV_M4, VFNMSUB_VV }, // 2052
|
|
{ PseudoVFNMSUB_VV_M4_MASK, VFNMSUB_VV }, // 2053
|
|
{ PseudoVFNMSUB_VV_M8, VFNMSUB_VV }, // 2054
|
|
{ PseudoVFNMSUB_VV_M8_MASK, VFNMSUB_VV }, // 2055
|
|
{ PseudoVFNMSUB_VV_MF2, VFNMSUB_VV }, // 2056
|
|
{ PseudoVFNMSUB_VV_MF2_MASK, VFNMSUB_VV }, // 2057
|
|
{ PseudoVFNMSUB_VV_MF4, VFNMSUB_VV }, // 2058
|
|
{ PseudoVFNMSUB_VV_MF4_MASK, VFNMSUB_VV }, // 2059
|
|
{ PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF }, // 2060
|
|
{ PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF }, // 2061
|
|
{ PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF }, // 2062
|
|
{ PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF }, // 2063
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF }, // 2064
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF }, // 2065
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF }, // 2066
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF }, // 2067
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF }, // 2068
|
|
{ PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF }, // 2069
|
|
{ PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF }, // 2070
|
|
{ PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF }, // 2071
|
|
{ PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF }, // 2072
|
|
{ PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF }, // 2073
|
|
{ PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF }, // 2074
|
|
{ PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF }, // 2075
|
|
{ PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF }, // 2076
|
|
{ PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF }, // 2077
|
|
{ PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF }, // 2078
|
|
{ PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF }, // 2079
|
|
{ PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF }, // 2080
|
|
{ PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF }, // 2081
|
|
{ PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF }, // 2082
|
|
{ PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF }, // 2083
|
|
{ PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF }, // 2084
|
|
{ PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF }, // 2085
|
|
{ PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF }, // 2086
|
|
{ PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF }, // 2087
|
|
{ PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF }, // 2088
|
|
{ PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF }, // 2089
|
|
{ PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF }, // 2090
|
|
{ PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF }, // 2091
|
|
{ PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF }, // 2092
|
|
{ PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF }, // 2093
|
|
{ PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF }, // 2094
|
|
{ PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF }, // 2095
|
|
{ PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF }, // 2096
|
|
{ PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF }, // 2097
|
|
{ PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF }, // 2098
|
|
{ PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF }, // 2099
|
|
{ PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF }, // 2100
|
|
{ PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF }, // 2101
|
|
{ PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF }, // 2102
|
|
{ PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF }, // 2103
|
|
{ PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF }, // 2104
|
|
{ PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF }, // 2105
|
|
{ PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF }, // 2106
|
|
{ PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF }, // 2107
|
|
{ PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF }, // 2108
|
|
{ PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF }, // 2109
|
|
{ PseudoVFREC7_V_M1, VFREC7_V }, // 2110
|
|
{ PseudoVFREC7_V_M1_MASK, VFREC7_V }, // 2111
|
|
{ PseudoVFREC7_V_M2, VFREC7_V }, // 2112
|
|
{ PseudoVFREC7_V_M2_MASK, VFREC7_V }, // 2113
|
|
{ PseudoVFREC7_V_M4, VFREC7_V }, // 2114
|
|
{ PseudoVFREC7_V_M4_MASK, VFREC7_V }, // 2115
|
|
{ PseudoVFREC7_V_M8, VFREC7_V }, // 2116
|
|
{ PseudoVFREC7_V_M8_MASK, VFREC7_V }, // 2117
|
|
{ PseudoVFREC7_V_MF2, VFREC7_V }, // 2118
|
|
{ PseudoVFREC7_V_MF2_MASK, VFREC7_V }, // 2119
|
|
{ PseudoVFREC7_V_MF4, VFREC7_V }, // 2120
|
|
{ PseudoVFREC7_V_MF4_MASK, VFREC7_V }, // 2121
|
|
{ PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS }, // 2122
|
|
{ PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS }, // 2123
|
|
{ PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS }, // 2124
|
|
{ PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS }, // 2125
|
|
{ PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS }, // 2126
|
|
{ PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS }, // 2127
|
|
{ PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS }, // 2128
|
|
{ PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS }, // 2129
|
|
{ PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS }, // 2130
|
|
{ PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS }, // 2131
|
|
{ PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS }, // 2132
|
|
{ PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS }, // 2133
|
|
{ PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS }, // 2134
|
|
{ PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS }, // 2135
|
|
{ PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS }, // 2136
|
|
{ PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS }, // 2137
|
|
{ PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS }, // 2138
|
|
{ PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS }, // 2139
|
|
{ PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS }, // 2140
|
|
{ PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS }, // 2141
|
|
{ PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS }, // 2142
|
|
{ PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS }, // 2143
|
|
{ PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS }, // 2144
|
|
{ PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS }, // 2145
|
|
{ PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS }, // 2146
|
|
{ PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS }, // 2147
|
|
{ PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS }, // 2148
|
|
{ PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS }, // 2149
|
|
{ PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS }, // 2150
|
|
{ PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS }, // 2151
|
|
{ PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS }, // 2152
|
|
{ PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS }, // 2153
|
|
{ PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS }, // 2154
|
|
{ PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS }, // 2155
|
|
{ PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS }, // 2156
|
|
{ PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS }, // 2157
|
|
{ PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS }, // 2158
|
|
{ PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS }, // 2159
|
|
{ PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS }, // 2160
|
|
{ PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS }, // 2161
|
|
{ PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS }, // 2162
|
|
{ PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS }, // 2163
|
|
{ PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS }, // 2164
|
|
{ PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS }, // 2165
|
|
{ PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS }, // 2166
|
|
{ PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS }, // 2167
|
|
{ PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS }, // 2168
|
|
{ PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS }, // 2169
|
|
{ PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS }, // 2170
|
|
{ PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS }, // 2171
|
|
{ PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS }, // 2172
|
|
{ PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS }, // 2173
|
|
{ PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS }, // 2174
|
|
{ PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS }, // 2175
|
|
{ PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS }, // 2176
|
|
{ PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS }, // 2177
|
|
{ PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS }, // 2178
|
|
{ PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS }, // 2179
|
|
{ PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS }, // 2180
|
|
{ PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS }, // 2181
|
|
{ PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS }, // 2182
|
|
{ PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS }, // 2183
|
|
{ PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS }, // 2184
|
|
{ PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS }, // 2185
|
|
{ PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS }, // 2186
|
|
{ PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS }, // 2187
|
|
{ PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS }, // 2188
|
|
{ PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS }, // 2189
|
|
{ PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS }, // 2190
|
|
{ PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS }, // 2191
|
|
{ PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS }, // 2192
|
|
{ PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS }, // 2193
|
|
{ PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS }, // 2194
|
|
{ PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS }, // 2195
|
|
{ PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS }, // 2196
|
|
{ PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS }, // 2197
|
|
{ PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS }, // 2198
|
|
{ PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS }, // 2199
|
|
{ PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS }, // 2200
|
|
{ PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS }, // 2201
|
|
{ PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS }, // 2202
|
|
{ PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS }, // 2203
|
|
{ PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS }, // 2204
|
|
{ PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS }, // 2205
|
|
{ PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS }, // 2206
|
|
{ PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS }, // 2207
|
|
{ PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS }, // 2208
|
|
{ PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS }, // 2209
|
|
{ PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS }, // 2210
|
|
{ PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS }, // 2211
|
|
{ PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS }, // 2212
|
|
{ PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS }, // 2213
|
|
{ PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS }, // 2214
|
|
{ PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS }, // 2215
|
|
{ PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS }, // 2216
|
|
{ PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS }, // 2217
|
|
{ PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS }, // 2218
|
|
{ PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS }, // 2219
|
|
{ PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS }, // 2220
|
|
{ PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS }, // 2221
|
|
{ PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS }, // 2222
|
|
{ PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS }, // 2223
|
|
{ PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS }, // 2224
|
|
{ PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS }, // 2225
|
|
{ PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS }, // 2226
|
|
{ PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS }, // 2227
|
|
{ PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS }, // 2228
|
|
{ PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS }, // 2229
|
|
{ PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS }, // 2230
|
|
{ PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS }, // 2231
|
|
{ PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS }, // 2232
|
|
{ PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS }, // 2233
|
|
{ PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS }, // 2234
|
|
{ PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS }, // 2235
|
|
{ PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS }, // 2236
|
|
{ PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS }, // 2237
|
|
{ PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS }, // 2238
|
|
{ PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS }, // 2239
|
|
{ PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS }, // 2240
|
|
{ PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS }, // 2241
|
|
{ PseudoVFRSQRT7_V_M1, VFRSQRT7_V }, // 2242
|
|
{ PseudoVFRSQRT7_V_M1_MASK, VFRSQRT7_V }, // 2243
|
|
{ PseudoVFRSQRT7_V_M2, VFRSQRT7_V }, // 2244
|
|
{ PseudoVFRSQRT7_V_M2_MASK, VFRSQRT7_V }, // 2245
|
|
{ PseudoVFRSQRT7_V_M4, VFRSQRT7_V }, // 2246
|
|
{ PseudoVFRSQRT7_V_M4_MASK, VFRSQRT7_V }, // 2247
|
|
{ PseudoVFRSQRT7_V_M8, VFRSQRT7_V }, // 2248
|
|
{ PseudoVFRSQRT7_V_M8_MASK, VFRSQRT7_V }, // 2249
|
|
{ PseudoVFRSQRT7_V_MF2, VFRSQRT7_V }, // 2250
|
|
{ PseudoVFRSQRT7_V_MF2_MASK, VFRSQRT7_V }, // 2251
|
|
{ PseudoVFRSQRT7_V_MF4, VFRSQRT7_V }, // 2252
|
|
{ PseudoVFRSQRT7_V_MF4_MASK, VFRSQRT7_V }, // 2253
|
|
{ PseudoVFRSUB_VFPR16_M1, VFRSUB_VF }, // 2254
|
|
{ PseudoVFRSUB_VFPR16_M1_MASK, VFRSUB_VF }, // 2255
|
|
{ PseudoVFRSUB_VFPR16_M2, VFRSUB_VF }, // 2256
|
|
{ PseudoVFRSUB_VFPR16_M2_MASK, VFRSUB_VF }, // 2257
|
|
{ PseudoVFRSUB_VFPR16_M4, VFRSUB_VF }, // 2258
|
|
{ PseudoVFRSUB_VFPR16_M4_MASK, VFRSUB_VF }, // 2259
|
|
{ PseudoVFRSUB_VFPR16_M8, VFRSUB_VF }, // 2260
|
|
{ PseudoVFRSUB_VFPR16_M8_MASK, VFRSUB_VF }, // 2261
|
|
{ PseudoVFRSUB_VFPR16_MF2, VFRSUB_VF }, // 2262
|
|
{ PseudoVFRSUB_VFPR16_MF2_MASK, VFRSUB_VF }, // 2263
|
|
{ PseudoVFRSUB_VFPR16_MF4, VFRSUB_VF }, // 2264
|
|
{ PseudoVFRSUB_VFPR16_MF4_MASK, VFRSUB_VF }, // 2265
|
|
{ PseudoVFRSUB_VFPR32_M1, VFRSUB_VF }, // 2266
|
|
{ PseudoVFRSUB_VFPR32_M1_MASK, VFRSUB_VF }, // 2267
|
|
{ PseudoVFRSUB_VFPR32_M2, VFRSUB_VF }, // 2268
|
|
{ PseudoVFRSUB_VFPR32_M2_MASK, VFRSUB_VF }, // 2269
|
|
{ PseudoVFRSUB_VFPR32_M4, VFRSUB_VF }, // 2270
|
|
{ PseudoVFRSUB_VFPR32_M4_MASK, VFRSUB_VF }, // 2271
|
|
{ PseudoVFRSUB_VFPR32_M8, VFRSUB_VF }, // 2272
|
|
{ PseudoVFRSUB_VFPR32_M8_MASK, VFRSUB_VF }, // 2273
|
|
{ PseudoVFRSUB_VFPR32_MF2, VFRSUB_VF }, // 2274
|
|
{ PseudoVFRSUB_VFPR32_MF2_MASK, VFRSUB_VF }, // 2275
|
|
{ PseudoVFRSUB_VFPR64_M1, VFRSUB_VF }, // 2276
|
|
{ PseudoVFRSUB_VFPR64_M1_MASK, VFRSUB_VF }, // 2277
|
|
{ PseudoVFRSUB_VFPR64_M2, VFRSUB_VF }, // 2278
|
|
{ PseudoVFRSUB_VFPR64_M2_MASK, VFRSUB_VF }, // 2279
|
|
{ PseudoVFRSUB_VFPR64_M4, VFRSUB_VF }, // 2280
|
|
{ PseudoVFRSUB_VFPR64_M4_MASK, VFRSUB_VF }, // 2281
|
|
{ PseudoVFRSUB_VFPR64_M8, VFRSUB_VF }, // 2282
|
|
{ PseudoVFRSUB_VFPR64_M8_MASK, VFRSUB_VF }, // 2283
|
|
{ PseudoVFSGNJN_VFPR16_M1, VFSGNJN_VF }, // 2284
|
|
{ PseudoVFSGNJN_VFPR16_M1_MASK, VFSGNJN_VF }, // 2285
|
|
{ PseudoVFSGNJN_VFPR16_M2, VFSGNJN_VF }, // 2286
|
|
{ PseudoVFSGNJN_VFPR16_M2_MASK, VFSGNJN_VF }, // 2287
|
|
{ PseudoVFSGNJN_VFPR16_M4, VFSGNJN_VF }, // 2288
|
|
{ PseudoVFSGNJN_VFPR16_M4_MASK, VFSGNJN_VF }, // 2289
|
|
{ PseudoVFSGNJN_VFPR16_M8, VFSGNJN_VF }, // 2290
|
|
{ PseudoVFSGNJN_VFPR16_M8_MASK, VFSGNJN_VF }, // 2291
|
|
{ PseudoVFSGNJN_VFPR16_MF2, VFSGNJN_VF }, // 2292
|
|
{ PseudoVFSGNJN_VFPR16_MF2_MASK, VFSGNJN_VF }, // 2293
|
|
{ PseudoVFSGNJN_VFPR16_MF4, VFSGNJN_VF }, // 2294
|
|
{ PseudoVFSGNJN_VFPR16_MF4_MASK, VFSGNJN_VF }, // 2295
|
|
{ PseudoVFSGNJN_VFPR32_M1, VFSGNJN_VF }, // 2296
|
|
{ PseudoVFSGNJN_VFPR32_M1_MASK, VFSGNJN_VF }, // 2297
|
|
{ PseudoVFSGNJN_VFPR32_M2, VFSGNJN_VF }, // 2298
|
|
{ PseudoVFSGNJN_VFPR32_M2_MASK, VFSGNJN_VF }, // 2299
|
|
{ PseudoVFSGNJN_VFPR32_M4, VFSGNJN_VF }, // 2300
|
|
{ PseudoVFSGNJN_VFPR32_M4_MASK, VFSGNJN_VF }, // 2301
|
|
{ PseudoVFSGNJN_VFPR32_M8, VFSGNJN_VF }, // 2302
|
|
{ PseudoVFSGNJN_VFPR32_M8_MASK, VFSGNJN_VF }, // 2303
|
|
{ PseudoVFSGNJN_VFPR32_MF2, VFSGNJN_VF }, // 2304
|
|
{ PseudoVFSGNJN_VFPR32_MF2_MASK, VFSGNJN_VF }, // 2305
|
|
{ PseudoVFSGNJN_VFPR64_M1, VFSGNJN_VF }, // 2306
|
|
{ PseudoVFSGNJN_VFPR64_M1_MASK, VFSGNJN_VF }, // 2307
|
|
{ PseudoVFSGNJN_VFPR64_M2, VFSGNJN_VF }, // 2308
|
|
{ PseudoVFSGNJN_VFPR64_M2_MASK, VFSGNJN_VF }, // 2309
|
|
{ PseudoVFSGNJN_VFPR64_M4, VFSGNJN_VF }, // 2310
|
|
{ PseudoVFSGNJN_VFPR64_M4_MASK, VFSGNJN_VF }, // 2311
|
|
{ PseudoVFSGNJN_VFPR64_M8, VFSGNJN_VF }, // 2312
|
|
{ PseudoVFSGNJN_VFPR64_M8_MASK, VFSGNJN_VF }, // 2313
|
|
{ PseudoVFSGNJN_VV_M1, VFSGNJN_VV }, // 2314
|
|
{ PseudoVFSGNJN_VV_M1_MASK, VFSGNJN_VV }, // 2315
|
|
{ PseudoVFSGNJN_VV_M2, VFSGNJN_VV }, // 2316
|
|
{ PseudoVFSGNJN_VV_M2_MASK, VFSGNJN_VV }, // 2317
|
|
{ PseudoVFSGNJN_VV_M4, VFSGNJN_VV }, // 2318
|
|
{ PseudoVFSGNJN_VV_M4_MASK, VFSGNJN_VV }, // 2319
|
|
{ PseudoVFSGNJN_VV_M8, VFSGNJN_VV }, // 2320
|
|
{ PseudoVFSGNJN_VV_M8_MASK, VFSGNJN_VV }, // 2321
|
|
{ PseudoVFSGNJN_VV_MF2, VFSGNJN_VV }, // 2322
|
|
{ PseudoVFSGNJN_VV_MF2_MASK, VFSGNJN_VV }, // 2323
|
|
{ PseudoVFSGNJN_VV_MF4, VFSGNJN_VV }, // 2324
|
|
{ PseudoVFSGNJN_VV_MF4_MASK, VFSGNJN_VV }, // 2325
|
|
{ PseudoVFSGNJX_VFPR16_M1, VFSGNJX_VF }, // 2326
|
|
{ PseudoVFSGNJX_VFPR16_M1_MASK, VFSGNJX_VF }, // 2327
|
|
{ PseudoVFSGNJX_VFPR16_M2, VFSGNJX_VF }, // 2328
|
|
{ PseudoVFSGNJX_VFPR16_M2_MASK, VFSGNJX_VF }, // 2329
|
|
{ PseudoVFSGNJX_VFPR16_M4, VFSGNJX_VF }, // 2330
|
|
{ PseudoVFSGNJX_VFPR16_M4_MASK, VFSGNJX_VF }, // 2331
|
|
{ PseudoVFSGNJX_VFPR16_M8, VFSGNJX_VF }, // 2332
|
|
{ PseudoVFSGNJX_VFPR16_M8_MASK, VFSGNJX_VF }, // 2333
|
|
{ PseudoVFSGNJX_VFPR16_MF2, VFSGNJX_VF }, // 2334
|
|
{ PseudoVFSGNJX_VFPR16_MF2_MASK, VFSGNJX_VF }, // 2335
|
|
{ PseudoVFSGNJX_VFPR16_MF4, VFSGNJX_VF }, // 2336
|
|
{ PseudoVFSGNJX_VFPR16_MF4_MASK, VFSGNJX_VF }, // 2337
|
|
{ PseudoVFSGNJX_VFPR32_M1, VFSGNJX_VF }, // 2338
|
|
{ PseudoVFSGNJX_VFPR32_M1_MASK, VFSGNJX_VF }, // 2339
|
|
{ PseudoVFSGNJX_VFPR32_M2, VFSGNJX_VF }, // 2340
|
|
{ PseudoVFSGNJX_VFPR32_M2_MASK, VFSGNJX_VF }, // 2341
|
|
{ PseudoVFSGNJX_VFPR32_M4, VFSGNJX_VF }, // 2342
|
|
{ PseudoVFSGNJX_VFPR32_M4_MASK, VFSGNJX_VF }, // 2343
|
|
{ PseudoVFSGNJX_VFPR32_M8, VFSGNJX_VF }, // 2344
|
|
{ PseudoVFSGNJX_VFPR32_M8_MASK, VFSGNJX_VF }, // 2345
|
|
{ PseudoVFSGNJX_VFPR32_MF2, VFSGNJX_VF }, // 2346
|
|
{ PseudoVFSGNJX_VFPR32_MF2_MASK, VFSGNJX_VF }, // 2347
|
|
{ PseudoVFSGNJX_VFPR64_M1, VFSGNJX_VF }, // 2348
|
|
{ PseudoVFSGNJX_VFPR64_M1_MASK, VFSGNJX_VF }, // 2349
|
|
{ PseudoVFSGNJX_VFPR64_M2, VFSGNJX_VF }, // 2350
|
|
{ PseudoVFSGNJX_VFPR64_M2_MASK, VFSGNJX_VF }, // 2351
|
|
{ PseudoVFSGNJX_VFPR64_M4, VFSGNJX_VF }, // 2352
|
|
{ PseudoVFSGNJX_VFPR64_M4_MASK, VFSGNJX_VF }, // 2353
|
|
{ PseudoVFSGNJX_VFPR64_M8, VFSGNJX_VF }, // 2354
|
|
{ PseudoVFSGNJX_VFPR64_M8_MASK, VFSGNJX_VF }, // 2355
|
|
{ PseudoVFSGNJX_VV_M1, VFSGNJX_VV }, // 2356
|
|
{ PseudoVFSGNJX_VV_M1_MASK, VFSGNJX_VV }, // 2357
|
|
{ PseudoVFSGNJX_VV_M2, VFSGNJX_VV }, // 2358
|
|
{ PseudoVFSGNJX_VV_M2_MASK, VFSGNJX_VV }, // 2359
|
|
{ PseudoVFSGNJX_VV_M4, VFSGNJX_VV }, // 2360
|
|
{ PseudoVFSGNJX_VV_M4_MASK, VFSGNJX_VV }, // 2361
|
|
{ PseudoVFSGNJX_VV_M8, VFSGNJX_VV }, // 2362
|
|
{ PseudoVFSGNJX_VV_M8_MASK, VFSGNJX_VV }, // 2363
|
|
{ PseudoVFSGNJX_VV_MF2, VFSGNJX_VV }, // 2364
|
|
{ PseudoVFSGNJX_VV_MF2_MASK, VFSGNJX_VV }, // 2365
|
|
{ PseudoVFSGNJX_VV_MF4, VFSGNJX_VV }, // 2366
|
|
{ PseudoVFSGNJX_VV_MF4_MASK, VFSGNJX_VV }, // 2367
|
|
{ PseudoVFSGNJ_VFPR16_M1, VFSGNJ_VF }, // 2368
|
|
{ PseudoVFSGNJ_VFPR16_M1_MASK, VFSGNJ_VF }, // 2369
|
|
{ PseudoVFSGNJ_VFPR16_M2, VFSGNJ_VF }, // 2370
|
|
{ PseudoVFSGNJ_VFPR16_M2_MASK, VFSGNJ_VF }, // 2371
|
|
{ PseudoVFSGNJ_VFPR16_M4, VFSGNJ_VF }, // 2372
|
|
{ PseudoVFSGNJ_VFPR16_M4_MASK, VFSGNJ_VF }, // 2373
|
|
{ PseudoVFSGNJ_VFPR16_M8, VFSGNJ_VF }, // 2374
|
|
{ PseudoVFSGNJ_VFPR16_M8_MASK, VFSGNJ_VF }, // 2375
|
|
{ PseudoVFSGNJ_VFPR16_MF2, VFSGNJ_VF }, // 2376
|
|
{ PseudoVFSGNJ_VFPR16_MF2_MASK, VFSGNJ_VF }, // 2377
|
|
{ PseudoVFSGNJ_VFPR16_MF4, VFSGNJ_VF }, // 2378
|
|
{ PseudoVFSGNJ_VFPR16_MF4_MASK, VFSGNJ_VF }, // 2379
|
|
{ PseudoVFSGNJ_VFPR32_M1, VFSGNJ_VF }, // 2380
|
|
{ PseudoVFSGNJ_VFPR32_M1_MASK, VFSGNJ_VF }, // 2381
|
|
{ PseudoVFSGNJ_VFPR32_M2, VFSGNJ_VF }, // 2382
|
|
{ PseudoVFSGNJ_VFPR32_M2_MASK, VFSGNJ_VF }, // 2383
|
|
{ PseudoVFSGNJ_VFPR32_M4, VFSGNJ_VF }, // 2384
|
|
{ PseudoVFSGNJ_VFPR32_M4_MASK, VFSGNJ_VF }, // 2385
|
|
{ PseudoVFSGNJ_VFPR32_M8, VFSGNJ_VF }, // 2386
|
|
{ PseudoVFSGNJ_VFPR32_M8_MASK, VFSGNJ_VF }, // 2387
|
|
{ PseudoVFSGNJ_VFPR32_MF2, VFSGNJ_VF }, // 2388
|
|
{ PseudoVFSGNJ_VFPR32_MF2_MASK, VFSGNJ_VF }, // 2389
|
|
{ PseudoVFSGNJ_VFPR64_M1, VFSGNJ_VF }, // 2390
|
|
{ PseudoVFSGNJ_VFPR64_M1_MASK, VFSGNJ_VF }, // 2391
|
|
{ PseudoVFSGNJ_VFPR64_M2, VFSGNJ_VF }, // 2392
|
|
{ PseudoVFSGNJ_VFPR64_M2_MASK, VFSGNJ_VF }, // 2393
|
|
{ PseudoVFSGNJ_VFPR64_M4, VFSGNJ_VF }, // 2394
|
|
{ PseudoVFSGNJ_VFPR64_M4_MASK, VFSGNJ_VF }, // 2395
|
|
{ PseudoVFSGNJ_VFPR64_M8, VFSGNJ_VF }, // 2396
|
|
{ PseudoVFSGNJ_VFPR64_M8_MASK, VFSGNJ_VF }, // 2397
|
|
{ PseudoVFSGNJ_VV_M1, VFSGNJ_VV }, // 2398
|
|
{ PseudoVFSGNJ_VV_M1_MASK, VFSGNJ_VV }, // 2399
|
|
{ PseudoVFSGNJ_VV_M2, VFSGNJ_VV }, // 2400
|
|
{ PseudoVFSGNJ_VV_M2_MASK, VFSGNJ_VV }, // 2401
|
|
{ PseudoVFSGNJ_VV_M4, VFSGNJ_VV }, // 2402
|
|
{ PseudoVFSGNJ_VV_M4_MASK, VFSGNJ_VV }, // 2403
|
|
{ PseudoVFSGNJ_VV_M8, VFSGNJ_VV }, // 2404
|
|
{ PseudoVFSGNJ_VV_M8_MASK, VFSGNJ_VV }, // 2405
|
|
{ PseudoVFSGNJ_VV_MF2, VFSGNJ_VV }, // 2406
|
|
{ PseudoVFSGNJ_VV_MF2_MASK, VFSGNJ_VV }, // 2407
|
|
{ PseudoVFSGNJ_VV_MF4, VFSGNJ_VV }, // 2408
|
|
{ PseudoVFSGNJ_VV_MF4_MASK, VFSGNJ_VV }, // 2409
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF }, // 2410
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF }, // 2411
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF }, // 2412
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF }, // 2413
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF }, // 2414
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF }, // 2415
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF }, // 2416
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF }, // 2417
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF }, // 2418
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF }, // 2419
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF }, // 2420
|
|
{ PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF }, // 2421
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF }, // 2422
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF }, // 2423
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF }, // 2424
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF }, // 2425
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF }, // 2426
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF }, // 2427
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF }, // 2428
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF }, // 2429
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF }, // 2430
|
|
{ PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF }, // 2431
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF }, // 2432
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF }, // 2433
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF }, // 2434
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF }, // 2435
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF }, // 2436
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF }, // 2437
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF }, // 2438
|
|
{ PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF }, // 2439
|
|
{ PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF }, // 2440
|
|
{ PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF }, // 2441
|
|
{ PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF }, // 2442
|
|
{ PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF }, // 2443
|
|
{ PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF }, // 2444
|
|
{ PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF }, // 2445
|
|
{ PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF }, // 2446
|
|
{ PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF }, // 2447
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF }, // 2448
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF }, // 2449
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF }, // 2450
|
|
{ PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF }, // 2451
|
|
{ PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF }, // 2452
|
|
{ PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF }, // 2453
|
|
{ PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF }, // 2454
|
|
{ PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF }, // 2455
|
|
{ PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF }, // 2456
|
|
{ PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF }, // 2457
|
|
{ PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF }, // 2458
|
|
{ PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF }, // 2459
|
|
{ PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF }, // 2460
|
|
{ PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF }, // 2461
|
|
{ PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF }, // 2462
|
|
{ PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF }, // 2463
|
|
{ PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF }, // 2464
|
|
{ PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF }, // 2465
|
|
{ PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF }, // 2466
|
|
{ PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF }, // 2467
|
|
{ PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF }, // 2468
|
|
{ PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF }, // 2469
|
|
{ PseudoVFSQRT_V_M1_E16, VFSQRT_V }, // 2470
|
|
{ PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V }, // 2471
|
|
{ PseudoVFSQRT_V_M1_E32, VFSQRT_V }, // 2472
|
|
{ PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V }, // 2473
|
|
{ PseudoVFSQRT_V_M1_E64, VFSQRT_V }, // 2474
|
|
{ PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V }, // 2475
|
|
{ PseudoVFSQRT_V_M2_E16, VFSQRT_V }, // 2476
|
|
{ PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V }, // 2477
|
|
{ PseudoVFSQRT_V_M2_E32, VFSQRT_V }, // 2478
|
|
{ PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V }, // 2479
|
|
{ PseudoVFSQRT_V_M2_E64, VFSQRT_V }, // 2480
|
|
{ PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V }, // 2481
|
|
{ PseudoVFSQRT_V_M4_E16, VFSQRT_V }, // 2482
|
|
{ PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V }, // 2483
|
|
{ PseudoVFSQRT_V_M4_E32, VFSQRT_V }, // 2484
|
|
{ PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V }, // 2485
|
|
{ PseudoVFSQRT_V_M4_E64, VFSQRT_V }, // 2486
|
|
{ PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V }, // 2487
|
|
{ PseudoVFSQRT_V_M8_E16, VFSQRT_V }, // 2488
|
|
{ PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V }, // 2489
|
|
{ PseudoVFSQRT_V_M8_E32, VFSQRT_V }, // 2490
|
|
{ PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V }, // 2491
|
|
{ PseudoVFSQRT_V_M8_E64, VFSQRT_V }, // 2492
|
|
{ PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V }, // 2493
|
|
{ PseudoVFSQRT_V_MF2_E16, VFSQRT_V }, // 2494
|
|
{ PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V }, // 2495
|
|
{ PseudoVFSQRT_V_MF2_E32, VFSQRT_V }, // 2496
|
|
{ PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V }, // 2497
|
|
{ PseudoVFSQRT_V_MF4_E16, VFSQRT_V }, // 2498
|
|
{ PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V }, // 2499
|
|
{ PseudoVFSUB_VFPR16_M1, VFSUB_VF }, // 2500
|
|
{ PseudoVFSUB_VFPR16_M1_MASK, VFSUB_VF }, // 2501
|
|
{ PseudoVFSUB_VFPR16_M2, VFSUB_VF }, // 2502
|
|
{ PseudoVFSUB_VFPR16_M2_MASK, VFSUB_VF }, // 2503
|
|
{ PseudoVFSUB_VFPR16_M4, VFSUB_VF }, // 2504
|
|
{ PseudoVFSUB_VFPR16_M4_MASK, VFSUB_VF }, // 2505
|
|
{ PseudoVFSUB_VFPR16_M8, VFSUB_VF }, // 2506
|
|
{ PseudoVFSUB_VFPR16_M8_MASK, VFSUB_VF }, // 2507
|
|
{ PseudoVFSUB_VFPR16_MF2, VFSUB_VF }, // 2508
|
|
{ PseudoVFSUB_VFPR16_MF2_MASK, VFSUB_VF }, // 2509
|
|
{ PseudoVFSUB_VFPR16_MF4, VFSUB_VF }, // 2510
|
|
{ PseudoVFSUB_VFPR16_MF4_MASK, VFSUB_VF }, // 2511
|
|
{ PseudoVFSUB_VFPR32_M1, VFSUB_VF }, // 2512
|
|
{ PseudoVFSUB_VFPR32_M1_MASK, VFSUB_VF }, // 2513
|
|
{ PseudoVFSUB_VFPR32_M2, VFSUB_VF }, // 2514
|
|
{ PseudoVFSUB_VFPR32_M2_MASK, VFSUB_VF }, // 2515
|
|
{ PseudoVFSUB_VFPR32_M4, VFSUB_VF }, // 2516
|
|
{ PseudoVFSUB_VFPR32_M4_MASK, VFSUB_VF }, // 2517
|
|
{ PseudoVFSUB_VFPR32_M8, VFSUB_VF }, // 2518
|
|
{ PseudoVFSUB_VFPR32_M8_MASK, VFSUB_VF }, // 2519
|
|
{ PseudoVFSUB_VFPR32_MF2, VFSUB_VF }, // 2520
|
|
{ PseudoVFSUB_VFPR32_MF2_MASK, VFSUB_VF }, // 2521
|
|
{ PseudoVFSUB_VFPR64_M1, VFSUB_VF }, // 2522
|
|
{ PseudoVFSUB_VFPR64_M1_MASK, VFSUB_VF }, // 2523
|
|
{ PseudoVFSUB_VFPR64_M2, VFSUB_VF }, // 2524
|
|
{ PseudoVFSUB_VFPR64_M2_MASK, VFSUB_VF }, // 2525
|
|
{ PseudoVFSUB_VFPR64_M4, VFSUB_VF }, // 2526
|
|
{ PseudoVFSUB_VFPR64_M4_MASK, VFSUB_VF }, // 2527
|
|
{ PseudoVFSUB_VFPR64_M8, VFSUB_VF }, // 2528
|
|
{ PseudoVFSUB_VFPR64_M8_MASK, VFSUB_VF }, // 2529
|
|
{ PseudoVFSUB_VV_M1, VFSUB_VV }, // 2530
|
|
{ PseudoVFSUB_VV_M1_MASK, VFSUB_VV }, // 2531
|
|
{ PseudoVFSUB_VV_M2, VFSUB_VV }, // 2532
|
|
{ PseudoVFSUB_VV_M2_MASK, VFSUB_VV }, // 2533
|
|
{ PseudoVFSUB_VV_M4, VFSUB_VV }, // 2534
|
|
{ PseudoVFSUB_VV_M4_MASK, VFSUB_VV }, // 2535
|
|
{ PseudoVFSUB_VV_M8, VFSUB_VV }, // 2536
|
|
{ PseudoVFSUB_VV_M8_MASK, VFSUB_VV }, // 2537
|
|
{ PseudoVFSUB_VV_MF2, VFSUB_VV }, // 2538
|
|
{ PseudoVFSUB_VV_MF2_MASK, VFSUB_VV }, // 2539
|
|
{ PseudoVFSUB_VV_MF4, VFSUB_VV }, // 2540
|
|
{ PseudoVFSUB_VV_MF4_MASK, VFSUB_VV }, // 2541
|
|
{ PseudoVFWADD_VFPR16_M1, VFWADD_VF }, // 2542
|
|
{ PseudoVFWADD_VFPR16_M1_MASK, VFWADD_VF }, // 2543
|
|
{ PseudoVFWADD_VFPR16_M2, VFWADD_VF }, // 2544
|
|
{ PseudoVFWADD_VFPR16_M2_MASK, VFWADD_VF }, // 2545
|
|
{ PseudoVFWADD_VFPR16_M4, VFWADD_VF }, // 2546
|
|
{ PseudoVFWADD_VFPR16_M4_MASK, VFWADD_VF }, // 2547
|
|
{ PseudoVFWADD_VFPR16_MF2, VFWADD_VF }, // 2548
|
|
{ PseudoVFWADD_VFPR16_MF2_MASK, VFWADD_VF }, // 2549
|
|
{ PseudoVFWADD_VFPR16_MF4, VFWADD_VF }, // 2550
|
|
{ PseudoVFWADD_VFPR16_MF4_MASK, VFWADD_VF }, // 2551
|
|
{ PseudoVFWADD_VFPR32_M1, VFWADD_VF }, // 2552
|
|
{ PseudoVFWADD_VFPR32_M1_MASK, VFWADD_VF }, // 2553
|
|
{ PseudoVFWADD_VFPR32_M2, VFWADD_VF }, // 2554
|
|
{ PseudoVFWADD_VFPR32_M2_MASK, VFWADD_VF }, // 2555
|
|
{ PseudoVFWADD_VFPR32_M4, VFWADD_VF }, // 2556
|
|
{ PseudoVFWADD_VFPR32_M4_MASK, VFWADD_VF }, // 2557
|
|
{ PseudoVFWADD_VFPR32_MF2, VFWADD_VF }, // 2558
|
|
{ PseudoVFWADD_VFPR32_MF2_MASK, VFWADD_VF }, // 2559
|
|
{ PseudoVFWADD_VV_M1, VFWADD_VV }, // 2560
|
|
{ PseudoVFWADD_VV_M1_MASK, VFWADD_VV }, // 2561
|
|
{ PseudoVFWADD_VV_M2, VFWADD_VV }, // 2562
|
|
{ PseudoVFWADD_VV_M2_MASK, VFWADD_VV }, // 2563
|
|
{ PseudoVFWADD_VV_M4, VFWADD_VV }, // 2564
|
|
{ PseudoVFWADD_VV_M4_MASK, VFWADD_VV }, // 2565
|
|
{ PseudoVFWADD_VV_MF2, VFWADD_VV }, // 2566
|
|
{ PseudoVFWADD_VV_MF2_MASK, VFWADD_VV }, // 2567
|
|
{ PseudoVFWADD_VV_MF4, VFWADD_VV }, // 2568
|
|
{ PseudoVFWADD_VV_MF4_MASK, VFWADD_VV }, // 2569
|
|
{ PseudoVFWADD_WFPR16_M1, VFWADD_WF }, // 2570
|
|
{ PseudoVFWADD_WFPR16_M1_MASK, VFWADD_WF }, // 2571
|
|
{ PseudoVFWADD_WFPR16_M2, VFWADD_WF }, // 2572
|
|
{ PseudoVFWADD_WFPR16_M2_MASK, VFWADD_WF }, // 2573
|
|
{ PseudoVFWADD_WFPR16_M4, VFWADD_WF }, // 2574
|
|
{ PseudoVFWADD_WFPR16_M4_MASK, VFWADD_WF }, // 2575
|
|
{ PseudoVFWADD_WFPR16_MF2, VFWADD_WF }, // 2576
|
|
{ PseudoVFWADD_WFPR16_MF2_MASK, VFWADD_WF }, // 2577
|
|
{ PseudoVFWADD_WFPR16_MF4, VFWADD_WF }, // 2578
|
|
{ PseudoVFWADD_WFPR16_MF4_MASK, VFWADD_WF }, // 2579
|
|
{ PseudoVFWADD_WFPR32_M1, VFWADD_WF }, // 2580
|
|
{ PseudoVFWADD_WFPR32_M1_MASK, VFWADD_WF }, // 2581
|
|
{ PseudoVFWADD_WFPR32_M2, VFWADD_WF }, // 2582
|
|
{ PseudoVFWADD_WFPR32_M2_MASK, VFWADD_WF }, // 2583
|
|
{ PseudoVFWADD_WFPR32_M4, VFWADD_WF }, // 2584
|
|
{ PseudoVFWADD_WFPR32_M4_MASK, VFWADD_WF }, // 2585
|
|
{ PseudoVFWADD_WFPR32_MF2, VFWADD_WF }, // 2586
|
|
{ PseudoVFWADD_WFPR32_MF2_MASK, VFWADD_WF }, // 2587
|
|
{ PseudoVFWADD_WV_M1, VFWADD_WV }, // 2588
|
|
{ PseudoVFWADD_WV_M1_MASK, VFWADD_WV }, // 2589
|
|
{ PseudoVFWADD_WV_M1_MASK_TIED, VFWADD_WV }, // 2590
|
|
{ PseudoVFWADD_WV_M1_TIED, VFWADD_WV }, // 2591
|
|
{ PseudoVFWADD_WV_M2, VFWADD_WV }, // 2592
|
|
{ PseudoVFWADD_WV_M2_MASK, VFWADD_WV }, // 2593
|
|
{ PseudoVFWADD_WV_M2_MASK_TIED, VFWADD_WV }, // 2594
|
|
{ PseudoVFWADD_WV_M2_TIED, VFWADD_WV }, // 2595
|
|
{ PseudoVFWADD_WV_M4, VFWADD_WV }, // 2596
|
|
{ PseudoVFWADD_WV_M4_MASK, VFWADD_WV }, // 2597
|
|
{ PseudoVFWADD_WV_M4_MASK_TIED, VFWADD_WV }, // 2598
|
|
{ PseudoVFWADD_WV_M4_TIED, VFWADD_WV }, // 2599
|
|
{ PseudoVFWADD_WV_MF2, VFWADD_WV }, // 2600
|
|
{ PseudoVFWADD_WV_MF2_MASK, VFWADD_WV }, // 2601
|
|
{ PseudoVFWADD_WV_MF2_MASK_TIED, VFWADD_WV }, // 2602
|
|
{ PseudoVFWADD_WV_MF2_TIED, VFWADD_WV }, // 2603
|
|
{ PseudoVFWADD_WV_MF4, VFWADD_WV }, // 2604
|
|
{ PseudoVFWADD_WV_MF4_MASK, VFWADD_WV }, // 2605
|
|
{ PseudoVFWADD_WV_MF4_MASK_TIED, VFWADD_WV }, // 2606
|
|
{ PseudoVFWADD_WV_MF4_TIED, VFWADD_WV }, // 2607
|
|
{ PseudoVFWCVTBF16_F_F_V_M1, VFWCVTBF16_F_F_V }, // 2608
|
|
{ PseudoVFWCVTBF16_F_F_V_M1_MASK, VFWCVTBF16_F_F_V }, // 2609
|
|
{ PseudoVFWCVTBF16_F_F_V_M2, VFWCVTBF16_F_F_V }, // 2610
|
|
{ PseudoVFWCVTBF16_F_F_V_M2_MASK, VFWCVTBF16_F_F_V }, // 2611
|
|
{ PseudoVFWCVTBF16_F_F_V_M4, VFWCVTBF16_F_F_V }, // 2612
|
|
{ PseudoVFWCVTBF16_F_F_V_M4_MASK, VFWCVTBF16_F_F_V }, // 2613
|
|
{ PseudoVFWCVTBF16_F_F_V_MF2, VFWCVTBF16_F_F_V }, // 2614
|
|
{ PseudoVFWCVTBF16_F_F_V_MF2_MASK, VFWCVTBF16_F_F_V }, // 2615
|
|
{ PseudoVFWCVTBF16_F_F_V_MF4, VFWCVTBF16_F_F_V }, // 2616
|
|
{ PseudoVFWCVTBF16_F_F_V_MF4_MASK, VFWCVTBF16_F_F_V }, // 2617
|
|
{ PseudoVFWCVT_F_F_V_M1, VFWCVT_F_F_V }, // 2618
|
|
{ PseudoVFWCVT_F_F_V_M1_MASK, VFWCVT_F_F_V }, // 2619
|
|
{ PseudoVFWCVT_F_F_V_M2, VFWCVT_F_F_V }, // 2620
|
|
{ PseudoVFWCVT_F_F_V_M2_MASK, VFWCVT_F_F_V }, // 2621
|
|
{ PseudoVFWCVT_F_F_V_M4, VFWCVT_F_F_V }, // 2622
|
|
{ PseudoVFWCVT_F_F_V_M4_MASK, VFWCVT_F_F_V }, // 2623
|
|
{ PseudoVFWCVT_F_F_V_MF2, VFWCVT_F_F_V }, // 2624
|
|
{ PseudoVFWCVT_F_F_V_MF2_MASK, VFWCVT_F_F_V }, // 2625
|
|
{ PseudoVFWCVT_F_F_V_MF4, VFWCVT_F_F_V }, // 2626
|
|
{ PseudoVFWCVT_F_F_V_MF4_MASK, VFWCVT_F_F_V }, // 2627
|
|
{ PseudoVFWCVT_F_XU_V_M1, VFWCVT_F_XU_V }, // 2628
|
|
{ PseudoVFWCVT_F_XU_V_M1_MASK, VFWCVT_F_XU_V }, // 2629
|
|
{ PseudoVFWCVT_F_XU_V_M2, VFWCVT_F_XU_V }, // 2630
|
|
{ PseudoVFWCVT_F_XU_V_M2_MASK, VFWCVT_F_XU_V }, // 2631
|
|
{ PseudoVFWCVT_F_XU_V_M4, VFWCVT_F_XU_V }, // 2632
|
|
{ PseudoVFWCVT_F_XU_V_M4_MASK, VFWCVT_F_XU_V }, // 2633
|
|
{ PseudoVFWCVT_F_XU_V_MF2, VFWCVT_F_XU_V }, // 2634
|
|
{ PseudoVFWCVT_F_XU_V_MF2_MASK, VFWCVT_F_XU_V }, // 2635
|
|
{ PseudoVFWCVT_F_XU_V_MF4, VFWCVT_F_XU_V }, // 2636
|
|
{ PseudoVFWCVT_F_XU_V_MF4_MASK, VFWCVT_F_XU_V }, // 2637
|
|
{ PseudoVFWCVT_F_XU_V_MF8, VFWCVT_F_XU_V }, // 2638
|
|
{ PseudoVFWCVT_F_XU_V_MF8_MASK, VFWCVT_F_XU_V }, // 2639
|
|
{ PseudoVFWCVT_F_X_V_M1, VFWCVT_F_X_V }, // 2640
|
|
{ PseudoVFWCVT_F_X_V_M1_MASK, VFWCVT_F_X_V }, // 2641
|
|
{ PseudoVFWCVT_F_X_V_M2, VFWCVT_F_X_V }, // 2642
|
|
{ PseudoVFWCVT_F_X_V_M2_MASK, VFWCVT_F_X_V }, // 2643
|
|
{ PseudoVFWCVT_F_X_V_M4, VFWCVT_F_X_V }, // 2644
|
|
{ PseudoVFWCVT_F_X_V_M4_MASK, VFWCVT_F_X_V }, // 2645
|
|
{ PseudoVFWCVT_F_X_V_MF2, VFWCVT_F_X_V }, // 2646
|
|
{ PseudoVFWCVT_F_X_V_MF2_MASK, VFWCVT_F_X_V }, // 2647
|
|
{ PseudoVFWCVT_F_X_V_MF4, VFWCVT_F_X_V }, // 2648
|
|
{ PseudoVFWCVT_F_X_V_MF4_MASK, VFWCVT_F_X_V }, // 2649
|
|
{ PseudoVFWCVT_F_X_V_MF8, VFWCVT_F_X_V }, // 2650
|
|
{ PseudoVFWCVT_F_X_V_MF8_MASK, VFWCVT_F_X_V }, // 2651
|
|
{ PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V }, // 2652
|
|
{ PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V }, // 2653
|
|
{ PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V }, // 2654
|
|
{ PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V }, // 2655
|
|
{ PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V }, // 2656
|
|
{ PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V }, // 2657
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V }, // 2658
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V }, // 2659
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V }, // 2660
|
|
{ PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V }, // 2661
|
|
{ PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V }, // 2662
|
|
{ PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V }, // 2663
|
|
{ PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V }, // 2664
|
|
{ PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V }, // 2665
|
|
{ PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V }, // 2666
|
|
{ PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V }, // 2667
|
|
{ PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V }, // 2668
|
|
{ PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V }, // 2669
|
|
{ PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V }, // 2670
|
|
{ PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V }, // 2671
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V }, // 2672
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V }, // 2673
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V }, // 2674
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V }, // 2675
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V }, // 2676
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V }, // 2677
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V }, // 2678
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V }, // 2679
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V }, // 2680
|
|
{ PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V }, // 2681
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V }, // 2682
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V }, // 2683
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V }, // 2684
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V }, // 2685
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V }, // 2686
|
|
{ PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V }, // 2687
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V }, // 2688
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V }, // 2689
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V }, // 2690
|
|
{ PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V }, // 2691
|
|
{ PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V }, // 2692
|
|
{ PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V }, // 2693
|
|
{ PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V }, // 2694
|
|
{ PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V }, // 2695
|
|
{ PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V }, // 2696
|
|
{ PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V }, // 2697
|
|
{ PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V }, // 2698
|
|
{ PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V }, // 2699
|
|
{ PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V }, // 2700
|
|
{ PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V }, // 2701
|
|
{ PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V }, // 2702
|
|
{ PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V }, // 2703
|
|
{ PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V }, // 2704
|
|
{ PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V }, // 2705
|
|
{ PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V }, // 2706
|
|
{ PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V }, // 2707
|
|
{ PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V }, // 2708
|
|
{ PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V }, // 2709
|
|
{ PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V }, // 2710
|
|
{ PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V }, // 2711
|
|
{ PseudoVFWMACCBF16_VFPR16_M1, VFWMACCBF16_VF }, // 2712
|
|
{ PseudoVFWMACCBF16_VFPR16_M1_MASK, VFWMACCBF16_VF }, // 2713
|
|
{ PseudoVFWMACCBF16_VFPR16_M2, VFWMACCBF16_VF }, // 2714
|
|
{ PseudoVFWMACCBF16_VFPR16_M2_MASK, VFWMACCBF16_VF }, // 2715
|
|
{ PseudoVFWMACCBF16_VFPR16_M4, VFWMACCBF16_VF }, // 2716
|
|
{ PseudoVFWMACCBF16_VFPR16_M4_MASK, VFWMACCBF16_VF }, // 2717
|
|
{ PseudoVFWMACCBF16_VFPR16_MF2, VFWMACCBF16_VF }, // 2718
|
|
{ PseudoVFWMACCBF16_VFPR16_MF2_MASK, VFWMACCBF16_VF }, // 2719
|
|
{ PseudoVFWMACCBF16_VFPR16_MF4, VFWMACCBF16_VF }, // 2720
|
|
{ PseudoVFWMACCBF16_VFPR16_MF4_MASK, VFWMACCBF16_VF }, // 2721
|
|
{ PseudoVFWMACCBF16_VV_M1, VFWMACCBF16_VV }, // 2722
|
|
{ PseudoVFWMACCBF16_VV_M1_MASK, VFWMACCBF16_VV }, // 2723
|
|
{ PseudoVFWMACCBF16_VV_M2, VFWMACCBF16_VV }, // 2724
|
|
{ PseudoVFWMACCBF16_VV_M2_MASK, VFWMACCBF16_VV }, // 2725
|
|
{ PseudoVFWMACCBF16_VV_M4, VFWMACCBF16_VV }, // 2726
|
|
{ PseudoVFWMACCBF16_VV_M4_MASK, VFWMACCBF16_VV }, // 2727
|
|
{ PseudoVFWMACCBF16_VV_MF2, VFWMACCBF16_VV }, // 2728
|
|
{ PseudoVFWMACCBF16_VV_MF2_MASK, VFWMACCBF16_VV }, // 2729
|
|
{ PseudoVFWMACCBF16_VV_MF4, VFWMACCBF16_VV }, // 2730
|
|
{ PseudoVFWMACCBF16_VV_MF4_MASK, VFWMACCBF16_VV }, // 2731
|
|
{ PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4 }, // 2732
|
|
{ PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4 }, // 2733
|
|
{ PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4 }, // 2734
|
|
{ PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4 }, // 2735
|
|
{ PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4 }, // 2736
|
|
{ PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4 }, // 2737
|
|
{ PseudoVFWMACC_VFPR16_M1, VFWMACC_VF }, // 2738
|
|
{ PseudoVFWMACC_VFPR16_M1_MASK, VFWMACC_VF }, // 2739
|
|
{ PseudoVFWMACC_VFPR16_M2, VFWMACC_VF }, // 2740
|
|
{ PseudoVFWMACC_VFPR16_M2_MASK, VFWMACC_VF }, // 2741
|
|
{ PseudoVFWMACC_VFPR16_M4, VFWMACC_VF }, // 2742
|
|
{ PseudoVFWMACC_VFPR16_M4_MASK, VFWMACC_VF }, // 2743
|
|
{ PseudoVFWMACC_VFPR16_MF2, VFWMACC_VF }, // 2744
|
|
{ PseudoVFWMACC_VFPR16_MF2_MASK, VFWMACC_VF }, // 2745
|
|
{ PseudoVFWMACC_VFPR16_MF4, VFWMACC_VF }, // 2746
|
|
{ PseudoVFWMACC_VFPR16_MF4_MASK, VFWMACC_VF }, // 2747
|
|
{ PseudoVFWMACC_VFPR32_M1, VFWMACC_VF }, // 2748
|
|
{ PseudoVFWMACC_VFPR32_M1_MASK, VFWMACC_VF }, // 2749
|
|
{ PseudoVFWMACC_VFPR32_M2, VFWMACC_VF }, // 2750
|
|
{ PseudoVFWMACC_VFPR32_M2_MASK, VFWMACC_VF }, // 2751
|
|
{ PseudoVFWMACC_VFPR32_M4, VFWMACC_VF }, // 2752
|
|
{ PseudoVFWMACC_VFPR32_M4_MASK, VFWMACC_VF }, // 2753
|
|
{ PseudoVFWMACC_VFPR32_MF2, VFWMACC_VF }, // 2754
|
|
{ PseudoVFWMACC_VFPR32_MF2_MASK, VFWMACC_VF }, // 2755
|
|
{ PseudoVFWMACC_VV_M1, VFWMACC_VV }, // 2756
|
|
{ PseudoVFWMACC_VV_M1_MASK, VFWMACC_VV }, // 2757
|
|
{ PseudoVFWMACC_VV_M2, VFWMACC_VV }, // 2758
|
|
{ PseudoVFWMACC_VV_M2_MASK, VFWMACC_VV }, // 2759
|
|
{ PseudoVFWMACC_VV_M4, VFWMACC_VV }, // 2760
|
|
{ PseudoVFWMACC_VV_M4_MASK, VFWMACC_VV }, // 2761
|
|
{ PseudoVFWMACC_VV_MF2, VFWMACC_VV }, // 2762
|
|
{ PseudoVFWMACC_VV_MF2_MASK, VFWMACC_VV }, // 2763
|
|
{ PseudoVFWMACC_VV_MF4, VFWMACC_VV }, // 2764
|
|
{ PseudoVFWMACC_VV_MF4_MASK, VFWMACC_VV }, // 2765
|
|
{ PseudoVFWMSAC_VFPR16_M1, VFWMSAC_VF }, // 2766
|
|
{ PseudoVFWMSAC_VFPR16_M1_MASK, VFWMSAC_VF }, // 2767
|
|
{ PseudoVFWMSAC_VFPR16_M2, VFWMSAC_VF }, // 2768
|
|
{ PseudoVFWMSAC_VFPR16_M2_MASK, VFWMSAC_VF }, // 2769
|
|
{ PseudoVFWMSAC_VFPR16_M4, VFWMSAC_VF }, // 2770
|
|
{ PseudoVFWMSAC_VFPR16_M4_MASK, VFWMSAC_VF }, // 2771
|
|
{ PseudoVFWMSAC_VFPR16_MF2, VFWMSAC_VF }, // 2772
|
|
{ PseudoVFWMSAC_VFPR16_MF2_MASK, VFWMSAC_VF }, // 2773
|
|
{ PseudoVFWMSAC_VFPR16_MF4, VFWMSAC_VF }, // 2774
|
|
{ PseudoVFWMSAC_VFPR16_MF4_MASK, VFWMSAC_VF }, // 2775
|
|
{ PseudoVFWMSAC_VFPR32_M1, VFWMSAC_VF }, // 2776
|
|
{ PseudoVFWMSAC_VFPR32_M1_MASK, VFWMSAC_VF }, // 2777
|
|
{ PseudoVFWMSAC_VFPR32_M2, VFWMSAC_VF }, // 2778
|
|
{ PseudoVFWMSAC_VFPR32_M2_MASK, VFWMSAC_VF }, // 2779
|
|
{ PseudoVFWMSAC_VFPR32_M4, VFWMSAC_VF }, // 2780
|
|
{ PseudoVFWMSAC_VFPR32_M4_MASK, VFWMSAC_VF }, // 2781
|
|
{ PseudoVFWMSAC_VFPR32_MF2, VFWMSAC_VF }, // 2782
|
|
{ PseudoVFWMSAC_VFPR32_MF2_MASK, VFWMSAC_VF }, // 2783
|
|
{ PseudoVFWMSAC_VV_M1, VFWMSAC_VV }, // 2784
|
|
{ PseudoVFWMSAC_VV_M1_MASK, VFWMSAC_VV }, // 2785
|
|
{ PseudoVFWMSAC_VV_M2, VFWMSAC_VV }, // 2786
|
|
{ PseudoVFWMSAC_VV_M2_MASK, VFWMSAC_VV }, // 2787
|
|
{ PseudoVFWMSAC_VV_M4, VFWMSAC_VV }, // 2788
|
|
{ PseudoVFWMSAC_VV_M4_MASK, VFWMSAC_VV }, // 2789
|
|
{ PseudoVFWMSAC_VV_MF2, VFWMSAC_VV }, // 2790
|
|
{ PseudoVFWMSAC_VV_MF2_MASK, VFWMSAC_VV }, // 2791
|
|
{ PseudoVFWMSAC_VV_MF4, VFWMSAC_VV }, // 2792
|
|
{ PseudoVFWMSAC_VV_MF4_MASK, VFWMSAC_VV }, // 2793
|
|
{ PseudoVFWMUL_VFPR16_M1, VFWMUL_VF }, // 2794
|
|
{ PseudoVFWMUL_VFPR16_M1_MASK, VFWMUL_VF }, // 2795
|
|
{ PseudoVFWMUL_VFPR16_M2, VFWMUL_VF }, // 2796
|
|
{ PseudoVFWMUL_VFPR16_M2_MASK, VFWMUL_VF }, // 2797
|
|
{ PseudoVFWMUL_VFPR16_M4, VFWMUL_VF }, // 2798
|
|
{ PseudoVFWMUL_VFPR16_M4_MASK, VFWMUL_VF }, // 2799
|
|
{ PseudoVFWMUL_VFPR16_MF2, VFWMUL_VF }, // 2800
|
|
{ PseudoVFWMUL_VFPR16_MF2_MASK, VFWMUL_VF }, // 2801
|
|
{ PseudoVFWMUL_VFPR16_MF4, VFWMUL_VF }, // 2802
|
|
{ PseudoVFWMUL_VFPR16_MF4_MASK, VFWMUL_VF }, // 2803
|
|
{ PseudoVFWMUL_VFPR32_M1, VFWMUL_VF }, // 2804
|
|
{ PseudoVFWMUL_VFPR32_M1_MASK, VFWMUL_VF }, // 2805
|
|
{ PseudoVFWMUL_VFPR32_M2, VFWMUL_VF }, // 2806
|
|
{ PseudoVFWMUL_VFPR32_M2_MASK, VFWMUL_VF }, // 2807
|
|
{ PseudoVFWMUL_VFPR32_M4, VFWMUL_VF }, // 2808
|
|
{ PseudoVFWMUL_VFPR32_M4_MASK, VFWMUL_VF }, // 2809
|
|
{ PseudoVFWMUL_VFPR32_MF2, VFWMUL_VF }, // 2810
|
|
{ PseudoVFWMUL_VFPR32_MF2_MASK, VFWMUL_VF }, // 2811
|
|
{ PseudoVFWMUL_VV_M1, VFWMUL_VV }, // 2812
|
|
{ PseudoVFWMUL_VV_M1_MASK, VFWMUL_VV }, // 2813
|
|
{ PseudoVFWMUL_VV_M2, VFWMUL_VV }, // 2814
|
|
{ PseudoVFWMUL_VV_M2_MASK, VFWMUL_VV }, // 2815
|
|
{ PseudoVFWMUL_VV_M4, VFWMUL_VV }, // 2816
|
|
{ PseudoVFWMUL_VV_M4_MASK, VFWMUL_VV }, // 2817
|
|
{ PseudoVFWMUL_VV_MF2, VFWMUL_VV }, // 2818
|
|
{ PseudoVFWMUL_VV_MF2_MASK, VFWMUL_VV }, // 2819
|
|
{ PseudoVFWMUL_VV_MF4, VFWMUL_VV }, // 2820
|
|
{ PseudoVFWMUL_VV_MF4_MASK, VFWMUL_VV }, // 2821
|
|
{ PseudoVFWNMACC_VFPR16_M1, VFWNMACC_VF }, // 2822
|
|
{ PseudoVFWNMACC_VFPR16_M1_MASK, VFWNMACC_VF }, // 2823
|
|
{ PseudoVFWNMACC_VFPR16_M2, VFWNMACC_VF }, // 2824
|
|
{ PseudoVFWNMACC_VFPR16_M2_MASK, VFWNMACC_VF }, // 2825
|
|
{ PseudoVFWNMACC_VFPR16_M4, VFWNMACC_VF }, // 2826
|
|
{ PseudoVFWNMACC_VFPR16_M4_MASK, VFWNMACC_VF }, // 2827
|
|
{ PseudoVFWNMACC_VFPR16_MF2, VFWNMACC_VF }, // 2828
|
|
{ PseudoVFWNMACC_VFPR16_MF2_MASK, VFWNMACC_VF }, // 2829
|
|
{ PseudoVFWNMACC_VFPR16_MF4, VFWNMACC_VF }, // 2830
|
|
{ PseudoVFWNMACC_VFPR16_MF4_MASK, VFWNMACC_VF }, // 2831
|
|
{ PseudoVFWNMACC_VFPR32_M1, VFWNMACC_VF }, // 2832
|
|
{ PseudoVFWNMACC_VFPR32_M1_MASK, VFWNMACC_VF }, // 2833
|
|
{ PseudoVFWNMACC_VFPR32_M2, VFWNMACC_VF }, // 2834
|
|
{ PseudoVFWNMACC_VFPR32_M2_MASK, VFWNMACC_VF }, // 2835
|
|
{ PseudoVFWNMACC_VFPR32_M4, VFWNMACC_VF }, // 2836
|
|
{ PseudoVFWNMACC_VFPR32_M4_MASK, VFWNMACC_VF }, // 2837
|
|
{ PseudoVFWNMACC_VFPR32_MF2, VFWNMACC_VF }, // 2838
|
|
{ PseudoVFWNMACC_VFPR32_MF2_MASK, VFWNMACC_VF }, // 2839
|
|
{ PseudoVFWNMACC_VV_M1, VFWNMACC_VV }, // 2840
|
|
{ PseudoVFWNMACC_VV_M1_MASK, VFWNMACC_VV }, // 2841
|
|
{ PseudoVFWNMACC_VV_M2, VFWNMACC_VV }, // 2842
|
|
{ PseudoVFWNMACC_VV_M2_MASK, VFWNMACC_VV }, // 2843
|
|
{ PseudoVFWNMACC_VV_M4, VFWNMACC_VV }, // 2844
|
|
{ PseudoVFWNMACC_VV_M4_MASK, VFWNMACC_VV }, // 2845
|
|
{ PseudoVFWNMACC_VV_MF2, VFWNMACC_VV }, // 2846
|
|
{ PseudoVFWNMACC_VV_MF2_MASK, VFWNMACC_VV }, // 2847
|
|
{ PseudoVFWNMACC_VV_MF4, VFWNMACC_VV }, // 2848
|
|
{ PseudoVFWNMACC_VV_MF4_MASK, VFWNMACC_VV }, // 2849
|
|
{ PseudoVFWNMSAC_VFPR16_M1, VFWNMSAC_VF }, // 2850
|
|
{ PseudoVFWNMSAC_VFPR16_M1_MASK, VFWNMSAC_VF }, // 2851
|
|
{ PseudoVFWNMSAC_VFPR16_M2, VFWNMSAC_VF }, // 2852
|
|
{ PseudoVFWNMSAC_VFPR16_M2_MASK, VFWNMSAC_VF }, // 2853
|
|
{ PseudoVFWNMSAC_VFPR16_M4, VFWNMSAC_VF }, // 2854
|
|
{ PseudoVFWNMSAC_VFPR16_M4_MASK, VFWNMSAC_VF }, // 2855
|
|
{ PseudoVFWNMSAC_VFPR16_MF2, VFWNMSAC_VF }, // 2856
|
|
{ PseudoVFWNMSAC_VFPR16_MF2_MASK, VFWNMSAC_VF }, // 2857
|
|
{ PseudoVFWNMSAC_VFPR16_MF4, VFWNMSAC_VF }, // 2858
|
|
{ PseudoVFWNMSAC_VFPR16_MF4_MASK, VFWNMSAC_VF }, // 2859
|
|
{ PseudoVFWNMSAC_VFPR32_M1, VFWNMSAC_VF }, // 2860
|
|
{ PseudoVFWNMSAC_VFPR32_M1_MASK, VFWNMSAC_VF }, // 2861
|
|
{ PseudoVFWNMSAC_VFPR32_M2, VFWNMSAC_VF }, // 2862
|
|
{ PseudoVFWNMSAC_VFPR32_M2_MASK, VFWNMSAC_VF }, // 2863
|
|
{ PseudoVFWNMSAC_VFPR32_M4, VFWNMSAC_VF }, // 2864
|
|
{ PseudoVFWNMSAC_VFPR32_M4_MASK, VFWNMSAC_VF }, // 2865
|
|
{ PseudoVFWNMSAC_VFPR32_MF2, VFWNMSAC_VF }, // 2866
|
|
{ PseudoVFWNMSAC_VFPR32_MF2_MASK, VFWNMSAC_VF }, // 2867
|
|
{ PseudoVFWNMSAC_VV_M1, VFWNMSAC_VV }, // 2868
|
|
{ PseudoVFWNMSAC_VV_M1_MASK, VFWNMSAC_VV }, // 2869
|
|
{ PseudoVFWNMSAC_VV_M2, VFWNMSAC_VV }, // 2870
|
|
{ PseudoVFWNMSAC_VV_M2_MASK, VFWNMSAC_VV }, // 2871
|
|
{ PseudoVFWNMSAC_VV_M4, VFWNMSAC_VV }, // 2872
|
|
{ PseudoVFWNMSAC_VV_M4_MASK, VFWNMSAC_VV }, // 2873
|
|
{ PseudoVFWNMSAC_VV_MF2, VFWNMSAC_VV }, // 2874
|
|
{ PseudoVFWNMSAC_VV_MF2_MASK, VFWNMSAC_VV }, // 2875
|
|
{ PseudoVFWNMSAC_VV_MF4, VFWNMSAC_VV }, // 2876
|
|
{ PseudoVFWNMSAC_VV_MF4_MASK, VFWNMSAC_VV }, // 2877
|
|
{ PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS }, // 2878
|
|
{ PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS }, // 2879
|
|
{ PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS }, // 2880
|
|
{ PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS }, // 2881
|
|
{ PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS }, // 2882
|
|
{ PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS }, // 2883
|
|
{ PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS }, // 2884
|
|
{ PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS }, // 2885
|
|
{ PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS }, // 2886
|
|
{ PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS }, // 2887
|
|
{ PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS }, // 2888
|
|
{ PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS }, // 2889
|
|
{ PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS }, // 2890
|
|
{ PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS }, // 2891
|
|
{ PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS }, // 2892
|
|
{ PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS }, // 2893
|
|
{ PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS }, // 2894
|
|
{ PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS }, // 2895
|
|
{ PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS }, // 2896
|
|
{ PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS }, // 2897
|
|
{ PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS }, // 2898
|
|
{ PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS }, // 2899
|
|
{ PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS }, // 2900
|
|
{ PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS }, // 2901
|
|
{ PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS }, // 2902
|
|
{ PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS }, // 2903
|
|
{ PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS }, // 2904
|
|
{ PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS }, // 2905
|
|
{ PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS }, // 2906
|
|
{ PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS }, // 2907
|
|
{ PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS }, // 2908
|
|
{ PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS }, // 2909
|
|
{ PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS }, // 2910
|
|
{ PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS }, // 2911
|
|
{ PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS }, // 2912
|
|
{ PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS }, // 2913
|
|
{ PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS }, // 2914
|
|
{ PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS }, // 2915
|
|
{ PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS }, // 2916
|
|
{ PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS }, // 2917
|
|
{ PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS }, // 2918
|
|
{ PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS }, // 2919
|
|
{ PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS }, // 2920
|
|
{ PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS }, // 2921
|
|
{ PseudoVFWSUB_VFPR16_M1, VFWSUB_VF }, // 2922
|
|
{ PseudoVFWSUB_VFPR16_M1_MASK, VFWSUB_VF }, // 2923
|
|
{ PseudoVFWSUB_VFPR16_M2, VFWSUB_VF }, // 2924
|
|
{ PseudoVFWSUB_VFPR16_M2_MASK, VFWSUB_VF }, // 2925
|
|
{ PseudoVFWSUB_VFPR16_M4, VFWSUB_VF }, // 2926
|
|
{ PseudoVFWSUB_VFPR16_M4_MASK, VFWSUB_VF }, // 2927
|
|
{ PseudoVFWSUB_VFPR16_MF2, VFWSUB_VF }, // 2928
|
|
{ PseudoVFWSUB_VFPR16_MF2_MASK, VFWSUB_VF }, // 2929
|
|
{ PseudoVFWSUB_VFPR16_MF4, VFWSUB_VF }, // 2930
|
|
{ PseudoVFWSUB_VFPR16_MF4_MASK, VFWSUB_VF }, // 2931
|
|
{ PseudoVFWSUB_VFPR32_M1, VFWSUB_VF }, // 2932
|
|
{ PseudoVFWSUB_VFPR32_M1_MASK, VFWSUB_VF }, // 2933
|
|
{ PseudoVFWSUB_VFPR32_M2, VFWSUB_VF }, // 2934
|
|
{ PseudoVFWSUB_VFPR32_M2_MASK, VFWSUB_VF }, // 2935
|
|
{ PseudoVFWSUB_VFPR32_M4, VFWSUB_VF }, // 2936
|
|
{ PseudoVFWSUB_VFPR32_M4_MASK, VFWSUB_VF }, // 2937
|
|
{ PseudoVFWSUB_VFPR32_MF2, VFWSUB_VF }, // 2938
|
|
{ PseudoVFWSUB_VFPR32_MF2_MASK, VFWSUB_VF }, // 2939
|
|
{ PseudoVFWSUB_VV_M1, VFWSUB_VV }, // 2940
|
|
{ PseudoVFWSUB_VV_M1_MASK, VFWSUB_VV }, // 2941
|
|
{ PseudoVFWSUB_VV_M2, VFWSUB_VV }, // 2942
|
|
{ PseudoVFWSUB_VV_M2_MASK, VFWSUB_VV }, // 2943
|
|
{ PseudoVFWSUB_VV_M4, VFWSUB_VV }, // 2944
|
|
{ PseudoVFWSUB_VV_M4_MASK, VFWSUB_VV }, // 2945
|
|
{ PseudoVFWSUB_VV_MF2, VFWSUB_VV }, // 2946
|
|
{ PseudoVFWSUB_VV_MF2_MASK, VFWSUB_VV }, // 2947
|
|
{ PseudoVFWSUB_VV_MF4, VFWSUB_VV }, // 2948
|
|
{ PseudoVFWSUB_VV_MF4_MASK, VFWSUB_VV }, // 2949
|
|
{ PseudoVFWSUB_WFPR16_M1, VFWSUB_WF }, // 2950
|
|
{ PseudoVFWSUB_WFPR16_M1_MASK, VFWSUB_WF }, // 2951
|
|
{ PseudoVFWSUB_WFPR16_M2, VFWSUB_WF }, // 2952
|
|
{ PseudoVFWSUB_WFPR16_M2_MASK, VFWSUB_WF }, // 2953
|
|
{ PseudoVFWSUB_WFPR16_M4, VFWSUB_WF }, // 2954
|
|
{ PseudoVFWSUB_WFPR16_M4_MASK, VFWSUB_WF }, // 2955
|
|
{ PseudoVFWSUB_WFPR16_MF2, VFWSUB_WF }, // 2956
|
|
{ PseudoVFWSUB_WFPR16_MF2_MASK, VFWSUB_WF }, // 2957
|
|
{ PseudoVFWSUB_WFPR16_MF4, VFWSUB_WF }, // 2958
|
|
{ PseudoVFWSUB_WFPR16_MF4_MASK, VFWSUB_WF }, // 2959
|
|
{ PseudoVFWSUB_WFPR32_M1, VFWSUB_WF }, // 2960
|
|
{ PseudoVFWSUB_WFPR32_M1_MASK, VFWSUB_WF }, // 2961
|
|
{ PseudoVFWSUB_WFPR32_M2, VFWSUB_WF }, // 2962
|
|
{ PseudoVFWSUB_WFPR32_M2_MASK, VFWSUB_WF }, // 2963
|
|
{ PseudoVFWSUB_WFPR32_M4, VFWSUB_WF }, // 2964
|
|
{ PseudoVFWSUB_WFPR32_M4_MASK, VFWSUB_WF }, // 2965
|
|
{ PseudoVFWSUB_WFPR32_MF2, VFWSUB_WF }, // 2966
|
|
{ PseudoVFWSUB_WFPR32_MF2_MASK, VFWSUB_WF }, // 2967
|
|
{ PseudoVFWSUB_WV_M1, VFWSUB_WV }, // 2968
|
|
{ PseudoVFWSUB_WV_M1_MASK, VFWSUB_WV }, // 2969
|
|
{ PseudoVFWSUB_WV_M1_MASK_TIED, VFWSUB_WV }, // 2970
|
|
{ PseudoVFWSUB_WV_M1_TIED, VFWSUB_WV }, // 2971
|
|
{ PseudoVFWSUB_WV_M2, VFWSUB_WV }, // 2972
|
|
{ PseudoVFWSUB_WV_M2_MASK, VFWSUB_WV }, // 2973
|
|
{ PseudoVFWSUB_WV_M2_MASK_TIED, VFWSUB_WV }, // 2974
|
|
{ PseudoVFWSUB_WV_M2_TIED, VFWSUB_WV }, // 2975
|
|
{ PseudoVFWSUB_WV_M4, VFWSUB_WV }, // 2976
|
|
{ PseudoVFWSUB_WV_M4_MASK, VFWSUB_WV }, // 2977
|
|
{ PseudoVFWSUB_WV_M4_MASK_TIED, VFWSUB_WV }, // 2978
|
|
{ PseudoVFWSUB_WV_M4_TIED, VFWSUB_WV }, // 2979
|
|
{ PseudoVFWSUB_WV_MF2, VFWSUB_WV }, // 2980
|
|
{ PseudoVFWSUB_WV_MF2_MASK, VFWSUB_WV }, // 2981
|
|
{ PseudoVFWSUB_WV_MF2_MASK_TIED, VFWSUB_WV }, // 2982
|
|
{ PseudoVFWSUB_WV_MF2_TIED, VFWSUB_WV }, // 2983
|
|
{ PseudoVFWSUB_WV_MF4, VFWSUB_WV }, // 2984
|
|
{ PseudoVFWSUB_WV_MF4_MASK, VFWSUB_WV }, // 2985
|
|
{ PseudoVFWSUB_WV_MF4_MASK_TIED, VFWSUB_WV }, // 2986
|
|
{ PseudoVFWSUB_WV_MF4_TIED, VFWSUB_WV }, // 2987
|
|
{ PseudoVGHSH_VV_M1, VGHSH_VV }, // 2988
|
|
{ PseudoVGHSH_VV_M2, VGHSH_VV }, // 2989
|
|
{ PseudoVGHSH_VV_M4, VGHSH_VV }, // 2990
|
|
{ PseudoVGHSH_VV_M8, VGHSH_VV }, // 2991
|
|
{ PseudoVGHSH_VV_MF2, VGHSH_VV }, // 2992
|
|
{ PseudoVGMUL_VV_M1, VGMUL_VV }, // 2993
|
|
{ PseudoVGMUL_VV_M2, VGMUL_VV }, // 2994
|
|
{ PseudoVGMUL_VV_M4, VGMUL_VV }, // 2995
|
|
{ PseudoVGMUL_VV_M8, VGMUL_VV }, // 2996
|
|
{ PseudoVGMUL_VV_MF2, VGMUL_VV }, // 2997
|
|
{ PseudoVID_V_M1, VID_V }, // 2998
|
|
{ PseudoVID_V_M1_MASK, VID_V }, // 2999
|
|
{ PseudoVID_V_M2, VID_V }, // 3000
|
|
{ PseudoVID_V_M2_MASK, VID_V }, // 3001
|
|
{ PseudoVID_V_M4, VID_V }, // 3002
|
|
{ PseudoVID_V_M4_MASK, VID_V }, // 3003
|
|
{ PseudoVID_V_M8, VID_V }, // 3004
|
|
{ PseudoVID_V_M8_MASK, VID_V }, // 3005
|
|
{ PseudoVID_V_MF2, VID_V }, // 3006
|
|
{ PseudoVID_V_MF2_MASK, VID_V }, // 3007
|
|
{ PseudoVID_V_MF4, VID_V }, // 3008
|
|
{ PseudoVID_V_MF4_MASK, VID_V }, // 3009
|
|
{ PseudoVID_V_MF8, VID_V }, // 3010
|
|
{ PseudoVID_V_MF8_MASK, VID_V }, // 3011
|
|
{ PseudoVIOTA_M_M1, VIOTA_M }, // 3012
|
|
{ PseudoVIOTA_M_M1_MASK, VIOTA_M }, // 3013
|
|
{ PseudoVIOTA_M_M2, VIOTA_M }, // 3014
|
|
{ PseudoVIOTA_M_M2_MASK, VIOTA_M }, // 3015
|
|
{ PseudoVIOTA_M_M4, VIOTA_M }, // 3016
|
|
{ PseudoVIOTA_M_M4_MASK, VIOTA_M }, // 3017
|
|
{ PseudoVIOTA_M_M8, VIOTA_M }, // 3018
|
|
{ PseudoVIOTA_M_M8_MASK, VIOTA_M }, // 3019
|
|
{ PseudoVIOTA_M_MF2, VIOTA_M }, // 3020
|
|
{ PseudoVIOTA_M_MF2_MASK, VIOTA_M }, // 3021
|
|
{ PseudoVIOTA_M_MF4, VIOTA_M }, // 3022
|
|
{ PseudoVIOTA_M_MF4_MASK, VIOTA_M }, // 3023
|
|
{ PseudoVIOTA_M_MF8, VIOTA_M }, // 3024
|
|
{ PseudoVIOTA_M_MF8_MASK, VIOTA_M }, // 3025
|
|
{ PseudoVLE16FF_V_M1, VLE16FF_V }, // 3026
|
|
{ PseudoVLE16FF_V_M1_MASK, VLE16FF_V }, // 3027
|
|
{ PseudoVLE16FF_V_M2, VLE16FF_V }, // 3028
|
|
{ PseudoVLE16FF_V_M2_MASK, VLE16FF_V }, // 3029
|
|
{ PseudoVLE16FF_V_M4, VLE16FF_V }, // 3030
|
|
{ PseudoVLE16FF_V_M4_MASK, VLE16FF_V }, // 3031
|
|
{ PseudoVLE16FF_V_M8, VLE16FF_V }, // 3032
|
|
{ PseudoVLE16FF_V_M8_MASK, VLE16FF_V }, // 3033
|
|
{ PseudoVLE16FF_V_MF2, VLE16FF_V }, // 3034
|
|
{ PseudoVLE16FF_V_MF2_MASK, VLE16FF_V }, // 3035
|
|
{ PseudoVLE16FF_V_MF4, VLE16FF_V }, // 3036
|
|
{ PseudoVLE16FF_V_MF4_MASK, VLE16FF_V }, // 3037
|
|
{ PseudoVLE16_V_M1, VLE16_V }, // 3038
|
|
{ PseudoVLE16_V_M1_MASK, VLE16_V }, // 3039
|
|
{ PseudoVLE16_V_M2, VLE16_V }, // 3040
|
|
{ PseudoVLE16_V_M2_MASK, VLE16_V }, // 3041
|
|
{ PseudoVLE16_V_M4, VLE16_V }, // 3042
|
|
{ PseudoVLE16_V_M4_MASK, VLE16_V }, // 3043
|
|
{ PseudoVLE16_V_M8, VLE16_V }, // 3044
|
|
{ PseudoVLE16_V_M8_MASK, VLE16_V }, // 3045
|
|
{ PseudoVLE16_V_MF2, VLE16_V }, // 3046
|
|
{ PseudoVLE16_V_MF2_MASK, VLE16_V }, // 3047
|
|
{ PseudoVLE16_V_MF4, VLE16_V }, // 3048
|
|
{ PseudoVLE16_V_MF4_MASK, VLE16_V }, // 3049
|
|
{ PseudoVLE32FF_V_M1, VLE32FF_V }, // 3050
|
|
{ PseudoVLE32FF_V_M1_MASK, VLE32FF_V }, // 3051
|
|
{ PseudoVLE32FF_V_M2, VLE32FF_V }, // 3052
|
|
{ PseudoVLE32FF_V_M2_MASK, VLE32FF_V }, // 3053
|
|
{ PseudoVLE32FF_V_M4, VLE32FF_V }, // 3054
|
|
{ PseudoVLE32FF_V_M4_MASK, VLE32FF_V }, // 3055
|
|
{ PseudoVLE32FF_V_M8, VLE32FF_V }, // 3056
|
|
{ PseudoVLE32FF_V_M8_MASK, VLE32FF_V }, // 3057
|
|
{ PseudoVLE32FF_V_MF2, VLE32FF_V }, // 3058
|
|
{ PseudoVLE32FF_V_MF2_MASK, VLE32FF_V }, // 3059
|
|
{ PseudoVLE32_V_M1, VLE32_V }, // 3060
|
|
{ PseudoVLE32_V_M1_MASK, VLE32_V }, // 3061
|
|
{ PseudoVLE32_V_M2, VLE32_V }, // 3062
|
|
{ PseudoVLE32_V_M2_MASK, VLE32_V }, // 3063
|
|
{ PseudoVLE32_V_M4, VLE32_V }, // 3064
|
|
{ PseudoVLE32_V_M4_MASK, VLE32_V }, // 3065
|
|
{ PseudoVLE32_V_M8, VLE32_V }, // 3066
|
|
{ PseudoVLE32_V_M8_MASK, VLE32_V }, // 3067
|
|
{ PseudoVLE32_V_MF2, VLE32_V }, // 3068
|
|
{ PseudoVLE32_V_MF2_MASK, VLE32_V }, // 3069
|
|
{ PseudoVLE64FF_V_M1, VLE64FF_V }, // 3070
|
|
{ PseudoVLE64FF_V_M1_MASK, VLE64FF_V }, // 3071
|
|
{ PseudoVLE64FF_V_M2, VLE64FF_V }, // 3072
|
|
{ PseudoVLE64FF_V_M2_MASK, VLE64FF_V }, // 3073
|
|
{ PseudoVLE64FF_V_M4, VLE64FF_V }, // 3074
|
|
{ PseudoVLE64FF_V_M4_MASK, VLE64FF_V }, // 3075
|
|
{ PseudoVLE64FF_V_M8, VLE64FF_V }, // 3076
|
|
{ PseudoVLE64FF_V_M8_MASK, VLE64FF_V }, // 3077
|
|
{ PseudoVLE64_V_M1, VLE64_V }, // 3078
|
|
{ PseudoVLE64_V_M1_MASK, VLE64_V }, // 3079
|
|
{ PseudoVLE64_V_M2, VLE64_V }, // 3080
|
|
{ PseudoVLE64_V_M2_MASK, VLE64_V }, // 3081
|
|
{ PseudoVLE64_V_M4, VLE64_V }, // 3082
|
|
{ PseudoVLE64_V_M4_MASK, VLE64_V }, // 3083
|
|
{ PseudoVLE64_V_M8, VLE64_V }, // 3084
|
|
{ PseudoVLE64_V_M8_MASK, VLE64_V }, // 3085
|
|
{ PseudoVLE8FF_V_M1, VLE8FF_V }, // 3086
|
|
{ PseudoVLE8FF_V_M1_MASK, VLE8FF_V }, // 3087
|
|
{ PseudoVLE8FF_V_M2, VLE8FF_V }, // 3088
|
|
{ PseudoVLE8FF_V_M2_MASK, VLE8FF_V }, // 3089
|
|
{ PseudoVLE8FF_V_M4, VLE8FF_V }, // 3090
|
|
{ PseudoVLE8FF_V_M4_MASK, VLE8FF_V }, // 3091
|
|
{ PseudoVLE8FF_V_M8, VLE8FF_V }, // 3092
|
|
{ PseudoVLE8FF_V_M8_MASK, VLE8FF_V }, // 3093
|
|
{ PseudoVLE8FF_V_MF2, VLE8FF_V }, // 3094
|
|
{ PseudoVLE8FF_V_MF2_MASK, VLE8FF_V }, // 3095
|
|
{ PseudoVLE8FF_V_MF4, VLE8FF_V }, // 3096
|
|
{ PseudoVLE8FF_V_MF4_MASK, VLE8FF_V }, // 3097
|
|
{ PseudoVLE8FF_V_MF8, VLE8FF_V }, // 3098
|
|
{ PseudoVLE8FF_V_MF8_MASK, VLE8FF_V }, // 3099
|
|
{ PseudoVLE8_V_M1, VLE8_V }, // 3100
|
|
{ PseudoVLE8_V_M1_MASK, VLE8_V }, // 3101
|
|
{ PseudoVLE8_V_M2, VLE8_V }, // 3102
|
|
{ PseudoVLE8_V_M2_MASK, VLE8_V }, // 3103
|
|
{ PseudoVLE8_V_M4, VLE8_V }, // 3104
|
|
{ PseudoVLE8_V_M4_MASK, VLE8_V }, // 3105
|
|
{ PseudoVLE8_V_M8, VLE8_V }, // 3106
|
|
{ PseudoVLE8_V_M8_MASK, VLE8_V }, // 3107
|
|
{ PseudoVLE8_V_MF2, VLE8_V }, // 3108
|
|
{ PseudoVLE8_V_MF2_MASK, VLE8_V }, // 3109
|
|
{ PseudoVLE8_V_MF4, VLE8_V }, // 3110
|
|
{ PseudoVLE8_V_MF4_MASK, VLE8_V }, // 3111
|
|
{ PseudoVLE8_V_MF8, VLE8_V }, // 3112
|
|
{ PseudoVLE8_V_MF8_MASK, VLE8_V }, // 3113
|
|
{ PseudoVLM_V_B1, VLM_V }, // 3114
|
|
{ PseudoVLM_V_B16, VLM_V }, // 3115
|
|
{ PseudoVLM_V_B2, VLM_V }, // 3116
|
|
{ PseudoVLM_V_B32, VLM_V }, // 3117
|
|
{ PseudoVLM_V_B4, VLM_V }, // 3118
|
|
{ PseudoVLM_V_B64, VLM_V }, // 3119
|
|
{ PseudoVLM_V_B8, VLM_V }, // 3120
|
|
{ PseudoVLOXEI16_V_M1_M1, VLOXEI16_V }, // 3121
|
|
{ PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V }, // 3122
|
|
{ PseudoVLOXEI16_V_M1_M2, VLOXEI16_V }, // 3123
|
|
{ PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V }, // 3124
|
|
{ PseudoVLOXEI16_V_M1_M4, VLOXEI16_V }, // 3125
|
|
{ PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V }, // 3126
|
|
{ PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V }, // 3127
|
|
{ PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V }, // 3128
|
|
{ PseudoVLOXEI16_V_M2_M1, VLOXEI16_V }, // 3129
|
|
{ PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V }, // 3130
|
|
{ PseudoVLOXEI16_V_M2_M2, VLOXEI16_V }, // 3131
|
|
{ PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V }, // 3132
|
|
{ PseudoVLOXEI16_V_M2_M4, VLOXEI16_V }, // 3133
|
|
{ PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V }, // 3134
|
|
{ PseudoVLOXEI16_V_M2_M8, VLOXEI16_V }, // 3135
|
|
{ PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V }, // 3136
|
|
{ PseudoVLOXEI16_V_M4_M2, VLOXEI16_V }, // 3137
|
|
{ PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V }, // 3138
|
|
{ PseudoVLOXEI16_V_M4_M4, VLOXEI16_V }, // 3139
|
|
{ PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V }, // 3140
|
|
{ PseudoVLOXEI16_V_M4_M8, VLOXEI16_V }, // 3141
|
|
{ PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V }, // 3142
|
|
{ PseudoVLOXEI16_V_M8_M4, VLOXEI16_V }, // 3143
|
|
{ PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V }, // 3144
|
|
{ PseudoVLOXEI16_V_M8_M8, VLOXEI16_V }, // 3145
|
|
{ PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V }, // 3146
|
|
{ PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V }, // 3147
|
|
{ PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V }, // 3148
|
|
{ PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V }, // 3149
|
|
{ PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V }, // 3150
|
|
{ PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V }, // 3151
|
|
{ PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V }, // 3152
|
|
{ PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V }, // 3153
|
|
{ PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V }, // 3154
|
|
{ PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V }, // 3155
|
|
{ PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V }, // 3156
|
|
{ PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V }, // 3157
|
|
{ PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V }, // 3158
|
|
{ PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V }, // 3159
|
|
{ PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V }, // 3160
|
|
{ PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V }, // 3161
|
|
{ PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V }, // 3162
|
|
{ PseudoVLOXEI32_V_M1_M1, VLOXEI32_V }, // 3163
|
|
{ PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V }, // 3164
|
|
{ PseudoVLOXEI32_V_M1_M2, VLOXEI32_V }, // 3165
|
|
{ PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V }, // 3166
|
|
{ PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V }, // 3167
|
|
{ PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V }, // 3168
|
|
{ PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V }, // 3169
|
|
{ PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V }, // 3170
|
|
{ PseudoVLOXEI32_V_M2_M1, VLOXEI32_V }, // 3171
|
|
{ PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V }, // 3172
|
|
{ PseudoVLOXEI32_V_M2_M2, VLOXEI32_V }, // 3173
|
|
{ PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V }, // 3174
|
|
{ PseudoVLOXEI32_V_M2_M4, VLOXEI32_V }, // 3175
|
|
{ PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V }, // 3176
|
|
{ PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V }, // 3177
|
|
{ PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V }, // 3178
|
|
{ PseudoVLOXEI32_V_M4_M1, VLOXEI32_V }, // 3179
|
|
{ PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V }, // 3180
|
|
{ PseudoVLOXEI32_V_M4_M2, VLOXEI32_V }, // 3181
|
|
{ PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V }, // 3182
|
|
{ PseudoVLOXEI32_V_M4_M4, VLOXEI32_V }, // 3183
|
|
{ PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V }, // 3184
|
|
{ PseudoVLOXEI32_V_M4_M8, VLOXEI32_V }, // 3185
|
|
{ PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V }, // 3186
|
|
{ PseudoVLOXEI32_V_M8_M2, VLOXEI32_V }, // 3187
|
|
{ PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V }, // 3188
|
|
{ PseudoVLOXEI32_V_M8_M4, VLOXEI32_V }, // 3189
|
|
{ PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V }, // 3190
|
|
{ PseudoVLOXEI32_V_M8_M8, VLOXEI32_V }, // 3191
|
|
{ PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V }, // 3192
|
|
{ PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V }, // 3193
|
|
{ PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V }, // 3194
|
|
{ PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V }, // 3195
|
|
{ PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V }, // 3196
|
|
{ PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V }, // 3197
|
|
{ PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V }, // 3198
|
|
{ PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V }, // 3199
|
|
{ PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V }, // 3200
|
|
{ PseudoVLOXEI64_V_M1_M1, VLOXEI64_V }, // 3201
|
|
{ PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V }, // 3202
|
|
{ PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V }, // 3203
|
|
{ PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V }, // 3204
|
|
{ PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V }, // 3205
|
|
{ PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V }, // 3206
|
|
{ PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V }, // 3207
|
|
{ PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V }, // 3208
|
|
{ PseudoVLOXEI64_V_M2_M1, VLOXEI64_V }, // 3209
|
|
{ PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V }, // 3210
|
|
{ PseudoVLOXEI64_V_M2_M2, VLOXEI64_V }, // 3211
|
|
{ PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V }, // 3212
|
|
{ PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V }, // 3213
|
|
{ PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V }, // 3214
|
|
{ PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V }, // 3215
|
|
{ PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V }, // 3216
|
|
{ PseudoVLOXEI64_V_M4_M1, VLOXEI64_V }, // 3217
|
|
{ PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V }, // 3218
|
|
{ PseudoVLOXEI64_V_M4_M2, VLOXEI64_V }, // 3219
|
|
{ PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V }, // 3220
|
|
{ PseudoVLOXEI64_V_M4_M4, VLOXEI64_V }, // 3221
|
|
{ PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V }, // 3222
|
|
{ PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V }, // 3223
|
|
{ PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V }, // 3224
|
|
{ PseudoVLOXEI64_V_M8_M1, VLOXEI64_V }, // 3225
|
|
{ PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V }, // 3226
|
|
{ PseudoVLOXEI64_V_M8_M2, VLOXEI64_V }, // 3227
|
|
{ PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V }, // 3228
|
|
{ PseudoVLOXEI64_V_M8_M4, VLOXEI64_V }, // 3229
|
|
{ PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V }, // 3230
|
|
{ PseudoVLOXEI64_V_M8_M8, VLOXEI64_V }, // 3231
|
|
{ PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V }, // 3232
|
|
{ PseudoVLOXEI8_V_M1_M1, VLOXEI8_V }, // 3233
|
|
{ PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V }, // 3234
|
|
{ PseudoVLOXEI8_V_M1_M2, VLOXEI8_V }, // 3235
|
|
{ PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V }, // 3236
|
|
{ PseudoVLOXEI8_V_M1_M4, VLOXEI8_V }, // 3237
|
|
{ PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V }, // 3238
|
|
{ PseudoVLOXEI8_V_M1_M8, VLOXEI8_V }, // 3239
|
|
{ PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V }, // 3240
|
|
{ PseudoVLOXEI8_V_M2_M2, VLOXEI8_V }, // 3241
|
|
{ PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V }, // 3242
|
|
{ PseudoVLOXEI8_V_M2_M4, VLOXEI8_V }, // 3243
|
|
{ PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V }, // 3244
|
|
{ PseudoVLOXEI8_V_M2_M8, VLOXEI8_V }, // 3245
|
|
{ PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V }, // 3246
|
|
{ PseudoVLOXEI8_V_M4_M4, VLOXEI8_V }, // 3247
|
|
{ PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V }, // 3248
|
|
{ PseudoVLOXEI8_V_M4_M8, VLOXEI8_V }, // 3249
|
|
{ PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V }, // 3250
|
|
{ PseudoVLOXEI8_V_M8_M8, VLOXEI8_V }, // 3251
|
|
{ PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V }, // 3252
|
|
{ PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V }, // 3253
|
|
{ PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V }, // 3254
|
|
{ PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V }, // 3255
|
|
{ PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V }, // 3256
|
|
{ PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V }, // 3257
|
|
{ PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V }, // 3258
|
|
{ PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V }, // 3259
|
|
{ PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V }, // 3260
|
|
{ PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V }, // 3261
|
|
{ PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V }, // 3262
|
|
{ PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V }, // 3263
|
|
{ PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V }, // 3264
|
|
{ PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V }, // 3265
|
|
{ PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V }, // 3266
|
|
{ PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V }, // 3267
|
|
{ PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V }, // 3268
|
|
{ PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V }, // 3269
|
|
{ PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V }, // 3270
|
|
{ PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V }, // 3271
|
|
{ PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V }, // 3272
|
|
{ PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V }, // 3273
|
|
{ PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V }, // 3274
|
|
{ PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V }, // 3275
|
|
{ PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V }, // 3276
|
|
{ PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V }, // 3277
|
|
{ PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V }, // 3278
|
|
{ PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V }, // 3279
|
|
{ PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V }, // 3280
|
|
{ PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V }, // 3281
|
|
{ PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V }, // 3282
|
|
{ PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V }, // 3283
|
|
{ PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V }, // 3284
|
|
{ PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V }, // 3285
|
|
{ PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V }, // 3286
|
|
{ PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V }, // 3287
|
|
{ PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V }, // 3288
|
|
{ PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V }, // 3289
|
|
{ PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V }, // 3290
|
|
{ PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V }, // 3291
|
|
{ PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V }, // 3292
|
|
{ PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V }, // 3293
|
|
{ PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V }, // 3294
|
|
{ PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V }, // 3295
|
|
{ PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V }, // 3296
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V }, // 3297
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V }, // 3298
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V }, // 3299
|
|
{ PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V }, // 3300
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V }, // 3301
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V }, // 3302
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V }, // 3303
|
|
{ PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V }, // 3304
|
|
{ PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V }, // 3305
|
|
{ PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V }, // 3306
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V }, // 3307
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V }, // 3308
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V }, // 3309
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V }, // 3310
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V }, // 3311
|
|
{ PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V }, // 3312
|
|
{ PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V }, // 3313
|
|
{ PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V }, // 3314
|
|
{ PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V }, // 3315
|
|
{ PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V }, // 3316
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V }, // 3317
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V }, // 3318
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V }, // 3319
|
|
{ PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V }, // 3320
|
|
{ PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V }, // 3321
|
|
{ PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V }, // 3322
|
|
{ PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V }, // 3323
|
|
{ PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V }, // 3324
|
|
{ PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V }, // 3325
|
|
{ PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V }, // 3326
|
|
{ PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V }, // 3327
|
|
{ PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V }, // 3328
|
|
{ PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V }, // 3329
|
|
{ PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V }, // 3330
|
|
{ PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V }, // 3331
|
|
{ PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V }, // 3332
|
|
{ PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V }, // 3333
|
|
{ PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V }, // 3334
|
|
{ PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V }, // 3335
|
|
{ PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V }, // 3336
|
|
{ PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V }, // 3337
|
|
{ PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V }, // 3338
|
|
{ PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V }, // 3339
|
|
{ PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V }, // 3340
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V }, // 3341
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V }, // 3342
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V }, // 3343
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V }, // 3344
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V }, // 3345
|
|
{ PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V }, // 3346
|
|
{ PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V }, // 3347
|
|
{ PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V }, // 3348
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V }, // 3349
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V }, // 3350
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V }, // 3351
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V }, // 3352
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V }, // 3353
|
|
{ PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V }, // 3354
|
|
{ PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V }, // 3355
|
|
{ PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V }, // 3356
|
|
{ PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V }, // 3357
|
|
{ PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V }, // 3358
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V }, // 3359
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V }, // 3360
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V }, // 3361
|
|
{ PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V }, // 3362
|
|
{ PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V }, // 3363
|
|
{ PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V }, // 3364
|
|
{ PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V }, // 3365
|
|
{ PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V }, // 3366
|
|
{ PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V }, // 3367
|
|
{ PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V }, // 3368
|
|
{ PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V }, // 3369
|
|
{ PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V }, // 3370
|
|
{ PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V }, // 3371
|
|
{ PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V }, // 3372
|
|
{ PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V }, // 3373
|
|
{ PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V }, // 3374
|
|
{ PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V }, // 3375
|
|
{ PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V }, // 3376
|
|
{ PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V }, // 3377
|
|
{ PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V }, // 3378
|
|
{ PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V }, // 3379
|
|
{ PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V }, // 3380
|
|
{ PseudoVLOXSEG2EI8_V_M1_M4, VLOXSEG2EI8_V }, // 3381
|
|
{ PseudoVLOXSEG2EI8_V_M1_M4_MASK, VLOXSEG2EI8_V }, // 3382
|
|
{ PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V }, // 3383
|
|
{ PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V }, // 3384
|
|
{ PseudoVLOXSEG2EI8_V_M2_M4, VLOXSEG2EI8_V }, // 3385
|
|
{ PseudoVLOXSEG2EI8_V_M2_M4_MASK, VLOXSEG2EI8_V }, // 3386
|
|
{ PseudoVLOXSEG2EI8_V_M4_M4, VLOXSEG2EI8_V }, // 3387
|
|
{ PseudoVLOXSEG2EI8_V_M4_M4_MASK, VLOXSEG2EI8_V }, // 3388
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V }, // 3389
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V }, // 3390
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V }, // 3391
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V }, // 3392
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M4, VLOXSEG2EI8_V }, // 3393
|
|
{ PseudoVLOXSEG2EI8_V_MF2_M4_MASK, VLOXSEG2EI8_V }, // 3394
|
|
{ PseudoVLOXSEG2EI8_V_MF2_MF2, VLOXSEG2EI8_V }, // 3395
|
|
{ PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, VLOXSEG2EI8_V }, // 3396
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V }, // 3397
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V }, // 3398
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V }, // 3399
|
|
{ PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V }, // 3400
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF2, VLOXSEG2EI8_V }, // 3401
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, VLOXSEG2EI8_V }, // 3402
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF4, VLOXSEG2EI8_V }, // 3403
|
|
{ PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, VLOXSEG2EI8_V }, // 3404
|
|
{ PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V }, // 3405
|
|
{ PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V }, // 3406
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF2, VLOXSEG2EI8_V }, // 3407
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, VLOXSEG2EI8_V }, // 3408
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF4, VLOXSEG2EI8_V }, // 3409
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, VLOXSEG2EI8_V }, // 3410
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF8, VLOXSEG2EI8_V }, // 3411
|
|
{ PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, VLOXSEG2EI8_V }, // 3412
|
|
{ PseudoVLOXSEG3EI16_V_M1_M1, VLOXSEG3EI16_V }, // 3413
|
|
{ PseudoVLOXSEG3EI16_V_M1_M1_MASK, VLOXSEG3EI16_V }, // 3414
|
|
{ PseudoVLOXSEG3EI16_V_M1_M2, VLOXSEG3EI16_V }, // 3415
|
|
{ PseudoVLOXSEG3EI16_V_M1_M2_MASK, VLOXSEG3EI16_V }, // 3416
|
|
{ PseudoVLOXSEG3EI16_V_M1_MF2, VLOXSEG3EI16_V }, // 3417
|
|
{ PseudoVLOXSEG3EI16_V_M1_MF2_MASK, VLOXSEG3EI16_V }, // 3418
|
|
{ PseudoVLOXSEG3EI16_V_M2_M1, VLOXSEG3EI16_V }, // 3419
|
|
{ PseudoVLOXSEG3EI16_V_M2_M1_MASK, VLOXSEG3EI16_V }, // 3420
|
|
{ PseudoVLOXSEG3EI16_V_M2_M2, VLOXSEG3EI16_V }, // 3421
|
|
{ PseudoVLOXSEG3EI16_V_M2_M2_MASK, VLOXSEG3EI16_V }, // 3422
|
|
{ PseudoVLOXSEG3EI16_V_M4_M2, VLOXSEG3EI16_V }, // 3423
|
|
{ PseudoVLOXSEG3EI16_V_M4_M2_MASK, VLOXSEG3EI16_V }, // 3424
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M1, VLOXSEG3EI16_V }, // 3425
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M1_MASK, VLOXSEG3EI16_V }, // 3426
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M2, VLOXSEG3EI16_V }, // 3427
|
|
{ PseudoVLOXSEG3EI16_V_MF2_M2_MASK, VLOXSEG3EI16_V }, // 3428
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF2, VLOXSEG3EI16_V }, // 3429
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, VLOXSEG3EI16_V }, // 3430
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF4, VLOXSEG3EI16_V }, // 3431
|
|
{ PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, VLOXSEG3EI16_V }, // 3432
|
|
{ PseudoVLOXSEG3EI16_V_MF4_M1, VLOXSEG3EI16_V }, // 3433
|
|
{ PseudoVLOXSEG3EI16_V_MF4_M1_MASK, VLOXSEG3EI16_V }, // 3434
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF2, VLOXSEG3EI16_V }, // 3435
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, VLOXSEG3EI16_V }, // 3436
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF4, VLOXSEG3EI16_V }, // 3437
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, VLOXSEG3EI16_V }, // 3438
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF8, VLOXSEG3EI16_V }, // 3439
|
|
{ PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, VLOXSEG3EI16_V }, // 3440
|
|
{ PseudoVLOXSEG3EI32_V_M1_M1, VLOXSEG3EI32_V }, // 3441
|
|
{ PseudoVLOXSEG3EI32_V_M1_M1_MASK, VLOXSEG3EI32_V }, // 3442
|
|
{ PseudoVLOXSEG3EI32_V_M1_M2, VLOXSEG3EI32_V }, // 3443
|
|
{ PseudoVLOXSEG3EI32_V_M1_M2_MASK, VLOXSEG3EI32_V }, // 3444
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF2, VLOXSEG3EI32_V }, // 3445
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF2_MASK, VLOXSEG3EI32_V }, // 3446
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF4, VLOXSEG3EI32_V }, // 3447
|
|
{ PseudoVLOXSEG3EI32_V_M1_MF4_MASK, VLOXSEG3EI32_V }, // 3448
|
|
{ PseudoVLOXSEG3EI32_V_M2_M1, VLOXSEG3EI32_V }, // 3449
|
|
{ PseudoVLOXSEG3EI32_V_M2_M1_MASK, VLOXSEG3EI32_V }, // 3450
|
|
{ PseudoVLOXSEG3EI32_V_M2_M2, VLOXSEG3EI32_V }, // 3451
|
|
{ PseudoVLOXSEG3EI32_V_M2_M2_MASK, VLOXSEG3EI32_V }, // 3452
|
|
{ PseudoVLOXSEG3EI32_V_M2_MF2, VLOXSEG3EI32_V }, // 3453
|
|
{ PseudoVLOXSEG3EI32_V_M2_MF2_MASK, VLOXSEG3EI32_V }, // 3454
|
|
{ PseudoVLOXSEG3EI32_V_M4_M1, VLOXSEG3EI32_V }, // 3455
|
|
{ PseudoVLOXSEG3EI32_V_M4_M1_MASK, VLOXSEG3EI32_V }, // 3456
|
|
{ PseudoVLOXSEG3EI32_V_M4_M2, VLOXSEG3EI32_V }, // 3457
|
|
{ PseudoVLOXSEG3EI32_V_M4_M2_MASK, VLOXSEG3EI32_V }, // 3458
|
|
{ PseudoVLOXSEG3EI32_V_M8_M2, VLOXSEG3EI32_V }, // 3459
|
|
{ PseudoVLOXSEG3EI32_V_M8_M2_MASK, VLOXSEG3EI32_V }, // 3460
|
|
{ PseudoVLOXSEG3EI32_V_MF2_M1, VLOXSEG3EI32_V }, // 3461
|
|
{ PseudoVLOXSEG3EI32_V_MF2_M1_MASK, VLOXSEG3EI32_V }, // 3462
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF2, VLOXSEG3EI32_V }, // 3463
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, VLOXSEG3EI32_V }, // 3464
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF4, VLOXSEG3EI32_V }, // 3465
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, VLOXSEG3EI32_V }, // 3466
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF8, VLOXSEG3EI32_V }, // 3467
|
|
{ PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, VLOXSEG3EI32_V }, // 3468
|
|
{ PseudoVLOXSEG3EI64_V_M1_M1, VLOXSEG3EI64_V }, // 3469
|
|
{ PseudoVLOXSEG3EI64_V_M1_M1_MASK, VLOXSEG3EI64_V }, // 3470
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF2, VLOXSEG3EI64_V }, // 3471
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF2_MASK, VLOXSEG3EI64_V }, // 3472
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF4, VLOXSEG3EI64_V }, // 3473
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF4_MASK, VLOXSEG3EI64_V }, // 3474
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF8, VLOXSEG3EI64_V }, // 3475
|
|
{ PseudoVLOXSEG3EI64_V_M1_MF8_MASK, VLOXSEG3EI64_V }, // 3476
|
|
{ PseudoVLOXSEG3EI64_V_M2_M1, VLOXSEG3EI64_V }, // 3477
|
|
{ PseudoVLOXSEG3EI64_V_M2_M1_MASK, VLOXSEG3EI64_V }, // 3478
|
|
{ PseudoVLOXSEG3EI64_V_M2_M2, VLOXSEG3EI64_V }, // 3479
|
|
{ PseudoVLOXSEG3EI64_V_M2_M2_MASK, VLOXSEG3EI64_V }, // 3480
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF2, VLOXSEG3EI64_V }, // 3481
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF2_MASK, VLOXSEG3EI64_V }, // 3482
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF4, VLOXSEG3EI64_V }, // 3483
|
|
{ PseudoVLOXSEG3EI64_V_M2_MF4_MASK, VLOXSEG3EI64_V }, // 3484
|
|
{ PseudoVLOXSEG3EI64_V_M4_M1, VLOXSEG3EI64_V }, // 3485
|
|
{ PseudoVLOXSEG3EI64_V_M4_M1_MASK, VLOXSEG3EI64_V }, // 3486
|
|
{ PseudoVLOXSEG3EI64_V_M4_M2, VLOXSEG3EI64_V }, // 3487
|
|
{ PseudoVLOXSEG3EI64_V_M4_M2_MASK, VLOXSEG3EI64_V }, // 3488
|
|
{ PseudoVLOXSEG3EI64_V_M4_MF2, VLOXSEG3EI64_V }, // 3489
|
|
{ PseudoVLOXSEG3EI64_V_M4_MF2_MASK, VLOXSEG3EI64_V }, // 3490
|
|
{ PseudoVLOXSEG3EI64_V_M8_M1, VLOXSEG3EI64_V }, // 3491
|
|
{ PseudoVLOXSEG3EI64_V_M8_M1_MASK, VLOXSEG3EI64_V }, // 3492
|
|
{ PseudoVLOXSEG3EI64_V_M8_M2, VLOXSEG3EI64_V }, // 3493
|
|
{ PseudoVLOXSEG3EI64_V_M8_M2_MASK, VLOXSEG3EI64_V }, // 3494
|
|
{ PseudoVLOXSEG3EI8_V_M1_M1, VLOXSEG3EI8_V }, // 3495
|
|
{ PseudoVLOXSEG3EI8_V_M1_M1_MASK, VLOXSEG3EI8_V }, // 3496
|
|
{ PseudoVLOXSEG3EI8_V_M1_M2, VLOXSEG3EI8_V }, // 3497
|
|
{ PseudoVLOXSEG3EI8_V_M1_M2_MASK, VLOXSEG3EI8_V }, // 3498
|
|
{ PseudoVLOXSEG3EI8_V_M2_M2, VLOXSEG3EI8_V }, // 3499
|
|
{ PseudoVLOXSEG3EI8_V_M2_M2_MASK, VLOXSEG3EI8_V }, // 3500
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M1, VLOXSEG3EI8_V }, // 3501
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M1_MASK, VLOXSEG3EI8_V }, // 3502
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M2, VLOXSEG3EI8_V }, // 3503
|
|
{ PseudoVLOXSEG3EI8_V_MF2_M2_MASK, VLOXSEG3EI8_V }, // 3504
|
|
{ PseudoVLOXSEG3EI8_V_MF2_MF2, VLOXSEG3EI8_V }, // 3505
|
|
{ PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, VLOXSEG3EI8_V }, // 3506
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M1, VLOXSEG3EI8_V }, // 3507
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M1_MASK, VLOXSEG3EI8_V }, // 3508
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M2, VLOXSEG3EI8_V }, // 3509
|
|
{ PseudoVLOXSEG3EI8_V_MF4_M2_MASK, VLOXSEG3EI8_V }, // 3510
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF2, VLOXSEG3EI8_V }, // 3511
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, VLOXSEG3EI8_V }, // 3512
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF4, VLOXSEG3EI8_V }, // 3513
|
|
{ PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, VLOXSEG3EI8_V }, // 3514
|
|
{ PseudoVLOXSEG3EI8_V_MF8_M1, VLOXSEG3EI8_V }, // 3515
|
|
{ PseudoVLOXSEG3EI8_V_MF8_M1_MASK, VLOXSEG3EI8_V }, // 3516
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF2, VLOXSEG3EI8_V }, // 3517
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, VLOXSEG3EI8_V }, // 3518
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF4, VLOXSEG3EI8_V }, // 3519
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, VLOXSEG3EI8_V }, // 3520
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF8, VLOXSEG3EI8_V }, // 3521
|
|
{ PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, VLOXSEG3EI8_V }, // 3522
|
|
{ PseudoVLOXSEG4EI16_V_M1_M1, VLOXSEG4EI16_V }, // 3523
|
|
{ PseudoVLOXSEG4EI16_V_M1_M1_MASK, VLOXSEG4EI16_V }, // 3524
|
|
{ PseudoVLOXSEG4EI16_V_M1_M2, VLOXSEG4EI16_V }, // 3525
|
|
{ PseudoVLOXSEG4EI16_V_M1_M2_MASK, VLOXSEG4EI16_V }, // 3526
|
|
{ PseudoVLOXSEG4EI16_V_M1_MF2, VLOXSEG4EI16_V }, // 3527
|
|
{ PseudoVLOXSEG4EI16_V_M1_MF2_MASK, VLOXSEG4EI16_V }, // 3528
|
|
{ PseudoVLOXSEG4EI16_V_M2_M1, VLOXSEG4EI16_V }, // 3529
|
|
{ PseudoVLOXSEG4EI16_V_M2_M1_MASK, VLOXSEG4EI16_V }, // 3530
|
|
{ PseudoVLOXSEG4EI16_V_M2_M2, VLOXSEG4EI16_V }, // 3531
|
|
{ PseudoVLOXSEG4EI16_V_M2_M2_MASK, VLOXSEG4EI16_V }, // 3532
|
|
{ PseudoVLOXSEG4EI16_V_M4_M2, VLOXSEG4EI16_V }, // 3533
|
|
{ PseudoVLOXSEG4EI16_V_M4_M2_MASK, VLOXSEG4EI16_V }, // 3534
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M1, VLOXSEG4EI16_V }, // 3535
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M1_MASK, VLOXSEG4EI16_V }, // 3536
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M2, VLOXSEG4EI16_V }, // 3537
|
|
{ PseudoVLOXSEG4EI16_V_MF2_M2_MASK, VLOXSEG4EI16_V }, // 3538
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF2, VLOXSEG4EI16_V }, // 3539
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, VLOXSEG4EI16_V }, // 3540
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF4, VLOXSEG4EI16_V }, // 3541
|
|
{ PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, VLOXSEG4EI16_V }, // 3542
|
|
{ PseudoVLOXSEG4EI16_V_MF4_M1, VLOXSEG4EI16_V }, // 3543
|
|
{ PseudoVLOXSEG4EI16_V_MF4_M1_MASK, VLOXSEG4EI16_V }, // 3544
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF2, VLOXSEG4EI16_V }, // 3545
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, VLOXSEG4EI16_V }, // 3546
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF4, VLOXSEG4EI16_V }, // 3547
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, VLOXSEG4EI16_V }, // 3548
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF8, VLOXSEG4EI16_V }, // 3549
|
|
{ PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, VLOXSEG4EI16_V }, // 3550
|
|
{ PseudoVLOXSEG4EI32_V_M1_M1, VLOXSEG4EI32_V }, // 3551
|
|
{ PseudoVLOXSEG4EI32_V_M1_M1_MASK, VLOXSEG4EI32_V }, // 3552
|
|
{ PseudoVLOXSEG4EI32_V_M1_M2, VLOXSEG4EI32_V }, // 3553
|
|
{ PseudoVLOXSEG4EI32_V_M1_M2_MASK, VLOXSEG4EI32_V }, // 3554
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF2, VLOXSEG4EI32_V }, // 3555
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF2_MASK, VLOXSEG4EI32_V }, // 3556
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF4, VLOXSEG4EI32_V }, // 3557
|
|
{ PseudoVLOXSEG4EI32_V_M1_MF4_MASK, VLOXSEG4EI32_V }, // 3558
|
|
{ PseudoVLOXSEG4EI32_V_M2_M1, VLOXSEG4EI32_V }, // 3559
|
|
{ PseudoVLOXSEG4EI32_V_M2_M1_MASK, VLOXSEG4EI32_V }, // 3560
|
|
{ PseudoVLOXSEG4EI32_V_M2_M2, VLOXSEG4EI32_V }, // 3561
|
|
{ PseudoVLOXSEG4EI32_V_M2_M2_MASK, VLOXSEG4EI32_V }, // 3562
|
|
{ PseudoVLOXSEG4EI32_V_M2_MF2, VLOXSEG4EI32_V }, // 3563
|
|
{ PseudoVLOXSEG4EI32_V_M2_MF2_MASK, VLOXSEG4EI32_V }, // 3564
|
|
{ PseudoVLOXSEG4EI32_V_M4_M1, VLOXSEG4EI32_V }, // 3565
|
|
{ PseudoVLOXSEG4EI32_V_M4_M1_MASK, VLOXSEG4EI32_V }, // 3566
|
|
{ PseudoVLOXSEG4EI32_V_M4_M2, VLOXSEG4EI32_V }, // 3567
|
|
{ PseudoVLOXSEG4EI32_V_M4_M2_MASK, VLOXSEG4EI32_V }, // 3568
|
|
{ PseudoVLOXSEG4EI32_V_M8_M2, VLOXSEG4EI32_V }, // 3569
|
|
{ PseudoVLOXSEG4EI32_V_M8_M2_MASK, VLOXSEG4EI32_V }, // 3570
|
|
{ PseudoVLOXSEG4EI32_V_MF2_M1, VLOXSEG4EI32_V }, // 3571
|
|
{ PseudoVLOXSEG4EI32_V_MF2_M1_MASK, VLOXSEG4EI32_V }, // 3572
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF2, VLOXSEG4EI32_V }, // 3573
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, VLOXSEG4EI32_V }, // 3574
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF4, VLOXSEG4EI32_V }, // 3575
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, VLOXSEG4EI32_V }, // 3576
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF8, VLOXSEG4EI32_V }, // 3577
|
|
{ PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, VLOXSEG4EI32_V }, // 3578
|
|
{ PseudoVLOXSEG4EI64_V_M1_M1, VLOXSEG4EI64_V }, // 3579
|
|
{ PseudoVLOXSEG4EI64_V_M1_M1_MASK, VLOXSEG4EI64_V }, // 3580
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF2, VLOXSEG4EI64_V }, // 3581
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF2_MASK, VLOXSEG4EI64_V }, // 3582
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF4, VLOXSEG4EI64_V }, // 3583
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF4_MASK, VLOXSEG4EI64_V }, // 3584
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF8, VLOXSEG4EI64_V }, // 3585
|
|
{ PseudoVLOXSEG4EI64_V_M1_MF8_MASK, VLOXSEG4EI64_V }, // 3586
|
|
{ PseudoVLOXSEG4EI64_V_M2_M1, VLOXSEG4EI64_V }, // 3587
|
|
{ PseudoVLOXSEG4EI64_V_M2_M1_MASK, VLOXSEG4EI64_V }, // 3588
|
|
{ PseudoVLOXSEG4EI64_V_M2_M2, VLOXSEG4EI64_V }, // 3589
|
|
{ PseudoVLOXSEG4EI64_V_M2_M2_MASK, VLOXSEG4EI64_V }, // 3590
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF2, VLOXSEG4EI64_V }, // 3591
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF2_MASK, VLOXSEG4EI64_V }, // 3592
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF4, VLOXSEG4EI64_V }, // 3593
|
|
{ PseudoVLOXSEG4EI64_V_M2_MF4_MASK, VLOXSEG4EI64_V }, // 3594
|
|
{ PseudoVLOXSEG4EI64_V_M4_M1, VLOXSEG4EI64_V }, // 3595
|
|
{ PseudoVLOXSEG4EI64_V_M4_M1_MASK, VLOXSEG4EI64_V }, // 3596
|
|
{ PseudoVLOXSEG4EI64_V_M4_M2, VLOXSEG4EI64_V }, // 3597
|
|
{ PseudoVLOXSEG4EI64_V_M4_M2_MASK, VLOXSEG4EI64_V }, // 3598
|
|
{ PseudoVLOXSEG4EI64_V_M4_MF2, VLOXSEG4EI64_V }, // 3599
|
|
{ PseudoVLOXSEG4EI64_V_M4_MF2_MASK, VLOXSEG4EI64_V }, // 3600
|
|
{ PseudoVLOXSEG4EI64_V_M8_M1, VLOXSEG4EI64_V }, // 3601
|
|
{ PseudoVLOXSEG4EI64_V_M8_M1_MASK, VLOXSEG4EI64_V }, // 3602
|
|
{ PseudoVLOXSEG4EI64_V_M8_M2, VLOXSEG4EI64_V }, // 3603
|
|
{ PseudoVLOXSEG4EI64_V_M8_M2_MASK, VLOXSEG4EI64_V }, // 3604
|
|
{ PseudoVLOXSEG4EI8_V_M1_M1, VLOXSEG4EI8_V }, // 3605
|
|
{ PseudoVLOXSEG4EI8_V_M1_M1_MASK, VLOXSEG4EI8_V }, // 3606
|
|
{ PseudoVLOXSEG4EI8_V_M1_M2, VLOXSEG4EI8_V }, // 3607
|
|
{ PseudoVLOXSEG4EI8_V_M1_M2_MASK, VLOXSEG4EI8_V }, // 3608
|
|
{ PseudoVLOXSEG4EI8_V_M2_M2, VLOXSEG4EI8_V }, // 3609
|
|
{ PseudoVLOXSEG4EI8_V_M2_M2_MASK, VLOXSEG4EI8_V }, // 3610
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M1, VLOXSEG4EI8_V }, // 3611
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M1_MASK, VLOXSEG4EI8_V }, // 3612
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M2, VLOXSEG4EI8_V }, // 3613
|
|
{ PseudoVLOXSEG4EI8_V_MF2_M2_MASK, VLOXSEG4EI8_V }, // 3614
|
|
{ PseudoVLOXSEG4EI8_V_MF2_MF2, VLOXSEG4EI8_V }, // 3615
|
|
{ PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, VLOXSEG4EI8_V }, // 3616
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M1, VLOXSEG4EI8_V }, // 3617
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M1_MASK, VLOXSEG4EI8_V }, // 3618
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M2, VLOXSEG4EI8_V }, // 3619
|
|
{ PseudoVLOXSEG4EI8_V_MF4_M2_MASK, VLOXSEG4EI8_V }, // 3620
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF2, VLOXSEG4EI8_V }, // 3621
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, VLOXSEG4EI8_V }, // 3622
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF4, VLOXSEG4EI8_V }, // 3623
|
|
{ PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, VLOXSEG4EI8_V }, // 3624
|
|
{ PseudoVLOXSEG4EI8_V_MF8_M1, VLOXSEG4EI8_V }, // 3625
|
|
{ PseudoVLOXSEG4EI8_V_MF8_M1_MASK, VLOXSEG4EI8_V }, // 3626
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF2, VLOXSEG4EI8_V }, // 3627
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, VLOXSEG4EI8_V }, // 3628
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF4, VLOXSEG4EI8_V }, // 3629
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, VLOXSEG4EI8_V }, // 3630
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF8, VLOXSEG4EI8_V }, // 3631
|
|
{ PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, VLOXSEG4EI8_V }, // 3632
|
|
{ PseudoVLOXSEG5EI16_V_M1_M1, VLOXSEG5EI16_V }, // 3633
|
|
{ PseudoVLOXSEG5EI16_V_M1_M1_MASK, VLOXSEG5EI16_V }, // 3634
|
|
{ PseudoVLOXSEG5EI16_V_M1_MF2, VLOXSEG5EI16_V }, // 3635
|
|
{ PseudoVLOXSEG5EI16_V_M1_MF2_MASK, VLOXSEG5EI16_V }, // 3636
|
|
{ PseudoVLOXSEG5EI16_V_M2_M1, VLOXSEG5EI16_V }, // 3637
|
|
{ PseudoVLOXSEG5EI16_V_M2_M1_MASK, VLOXSEG5EI16_V }, // 3638
|
|
{ PseudoVLOXSEG5EI16_V_MF2_M1, VLOXSEG5EI16_V }, // 3639
|
|
{ PseudoVLOXSEG5EI16_V_MF2_M1_MASK, VLOXSEG5EI16_V }, // 3640
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF2, VLOXSEG5EI16_V }, // 3641
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, VLOXSEG5EI16_V }, // 3642
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF4, VLOXSEG5EI16_V }, // 3643
|
|
{ PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, VLOXSEG5EI16_V }, // 3644
|
|
{ PseudoVLOXSEG5EI16_V_MF4_M1, VLOXSEG5EI16_V }, // 3645
|
|
{ PseudoVLOXSEG5EI16_V_MF4_M1_MASK, VLOXSEG5EI16_V }, // 3646
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF2, VLOXSEG5EI16_V }, // 3647
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, VLOXSEG5EI16_V }, // 3648
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF4, VLOXSEG5EI16_V }, // 3649
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, VLOXSEG5EI16_V }, // 3650
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF8, VLOXSEG5EI16_V }, // 3651
|
|
{ PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, VLOXSEG5EI16_V }, // 3652
|
|
{ PseudoVLOXSEG5EI32_V_M1_M1, VLOXSEG5EI32_V }, // 3653
|
|
{ PseudoVLOXSEG5EI32_V_M1_M1_MASK, VLOXSEG5EI32_V }, // 3654
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF2, VLOXSEG5EI32_V }, // 3655
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF2_MASK, VLOXSEG5EI32_V }, // 3656
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF4, VLOXSEG5EI32_V }, // 3657
|
|
{ PseudoVLOXSEG5EI32_V_M1_MF4_MASK, VLOXSEG5EI32_V }, // 3658
|
|
{ PseudoVLOXSEG5EI32_V_M2_M1, VLOXSEG5EI32_V }, // 3659
|
|
{ PseudoVLOXSEG5EI32_V_M2_M1_MASK, VLOXSEG5EI32_V }, // 3660
|
|
{ PseudoVLOXSEG5EI32_V_M2_MF2, VLOXSEG5EI32_V }, // 3661
|
|
{ PseudoVLOXSEG5EI32_V_M2_MF2_MASK, VLOXSEG5EI32_V }, // 3662
|
|
{ PseudoVLOXSEG5EI32_V_M4_M1, VLOXSEG5EI32_V }, // 3663
|
|
{ PseudoVLOXSEG5EI32_V_M4_M1_MASK, VLOXSEG5EI32_V }, // 3664
|
|
{ PseudoVLOXSEG5EI32_V_MF2_M1, VLOXSEG5EI32_V }, // 3665
|
|
{ PseudoVLOXSEG5EI32_V_MF2_M1_MASK, VLOXSEG5EI32_V }, // 3666
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF2, VLOXSEG5EI32_V }, // 3667
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, VLOXSEG5EI32_V }, // 3668
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF4, VLOXSEG5EI32_V }, // 3669
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, VLOXSEG5EI32_V }, // 3670
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF8, VLOXSEG5EI32_V }, // 3671
|
|
{ PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, VLOXSEG5EI32_V }, // 3672
|
|
{ PseudoVLOXSEG5EI64_V_M1_M1, VLOXSEG5EI64_V }, // 3673
|
|
{ PseudoVLOXSEG5EI64_V_M1_M1_MASK, VLOXSEG5EI64_V }, // 3674
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF2, VLOXSEG5EI64_V }, // 3675
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF2_MASK, VLOXSEG5EI64_V }, // 3676
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF4, VLOXSEG5EI64_V }, // 3677
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF4_MASK, VLOXSEG5EI64_V }, // 3678
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF8, VLOXSEG5EI64_V }, // 3679
|
|
{ PseudoVLOXSEG5EI64_V_M1_MF8_MASK, VLOXSEG5EI64_V }, // 3680
|
|
{ PseudoVLOXSEG5EI64_V_M2_M1, VLOXSEG5EI64_V }, // 3681
|
|
{ PseudoVLOXSEG5EI64_V_M2_M1_MASK, VLOXSEG5EI64_V }, // 3682
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF2, VLOXSEG5EI64_V }, // 3683
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF2_MASK, VLOXSEG5EI64_V }, // 3684
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF4, VLOXSEG5EI64_V }, // 3685
|
|
{ PseudoVLOXSEG5EI64_V_M2_MF4_MASK, VLOXSEG5EI64_V }, // 3686
|
|
{ PseudoVLOXSEG5EI64_V_M4_M1, VLOXSEG5EI64_V }, // 3687
|
|
{ PseudoVLOXSEG5EI64_V_M4_M1_MASK, VLOXSEG5EI64_V }, // 3688
|
|
{ PseudoVLOXSEG5EI64_V_M4_MF2, VLOXSEG5EI64_V }, // 3689
|
|
{ PseudoVLOXSEG5EI64_V_M4_MF2_MASK, VLOXSEG5EI64_V }, // 3690
|
|
{ PseudoVLOXSEG5EI64_V_M8_M1, VLOXSEG5EI64_V }, // 3691
|
|
{ PseudoVLOXSEG5EI64_V_M8_M1_MASK, VLOXSEG5EI64_V }, // 3692
|
|
{ PseudoVLOXSEG5EI8_V_M1_M1, VLOXSEG5EI8_V }, // 3693
|
|
{ PseudoVLOXSEG5EI8_V_M1_M1_MASK, VLOXSEG5EI8_V }, // 3694
|
|
{ PseudoVLOXSEG5EI8_V_MF2_M1, VLOXSEG5EI8_V }, // 3695
|
|
{ PseudoVLOXSEG5EI8_V_MF2_M1_MASK, VLOXSEG5EI8_V }, // 3696
|
|
{ PseudoVLOXSEG5EI8_V_MF2_MF2, VLOXSEG5EI8_V }, // 3697
|
|
{ PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, VLOXSEG5EI8_V }, // 3698
|
|
{ PseudoVLOXSEG5EI8_V_MF4_M1, VLOXSEG5EI8_V }, // 3699
|
|
{ PseudoVLOXSEG5EI8_V_MF4_M1_MASK, VLOXSEG5EI8_V }, // 3700
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF2, VLOXSEG5EI8_V }, // 3701
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, VLOXSEG5EI8_V }, // 3702
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF4, VLOXSEG5EI8_V }, // 3703
|
|
{ PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, VLOXSEG5EI8_V }, // 3704
|
|
{ PseudoVLOXSEG5EI8_V_MF8_M1, VLOXSEG5EI8_V }, // 3705
|
|
{ PseudoVLOXSEG5EI8_V_MF8_M1_MASK, VLOXSEG5EI8_V }, // 3706
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF2, VLOXSEG5EI8_V }, // 3707
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, VLOXSEG5EI8_V }, // 3708
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF4, VLOXSEG5EI8_V }, // 3709
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, VLOXSEG5EI8_V }, // 3710
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF8, VLOXSEG5EI8_V }, // 3711
|
|
{ PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, VLOXSEG5EI8_V }, // 3712
|
|
{ PseudoVLOXSEG6EI16_V_M1_M1, VLOXSEG6EI16_V }, // 3713
|
|
{ PseudoVLOXSEG6EI16_V_M1_M1_MASK, VLOXSEG6EI16_V }, // 3714
|
|
{ PseudoVLOXSEG6EI16_V_M1_MF2, VLOXSEG6EI16_V }, // 3715
|
|
{ PseudoVLOXSEG6EI16_V_M1_MF2_MASK, VLOXSEG6EI16_V }, // 3716
|
|
{ PseudoVLOXSEG6EI16_V_M2_M1, VLOXSEG6EI16_V }, // 3717
|
|
{ PseudoVLOXSEG6EI16_V_M2_M1_MASK, VLOXSEG6EI16_V }, // 3718
|
|
{ PseudoVLOXSEG6EI16_V_MF2_M1, VLOXSEG6EI16_V }, // 3719
|
|
{ PseudoVLOXSEG6EI16_V_MF2_M1_MASK, VLOXSEG6EI16_V }, // 3720
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF2, VLOXSEG6EI16_V }, // 3721
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, VLOXSEG6EI16_V }, // 3722
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF4, VLOXSEG6EI16_V }, // 3723
|
|
{ PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, VLOXSEG6EI16_V }, // 3724
|
|
{ PseudoVLOXSEG6EI16_V_MF4_M1, VLOXSEG6EI16_V }, // 3725
|
|
{ PseudoVLOXSEG6EI16_V_MF4_M1_MASK, VLOXSEG6EI16_V }, // 3726
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF2, VLOXSEG6EI16_V }, // 3727
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, VLOXSEG6EI16_V }, // 3728
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF4, VLOXSEG6EI16_V }, // 3729
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, VLOXSEG6EI16_V }, // 3730
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF8, VLOXSEG6EI16_V }, // 3731
|
|
{ PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, VLOXSEG6EI16_V }, // 3732
|
|
{ PseudoVLOXSEG6EI32_V_M1_M1, VLOXSEG6EI32_V }, // 3733
|
|
{ PseudoVLOXSEG6EI32_V_M1_M1_MASK, VLOXSEG6EI32_V }, // 3734
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF2, VLOXSEG6EI32_V }, // 3735
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF2_MASK, VLOXSEG6EI32_V }, // 3736
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF4, VLOXSEG6EI32_V }, // 3737
|
|
{ PseudoVLOXSEG6EI32_V_M1_MF4_MASK, VLOXSEG6EI32_V }, // 3738
|
|
{ PseudoVLOXSEG6EI32_V_M2_M1, VLOXSEG6EI32_V }, // 3739
|
|
{ PseudoVLOXSEG6EI32_V_M2_M1_MASK, VLOXSEG6EI32_V }, // 3740
|
|
{ PseudoVLOXSEG6EI32_V_M2_MF2, VLOXSEG6EI32_V }, // 3741
|
|
{ PseudoVLOXSEG6EI32_V_M2_MF2_MASK, VLOXSEG6EI32_V }, // 3742
|
|
{ PseudoVLOXSEG6EI32_V_M4_M1, VLOXSEG6EI32_V }, // 3743
|
|
{ PseudoVLOXSEG6EI32_V_M4_M1_MASK, VLOXSEG6EI32_V }, // 3744
|
|
{ PseudoVLOXSEG6EI32_V_MF2_M1, VLOXSEG6EI32_V }, // 3745
|
|
{ PseudoVLOXSEG6EI32_V_MF2_M1_MASK, VLOXSEG6EI32_V }, // 3746
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF2, VLOXSEG6EI32_V }, // 3747
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, VLOXSEG6EI32_V }, // 3748
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF4, VLOXSEG6EI32_V }, // 3749
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, VLOXSEG6EI32_V }, // 3750
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF8, VLOXSEG6EI32_V }, // 3751
|
|
{ PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, VLOXSEG6EI32_V }, // 3752
|
|
{ PseudoVLOXSEG6EI64_V_M1_M1, VLOXSEG6EI64_V }, // 3753
|
|
{ PseudoVLOXSEG6EI64_V_M1_M1_MASK, VLOXSEG6EI64_V }, // 3754
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF2, VLOXSEG6EI64_V }, // 3755
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF2_MASK, VLOXSEG6EI64_V }, // 3756
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF4, VLOXSEG6EI64_V }, // 3757
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF4_MASK, VLOXSEG6EI64_V }, // 3758
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF8, VLOXSEG6EI64_V }, // 3759
|
|
{ PseudoVLOXSEG6EI64_V_M1_MF8_MASK, VLOXSEG6EI64_V }, // 3760
|
|
{ PseudoVLOXSEG6EI64_V_M2_M1, VLOXSEG6EI64_V }, // 3761
|
|
{ PseudoVLOXSEG6EI64_V_M2_M1_MASK, VLOXSEG6EI64_V }, // 3762
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF2, VLOXSEG6EI64_V }, // 3763
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF2_MASK, VLOXSEG6EI64_V }, // 3764
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF4, VLOXSEG6EI64_V }, // 3765
|
|
{ PseudoVLOXSEG6EI64_V_M2_MF4_MASK, VLOXSEG6EI64_V }, // 3766
|
|
{ PseudoVLOXSEG6EI64_V_M4_M1, VLOXSEG6EI64_V }, // 3767
|
|
{ PseudoVLOXSEG6EI64_V_M4_M1_MASK, VLOXSEG6EI64_V }, // 3768
|
|
{ PseudoVLOXSEG6EI64_V_M4_MF2, VLOXSEG6EI64_V }, // 3769
|
|
{ PseudoVLOXSEG6EI64_V_M4_MF2_MASK, VLOXSEG6EI64_V }, // 3770
|
|
{ PseudoVLOXSEG6EI64_V_M8_M1, VLOXSEG6EI64_V }, // 3771
|
|
{ PseudoVLOXSEG6EI64_V_M8_M1_MASK, VLOXSEG6EI64_V }, // 3772
|
|
{ PseudoVLOXSEG6EI8_V_M1_M1, VLOXSEG6EI8_V }, // 3773
|
|
{ PseudoVLOXSEG6EI8_V_M1_M1_MASK, VLOXSEG6EI8_V }, // 3774
|
|
{ PseudoVLOXSEG6EI8_V_MF2_M1, VLOXSEG6EI8_V }, // 3775
|
|
{ PseudoVLOXSEG6EI8_V_MF2_M1_MASK, VLOXSEG6EI8_V }, // 3776
|
|
{ PseudoVLOXSEG6EI8_V_MF2_MF2, VLOXSEG6EI8_V }, // 3777
|
|
{ PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, VLOXSEG6EI8_V }, // 3778
|
|
{ PseudoVLOXSEG6EI8_V_MF4_M1, VLOXSEG6EI8_V }, // 3779
|
|
{ PseudoVLOXSEG6EI8_V_MF4_M1_MASK, VLOXSEG6EI8_V }, // 3780
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF2, VLOXSEG6EI8_V }, // 3781
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, VLOXSEG6EI8_V }, // 3782
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF4, VLOXSEG6EI8_V }, // 3783
|
|
{ PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, VLOXSEG6EI8_V }, // 3784
|
|
{ PseudoVLOXSEG6EI8_V_MF8_M1, VLOXSEG6EI8_V }, // 3785
|
|
{ PseudoVLOXSEG6EI8_V_MF8_M1_MASK, VLOXSEG6EI8_V }, // 3786
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF2, VLOXSEG6EI8_V }, // 3787
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, VLOXSEG6EI8_V }, // 3788
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF4, VLOXSEG6EI8_V }, // 3789
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, VLOXSEG6EI8_V }, // 3790
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF8, VLOXSEG6EI8_V }, // 3791
|
|
{ PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, VLOXSEG6EI8_V }, // 3792
|
|
{ PseudoVLOXSEG7EI16_V_M1_M1, VLOXSEG7EI16_V }, // 3793
|
|
{ PseudoVLOXSEG7EI16_V_M1_M1_MASK, VLOXSEG7EI16_V }, // 3794
|
|
{ PseudoVLOXSEG7EI16_V_M1_MF2, VLOXSEG7EI16_V }, // 3795
|
|
{ PseudoVLOXSEG7EI16_V_M1_MF2_MASK, VLOXSEG7EI16_V }, // 3796
|
|
{ PseudoVLOXSEG7EI16_V_M2_M1, VLOXSEG7EI16_V }, // 3797
|
|
{ PseudoVLOXSEG7EI16_V_M2_M1_MASK, VLOXSEG7EI16_V }, // 3798
|
|
{ PseudoVLOXSEG7EI16_V_MF2_M1, VLOXSEG7EI16_V }, // 3799
|
|
{ PseudoVLOXSEG7EI16_V_MF2_M1_MASK, VLOXSEG7EI16_V }, // 3800
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF2, VLOXSEG7EI16_V }, // 3801
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, VLOXSEG7EI16_V }, // 3802
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF4, VLOXSEG7EI16_V }, // 3803
|
|
{ PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, VLOXSEG7EI16_V }, // 3804
|
|
{ PseudoVLOXSEG7EI16_V_MF4_M1, VLOXSEG7EI16_V }, // 3805
|
|
{ PseudoVLOXSEG7EI16_V_MF4_M1_MASK, VLOXSEG7EI16_V }, // 3806
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF2, VLOXSEG7EI16_V }, // 3807
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, VLOXSEG7EI16_V }, // 3808
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF4, VLOXSEG7EI16_V }, // 3809
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, VLOXSEG7EI16_V }, // 3810
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF8, VLOXSEG7EI16_V }, // 3811
|
|
{ PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, VLOXSEG7EI16_V }, // 3812
|
|
{ PseudoVLOXSEG7EI32_V_M1_M1, VLOXSEG7EI32_V }, // 3813
|
|
{ PseudoVLOXSEG7EI32_V_M1_M1_MASK, VLOXSEG7EI32_V }, // 3814
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF2, VLOXSEG7EI32_V }, // 3815
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF2_MASK, VLOXSEG7EI32_V }, // 3816
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF4, VLOXSEG7EI32_V }, // 3817
|
|
{ PseudoVLOXSEG7EI32_V_M1_MF4_MASK, VLOXSEG7EI32_V }, // 3818
|
|
{ PseudoVLOXSEG7EI32_V_M2_M1, VLOXSEG7EI32_V }, // 3819
|
|
{ PseudoVLOXSEG7EI32_V_M2_M1_MASK, VLOXSEG7EI32_V }, // 3820
|
|
{ PseudoVLOXSEG7EI32_V_M2_MF2, VLOXSEG7EI32_V }, // 3821
|
|
{ PseudoVLOXSEG7EI32_V_M2_MF2_MASK, VLOXSEG7EI32_V }, // 3822
|
|
{ PseudoVLOXSEG7EI32_V_M4_M1, VLOXSEG7EI32_V }, // 3823
|
|
{ PseudoVLOXSEG7EI32_V_M4_M1_MASK, VLOXSEG7EI32_V }, // 3824
|
|
{ PseudoVLOXSEG7EI32_V_MF2_M1, VLOXSEG7EI32_V }, // 3825
|
|
{ PseudoVLOXSEG7EI32_V_MF2_M1_MASK, VLOXSEG7EI32_V }, // 3826
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF2, VLOXSEG7EI32_V }, // 3827
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, VLOXSEG7EI32_V }, // 3828
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF4, VLOXSEG7EI32_V }, // 3829
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, VLOXSEG7EI32_V }, // 3830
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF8, VLOXSEG7EI32_V }, // 3831
|
|
{ PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, VLOXSEG7EI32_V }, // 3832
|
|
{ PseudoVLOXSEG7EI64_V_M1_M1, VLOXSEG7EI64_V }, // 3833
|
|
{ PseudoVLOXSEG7EI64_V_M1_M1_MASK, VLOXSEG7EI64_V }, // 3834
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF2, VLOXSEG7EI64_V }, // 3835
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF2_MASK, VLOXSEG7EI64_V }, // 3836
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF4, VLOXSEG7EI64_V }, // 3837
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF4_MASK, VLOXSEG7EI64_V }, // 3838
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF8, VLOXSEG7EI64_V }, // 3839
|
|
{ PseudoVLOXSEG7EI64_V_M1_MF8_MASK, VLOXSEG7EI64_V }, // 3840
|
|
{ PseudoVLOXSEG7EI64_V_M2_M1, VLOXSEG7EI64_V }, // 3841
|
|
{ PseudoVLOXSEG7EI64_V_M2_M1_MASK, VLOXSEG7EI64_V }, // 3842
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF2, VLOXSEG7EI64_V }, // 3843
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF2_MASK, VLOXSEG7EI64_V }, // 3844
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF4, VLOXSEG7EI64_V }, // 3845
|
|
{ PseudoVLOXSEG7EI64_V_M2_MF4_MASK, VLOXSEG7EI64_V }, // 3846
|
|
{ PseudoVLOXSEG7EI64_V_M4_M1, VLOXSEG7EI64_V }, // 3847
|
|
{ PseudoVLOXSEG7EI64_V_M4_M1_MASK, VLOXSEG7EI64_V }, // 3848
|
|
{ PseudoVLOXSEG7EI64_V_M4_MF2, VLOXSEG7EI64_V }, // 3849
|
|
{ PseudoVLOXSEG7EI64_V_M4_MF2_MASK, VLOXSEG7EI64_V }, // 3850
|
|
{ PseudoVLOXSEG7EI64_V_M8_M1, VLOXSEG7EI64_V }, // 3851
|
|
{ PseudoVLOXSEG7EI64_V_M8_M1_MASK, VLOXSEG7EI64_V }, // 3852
|
|
{ PseudoVLOXSEG7EI8_V_M1_M1, VLOXSEG7EI8_V }, // 3853
|
|
{ PseudoVLOXSEG7EI8_V_M1_M1_MASK, VLOXSEG7EI8_V }, // 3854
|
|
{ PseudoVLOXSEG7EI8_V_MF2_M1, VLOXSEG7EI8_V }, // 3855
|
|
{ PseudoVLOXSEG7EI8_V_MF2_M1_MASK, VLOXSEG7EI8_V }, // 3856
|
|
{ PseudoVLOXSEG7EI8_V_MF2_MF2, VLOXSEG7EI8_V }, // 3857
|
|
{ PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, VLOXSEG7EI8_V }, // 3858
|
|
{ PseudoVLOXSEG7EI8_V_MF4_M1, VLOXSEG7EI8_V }, // 3859
|
|
{ PseudoVLOXSEG7EI8_V_MF4_M1_MASK, VLOXSEG7EI8_V }, // 3860
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF2, VLOXSEG7EI8_V }, // 3861
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, VLOXSEG7EI8_V }, // 3862
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF4, VLOXSEG7EI8_V }, // 3863
|
|
{ PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, VLOXSEG7EI8_V }, // 3864
|
|
{ PseudoVLOXSEG7EI8_V_MF8_M1, VLOXSEG7EI8_V }, // 3865
|
|
{ PseudoVLOXSEG7EI8_V_MF8_M1_MASK, VLOXSEG7EI8_V }, // 3866
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF2, VLOXSEG7EI8_V }, // 3867
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, VLOXSEG7EI8_V }, // 3868
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF4, VLOXSEG7EI8_V }, // 3869
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, VLOXSEG7EI8_V }, // 3870
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF8, VLOXSEG7EI8_V }, // 3871
|
|
{ PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, VLOXSEG7EI8_V }, // 3872
|
|
{ PseudoVLOXSEG8EI16_V_M1_M1, VLOXSEG8EI16_V }, // 3873
|
|
{ PseudoVLOXSEG8EI16_V_M1_M1_MASK, VLOXSEG8EI16_V }, // 3874
|
|
{ PseudoVLOXSEG8EI16_V_M1_MF2, VLOXSEG8EI16_V }, // 3875
|
|
{ PseudoVLOXSEG8EI16_V_M1_MF2_MASK, VLOXSEG8EI16_V }, // 3876
|
|
{ PseudoVLOXSEG8EI16_V_M2_M1, VLOXSEG8EI16_V }, // 3877
|
|
{ PseudoVLOXSEG8EI16_V_M2_M1_MASK, VLOXSEG8EI16_V }, // 3878
|
|
{ PseudoVLOXSEG8EI16_V_MF2_M1, VLOXSEG8EI16_V }, // 3879
|
|
{ PseudoVLOXSEG8EI16_V_MF2_M1_MASK, VLOXSEG8EI16_V }, // 3880
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF2, VLOXSEG8EI16_V }, // 3881
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, VLOXSEG8EI16_V }, // 3882
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF4, VLOXSEG8EI16_V }, // 3883
|
|
{ PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, VLOXSEG8EI16_V }, // 3884
|
|
{ PseudoVLOXSEG8EI16_V_MF4_M1, VLOXSEG8EI16_V }, // 3885
|
|
{ PseudoVLOXSEG8EI16_V_MF4_M1_MASK, VLOXSEG8EI16_V }, // 3886
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF2, VLOXSEG8EI16_V }, // 3887
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, VLOXSEG8EI16_V }, // 3888
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF4, VLOXSEG8EI16_V }, // 3889
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, VLOXSEG8EI16_V }, // 3890
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF8, VLOXSEG8EI16_V }, // 3891
|
|
{ PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, VLOXSEG8EI16_V }, // 3892
|
|
{ PseudoVLOXSEG8EI32_V_M1_M1, VLOXSEG8EI32_V }, // 3893
|
|
{ PseudoVLOXSEG8EI32_V_M1_M1_MASK, VLOXSEG8EI32_V }, // 3894
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF2, VLOXSEG8EI32_V }, // 3895
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF2_MASK, VLOXSEG8EI32_V }, // 3896
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF4, VLOXSEG8EI32_V }, // 3897
|
|
{ PseudoVLOXSEG8EI32_V_M1_MF4_MASK, VLOXSEG8EI32_V }, // 3898
|
|
{ PseudoVLOXSEG8EI32_V_M2_M1, VLOXSEG8EI32_V }, // 3899
|
|
{ PseudoVLOXSEG8EI32_V_M2_M1_MASK, VLOXSEG8EI32_V }, // 3900
|
|
{ PseudoVLOXSEG8EI32_V_M2_MF2, VLOXSEG8EI32_V }, // 3901
|
|
{ PseudoVLOXSEG8EI32_V_M2_MF2_MASK, VLOXSEG8EI32_V }, // 3902
|
|
{ PseudoVLOXSEG8EI32_V_M4_M1, VLOXSEG8EI32_V }, // 3903
|
|
{ PseudoVLOXSEG8EI32_V_M4_M1_MASK, VLOXSEG8EI32_V }, // 3904
|
|
{ PseudoVLOXSEG8EI32_V_MF2_M1, VLOXSEG8EI32_V }, // 3905
|
|
{ PseudoVLOXSEG8EI32_V_MF2_M1_MASK, VLOXSEG8EI32_V }, // 3906
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF2, VLOXSEG8EI32_V }, // 3907
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, VLOXSEG8EI32_V }, // 3908
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF4, VLOXSEG8EI32_V }, // 3909
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, VLOXSEG8EI32_V }, // 3910
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF8, VLOXSEG8EI32_V }, // 3911
|
|
{ PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, VLOXSEG8EI32_V }, // 3912
|
|
{ PseudoVLOXSEG8EI64_V_M1_M1, VLOXSEG8EI64_V }, // 3913
|
|
{ PseudoVLOXSEG8EI64_V_M1_M1_MASK, VLOXSEG8EI64_V }, // 3914
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF2, VLOXSEG8EI64_V }, // 3915
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF2_MASK, VLOXSEG8EI64_V }, // 3916
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF4, VLOXSEG8EI64_V }, // 3917
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF4_MASK, VLOXSEG8EI64_V }, // 3918
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF8, VLOXSEG8EI64_V }, // 3919
|
|
{ PseudoVLOXSEG8EI64_V_M1_MF8_MASK, VLOXSEG8EI64_V }, // 3920
|
|
{ PseudoVLOXSEG8EI64_V_M2_M1, VLOXSEG8EI64_V }, // 3921
|
|
{ PseudoVLOXSEG8EI64_V_M2_M1_MASK, VLOXSEG8EI64_V }, // 3922
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF2, VLOXSEG8EI64_V }, // 3923
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF2_MASK, VLOXSEG8EI64_V }, // 3924
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF4, VLOXSEG8EI64_V }, // 3925
|
|
{ PseudoVLOXSEG8EI64_V_M2_MF4_MASK, VLOXSEG8EI64_V }, // 3926
|
|
{ PseudoVLOXSEG8EI64_V_M4_M1, VLOXSEG8EI64_V }, // 3927
|
|
{ PseudoVLOXSEG8EI64_V_M4_M1_MASK, VLOXSEG8EI64_V }, // 3928
|
|
{ PseudoVLOXSEG8EI64_V_M4_MF2, VLOXSEG8EI64_V }, // 3929
|
|
{ PseudoVLOXSEG8EI64_V_M4_MF2_MASK, VLOXSEG8EI64_V }, // 3930
|
|
{ PseudoVLOXSEG8EI64_V_M8_M1, VLOXSEG8EI64_V }, // 3931
|
|
{ PseudoVLOXSEG8EI64_V_M8_M1_MASK, VLOXSEG8EI64_V }, // 3932
|
|
{ PseudoVLOXSEG8EI8_V_M1_M1, VLOXSEG8EI8_V }, // 3933
|
|
{ PseudoVLOXSEG8EI8_V_M1_M1_MASK, VLOXSEG8EI8_V }, // 3934
|
|
{ PseudoVLOXSEG8EI8_V_MF2_M1, VLOXSEG8EI8_V }, // 3935
|
|
{ PseudoVLOXSEG8EI8_V_MF2_M1_MASK, VLOXSEG8EI8_V }, // 3936
|
|
{ PseudoVLOXSEG8EI8_V_MF2_MF2, VLOXSEG8EI8_V }, // 3937
|
|
{ PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, VLOXSEG8EI8_V }, // 3938
|
|
{ PseudoVLOXSEG8EI8_V_MF4_M1, VLOXSEG8EI8_V }, // 3939
|
|
{ PseudoVLOXSEG8EI8_V_MF4_M1_MASK, VLOXSEG8EI8_V }, // 3940
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF2, VLOXSEG8EI8_V }, // 3941
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, VLOXSEG8EI8_V }, // 3942
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF4, VLOXSEG8EI8_V }, // 3943
|
|
{ PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, VLOXSEG8EI8_V }, // 3944
|
|
{ PseudoVLOXSEG8EI8_V_MF8_M1, VLOXSEG8EI8_V }, // 3945
|
|
{ PseudoVLOXSEG8EI8_V_MF8_M1_MASK, VLOXSEG8EI8_V }, // 3946
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF2, VLOXSEG8EI8_V }, // 3947
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, VLOXSEG8EI8_V }, // 3948
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF4, VLOXSEG8EI8_V }, // 3949
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, VLOXSEG8EI8_V }, // 3950
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF8, VLOXSEG8EI8_V }, // 3951
|
|
{ PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, VLOXSEG8EI8_V }, // 3952
|
|
{ PseudoVLSE16_V_M1, VLSE16_V }, // 3953
|
|
{ PseudoVLSE16_V_M1_MASK, VLSE16_V }, // 3954
|
|
{ PseudoVLSE16_V_M2, VLSE16_V }, // 3955
|
|
{ PseudoVLSE16_V_M2_MASK, VLSE16_V }, // 3956
|
|
{ PseudoVLSE16_V_M4, VLSE16_V }, // 3957
|
|
{ PseudoVLSE16_V_M4_MASK, VLSE16_V }, // 3958
|
|
{ PseudoVLSE16_V_M8, VLSE16_V }, // 3959
|
|
{ PseudoVLSE16_V_M8_MASK, VLSE16_V }, // 3960
|
|
{ PseudoVLSE16_V_MF2, VLSE16_V }, // 3961
|
|
{ PseudoVLSE16_V_MF2_MASK, VLSE16_V }, // 3962
|
|
{ PseudoVLSE16_V_MF4, VLSE16_V }, // 3963
|
|
{ PseudoVLSE16_V_MF4_MASK, VLSE16_V }, // 3964
|
|
{ PseudoVLSE32_V_M1, VLSE32_V }, // 3965
|
|
{ PseudoVLSE32_V_M1_MASK, VLSE32_V }, // 3966
|
|
{ PseudoVLSE32_V_M2, VLSE32_V }, // 3967
|
|
{ PseudoVLSE32_V_M2_MASK, VLSE32_V }, // 3968
|
|
{ PseudoVLSE32_V_M4, VLSE32_V }, // 3969
|
|
{ PseudoVLSE32_V_M4_MASK, VLSE32_V }, // 3970
|
|
{ PseudoVLSE32_V_M8, VLSE32_V }, // 3971
|
|
{ PseudoVLSE32_V_M8_MASK, VLSE32_V }, // 3972
|
|
{ PseudoVLSE32_V_MF2, VLSE32_V }, // 3973
|
|
{ PseudoVLSE32_V_MF2_MASK, VLSE32_V }, // 3974
|
|
{ PseudoVLSE64_V_M1, VLSE64_V }, // 3975
|
|
{ PseudoVLSE64_V_M1_MASK, VLSE64_V }, // 3976
|
|
{ PseudoVLSE64_V_M2, VLSE64_V }, // 3977
|
|
{ PseudoVLSE64_V_M2_MASK, VLSE64_V }, // 3978
|
|
{ PseudoVLSE64_V_M4, VLSE64_V }, // 3979
|
|
{ PseudoVLSE64_V_M4_MASK, VLSE64_V }, // 3980
|
|
{ PseudoVLSE64_V_M8, VLSE64_V }, // 3981
|
|
{ PseudoVLSE64_V_M8_MASK, VLSE64_V }, // 3982
|
|
{ PseudoVLSE8_V_M1, VLSE8_V }, // 3983
|
|
{ PseudoVLSE8_V_M1_MASK, VLSE8_V }, // 3984
|
|
{ PseudoVLSE8_V_M2, VLSE8_V }, // 3985
|
|
{ PseudoVLSE8_V_M2_MASK, VLSE8_V }, // 3986
|
|
{ PseudoVLSE8_V_M4, VLSE8_V }, // 3987
|
|
{ PseudoVLSE8_V_M4_MASK, VLSE8_V }, // 3988
|
|
{ PseudoVLSE8_V_M8, VLSE8_V }, // 3989
|
|
{ PseudoVLSE8_V_M8_MASK, VLSE8_V }, // 3990
|
|
{ PseudoVLSE8_V_MF2, VLSE8_V }, // 3991
|
|
{ PseudoVLSE8_V_MF2_MASK, VLSE8_V }, // 3992
|
|
{ PseudoVLSE8_V_MF4, VLSE8_V }, // 3993
|
|
{ PseudoVLSE8_V_MF4_MASK, VLSE8_V }, // 3994
|
|
{ PseudoVLSE8_V_MF8, VLSE8_V }, // 3995
|
|
{ PseudoVLSE8_V_MF8_MASK, VLSE8_V }, // 3996
|
|
{ PseudoVLSEG2E16FF_V_M1, VLSEG2E16FF_V }, // 3997
|
|
{ PseudoVLSEG2E16FF_V_M1_MASK, VLSEG2E16FF_V }, // 3998
|
|
{ PseudoVLSEG2E16FF_V_M2, VLSEG2E16FF_V }, // 3999
|
|
{ PseudoVLSEG2E16FF_V_M2_MASK, VLSEG2E16FF_V }, // 4000
|
|
{ PseudoVLSEG2E16FF_V_M4, VLSEG2E16FF_V }, // 4001
|
|
{ PseudoVLSEG2E16FF_V_M4_MASK, VLSEG2E16FF_V }, // 4002
|
|
{ PseudoVLSEG2E16FF_V_MF2, VLSEG2E16FF_V }, // 4003
|
|
{ PseudoVLSEG2E16FF_V_MF2_MASK, VLSEG2E16FF_V }, // 4004
|
|
{ PseudoVLSEG2E16FF_V_MF4, VLSEG2E16FF_V }, // 4005
|
|
{ PseudoVLSEG2E16FF_V_MF4_MASK, VLSEG2E16FF_V }, // 4006
|
|
{ PseudoVLSEG2E16_V_M1, VLSEG2E16_V }, // 4007
|
|
{ PseudoVLSEG2E16_V_M1_MASK, VLSEG2E16_V }, // 4008
|
|
{ PseudoVLSEG2E16_V_M2, VLSEG2E16_V }, // 4009
|
|
{ PseudoVLSEG2E16_V_M2_MASK, VLSEG2E16_V }, // 4010
|
|
{ PseudoVLSEG2E16_V_M4, VLSEG2E16_V }, // 4011
|
|
{ PseudoVLSEG2E16_V_M4_MASK, VLSEG2E16_V }, // 4012
|
|
{ PseudoVLSEG2E16_V_MF2, VLSEG2E16_V }, // 4013
|
|
{ PseudoVLSEG2E16_V_MF2_MASK, VLSEG2E16_V }, // 4014
|
|
{ PseudoVLSEG2E16_V_MF4, VLSEG2E16_V }, // 4015
|
|
{ PseudoVLSEG2E16_V_MF4_MASK, VLSEG2E16_V }, // 4016
|
|
{ PseudoVLSEG2E32FF_V_M1, VLSEG2E32FF_V }, // 4017
|
|
{ PseudoVLSEG2E32FF_V_M1_MASK, VLSEG2E32FF_V }, // 4018
|
|
{ PseudoVLSEG2E32FF_V_M2, VLSEG2E32FF_V }, // 4019
|
|
{ PseudoVLSEG2E32FF_V_M2_MASK, VLSEG2E32FF_V }, // 4020
|
|
{ PseudoVLSEG2E32FF_V_M4, VLSEG2E32FF_V }, // 4021
|
|
{ PseudoVLSEG2E32FF_V_M4_MASK, VLSEG2E32FF_V }, // 4022
|
|
{ PseudoVLSEG2E32FF_V_MF2, VLSEG2E32FF_V }, // 4023
|
|
{ PseudoVLSEG2E32FF_V_MF2_MASK, VLSEG2E32FF_V }, // 4024
|
|
{ PseudoVLSEG2E32_V_M1, VLSEG2E32_V }, // 4025
|
|
{ PseudoVLSEG2E32_V_M1_MASK, VLSEG2E32_V }, // 4026
|
|
{ PseudoVLSEG2E32_V_M2, VLSEG2E32_V }, // 4027
|
|
{ PseudoVLSEG2E32_V_M2_MASK, VLSEG2E32_V }, // 4028
|
|
{ PseudoVLSEG2E32_V_M4, VLSEG2E32_V }, // 4029
|
|
{ PseudoVLSEG2E32_V_M4_MASK, VLSEG2E32_V }, // 4030
|
|
{ PseudoVLSEG2E32_V_MF2, VLSEG2E32_V }, // 4031
|
|
{ PseudoVLSEG2E32_V_MF2_MASK, VLSEG2E32_V }, // 4032
|
|
{ PseudoVLSEG2E64FF_V_M1, VLSEG2E64FF_V }, // 4033
|
|
{ PseudoVLSEG2E64FF_V_M1_MASK, VLSEG2E64FF_V }, // 4034
|
|
{ PseudoVLSEG2E64FF_V_M2, VLSEG2E64FF_V }, // 4035
|
|
{ PseudoVLSEG2E64FF_V_M2_MASK, VLSEG2E64FF_V }, // 4036
|
|
{ PseudoVLSEG2E64FF_V_M4, VLSEG2E64FF_V }, // 4037
|
|
{ PseudoVLSEG2E64FF_V_M4_MASK, VLSEG2E64FF_V }, // 4038
|
|
{ PseudoVLSEG2E64_V_M1, VLSEG2E64_V }, // 4039
|
|
{ PseudoVLSEG2E64_V_M1_MASK, VLSEG2E64_V }, // 4040
|
|
{ PseudoVLSEG2E64_V_M2, VLSEG2E64_V }, // 4041
|
|
{ PseudoVLSEG2E64_V_M2_MASK, VLSEG2E64_V }, // 4042
|
|
{ PseudoVLSEG2E64_V_M4, VLSEG2E64_V }, // 4043
|
|
{ PseudoVLSEG2E64_V_M4_MASK, VLSEG2E64_V }, // 4044
|
|
{ PseudoVLSEG2E8FF_V_M1, VLSEG2E8FF_V }, // 4045
|
|
{ PseudoVLSEG2E8FF_V_M1_MASK, VLSEG2E8FF_V }, // 4046
|
|
{ PseudoVLSEG2E8FF_V_M2, VLSEG2E8FF_V }, // 4047
|
|
{ PseudoVLSEG2E8FF_V_M2_MASK, VLSEG2E8FF_V }, // 4048
|
|
{ PseudoVLSEG2E8FF_V_M4, VLSEG2E8FF_V }, // 4049
|
|
{ PseudoVLSEG2E8FF_V_M4_MASK, VLSEG2E8FF_V }, // 4050
|
|
{ PseudoVLSEG2E8FF_V_MF2, VLSEG2E8FF_V }, // 4051
|
|
{ PseudoVLSEG2E8FF_V_MF2_MASK, VLSEG2E8FF_V }, // 4052
|
|
{ PseudoVLSEG2E8FF_V_MF4, VLSEG2E8FF_V }, // 4053
|
|
{ PseudoVLSEG2E8FF_V_MF4_MASK, VLSEG2E8FF_V }, // 4054
|
|
{ PseudoVLSEG2E8FF_V_MF8, VLSEG2E8FF_V }, // 4055
|
|
{ PseudoVLSEG2E8FF_V_MF8_MASK, VLSEG2E8FF_V }, // 4056
|
|
{ PseudoVLSEG2E8_V_M1, VLSEG2E8_V }, // 4057
|
|
{ PseudoVLSEG2E8_V_M1_MASK, VLSEG2E8_V }, // 4058
|
|
{ PseudoVLSEG2E8_V_M2, VLSEG2E8_V }, // 4059
|
|
{ PseudoVLSEG2E8_V_M2_MASK, VLSEG2E8_V }, // 4060
|
|
{ PseudoVLSEG2E8_V_M4, VLSEG2E8_V }, // 4061
|
|
{ PseudoVLSEG2E8_V_M4_MASK, VLSEG2E8_V }, // 4062
|
|
{ PseudoVLSEG2E8_V_MF2, VLSEG2E8_V }, // 4063
|
|
{ PseudoVLSEG2E8_V_MF2_MASK, VLSEG2E8_V }, // 4064
|
|
{ PseudoVLSEG2E8_V_MF4, VLSEG2E8_V }, // 4065
|
|
{ PseudoVLSEG2E8_V_MF4_MASK, VLSEG2E8_V }, // 4066
|
|
{ PseudoVLSEG2E8_V_MF8, VLSEG2E8_V }, // 4067
|
|
{ PseudoVLSEG2E8_V_MF8_MASK, VLSEG2E8_V }, // 4068
|
|
{ PseudoVLSEG3E16FF_V_M1, VLSEG3E16FF_V }, // 4069
|
|
{ PseudoVLSEG3E16FF_V_M1_MASK, VLSEG3E16FF_V }, // 4070
|
|
{ PseudoVLSEG3E16FF_V_M2, VLSEG3E16FF_V }, // 4071
|
|
{ PseudoVLSEG3E16FF_V_M2_MASK, VLSEG3E16FF_V }, // 4072
|
|
{ PseudoVLSEG3E16FF_V_MF2, VLSEG3E16FF_V }, // 4073
|
|
{ PseudoVLSEG3E16FF_V_MF2_MASK, VLSEG3E16FF_V }, // 4074
|
|
{ PseudoVLSEG3E16FF_V_MF4, VLSEG3E16FF_V }, // 4075
|
|
{ PseudoVLSEG3E16FF_V_MF4_MASK, VLSEG3E16FF_V }, // 4076
|
|
{ PseudoVLSEG3E16_V_M1, VLSEG3E16_V }, // 4077
|
|
{ PseudoVLSEG3E16_V_M1_MASK, VLSEG3E16_V }, // 4078
|
|
{ PseudoVLSEG3E16_V_M2, VLSEG3E16_V }, // 4079
|
|
{ PseudoVLSEG3E16_V_M2_MASK, VLSEG3E16_V }, // 4080
|
|
{ PseudoVLSEG3E16_V_MF2, VLSEG3E16_V }, // 4081
|
|
{ PseudoVLSEG3E16_V_MF2_MASK, VLSEG3E16_V }, // 4082
|
|
{ PseudoVLSEG3E16_V_MF4, VLSEG3E16_V }, // 4083
|
|
{ PseudoVLSEG3E16_V_MF4_MASK, VLSEG3E16_V }, // 4084
|
|
{ PseudoVLSEG3E32FF_V_M1, VLSEG3E32FF_V }, // 4085
|
|
{ PseudoVLSEG3E32FF_V_M1_MASK, VLSEG3E32FF_V }, // 4086
|
|
{ PseudoVLSEG3E32FF_V_M2, VLSEG3E32FF_V }, // 4087
|
|
{ PseudoVLSEG3E32FF_V_M2_MASK, VLSEG3E32FF_V }, // 4088
|
|
{ PseudoVLSEG3E32FF_V_MF2, VLSEG3E32FF_V }, // 4089
|
|
{ PseudoVLSEG3E32FF_V_MF2_MASK, VLSEG3E32FF_V }, // 4090
|
|
{ PseudoVLSEG3E32_V_M1, VLSEG3E32_V }, // 4091
|
|
{ PseudoVLSEG3E32_V_M1_MASK, VLSEG3E32_V }, // 4092
|
|
{ PseudoVLSEG3E32_V_M2, VLSEG3E32_V }, // 4093
|
|
{ PseudoVLSEG3E32_V_M2_MASK, VLSEG3E32_V }, // 4094
|
|
{ PseudoVLSEG3E32_V_MF2, VLSEG3E32_V }, // 4095
|
|
{ PseudoVLSEG3E32_V_MF2_MASK, VLSEG3E32_V }, // 4096
|
|
{ PseudoVLSEG3E64FF_V_M1, VLSEG3E64FF_V }, // 4097
|
|
{ PseudoVLSEG3E64FF_V_M1_MASK, VLSEG3E64FF_V }, // 4098
|
|
{ PseudoVLSEG3E64FF_V_M2, VLSEG3E64FF_V }, // 4099
|
|
{ PseudoVLSEG3E64FF_V_M2_MASK, VLSEG3E64FF_V }, // 4100
|
|
{ PseudoVLSEG3E64_V_M1, VLSEG3E64_V }, // 4101
|
|
{ PseudoVLSEG3E64_V_M1_MASK, VLSEG3E64_V }, // 4102
|
|
{ PseudoVLSEG3E64_V_M2, VLSEG3E64_V }, // 4103
|
|
{ PseudoVLSEG3E64_V_M2_MASK, VLSEG3E64_V }, // 4104
|
|
{ PseudoVLSEG3E8FF_V_M1, VLSEG3E8FF_V }, // 4105
|
|
{ PseudoVLSEG3E8FF_V_M1_MASK, VLSEG3E8FF_V }, // 4106
|
|
{ PseudoVLSEG3E8FF_V_M2, VLSEG3E8FF_V }, // 4107
|
|
{ PseudoVLSEG3E8FF_V_M2_MASK, VLSEG3E8FF_V }, // 4108
|
|
{ PseudoVLSEG3E8FF_V_MF2, VLSEG3E8FF_V }, // 4109
|
|
{ PseudoVLSEG3E8FF_V_MF2_MASK, VLSEG3E8FF_V }, // 4110
|
|
{ PseudoVLSEG3E8FF_V_MF4, VLSEG3E8FF_V }, // 4111
|
|
{ PseudoVLSEG3E8FF_V_MF4_MASK, VLSEG3E8FF_V }, // 4112
|
|
{ PseudoVLSEG3E8FF_V_MF8, VLSEG3E8FF_V }, // 4113
|
|
{ PseudoVLSEG3E8FF_V_MF8_MASK, VLSEG3E8FF_V }, // 4114
|
|
{ PseudoVLSEG3E8_V_M1, VLSEG3E8_V }, // 4115
|
|
{ PseudoVLSEG3E8_V_M1_MASK, VLSEG3E8_V }, // 4116
|
|
{ PseudoVLSEG3E8_V_M2, VLSEG3E8_V }, // 4117
|
|
{ PseudoVLSEG3E8_V_M2_MASK, VLSEG3E8_V }, // 4118
|
|
{ PseudoVLSEG3E8_V_MF2, VLSEG3E8_V }, // 4119
|
|
{ PseudoVLSEG3E8_V_MF2_MASK, VLSEG3E8_V }, // 4120
|
|
{ PseudoVLSEG3E8_V_MF4, VLSEG3E8_V }, // 4121
|
|
{ PseudoVLSEG3E8_V_MF4_MASK, VLSEG3E8_V }, // 4122
|
|
{ PseudoVLSEG3E8_V_MF8, VLSEG3E8_V }, // 4123
|
|
{ PseudoVLSEG3E8_V_MF8_MASK, VLSEG3E8_V }, // 4124
|
|
{ PseudoVLSEG4E16FF_V_M1, VLSEG4E16FF_V }, // 4125
|
|
{ PseudoVLSEG4E16FF_V_M1_MASK, VLSEG4E16FF_V }, // 4126
|
|
{ PseudoVLSEG4E16FF_V_M2, VLSEG4E16FF_V }, // 4127
|
|
{ PseudoVLSEG4E16FF_V_M2_MASK, VLSEG4E16FF_V }, // 4128
|
|
{ PseudoVLSEG4E16FF_V_MF2, VLSEG4E16FF_V }, // 4129
|
|
{ PseudoVLSEG4E16FF_V_MF2_MASK, VLSEG4E16FF_V }, // 4130
|
|
{ PseudoVLSEG4E16FF_V_MF4, VLSEG4E16FF_V }, // 4131
|
|
{ PseudoVLSEG4E16FF_V_MF4_MASK, VLSEG4E16FF_V }, // 4132
|
|
{ PseudoVLSEG4E16_V_M1, VLSEG4E16_V }, // 4133
|
|
{ PseudoVLSEG4E16_V_M1_MASK, VLSEG4E16_V }, // 4134
|
|
{ PseudoVLSEG4E16_V_M2, VLSEG4E16_V }, // 4135
|
|
{ PseudoVLSEG4E16_V_M2_MASK, VLSEG4E16_V }, // 4136
|
|
{ PseudoVLSEG4E16_V_MF2, VLSEG4E16_V }, // 4137
|
|
{ PseudoVLSEG4E16_V_MF2_MASK, VLSEG4E16_V }, // 4138
|
|
{ PseudoVLSEG4E16_V_MF4, VLSEG4E16_V }, // 4139
|
|
{ PseudoVLSEG4E16_V_MF4_MASK, VLSEG4E16_V }, // 4140
|
|
{ PseudoVLSEG4E32FF_V_M1, VLSEG4E32FF_V }, // 4141
|
|
{ PseudoVLSEG4E32FF_V_M1_MASK, VLSEG4E32FF_V }, // 4142
|
|
{ PseudoVLSEG4E32FF_V_M2, VLSEG4E32FF_V }, // 4143
|
|
{ PseudoVLSEG4E32FF_V_M2_MASK, VLSEG4E32FF_V }, // 4144
|
|
{ PseudoVLSEG4E32FF_V_MF2, VLSEG4E32FF_V }, // 4145
|
|
{ PseudoVLSEG4E32FF_V_MF2_MASK, VLSEG4E32FF_V }, // 4146
|
|
{ PseudoVLSEG4E32_V_M1, VLSEG4E32_V }, // 4147
|
|
{ PseudoVLSEG4E32_V_M1_MASK, VLSEG4E32_V }, // 4148
|
|
{ PseudoVLSEG4E32_V_M2, VLSEG4E32_V }, // 4149
|
|
{ PseudoVLSEG4E32_V_M2_MASK, VLSEG4E32_V }, // 4150
|
|
{ PseudoVLSEG4E32_V_MF2, VLSEG4E32_V }, // 4151
|
|
{ PseudoVLSEG4E32_V_MF2_MASK, VLSEG4E32_V }, // 4152
|
|
{ PseudoVLSEG4E64FF_V_M1, VLSEG4E64FF_V }, // 4153
|
|
{ PseudoVLSEG4E64FF_V_M1_MASK, VLSEG4E64FF_V }, // 4154
|
|
{ PseudoVLSEG4E64FF_V_M2, VLSEG4E64FF_V }, // 4155
|
|
{ PseudoVLSEG4E64FF_V_M2_MASK, VLSEG4E64FF_V }, // 4156
|
|
{ PseudoVLSEG4E64_V_M1, VLSEG4E64_V }, // 4157
|
|
{ PseudoVLSEG4E64_V_M1_MASK, VLSEG4E64_V }, // 4158
|
|
{ PseudoVLSEG4E64_V_M2, VLSEG4E64_V }, // 4159
|
|
{ PseudoVLSEG4E64_V_M2_MASK, VLSEG4E64_V }, // 4160
|
|
{ PseudoVLSEG4E8FF_V_M1, VLSEG4E8FF_V }, // 4161
|
|
{ PseudoVLSEG4E8FF_V_M1_MASK, VLSEG4E8FF_V }, // 4162
|
|
{ PseudoVLSEG4E8FF_V_M2, VLSEG4E8FF_V }, // 4163
|
|
{ PseudoVLSEG4E8FF_V_M2_MASK, VLSEG4E8FF_V }, // 4164
|
|
{ PseudoVLSEG4E8FF_V_MF2, VLSEG4E8FF_V }, // 4165
|
|
{ PseudoVLSEG4E8FF_V_MF2_MASK, VLSEG4E8FF_V }, // 4166
|
|
{ PseudoVLSEG4E8FF_V_MF4, VLSEG4E8FF_V }, // 4167
|
|
{ PseudoVLSEG4E8FF_V_MF4_MASK, VLSEG4E8FF_V }, // 4168
|
|
{ PseudoVLSEG4E8FF_V_MF8, VLSEG4E8FF_V }, // 4169
|
|
{ PseudoVLSEG4E8FF_V_MF8_MASK, VLSEG4E8FF_V }, // 4170
|
|
{ PseudoVLSEG4E8_V_M1, VLSEG4E8_V }, // 4171
|
|
{ PseudoVLSEG4E8_V_M1_MASK, VLSEG4E8_V }, // 4172
|
|
{ PseudoVLSEG4E8_V_M2, VLSEG4E8_V }, // 4173
|
|
{ PseudoVLSEG4E8_V_M2_MASK, VLSEG4E8_V }, // 4174
|
|
{ PseudoVLSEG4E8_V_MF2, VLSEG4E8_V }, // 4175
|
|
{ PseudoVLSEG4E8_V_MF2_MASK, VLSEG4E8_V }, // 4176
|
|
{ PseudoVLSEG4E8_V_MF4, VLSEG4E8_V }, // 4177
|
|
{ PseudoVLSEG4E8_V_MF4_MASK, VLSEG4E8_V }, // 4178
|
|
{ PseudoVLSEG4E8_V_MF8, VLSEG4E8_V }, // 4179
|
|
{ PseudoVLSEG4E8_V_MF8_MASK, VLSEG4E8_V }, // 4180
|
|
{ PseudoVLSEG5E16FF_V_M1, VLSEG5E16FF_V }, // 4181
|
|
{ PseudoVLSEG5E16FF_V_M1_MASK, VLSEG5E16FF_V }, // 4182
|
|
{ PseudoVLSEG5E16FF_V_MF2, VLSEG5E16FF_V }, // 4183
|
|
{ PseudoVLSEG5E16FF_V_MF2_MASK, VLSEG5E16FF_V }, // 4184
|
|
{ PseudoVLSEG5E16FF_V_MF4, VLSEG5E16FF_V }, // 4185
|
|
{ PseudoVLSEG5E16FF_V_MF4_MASK, VLSEG5E16FF_V }, // 4186
|
|
{ PseudoVLSEG5E16_V_M1, VLSEG5E16_V }, // 4187
|
|
{ PseudoVLSEG5E16_V_M1_MASK, VLSEG5E16_V }, // 4188
|
|
{ PseudoVLSEG5E16_V_MF2, VLSEG5E16_V }, // 4189
|
|
{ PseudoVLSEG5E16_V_MF2_MASK, VLSEG5E16_V }, // 4190
|
|
{ PseudoVLSEG5E16_V_MF4, VLSEG5E16_V }, // 4191
|
|
{ PseudoVLSEG5E16_V_MF4_MASK, VLSEG5E16_V }, // 4192
|
|
{ PseudoVLSEG5E32FF_V_M1, VLSEG5E32FF_V }, // 4193
|
|
{ PseudoVLSEG5E32FF_V_M1_MASK, VLSEG5E32FF_V }, // 4194
|
|
{ PseudoVLSEG5E32FF_V_MF2, VLSEG5E32FF_V }, // 4195
|
|
{ PseudoVLSEG5E32FF_V_MF2_MASK, VLSEG5E32FF_V }, // 4196
|
|
{ PseudoVLSEG5E32_V_M1, VLSEG5E32_V }, // 4197
|
|
{ PseudoVLSEG5E32_V_M1_MASK, VLSEG5E32_V }, // 4198
|
|
{ PseudoVLSEG5E32_V_MF2, VLSEG5E32_V }, // 4199
|
|
{ PseudoVLSEG5E32_V_MF2_MASK, VLSEG5E32_V }, // 4200
|
|
{ PseudoVLSEG5E64FF_V_M1, VLSEG5E64FF_V }, // 4201
|
|
{ PseudoVLSEG5E64FF_V_M1_MASK, VLSEG5E64FF_V }, // 4202
|
|
{ PseudoVLSEG5E64_V_M1, VLSEG5E64_V }, // 4203
|
|
{ PseudoVLSEG5E64_V_M1_MASK, VLSEG5E64_V }, // 4204
|
|
{ PseudoVLSEG5E8FF_V_M1, VLSEG5E8FF_V }, // 4205
|
|
{ PseudoVLSEG5E8FF_V_M1_MASK, VLSEG5E8FF_V }, // 4206
|
|
{ PseudoVLSEG5E8FF_V_MF2, VLSEG5E8FF_V }, // 4207
|
|
{ PseudoVLSEG5E8FF_V_MF2_MASK, VLSEG5E8FF_V }, // 4208
|
|
{ PseudoVLSEG5E8FF_V_MF4, VLSEG5E8FF_V }, // 4209
|
|
{ PseudoVLSEG5E8FF_V_MF4_MASK, VLSEG5E8FF_V }, // 4210
|
|
{ PseudoVLSEG5E8FF_V_MF8, VLSEG5E8FF_V }, // 4211
|
|
{ PseudoVLSEG5E8FF_V_MF8_MASK, VLSEG5E8FF_V }, // 4212
|
|
{ PseudoVLSEG5E8_V_M1, VLSEG5E8_V }, // 4213
|
|
{ PseudoVLSEG5E8_V_M1_MASK, VLSEG5E8_V }, // 4214
|
|
{ PseudoVLSEG5E8_V_MF2, VLSEG5E8_V }, // 4215
|
|
{ PseudoVLSEG5E8_V_MF2_MASK, VLSEG5E8_V }, // 4216
|
|
{ PseudoVLSEG5E8_V_MF4, VLSEG5E8_V }, // 4217
|
|
{ PseudoVLSEG5E8_V_MF4_MASK, VLSEG5E8_V }, // 4218
|
|
{ PseudoVLSEG5E8_V_MF8, VLSEG5E8_V }, // 4219
|
|
{ PseudoVLSEG5E8_V_MF8_MASK, VLSEG5E8_V }, // 4220
|
|
{ PseudoVLSEG6E16FF_V_M1, VLSEG6E16FF_V }, // 4221
|
|
{ PseudoVLSEG6E16FF_V_M1_MASK, VLSEG6E16FF_V }, // 4222
|
|
{ PseudoVLSEG6E16FF_V_MF2, VLSEG6E16FF_V }, // 4223
|
|
{ PseudoVLSEG6E16FF_V_MF2_MASK, VLSEG6E16FF_V }, // 4224
|
|
{ PseudoVLSEG6E16FF_V_MF4, VLSEG6E16FF_V }, // 4225
|
|
{ PseudoVLSEG6E16FF_V_MF4_MASK, VLSEG6E16FF_V }, // 4226
|
|
{ PseudoVLSEG6E16_V_M1, VLSEG6E16_V }, // 4227
|
|
{ PseudoVLSEG6E16_V_M1_MASK, VLSEG6E16_V }, // 4228
|
|
{ PseudoVLSEG6E16_V_MF2, VLSEG6E16_V }, // 4229
|
|
{ PseudoVLSEG6E16_V_MF2_MASK, VLSEG6E16_V }, // 4230
|
|
{ PseudoVLSEG6E16_V_MF4, VLSEG6E16_V }, // 4231
|
|
{ PseudoVLSEG6E16_V_MF4_MASK, VLSEG6E16_V }, // 4232
|
|
{ PseudoVLSEG6E32FF_V_M1, VLSEG6E32FF_V }, // 4233
|
|
{ PseudoVLSEG6E32FF_V_M1_MASK, VLSEG6E32FF_V }, // 4234
|
|
{ PseudoVLSEG6E32FF_V_MF2, VLSEG6E32FF_V }, // 4235
|
|
{ PseudoVLSEG6E32FF_V_MF2_MASK, VLSEG6E32FF_V }, // 4236
|
|
{ PseudoVLSEG6E32_V_M1, VLSEG6E32_V }, // 4237
|
|
{ PseudoVLSEG6E32_V_M1_MASK, VLSEG6E32_V }, // 4238
|
|
{ PseudoVLSEG6E32_V_MF2, VLSEG6E32_V }, // 4239
|
|
{ PseudoVLSEG6E32_V_MF2_MASK, VLSEG6E32_V }, // 4240
|
|
{ PseudoVLSEG6E64FF_V_M1, VLSEG6E64FF_V }, // 4241
|
|
{ PseudoVLSEG6E64FF_V_M1_MASK, VLSEG6E64FF_V }, // 4242
|
|
{ PseudoVLSEG6E64_V_M1, VLSEG6E64_V }, // 4243
|
|
{ PseudoVLSEG6E64_V_M1_MASK, VLSEG6E64_V }, // 4244
|
|
{ PseudoVLSEG6E8FF_V_M1, VLSEG6E8FF_V }, // 4245
|
|
{ PseudoVLSEG6E8FF_V_M1_MASK, VLSEG6E8FF_V }, // 4246
|
|
{ PseudoVLSEG6E8FF_V_MF2, VLSEG6E8FF_V }, // 4247
|
|
{ PseudoVLSEG6E8FF_V_MF2_MASK, VLSEG6E8FF_V }, // 4248
|
|
{ PseudoVLSEG6E8FF_V_MF4, VLSEG6E8FF_V }, // 4249
|
|
{ PseudoVLSEG6E8FF_V_MF4_MASK, VLSEG6E8FF_V }, // 4250
|
|
{ PseudoVLSEG6E8FF_V_MF8, VLSEG6E8FF_V }, // 4251
|
|
{ PseudoVLSEG6E8FF_V_MF8_MASK, VLSEG6E8FF_V }, // 4252
|
|
{ PseudoVLSEG6E8_V_M1, VLSEG6E8_V }, // 4253
|
|
{ PseudoVLSEG6E8_V_M1_MASK, VLSEG6E8_V }, // 4254
|
|
{ PseudoVLSEG6E8_V_MF2, VLSEG6E8_V }, // 4255
|
|
{ PseudoVLSEG6E8_V_MF2_MASK, VLSEG6E8_V }, // 4256
|
|
{ PseudoVLSEG6E8_V_MF4, VLSEG6E8_V }, // 4257
|
|
{ PseudoVLSEG6E8_V_MF4_MASK, VLSEG6E8_V }, // 4258
|
|
{ PseudoVLSEG6E8_V_MF8, VLSEG6E8_V }, // 4259
|
|
{ PseudoVLSEG6E8_V_MF8_MASK, VLSEG6E8_V }, // 4260
|
|
{ PseudoVLSEG7E16FF_V_M1, VLSEG7E16FF_V }, // 4261
|
|
{ PseudoVLSEG7E16FF_V_M1_MASK, VLSEG7E16FF_V }, // 4262
|
|
{ PseudoVLSEG7E16FF_V_MF2, VLSEG7E16FF_V }, // 4263
|
|
{ PseudoVLSEG7E16FF_V_MF2_MASK, VLSEG7E16FF_V }, // 4264
|
|
{ PseudoVLSEG7E16FF_V_MF4, VLSEG7E16FF_V }, // 4265
|
|
{ PseudoVLSEG7E16FF_V_MF4_MASK, VLSEG7E16FF_V }, // 4266
|
|
{ PseudoVLSEG7E16_V_M1, VLSEG7E16_V }, // 4267
|
|
{ PseudoVLSEG7E16_V_M1_MASK, VLSEG7E16_V }, // 4268
|
|
{ PseudoVLSEG7E16_V_MF2, VLSEG7E16_V }, // 4269
|
|
{ PseudoVLSEG7E16_V_MF2_MASK, VLSEG7E16_V }, // 4270
|
|
{ PseudoVLSEG7E16_V_MF4, VLSEG7E16_V }, // 4271
|
|
{ PseudoVLSEG7E16_V_MF4_MASK, VLSEG7E16_V }, // 4272
|
|
{ PseudoVLSEG7E32FF_V_M1, VLSEG7E32FF_V }, // 4273
|
|
{ PseudoVLSEG7E32FF_V_M1_MASK, VLSEG7E32FF_V }, // 4274
|
|
{ PseudoVLSEG7E32FF_V_MF2, VLSEG7E32FF_V }, // 4275
|
|
{ PseudoVLSEG7E32FF_V_MF2_MASK, VLSEG7E32FF_V }, // 4276
|
|
{ PseudoVLSEG7E32_V_M1, VLSEG7E32_V }, // 4277
|
|
{ PseudoVLSEG7E32_V_M1_MASK, VLSEG7E32_V }, // 4278
|
|
{ PseudoVLSEG7E32_V_MF2, VLSEG7E32_V }, // 4279
|
|
{ PseudoVLSEG7E32_V_MF2_MASK, VLSEG7E32_V }, // 4280
|
|
{ PseudoVLSEG7E64FF_V_M1, VLSEG7E64FF_V }, // 4281
|
|
{ PseudoVLSEG7E64FF_V_M1_MASK, VLSEG7E64FF_V }, // 4282
|
|
{ PseudoVLSEG7E64_V_M1, VLSEG7E64_V }, // 4283
|
|
{ PseudoVLSEG7E64_V_M1_MASK, VLSEG7E64_V }, // 4284
|
|
{ PseudoVLSEG7E8FF_V_M1, VLSEG7E8FF_V }, // 4285
|
|
{ PseudoVLSEG7E8FF_V_M1_MASK, VLSEG7E8FF_V }, // 4286
|
|
{ PseudoVLSEG7E8FF_V_MF2, VLSEG7E8FF_V }, // 4287
|
|
{ PseudoVLSEG7E8FF_V_MF2_MASK, VLSEG7E8FF_V }, // 4288
|
|
{ PseudoVLSEG7E8FF_V_MF4, VLSEG7E8FF_V }, // 4289
|
|
{ PseudoVLSEG7E8FF_V_MF4_MASK, VLSEG7E8FF_V }, // 4290
|
|
{ PseudoVLSEG7E8FF_V_MF8, VLSEG7E8FF_V }, // 4291
|
|
{ PseudoVLSEG7E8FF_V_MF8_MASK, VLSEG7E8FF_V }, // 4292
|
|
{ PseudoVLSEG7E8_V_M1, VLSEG7E8_V }, // 4293
|
|
{ PseudoVLSEG7E8_V_M1_MASK, VLSEG7E8_V }, // 4294
|
|
{ PseudoVLSEG7E8_V_MF2, VLSEG7E8_V }, // 4295
|
|
{ PseudoVLSEG7E8_V_MF2_MASK, VLSEG7E8_V }, // 4296
|
|
{ PseudoVLSEG7E8_V_MF4, VLSEG7E8_V }, // 4297
|
|
{ PseudoVLSEG7E8_V_MF4_MASK, VLSEG7E8_V }, // 4298
|
|
{ PseudoVLSEG7E8_V_MF8, VLSEG7E8_V }, // 4299
|
|
{ PseudoVLSEG7E8_V_MF8_MASK, VLSEG7E8_V }, // 4300
|
|
{ PseudoVLSEG8E16FF_V_M1, VLSEG8E16FF_V }, // 4301
|
|
{ PseudoVLSEG8E16FF_V_M1_MASK, VLSEG8E16FF_V }, // 4302
|
|
{ PseudoVLSEG8E16FF_V_MF2, VLSEG8E16FF_V }, // 4303
|
|
{ PseudoVLSEG8E16FF_V_MF2_MASK, VLSEG8E16FF_V }, // 4304
|
|
{ PseudoVLSEG8E16FF_V_MF4, VLSEG8E16FF_V }, // 4305
|
|
{ PseudoVLSEG8E16FF_V_MF4_MASK, VLSEG8E16FF_V }, // 4306
|
|
{ PseudoVLSEG8E16_V_M1, VLSEG8E16_V }, // 4307
|
|
{ PseudoVLSEG8E16_V_M1_MASK, VLSEG8E16_V }, // 4308
|
|
{ PseudoVLSEG8E16_V_MF2, VLSEG8E16_V }, // 4309
|
|
{ PseudoVLSEG8E16_V_MF2_MASK, VLSEG8E16_V }, // 4310
|
|
{ PseudoVLSEG8E16_V_MF4, VLSEG8E16_V }, // 4311
|
|
{ PseudoVLSEG8E16_V_MF4_MASK, VLSEG8E16_V }, // 4312
|
|
{ PseudoVLSEG8E32FF_V_M1, VLSEG8E32FF_V }, // 4313
|
|
{ PseudoVLSEG8E32FF_V_M1_MASK, VLSEG8E32FF_V }, // 4314
|
|
{ PseudoVLSEG8E32FF_V_MF2, VLSEG8E32FF_V }, // 4315
|
|
{ PseudoVLSEG8E32FF_V_MF2_MASK, VLSEG8E32FF_V }, // 4316
|
|
{ PseudoVLSEG8E32_V_M1, VLSEG8E32_V }, // 4317
|
|
{ PseudoVLSEG8E32_V_M1_MASK, VLSEG8E32_V }, // 4318
|
|
{ PseudoVLSEG8E32_V_MF2, VLSEG8E32_V }, // 4319
|
|
{ PseudoVLSEG8E32_V_MF2_MASK, VLSEG8E32_V }, // 4320
|
|
{ PseudoVLSEG8E64FF_V_M1, VLSEG8E64FF_V }, // 4321
|
|
{ PseudoVLSEG8E64FF_V_M1_MASK, VLSEG8E64FF_V }, // 4322
|
|
{ PseudoVLSEG8E64_V_M1, VLSEG8E64_V }, // 4323
|
|
{ PseudoVLSEG8E64_V_M1_MASK, VLSEG8E64_V }, // 4324
|
|
{ PseudoVLSEG8E8FF_V_M1, VLSEG8E8FF_V }, // 4325
|
|
{ PseudoVLSEG8E8FF_V_M1_MASK, VLSEG8E8FF_V }, // 4326
|
|
{ PseudoVLSEG8E8FF_V_MF2, VLSEG8E8FF_V }, // 4327
|
|
{ PseudoVLSEG8E8FF_V_MF2_MASK, VLSEG8E8FF_V }, // 4328
|
|
{ PseudoVLSEG8E8FF_V_MF4, VLSEG8E8FF_V }, // 4329
|
|
{ PseudoVLSEG8E8FF_V_MF4_MASK, VLSEG8E8FF_V }, // 4330
|
|
{ PseudoVLSEG8E8FF_V_MF8, VLSEG8E8FF_V }, // 4331
|
|
{ PseudoVLSEG8E8FF_V_MF8_MASK, VLSEG8E8FF_V }, // 4332
|
|
{ PseudoVLSEG8E8_V_M1, VLSEG8E8_V }, // 4333
|
|
{ PseudoVLSEG8E8_V_M1_MASK, VLSEG8E8_V }, // 4334
|
|
{ PseudoVLSEG8E8_V_MF2, VLSEG8E8_V }, // 4335
|
|
{ PseudoVLSEG8E8_V_MF2_MASK, VLSEG8E8_V }, // 4336
|
|
{ PseudoVLSEG8E8_V_MF4, VLSEG8E8_V }, // 4337
|
|
{ PseudoVLSEG8E8_V_MF4_MASK, VLSEG8E8_V }, // 4338
|
|
{ PseudoVLSEG8E8_V_MF8, VLSEG8E8_V }, // 4339
|
|
{ PseudoVLSEG8E8_V_MF8_MASK, VLSEG8E8_V }, // 4340
|
|
{ PseudoVLSSEG2E16_V_M1, VLSSEG2E16_V }, // 4341
|
|
{ PseudoVLSSEG2E16_V_M1_MASK, VLSSEG2E16_V }, // 4342
|
|
{ PseudoVLSSEG2E16_V_M2, VLSSEG2E16_V }, // 4343
|
|
{ PseudoVLSSEG2E16_V_M2_MASK, VLSSEG2E16_V }, // 4344
|
|
{ PseudoVLSSEG2E16_V_M4, VLSSEG2E16_V }, // 4345
|
|
{ PseudoVLSSEG2E16_V_M4_MASK, VLSSEG2E16_V }, // 4346
|
|
{ PseudoVLSSEG2E16_V_MF2, VLSSEG2E16_V }, // 4347
|
|
{ PseudoVLSSEG2E16_V_MF2_MASK, VLSSEG2E16_V }, // 4348
|
|
{ PseudoVLSSEG2E16_V_MF4, VLSSEG2E16_V }, // 4349
|
|
{ PseudoVLSSEG2E16_V_MF4_MASK, VLSSEG2E16_V }, // 4350
|
|
{ PseudoVLSSEG2E32_V_M1, VLSSEG2E32_V }, // 4351
|
|
{ PseudoVLSSEG2E32_V_M1_MASK, VLSSEG2E32_V }, // 4352
|
|
{ PseudoVLSSEG2E32_V_M2, VLSSEG2E32_V }, // 4353
|
|
{ PseudoVLSSEG2E32_V_M2_MASK, VLSSEG2E32_V }, // 4354
|
|
{ PseudoVLSSEG2E32_V_M4, VLSSEG2E32_V }, // 4355
|
|
{ PseudoVLSSEG2E32_V_M4_MASK, VLSSEG2E32_V }, // 4356
|
|
{ PseudoVLSSEG2E32_V_MF2, VLSSEG2E32_V }, // 4357
|
|
{ PseudoVLSSEG2E32_V_MF2_MASK, VLSSEG2E32_V }, // 4358
|
|
{ PseudoVLSSEG2E64_V_M1, VLSSEG2E64_V }, // 4359
|
|
{ PseudoVLSSEG2E64_V_M1_MASK, VLSSEG2E64_V }, // 4360
|
|
{ PseudoVLSSEG2E64_V_M2, VLSSEG2E64_V }, // 4361
|
|
{ PseudoVLSSEG2E64_V_M2_MASK, VLSSEG2E64_V }, // 4362
|
|
{ PseudoVLSSEG2E64_V_M4, VLSSEG2E64_V }, // 4363
|
|
{ PseudoVLSSEG2E64_V_M4_MASK, VLSSEG2E64_V }, // 4364
|
|
{ PseudoVLSSEG2E8_V_M1, VLSSEG2E8_V }, // 4365
|
|
{ PseudoVLSSEG2E8_V_M1_MASK, VLSSEG2E8_V }, // 4366
|
|
{ PseudoVLSSEG2E8_V_M2, VLSSEG2E8_V }, // 4367
|
|
{ PseudoVLSSEG2E8_V_M2_MASK, VLSSEG2E8_V }, // 4368
|
|
{ PseudoVLSSEG2E8_V_M4, VLSSEG2E8_V }, // 4369
|
|
{ PseudoVLSSEG2E8_V_M4_MASK, VLSSEG2E8_V }, // 4370
|
|
{ PseudoVLSSEG2E8_V_MF2, VLSSEG2E8_V }, // 4371
|
|
{ PseudoVLSSEG2E8_V_MF2_MASK, VLSSEG2E8_V }, // 4372
|
|
{ PseudoVLSSEG2E8_V_MF4, VLSSEG2E8_V }, // 4373
|
|
{ PseudoVLSSEG2E8_V_MF4_MASK, VLSSEG2E8_V }, // 4374
|
|
{ PseudoVLSSEG2E8_V_MF8, VLSSEG2E8_V }, // 4375
|
|
{ PseudoVLSSEG2E8_V_MF8_MASK, VLSSEG2E8_V }, // 4376
|
|
{ PseudoVLSSEG3E16_V_M1, VLSSEG3E16_V }, // 4377
|
|
{ PseudoVLSSEG3E16_V_M1_MASK, VLSSEG3E16_V }, // 4378
|
|
{ PseudoVLSSEG3E16_V_M2, VLSSEG3E16_V }, // 4379
|
|
{ PseudoVLSSEG3E16_V_M2_MASK, VLSSEG3E16_V }, // 4380
|
|
{ PseudoVLSSEG3E16_V_MF2, VLSSEG3E16_V }, // 4381
|
|
{ PseudoVLSSEG3E16_V_MF2_MASK, VLSSEG3E16_V }, // 4382
|
|
{ PseudoVLSSEG3E16_V_MF4, VLSSEG3E16_V }, // 4383
|
|
{ PseudoVLSSEG3E16_V_MF4_MASK, VLSSEG3E16_V }, // 4384
|
|
{ PseudoVLSSEG3E32_V_M1, VLSSEG3E32_V }, // 4385
|
|
{ PseudoVLSSEG3E32_V_M1_MASK, VLSSEG3E32_V }, // 4386
|
|
{ PseudoVLSSEG3E32_V_M2, VLSSEG3E32_V }, // 4387
|
|
{ PseudoVLSSEG3E32_V_M2_MASK, VLSSEG3E32_V }, // 4388
|
|
{ PseudoVLSSEG3E32_V_MF2, VLSSEG3E32_V }, // 4389
|
|
{ PseudoVLSSEG3E32_V_MF2_MASK, VLSSEG3E32_V }, // 4390
|
|
{ PseudoVLSSEG3E64_V_M1, VLSSEG3E64_V }, // 4391
|
|
{ PseudoVLSSEG3E64_V_M1_MASK, VLSSEG3E64_V }, // 4392
|
|
{ PseudoVLSSEG3E64_V_M2, VLSSEG3E64_V }, // 4393
|
|
{ PseudoVLSSEG3E64_V_M2_MASK, VLSSEG3E64_V }, // 4394
|
|
{ PseudoVLSSEG3E8_V_M1, VLSSEG3E8_V }, // 4395
|
|
{ PseudoVLSSEG3E8_V_M1_MASK, VLSSEG3E8_V }, // 4396
|
|
{ PseudoVLSSEG3E8_V_M2, VLSSEG3E8_V }, // 4397
|
|
{ PseudoVLSSEG3E8_V_M2_MASK, VLSSEG3E8_V }, // 4398
|
|
{ PseudoVLSSEG3E8_V_MF2, VLSSEG3E8_V }, // 4399
|
|
{ PseudoVLSSEG3E8_V_MF2_MASK, VLSSEG3E8_V }, // 4400
|
|
{ PseudoVLSSEG3E8_V_MF4, VLSSEG3E8_V }, // 4401
|
|
{ PseudoVLSSEG3E8_V_MF4_MASK, VLSSEG3E8_V }, // 4402
|
|
{ PseudoVLSSEG3E8_V_MF8, VLSSEG3E8_V }, // 4403
|
|
{ PseudoVLSSEG3E8_V_MF8_MASK, VLSSEG3E8_V }, // 4404
|
|
{ PseudoVLSSEG4E16_V_M1, VLSSEG4E16_V }, // 4405
|
|
{ PseudoVLSSEG4E16_V_M1_MASK, VLSSEG4E16_V }, // 4406
|
|
{ PseudoVLSSEG4E16_V_M2, VLSSEG4E16_V }, // 4407
|
|
{ PseudoVLSSEG4E16_V_M2_MASK, VLSSEG4E16_V }, // 4408
|
|
{ PseudoVLSSEG4E16_V_MF2, VLSSEG4E16_V }, // 4409
|
|
{ PseudoVLSSEG4E16_V_MF2_MASK, VLSSEG4E16_V }, // 4410
|
|
{ PseudoVLSSEG4E16_V_MF4, VLSSEG4E16_V }, // 4411
|
|
{ PseudoVLSSEG4E16_V_MF4_MASK, VLSSEG4E16_V }, // 4412
|
|
{ PseudoVLSSEG4E32_V_M1, VLSSEG4E32_V }, // 4413
|
|
{ PseudoVLSSEG4E32_V_M1_MASK, VLSSEG4E32_V }, // 4414
|
|
{ PseudoVLSSEG4E32_V_M2, VLSSEG4E32_V }, // 4415
|
|
{ PseudoVLSSEG4E32_V_M2_MASK, VLSSEG4E32_V }, // 4416
|
|
{ PseudoVLSSEG4E32_V_MF2, VLSSEG4E32_V }, // 4417
|
|
{ PseudoVLSSEG4E32_V_MF2_MASK, VLSSEG4E32_V }, // 4418
|
|
{ PseudoVLSSEG4E64_V_M1, VLSSEG4E64_V }, // 4419
|
|
{ PseudoVLSSEG4E64_V_M1_MASK, VLSSEG4E64_V }, // 4420
|
|
{ PseudoVLSSEG4E64_V_M2, VLSSEG4E64_V }, // 4421
|
|
{ PseudoVLSSEG4E64_V_M2_MASK, VLSSEG4E64_V }, // 4422
|
|
{ PseudoVLSSEG4E8_V_M1, VLSSEG4E8_V }, // 4423
|
|
{ PseudoVLSSEG4E8_V_M1_MASK, VLSSEG4E8_V }, // 4424
|
|
{ PseudoVLSSEG4E8_V_M2, VLSSEG4E8_V }, // 4425
|
|
{ PseudoVLSSEG4E8_V_M2_MASK, VLSSEG4E8_V }, // 4426
|
|
{ PseudoVLSSEG4E8_V_MF2, VLSSEG4E8_V }, // 4427
|
|
{ PseudoVLSSEG4E8_V_MF2_MASK, VLSSEG4E8_V }, // 4428
|
|
{ PseudoVLSSEG4E8_V_MF4, VLSSEG4E8_V }, // 4429
|
|
{ PseudoVLSSEG4E8_V_MF4_MASK, VLSSEG4E8_V }, // 4430
|
|
{ PseudoVLSSEG4E8_V_MF8, VLSSEG4E8_V }, // 4431
|
|
{ PseudoVLSSEG4E8_V_MF8_MASK, VLSSEG4E8_V }, // 4432
|
|
{ PseudoVLSSEG5E16_V_M1, VLSSEG5E16_V }, // 4433
|
|
{ PseudoVLSSEG5E16_V_M1_MASK, VLSSEG5E16_V }, // 4434
|
|
{ PseudoVLSSEG5E16_V_MF2, VLSSEG5E16_V }, // 4435
|
|
{ PseudoVLSSEG5E16_V_MF2_MASK, VLSSEG5E16_V }, // 4436
|
|
{ PseudoVLSSEG5E16_V_MF4, VLSSEG5E16_V }, // 4437
|
|
{ PseudoVLSSEG5E16_V_MF4_MASK, VLSSEG5E16_V }, // 4438
|
|
{ PseudoVLSSEG5E32_V_M1, VLSSEG5E32_V }, // 4439
|
|
{ PseudoVLSSEG5E32_V_M1_MASK, VLSSEG5E32_V }, // 4440
|
|
{ PseudoVLSSEG5E32_V_MF2, VLSSEG5E32_V }, // 4441
|
|
{ PseudoVLSSEG5E32_V_MF2_MASK, VLSSEG5E32_V }, // 4442
|
|
{ PseudoVLSSEG5E64_V_M1, VLSSEG5E64_V }, // 4443
|
|
{ PseudoVLSSEG5E64_V_M1_MASK, VLSSEG5E64_V }, // 4444
|
|
{ PseudoVLSSEG5E8_V_M1, VLSSEG5E8_V }, // 4445
|
|
{ PseudoVLSSEG5E8_V_M1_MASK, VLSSEG5E8_V }, // 4446
|
|
{ PseudoVLSSEG5E8_V_MF2, VLSSEG5E8_V }, // 4447
|
|
{ PseudoVLSSEG5E8_V_MF2_MASK, VLSSEG5E8_V }, // 4448
|
|
{ PseudoVLSSEG5E8_V_MF4, VLSSEG5E8_V }, // 4449
|
|
{ PseudoVLSSEG5E8_V_MF4_MASK, VLSSEG5E8_V }, // 4450
|
|
{ PseudoVLSSEG5E8_V_MF8, VLSSEG5E8_V }, // 4451
|
|
{ PseudoVLSSEG5E8_V_MF8_MASK, VLSSEG5E8_V }, // 4452
|
|
{ PseudoVLSSEG6E16_V_M1, VLSSEG6E16_V }, // 4453
|
|
{ PseudoVLSSEG6E16_V_M1_MASK, VLSSEG6E16_V }, // 4454
|
|
{ PseudoVLSSEG6E16_V_MF2, VLSSEG6E16_V }, // 4455
|
|
{ PseudoVLSSEG6E16_V_MF2_MASK, VLSSEG6E16_V }, // 4456
|
|
{ PseudoVLSSEG6E16_V_MF4, VLSSEG6E16_V }, // 4457
|
|
{ PseudoVLSSEG6E16_V_MF4_MASK, VLSSEG6E16_V }, // 4458
|
|
{ PseudoVLSSEG6E32_V_M1, VLSSEG6E32_V }, // 4459
|
|
{ PseudoVLSSEG6E32_V_M1_MASK, VLSSEG6E32_V }, // 4460
|
|
{ PseudoVLSSEG6E32_V_MF2, VLSSEG6E32_V }, // 4461
|
|
{ PseudoVLSSEG6E32_V_MF2_MASK, VLSSEG6E32_V }, // 4462
|
|
{ PseudoVLSSEG6E64_V_M1, VLSSEG6E64_V }, // 4463
|
|
{ PseudoVLSSEG6E64_V_M1_MASK, VLSSEG6E64_V }, // 4464
|
|
{ PseudoVLSSEG6E8_V_M1, VLSSEG6E8_V }, // 4465
|
|
{ PseudoVLSSEG6E8_V_M1_MASK, VLSSEG6E8_V }, // 4466
|
|
{ PseudoVLSSEG6E8_V_MF2, VLSSEG6E8_V }, // 4467
|
|
{ PseudoVLSSEG6E8_V_MF2_MASK, VLSSEG6E8_V }, // 4468
|
|
{ PseudoVLSSEG6E8_V_MF4, VLSSEG6E8_V }, // 4469
|
|
{ PseudoVLSSEG6E8_V_MF4_MASK, VLSSEG6E8_V }, // 4470
|
|
{ PseudoVLSSEG6E8_V_MF8, VLSSEG6E8_V }, // 4471
|
|
{ PseudoVLSSEG6E8_V_MF8_MASK, VLSSEG6E8_V }, // 4472
|
|
{ PseudoVLSSEG7E16_V_M1, VLSSEG7E16_V }, // 4473
|
|
{ PseudoVLSSEG7E16_V_M1_MASK, VLSSEG7E16_V }, // 4474
|
|
{ PseudoVLSSEG7E16_V_MF2, VLSSEG7E16_V }, // 4475
|
|
{ PseudoVLSSEG7E16_V_MF2_MASK, VLSSEG7E16_V }, // 4476
|
|
{ PseudoVLSSEG7E16_V_MF4, VLSSEG7E16_V }, // 4477
|
|
{ PseudoVLSSEG7E16_V_MF4_MASK, VLSSEG7E16_V }, // 4478
|
|
{ PseudoVLSSEG7E32_V_M1, VLSSEG7E32_V }, // 4479
|
|
{ PseudoVLSSEG7E32_V_M1_MASK, VLSSEG7E32_V }, // 4480
|
|
{ PseudoVLSSEG7E32_V_MF2, VLSSEG7E32_V }, // 4481
|
|
{ PseudoVLSSEG7E32_V_MF2_MASK, VLSSEG7E32_V }, // 4482
|
|
{ PseudoVLSSEG7E64_V_M1, VLSSEG7E64_V }, // 4483
|
|
{ PseudoVLSSEG7E64_V_M1_MASK, VLSSEG7E64_V }, // 4484
|
|
{ PseudoVLSSEG7E8_V_M1, VLSSEG7E8_V }, // 4485
|
|
{ PseudoVLSSEG7E8_V_M1_MASK, VLSSEG7E8_V }, // 4486
|
|
{ PseudoVLSSEG7E8_V_MF2, VLSSEG7E8_V }, // 4487
|
|
{ PseudoVLSSEG7E8_V_MF2_MASK, VLSSEG7E8_V }, // 4488
|
|
{ PseudoVLSSEG7E8_V_MF4, VLSSEG7E8_V }, // 4489
|
|
{ PseudoVLSSEG7E8_V_MF4_MASK, VLSSEG7E8_V }, // 4490
|
|
{ PseudoVLSSEG7E8_V_MF8, VLSSEG7E8_V }, // 4491
|
|
{ PseudoVLSSEG7E8_V_MF8_MASK, VLSSEG7E8_V }, // 4492
|
|
{ PseudoVLSSEG8E16_V_M1, VLSSEG8E16_V }, // 4493
|
|
{ PseudoVLSSEG8E16_V_M1_MASK, VLSSEG8E16_V }, // 4494
|
|
{ PseudoVLSSEG8E16_V_MF2, VLSSEG8E16_V }, // 4495
|
|
{ PseudoVLSSEG8E16_V_MF2_MASK, VLSSEG8E16_V }, // 4496
|
|
{ PseudoVLSSEG8E16_V_MF4, VLSSEG8E16_V }, // 4497
|
|
{ PseudoVLSSEG8E16_V_MF4_MASK, VLSSEG8E16_V }, // 4498
|
|
{ PseudoVLSSEG8E32_V_M1, VLSSEG8E32_V }, // 4499
|
|
{ PseudoVLSSEG8E32_V_M1_MASK, VLSSEG8E32_V }, // 4500
|
|
{ PseudoVLSSEG8E32_V_MF2, VLSSEG8E32_V }, // 4501
|
|
{ PseudoVLSSEG8E32_V_MF2_MASK, VLSSEG8E32_V }, // 4502
|
|
{ PseudoVLSSEG8E64_V_M1, VLSSEG8E64_V }, // 4503
|
|
{ PseudoVLSSEG8E64_V_M1_MASK, VLSSEG8E64_V }, // 4504
|
|
{ PseudoVLSSEG8E8_V_M1, VLSSEG8E8_V }, // 4505
|
|
{ PseudoVLSSEG8E8_V_M1_MASK, VLSSEG8E8_V }, // 4506
|
|
{ PseudoVLSSEG8E8_V_MF2, VLSSEG8E8_V }, // 4507
|
|
{ PseudoVLSSEG8E8_V_MF2_MASK, VLSSEG8E8_V }, // 4508
|
|
{ PseudoVLSSEG8E8_V_MF4, VLSSEG8E8_V }, // 4509
|
|
{ PseudoVLSSEG8E8_V_MF4_MASK, VLSSEG8E8_V }, // 4510
|
|
{ PseudoVLSSEG8E8_V_MF8, VLSSEG8E8_V }, // 4511
|
|
{ PseudoVLSSEG8E8_V_MF8_MASK, VLSSEG8E8_V }, // 4512
|
|
{ PseudoVLUXEI16_V_M1_M1, VLUXEI16_V }, // 4513
|
|
{ PseudoVLUXEI16_V_M1_M1_MASK, VLUXEI16_V }, // 4514
|
|
{ PseudoVLUXEI16_V_M1_M2, VLUXEI16_V }, // 4515
|
|
{ PseudoVLUXEI16_V_M1_M2_MASK, VLUXEI16_V }, // 4516
|
|
{ PseudoVLUXEI16_V_M1_M4, VLUXEI16_V }, // 4517
|
|
{ PseudoVLUXEI16_V_M1_M4_MASK, VLUXEI16_V }, // 4518
|
|
{ PseudoVLUXEI16_V_M1_MF2, VLUXEI16_V }, // 4519
|
|
{ PseudoVLUXEI16_V_M1_MF2_MASK, VLUXEI16_V }, // 4520
|
|
{ PseudoVLUXEI16_V_M2_M1, VLUXEI16_V }, // 4521
|
|
{ PseudoVLUXEI16_V_M2_M1_MASK, VLUXEI16_V }, // 4522
|
|
{ PseudoVLUXEI16_V_M2_M2, VLUXEI16_V }, // 4523
|
|
{ PseudoVLUXEI16_V_M2_M2_MASK, VLUXEI16_V }, // 4524
|
|
{ PseudoVLUXEI16_V_M2_M4, VLUXEI16_V }, // 4525
|
|
{ PseudoVLUXEI16_V_M2_M4_MASK, VLUXEI16_V }, // 4526
|
|
{ PseudoVLUXEI16_V_M2_M8, VLUXEI16_V }, // 4527
|
|
{ PseudoVLUXEI16_V_M2_M8_MASK, VLUXEI16_V }, // 4528
|
|
{ PseudoVLUXEI16_V_M4_M2, VLUXEI16_V }, // 4529
|
|
{ PseudoVLUXEI16_V_M4_M2_MASK, VLUXEI16_V }, // 4530
|
|
{ PseudoVLUXEI16_V_M4_M4, VLUXEI16_V }, // 4531
|
|
{ PseudoVLUXEI16_V_M4_M4_MASK, VLUXEI16_V }, // 4532
|
|
{ PseudoVLUXEI16_V_M4_M8, VLUXEI16_V }, // 4533
|
|
{ PseudoVLUXEI16_V_M4_M8_MASK, VLUXEI16_V }, // 4534
|
|
{ PseudoVLUXEI16_V_M8_M4, VLUXEI16_V }, // 4535
|
|
{ PseudoVLUXEI16_V_M8_M4_MASK, VLUXEI16_V }, // 4536
|
|
{ PseudoVLUXEI16_V_M8_M8, VLUXEI16_V }, // 4537
|
|
{ PseudoVLUXEI16_V_M8_M8_MASK, VLUXEI16_V }, // 4538
|
|
{ PseudoVLUXEI16_V_MF2_M1, VLUXEI16_V }, // 4539
|
|
{ PseudoVLUXEI16_V_MF2_M1_MASK, VLUXEI16_V }, // 4540
|
|
{ PseudoVLUXEI16_V_MF2_M2, VLUXEI16_V }, // 4541
|
|
{ PseudoVLUXEI16_V_MF2_M2_MASK, VLUXEI16_V }, // 4542
|
|
{ PseudoVLUXEI16_V_MF2_MF2, VLUXEI16_V }, // 4543
|
|
{ PseudoVLUXEI16_V_MF2_MF2_MASK, VLUXEI16_V }, // 4544
|
|
{ PseudoVLUXEI16_V_MF2_MF4, VLUXEI16_V }, // 4545
|
|
{ PseudoVLUXEI16_V_MF2_MF4_MASK, VLUXEI16_V }, // 4546
|
|
{ PseudoVLUXEI16_V_MF4_M1, VLUXEI16_V }, // 4547
|
|
{ PseudoVLUXEI16_V_MF4_M1_MASK, VLUXEI16_V }, // 4548
|
|
{ PseudoVLUXEI16_V_MF4_MF2, VLUXEI16_V }, // 4549
|
|
{ PseudoVLUXEI16_V_MF4_MF2_MASK, VLUXEI16_V }, // 4550
|
|
{ PseudoVLUXEI16_V_MF4_MF4, VLUXEI16_V }, // 4551
|
|
{ PseudoVLUXEI16_V_MF4_MF4_MASK, VLUXEI16_V }, // 4552
|
|
{ PseudoVLUXEI16_V_MF4_MF8, VLUXEI16_V }, // 4553
|
|
{ PseudoVLUXEI16_V_MF4_MF8_MASK, VLUXEI16_V }, // 4554
|
|
{ PseudoVLUXEI32_V_M1_M1, VLUXEI32_V }, // 4555
|
|
{ PseudoVLUXEI32_V_M1_M1_MASK, VLUXEI32_V }, // 4556
|
|
{ PseudoVLUXEI32_V_M1_M2, VLUXEI32_V }, // 4557
|
|
{ PseudoVLUXEI32_V_M1_M2_MASK, VLUXEI32_V }, // 4558
|
|
{ PseudoVLUXEI32_V_M1_MF2, VLUXEI32_V }, // 4559
|
|
{ PseudoVLUXEI32_V_M1_MF2_MASK, VLUXEI32_V }, // 4560
|
|
{ PseudoVLUXEI32_V_M1_MF4, VLUXEI32_V }, // 4561
|
|
{ PseudoVLUXEI32_V_M1_MF4_MASK, VLUXEI32_V }, // 4562
|
|
{ PseudoVLUXEI32_V_M2_M1, VLUXEI32_V }, // 4563
|
|
{ PseudoVLUXEI32_V_M2_M1_MASK, VLUXEI32_V }, // 4564
|
|
{ PseudoVLUXEI32_V_M2_M2, VLUXEI32_V }, // 4565
|
|
{ PseudoVLUXEI32_V_M2_M2_MASK, VLUXEI32_V }, // 4566
|
|
{ PseudoVLUXEI32_V_M2_M4, VLUXEI32_V }, // 4567
|
|
{ PseudoVLUXEI32_V_M2_M4_MASK, VLUXEI32_V }, // 4568
|
|
{ PseudoVLUXEI32_V_M2_MF2, VLUXEI32_V }, // 4569
|
|
{ PseudoVLUXEI32_V_M2_MF2_MASK, VLUXEI32_V }, // 4570
|
|
{ PseudoVLUXEI32_V_M4_M1, VLUXEI32_V }, // 4571
|
|
{ PseudoVLUXEI32_V_M4_M1_MASK, VLUXEI32_V }, // 4572
|
|
{ PseudoVLUXEI32_V_M4_M2, VLUXEI32_V }, // 4573
|
|
{ PseudoVLUXEI32_V_M4_M2_MASK, VLUXEI32_V }, // 4574
|
|
{ PseudoVLUXEI32_V_M4_M4, VLUXEI32_V }, // 4575
|
|
{ PseudoVLUXEI32_V_M4_M4_MASK, VLUXEI32_V }, // 4576
|
|
{ PseudoVLUXEI32_V_M4_M8, VLUXEI32_V }, // 4577
|
|
{ PseudoVLUXEI32_V_M4_M8_MASK, VLUXEI32_V }, // 4578
|
|
{ PseudoVLUXEI32_V_M8_M2, VLUXEI32_V }, // 4579
|
|
{ PseudoVLUXEI32_V_M8_M2_MASK, VLUXEI32_V }, // 4580
|
|
{ PseudoVLUXEI32_V_M8_M4, VLUXEI32_V }, // 4581
|
|
{ PseudoVLUXEI32_V_M8_M4_MASK, VLUXEI32_V }, // 4582
|
|
{ PseudoVLUXEI32_V_M8_M8, VLUXEI32_V }, // 4583
|
|
{ PseudoVLUXEI32_V_M8_M8_MASK, VLUXEI32_V }, // 4584
|
|
{ PseudoVLUXEI32_V_MF2_M1, VLUXEI32_V }, // 4585
|
|
{ PseudoVLUXEI32_V_MF2_M1_MASK, VLUXEI32_V }, // 4586
|
|
{ PseudoVLUXEI32_V_MF2_MF2, VLUXEI32_V }, // 4587
|
|
{ PseudoVLUXEI32_V_MF2_MF2_MASK, VLUXEI32_V }, // 4588
|
|
{ PseudoVLUXEI32_V_MF2_MF4, VLUXEI32_V }, // 4589
|
|
{ PseudoVLUXEI32_V_MF2_MF4_MASK, VLUXEI32_V }, // 4590
|
|
{ PseudoVLUXEI32_V_MF2_MF8, VLUXEI32_V }, // 4591
|
|
{ PseudoVLUXEI32_V_MF2_MF8_MASK, VLUXEI32_V }, // 4592
|
|
{ PseudoVLUXEI64_V_M1_M1, VLUXEI64_V }, // 4593
|
|
{ PseudoVLUXEI64_V_M1_M1_MASK, VLUXEI64_V }, // 4594
|
|
{ PseudoVLUXEI64_V_M1_MF2, VLUXEI64_V }, // 4595
|
|
{ PseudoVLUXEI64_V_M1_MF2_MASK, VLUXEI64_V }, // 4596
|
|
{ PseudoVLUXEI64_V_M1_MF4, VLUXEI64_V }, // 4597
|
|
{ PseudoVLUXEI64_V_M1_MF4_MASK, VLUXEI64_V }, // 4598
|
|
{ PseudoVLUXEI64_V_M1_MF8, VLUXEI64_V }, // 4599
|
|
{ PseudoVLUXEI64_V_M1_MF8_MASK, VLUXEI64_V }, // 4600
|
|
{ PseudoVLUXEI64_V_M2_M1, VLUXEI64_V }, // 4601
|
|
{ PseudoVLUXEI64_V_M2_M1_MASK, VLUXEI64_V }, // 4602
|
|
{ PseudoVLUXEI64_V_M2_M2, VLUXEI64_V }, // 4603
|
|
{ PseudoVLUXEI64_V_M2_M2_MASK, VLUXEI64_V }, // 4604
|
|
{ PseudoVLUXEI64_V_M2_MF2, VLUXEI64_V }, // 4605
|
|
{ PseudoVLUXEI64_V_M2_MF2_MASK, VLUXEI64_V }, // 4606
|
|
{ PseudoVLUXEI64_V_M2_MF4, VLUXEI64_V }, // 4607
|
|
{ PseudoVLUXEI64_V_M2_MF4_MASK, VLUXEI64_V }, // 4608
|
|
{ PseudoVLUXEI64_V_M4_M1, VLUXEI64_V }, // 4609
|
|
{ PseudoVLUXEI64_V_M4_M1_MASK, VLUXEI64_V }, // 4610
|
|
{ PseudoVLUXEI64_V_M4_M2, VLUXEI64_V }, // 4611
|
|
{ PseudoVLUXEI64_V_M4_M2_MASK, VLUXEI64_V }, // 4612
|
|
{ PseudoVLUXEI64_V_M4_M4, VLUXEI64_V }, // 4613
|
|
{ PseudoVLUXEI64_V_M4_M4_MASK, VLUXEI64_V }, // 4614
|
|
{ PseudoVLUXEI64_V_M4_MF2, VLUXEI64_V }, // 4615
|
|
{ PseudoVLUXEI64_V_M4_MF2_MASK, VLUXEI64_V }, // 4616
|
|
{ PseudoVLUXEI64_V_M8_M1, VLUXEI64_V }, // 4617
|
|
{ PseudoVLUXEI64_V_M8_M1_MASK, VLUXEI64_V }, // 4618
|
|
{ PseudoVLUXEI64_V_M8_M2, VLUXEI64_V }, // 4619
|
|
{ PseudoVLUXEI64_V_M8_M2_MASK, VLUXEI64_V }, // 4620
|
|
{ PseudoVLUXEI64_V_M8_M4, VLUXEI64_V }, // 4621
|
|
{ PseudoVLUXEI64_V_M8_M4_MASK, VLUXEI64_V }, // 4622
|
|
{ PseudoVLUXEI64_V_M8_M8, VLUXEI64_V }, // 4623
|
|
{ PseudoVLUXEI64_V_M8_M8_MASK, VLUXEI64_V }, // 4624
|
|
{ PseudoVLUXEI8_V_M1_M1, VLUXEI8_V }, // 4625
|
|
{ PseudoVLUXEI8_V_M1_M1_MASK, VLUXEI8_V }, // 4626
|
|
{ PseudoVLUXEI8_V_M1_M2, VLUXEI8_V }, // 4627
|
|
{ PseudoVLUXEI8_V_M1_M2_MASK, VLUXEI8_V }, // 4628
|
|
{ PseudoVLUXEI8_V_M1_M4, VLUXEI8_V }, // 4629
|
|
{ PseudoVLUXEI8_V_M1_M4_MASK, VLUXEI8_V }, // 4630
|
|
{ PseudoVLUXEI8_V_M1_M8, VLUXEI8_V }, // 4631
|
|
{ PseudoVLUXEI8_V_M1_M8_MASK, VLUXEI8_V }, // 4632
|
|
{ PseudoVLUXEI8_V_M2_M2, VLUXEI8_V }, // 4633
|
|
{ PseudoVLUXEI8_V_M2_M2_MASK, VLUXEI8_V }, // 4634
|
|
{ PseudoVLUXEI8_V_M2_M4, VLUXEI8_V }, // 4635
|
|
{ PseudoVLUXEI8_V_M2_M4_MASK, VLUXEI8_V }, // 4636
|
|
{ PseudoVLUXEI8_V_M2_M8, VLUXEI8_V }, // 4637
|
|
{ PseudoVLUXEI8_V_M2_M8_MASK, VLUXEI8_V }, // 4638
|
|
{ PseudoVLUXEI8_V_M4_M4, VLUXEI8_V }, // 4639
|
|
{ PseudoVLUXEI8_V_M4_M4_MASK, VLUXEI8_V }, // 4640
|
|
{ PseudoVLUXEI8_V_M4_M8, VLUXEI8_V }, // 4641
|
|
{ PseudoVLUXEI8_V_M4_M8_MASK, VLUXEI8_V }, // 4642
|
|
{ PseudoVLUXEI8_V_M8_M8, VLUXEI8_V }, // 4643
|
|
{ PseudoVLUXEI8_V_M8_M8_MASK, VLUXEI8_V }, // 4644
|
|
{ PseudoVLUXEI8_V_MF2_M1, VLUXEI8_V }, // 4645
|
|
{ PseudoVLUXEI8_V_MF2_M1_MASK, VLUXEI8_V }, // 4646
|
|
{ PseudoVLUXEI8_V_MF2_M2, VLUXEI8_V }, // 4647
|
|
{ PseudoVLUXEI8_V_MF2_M2_MASK, VLUXEI8_V }, // 4648
|
|
{ PseudoVLUXEI8_V_MF2_M4, VLUXEI8_V }, // 4649
|
|
{ PseudoVLUXEI8_V_MF2_M4_MASK, VLUXEI8_V }, // 4650
|
|
{ PseudoVLUXEI8_V_MF2_MF2, VLUXEI8_V }, // 4651
|
|
{ PseudoVLUXEI8_V_MF2_MF2_MASK, VLUXEI8_V }, // 4652
|
|
{ PseudoVLUXEI8_V_MF4_M1, VLUXEI8_V }, // 4653
|
|
{ PseudoVLUXEI8_V_MF4_M1_MASK, VLUXEI8_V }, // 4654
|
|
{ PseudoVLUXEI8_V_MF4_M2, VLUXEI8_V }, // 4655
|
|
{ PseudoVLUXEI8_V_MF4_M2_MASK, VLUXEI8_V }, // 4656
|
|
{ PseudoVLUXEI8_V_MF4_MF2, VLUXEI8_V }, // 4657
|
|
{ PseudoVLUXEI8_V_MF4_MF2_MASK, VLUXEI8_V }, // 4658
|
|
{ PseudoVLUXEI8_V_MF4_MF4, VLUXEI8_V }, // 4659
|
|
{ PseudoVLUXEI8_V_MF4_MF4_MASK, VLUXEI8_V }, // 4660
|
|
{ PseudoVLUXEI8_V_MF8_M1, VLUXEI8_V }, // 4661
|
|
{ PseudoVLUXEI8_V_MF8_M1_MASK, VLUXEI8_V }, // 4662
|
|
{ PseudoVLUXEI8_V_MF8_MF2, VLUXEI8_V }, // 4663
|
|
{ PseudoVLUXEI8_V_MF8_MF2_MASK, VLUXEI8_V }, // 4664
|
|
{ PseudoVLUXEI8_V_MF8_MF4, VLUXEI8_V }, // 4665
|
|
{ PseudoVLUXEI8_V_MF8_MF4_MASK, VLUXEI8_V }, // 4666
|
|
{ PseudoVLUXEI8_V_MF8_MF8, VLUXEI8_V }, // 4667
|
|
{ PseudoVLUXEI8_V_MF8_MF8_MASK, VLUXEI8_V }, // 4668
|
|
{ PseudoVLUXSEG2EI16_V_M1_M1, VLUXSEG2EI16_V }, // 4669
|
|
{ PseudoVLUXSEG2EI16_V_M1_M1_MASK, VLUXSEG2EI16_V }, // 4670
|
|
{ PseudoVLUXSEG2EI16_V_M1_M2, VLUXSEG2EI16_V }, // 4671
|
|
{ PseudoVLUXSEG2EI16_V_M1_M2_MASK, VLUXSEG2EI16_V }, // 4672
|
|
{ PseudoVLUXSEG2EI16_V_M1_M4, VLUXSEG2EI16_V }, // 4673
|
|
{ PseudoVLUXSEG2EI16_V_M1_M4_MASK, VLUXSEG2EI16_V }, // 4674
|
|
{ PseudoVLUXSEG2EI16_V_M1_MF2, VLUXSEG2EI16_V }, // 4675
|
|
{ PseudoVLUXSEG2EI16_V_M1_MF2_MASK, VLUXSEG2EI16_V }, // 4676
|
|
{ PseudoVLUXSEG2EI16_V_M2_M1, VLUXSEG2EI16_V }, // 4677
|
|
{ PseudoVLUXSEG2EI16_V_M2_M1_MASK, VLUXSEG2EI16_V }, // 4678
|
|
{ PseudoVLUXSEG2EI16_V_M2_M2, VLUXSEG2EI16_V }, // 4679
|
|
{ PseudoVLUXSEG2EI16_V_M2_M2_MASK, VLUXSEG2EI16_V }, // 4680
|
|
{ PseudoVLUXSEG2EI16_V_M2_M4, VLUXSEG2EI16_V }, // 4681
|
|
{ PseudoVLUXSEG2EI16_V_M2_M4_MASK, VLUXSEG2EI16_V }, // 4682
|
|
{ PseudoVLUXSEG2EI16_V_M4_M2, VLUXSEG2EI16_V }, // 4683
|
|
{ PseudoVLUXSEG2EI16_V_M4_M2_MASK, VLUXSEG2EI16_V }, // 4684
|
|
{ PseudoVLUXSEG2EI16_V_M4_M4, VLUXSEG2EI16_V }, // 4685
|
|
{ PseudoVLUXSEG2EI16_V_M4_M4_MASK, VLUXSEG2EI16_V }, // 4686
|
|
{ PseudoVLUXSEG2EI16_V_M8_M4, VLUXSEG2EI16_V }, // 4687
|
|
{ PseudoVLUXSEG2EI16_V_M8_M4_MASK, VLUXSEG2EI16_V }, // 4688
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M1, VLUXSEG2EI16_V }, // 4689
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M1_MASK, VLUXSEG2EI16_V }, // 4690
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M2, VLUXSEG2EI16_V }, // 4691
|
|
{ PseudoVLUXSEG2EI16_V_MF2_M2_MASK, VLUXSEG2EI16_V }, // 4692
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF2, VLUXSEG2EI16_V }, // 4693
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, VLUXSEG2EI16_V }, // 4694
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF4, VLUXSEG2EI16_V }, // 4695
|
|
{ PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, VLUXSEG2EI16_V }, // 4696
|
|
{ PseudoVLUXSEG2EI16_V_MF4_M1, VLUXSEG2EI16_V }, // 4697
|
|
{ PseudoVLUXSEG2EI16_V_MF4_M1_MASK, VLUXSEG2EI16_V }, // 4698
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF2, VLUXSEG2EI16_V }, // 4699
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, VLUXSEG2EI16_V }, // 4700
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF4, VLUXSEG2EI16_V }, // 4701
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, VLUXSEG2EI16_V }, // 4702
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF8, VLUXSEG2EI16_V }, // 4703
|
|
{ PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, VLUXSEG2EI16_V }, // 4704
|
|
{ PseudoVLUXSEG2EI32_V_M1_M1, VLUXSEG2EI32_V }, // 4705
|
|
{ PseudoVLUXSEG2EI32_V_M1_M1_MASK, VLUXSEG2EI32_V }, // 4706
|
|
{ PseudoVLUXSEG2EI32_V_M1_M2, VLUXSEG2EI32_V }, // 4707
|
|
{ PseudoVLUXSEG2EI32_V_M1_M2_MASK, VLUXSEG2EI32_V }, // 4708
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF2, VLUXSEG2EI32_V }, // 4709
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF2_MASK, VLUXSEG2EI32_V }, // 4710
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF4, VLUXSEG2EI32_V }, // 4711
|
|
{ PseudoVLUXSEG2EI32_V_M1_MF4_MASK, VLUXSEG2EI32_V }, // 4712
|
|
{ PseudoVLUXSEG2EI32_V_M2_M1, VLUXSEG2EI32_V }, // 4713
|
|
{ PseudoVLUXSEG2EI32_V_M2_M1_MASK, VLUXSEG2EI32_V }, // 4714
|
|
{ PseudoVLUXSEG2EI32_V_M2_M2, VLUXSEG2EI32_V }, // 4715
|
|
{ PseudoVLUXSEG2EI32_V_M2_M2_MASK, VLUXSEG2EI32_V }, // 4716
|
|
{ PseudoVLUXSEG2EI32_V_M2_M4, VLUXSEG2EI32_V }, // 4717
|
|
{ PseudoVLUXSEG2EI32_V_M2_M4_MASK, VLUXSEG2EI32_V }, // 4718
|
|
{ PseudoVLUXSEG2EI32_V_M2_MF2, VLUXSEG2EI32_V }, // 4719
|
|
{ PseudoVLUXSEG2EI32_V_M2_MF2_MASK, VLUXSEG2EI32_V }, // 4720
|
|
{ PseudoVLUXSEG2EI32_V_M4_M1, VLUXSEG2EI32_V }, // 4721
|
|
{ PseudoVLUXSEG2EI32_V_M4_M1_MASK, VLUXSEG2EI32_V }, // 4722
|
|
{ PseudoVLUXSEG2EI32_V_M4_M2, VLUXSEG2EI32_V }, // 4723
|
|
{ PseudoVLUXSEG2EI32_V_M4_M2_MASK, VLUXSEG2EI32_V }, // 4724
|
|
{ PseudoVLUXSEG2EI32_V_M4_M4, VLUXSEG2EI32_V }, // 4725
|
|
{ PseudoVLUXSEG2EI32_V_M4_M4_MASK, VLUXSEG2EI32_V }, // 4726
|
|
{ PseudoVLUXSEG2EI32_V_M8_M2, VLUXSEG2EI32_V }, // 4727
|
|
{ PseudoVLUXSEG2EI32_V_M8_M2_MASK, VLUXSEG2EI32_V }, // 4728
|
|
{ PseudoVLUXSEG2EI32_V_M8_M4, VLUXSEG2EI32_V }, // 4729
|
|
{ PseudoVLUXSEG2EI32_V_M8_M4_MASK, VLUXSEG2EI32_V }, // 4730
|
|
{ PseudoVLUXSEG2EI32_V_MF2_M1, VLUXSEG2EI32_V }, // 4731
|
|
{ PseudoVLUXSEG2EI32_V_MF2_M1_MASK, VLUXSEG2EI32_V }, // 4732
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF2, VLUXSEG2EI32_V }, // 4733
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, VLUXSEG2EI32_V }, // 4734
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF4, VLUXSEG2EI32_V }, // 4735
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, VLUXSEG2EI32_V }, // 4736
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF8, VLUXSEG2EI32_V }, // 4737
|
|
{ PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, VLUXSEG2EI32_V }, // 4738
|
|
{ PseudoVLUXSEG2EI64_V_M1_M1, VLUXSEG2EI64_V }, // 4739
|
|
{ PseudoVLUXSEG2EI64_V_M1_M1_MASK, VLUXSEG2EI64_V }, // 4740
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF2, VLUXSEG2EI64_V }, // 4741
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF2_MASK, VLUXSEG2EI64_V }, // 4742
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF4, VLUXSEG2EI64_V }, // 4743
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF4_MASK, VLUXSEG2EI64_V }, // 4744
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF8, VLUXSEG2EI64_V }, // 4745
|
|
{ PseudoVLUXSEG2EI64_V_M1_MF8_MASK, VLUXSEG2EI64_V }, // 4746
|
|
{ PseudoVLUXSEG2EI64_V_M2_M1, VLUXSEG2EI64_V }, // 4747
|
|
{ PseudoVLUXSEG2EI64_V_M2_M1_MASK, VLUXSEG2EI64_V }, // 4748
|
|
{ PseudoVLUXSEG2EI64_V_M2_M2, VLUXSEG2EI64_V }, // 4749
|
|
{ PseudoVLUXSEG2EI64_V_M2_M2_MASK, VLUXSEG2EI64_V }, // 4750
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF2, VLUXSEG2EI64_V }, // 4751
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF2_MASK, VLUXSEG2EI64_V }, // 4752
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF4, VLUXSEG2EI64_V }, // 4753
|
|
{ PseudoVLUXSEG2EI64_V_M2_MF4_MASK, VLUXSEG2EI64_V }, // 4754
|
|
{ PseudoVLUXSEG2EI64_V_M4_M1, VLUXSEG2EI64_V }, // 4755
|
|
{ PseudoVLUXSEG2EI64_V_M4_M1_MASK, VLUXSEG2EI64_V }, // 4756
|
|
{ PseudoVLUXSEG2EI64_V_M4_M2, VLUXSEG2EI64_V }, // 4757
|
|
{ PseudoVLUXSEG2EI64_V_M4_M2_MASK, VLUXSEG2EI64_V }, // 4758
|
|
{ PseudoVLUXSEG2EI64_V_M4_M4, VLUXSEG2EI64_V }, // 4759
|
|
{ PseudoVLUXSEG2EI64_V_M4_M4_MASK, VLUXSEG2EI64_V }, // 4760
|
|
{ PseudoVLUXSEG2EI64_V_M4_MF2, VLUXSEG2EI64_V }, // 4761
|
|
{ PseudoVLUXSEG2EI64_V_M4_MF2_MASK, VLUXSEG2EI64_V }, // 4762
|
|
{ PseudoVLUXSEG2EI64_V_M8_M1, VLUXSEG2EI64_V }, // 4763
|
|
{ PseudoVLUXSEG2EI64_V_M8_M1_MASK, VLUXSEG2EI64_V }, // 4764
|
|
{ PseudoVLUXSEG2EI64_V_M8_M2, VLUXSEG2EI64_V }, // 4765
|
|
{ PseudoVLUXSEG2EI64_V_M8_M2_MASK, VLUXSEG2EI64_V }, // 4766
|
|
{ PseudoVLUXSEG2EI64_V_M8_M4, VLUXSEG2EI64_V }, // 4767
|
|
{ PseudoVLUXSEG2EI64_V_M8_M4_MASK, VLUXSEG2EI64_V }, // 4768
|
|
{ PseudoVLUXSEG2EI8_V_M1_M1, VLUXSEG2EI8_V }, // 4769
|
|
{ PseudoVLUXSEG2EI8_V_M1_M1_MASK, VLUXSEG2EI8_V }, // 4770
|
|
{ PseudoVLUXSEG2EI8_V_M1_M2, VLUXSEG2EI8_V }, // 4771
|
|
{ PseudoVLUXSEG2EI8_V_M1_M2_MASK, VLUXSEG2EI8_V }, // 4772
|
|
{ PseudoVLUXSEG2EI8_V_M1_M4, VLUXSEG2EI8_V }, // 4773
|
|
{ PseudoVLUXSEG2EI8_V_M1_M4_MASK, VLUXSEG2EI8_V }, // 4774
|
|
{ PseudoVLUXSEG2EI8_V_M2_M2, VLUXSEG2EI8_V }, // 4775
|
|
{ PseudoVLUXSEG2EI8_V_M2_M2_MASK, VLUXSEG2EI8_V }, // 4776
|
|
{ PseudoVLUXSEG2EI8_V_M2_M4, VLUXSEG2EI8_V }, // 4777
|
|
{ PseudoVLUXSEG2EI8_V_M2_M4_MASK, VLUXSEG2EI8_V }, // 4778
|
|
{ PseudoVLUXSEG2EI8_V_M4_M4, VLUXSEG2EI8_V }, // 4779
|
|
{ PseudoVLUXSEG2EI8_V_M4_M4_MASK, VLUXSEG2EI8_V }, // 4780
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M1, VLUXSEG2EI8_V }, // 4781
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M1_MASK, VLUXSEG2EI8_V }, // 4782
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M2, VLUXSEG2EI8_V }, // 4783
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M2_MASK, VLUXSEG2EI8_V }, // 4784
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M4, VLUXSEG2EI8_V }, // 4785
|
|
{ PseudoVLUXSEG2EI8_V_MF2_M4_MASK, VLUXSEG2EI8_V }, // 4786
|
|
{ PseudoVLUXSEG2EI8_V_MF2_MF2, VLUXSEG2EI8_V }, // 4787
|
|
{ PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, VLUXSEG2EI8_V }, // 4788
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M1, VLUXSEG2EI8_V }, // 4789
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M1_MASK, VLUXSEG2EI8_V }, // 4790
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M2, VLUXSEG2EI8_V }, // 4791
|
|
{ PseudoVLUXSEG2EI8_V_MF4_M2_MASK, VLUXSEG2EI8_V }, // 4792
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF2, VLUXSEG2EI8_V }, // 4793
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, VLUXSEG2EI8_V }, // 4794
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF4, VLUXSEG2EI8_V }, // 4795
|
|
{ PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, VLUXSEG2EI8_V }, // 4796
|
|
{ PseudoVLUXSEG2EI8_V_MF8_M1, VLUXSEG2EI8_V }, // 4797
|
|
{ PseudoVLUXSEG2EI8_V_MF8_M1_MASK, VLUXSEG2EI8_V }, // 4798
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF2, VLUXSEG2EI8_V }, // 4799
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, VLUXSEG2EI8_V }, // 4800
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF4, VLUXSEG2EI8_V }, // 4801
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, VLUXSEG2EI8_V }, // 4802
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF8, VLUXSEG2EI8_V }, // 4803
|
|
{ PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, VLUXSEG2EI8_V }, // 4804
|
|
{ PseudoVLUXSEG3EI16_V_M1_M1, VLUXSEG3EI16_V }, // 4805
|
|
{ PseudoVLUXSEG3EI16_V_M1_M1_MASK, VLUXSEG3EI16_V }, // 4806
|
|
{ PseudoVLUXSEG3EI16_V_M1_M2, VLUXSEG3EI16_V }, // 4807
|
|
{ PseudoVLUXSEG3EI16_V_M1_M2_MASK, VLUXSEG3EI16_V }, // 4808
|
|
{ PseudoVLUXSEG3EI16_V_M1_MF2, VLUXSEG3EI16_V }, // 4809
|
|
{ PseudoVLUXSEG3EI16_V_M1_MF2_MASK, VLUXSEG3EI16_V }, // 4810
|
|
{ PseudoVLUXSEG3EI16_V_M2_M1, VLUXSEG3EI16_V }, // 4811
|
|
{ PseudoVLUXSEG3EI16_V_M2_M1_MASK, VLUXSEG3EI16_V }, // 4812
|
|
{ PseudoVLUXSEG3EI16_V_M2_M2, VLUXSEG3EI16_V }, // 4813
|
|
{ PseudoVLUXSEG3EI16_V_M2_M2_MASK, VLUXSEG3EI16_V }, // 4814
|
|
{ PseudoVLUXSEG3EI16_V_M4_M2, VLUXSEG3EI16_V }, // 4815
|
|
{ PseudoVLUXSEG3EI16_V_M4_M2_MASK, VLUXSEG3EI16_V }, // 4816
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M1, VLUXSEG3EI16_V }, // 4817
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M1_MASK, VLUXSEG3EI16_V }, // 4818
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M2, VLUXSEG3EI16_V }, // 4819
|
|
{ PseudoVLUXSEG3EI16_V_MF2_M2_MASK, VLUXSEG3EI16_V }, // 4820
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF2, VLUXSEG3EI16_V }, // 4821
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, VLUXSEG3EI16_V }, // 4822
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF4, VLUXSEG3EI16_V }, // 4823
|
|
{ PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, VLUXSEG3EI16_V }, // 4824
|
|
{ PseudoVLUXSEG3EI16_V_MF4_M1, VLUXSEG3EI16_V }, // 4825
|
|
{ PseudoVLUXSEG3EI16_V_MF4_M1_MASK, VLUXSEG3EI16_V }, // 4826
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF2, VLUXSEG3EI16_V }, // 4827
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, VLUXSEG3EI16_V }, // 4828
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF4, VLUXSEG3EI16_V }, // 4829
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, VLUXSEG3EI16_V }, // 4830
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF8, VLUXSEG3EI16_V }, // 4831
|
|
{ PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, VLUXSEG3EI16_V }, // 4832
|
|
{ PseudoVLUXSEG3EI32_V_M1_M1, VLUXSEG3EI32_V }, // 4833
|
|
{ PseudoVLUXSEG3EI32_V_M1_M1_MASK, VLUXSEG3EI32_V }, // 4834
|
|
{ PseudoVLUXSEG3EI32_V_M1_M2, VLUXSEG3EI32_V }, // 4835
|
|
{ PseudoVLUXSEG3EI32_V_M1_M2_MASK, VLUXSEG3EI32_V }, // 4836
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF2, VLUXSEG3EI32_V }, // 4837
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF2_MASK, VLUXSEG3EI32_V }, // 4838
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF4, VLUXSEG3EI32_V }, // 4839
|
|
{ PseudoVLUXSEG3EI32_V_M1_MF4_MASK, VLUXSEG3EI32_V }, // 4840
|
|
{ PseudoVLUXSEG3EI32_V_M2_M1, VLUXSEG3EI32_V }, // 4841
|
|
{ PseudoVLUXSEG3EI32_V_M2_M1_MASK, VLUXSEG3EI32_V }, // 4842
|
|
{ PseudoVLUXSEG3EI32_V_M2_M2, VLUXSEG3EI32_V }, // 4843
|
|
{ PseudoVLUXSEG3EI32_V_M2_M2_MASK, VLUXSEG3EI32_V }, // 4844
|
|
{ PseudoVLUXSEG3EI32_V_M2_MF2, VLUXSEG3EI32_V }, // 4845
|
|
{ PseudoVLUXSEG3EI32_V_M2_MF2_MASK, VLUXSEG3EI32_V }, // 4846
|
|
{ PseudoVLUXSEG3EI32_V_M4_M1, VLUXSEG3EI32_V }, // 4847
|
|
{ PseudoVLUXSEG3EI32_V_M4_M1_MASK, VLUXSEG3EI32_V }, // 4848
|
|
{ PseudoVLUXSEG3EI32_V_M4_M2, VLUXSEG3EI32_V }, // 4849
|
|
{ PseudoVLUXSEG3EI32_V_M4_M2_MASK, VLUXSEG3EI32_V }, // 4850
|
|
{ PseudoVLUXSEG3EI32_V_M8_M2, VLUXSEG3EI32_V }, // 4851
|
|
{ PseudoVLUXSEG3EI32_V_M8_M2_MASK, VLUXSEG3EI32_V }, // 4852
|
|
{ PseudoVLUXSEG3EI32_V_MF2_M1, VLUXSEG3EI32_V }, // 4853
|
|
{ PseudoVLUXSEG3EI32_V_MF2_M1_MASK, VLUXSEG3EI32_V }, // 4854
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF2, VLUXSEG3EI32_V }, // 4855
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, VLUXSEG3EI32_V }, // 4856
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF4, VLUXSEG3EI32_V }, // 4857
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, VLUXSEG3EI32_V }, // 4858
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF8, VLUXSEG3EI32_V }, // 4859
|
|
{ PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, VLUXSEG3EI32_V }, // 4860
|
|
{ PseudoVLUXSEG3EI64_V_M1_M1, VLUXSEG3EI64_V }, // 4861
|
|
{ PseudoVLUXSEG3EI64_V_M1_M1_MASK, VLUXSEG3EI64_V }, // 4862
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF2, VLUXSEG3EI64_V }, // 4863
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF2_MASK, VLUXSEG3EI64_V }, // 4864
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF4, VLUXSEG3EI64_V }, // 4865
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF4_MASK, VLUXSEG3EI64_V }, // 4866
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF8, VLUXSEG3EI64_V }, // 4867
|
|
{ PseudoVLUXSEG3EI64_V_M1_MF8_MASK, VLUXSEG3EI64_V }, // 4868
|
|
{ PseudoVLUXSEG3EI64_V_M2_M1, VLUXSEG3EI64_V }, // 4869
|
|
{ PseudoVLUXSEG3EI64_V_M2_M1_MASK, VLUXSEG3EI64_V }, // 4870
|
|
{ PseudoVLUXSEG3EI64_V_M2_M2, VLUXSEG3EI64_V }, // 4871
|
|
{ PseudoVLUXSEG3EI64_V_M2_M2_MASK, VLUXSEG3EI64_V }, // 4872
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF2, VLUXSEG3EI64_V }, // 4873
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF2_MASK, VLUXSEG3EI64_V }, // 4874
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF4, VLUXSEG3EI64_V }, // 4875
|
|
{ PseudoVLUXSEG3EI64_V_M2_MF4_MASK, VLUXSEG3EI64_V }, // 4876
|
|
{ PseudoVLUXSEG3EI64_V_M4_M1, VLUXSEG3EI64_V }, // 4877
|
|
{ PseudoVLUXSEG3EI64_V_M4_M1_MASK, VLUXSEG3EI64_V }, // 4878
|
|
{ PseudoVLUXSEG3EI64_V_M4_M2, VLUXSEG3EI64_V }, // 4879
|
|
{ PseudoVLUXSEG3EI64_V_M4_M2_MASK, VLUXSEG3EI64_V }, // 4880
|
|
{ PseudoVLUXSEG3EI64_V_M4_MF2, VLUXSEG3EI64_V }, // 4881
|
|
{ PseudoVLUXSEG3EI64_V_M4_MF2_MASK, VLUXSEG3EI64_V }, // 4882
|
|
{ PseudoVLUXSEG3EI64_V_M8_M1, VLUXSEG3EI64_V }, // 4883
|
|
{ PseudoVLUXSEG3EI64_V_M8_M1_MASK, VLUXSEG3EI64_V }, // 4884
|
|
{ PseudoVLUXSEG3EI64_V_M8_M2, VLUXSEG3EI64_V }, // 4885
|
|
{ PseudoVLUXSEG3EI64_V_M8_M2_MASK, VLUXSEG3EI64_V }, // 4886
|
|
{ PseudoVLUXSEG3EI8_V_M1_M1, VLUXSEG3EI8_V }, // 4887
|
|
{ PseudoVLUXSEG3EI8_V_M1_M1_MASK, VLUXSEG3EI8_V }, // 4888
|
|
{ PseudoVLUXSEG3EI8_V_M1_M2, VLUXSEG3EI8_V }, // 4889
|
|
{ PseudoVLUXSEG3EI8_V_M1_M2_MASK, VLUXSEG3EI8_V }, // 4890
|
|
{ PseudoVLUXSEG3EI8_V_M2_M2, VLUXSEG3EI8_V }, // 4891
|
|
{ PseudoVLUXSEG3EI8_V_M2_M2_MASK, VLUXSEG3EI8_V }, // 4892
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M1, VLUXSEG3EI8_V }, // 4893
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M1_MASK, VLUXSEG3EI8_V }, // 4894
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M2, VLUXSEG3EI8_V }, // 4895
|
|
{ PseudoVLUXSEG3EI8_V_MF2_M2_MASK, VLUXSEG3EI8_V }, // 4896
|
|
{ PseudoVLUXSEG3EI8_V_MF2_MF2, VLUXSEG3EI8_V }, // 4897
|
|
{ PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, VLUXSEG3EI8_V }, // 4898
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M1, VLUXSEG3EI8_V }, // 4899
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M1_MASK, VLUXSEG3EI8_V }, // 4900
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M2, VLUXSEG3EI8_V }, // 4901
|
|
{ PseudoVLUXSEG3EI8_V_MF4_M2_MASK, VLUXSEG3EI8_V }, // 4902
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF2, VLUXSEG3EI8_V }, // 4903
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, VLUXSEG3EI8_V }, // 4904
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF4, VLUXSEG3EI8_V }, // 4905
|
|
{ PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, VLUXSEG3EI8_V }, // 4906
|
|
{ PseudoVLUXSEG3EI8_V_MF8_M1, VLUXSEG3EI8_V }, // 4907
|
|
{ PseudoVLUXSEG3EI8_V_MF8_M1_MASK, VLUXSEG3EI8_V }, // 4908
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF2, VLUXSEG3EI8_V }, // 4909
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, VLUXSEG3EI8_V }, // 4910
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF4, VLUXSEG3EI8_V }, // 4911
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, VLUXSEG3EI8_V }, // 4912
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF8, VLUXSEG3EI8_V }, // 4913
|
|
{ PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, VLUXSEG3EI8_V }, // 4914
|
|
{ PseudoVLUXSEG4EI16_V_M1_M1, VLUXSEG4EI16_V }, // 4915
|
|
{ PseudoVLUXSEG4EI16_V_M1_M1_MASK, VLUXSEG4EI16_V }, // 4916
|
|
{ PseudoVLUXSEG4EI16_V_M1_M2, VLUXSEG4EI16_V }, // 4917
|
|
{ PseudoVLUXSEG4EI16_V_M1_M2_MASK, VLUXSEG4EI16_V }, // 4918
|
|
{ PseudoVLUXSEG4EI16_V_M1_MF2, VLUXSEG4EI16_V }, // 4919
|
|
{ PseudoVLUXSEG4EI16_V_M1_MF2_MASK, VLUXSEG4EI16_V }, // 4920
|
|
{ PseudoVLUXSEG4EI16_V_M2_M1, VLUXSEG4EI16_V }, // 4921
|
|
{ PseudoVLUXSEG4EI16_V_M2_M1_MASK, VLUXSEG4EI16_V }, // 4922
|
|
{ PseudoVLUXSEG4EI16_V_M2_M2, VLUXSEG4EI16_V }, // 4923
|
|
{ PseudoVLUXSEG4EI16_V_M2_M2_MASK, VLUXSEG4EI16_V }, // 4924
|
|
{ PseudoVLUXSEG4EI16_V_M4_M2, VLUXSEG4EI16_V }, // 4925
|
|
{ PseudoVLUXSEG4EI16_V_M4_M2_MASK, VLUXSEG4EI16_V }, // 4926
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M1, VLUXSEG4EI16_V }, // 4927
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M1_MASK, VLUXSEG4EI16_V }, // 4928
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M2, VLUXSEG4EI16_V }, // 4929
|
|
{ PseudoVLUXSEG4EI16_V_MF2_M2_MASK, VLUXSEG4EI16_V }, // 4930
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF2, VLUXSEG4EI16_V }, // 4931
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, VLUXSEG4EI16_V }, // 4932
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF4, VLUXSEG4EI16_V }, // 4933
|
|
{ PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, VLUXSEG4EI16_V }, // 4934
|
|
{ PseudoVLUXSEG4EI16_V_MF4_M1, VLUXSEG4EI16_V }, // 4935
|
|
{ PseudoVLUXSEG4EI16_V_MF4_M1_MASK, VLUXSEG4EI16_V }, // 4936
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF2, VLUXSEG4EI16_V }, // 4937
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, VLUXSEG4EI16_V }, // 4938
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF4, VLUXSEG4EI16_V }, // 4939
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, VLUXSEG4EI16_V }, // 4940
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF8, VLUXSEG4EI16_V }, // 4941
|
|
{ PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, VLUXSEG4EI16_V }, // 4942
|
|
{ PseudoVLUXSEG4EI32_V_M1_M1, VLUXSEG4EI32_V }, // 4943
|
|
{ PseudoVLUXSEG4EI32_V_M1_M1_MASK, VLUXSEG4EI32_V }, // 4944
|
|
{ PseudoVLUXSEG4EI32_V_M1_M2, VLUXSEG4EI32_V }, // 4945
|
|
{ PseudoVLUXSEG4EI32_V_M1_M2_MASK, VLUXSEG4EI32_V }, // 4946
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF2, VLUXSEG4EI32_V }, // 4947
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF2_MASK, VLUXSEG4EI32_V }, // 4948
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF4, VLUXSEG4EI32_V }, // 4949
|
|
{ PseudoVLUXSEG4EI32_V_M1_MF4_MASK, VLUXSEG4EI32_V }, // 4950
|
|
{ PseudoVLUXSEG4EI32_V_M2_M1, VLUXSEG4EI32_V }, // 4951
|
|
{ PseudoVLUXSEG4EI32_V_M2_M1_MASK, VLUXSEG4EI32_V }, // 4952
|
|
{ PseudoVLUXSEG4EI32_V_M2_M2, VLUXSEG4EI32_V }, // 4953
|
|
{ PseudoVLUXSEG4EI32_V_M2_M2_MASK, VLUXSEG4EI32_V }, // 4954
|
|
{ PseudoVLUXSEG4EI32_V_M2_MF2, VLUXSEG4EI32_V }, // 4955
|
|
{ PseudoVLUXSEG4EI32_V_M2_MF2_MASK, VLUXSEG4EI32_V }, // 4956
|
|
{ PseudoVLUXSEG4EI32_V_M4_M1, VLUXSEG4EI32_V }, // 4957
|
|
{ PseudoVLUXSEG4EI32_V_M4_M1_MASK, VLUXSEG4EI32_V }, // 4958
|
|
{ PseudoVLUXSEG4EI32_V_M4_M2, VLUXSEG4EI32_V }, // 4959
|
|
{ PseudoVLUXSEG4EI32_V_M4_M2_MASK, VLUXSEG4EI32_V }, // 4960
|
|
{ PseudoVLUXSEG4EI32_V_M8_M2, VLUXSEG4EI32_V }, // 4961
|
|
{ PseudoVLUXSEG4EI32_V_M8_M2_MASK, VLUXSEG4EI32_V }, // 4962
|
|
{ PseudoVLUXSEG4EI32_V_MF2_M1, VLUXSEG4EI32_V }, // 4963
|
|
{ PseudoVLUXSEG4EI32_V_MF2_M1_MASK, VLUXSEG4EI32_V }, // 4964
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF2, VLUXSEG4EI32_V }, // 4965
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, VLUXSEG4EI32_V }, // 4966
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF4, VLUXSEG4EI32_V }, // 4967
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, VLUXSEG4EI32_V }, // 4968
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF8, VLUXSEG4EI32_V }, // 4969
|
|
{ PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, VLUXSEG4EI32_V }, // 4970
|
|
{ PseudoVLUXSEG4EI64_V_M1_M1, VLUXSEG4EI64_V }, // 4971
|
|
{ PseudoVLUXSEG4EI64_V_M1_M1_MASK, VLUXSEG4EI64_V }, // 4972
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF2, VLUXSEG4EI64_V }, // 4973
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF2_MASK, VLUXSEG4EI64_V }, // 4974
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF4, VLUXSEG4EI64_V }, // 4975
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF4_MASK, VLUXSEG4EI64_V }, // 4976
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF8, VLUXSEG4EI64_V }, // 4977
|
|
{ PseudoVLUXSEG4EI64_V_M1_MF8_MASK, VLUXSEG4EI64_V }, // 4978
|
|
{ PseudoVLUXSEG4EI64_V_M2_M1, VLUXSEG4EI64_V }, // 4979
|
|
{ PseudoVLUXSEG4EI64_V_M2_M1_MASK, VLUXSEG4EI64_V }, // 4980
|
|
{ PseudoVLUXSEG4EI64_V_M2_M2, VLUXSEG4EI64_V }, // 4981
|
|
{ PseudoVLUXSEG4EI64_V_M2_M2_MASK, VLUXSEG4EI64_V }, // 4982
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF2, VLUXSEG4EI64_V }, // 4983
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF2_MASK, VLUXSEG4EI64_V }, // 4984
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF4, VLUXSEG4EI64_V }, // 4985
|
|
{ PseudoVLUXSEG4EI64_V_M2_MF4_MASK, VLUXSEG4EI64_V }, // 4986
|
|
{ PseudoVLUXSEG4EI64_V_M4_M1, VLUXSEG4EI64_V }, // 4987
|
|
{ PseudoVLUXSEG4EI64_V_M4_M1_MASK, VLUXSEG4EI64_V }, // 4988
|
|
{ PseudoVLUXSEG4EI64_V_M4_M2, VLUXSEG4EI64_V }, // 4989
|
|
{ PseudoVLUXSEG4EI64_V_M4_M2_MASK, VLUXSEG4EI64_V }, // 4990
|
|
{ PseudoVLUXSEG4EI64_V_M4_MF2, VLUXSEG4EI64_V }, // 4991
|
|
{ PseudoVLUXSEG4EI64_V_M4_MF2_MASK, VLUXSEG4EI64_V }, // 4992
|
|
{ PseudoVLUXSEG4EI64_V_M8_M1, VLUXSEG4EI64_V }, // 4993
|
|
{ PseudoVLUXSEG4EI64_V_M8_M1_MASK, VLUXSEG4EI64_V }, // 4994
|
|
{ PseudoVLUXSEG4EI64_V_M8_M2, VLUXSEG4EI64_V }, // 4995
|
|
{ PseudoVLUXSEG4EI64_V_M8_M2_MASK, VLUXSEG4EI64_V }, // 4996
|
|
{ PseudoVLUXSEG4EI8_V_M1_M1, VLUXSEG4EI8_V }, // 4997
|
|
{ PseudoVLUXSEG4EI8_V_M1_M1_MASK, VLUXSEG4EI8_V }, // 4998
|
|
{ PseudoVLUXSEG4EI8_V_M1_M2, VLUXSEG4EI8_V }, // 4999
|
|
{ PseudoVLUXSEG4EI8_V_M1_M2_MASK, VLUXSEG4EI8_V }, // 5000
|
|
{ PseudoVLUXSEG4EI8_V_M2_M2, VLUXSEG4EI8_V }, // 5001
|
|
{ PseudoVLUXSEG4EI8_V_M2_M2_MASK, VLUXSEG4EI8_V }, // 5002
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M1, VLUXSEG4EI8_V }, // 5003
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M1_MASK, VLUXSEG4EI8_V }, // 5004
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M2, VLUXSEG4EI8_V }, // 5005
|
|
{ PseudoVLUXSEG4EI8_V_MF2_M2_MASK, VLUXSEG4EI8_V }, // 5006
|
|
{ PseudoVLUXSEG4EI8_V_MF2_MF2, VLUXSEG4EI8_V }, // 5007
|
|
{ PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, VLUXSEG4EI8_V }, // 5008
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M1, VLUXSEG4EI8_V }, // 5009
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M1_MASK, VLUXSEG4EI8_V }, // 5010
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M2, VLUXSEG4EI8_V }, // 5011
|
|
{ PseudoVLUXSEG4EI8_V_MF4_M2_MASK, VLUXSEG4EI8_V }, // 5012
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF2, VLUXSEG4EI8_V }, // 5013
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, VLUXSEG4EI8_V }, // 5014
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF4, VLUXSEG4EI8_V }, // 5015
|
|
{ PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, VLUXSEG4EI8_V }, // 5016
|
|
{ PseudoVLUXSEG4EI8_V_MF8_M1, VLUXSEG4EI8_V }, // 5017
|
|
{ PseudoVLUXSEG4EI8_V_MF8_M1_MASK, VLUXSEG4EI8_V }, // 5018
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF2, VLUXSEG4EI8_V }, // 5019
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, VLUXSEG4EI8_V }, // 5020
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF4, VLUXSEG4EI8_V }, // 5021
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, VLUXSEG4EI8_V }, // 5022
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF8, VLUXSEG4EI8_V }, // 5023
|
|
{ PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, VLUXSEG4EI8_V }, // 5024
|
|
{ PseudoVLUXSEG5EI16_V_M1_M1, VLUXSEG5EI16_V }, // 5025
|
|
{ PseudoVLUXSEG5EI16_V_M1_M1_MASK, VLUXSEG5EI16_V }, // 5026
|
|
{ PseudoVLUXSEG5EI16_V_M1_MF2, VLUXSEG5EI16_V }, // 5027
|
|
{ PseudoVLUXSEG5EI16_V_M1_MF2_MASK, VLUXSEG5EI16_V }, // 5028
|
|
{ PseudoVLUXSEG5EI16_V_M2_M1, VLUXSEG5EI16_V }, // 5029
|
|
{ PseudoVLUXSEG5EI16_V_M2_M1_MASK, VLUXSEG5EI16_V }, // 5030
|
|
{ PseudoVLUXSEG5EI16_V_MF2_M1, VLUXSEG5EI16_V }, // 5031
|
|
{ PseudoVLUXSEG5EI16_V_MF2_M1_MASK, VLUXSEG5EI16_V }, // 5032
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF2, VLUXSEG5EI16_V }, // 5033
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, VLUXSEG5EI16_V }, // 5034
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF4, VLUXSEG5EI16_V }, // 5035
|
|
{ PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, VLUXSEG5EI16_V }, // 5036
|
|
{ PseudoVLUXSEG5EI16_V_MF4_M1, VLUXSEG5EI16_V }, // 5037
|
|
{ PseudoVLUXSEG5EI16_V_MF4_M1_MASK, VLUXSEG5EI16_V }, // 5038
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF2, VLUXSEG5EI16_V }, // 5039
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, VLUXSEG5EI16_V }, // 5040
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF4, VLUXSEG5EI16_V }, // 5041
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, VLUXSEG5EI16_V }, // 5042
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF8, VLUXSEG5EI16_V }, // 5043
|
|
{ PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, VLUXSEG5EI16_V }, // 5044
|
|
{ PseudoVLUXSEG5EI32_V_M1_M1, VLUXSEG5EI32_V }, // 5045
|
|
{ PseudoVLUXSEG5EI32_V_M1_M1_MASK, VLUXSEG5EI32_V }, // 5046
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF2, VLUXSEG5EI32_V }, // 5047
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF2_MASK, VLUXSEG5EI32_V }, // 5048
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF4, VLUXSEG5EI32_V }, // 5049
|
|
{ PseudoVLUXSEG5EI32_V_M1_MF4_MASK, VLUXSEG5EI32_V }, // 5050
|
|
{ PseudoVLUXSEG5EI32_V_M2_M1, VLUXSEG5EI32_V }, // 5051
|
|
{ PseudoVLUXSEG5EI32_V_M2_M1_MASK, VLUXSEG5EI32_V }, // 5052
|
|
{ PseudoVLUXSEG5EI32_V_M2_MF2, VLUXSEG5EI32_V }, // 5053
|
|
{ PseudoVLUXSEG5EI32_V_M2_MF2_MASK, VLUXSEG5EI32_V }, // 5054
|
|
{ PseudoVLUXSEG5EI32_V_M4_M1, VLUXSEG5EI32_V }, // 5055
|
|
{ PseudoVLUXSEG5EI32_V_M4_M1_MASK, VLUXSEG5EI32_V }, // 5056
|
|
{ PseudoVLUXSEG5EI32_V_MF2_M1, VLUXSEG5EI32_V }, // 5057
|
|
{ PseudoVLUXSEG5EI32_V_MF2_M1_MASK, VLUXSEG5EI32_V }, // 5058
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF2, VLUXSEG5EI32_V }, // 5059
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, VLUXSEG5EI32_V }, // 5060
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF4, VLUXSEG5EI32_V }, // 5061
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, VLUXSEG5EI32_V }, // 5062
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF8, VLUXSEG5EI32_V }, // 5063
|
|
{ PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, VLUXSEG5EI32_V }, // 5064
|
|
{ PseudoVLUXSEG5EI64_V_M1_M1, VLUXSEG5EI64_V }, // 5065
|
|
{ PseudoVLUXSEG5EI64_V_M1_M1_MASK, VLUXSEG5EI64_V }, // 5066
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF2, VLUXSEG5EI64_V }, // 5067
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF2_MASK, VLUXSEG5EI64_V }, // 5068
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF4, VLUXSEG5EI64_V }, // 5069
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF4_MASK, VLUXSEG5EI64_V }, // 5070
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF8, VLUXSEG5EI64_V }, // 5071
|
|
{ PseudoVLUXSEG5EI64_V_M1_MF8_MASK, VLUXSEG5EI64_V }, // 5072
|
|
{ PseudoVLUXSEG5EI64_V_M2_M1, VLUXSEG5EI64_V }, // 5073
|
|
{ PseudoVLUXSEG5EI64_V_M2_M1_MASK, VLUXSEG5EI64_V }, // 5074
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF2, VLUXSEG5EI64_V }, // 5075
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF2_MASK, VLUXSEG5EI64_V }, // 5076
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF4, VLUXSEG5EI64_V }, // 5077
|
|
{ PseudoVLUXSEG5EI64_V_M2_MF4_MASK, VLUXSEG5EI64_V }, // 5078
|
|
{ PseudoVLUXSEG5EI64_V_M4_M1, VLUXSEG5EI64_V }, // 5079
|
|
{ PseudoVLUXSEG5EI64_V_M4_M1_MASK, VLUXSEG5EI64_V }, // 5080
|
|
{ PseudoVLUXSEG5EI64_V_M4_MF2, VLUXSEG5EI64_V }, // 5081
|
|
{ PseudoVLUXSEG5EI64_V_M4_MF2_MASK, VLUXSEG5EI64_V }, // 5082
|
|
{ PseudoVLUXSEG5EI64_V_M8_M1, VLUXSEG5EI64_V }, // 5083
|
|
{ PseudoVLUXSEG5EI64_V_M8_M1_MASK, VLUXSEG5EI64_V }, // 5084
|
|
{ PseudoVLUXSEG5EI8_V_M1_M1, VLUXSEG5EI8_V }, // 5085
|
|
{ PseudoVLUXSEG5EI8_V_M1_M1_MASK, VLUXSEG5EI8_V }, // 5086
|
|
{ PseudoVLUXSEG5EI8_V_MF2_M1, VLUXSEG5EI8_V }, // 5087
|
|
{ PseudoVLUXSEG5EI8_V_MF2_M1_MASK, VLUXSEG5EI8_V }, // 5088
|
|
{ PseudoVLUXSEG5EI8_V_MF2_MF2, VLUXSEG5EI8_V }, // 5089
|
|
{ PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, VLUXSEG5EI8_V }, // 5090
|
|
{ PseudoVLUXSEG5EI8_V_MF4_M1, VLUXSEG5EI8_V }, // 5091
|
|
{ PseudoVLUXSEG5EI8_V_MF4_M1_MASK, VLUXSEG5EI8_V }, // 5092
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF2, VLUXSEG5EI8_V }, // 5093
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, VLUXSEG5EI8_V }, // 5094
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF4, VLUXSEG5EI8_V }, // 5095
|
|
{ PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, VLUXSEG5EI8_V }, // 5096
|
|
{ PseudoVLUXSEG5EI8_V_MF8_M1, VLUXSEG5EI8_V }, // 5097
|
|
{ PseudoVLUXSEG5EI8_V_MF8_M1_MASK, VLUXSEG5EI8_V }, // 5098
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF2, VLUXSEG5EI8_V }, // 5099
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, VLUXSEG5EI8_V }, // 5100
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF4, VLUXSEG5EI8_V }, // 5101
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, VLUXSEG5EI8_V }, // 5102
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF8, VLUXSEG5EI8_V }, // 5103
|
|
{ PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, VLUXSEG5EI8_V }, // 5104
|
|
{ PseudoVLUXSEG6EI16_V_M1_M1, VLUXSEG6EI16_V }, // 5105
|
|
{ PseudoVLUXSEG6EI16_V_M1_M1_MASK, VLUXSEG6EI16_V }, // 5106
|
|
{ PseudoVLUXSEG6EI16_V_M1_MF2, VLUXSEG6EI16_V }, // 5107
|
|
{ PseudoVLUXSEG6EI16_V_M1_MF2_MASK, VLUXSEG6EI16_V }, // 5108
|
|
{ PseudoVLUXSEG6EI16_V_M2_M1, VLUXSEG6EI16_V }, // 5109
|
|
{ PseudoVLUXSEG6EI16_V_M2_M1_MASK, VLUXSEG6EI16_V }, // 5110
|
|
{ PseudoVLUXSEG6EI16_V_MF2_M1, VLUXSEG6EI16_V }, // 5111
|
|
{ PseudoVLUXSEG6EI16_V_MF2_M1_MASK, VLUXSEG6EI16_V }, // 5112
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF2, VLUXSEG6EI16_V }, // 5113
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, VLUXSEG6EI16_V }, // 5114
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF4, VLUXSEG6EI16_V }, // 5115
|
|
{ PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, VLUXSEG6EI16_V }, // 5116
|
|
{ PseudoVLUXSEG6EI16_V_MF4_M1, VLUXSEG6EI16_V }, // 5117
|
|
{ PseudoVLUXSEG6EI16_V_MF4_M1_MASK, VLUXSEG6EI16_V }, // 5118
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF2, VLUXSEG6EI16_V }, // 5119
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, VLUXSEG6EI16_V }, // 5120
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF4, VLUXSEG6EI16_V }, // 5121
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, VLUXSEG6EI16_V }, // 5122
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF8, VLUXSEG6EI16_V }, // 5123
|
|
{ PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, VLUXSEG6EI16_V }, // 5124
|
|
{ PseudoVLUXSEG6EI32_V_M1_M1, VLUXSEG6EI32_V }, // 5125
|
|
{ PseudoVLUXSEG6EI32_V_M1_M1_MASK, VLUXSEG6EI32_V }, // 5126
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF2, VLUXSEG6EI32_V }, // 5127
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF2_MASK, VLUXSEG6EI32_V }, // 5128
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF4, VLUXSEG6EI32_V }, // 5129
|
|
{ PseudoVLUXSEG6EI32_V_M1_MF4_MASK, VLUXSEG6EI32_V }, // 5130
|
|
{ PseudoVLUXSEG6EI32_V_M2_M1, VLUXSEG6EI32_V }, // 5131
|
|
{ PseudoVLUXSEG6EI32_V_M2_M1_MASK, VLUXSEG6EI32_V }, // 5132
|
|
{ PseudoVLUXSEG6EI32_V_M2_MF2, VLUXSEG6EI32_V }, // 5133
|
|
{ PseudoVLUXSEG6EI32_V_M2_MF2_MASK, VLUXSEG6EI32_V }, // 5134
|
|
{ PseudoVLUXSEG6EI32_V_M4_M1, VLUXSEG6EI32_V }, // 5135
|
|
{ PseudoVLUXSEG6EI32_V_M4_M1_MASK, VLUXSEG6EI32_V }, // 5136
|
|
{ PseudoVLUXSEG6EI32_V_MF2_M1, VLUXSEG6EI32_V }, // 5137
|
|
{ PseudoVLUXSEG6EI32_V_MF2_M1_MASK, VLUXSEG6EI32_V }, // 5138
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF2, VLUXSEG6EI32_V }, // 5139
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, VLUXSEG6EI32_V }, // 5140
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF4, VLUXSEG6EI32_V }, // 5141
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, VLUXSEG6EI32_V }, // 5142
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF8, VLUXSEG6EI32_V }, // 5143
|
|
{ PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, VLUXSEG6EI32_V }, // 5144
|
|
{ PseudoVLUXSEG6EI64_V_M1_M1, VLUXSEG6EI64_V }, // 5145
|
|
{ PseudoVLUXSEG6EI64_V_M1_M1_MASK, VLUXSEG6EI64_V }, // 5146
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF2, VLUXSEG6EI64_V }, // 5147
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF2_MASK, VLUXSEG6EI64_V }, // 5148
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF4, VLUXSEG6EI64_V }, // 5149
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF4_MASK, VLUXSEG6EI64_V }, // 5150
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF8, VLUXSEG6EI64_V }, // 5151
|
|
{ PseudoVLUXSEG6EI64_V_M1_MF8_MASK, VLUXSEG6EI64_V }, // 5152
|
|
{ PseudoVLUXSEG6EI64_V_M2_M1, VLUXSEG6EI64_V }, // 5153
|
|
{ PseudoVLUXSEG6EI64_V_M2_M1_MASK, VLUXSEG6EI64_V }, // 5154
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF2, VLUXSEG6EI64_V }, // 5155
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF2_MASK, VLUXSEG6EI64_V }, // 5156
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF4, VLUXSEG6EI64_V }, // 5157
|
|
{ PseudoVLUXSEG6EI64_V_M2_MF4_MASK, VLUXSEG6EI64_V }, // 5158
|
|
{ PseudoVLUXSEG6EI64_V_M4_M1, VLUXSEG6EI64_V }, // 5159
|
|
{ PseudoVLUXSEG6EI64_V_M4_M1_MASK, VLUXSEG6EI64_V }, // 5160
|
|
{ PseudoVLUXSEG6EI64_V_M4_MF2, VLUXSEG6EI64_V }, // 5161
|
|
{ PseudoVLUXSEG6EI64_V_M4_MF2_MASK, VLUXSEG6EI64_V }, // 5162
|
|
{ PseudoVLUXSEG6EI64_V_M8_M1, VLUXSEG6EI64_V }, // 5163
|
|
{ PseudoVLUXSEG6EI64_V_M8_M1_MASK, VLUXSEG6EI64_V }, // 5164
|
|
{ PseudoVLUXSEG6EI8_V_M1_M1, VLUXSEG6EI8_V }, // 5165
|
|
{ PseudoVLUXSEG6EI8_V_M1_M1_MASK, VLUXSEG6EI8_V }, // 5166
|
|
{ PseudoVLUXSEG6EI8_V_MF2_M1, VLUXSEG6EI8_V }, // 5167
|
|
{ PseudoVLUXSEG6EI8_V_MF2_M1_MASK, VLUXSEG6EI8_V }, // 5168
|
|
{ PseudoVLUXSEG6EI8_V_MF2_MF2, VLUXSEG6EI8_V }, // 5169
|
|
{ PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, VLUXSEG6EI8_V }, // 5170
|
|
{ PseudoVLUXSEG6EI8_V_MF4_M1, VLUXSEG6EI8_V }, // 5171
|
|
{ PseudoVLUXSEG6EI8_V_MF4_M1_MASK, VLUXSEG6EI8_V }, // 5172
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF2, VLUXSEG6EI8_V }, // 5173
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, VLUXSEG6EI8_V }, // 5174
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF4, VLUXSEG6EI8_V }, // 5175
|
|
{ PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, VLUXSEG6EI8_V }, // 5176
|
|
{ PseudoVLUXSEG6EI8_V_MF8_M1, VLUXSEG6EI8_V }, // 5177
|
|
{ PseudoVLUXSEG6EI8_V_MF8_M1_MASK, VLUXSEG6EI8_V }, // 5178
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF2, VLUXSEG6EI8_V }, // 5179
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, VLUXSEG6EI8_V }, // 5180
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF4, VLUXSEG6EI8_V }, // 5181
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, VLUXSEG6EI8_V }, // 5182
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF8, VLUXSEG6EI8_V }, // 5183
|
|
{ PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, VLUXSEG6EI8_V }, // 5184
|
|
{ PseudoVLUXSEG7EI16_V_M1_M1, VLUXSEG7EI16_V }, // 5185
|
|
{ PseudoVLUXSEG7EI16_V_M1_M1_MASK, VLUXSEG7EI16_V }, // 5186
|
|
{ PseudoVLUXSEG7EI16_V_M1_MF2, VLUXSEG7EI16_V }, // 5187
|
|
{ PseudoVLUXSEG7EI16_V_M1_MF2_MASK, VLUXSEG7EI16_V }, // 5188
|
|
{ PseudoVLUXSEG7EI16_V_M2_M1, VLUXSEG7EI16_V }, // 5189
|
|
{ PseudoVLUXSEG7EI16_V_M2_M1_MASK, VLUXSEG7EI16_V }, // 5190
|
|
{ PseudoVLUXSEG7EI16_V_MF2_M1, VLUXSEG7EI16_V }, // 5191
|
|
{ PseudoVLUXSEG7EI16_V_MF2_M1_MASK, VLUXSEG7EI16_V }, // 5192
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF2, VLUXSEG7EI16_V }, // 5193
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, VLUXSEG7EI16_V }, // 5194
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF4, VLUXSEG7EI16_V }, // 5195
|
|
{ PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, VLUXSEG7EI16_V }, // 5196
|
|
{ PseudoVLUXSEG7EI16_V_MF4_M1, VLUXSEG7EI16_V }, // 5197
|
|
{ PseudoVLUXSEG7EI16_V_MF4_M1_MASK, VLUXSEG7EI16_V }, // 5198
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF2, VLUXSEG7EI16_V }, // 5199
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, VLUXSEG7EI16_V }, // 5200
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF4, VLUXSEG7EI16_V }, // 5201
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, VLUXSEG7EI16_V }, // 5202
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF8, VLUXSEG7EI16_V }, // 5203
|
|
{ PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, VLUXSEG7EI16_V }, // 5204
|
|
{ PseudoVLUXSEG7EI32_V_M1_M1, VLUXSEG7EI32_V }, // 5205
|
|
{ PseudoVLUXSEG7EI32_V_M1_M1_MASK, VLUXSEG7EI32_V }, // 5206
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF2, VLUXSEG7EI32_V }, // 5207
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF2_MASK, VLUXSEG7EI32_V }, // 5208
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF4, VLUXSEG7EI32_V }, // 5209
|
|
{ PseudoVLUXSEG7EI32_V_M1_MF4_MASK, VLUXSEG7EI32_V }, // 5210
|
|
{ PseudoVLUXSEG7EI32_V_M2_M1, VLUXSEG7EI32_V }, // 5211
|
|
{ PseudoVLUXSEG7EI32_V_M2_M1_MASK, VLUXSEG7EI32_V }, // 5212
|
|
{ PseudoVLUXSEG7EI32_V_M2_MF2, VLUXSEG7EI32_V }, // 5213
|
|
{ PseudoVLUXSEG7EI32_V_M2_MF2_MASK, VLUXSEG7EI32_V }, // 5214
|
|
{ PseudoVLUXSEG7EI32_V_M4_M1, VLUXSEG7EI32_V }, // 5215
|
|
{ PseudoVLUXSEG7EI32_V_M4_M1_MASK, VLUXSEG7EI32_V }, // 5216
|
|
{ PseudoVLUXSEG7EI32_V_MF2_M1, VLUXSEG7EI32_V }, // 5217
|
|
{ PseudoVLUXSEG7EI32_V_MF2_M1_MASK, VLUXSEG7EI32_V }, // 5218
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF2, VLUXSEG7EI32_V }, // 5219
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, VLUXSEG7EI32_V }, // 5220
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF4, VLUXSEG7EI32_V }, // 5221
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, VLUXSEG7EI32_V }, // 5222
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF8, VLUXSEG7EI32_V }, // 5223
|
|
{ PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, VLUXSEG7EI32_V }, // 5224
|
|
{ PseudoVLUXSEG7EI64_V_M1_M1, VLUXSEG7EI64_V }, // 5225
|
|
{ PseudoVLUXSEG7EI64_V_M1_M1_MASK, VLUXSEG7EI64_V }, // 5226
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF2, VLUXSEG7EI64_V }, // 5227
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF2_MASK, VLUXSEG7EI64_V }, // 5228
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF4, VLUXSEG7EI64_V }, // 5229
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF4_MASK, VLUXSEG7EI64_V }, // 5230
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF8, VLUXSEG7EI64_V }, // 5231
|
|
{ PseudoVLUXSEG7EI64_V_M1_MF8_MASK, VLUXSEG7EI64_V }, // 5232
|
|
{ PseudoVLUXSEG7EI64_V_M2_M1, VLUXSEG7EI64_V }, // 5233
|
|
{ PseudoVLUXSEG7EI64_V_M2_M1_MASK, VLUXSEG7EI64_V }, // 5234
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF2, VLUXSEG7EI64_V }, // 5235
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF2_MASK, VLUXSEG7EI64_V }, // 5236
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF4, VLUXSEG7EI64_V }, // 5237
|
|
{ PseudoVLUXSEG7EI64_V_M2_MF4_MASK, VLUXSEG7EI64_V }, // 5238
|
|
{ PseudoVLUXSEG7EI64_V_M4_M1, VLUXSEG7EI64_V }, // 5239
|
|
{ PseudoVLUXSEG7EI64_V_M4_M1_MASK, VLUXSEG7EI64_V }, // 5240
|
|
{ PseudoVLUXSEG7EI64_V_M4_MF2, VLUXSEG7EI64_V }, // 5241
|
|
{ PseudoVLUXSEG7EI64_V_M4_MF2_MASK, VLUXSEG7EI64_V }, // 5242
|
|
{ PseudoVLUXSEG7EI64_V_M8_M1, VLUXSEG7EI64_V }, // 5243
|
|
{ PseudoVLUXSEG7EI64_V_M8_M1_MASK, VLUXSEG7EI64_V }, // 5244
|
|
{ PseudoVLUXSEG7EI8_V_M1_M1, VLUXSEG7EI8_V }, // 5245
|
|
{ PseudoVLUXSEG7EI8_V_M1_M1_MASK, VLUXSEG7EI8_V }, // 5246
|
|
{ PseudoVLUXSEG7EI8_V_MF2_M1, VLUXSEG7EI8_V }, // 5247
|
|
{ PseudoVLUXSEG7EI8_V_MF2_M1_MASK, VLUXSEG7EI8_V }, // 5248
|
|
{ PseudoVLUXSEG7EI8_V_MF2_MF2, VLUXSEG7EI8_V }, // 5249
|
|
{ PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, VLUXSEG7EI8_V }, // 5250
|
|
{ PseudoVLUXSEG7EI8_V_MF4_M1, VLUXSEG7EI8_V }, // 5251
|
|
{ PseudoVLUXSEG7EI8_V_MF4_M1_MASK, VLUXSEG7EI8_V }, // 5252
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF2, VLUXSEG7EI8_V }, // 5253
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, VLUXSEG7EI8_V }, // 5254
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF4, VLUXSEG7EI8_V }, // 5255
|
|
{ PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, VLUXSEG7EI8_V }, // 5256
|
|
{ PseudoVLUXSEG7EI8_V_MF8_M1, VLUXSEG7EI8_V }, // 5257
|
|
{ PseudoVLUXSEG7EI8_V_MF8_M1_MASK, VLUXSEG7EI8_V }, // 5258
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF2, VLUXSEG7EI8_V }, // 5259
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, VLUXSEG7EI8_V }, // 5260
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF4, VLUXSEG7EI8_V }, // 5261
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, VLUXSEG7EI8_V }, // 5262
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF8, VLUXSEG7EI8_V }, // 5263
|
|
{ PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, VLUXSEG7EI8_V }, // 5264
|
|
{ PseudoVLUXSEG8EI16_V_M1_M1, VLUXSEG8EI16_V }, // 5265
|
|
{ PseudoVLUXSEG8EI16_V_M1_M1_MASK, VLUXSEG8EI16_V }, // 5266
|
|
{ PseudoVLUXSEG8EI16_V_M1_MF2, VLUXSEG8EI16_V }, // 5267
|
|
{ PseudoVLUXSEG8EI16_V_M1_MF2_MASK, VLUXSEG8EI16_V }, // 5268
|
|
{ PseudoVLUXSEG8EI16_V_M2_M1, VLUXSEG8EI16_V }, // 5269
|
|
{ PseudoVLUXSEG8EI16_V_M2_M1_MASK, VLUXSEG8EI16_V }, // 5270
|
|
{ PseudoVLUXSEG8EI16_V_MF2_M1, VLUXSEG8EI16_V }, // 5271
|
|
{ PseudoVLUXSEG8EI16_V_MF2_M1_MASK, VLUXSEG8EI16_V }, // 5272
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF2, VLUXSEG8EI16_V }, // 5273
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, VLUXSEG8EI16_V }, // 5274
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF4, VLUXSEG8EI16_V }, // 5275
|
|
{ PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, VLUXSEG8EI16_V }, // 5276
|
|
{ PseudoVLUXSEG8EI16_V_MF4_M1, VLUXSEG8EI16_V }, // 5277
|
|
{ PseudoVLUXSEG8EI16_V_MF4_M1_MASK, VLUXSEG8EI16_V }, // 5278
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF2, VLUXSEG8EI16_V }, // 5279
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, VLUXSEG8EI16_V }, // 5280
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF4, VLUXSEG8EI16_V }, // 5281
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, VLUXSEG8EI16_V }, // 5282
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF8, VLUXSEG8EI16_V }, // 5283
|
|
{ PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, VLUXSEG8EI16_V }, // 5284
|
|
{ PseudoVLUXSEG8EI32_V_M1_M1, VLUXSEG8EI32_V }, // 5285
|
|
{ PseudoVLUXSEG8EI32_V_M1_M1_MASK, VLUXSEG8EI32_V }, // 5286
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF2, VLUXSEG8EI32_V }, // 5287
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF2_MASK, VLUXSEG8EI32_V }, // 5288
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF4, VLUXSEG8EI32_V }, // 5289
|
|
{ PseudoVLUXSEG8EI32_V_M1_MF4_MASK, VLUXSEG8EI32_V }, // 5290
|
|
{ PseudoVLUXSEG8EI32_V_M2_M1, VLUXSEG8EI32_V }, // 5291
|
|
{ PseudoVLUXSEG8EI32_V_M2_M1_MASK, VLUXSEG8EI32_V }, // 5292
|
|
{ PseudoVLUXSEG8EI32_V_M2_MF2, VLUXSEG8EI32_V }, // 5293
|
|
{ PseudoVLUXSEG8EI32_V_M2_MF2_MASK, VLUXSEG8EI32_V }, // 5294
|
|
{ PseudoVLUXSEG8EI32_V_M4_M1, VLUXSEG8EI32_V }, // 5295
|
|
{ PseudoVLUXSEG8EI32_V_M4_M1_MASK, VLUXSEG8EI32_V }, // 5296
|
|
{ PseudoVLUXSEG8EI32_V_MF2_M1, VLUXSEG8EI32_V }, // 5297
|
|
{ PseudoVLUXSEG8EI32_V_MF2_M1_MASK, VLUXSEG8EI32_V }, // 5298
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF2, VLUXSEG8EI32_V }, // 5299
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, VLUXSEG8EI32_V }, // 5300
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF4, VLUXSEG8EI32_V }, // 5301
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, VLUXSEG8EI32_V }, // 5302
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF8, VLUXSEG8EI32_V }, // 5303
|
|
{ PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, VLUXSEG8EI32_V }, // 5304
|
|
{ PseudoVLUXSEG8EI64_V_M1_M1, VLUXSEG8EI64_V }, // 5305
|
|
{ PseudoVLUXSEG8EI64_V_M1_M1_MASK, VLUXSEG8EI64_V }, // 5306
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF2, VLUXSEG8EI64_V }, // 5307
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF2_MASK, VLUXSEG8EI64_V }, // 5308
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF4, VLUXSEG8EI64_V }, // 5309
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF4_MASK, VLUXSEG8EI64_V }, // 5310
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF8, VLUXSEG8EI64_V }, // 5311
|
|
{ PseudoVLUXSEG8EI64_V_M1_MF8_MASK, VLUXSEG8EI64_V }, // 5312
|
|
{ PseudoVLUXSEG8EI64_V_M2_M1, VLUXSEG8EI64_V }, // 5313
|
|
{ PseudoVLUXSEG8EI64_V_M2_M1_MASK, VLUXSEG8EI64_V }, // 5314
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF2, VLUXSEG8EI64_V }, // 5315
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF2_MASK, VLUXSEG8EI64_V }, // 5316
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF4, VLUXSEG8EI64_V }, // 5317
|
|
{ PseudoVLUXSEG8EI64_V_M2_MF4_MASK, VLUXSEG8EI64_V }, // 5318
|
|
{ PseudoVLUXSEG8EI64_V_M4_M1, VLUXSEG8EI64_V }, // 5319
|
|
{ PseudoVLUXSEG8EI64_V_M4_M1_MASK, VLUXSEG8EI64_V }, // 5320
|
|
{ PseudoVLUXSEG8EI64_V_M4_MF2, VLUXSEG8EI64_V }, // 5321
|
|
{ PseudoVLUXSEG8EI64_V_M4_MF2_MASK, VLUXSEG8EI64_V }, // 5322
|
|
{ PseudoVLUXSEG8EI64_V_M8_M1, VLUXSEG8EI64_V }, // 5323
|
|
{ PseudoVLUXSEG8EI64_V_M8_M1_MASK, VLUXSEG8EI64_V }, // 5324
|
|
{ PseudoVLUXSEG8EI8_V_M1_M1, VLUXSEG8EI8_V }, // 5325
|
|
{ PseudoVLUXSEG8EI8_V_M1_M1_MASK, VLUXSEG8EI8_V }, // 5326
|
|
{ PseudoVLUXSEG8EI8_V_MF2_M1, VLUXSEG8EI8_V }, // 5327
|
|
{ PseudoVLUXSEG8EI8_V_MF2_M1_MASK, VLUXSEG8EI8_V }, // 5328
|
|
{ PseudoVLUXSEG8EI8_V_MF2_MF2, VLUXSEG8EI8_V }, // 5329
|
|
{ PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, VLUXSEG8EI8_V }, // 5330
|
|
{ PseudoVLUXSEG8EI8_V_MF4_M1, VLUXSEG8EI8_V }, // 5331
|
|
{ PseudoVLUXSEG8EI8_V_MF4_M1_MASK, VLUXSEG8EI8_V }, // 5332
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF2, VLUXSEG8EI8_V }, // 5333
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, VLUXSEG8EI8_V }, // 5334
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF4, VLUXSEG8EI8_V }, // 5335
|
|
{ PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, VLUXSEG8EI8_V }, // 5336
|
|
{ PseudoVLUXSEG8EI8_V_MF8_M1, VLUXSEG8EI8_V }, // 5337
|
|
{ PseudoVLUXSEG8EI8_V_MF8_M1_MASK, VLUXSEG8EI8_V }, // 5338
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF2, VLUXSEG8EI8_V }, // 5339
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, VLUXSEG8EI8_V }, // 5340
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF4, VLUXSEG8EI8_V }, // 5341
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, VLUXSEG8EI8_V }, // 5342
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF8, VLUXSEG8EI8_V }, // 5343
|
|
{ PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, VLUXSEG8EI8_V }, // 5344
|
|
{ PseudoVMACC_VV_M1, VMACC_VV }, // 5345
|
|
{ PseudoVMACC_VV_M1_MASK, VMACC_VV }, // 5346
|
|
{ PseudoVMACC_VV_M2, VMACC_VV }, // 5347
|
|
{ PseudoVMACC_VV_M2_MASK, VMACC_VV }, // 5348
|
|
{ PseudoVMACC_VV_M4, VMACC_VV }, // 5349
|
|
{ PseudoVMACC_VV_M4_MASK, VMACC_VV }, // 5350
|
|
{ PseudoVMACC_VV_M8, VMACC_VV }, // 5351
|
|
{ PseudoVMACC_VV_M8_MASK, VMACC_VV }, // 5352
|
|
{ PseudoVMACC_VV_MF2, VMACC_VV }, // 5353
|
|
{ PseudoVMACC_VV_MF2_MASK, VMACC_VV }, // 5354
|
|
{ PseudoVMACC_VV_MF4, VMACC_VV }, // 5355
|
|
{ PseudoVMACC_VV_MF4_MASK, VMACC_VV }, // 5356
|
|
{ PseudoVMACC_VV_MF8, VMACC_VV }, // 5357
|
|
{ PseudoVMACC_VV_MF8_MASK, VMACC_VV }, // 5358
|
|
{ PseudoVMACC_VX_M1, VMACC_VX }, // 5359
|
|
{ PseudoVMACC_VX_M1_MASK, VMACC_VX }, // 5360
|
|
{ PseudoVMACC_VX_M2, VMACC_VX }, // 5361
|
|
{ PseudoVMACC_VX_M2_MASK, VMACC_VX }, // 5362
|
|
{ PseudoVMACC_VX_M4, VMACC_VX }, // 5363
|
|
{ PseudoVMACC_VX_M4_MASK, VMACC_VX }, // 5364
|
|
{ PseudoVMACC_VX_M8, VMACC_VX }, // 5365
|
|
{ PseudoVMACC_VX_M8_MASK, VMACC_VX }, // 5366
|
|
{ PseudoVMACC_VX_MF2, VMACC_VX }, // 5367
|
|
{ PseudoVMACC_VX_MF2_MASK, VMACC_VX }, // 5368
|
|
{ PseudoVMACC_VX_MF4, VMACC_VX }, // 5369
|
|
{ PseudoVMACC_VX_MF4_MASK, VMACC_VX }, // 5370
|
|
{ PseudoVMACC_VX_MF8, VMACC_VX }, // 5371
|
|
{ PseudoVMACC_VX_MF8_MASK, VMACC_VX }, // 5372
|
|
{ PseudoVMADC_VIM_M1, VMADC_VIM }, // 5373
|
|
{ PseudoVMADC_VIM_M2, VMADC_VIM }, // 5374
|
|
{ PseudoVMADC_VIM_M4, VMADC_VIM }, // 5375
|
|
{ PseudoVMADC_VIM_M8, VMADC_VIM }, // 5376
|
|
{ PseudoVMADC_VIM_MF2, VMADC_VIM }, // 5377
|
|
{ PseudoVMADC_VIM_MF4, VMADC_VIM }, // 5378
|
|
{ PseudoVMADC_VIM_MF8, VMADC_VIM }, // 5379
|
|
{ PseudoVMADC_VI_M1, VMADC_VI }, // 5380
|
|
{ PseudoVMADC_VI_M2, VMADC_VI }, // 5381
|
|
{ PseudoVMADC_VI_M4, VMADC_VI }, // 5382
|
|
{ PseudoVMADC_VI_M8, VMADC_VI }, // 5383
|
|
{ PseudoVMADC_VI_MF2, VMADC_VI }, // 5384
|
|
{ PseudoVMADC_VI_MF4, VMADC_VI }, // 5385
|
|
{ PseudoVMADC_VI_MF8, VMADC_VI }, // 5386
|
|
{ PseudoVMADC_VVM_M1, VMADC_VVM }, // 5387
|
|
{ PseudoVMADC_VVM_M2, VMADC_VVM }, // 5388
|
|
{ PseudoVMADC_VVM_M4, VMADC_VVM }, // 5389
|
|
{ PseudoVMADC_VVM_M8, VMADC_VVM }, // 5390
|
|
{ PseudoVMADC_VVM_MF2, VMADC_VVM }, // 5391
|
|
{ PseudoVMADC_VVM_MF4, VMADC_VVM }, // 5392
|
|
{ PseudoVMADC_VVM_MF8, VMADC_VVM }, // 5393
|
|
{ PseudoVMADC_VV_M1, VMADC_VV }, // 5394
|
|
{ PseudoVMADC_VV_M2, VMADC_VV }, // 5395
|
|
{ PseudoVMADC_VV_M4, VMADC_VV }, // 5396
|
|
{ PseudoVMADC_VV_M8, VMADC_VV }, // 5397
|
|
{ PseudoVMADC_VV_MF2, VMADC_VV }, // 5398
|
|
{ PseudoVMADC_VV_MF4, VMADC_VV }, // 5399
|
|
{ PseudoVMADC_VV_MF8, VMADC_VV }, // 5400
|
|
{ PseudoVMADC_VXM_M1, VMADC_VXM }, // 5401
|
|
{ PseudoVMADC_VXM_M2, VMADC_VXM }, // 5402
|
|
{ PseudoVMADC_VXM_M4, VMADC_VXM }, // 5403
|
|
{ PseudoVMADC_VXM_M8, VMADC_VXM }, // 5404
|
|
{ PseudoVMADC_VXM_MF2, VMADC_VXM }, // 5405
|
|
{ PseudoVMADC_VXM_MF4, VMADC_VXM }, // 5406
|
|
{ PseudoVMADC_VXM_MF8, VMADC_VXM }, // 5407
|
|
{ PseudoVMADC_VX_M1, VMADC_VX }, // 5408
|
|
{ PseudoVMADC_VX_M2, VMADC_VX }, // 5409
|
|
{ PseudoVMADC_VX_M4, VMADC_VX }, // 5410
|
|
{ PseudoVMADC_VX_M8, VMADC_VX }, // 5411
|
|
{ PseudoVMADC_VX_MF2, VMADC_VX }, // 5412
|
|
{ PseudoVMADC_VX_MF4, VMADC_VX }, // 5413
|
|
{ PseudoVMADC_VX_MF8, VMADC_VX }, // 5414
|
|
{ PseudoVMADD_VV_M1, VMADD_VV }, // 5415
|
|
{ PseudoVMADD_VV_M1_MASK, VMADD_VV }, // 5416
|
|
{ PseudoVMADD_VV_M2, VMADD_VV }, // 5417
|
|
{ PseudoVMADD_VV_M2_MASK, VMADD_VV }, // 5418
|
|
{ PseudoVMADD_VV_M4, VMADD_VV }, // 5419
|
|
{ PseudoVMADD_VV_M4_MASK, VMADD_VV }, // 5420
|
|
{ PseudoVMADD_VV_M8, VMADD_VV }, // 5421
|
|
{ PseudoVMADD_VV_M8_MASK, VMADD_VV }, // 5422
|
|
{ PseudoVMADD_VV_MF2, VMADD_VV }, // 5423
|
|
{ PseudoVMADD_VV_MF2_MASK, VMADD_VV }, // 5424
|
|
{ PseudoVMADD_VV_MF4, VMADD_VV }, // 5425
|
|
{ PseudoVMADD_VV_MF4_MASK, VMADD_VV }, // 5426
|
|
{ PseudoVMADD_VV_MF8, VMADD_VV }, // 5427
|
|
{ PseudoVMADD_VV_MF8_MASK, VMADD_VV }, // 5428
|
|
{ PseudoVMADD_VX_M1, VMADD_VX }, // 5429
|
|
{ PseudoVMADD_VX_M1_MASK, VMADD_VX }, // 5430
|
|
{ PseudoVMADD_VX_M2, VMADD_VX }, // 5431
|
|
{ PseudoVMADD_VX_M2_MASK, VMADD_VX }, // 5432
|
|
{ PseudoVMADD_VX_M4, VMADD_VX }, // 5433
|
|
{ PseudoVMADD_VX_M4_MASK, VMADD_VX }, // 5434
|
|
{ PseudoVMADD_VX_M8, VMADD_VX }, // 5435
|
|
{ PseudoVMADD_VX_M8_MASK, VMADD_VX }, // 5436
|
|
{ PseudoVMADD_VX_MF2, VMADD_VX }, // 5437
|
|
{ PseudoVMADD_VX_MF2_MASK, VMADD_VX }, // 5438
|
|
{ PseudoVMADD_VX_MF4, VMADD_VX }, // 5439
|
|
{ PseudoVMADD_VX_MF4_MASK, VMADD_VX }, // 5440
|
|
{ PseudoVMADD_VX_MF8, VMADD_VX }, // 5441
|
|
{ PseudoVMADD_VX_MF8_MASK, VMADD_VX }, // 5442
|
|
{ PseudoVMANDN_MM_M1, VMANDN_MM }, // 5443
|
|
{ PseudoVMANDN_MM_M2, VMANDN_MM }, // 5444
|
|
{ PseudoVMANDN_MM_M4, VMANDN_MM }, // 5445
|
|
{ PseudoVMANDN_MM_M8, VMANDN_MM }, // 5446
|
|
{ PseudoVMANDN_MM_MF2, VMANDN_MM }, // 5447
|
|
{ PseudoVMANDN_MM_MF4, VMANDN_MM }, // 5448
|
|
{ PseudoVMANDN_MM_MF8, VMANDN_MM }, // 5449
|
|
{ PseudoVMAND_MM_M1, VMAND_MM }, // 5450
|
|
{ PseudoVMAND_MM_M2, VMAND_MM }, // 5451
|
|
{ PseudoVMAND_MM_M4, VMAND_MM }, // 5452
|
|
{ PseudoVMAND_MM_M8, VMAND_MM }, // 5453
|
|
{ PseudoVMAND_MM_MF2, VMAND_MM }, // 5454
|
|
{ PseudoVMAND_MM_MF4, VMAND_MM }, // 5455
|
|
{ PseudoVMAND_MM_MF8, VMAND_MM }, // 5456
|
|
{ PseudoVMAXU_VV_M1, VMAXU_VV }, // 5457
|
|
{ PseudoVMAXU_VV_M1_MASK, VMAXU_VV }, // 5458
|
|
{ PseudoVMAXU_VV_M2, VMAXU_VV }, // 5459
|
|
{ PseudoVMAXU_VV_M2_MASK, VMAXU_VV }, // 5460
|
|
{ PseudoVMAXU_VV_M4, VMAXU_VV }, // 5461
|
|
{ PseudoVMAXU_VV_M4_MASK, VMAXU_VV }, // 5462
|
|
{ PseudoVMAXU_VV_M8, VMAXU_VV }, // 5463
|
|
{ PseudoVMAXU_VV_M8_MASK, VMAXU_VV }, // 5464
|
|
{ PseudoVMAXU_VV_MF2, VMAXU_VV }, // 5465
|
|
{ PseudoVMAXU_VV_MF2_MASK, VMAXU_VV }, // 5466
|
|
{ PseudoVMAXU_VV_MF4, VMAXU_VV }, // 5467
|
|
{ PseudoVMAXU_VV_MF4_MASK, VMAXU_VV }, // 5468
|
|
{ PseudoVMAXU_VV_MF8, VMAXU_VV }, // 5469
|
|
{ PseudoVMAXU_VV_MF8_MASK, VMAXU_VV }, // 5470
|
|
{ PseudoVMAXU_VX_M1, VMAXU_VX }, // 5471
|
|
{ PseudoVMAXU_VX_M1_MASK, VMAXU_VX }, // 5472
|
|
{ PseudoVMAXU_VX_M2, VMAXU_VX }, // 5473
|
|
{ PseudoVMAXU_VX_M2_MASK, VMAXU_VX }, // 5474
|
|
{ PseudoVMAXU_VX_M4, VMAXU_VX }, // 5475
|
|
{ PseudoVMAXU_VX_M4_MASK, VMAXU_VX }, // 5476
|
|
{ PseudoVMAXU_VX_M8, VMAXU_VX }, // 5477
|
|
{ PseudoVMAXU_VX_M8_MASK, VMAXU_VX }, // 5478
|
|
{ PseudoVMAXU_VX_MF2, VMAXU_VX }, // 5479
|
|
{ PseudoVMAXU_VX_MF2_MASK, VMAXU_VX }, // 5480
|
|
{ PseudoVMAXU_VX_MF4, VMAXU_VX }, // 5481
|
|
{ PseudoVMAXU_VX_MF4_MASK, VMAXU_VX }, // 5482
|
|
{ PseudoVMAXU_VX_MF8, VMAXU_VX }, // 5483
|
|
{ PseudoVMAXU_VX_MF8_MASK, VMAXU_VX }, // 5484
|
|
{ PseudoVMAX_VV_M1, VMAX_VV }, // 5485
|
|
{ PseudoVMAX_VV_M1_MASK, VMAX_VV }, // 5486
|
|
{ PseudoVMAX_VV_M2, VMAX_VV }, // 5487
|
|
{ PseudoVMAX_VV_M2_MASK, VMAX_VV }, // 5488
|
|
{ PseudoVMAX_VV_M4, VMAX_VV }, // 5489
|
|
{ PseudoVMAX_VV_M4_MASK, VMAX_VV }, // 5490
|
|
{ PseudoVMAX_VV_M8, VMAX_VV }, // 5491
|
|
{ PseudoVMAX_VV_M8_MASK, VMAX_VV }, // 5492
|
|
{ PseudoVMAX_VV_MF2, VMAX_VV }, // 5493
|
|
{ PseudoVMAX_VV_MF2_MASK, VMAX_VV }, // 5494
|
|
{ PseudoVMAX_VV_MF4, VMAX_VV }, // 5495
|
|
{ PseudoVMAX_VV_MF4_MASK, VMAX_VV }, // 5496
|
|
{ PseudoVMAX_VV_MF8, VMAX_VV }, // 5497
|
|
{ PseudoVMAX_VV_MF8_MASK, VMAX_VV }, // 5498
|
|
{ PseudoVMAX_VX_M1, VMAX_VX }, // 5499
|
|
{ PseudoVMAX_VX_M1_MASK, VMAX_VX }, // 5500
|
|
{ PseudoVMAX_VX_M2, VMAX_VX }, // 5501
|
|
{ PseudoVMAX_VX_M2_MASK, VMAX_VX }, // 5502
|
|
{ PseudoVMAX_VX_M4, VMAX_VX }, // 5503
|
|
{ PseudoVMAX_VX_M4_MASK, VMAX_VX }, // 5504
|
|
{ PseudoVMAX_VX_M8, VMAX_VX }, // 5505
|
|
{ PseudoVMAX_VX_M8_MASK, VMAX_VX }, // 5506
|
|
{ PseudoVMAX_VX_MF2, VMAX_VX }, // 5507
|
|
{ PseudoVMAX_VX_MF2_MASK, VMAX_VX }, // 5508
|
|
{ PseudoVMAX_VX_MF4, VMAX_VX }, // 5509
|
|
{ PseudoVMAX_VX_MF4_MASK, VMAX_VX }, // 5510
|
|
{ PseudoVMAX_VX_MF8, VMAX_VX }, // 5511
|
|
{ PseudoVMAX_VX_MF8_MASK, VMAX_VX }, // 5512
|
|
{ PseudoVMERGE_VIM_M1, VMERGE_VIM }, // 5513
|
|
{ PseudoVMERGE_VIM_M2, VMERGE_VIM }, // 5514
|
|
{ PseudoVMERGE_VIM_M4, VMERGE_VIM }, // 5515
|
|
{ PseudoVMERGE_VIM_M8, VMERGE_VIM }, // 5516
|
|
{ PseudoVMERGE_VIM_MF2, VMERGE_VIM }, // 5517
|
|
{ PseudoVMERGE_VIM_MF4, VMERGE_VIM }, // 5518
|
|
{ PseudoVMERGE_VIM_MF8, VMERGE_VIM }, // 5519
|
|
{ PseudoVMERGE_VVM_M1, VMERGE_VVM }, // 5520
|
|
{ PseudoVMERGE_VVM_M2, VMERGE_VVM }, // 5521
|
|
{ PseudoVMERGE_VVM_M4, VMERGE_VVM }, // 5522
|
|
{ PseudoVMERGE_VVM_M8, VMERGE_VVM }, // 5523
|
|
{ PseudoVMERGE_VVM_MF2, VMERGE_VVM }, // 5524
|
|
{ PseudoVMERGE_VVM_MF4, VMERGE_VVM }, // 5525
|
|
{ PseudoVMERGE_VVM_MF8, VMERGE_VVM }, // 5526
|
|
{ PseudoVMERGE_VXM_M1, VMERGE_VXM }, // 5527
|
|
{ PseudoVMERGE_VXM_M2, VMERGE_VXM }, // 5528
|
|
{ PseudoVMERGE_VXM_M4, VMERGE_VXM }, // 5529
|
|
{ PseudoVMERGE_VXM_M8, VMERGE_VXM }, // 5530
|
|
{ PseudoVMERGE_VXM_MF2, VMERGE_VXM }, // 5531
|
|
{ PseudoVMERGE_VXM_MF4, VMERGE_VXM }, // 5532
|
|
{ PseudoVMERGE_VXM_MF8, VMERGE_VXM }, // 5533
|
|
{ PseudoVMFEQ_VFPR16_M1, VMFEQ_VF }, // 5534
|
|
{ PseudoVMFEQ_VFPR16_M1_MASK, VMFEQ_VF }, // 5535
|
|
{ PseudoVMFEQ_VFPR16_M2, VMFEQ_VF }, // 5536
|
|
{ PseudoVMFEQ_VFPR16_M2_MASK, VMFEQ_VF }, // 5537
|
|
{ PseudoVMFEQ_VFPR16_M4, VMFEQ_VF }, // 5538
|
|
{ PseudoVMFEQ_VFPR16_M4_MASK, VMFEQ_VF }, // 5539
|
|
{ PseudoVMFEQ_VFPR16_M8, VMFEQ_VF }, // 5540
|
|
{ PseudoVMFEQ_VFPR16_M8_MASK, VMFEQ_VF }, // 5541
|
|
{ PseudoVMFEQ_VFPR16_MF2, VMFEQ_VF }, // 5542
|
|
{ PseudoVMFEQ_VFPR16_MF2_MASK, VMFEQ_VF }, // 5543
|
|
{ PseudoVMFEQ_VFPR16_MF4, VMFEQ_VF }, // 5544
|
|
{ PseudoVMFEQ_VFPR16_MF4_MASK, VMFEQ_VF }, // 5545
|
|
{ PseudoVMFEQ_VFPR32_M1, VMFEQ_VF }, // 5546
|
|
{ PseudoVMFEQ_VFPR32_M1_MASK, VMFEQ_VF }, // 5547
|
|
{ PseudoVMFEQ_VFPR32_M2, VMFEQ_VF }, // 5548
|
|
{ PseudoVMFEQ_VFPR32_M2_MASK, VMFEQ_VF }, // 5549
|
|
{ PseudoVMFEQ_VFPR32_M4, VMFEQ_VF }, // 5550
|
|
{ PseudoVMFEQ_VFPR32_M4_MASK, VMFEQ_VF }, // 5551
|
|
{ PseudoVMFEQ_VFPR32_M8, VMFEQ_VF }, // 5552
|
|
{ PseudoVMFEQ_VFPR32_M8_MASK, VMFEQ_VF }, // 5553
|
|
{ PseudoVMFEQ_VFPR32_MF2, VMFEQ_VF }, // 5554
|
|
{ PseudoVMFEQ_VFPR32_MF2_MASK, VMFEQ_VF }, // 5555
|
|
{ PseudoVMFEQ_VFPR64_M1, VMFEQ_VF }, // 5556
|
|
{ PseudoVMFEQ_VFPR64_M1_MASK, VMFEQ_VF }, // 5557
|
|
{ PseudoVMFEQ_VFPR64_M2, VMFEQ_VF }, // 5558
|
|
{ PseudoVMFEQ_VFPR64_M2_MASK, VMFEQ_VF }, // 5559
|
|
{ PseudoVMFEQ_VFPR64_M4, VMFEQ_VF }, // 5560
|
|
{ PseudoVMFEQ_VFPR64_M4_MASK, VMFEQ_VF }, // 5561
|
|
{ PseudoVMFEQ_VFPR64_M8, VMFEQ_VF }, // 5562
|
|
{ PseudoVMFEQ_VFPR64_M8_MASK, VMFEQ_VF }, // 5563
|
|
{ PseudoVMFEQ_VV_M1, VMFEQ_VV }, // 5564
|
|
{ PseudoVMFEQ_VV_M1_MASK, VMFEQ_VV }, // 5565
|
|
{ PseudoVMFEQ_VV_M2, VMFEQ_VV }, // 5566
|
|
{ PseudoVMFEQ_VV_M2_MASK, VMFEQ_VV }, // 5567
|
|
{ PseudoVMFEQ_VV_M4, VMFEQ_VV }, // 5568
|
|
{ PseudoVMFEQ_VV_M4_MASK, VMFEQ_VV }, // 5569
|
|
{ PseudoVMFEQ_VV_M8, VMFEQ_VV }, // 5570
|
|
{ PseudoVMFEQ_VV_M8_MASK, VMFEQ_VV }, // 5571
|
|
{ PseudoVMFEQ_VV_MF2, VMFEQ_VV }, // 5572
|
|
{ PseudoVMFEQ_VV_MF2_MASK, VMFEQ_VV }, // 5573
|
|
{ PseudoVMFEQ_VV_MF4, VMFEQ_VV }, // 5574
|
|
{ PseudoVMFEQ_VV_MF4_MASK, VMFEQ_VV }, // 5575
|
|
{ PseudoVMFGE_VFPR16_M1, VMFGE_VF }, // 5576
|
|
{ PseudoVMFGE_VFPR16_M1_MASK, VMFGE_VF }, // 5577
|
|
{ PseudoVMFGE_VFPR16_M2, VMFGE_VF }, // 5578
|
|
{ PseudoVMFGE_VFPR16_M2_MASK, VMFGE_VF }, // 5579
|
|
{ PseudoVMFGE_VFPR16_M4, VMFGE_VF }, // 5580
|
|
{ PseudoVMFGE_VFPR16_M4_MASK, VMFGE_VF }, // 5581
|
|
{ PseudoVMFGE_VFPR16_M8, VMFGE_VF }, // 5582
|
|
{ PseudoVMFGE_VFPR16_M8_MASK, VMFGE_VF }, // 5583
|
|
{ PseudoVMFGE_VFPR16_MF2, VMFGE_VF }, // 5584
|
|
{ PseudoVMFGE_VFPR16_MF2_MASK, VMFGE_VF }, // 5585
|
|
{ PseudoVMFGE_VFPR16_MF4, VMFGE_VF }, // 5586
|
|
{ PseudoVMFGE_VFPR16_MF4_MASK, VMFGE_VF }, // 5587
|
|
{ PseudoVMFGE_VFPR32_M1, VMFGE_VF }, // 5588
|
|
{ PseudoVMFGE_VFPR32_M1_MASK, VMFGE_VF }, // 5589
|
|
{ PseudoVMFGE_VFPR32_M2, VMFGE_VF }, // 5590
|
|
{ PseudoVMFGE_VFPR32_M2_MASK, VMFGE_VF }, // 5591
|
|
{ PseudoVMFGE_VFPR32_M4, VMFGE_VF }, // 5592
|
|
{ PseudoVMFGE_VFPR32_M4_MASK, VMFGE_VF }, // 5593
|
|
{ PseudoVMFGE_VFPR32_M8, VMFGE_VF }, // 5594
|
|
{ PseudoVMFGE_VFPR32_M8_MASK, VMFGE_VF }, // 5595
|
|
{ PseudoVMFGE_VFPR32_MF2, VMFGE_VF }, // 5596
|
|
{ PseudoVMFGE_VFPR32_MF2_MASK, VMFGE_VF }, // 5597
|
|
{ PseudoVMFGE_VFPR64_M1, VMFGE_VF }, // 5598
|
|
{ PseudoVMFGE_VFPR64_M1_MASK, VMFGE_VF }, // 5599
|
|
{ PseudoVMFGE_VFPR64_M2, VMFGE_VF }, // 5600
|
|
{ PseudoVMFGE_VFPR64_M2_MASK, VMFGE_VF }, // 5601
|
|
{ PseudoVMFGE_VFPR64_M4, VMFGE_VF }, // 5602
|
|
{ PseudoVMFGE_VFPR64_M4_MASK, VMFGE_VF }, // 5603
|
|
{ PseudoVMFGE_VFPR64_M8, VMFGE_VF }, // 5604
|
|
{ PseudoVMFGE_VFPR64_M8_MASK, VMFGE_VF }, // 5605
|
|
{ PseudoVMFGT_VFPR16_M1, VMFGT_VF }, // 5606
|
|
{ PseudoVMFGT_VFPR16_M1_MASK, VMFGT_VF }, // 5607
|
|
{ PseudoVMFGT_VFPR16_M2, VMFGT_VF }, // 5608
|
|
{ PseudoVMFGT_VFPR16_M2_MASK, VMFGT_VF }, // 5609
|
|
{ PseudoVMFGT_VFPR16_M4, VMFGT_VF }, // 5610
|
|
{ PseudoVMFGT_VFPR16_M4_MASK, VMFGT_VF }, // 5611
|
|
{ PseudoVMFGT_VFPR16_M8, VMFGT_VF }, // 5612
|
|
{ PseudoVMFGT_VFPR16_M8_MASK, VMFGT_VF }, // 5613
|
|
{ PseudoVMFGT_VFPR16_MF2, VMFGT_VF }, // 5614
|
|
{ PseudoVMFGT_VFPR16_MF2_MASK, VMFGT_VF }, // 5615
|
|
{ PseudoVMFGT_VFPR16_MF4, VMFGT_VF }, // 5616
|
|
{ PseudoVMFGT_VFPR16_MF4_MASK, VMFGT_VF }, // 5617
|
|
{ PseudoVMFGT_VFPR32_M1, VMFGT_VF }, // 5618
|
|
{ PseudoVMFGT_VFPR32_M1_MASK, VMFGT_VF }, // 5619
|
|
{ PseudoVMFGT_VFPR32_M2, VMFGT_VF }, // 5620
|
|
{ PseudoVMFGT_VFPR32_M2_MASK, VMFGT_VF }, // 5621
|
|
{ PseudoVMFGT_VFPR32_M4, VMFGT_VF }, // 5622
|
|
{ PseudoVMFGT_VFPR32_M4_MASK, VMFGT_VF }, // 5623
|
|
{ PseudoVMFGT_VFPR32_M8, VMFGT_VF }, // 5624
|
|
{ PseudoVMFGT_VFPR32_M8_MASK, VMFGT_VF }, // 5625
|
|
{ PseudoVMFGT_VFPR32_MF2, VMFGT_VF }, // 5626
|
|
{ PseudoVMFGT_VFPR32_MF2_MASK, VMFGT_VF }, // 5627
|
|
{ PseudoVMFGT_VFPR64_M1, VMFGT_VF }, // 5628
|
|
{ PseudoVMFGT_VFPR64_M1_MASK, VMFGT_VF }, // 5629
|
|
{ PseudoVMFGT_VFPR64_M2, VMFGT_VF }, // 5630
|
|
{ PseudoVMFGT_VFPR64_M2_MASK, VMFGT_VF }, // 5631
|
|
{ PseudoVMFGT_VFPR64_M4, VMFGT_VF }, // 5632
|
|
{ PseudoVMFGT_VFPR64_M4_MASK, VMFGT_VF }, // 5633
|
|
{ PseudoVMFGT_VFPR64_M8, VMFGT_VF }, // 5634
|
|
{ PseudoVMFGT_VFPR64_M8_MASK, VMFGT_VF }, // 5635
|
|
{ PseudoVMFLE_VFPR16_M1, VMFLE_VF }, // 5636
|
|
{ PseudoVMFLE_VFPR16_M1_MASK, VMFLE_VF }, // 5637
|
|
{ PseudoVMFLE_VFPR16_M2, VMFLE_VF }, // 5638
|
|
{ PseudoVMFLE_VFPR16_M2_MASK, VMFLE_VF }, // 5639
|
|
{ PseudoVMFLE_VFPR16_M4, VMFLE_VF }, // 5640
|
|
{ PseudoVMFLE_VFPR16_M4_MASK, VMFLE_VF }, // 5641
|
|
{ PseudoVMFLE_VFPR16_M8, VMFLE_VF }, // 5642
|
|
{ PseudoVMFLE_VFPR16_M8_MASK, VMFLE_VF }, // 5643
|
|
{ PseudoVMFLE_VFPR16_MF2, VMFLE_VF }, // 5644
|
|
{ PseudoVMFLE_VFPR16_MF2_MASK, VMFLE_VF }, // 5645
|
|
{ PseudoVMFLE_VFPR16_MF4, VMFLE_VF }, // 5646
|
|
{ PseudoVMFLE_VFPR16_MF4_MASK, VMFLE_VF }, // 5647
|
|
{ PseudoVMFLE_VFPR32_M1, VMFLE_VF }, // 5648
|
|
{ PseudoVMFLE_VFPR32_M1_MASK, VMFLE_VF }, // 5649
|
|
{ PseudoVMFLE_VFPR32_M2, VMFLE_VF }, // 5650
|
|
{ PseudoVMFLE_VFPR32_M2_MASK, VMFLE_VF }, // 5651
|
|
{ PseudoVMFLE_VFPR32_M4, VMFLE_VF }, // 5652
|
|
{ PseudoVMFLE_VFPR32_M4_MASK, VMFLE_VF }, // 5653
|
|
{ PseudoVMFLE_VFPR32_M8, VMFLE_VF }, // 5654
|
|
{ PseudoVMFLE_VFPR32_M8_MASK, VMFLE_VF }, // 5655
|
|
{ PseudoVMFLE_VFPR32_MF2, VMFLE_VF }, // 5656
|
|
{ PseudoVMFLE_VFPR32_MF2_MASK, VMFLE_VF }, // 5657
|
|
{ PseudoVMFLE_VFPR64_M1, VMFLE_VF }, // 5658
|
|
{ PseudoVMFLE_VFPR64_M1_MASK, VMFLE_VF }, // 5659
|
|
{ PseudoVMFLE_VFPR64_M2, VMFLE_VF }, // 5660
|
|
{ PseudoVMFLE_VFPR64_M2_MASK, VMFLE_VF }, // 5661
|
|
{ PseudoVMFLE_VFPR64_M4, VMFLE_VF }, // 5662
|
|
{ PseudoVMFLE_VFPR64_M4_MASK, VMFLE_VF }, // 5663
|
|
{ PseudoVMFLE_VFPR64_M8, VMFLE_VF }, // 5664
|
|
{ PseudoVMFLE_VFPR64_M8_MASK, VMFLE_VF }, // 5665
|
|
{ PseudoVMFLE_VV_M1, VMFLE_VV }, // 5666
|
|
{ PseudoVMFLE_VV_M1_MASK, VMFLE_VV }, // 5667
|
|
{ PseudoVMFLE_VV_M2, VMFLE_VV }, // 5668
|
|
{ PseudoVMFLE_VV_M2_MASK, VMFLE_VV }, // 5669
|
|
{ PseudoVMFLE_VV_M4, VMFLE_VV }, // 5670
|
|
{ PseudoVMFLE_VV_M4_MASK, VMFLE_VV }, // 5671
|
|
{ PseudoVMFLE_VV_M8, VMFLE_VV }, // 5672
|
|
{ PseudoVMFLE_VV_M8_MASK, VMFLE_VV }, // 5673
|
|
{ PseudoVMFLE_VV_MF2, VMFLE_VV }, // 5674
|
|
{ PseudoVMFLE_VV_MF2_MASK, VMFLE_VV }, // 5675
|
|
{ PseudoVMFLE_VV_MF4, VMFLE_VV }, // 5676
|
|
{ PseudoVMFLE_VV_MF4_MASK, VMFLE_VV }, // 5677
|
|
{ PseudoVMFLT_VFPR16_M1, VMFLT_VF }, // 5678
|
|
{ PseudoVMFLT_VFPR16_M1_MASK, VMFLT_VF }, // 5679
|
|
{ PseudoVMFLT_VFPR16_M2, VMFLT_VF }, // 5680
|
|
{ PseudoVMFLT_VFPR16_M2_MASK, VMFLT_VF }, // 5681
|
|
{ PseudoVMFLT_VFPR16_M4, VMFLT_VF }, // 5682
|
|
{ PseudoVMFLT_VFPR16_M4_MASK, VMFLT_VF }, // 5683
|
|
{ PseudoVMFLT_VFPR16_M8, VMFLT_VF }, // 5684
|
|
{ PseudoVMFLT_VFPR16_M8_MASK, VMFLT_VF }, // 5685
|
|
{ PseudoVMFLT_VFPR16_MF2, VMFLT_VF }, // 5686
|
|
{ PseudoVMFLT_VFPR16_MF2_MASK, VMFLT_VF }, // 5687
|
|
{ PseudoVMFLT_VFPR16_MF4, VMFLT_VF }, // 5688
|
|
{ PseudoVMFLT_VFPR16_MF4_MASK, VMFLT_VF }, // 5689
|
|
{ PseudoVMFLT_VFPR32_M1, VMFLT_VF }, // 5690
|
|
{ PseudoVMFLT_VFPR32_M1_MASK, VMFLT_VF }, // 5691
|
|
{ PseudoVMFLT_VFPR32_M2, VMFLT_VF }, // 5692
|
|
{ PseudoVMFLT_VFPR32_M2_MASK, VMFLT_VF }, // 5693
|
|
{ PseudoVMFLT_VFPR32_M4, VMFLT_VF }, // 5694
|
|
{ PseudoVMFLT_VFPR32_M4_MASK, VMFLT_VF }, // 5695
|
|
{ PseudoVMFLT_VFPR32_M8, VMFLT_VF }, // 5696
|
|
{ PseudoVMFLT_VFPR32_M8_MASK, VMFLT_VF }, // 5697
|
|
{ PseudoVMFLT_VFPR32_MF2, VMFLT_VF }, // 5698
|
|
{ PseudoVMFLT_VFPR32_MF2_MASK, VMFLT_VF }, // 5699
|
|
{ PseudoVMFLT_VFPR64_M1, VMFLT_VF }, // 5700
|
|
{ PseudoVMFLT_VFPR64_M1_MASK, VMFLT_VF }, // 5701
|
|
{ PseudoVMFLT_VFPR64_M2, VMFLT_VF }, // 5702
|
|
{ PseudoVMFLT_VFPR64_M2_MASK, VMFLT_VF }, // 5703
|
|
{ PseudoVMFLT_VFPR64_M4, VMFLT_VF }, // 5704
|
|
{ PseudoVMFLT_VFPR64_M4_MASK, VMFLT_VF }, // 5705
|
|
{ PseudoVMFLT_VFPR64_M8, VMFLT_VF }, // 5706
|
|
{ PseudoVMFLT_VFPR64_M8_MASK, VMFLT_VF }, // 5707
|
|
{ PseudoVMFLT_VV_M1, VMFLT_VV }, // 5708
|
|
{ PseudoVMFLT_VV_M1_MASK, VMFLT_VV }, // 5709
|
|
{ PseudoVMFLT_VV_M2, VMFLT_VV }, // 5710
|
|
{ PseudoVMFLT_VV_M2_MASK, VMFLT_VV }, // 5711
|
|
{ PseudoVMFLT_VV_M4, VMFLT_VV }, // 5712
|
|
{ PseudoVMFLT_VV_M4_MASK, VMFLT_VV }, // 5713
|
|
{ PseudoVMFLT_VV_M8, VMFLT_VV }, // 5714
|
|
{ PseudoVMFLT_VV_M8_MASK, VMFLT_VV }, // 5715
|
|
{ PseudoVMFLT_VV_MF2, VMFLT_VV }, // 5716
|
|
{ PseudoVMFLT_VV_MF2_MASK, VMFLT_VV }, // 5717
|
|
{ PseudoVMFLT_VV_MF4, VMFLT_VV }, // 5718
|
|
{ PseudoVMFLT_VV_MF4_MASK, VMFLT_VV }, // 5719
|
|
{ PseudoVMFNE_VFPR16_M1, VMFNE_VF }, // 5720
|
|
{ PseudoVMFNE_VFPR16_M1_MASK, VMFNE_VF }, // 5721
|
|
{ PseudoVMFNE_VFPR16_M2, VMFNE_VF }, // 5722
|
|
{ PseudoVMFNE_VFPR16_M2_MASK, VMFNE_VF }, // 5723
|
|
{ PseudoVMFNE_VFPR16_M4, VMFNE_VF }, // 5724
|
|
{ PseudoVMFNE_VFPR16_M4_MASK, VMFNE_VF }, // 5725
|
|
{ PseudoVMFNE_VFPR16_M8, VMFNE_VF }, // 5726
|
|
{ PseudoVMFNE_VFPR16_M8_MASK, VMFNE_VF }, // 5727
|
|
{ PseudoVMFNE_VFPR16_MF2, VMFNE_VF }, // 5728
|
|
{ PseudoVMFNE_VFPR16_MF2_MASK, VMFNE_VF }, // 5729
|
|
{ PseudoVMFNE_VFPR16_MF4, VMFNE_VF }, // 5730
|
|
{ PseudoVMFNE_VFPR16_MF4_MASK, VMFNE_VF }, // 5731
|
|
{ PseudoVMFNE_VFPR32_M1, VMFNE_VF }, // 5732
|
|
{ PseudoVMFNE_VFPR32_M1_MASK, VMFNE_VF }, // 5733
|
|
{ PseudoVMFNE_VFPR32_M2, VMFNE_VF }, // 5734
|
|
{ PseudoVMFNE_VFPR32_M2_MASK, VMFNE_VF }, // 5735
|
|
{ PseudoVMFNE_VFPR32_M4, VMFNE_VF }, // 5736
|
|
{ PseudoVMFNE_VFPR32_M4_MASK, VMFNE_VF }, // 5737
|
|
{ PseudoVMFNE_VFPR32_M8, VMFNE_VF }, // 5738
|
|
{ PseudoVMFNE_VFPR32_M8_MASK, VMFNE_VF }, // 5739
|
|
{ PseudoVMFNE_VFPR32_MF2, VMFNE_VF }, // 5740
|
|
{ PseudoVMFNE_VFPR32_MF2_MASK, VMFNE_VF }, // 5741
|
|
{ PseudoVMFNE_VFPR64_M1, VMFNE_VF }, // 5742
|
|
{ PseudoVMFNE_VFPR64_M1_MASK, VMFNE_VF }, // 5743
|
|
{ PseudoVMFNE_VFPR64_M2, VMFNE_VF }, // 5744
|
|
{ PseudoVMFNE_VFPR64_M2_MASK, VMFNE_VF }, // 5745
|
|
{ PseudoVMFNE_VFPR64_M4, VMFNE_VF }, // 5746
|
|
{ PseudoVMFNE_VFPR64_M4_MASK, VMFNE_VF }, // 5747
|
|
{ PseudoVMFNE_VFPR64_M8, VMFNE_VF }, // 5748
|
|
{ PseudoVMFNE_VFPR64_M8_MASK, VMFNE_VF }, // 5749
|
|
{ PseudoVMFNE_VV_M1, VMFNE_VV }, // 5750
|
|
{ PseudoVMFNE_VV_M1_MASK, VMFNE_VV }, // 5751
|
|
{ PseudoVMFNE_VV_M2, VMFNE_VV }, // 5752
|
|
{ PseudoVMFNE_VV_M2_MASK, VMFNE_VV }, // 5753
|
|
{ PseudoVMFNE_VV_M4, VMFNE_VV }, // 5754
|
|
{ PseudoVMFNE_VV_M4_MASK, VMFNE_VV }, // 5755
|
|
{ PseudoVMFNE_VV_M8, VMFNE_VV }, // 5756
|
|
{ PseudoVMFNE_VV_M8_MASK, VMFNE_VV }, // 5757
|
|
{ PseudoVMFNE_VV_MF2, VMFNE_VV }, // 5758
|
|
{ PseudoVMFNE_VV_MF2_MASK, VMFNE_VV }, // 5759
|
|
{ PseudoVMFNE_VV_MF4, VMFNE_VV }, // 5760
|
|
{ PseudoVMFNE_VV_MF4_MASK, VMFNE_VV }, // 5761
|
|
{ PseudoVMINU_VV_M1, VMINU_VV }, // 5762
|
|
{ PseudoVMINU_VV_M1_MASK, VMINU_VV }, // 5763
|
|
{ PseudoVMINU_VV_M2, VMINU_VV }, // 5764
|
|
{ PseudoVMINU_VV_M2_MASK, VMINU_VV }, // 5765
|
|
{ PseudoVMINU_VV_M4, VMINU_VV }, // 5766
|
|
{ PseudoVMINU_VV_M4_MASK, VMINU_VV }, // 5767
|
|
{ PseudoVMINU_VV_M8, VMINU_VV }, // 5768
|
|
{ PseudoVMINU_VV_M8_MASK, VMINU_VV }, // 5769
|
|
{ PseudoVMINU_VV_MF2, VMINU_VV }, // 5770
|
|
{ PseudoVMINU_VV_MF2_MASK, VMINU_VV }, // 5771
|
|
{ PseudoVMINU_VV_MF4, VMINU_VV }, // 5772
|
|
{ PseudoVMINU_VV_MF4_MASK, VMINU_VV }, // 5773
|
|
{ PseudoVMINU_VV_MF8, VMINU_VV }, // 5774
|
|
{ PseudoVMINU_VV_MF8_MASK, VMINU_VV }, // 5775
|
|
{ PseudoVMINU_VX_M1, VMINU_VX }, // 5776
|
|
{ PseudoVMINU_VX_M1_MASK, VMINU_VX }, // 5777
|
|
{ PseudoVMINU_VX_M2, VMINU_VX }, // 5778
|
|
{ PseudoVMINU_VX_M2_MASK, VMINU_VX }, // 5779
|
|
{ PseudoVMINU_VX_M4, VMINU_VX }, // 5780
|
|
{ PseudoVMINU_VX_M4_MASK, VMINU_VX }, // 5781
|
|
{ PseudoVMINU_VX_M8, VMINU_VX }, // 5782
|
|
{ PseudoVMINU_VX_M8_MASK, VMINU_VX }, // 5783
|
|
{ PseudoVMINU_VX_MF2, VMINU_VX }, // 5784
|
|
{ PseudoVMINU_VX_MF2_MASK, VMINU_VX }, // 5785
|
|
{ PseudoVMINU_VX_MF4, VMINU_VX }, // 5786
|
|
{ PseudoVMINU_VX_MF4_MASK, VMINU_VX }, // 5787
|
|
{ PseudoVMINU_VX_MF8, VMINU_VX }, // 5788
|
|
{ PseudoVMINU_VX_MF8_MASK, VMINU_VX }, // 5789
|
|
{ PseudoVMIN_VV_M1, VMIN_VV }, // 5790
|
|
{ PseudoVMIN_VV_M1_MASK, VMIN_VV }, // 5791
|
|
{ PseudoVMIN_VV_M2, VMIN_VV }, // 5792
|
|
{ PseudoVMIN_VV_M2_MASK, VMIN_VV }, // 5793
|
|
{ PseudoVMIN_VV_M4, VMIN_VV }, // 5794
|
|
{ PseudoVMIN_VV_M4_MASK, VMIN_VV }, // 5795
|
|
{ PseudoVMIN_VV_M8, VMIN_VV }, // 5796
|
|
{ PseudoVMIN_VV_M8_MASK, VMIN_VV }, // 5797
|
|
{ PseudoVMIN_VV_MF2, VMIN_VV }, // 5798
|
|
{ PseudoVMIN_VV_MF2_MASK, VMIN_VV }, // 5799
|
|
{ PseudoVMIN_VV_MF4, VMIN_VV }, // 5800
|
|
{ PseudoVMIN_VV_MF4_MASK, VMIN_VV }, // 5801
|
|
{ PseudoVMIN_VV_MF8, VMIN_VV }, // 5802
|
|
{ PseudoVMIN_VV_MF8_MASK, VMIN_VV }, // 5803
|
|
{ PseudoVMIN_VX_M1, VMIN_VX }, // 5804
|
|
{ PseudoVMIN_VX_M1_MASK, VMIN_VX }, // 5805
|
|
{ PseudoVMIN_VX_M2, VMIN_VX }, // 5806
|
|
{ PseudoVMIN_VX_M2_MASK, VMIN_VX }, // 5807
|
|
{ PseudoVMIN_VX_M4, VMIN_VX }, // 5808
|
|
{ PseudoVMIN_VX_M4_MASK, VMIN_VX }, // 5809
|
|
{ PseudoVMIN_VX_M8, VMIN_VX }, // 5810
|
|
{ PseudoVMIN_VX_M8_MASK, VMIN_VX }, // 5811
|
|
{ PseudoVMIN_VX_MF2, VMIN_VX }, // 5812
|
|
{ PseudoVMIN_VX_MF2_MASK, VMIN_VX }, // 5813
|
|
{ PseudoVMIN_VX_MF4, VMIN_VX }, // 5814
|
|
{ PseudoVMIN_VX_MF4_MASK, VMIN_VX }, // 5815
|
|
{ PseudoVMIN_VX_MF8, VMIN_VX }, // 5816
|
|
{ PseudoVMIN_VX_MF8_MASK, VMIN_VX }, // 5817
|
|
{ PseudoVMNAND_MM_M1, VMNAND_MM }, // 5818
|
|
{ PseudoVMNAND_MM_M2, VMNAND_MM }, // 5819
|
|
{ PseudoVMNAND_MM_M4, VMNAND_MM }, // 5820
|
|
{ PseudoVMNAND_MM_M8, VMNAND_MM }, // 5821
|
|
{ PseudoVMNAND_MM_MF2, VMNAND_MM }, // 5822
|
|
{ PseudoVMNAND_MM_MF4, VMNAND_MM }, // 5823
|
|
{ PseudoVMNAND_MM_MF8, VMNAND_MM }, // 5824
|
|
{ PseudoVMNOR_MM_M1, VMNOR_MM }, // 5825
|
|
{ PseudoVMNOR_MM_M2, VMNOR_MM }, // 5826
|
|
{ PseudoVMNOR_MM_M4, VMNOR_MM }, // 5827
|
|
{ PseudoVMNOR_MM_M8, VMNOR_MM }, // 5828
|
|
{ PseudoVMNOR_MM_MF2, VMNOR_MM }, // 5829
|
|
{ PseudoVMNOR_MM_MF4, VMNOR_MM }, // 5830
|
|
{ PseudoVMNOR_MM_MF8, VMNOR_MM }, // 5831
|
|
{ PseudoVMORN_MM_M1, VMORN_MM }, // 5832
|
|
{ PseudoVMORN_MM_M2, VMORN_MM }, // 5833
|
|
{ PseudoVMORN_MM_M4, VMORN_MM }, // 5834
|
|
{ PseudoVMORN_MM_M8, VMORN_MM }, // 5835
|
|
{ PseudoVMORN_MM_MF2, VMORN_MM }, // 5836
|
|
{ PseudoVMORN_MM_MF4, VMORN_MM }, // 5837
|
|
{ PseudoVMORN_MM_MF8, VMORN_MM }, // 5838
|
|
{ PseudoVMOR_MM_M1, VMOR_MM }, // 5839
|
|
{ PseudoVMOR_MM_M2, VMOR_MM }, // 5840
|
|
{ PseudoVMOR_MM_M4, VMOR_MM }, // 5841
|
|
{ PseudoVMOR_MM_M8, VMOR_MM }, // 5842
|
|
{ PseudoVMOR_MM_MF2, VMOR_MM }, // 5843
|
|
{ PseudoVMOR_MM_MF4, VMOR_MM }, // 5844
|
|
{ PseudoVMOR_MM_MF8, VMOR_MM }, // 5845
|
|
{ PseudoVMSBC_VVM_M1, VMSBC_VVM }, // 5846
|
|
{ PseudoVMSBC_VVM_M2, VMSBC_VVM }, // 5847
|
|
{ PseudoVMSBC_VVM_M4, VMSBC_VVM }, // 5848
|
|
{ PseudoVMSBC_VVM_M8, VMSBC_VVM }, // 5849
|
|
{ PseudoVMSBC_VVM_MF2, VMSBC_VVM }, // 5850
|
|
{ PseudoVMSBC_VVM_MF4, VMSBC_VVM }, // 5851
|
|
{ PseudoVMSBC_VVM_MF8, VMSBC_VVM }, // 5852
|
|
{ PseudoVMSBC_VV_M1, VMSBC_VV }, // 5853
|
|
{ PseudoVMSBC_VV_M2, VMSBC_VV }, // 5854
|
|
{ PseudoVMSBC_VV_M4, VMSBC_VV }, // 5855
|
|
{ PseudoVMSBC_VV_M8, VMSBC_VV }, // 5856
|
|
{ PseudoVMSBC_VV_MF2, VMSBC_VV }, // 5857
|
|
{ PseudoVMSBC_VV_MF4, VMSBC_VV }, // 5858
|
|
{ PseudoVMSBC_VV_MF8, VMSBC_VV }, // 5859
|
|
{ PseudoVMSBC_VXM_M1, VMSBC_VXM }, // 5860
|
|
{ PseudoVMSBC_VXM_M2, VMSBC_VXM }, // 5861
|
|
{ PseudoVMSBC_VXM_M4, VMSBC_VXM }, // 5862
|
|
{ PseudoVMSBC_VXM_M8, VMSBC_VXM }, // 5863
|
|
{ PseudoVMSBC_VXM_MF2, VMSBC_VXM }, // 5864
|
|
{ PseudoVMSBC_VXM_MF4, VMSBC_VXM }, // 5865
|
|
{ PseudoVMSBC_VXM_MF8, VMSBC_VXM }, // 5866
|
|
{ PseudoVMSBC_VX_M1, VMSBC_VX }, // 5867
|
|
{ PseudoVMSBC_VX_M2, VMSBC_VX }, // 5868
|
|
{ PseudoVMSBC_VX_M4, VMSBC_VX }, // 5869
|
|
{ PseudoVMSBC_VX_M8, VMSBC_VX }, // 5870
|
|
{ PseudoVMSBC_VX_MF2, VMSBC_VX }, // 5871
|
|
{ PseudoVMSBC_VX_MF4, VMSBC_VX }, // 5872
|
|
{ PseudoVMSBC_VX_MF8, VMSBC_VX }, // 5873
|
|
{ PseudoVMSBF_M_B1, VMSBF_M }, // 5874
|
|
{ PseudoVMSBF_M_B16, VMSBF_M }, // 5875
|
|
{ PseudoVMSBF_M_B16_MASK, VMSBF_M }, // 5876
|
|
{ PseudoVMSBF_M_B1_MASK, VMSBF_M }, // 5877
|
|
{ PseudoVMSBF_M_B2, VMSBF_M }, // 5878
|
|
{ PseudoVMSBF_M_B2_MASK, VMSBF_M }, // 5879
|
|
{ PseudoVMSBF_M_B32, VMSBF_M }, // 5880
|
|
{ PseudoVMSBF_M_B32_MASK, VMSBF_M }, // 5881
|
|
{ PseudoVMSBF_M_B4, VMSBF_M }, // 5882
|
|
{ PseudoVMSBF_M_B4_MASK, VMSBF_M }, // 5883
|
|
{ PseudoVMSBF_M_B64, VMSBF_M }, // 5884
|
|
{ PseudoVMSBF_M_B64_MASK, VMSBF_M }, // 5885
|
|
{ PseudoVMSBF_M_B8, VMSBF_M }, // 5886
|
|
{ PseudoVMSBF_M_B8_MASK, VMSBF_M }, // 5887
|
|
{ PseudoVMSEQ_VI_M1, VMSEQ_VI }, // 5888
|
|
{ PseudoVMSEQ_VI_M1_MASK, VMSEQ_VI }, // 5889
|
|
{ PseudoVMSEQ_VI_M2, VMSEQ_VI }, // 5890
|
|
{ PseudoVMSEQ_VI_M2_MASK, VMSEQ_VI }, // 5891
|
|
{ PseudoVMSEQ_VI_M4, VMSEQ_VI }, // 5892
|
|
{ PseudoVMSEQ_VI_M4_MASK, VMSEQ_VI }, // 5893
|
|
{ PseudoVMSEQ_VI_M8, VMSEQ_VI }, // 5894
|
|
{ PseudoVMSEQ_VI_M8_MASK, VMSEQ_VI }, // 5895
|
|
{ PseudoVMSEQ_VI_MF2, VMSEQ_VI }, // 5896
|
|
{ PseudoVMSEQ_VI_MF2_MASK, VMSEQ_VI }, // 5897
|
|
{ PseudoVMSEQ_VI_MF4, VMSEQ_VI }, // 5898
|
|
{ PseudoVMSEQ_VI_MF4_MASK, VMSEQ_VI }, // 5899
|
|
{ PseudoVMSEQ_VI_MF8, VMSEQ_VI }, // 5900
|
|
{ PseudoVMSEQ_VI_MF8_MASK, VMSEQ_VI }, // 5901
|
|
{ PseudoVMSEQ_VV_M1, VMSEQ_VV }, // 5902
|
|
{ PseudoVMSEQ_VV_M1_MASK, VMSEQ_VV }, // 5903
|
|
{ PseudoVMSEQ_VV_M2, VMSEQ_VV }, // 5904
|
|
{ PseudoVMSEQ_VV_M2_MASK, VMSEQ_VV }, // 5905
|
|
{ PseudoVMSEQ_VV_M4, VMSEQ_VV }, // 5906
|
|
{ PseudoVMSEQ_VV_M4_MASK, VMSEQ_VV }, // 5907
|
|
{ PseudoVMSEQ_VV_M8, VMSEQ_VV }, // 5908
|
|
{ PseudoVMSEQ_VV_M8_MASK, VMSEQ_VV }, // 5909
|
|
{ PseudoVMSEQ_VV_MF2, VMSEQ_VV }, // 5910
|
|
{ PseudoVMSEQ_VV_MF2_MASK, VMSEQ_VV }, // 5911
|
|
{ PseudoVMSEQ_VV_MF4, VMSEQ_VV }, // 5912
|
|
{ PseudoVMSEQ_VV_MF4_MASK, VMSEQ_VV }, // 5913
|
|
{ PseudoVMSEQ_VV_MF8, VMSEQ_VV }, // 5914
|
|
{ PseudoVMSEQ_VV_MF8_MASK, VMSEQ_VV }, // 5915
|
|
{ PseudoVMSEQ_VX_M1, VMSEQ_VX }, // 5916
|
|
{ PseudoVMSEQ_VX_M1_MASK, VMSEQ_VX }, // 5917
|
|
{ PseudoVMSEQ_VX_M2, VMSEQ_VX }, // 5918
|
|
{ PseudoVMSEQ_VX_M2_MASK, VMSEQ_VX }, // 5919
|
|
{ PseudoVMSEQ_VX_M4, VMSEQ_VX }, // 5920
|
|
{ PseudoVMSEQ_VX_M4_MASK, VMSEQ_VX }, // 5921
|
|
{ PseudoVMSEQ_VX_M8, VMSEQ_VX }, // 5922
|
|
{ PseudoVMSEQ_VX_M8_MASK, VMSEQ_VX }, // 5923
|
|
{ PseudoVMSEQ_VX_MF2, VMSEQ_VX }, // 5924
|
|
{ PseudoVMSEQ_VX_MF2_MASK, VMSEQ_VX }, // 5925
|
|
{ PseudoVMSEQ_VX_MF4, VMSEQ_VX }, // 5926
|
|
{ PseudoVMSEQ_VX_MF4_MASK, VMSEQ_VX }, // 5927
|
|
{ PseudoVMSEQ_VX_MF8, VMSEQ_VX }, // 5928
|
|
{ PseudoVMSEQ_VX_MF8_MASK, VMSEQ_VX }, // 5929
|
|
{ PseudoVMSGTU_VI_M1, VMSGTU_VI }, // 5930
|
|
{ PseudoVMSGTU_VI_M1_MASK, VMSGTU_VI }, // 5931
|
|
{ PseudoVMSGTU_VI_M2, VMSGTU_VI }, // 5932
|
|
{ PseudoVMSGTU_VI_M2_MASK, VMSGTU_VI }, // 5933
|
|
{ PseudoVMSGTU_VI_M4, VMSGTU_VI }, // 5934
|
|
{ PseudoVMSGTU_VI_M4_MASK, VMSGTU_VI }, // 5935
|
|
{ PseudoVMSGTU_VI_M8, VMSGTU_VI }, // 5936
|
|
{ PseudoVMSGTU_VI_M8_MASK, VMSGTU_VI }, // 5937
|
|
{ PseudoVMSGTU_VI_MF2, VMSGTU_VI }, // 5938
|
|
{ PseudoVMSGTU_VI_MF2_MASK, VMSGTU_VI }, // 5939
|
|
{ PseudoVMSGTU_VI_MF4, VMSGTU_VI }, // 5940
|
|
{ PseudoVMSGTU_VI_MF4_MASK, VMSGTU_VI }, // 5941
|
|
{ PseudoVMSGTU_VI_MF8, VMSGTU_VI }, // 5942
|
|
{ PseudoVMSGTU_VI_MF8_MASK, VMSGTU_VI }, // 5943
|
|
{ PseudoVMSGTU_VX_M1, VMSGTU_VX }, // 5944
|
|
{ PseudoVMSGTU_VX_M1_MASK, VMSGTU_VX }, // 5945
|
|
{ PseudoVMSGTU_VX_M2, VMSGTU_VX }, // 5946
|
|
{ PseudoVMSGTU_VX_M2_MASK, VMSGTU_VX }, // 5947
|
|
{ PseudoVMSGTU_VX_M4, VMSGTU_VX }, // 5948
|
|
{ PseudoVMSGTU_VX_M4_MASK, VMSGTU_VX }, // 5949
|
|
{ PseudoVMSGTU_VX_M8, VMSGTU_VX }, // 5950
|
|
{ PseudoVMSGTU_VX_M8_MASK, VMSGTU_VX }, // 5951
|
|
{ PseudoVMSGTU_VX_MF2, VMSGTU_VX }, // 5952
|
|
{ PseudoVMSGTU_VX_MF2_MASK, VMSGTU_VX }, // 5953
|
|
{ PseudoVMSGTU_VX_MF4, VMSGTU_VX }, // 5954
|
|
{ PseudoVMSGTU_VX_MF4_MASK, VMSGTU_VX }, // 5955
|
|
{ PseudoVMSGTU_VX_MF8, VMSGTU_VX }, // 5956
|
|
{ PseudoVMSGTU_VX_MF8_MASK, VMSGTU_VX }, // 5957
|
|
{ PseudoVMSGT_VI_M1, VMSGT_VI }, // 5958
|
|
{ PseudoVMSGT_VI_M1_MASK, VMSGT_VI }, // 5959
|
|
{ PseudoVMSGT_VI_M2, VMSGT_VI }, // 5960
|
|
{ PseudoVMSGT_VI_M2_MASK, VMSGT_VI }, // 5961
|
|
{ PseudoVMSGT_VI_M4, VMSGT_VI }, // 5962
|
|
{ PseudoVMSGT_VI_M4_MASK, VMSGT_VI }, // 5963
|
|
{ PseudoVMSGT_VI_M8, VMSGT_VI }, // 5964
|
|
{ PseudoVMSGT_VI_M8_MASK, VMSGT_VI }, // 5965
|
|
{ PseudoVMSGT_VI_MF2, VMSGT_VI }, // 5966
|
|
{ PseudoVMSGT_VI_MF2_MASK, VMSGT_VI }, // 5967
|
|
{ PseudoVMSGT_VI_MF4, VMSGT_VI }, // 5968
|
|
{ PseudoVMSGT_VI_MF4_MASK, VMSGT_VI }, // 5969
|
|
{ PseudoVMSGT_VI_MF8, VMSGT_VI }, // 5970
|
|
{ PseudoVMSGT_VI_MF8_MASK, VMSGT_VI }, // 5971
|
|
{ PseudoVMSGT_VX_M1, VMSGT_VX }, // 5972
|
|
{ PseudoVMSGT_VX_M1_MASK, VMSGT_VX }, // 5973
|
|
{ PseudoVMSGT_VX_M2, VMSGT_VX }, // 5974
|
|
{ PseudoVMSGT_VX_M2_MASK, VMSGT_VX }, // 5975
|
|
{ PseudoVMSGT_VX_M4, VMSGT_VX }, // 5976
|
|
{ PseudoVMSGT_VX_M4_MASK, VMSGT_VX }, // 5977
|
|
{ PseudoVMSGT_VX_M8, VMSGT_VX }, // 5978
|
|
{ PseudoVMSGT_VX_M8_MASK, VMSGT_VX }, // 5979
|
|
{ PseudoVMSGT_VX_MF2, VMSGT_VX }, // 5980
|
|
{ PseudoVMSGT_VX_MF2_MASK, VMSGT_VX }, // 5981
|
|
{ PseudoVMSGT_VX_MF4, VMSGT_VX }, // 5982
|
|
{ PseudoVMSGT_VX_MF4_MASK, VMSGT_VX }, // 5983
|
|
{ PseudoVMSGT_VX_MF8, VMSGT_VX }, // 5984
|
|
{ PseudoVMSGT_VX_MF8_MASK, VMSGT_VX }, // 5985
|
|
{ PseudoVMSIF_M_B1, VMSIF_M }, // 5986
|
|
{ PseudoVMSIF_M_B16, VMSIF_M }, // 5987
|
|
{ PseudoVMSIF_M_B16_MASK, VMSIF_M }, // 5988
|
|
{ PseudoVMSIF_M_B1_MASK, VMSIF_M }, // 5989
|
|
{ PseudoVMSIF_M_B2, VMSIF_M }, // 5990
|
|
{ PseudoVMSIF_M_B2_MASK, VMSIF_M }, // 5991
|
|
{ PseudoVMSIF_M_B32, VMSIF_M }, // 5992
|
|
{ PseudoVMSIF_M_B32_MASK, VMSIF_M }, // 5993
|
|
{ PseudoVMSIF_M_B4, VMSIF_M }, // 5994
|
|
{ PseudoVMSIF_M_B4_MASK, VMSIF_M }, // 5995
|
|
{ PseudoVMSIF_M_B64, VMSIF_M }, // 5996
|
|
{ PseudoVMSIF_M_B64_MASK, VMSIF_M }, // 5997
|
|
{ PseudoVMSIF_M_B8, VMSIF_M }, // 5998
|
|
{ PseudoVMSIF_M_B8_MASK, VMSIF_M }, // 5999
|
|
{ PseudoVMSLEU_VI_M1, VMSLEU_VI }, // 6000
|
|
{ PseudoVMSLEU_VI_M1_MASK, VMSLEU_VI }, // 6001
|
|
{ PseudoVMSLEU_VI_M2, VMSLEU_VI }, // 6002
|
|
{ PseudoVMSLEU_VI_M2_MASK, VMSLEU_VI }, // 6003
|
|
{ PseudoVMSLEU_VI_M4, VMSLEU_VI }, // 6004
|
|
{ PseudoVMSLEU_VI_M4_MASK, VMSLEU_VI }, // 6005
|
|
{ PseudoVMSLEU_VI_M8, VMSLEU_VI }, // 6006
|
|
{ PseudoVMSLEU_VI_M8_MASK, VMSLEU_VI }, // 6007
|
|
{ PseudoVMSLEU_VI_MF2, VMSLEU_VI }, // 6008
|
|
{ PseudoVMSLEU_VI_MF2_MASK, VMSLEU_VI }, // 6009
|
|
{ PseudoVMSLEU_VI_MF4, VMSLEU_VI }, // 6010
|
|
{ PseudoVMSLEU_VI_MF4_MASK, VMSLEU_VI }, // 6011
|
|
{ PseudoVMSLEU_VI_MF8, VMSLEU_VI }, // 6012
|
|
{ PseudoVMSLEU_VI_MF8_MASK, VMSLEU_VI }, // 6013
|
|
{ PseudoVMSLEU_VV_M1, VMSLEU_VV }, // 6014
|
|
{ PseudoVMSLEU_VV_M1_MASK, VMSLEU_VV }, // 6015
|
|
{ PseudoVMSLEU_VV_M2, VMSLEU_VV }, // 6016
|
|
{ PseudoVMSLEU_VV_M2_MASK, VMSLEU_VV }, // 6017
|
|
{ PseudoVMSLEU_VV_M4, VMSLEU_VV }, // 6018
|
|
{ PseudoVMSLEU_VV_M4_MASK, VMSLEU_VV }, // 6019
|
|
{ PseudoVMSLEU_VV_M8, VMSLEU_VV }, // 6020
|
|
{ PseudoVMSLEU_VV_M8_MASK, VMSLEU_VV }, // 6021
|
|
{ PseudoVMSLEU_VV_MF2, VMSLEU_VV }, // 6022
|
|
{ PseudoVMSLEU_VV_MF2_MASK, VMSLEU_VV }, // 6023
|
|
{ PseudoVMSLEU_VV_MF4, VMSLEU_VV }, // 6024
|
|
{ PseudoVMSLEU_VV_MF4_MASK, VMSLEU_VV }, // 6025
|
|
{ PseudoVMSLEU_VV_MF8, VMSLEU_VV }, // 6026
|
|
{ PseudoVMSLEU_VV_MF8_MASK, VMSLEU_VV }, // 6027
|
|
{ PseudoVMSLEU_VX_M1, VMSLEU_VX }, // 6028
|
|
{ PseudoVMSLEU_VX_M1_MASK, VMSLEU_VX }, // 6029
|
|
{ PseudoVMSLEU_VX_M2, VMSLEU_VX }, // 6030
|
|
{ PseudoVMSLEU_VX_M2_MASK, VMSLEU_VX }, // 6031
|
|
{ PseudoVMSLEU_VX_M4, VMSLEU_VX }, // 6032
|
|
{ PseudoVMSLEU_VX_M4_MASK, VMSLEU_VX }, // 6033
|
|
{ PseudoVMSLEU_VX_M8, VMSLEU_VX }, // 6034
|
|
{ PseudoVMSLEU_VX_M8_MASK, VMSLEU_VX }, // 6035
|
|
{ PseudoVMSLEU_VX_MF2, VMSLEU_VX }, // 6036
|
|
{ PseudoVMSLEU_VX_MF2_MASK, VMSLEU_VX }, // 6037
|
|
{ PseudoVMSLEU_VX_MF4, VMSLEU_VX }, // 6038
|
|
{ PseudoVMSLEU_VX_MF4_MASK, VMSLEU_VX }, // 6039
|
|
{ PseudoVMSLEU_VX_MF8, VMSLEU_VX }, // 6040
|
|
{ PseudoVMSLEU_VX_MF8_MASK, VMSLEU_VX }, // 6041
|
|
{ PseudoVMSLE_VI_M1, VMSLE_VI }, // 6042
|
|
{ PseudoVMSLE_VI_M1_MASK, VMSLE_VI }, // 6043
|
|
{ PseudoVMSLE_VI_M2, VMSLE_VI }, // 6044
|
|
{ PseudoVMSLE_VI_M2_MASK, VMSLE_VI }, // 6045
|
|
{ PseudoVMSLE_VI_M4, VMSLE_VI }, // 6046
|
|
{ PseudoVMSLE_VI_M4_MASK, VMSLE_VI }, // 6047
|
|
{ PseudoVMSLE_VI_M8, VMSLE_VI }, // 6048
|
|
{ PseudoVMSLE_VI_M8_MASK, VMSLE_VI }, // 6049
|
|
{ PseudoVMSLE_VI_MF2, VMSLE_VI }, // 6050
|
|
{ PseudoVMSLE_VI_MF2_MASK, VMSLE_VI }, // 6051
|
|
{ PseudoVMSLE_VI_MF4, VMSLE_VI }, // 6052
|
|
{ PseudoVMSLE_VI_MF4_MASK, VMSLE_VI }, // 6053
|
|
{ PseudoVMSLE_VI_MF8, VMSLE_VI }, // 6054
|
|
{ PseudoVMSLE_VI_MF8_MASK, VMSLE_VI }, // 6055
|
|
{ PseudoVMSLE_VV_M1, VMSLE_VV }, // 6056
|
|
{ PseudoVMSLE_VV_M1_MASK, VMSLE_VV }, // 6057
|
|
{ PseudoVMSLE_VV_M2, VMSLE_VV }, // 6058
|
|
{ PseudoVMSLE_VV_M2_MASK, VMSLE_VV }, // 6059
|
|
{ PseudoVMSLE_VV_M4, VMSLE_VV }, // 6060
|
|
{ PseudoVMSLE_VV_M4_MASK, VMSLE_VV }, // 6061
|
|
{ PseudoVMSLE_VV_M8, VMSLE_VV }, // 6062
|
|
{ PseudoVMSLE_VV_M8_MASK, VMSLE_VV }, // 6063
|
|
{ PseudoVMSLE_VV_MF2, VMSLE_VV }, // 6064
|
|
{ PseudoVMSLE_VV_MF2_MASK, VMSLE_VV }, // 6065
|
|
{ PseudoVMSLE_VV_MF4, VMSLE_VV }, // 6066
|
|
{ PseudoVMSLE_VV_MF4_MASK, VMSLE_VV }, // 6067
|
|
{ PseudoVMSLE_VV_MF8, VMSLE_VV }, // 6068
|
|
{ PseudoVMSLE_VV_MF8_MASK, VMSLE_VV }, // 6069
|
|
{ PseudoVMSLE_VX_M1, VMSLE_VX }, // 6070
|
|
{ PseudoVMSLE_VX_M1_MASK, VMSLE_VX }, // 6071
|
|
{ PseudoVMSLE_VX_M2, VMSLE_VX }, // 6072
|
|
{ PseudoVMSLE_VX_M2_MASK, VMSLE_VX }, // 6073
|
|
{ PseudoVMSLE_VX_M4, VMSLE_VX }, // 6074
|
|
{ PseudoVMSLE_VX_M4_MASK, VMSLE_VX }, // 6075
|
|
{ PseudoVMSLE_VX_M8, VMSLE_VX }, // 6076
|
|
{ PseudoVMSLE_VX_M8_MASK, VMSLE_VX }, // 6077
|
|
{ PseudoVMSLE_VX_MF2, VMSLE_VX }, // 6078
|
|
{ PseudoVMSLE_VX_MF2_MASK, VMSLE_VX }, // 6079
|
|
{ PseudoVMSLE_VX_MF4, VMSLE_VX }, // 6080
|
|
{ PseudoVMSLE_VX_MF4_MASK, VMSLE_VX }, // 6081
|
|
{ PseudoVMSLE_VX_MF8, VMSLE_VX }, // 6082
|
|
{ PseudoVMSLE_VX_MF8_MASK, VMSLE_VX }, // 6083
|
|
{ PseudoVMSLTU_VV_M1, VMSLTU_VV }, // 6084
|
|
{ PseudoVMSLTU_VV_M1_MASK, VMSLTU_VV }, // 6085
|
|
{ PseudoVMSLTU_VV_M2, VMSLTU_VV }, // 6086
|
|
{ PseudoVMSLTU_VV_M2_MASK, VMSLTU_VV }, // 6087
|
|
{ PseudoVMSLTU_VV_M4, VMSLTU_VV }, // 6088
|
|
{ PseudoVMSLTU_VV_M4_MASK, VMSLTU_VV }, // 6089
|
|
{ PseudoVMSLTU_VV_M8, VMSLTU_VV }, // 6090
|
|
{ PseudoVMSLTU_VV_M8_MASK, VMSLTU_VV }, // 6091
|
|
{ PseudoVMSLTU_VV_MF2, VMSLTU_VV }, // 6092
|
|
{ PseudoVMSLTU_VV_MF2_MASK, VMSLTU_VV }, // 6093
|
|
{ PseudoVMSLTU_VV_MF4, VMSLTU_VV }, // 6094
|
|
{ PseudoVMSLTU_VV_MF4_MASK, VMSLTU_VV }, // 6095
|
|
{ PseudoVMSLTU_VV_MF8, VMSLTU_VV }, // 6096
|
|
{ PseudoVMSLTU_VV_MF8_MASK, VMSLTU_VV }, // 6097
|
|
{ PseudoVMSLTU_VX_M1, VMSLTU_VX }, // 6098
|
|
{ PseudoVMSLTU_VX_M1_MASK, VMSLTU_VX }, // 6099
|
|
{ PseudoVMSLTU_VX_M2, VMSLTU_VX }, // 6100
|
|
{ PseudoVMSLTU_VX_M2_MASK, VMSLTU_VX }, // 6101
|
|
{ PseudoVMSLTU_VX_M4, VMSLTU_VX }, // 6102
|
|
{ PseudoVMSLTU_VX_M4_MASK, VMSLTU_VX }, // 6103
|
|
{ PseudoVMSLTU_VX_M8, VMSLTU_VX }, // 6104
|
|
{ PseudoVMSLTU_VX_M8_MASK, VMSLTU_VX }, // 6105
|
|
{ PseudoVMSLTU_VX_MF2, VMSLTU_VX }, // 6106
|
|
{ PseudoVMSLTU_VX_MF2_MASK, VMSLTU_VX }, // 6107
|
|
{ PseudoVMSLTU_VX_MF4, VMSLTU_VX }, // 6108
|
|
{ PseudoVMSLTU_VX_MF4_MASK, VMSLTU_VX }, // 6109
|
|
{ PseudoVMSLTU_VX_MF8, VMSLTU_VX }, // 6110
|
|
{ PseudoVMSLTU_VX_MF8_MASK, VMSLTU_VX }, // 6111
|
|
{ PseudoVMSLT_VV_M1, VMSLT_VV }, // 6112
|
|
{ PseudoVMSLT_VV_M1_MASK, VMSLT_VV }, // 6113
|
|
{ PseudoVMSLT_VV_M2, VMSLT_VV }, // 6114
|
|
{ PseudoVMSLT_VV_M2_MASK, VMSLT_VV }, // 6115
|
|
{ PseudoVMSLT_VV_M4, VMSLT_VV }, // 6116
|
|
{ PseudoVMSLT_VV_M4_MASK, VMSLT_VV }, // 6117
|
|
{ PseudoVMSLT_VV_M8, VMSLT_VV }, // 6118
|
|
{ PseudoVMSLT_VV_M8_MASK, VMSLT_VV }, // 6119
|
|
{ PseudoVMSLT_VV_MF2, VMSLT_VV }, // 6120
|
|
{ PseudoVMSLT_VV_MF2_MASK, VMSLT_VV }, // 6121
|
|
{ PseudoVMSLT_VV_MF4, VMSLT_VV }, // 6122
|
|
{ PseudoVMSLT_VV_MF4_MASK, VMSLT_VV }, // 6123
|
|
{ PseudoVMSLT_VV_MF8, VMSLT_VV }, // 6124
|
|
{ PseudoVMSLT_VV_MF8_MASK, VMSLT_VV }, // 6125
|
|
{ PseudoVMSLT_VX_M1, VMSLT_VX }, // 6126
|
|
{ PseudoVMSLT_VX_M1_MASK, VMSLT_VX }, // 6127
|
|
{ PseudoVMSLT_VX_M2, VMSLT_VX }, // 6128
|
|
{ PseudoVMSLT_VX_M2_MASK, VMSLT_VX }, // 6129
|
|
{ PseudoVMSLT_VX_M4, VMSLT_VX }, // 6130
|
|
{ PseudoVMSLT_VX_M4_MASK, VMSLT_VX }, // 6131
|
|
{ PseudoVMSLT_VX_M8, VMSLT_VX }, // 6132
|
|
{ PseudoVMSLT_VX_M8_MASK, VMSLT_VX }, // 6133
|
|
{ PseudoVMSLT_VX_MF2, VMSLT_VX }, // 6134
|
|
{ PseudoVMSLT_VX_MF2_MASK, VMSLT_VX }, // 6135
|
|
{ PseudoVMSLT_VX_MF4, VMSLT_VX }, // 6136
|
|
{ PseudoVMSLT_VX_MF4_MASK, VMSLT_VX }, // 6137
|
|
{ PseudoVMSLT_VX_MF8, VMSLT_VX }, // 6138
|
|
{ PseudoVMSLT_VX_MF8_MASK, VMSLT_VX }, // 6139
|
|
{ PseudoVMSNE_VI_M1, VMSNE_VI }, // 6140
|
|
{ PseudoVMSNE_VI_M1_MASK, VMSNE_VI }, // 6141
|
|
{ PseudoVMSNE_VI_M2, VMSNE_VI }, // 6142
|
|
{ PseudoVMSNE_VI_M2_MASK, VMSNE_VI }, // 6143
|
|
{ PseudoVMSNE_VI_M4, VMSNE_VI }, // 6144
|
|
{ PseudoVMSNE_VI_M4_MASK, VMSNE_VI }, // 6145
|
|
{ PseudoVMSNE_VI_M8, VMSNE_VI }, // 6146
|
|
{ PseudoVMSNE_VI_M8_MASK, VMSNE_VI }, // 6147
|
|
{ PseudoVMSNE_VI_MF2, VMSNE_VI }, // 6148
|
|
{ PseudoVMSNE_VI_MF2_MASK, VMSNE_VI }, // 6149
|
|
{ PseudoVMSNE_VI_MF4, VMSNE_VI }, // 6150
|
|
{ PseudoVMSNE_VI_MF4_MASK, VMSNE_VI }, // 6151
|
|
{ PseudoVMSNE_VI_MF8, VMSNE_VI }, // 6152
|
|
{ PseudoVMSNE_VI_MF8_MASK, VMSNE_VI }, // 6153
|
|
{ PseudoVMSNE_VV_M1, VMSNE_VV }, // 6154
|
|
{ PseudoVMSNE_VV_M1_MASK, VMSNE_VV }, // 6155
|
|
{ PseudoVMSNE_VV_M2, VMSNE_VV }, // 6156
|
|
{ PseudoVMSNE_VV_M2_MASK, VMSNE_VV }, // 6157
|
|
{ PseudoVMSNE_VV_M4, VMSNE_VV }, // 6158
|
|
{ PseudoVMSNE_VV_M4_MASK, VMSNE_VV }, // 6159
|
|
{ PseudoVMSNE_VV_M8, VMSNE_VV }, // 6160
|
|
{ PseudoVMSNE_VV_M8_MASK, VMSNE_VV }, // 6161
|
|
{ PseudoVMSNE_VV_MF2, VMSNE_VV }, // 6162
|
|
{ PseudoVMSNE_VV_MF2_MASK, VMSNE_VV }, // 6163
|
|
{ PseudoVMSNE_VV_MF4, VMSNE_VV }, // 6164
|
|
{ PseudoVMSNE_VV_MF4_MASK, VMSNE_VV }, // 6165
|
|
{ PseudoVMSNE_VV_MF8, VMSNE_VV }, // 6166
|
|
{ PseudoVMSNE_VV_MF8_MASK, VMSNE_VV }, // 6167
|
|
{ PseudoVMSNE_VX_M1, VMSNE_VX }, // 6168
|
|
{ PseudoVMSNE_VX_M1_MASK, VMSNE_VX }, // 6169
|
|
{ PseudoVMSNE_VX_M2, VMSNE_VX }, // 6170
|
|
{ PseudoVMSNE_VX_M2_MASK, VMSNE_VX }, // 6171
|
|
{ PseudoVMSNE_VX_M4, VMSNE_VX }, // 6172
|
|
{ PseudoVMSNE_VX_M4_MASK, VMSNE_VX }, // 6173
|
|
{ PseudoVMSNE_VX_M8, VMSNE_VX }, // 6174
|
|
{ PseudoVMSNE_VX_M8_MASK, VMSNE_VX }, // 6175
|
|
{ PseudoVMSNE_VX_MF2, VMSNE_VX }, // 6176
|
|
{ PseudoVMSNE_VX_MF2_MASK, VMSNE_VX }, // 6177
|
|
{ PseudoVMSNE_VX_MF4, VMSNE_VX }, // 6178
|
|
{ PseudoVMSNE_VX_MF4_MASK, VMSNE_VX }, // 6179
|
|
{ PseudoVMSNE_VX_MF8, VMSNE_VX }, // 6180
|
|
{ PseudoVMSNE_VX_MF8_MASK, VMSNE_VX }, // 6181
|
|
{ PseudoVMSOF_M_B1, VMSOF_M }, // 6182
|
|
{ PseudoVMSOF_M_B16, VMSOF_M }, // 6183
|
|
{ PseudoVMSOF_M_B16_MASK, VMSOF_M }, // 6184
|
|
{ PseudoVMSOF_M_B1_MASK, VMSOF_M }, // 6185
|
|
{ PseudoVMSOF_M_B2, VMSOF_M }, // 6186
|
|
{ PseudoVMSOF_M_B2_MASK, VMSOF_M }, // 6187
|
|
{ PseudoVMSOF_M_B32, VMSOF_M }, // 6188
|
|
{ PseudoVMSOF_M_B32_MASK, VMSOF_M }, // 6189
|
|
{ PseudoVMSOF_M_B4, VMSOF_M }, // 6190
|
|
{ PseudoVMSOF_M_B4_MASK, VMSOF_M }, // 6191
|
|
{ PseudoVMSOF_M_B64, VMSOF_M }, // 6192
|
|
{ PseudoVMSOF_M_B64_MASK, VMSOF_M }, // 6193
|
|
{ PseudoVMSOF_M_B8, VMSOF_M }, // 6194
|
|
{ PseudoVMSOF_M_B8_MASK, VMSOF_M }, // 6195
|
|
{ PseudoVMULHSU_VV_M1, VMULHSU_VV }, // 6196
|
|
{ PseudoVMULHSU_VV_M1_MASK, VMULHSU_VV }, // 6197
|
|
{ PseudoVMULHSU_VV_M2, VMULHSU_VV }, // 6198
|
|
{ PseudoVMULHSU_VV_M2_MASK, VMULHSU_VV }, // 6199
|
|
{ PseudoVMULHSU_VV_M4, VMULHSU_VV }, // 6200
|
|
{ PseudoVMULHSU_VV_M4_MASK, VMULHSU_VV }, // 6201
|
|
{ PseudoVMULHSU_VV_M8, VMULHSU_VV }, // 6202
|
|
{ PseudoVMULHSU_VV_M8_MASK, VMULHSU_VV }, // 6203
|
|
{ PseudoVMULHSU_VV_MF2, VMULHSU_VV }, // 6204
|
|
{ PseudoVMULHSU_VV_MF2_MASK, VMULHSU_VV }, // 6205
|
|
{ PseudoVMULHSU_VV_MF4, VMULHSU_VV }, // 6206
|
|
{ PseudoVMULHSU_VV_MF4_MASK, VMULHSU_VV }, // 6207
|
|
{ PseudoVMULHSU_VV_MF8, VMULHSU_VV }, // 6208
|
|
{ PseudoVMULHSU_VV_MF8_MASK, VMULHSU_VV }, // 6209
|
|
{ PseudoVMULHSU_VX_M1, VMULHSU_VX }, // 6210
|
|
{ PseudoVMULHSU_VX_M1_MASK, VMULHSU_VX }, // 6211
|
|
{ PseudoVMULHSU_VX_M2, VMULHSU_VX }, // 6212
|
|
{ PseudoVMULHSU_VX_M2_MASK, VMULHSU_VX }, // 6213
|
|
{ PseudoVMULHSU_VX_M4, VMULHSU_VX }, // 6214
|
|
{ PseudoVMULHSU_VX_M4_MASK, VMULHSU_VX }, // 6215
|
|
{ PseudoVMULHSU_VX_M8, VMULHSU_VX }, // 6216
|
|
{ PseudoVMULHSU_VX_M8_MASK, VMULHSU_VX }, // 6217
|
|
{ PseudoVMULHSU_VX_MF2, VMULHSU_VX }, // 6218
|
|
{ PseudoVMULHSU_VX_MF2_MASK, VMULHSU_VX }, // 6219
|
|
{ PseudoVMULHSU_VX_MF4, VMULHSU_VX }, // 6220
|
|
{ PseudoVMULHSU_VX_MF4_MASK, VMULHSU_VX }, // 6221
|
|
{ PseudoVMULHSU_VX_MF8, VMULHSU_VX }, // 6222
|
|
{ PseudoVMULHSU_VX_MF8_MASK, VMULHSU_VX }, // 6223
|
|
{ PseudoVMULHU_VV_M1, VMULHU_VV }, // 6224
|
|
{ PseudoVMULHU_VV_M1_MASK, VMULHU_VV }, // 6225
|
|
{ PseudoVMULHU_VV_M2, VMULHU_VV }, // 6226
|
|
{ PseudoVMULHU_VV_M2_MASK, VMULHU_VV }, // 6227
|
|
{ PseudoVMULHU_VV_M4, VMULHU_VV }, // 6228
|
|
{ PseudoVMULHU_VV_M4_MASK, VMULHU_VV }, // 6229
|
|
{ PseudoVMULHU_VV_M8, VMULHU_VV }, // 6230
|
|
{ PseudoVMULHU_VV_M8_MASK, VMULHU_VV }, // 6231
|
|
{ PseudoVMULHU_VV_MF2, VMULHU_VV }, // 6232
|
|
{ PseudoVMULHU_VV_MF2_MASK, VMULHU_VV }, // 6233
|
|
{ PseudoVMULHU_VV_MF4, VMULHU_VV }, // 6234
|
|
{ PseudoVMULHU_VV_MF4_MASK, VMULHU_VV }, // 6235
|
|
{ PseudoVMULHU_VV_MF8, VMULHU_VV }, // 6236
|
|
{ PseudoVMULHU_VV_MF8_MASK, VMULHU_VV }, // 6237
|
|
{ PseudoVMULHU_VX_M1, VMULHU_VX }, // 6238
|
|
{ PseudoVMULHU_VX_M1_MASK, VMULHU_VX }, // 6239
|
|
{ PseudoVMULHU_VX_M2, VMULHU_VX }, // 6240
|
|
{ PseudoVMULHU_VX_M2_MASK, VMULHU_VX }, // 6241
|
|
{ PseudoVMULHU_VX_M4, VMULHU_VX }, // 6242
|
|
{ PseudoVMULHU_VX_M4_MASK, VMULHU_VX }, // 6243
|
|
{ PseudoVMULHU_VX_M8, VMULHU_VX }, // 6244
|
|
{ PseudoVMULHU_VX_M8_MASK, VMULHU_VX }, // 6245
|
|
{ PseudoVMULHU_VX_MF2, VMULHU_VX }, // 6246
|
|
{ PseudoVMULHU_VX_MF2_MASK, VMULHU_VX }, // 6247
|
|
{ PseudoVMULHU_VX_MF4, VMULHU_VX }, // 6248
|
|
{ PseudoVMULHU_VX_MF4_MASK, VMULHU_VX }, // 6249
|
|
{ PseudoVMULHU_VX_MF8, VMULHU_VX }, // 6250
|
|
{ PseudoVMULHU_VX_MF8_MASK, VMULHU_VX }, // 6251
|
|
{ PseudoVMULH_VV_M1, VMULH_VV }, // 6252
|
|
{ PseudoVMULH_VV_M1_MASK, VMULH_VV }, // 6253
|
|
{ PseudoVMULH_VV_M2, VMULH_VV }, // 6254
|
|
{ PseudoVMULH_VV_M2_MASK, VMULH_VV }, // 6255
|
|
{ PseudoVMULH_VV_M4, VMULH_VV }, // 6256
|
|
{ PseudoVMULH_VV_M4_MASK, VMULH_VV }, // 6257
|
|
{ PseudoVMULH_VV_M8, VMULH_VV }, // 6258
|
|
{ PseudoVMULH_VV_M8_MASK, VMULH_VV }, // 6259
|
|
{ PseudoVMULH_VV_MF2, VMULH_VV }, // 6260
|
|
{ PseudoVMULH_VV_MF2_MASK, VMULH_VV }, // 6261
|
|
{ PseudoVMULH_VV_MF4, VMULH_VV }, // 6262
|
|
{ PseudoVMULH_VV_MF4_MASK, VMULH_VV }, // 6263
|
|
{ PseudoVMULH_VV_MF8, VMULH_VV }, // 6264
|
|
{ PseudoVMULH_VV_MF8_MASK, VMULH_VV }, // 6265
|
|
{ PseudoVMULH_VX_M1, VMULH_VX }, // 6266
|
|
{ PseudoVMULH_VX_M1_MASK, VMULH_VX }, // 6267
|
|
{ PseudoVMULH_VX_M2, VMULH_VX }, // 6268
|
|
{ PseudoVMULH_VX_M2_MASK, VMULH_VX }, // 6269
|
|
{ PseudoVMULH_VX_M4, VMULH_VX }, // 6270
|
|
{ PseudoVMULH_VX_M4_MASK, VMULH_VX }, // 6271
|
|
{ PseudoVMULH_VX_M8, VMULH_VX }, // 6272
|
|
{ PseudoVMULH_VX_M8_MASK, VMULH_VX }, // 6273
|
|
{ PseudoVMULH_VX_MF2, VMULH_VX }, // 6274
|
|
{ PseudoVMULH_VX_MF2_MASK, VMULH_VX }, // 6275
|
|
{ PseudoVMULH_VX_MF4, VMULH_VX }, // 6276
|
|
{ PseudoVMULH_VX_MF4_MASK, VMULH_VX }, // 6277
|
|
{ PseudoVMULH_VX_MF8, VMULH_VX }, // 6278
|
|
{ PseudoVMULH_VX_MF8_MASK, VMULH_VX }, // 6279
|
|
{ PseudoVMUL_VV_M1, VMUL_VV }, // 6280
|
|
{ PseudoVMUL_VV_M1_MASK, VMUL_VV }, // 6281
|
|
{ PseudoVMUL_VV_M2, VMUL_VV }, // 6282
|
|
{ PseudoVMUL_VV_M2_MASK, VMUL_VV }, // 6283
|
|
{ PseudoVMUL_VV_M4, VMUL_VV }, // 6284
|
|
{ PseudoVMUL_VV_M4_MASK, VMUL_VV }, // 6285
|
|
{ PseudoVMUL_VV_M8, VMUL_VV }, // 6286
|
|
{ PseudoVMUL_VV_M8_MASK, VMUL_VV }, // 6287
|
|
{ PseudoVMUL_VV_MF2, VMUL_VV }, // 6288
|
|
{ PseudoVMUL_VV_MF2_MASK, VMUL_VV }, // 6289
|
|
{ PseudoVMUL_VV_MF4, VMUL_VV }, // 6290
|
|
{ PseudoVMUL_VV_MF4_MASK, VMUL_VV }, // 6291
|
|
{ PseudoVMUL_VV_MF8, VMUL_VV }, // 6292
|
|
{ PseudoVMUL_VV_MF8_MASK, VMUL_VV }, // 6293
|
|
{ PseudoVMUL_VX_M1, VMUL_VX }, // 6294
|
|
{ PseudoVMUL_VX_M1_MASK, VMUL_VX }, // 6295
|
|
{ PseudoVMUL_VX_M2, VMUL_VX }, // 6296
|
|
{ PseudoVMUL_VX_M2_MASK, VMUL_VX }, // 6297
|
|
{ PseudoVMUL_VX_M4, VMUL_VX }, // 6298
|
|
{ PseudoVMUL_VX_M4_MASK, VMUL_VX }, // 6299
|
|
{ PseudoVMUL_VX_M8, VMUL_VX }, // 6300
|
|
{ PseudoVMUL_VX_M8_MASK, VMUL_VX }, // 6301
|
|
{ PseudoVMUL_VX_MF2, VMUL_VX }, // 6302
|
|
{ PseudoVMUL_VX_MF2_MASK, VMUL_VX }, // 6303
|
|
{ PseudoVMUL_VX_MF4, VMUL_VX }, // 6304
|
|
{ PseudoVMUL_VX_MF4_MASK, VMUL_VX }, // 6305
|
|
{ PseudoVMUL_VX_MF8, VMUL_VX }, // 6306
|
|
{ PseudoVMUL_VX_MF8_MASK, VMUL_VX }, // 6307
|
|
{ PseudoVMV_S_X, VMV_S_X }, // 6308
|
|
{ PseudoVMV_V_I_M1, VMV_V_I }, // 6309
|
|
{ PseudoVMV_V_I_M2, VMV_V_I }, // 6310
|
|
{ PseudoVMV_V_I_M4, VMV_V_I }, // 6311
|
|
{ PseudoVMV_V_I_M8, VMV_V_I }, // 6312
|
|
{ PseudoVMV_V_I_MF2, VMV_V_I }, // 6313
|
|
{ PseudoVMV_V_I_MF4, VMV_V_I }, // 6314
|
|
{ PseudoVMV_V_I_MF8, VMV_V_I }, // 6315
|
|
{ PseudoVMV_V_V_M1, VMV_V_V }, // 6316
|
|
{ PseudoVMV_V_V_M2, VMV_V_V }, // 6317
|
|
{ PseudoVMV_V_V_M4, VMV_V_V }, // 6318
|
|
{ PseudoVMV_V_V_M8, VMV_V_V }, // 6319
|
|
{ PseudoVMV_V_V_MF2, VMV_V_V }, // 6320
|
|
{ PseudoVMV_V_V_MF4, VMV_V_V }, // 6321
|
|
{ PseudoVMV_V_V_MF8, VMV_V_V }, // 6322
|
|
{ PseudoVMV_V_X_M1, VMV_V_X }, // 6323
|
|
{ PseudoVMV_V_X_M2, VMV_V_X }, // 6324
|
|
{ PseudoVMV_V_X_M4, VMV_V_X }, // 6325
|
|
{ PseudoVMV_V_X_M8, VMV_V_X }, // 6326
|
|
{ PseudoVMV_V_X_MF2, VMV_V_X }, // 6327
|
|
{ PseudoVMV_V_X_MF4, VMV_V_X }, // 6328
|
|
{ PseudoVMV_V_X_MF8, VMV_V_X }, // 6329
|
|
{ PseudoVMV_X_S, VMV_X_S }, // 6330
|
|
{ PseudoVMXNOR_MM_M1, VMXNOR_MM }, // 6331
|
|
{ PseudoVMXNOR_MM_M2, VMXNOR_MM }, // 6332
|
|
{ PseudoVMXNOR_MM_M4, VMXNOR_MM }, // 6333
|
|
{ PseudoVMXNOR_MM_M8, VMXNOR_MM }, // 6334
|
|
{ PseudoVMXNOR_MM_MF2, VMXNOR_MM }, // 6335
|
|
{ PseudoVMXNOR_MM_MF4, VMXNOR_MM }, // 6336
|
|
{ PseudoVMXNOR_MM_MF8, VMXNOR_MM }, // 6337
|
|
{ PseudoVMXOR_MM_M1, VMXOR_MM }, // 6338
|
|
{ PseudoVMXOR_MM_M2, VMXOR_MM }, // 6339
|
|
{ PseudoVMXOR_MM_M4, VMXOR_MM }, // 6340
|
|
{ PseudoVMXOR_MM_M8, VMXOR_MM }, // 6341
|
|
{ PseudoVMXOR_MM_MF2, VMXOR_MM }, // 6342
|
|
{ PseudoVMXOR_MM_MF4, VMXOR_MM }, // 6343
|
|
{ PseudoVMXOR_MM_MF8, VMXOR_MM }, // 6344
|
|
{ PseudoVNCLIPU_WI_M1, VNCLIPU_WI }, // 6345
|
|
{ PseudoVNCLIPU_WI_M1_MASK, VNCLIPU_WI }, // 6346
|
|
{ PseudoVNCLIPU_WI_M2, VNCLIPU_WI }, // 6347
|
|
{ PseudoVNCLIPU_WI_M2_MASK, VNCLIPU_WI }, // 6348
|
|
{ PseudoVNCLIPU_WI_M4, VNCLIPU_WI }, // 6349
|
|
{ PseudoVNCLIPU_WI_M4_MASK, VNCLIPU_WI }, // 6350
|
|
{ PseudoVNCLIPU_WI_MF2, VNCLIPU_WI }, // 6351
|
|
{ PseudoVNCLIPU_WI_MF2_MASK, VNCLIPU_WI }, // 6352
|
|
{ PseudoVNCLIPU_WI_MF4, VNCLIPU_WI }, // 6353
|
|
{ PseudoVNCLIPU_WI_MF4_MASK, VNCLIPU_WI }, // 6354
|
|
{ PseudoVNCLIPU_WI_MF8, VNCLIPU_WI }, // 6355
|
|
{ PseudoVNCLIPU_WI_MF8_MASK, VNCLIPU_WI }, // 6356
|
|
{ PseudoVNCLIPU_WV_M1, VNCLIPU_WV }, // 6357
|
|
{ PseudoVNCLIPU_WV_M1_MASK, VNCLIPU_WV }, // 6358
|
|
{ PseudoVNCLIPU_WV_M2, VNCLIPU_WV }, // 6359
|
|
{ PseudoVNCLIPU_WV_M2_MASK, VNCLIPU_WV }, // 6360
|
|
{ PseudoVNCLIPU_WV_M4, VNCLIPU_WV }, // 6361
|
|
{ PseudoVNCLIPU_WV_M4_MASK, VNCLIPU_WV }, // 6362
|
|
{ PseudoVNCLIPU_WV_MF2, VNCLIPU_WV }, // 6363
|
|
{ PseudoVNCLIPU_WV_MF2_MASK, VNCLIPU_WV }, // 6364
|
|
{ PseudoVNCLIPU_WV_MF4, VNCLIPU_WV }, // 6365
|
|
{ PseudoVNCLIPU_WV_MF4_MASK, VNCLIPU_WV }, // 6366
|
|
{ PseudoVNCLIPU_WV_MF8, VNCLIPU_WV }, // 6367
|
|
{ PseudoVNCLIPU_WV_MF8_MASK, VNCLIPU_WV }, // 6368
|
|
{ PseudoVNCLIPU_WX_M1, VNCLIPU_WX }, // 6369
|
|
{ PseudoVNCLIPU_WX_M1_MASK, VNCLIPU_WX }, // 6370
|
|
{ PseudoVNCLIPU_WX_M2, VNCLIPU_WX }, // 6371
|
|
{ PseudoVNCLIPU_WX_M2_MASK, VNCLIPU_WX }, // 6372
|
|
{ PseudoVNCLIPU_WX_M4, VNCLIPU_WX }, // 6373
|
|
{ PseudoVNCLIPU_WX_M4_MASK, VNCLIPU_WX }, // 6374
|
|
{ PseudoVNCLIPU_WX_MF2, VNCLIPU_WX }, // 6375
|
|
{ PseudoVNCLIPU_WX_MF2_MASK, VNCLIPU_WX }, // 6376
|
|
{ PseudoVNCLIPU_WX_MF4, VNCLIPU_WX }, // 6377
|
|
{ PseudoVNCLIPU_WX_MF4_MASK, VNCLIPU_WX }, // 6378
|
|
{ PseudoVNCLIPU_WX_MF8, VNCLIPU_WX }, // 6379
|
|
{ PseudoVNCLIPU_WX_MF8_MASK, VNCLIPU_WX }, // 6380
|
|
{ PseudoVNCLIP_WI_M1, VNCLIP_WI }, // 6381
|
|
{ PseudoVNCLIP_WI_M1_MASK, VNCLIP_WI }, // 6382
|
|
{ PseudoVNCLIP_WI_M2, VNCLIP_WI }, // 6383
|
|
{ PseudoVNCLIP_WI_M2_MASK, VNCLIP_WI }, // 6384
|
|
{ PseudoVNCLIP_WI_M4, VNCLIP_WI }, // 6385
|
|
{ PseudoVNCLIP_WI_M4_MASK, VNCLIP_WI }, // 6386
|
|
{ PseudoVNCLIP_WI_MF2, VNCLIP_WI }, // 6387
|
|
{ PseudoVNCLIP_WI_MF2_MASK, VNCLIP_WI }, // 6388
|
|
{ PseudoVNCLIP_WI_MF4, VNCLIP_WI }, // 6389
|
|
{ PseudoVNCLIP_WI_MF4_MASK, VNCLIP_WI }, // 6390
|
|
{ PseudoVNCLIP_WI_MF8, VNCLIP_WI }, // 6391
|
|
{ PseudoVNCLIP_WI_MF8_MASK, VNCLIP_WI }, // 6392
|
|
{ PseudoVNCLIP_WV_M1, VNCLIP_WV }, // 6393
|
|
{ PseudoVNCLIP_WV_M1_MASK, VNCLIP_WV }, // 6394
|
|
{ PseudoVNCLIP_WV_M2, VNCLIP_WV }, // 6395
|
|
{ PseudoVNCLIP_WV_M2_MASK, VNCLIP_WV }, // 6396
|
|
{ PseudoVNCLIP_WV_M4, VNCLIP_WV }, // 6397
|
|
{ PseudoVNCLIP_WV_M4_MASK, VNCLIP_WV }, // 6398
|
|
{ PseudoVNCLIP_WV_MF2, VNCLIP_WV }, // 6399
|
|
{ PseudoVNCLIP_WV_MF2_MASK, VNCLIP_WV }, // 6400
|
|
{ PseudoVNCLIP_WV_MF4, VNCLIP_WV }, // 6401
|
|
{ PseudoVNCLIP_WV_MF4_MASK, VNCLIP_WV }, // 6402
|
|
{ PseudoVNCLIP_WV_MF8, VNCLIP_WV }, // 6403
|
|
{ PseudoVNCLIP_WV_MF8_MASK, VNCLIP_WV }, // 6404
|
|
{ PseudoVNCLIP_WX_M1, VNCLIP_WX }, // 6405
|
|
{ PseudoVNCLIP_WX_M1_MASK, VNCLIP_WX }, // 6406
|
|
{ PseudoVNCLIP_WX_M2, VNCLIP_WX }, // 6407
|
|
{ PseudoVNCLIP_WX_M2_MASK, VNCLIP_WX }, // 6408
|
|
{ PseudoVNCLIP_WX_M4, VNCLIP_WX }, // 6409
|
|
{ PseudoVNCLIP_WX_M4_MASK, VNCLIP_WX }, // 6410
|
|
{ PseudoVNCLIP_WX_MF2, VNCLIP_WX }, // 6411
|
|
{ PseudoVNCLIP_WX_MF2_MASK, VNCLIP_WX }, // 6412
|
|
{ PseudoVNCLIP_WX_MF4, VNCLIP_WX }, // 6413
|
|
{ PseudoVNCLIP_WX_MF4_MASK, VNCLIP_WX }, // 6414
|
|
{ PseudoVNCLIP_WX_MF8, VNCLIP_WX }, // 6415
|
|
{ PseudoVNCLIP_WX_MF8_MASK, VNCLIP_WX }, // 6416
|
|
{ PseudoVNMSAC_VV_M1, VNMSAC_VV }, // 6417
|
|
{ PseudoVNMSAC_VV_M1_MASK, VNMSAC_VV }, // 6418
|
|
{ PseudoVNMSAC_VV_M2, VNMSAC_VV }, // 6419
|
|
{ PseudoVNMSAC_VV_M2_MASK, VNMSAC_VV }, // 6420
|
|
{ PseudoVNMSAC_VV_M4, VNMSAC_VV }, // 6421
|
|
{ PseudoVNMSAC_VV_M4_MASK, VNMSAC_VV }, // 6422
|
|
{ PseudoVNMSAC_VV_M8, VNMSAC_VV }, // 6423
|
|
{ PseudoVNMSAC_VV_M8_MASK, VNMSAC_VV }, // 6424
|
|
{ PseudoVNMSAC_VV_MF2, VNMSAC_VV }, // 6425
|
|
{ PseudoVNMSAC_VV_MF2_MASK, VNMSAC_VV }, // 6426
|
|
{ PseudoVNMSAC_VV_MF4, VNMSAC_VV }, // 6427
|
|
{ PseudoVNMSAC_VV_MF4_MASK, VNMSAC_VV }, // 6428
|
|
{ PseudoVNMSAC_VV_MF8, VNMSAC_VV }, // 6429
|
|
{ PseudoVNMSAC_VV_MF8_MASK, VNMSAC_VV }, // 6430
|
|
{ PseudoVNMSAC_VX_M1, VNMSAC_VX }, // 6431
|
|
{ PseudoVNMSAC_VX_M1_MASK, VNMSAC_VX }, // 6432
|
|
{ PseudoVNMSAC_VX_M2, VNMSAC_VX }, // 6433
|
|
{ PseudoVNMSAC_VX_M2_MASK, VNMSAC_VX }, // 6434
|
|
{ PseudoVNMSAC_VX_M4, VNMSAC_VX }, // 6435
|
|
{ PseudoVNMSAC_VX_M4_MASK, VNMSAC_VX }, // 6436
|
|
{ PseudoVNMSAC_VX_M8, VNMSAC_VX }, // 6437
|
|
{ PseudoVNMSAC_VX_M8_MASK, VNMSAC_VX }, // 6438
|
|
{ PseudoVNMSAC_VX_MF2, VNMSAC_VX }, // 6439
|
|
{ PseudoVNMSAC_VX_MF2_MASK, VNMSAC_VX }, // 6440
|
|
{ PseudoVNMSAC_VX_MF4, VNMSAC_VX }, // 6441
|
|
{ PseudoVNMSAC_VX_MF4_MASK, VNMSAC_VX }, // 6442
|
|
{ PseudoVNMSAC_VX_MF8, VNMSAC_VX }, // 6443
|
|
{ PseudoVNMSAC_VX_MF8_MASK, VNMSAC_VX }, // 6444
|
|
{ PseudoVNMSUB_VV_M1, VNMSUB_VV }, // 6445
|
|
{ PseudoVNMSUB_VV_M1_MASK, VNMSUB_VV }, // 6446
|
|
{ PseudoVNMSUB_VV_M2, VNMSUB_VV }, // 6447
|
|
{ PseudoVNMSUB_VV_M2_MASK, VNMSUB_VV }, // 6448
|
|
{ PseudoVNMSUB_VV_M4, VNMSUB_VV }, // 6449
|
|
{ PseudoVNMSUB_VV_M4_MASK, VNMSUB_VV }, // 6450
|
|
{ PseudoVNMSUB_VV_M8, VNMSUB_VV }, // 6451
|
|
{ PseudoVNMSUB_VV_M8_MASK, VNMSUB_VV }, // 6452
|
|
{ PseudoVNMSUB_VV_MF2, VNMSUB_VV }, // 6453
|
|
{ PseudoVNMSUB_VV_MF2_MASK, VNMSUB_VV }, // 6454
|
|
{ PseudoVNMSUB_VV_MF4, VNMSUB_VV }, // 6455
|
|
{ PseudoVNMSUB_VV_MF4_MASK, VNMSUB_VV }, // 6456
|
|
{ PseudoVNMSUB_VV_MF8, VNMSUB_VV }, // 6457
|
|
{ PseudoVNMSUB_VV_MF8_MASK, VNMSUB_VV }, // 6458
|
|
{ PseudoVNMSUB_VX_M1, VNMSUB_VX }, // 6459
|
|
{ PseudoVNMSUB_VX_M1_MASK, VNMSUB_VX }, // 6460
|
|
{ PseudoVNMSUB_VX_M2, VNMSUB_VX }, // 6461
|
|
{ PseudoVNMSUB_VX_M2_MASK, VNMSUB_VX }, // 6462
|
|
{ PseudoVNMSUB_VX_M4, VNMSUB_VX }, // 6463
|
|
{ PseudoVNMSUB_VX_M4_MASK, VNMSUB_VX }, // 6464
|
|
{ PseudoVNMSUB_VX_M8, VNMSUB_VX }, // 6465
|
|
{ PseudoVNMSUB_VX_M8_MASK, VNMSUB_VX }, // 6466
|
|
{ PseudoVNMSUB_VX_MF2, VNMSUB_VX }, // 6467
|
|
{ PseudoVNMSUB_VX_MF2_MASK, VNMSUB_VX }, // 6468
|
|
{ PseudoVNMSUB_VX_MF4, VNMSUB_VX }, // 6469
|
|
{ PseudoVNMSUB_VX_MF4_MASK, VNMSUB_VX }, // 6470
|
|
{ PseudoVNMSUB_VX_MF8, VNMSUB_VX }, // 6471
|
|
{ PseudoVNMSUB_VX_MF8_MASK, VNMSUB_VX }, // 6472
|
|
{ PseudoVNSRA_WI_M1, VNSRA_WI }, // 6473
|
|
{ PseudoVNSRA_WI_M1_MASK, VNSRA_WI }, // 6474
|
|
{ PseudoVNSRA_WI_M2, VNSRA_WI }, // 6475
|
|
{ PseudoVNSRA_WI_M2_MASK, VNSRA_WI }, // 6476
|
|
{ PseudoVNSRA_WI_M4, VNSRA_WI }, // 6477
|
|
{ PseudoVNSRA_WI_M4_MASK, VNSRA_WI }, // 6478
|
|
{ PseudoVNSRA_WI_MF2, VNSRA_WI }, // 6479
|
|
{ PseudoVNSRA_WI_MF2_MASK, VNSRA_WI }, // 6480
|
|
{ PseudoVNSRA_WI_MF4, VNSRA_WI }, // 6481
|
|
{ PseudoVNSRA_WI_MF4_MASK, VNSRA_WI }, // 6482
|
|
{ PseudoVNSRA_WI_MF8, VNSRA_WI }, // 6483
|
|
{ PseudoVNSRA_WI_MF8_MASK, VNSRA_WI }, // 6484
|
|
{ PseudoVNSRA_WV_M1, VNSRA_WV }, // 6485
|
|
{ PseudoVNSRA_WV_M1_MASK, VNSRA_WV }, // 6486
|
|
{ PseudoVNSRA_WV_M2, VNSRA_WV }, // 6487
|
|
{ PseudoVNSRA_WV_M2_MASK, VNSRA_WV }, // 6488
|
|
{ PseudoVNSRA_WV_M4, VNSRA_WV }, // 6489
|
|
{ PseudoVNSRA_WV_M4_MASK, VNSRA_WV }, // 6490
|
|
{ PseudoVNSRA_WV_MF2, VNSRA_WV }, // 6491
|
|
{ PseudoVNSRA_WV_MF2_MASK, VNSRA_WV }, // 6492
|
|
{ PseudoVNSRA_WV_MF4, VNSRA_WV }, // 6493
|
|
{ PseudoVNSRA_WV_MF4_MASK, VNSRA_WV }, // 6494
|
|
{ PseudoVNSRA_WV_MF8, VNSRA_WV }, // 6495
|
|
{ PseudoVNSRA_WV_MF8_MASK, VNSRA_WV }, // 6496
|
|
{ PseudoVNSRA_WX_M1, VNSRA_WX }, // 6497
|
|
{ PseudoVNSRA_WX_M1_MASK, VNSRA_WX }, // 6498
|
|
{ PseudoVNSRA_WX_M2, VNSRA_WX }, // 6499
|
|
{ PseudoVNSRA_WX_M2_MASK, VNSRA_WX }, // 6500
|
|
{ PseudoVNSRA_WX_M4, VNSRA_WX }, // 6501
|
|
{ PseudoVNSRA_WX_M4_MASK, VNSRA_WX }, // 6502
|
|
{ PseudoVNSRA_WX_MF2, VNSRA_WX }, // 6503
|
|
{ PseudoVNSRA_WX_MF2_MASK, VNSRA_WX }, // 6504
|
|
{ PseudoVNSRA_WX_MF4, VNSRA_WX }, // 6505
|
|
{ PseudoVNSRA_WX_MF4_MASK, VNSRA_WX }, // 6506
|
|
{ PseudoVNSRA_WX_MF8, VNSRA_WX }, // 6507
|
|
{ PseudoVNSRA_WX_MF8_MASK, VNSRA_WX }, // 6508
|
|
{ PseudoVNSRL_WI_M1, VNSRL_WI }, // 6509
|
|
{ PseudoVNSRL_WI_M1_MASK, VNSRL_WI }, // 6510
|
|
{ PseudoVNSRL_WI_M2, VNSRL_WI }, // 6511
|
|
{ PseudoVNSRL_WI_M2_MASK, VNSRL_WI }, // 6512
|
|
{ PseudoVNSRL_WI_M4, VNSRL_WI }, // 6513
|
|
{ PseudoVNSRL_WI_M4_MASK, VNSRL_WI }, // 6514
|
|
{ PseudoVNSRL_WI_MF2, VNSRL_WI }, // 6515
|
|
{ PseudoVNSRL_WI_MF2_MASK, VNSRL_WI }, // 6516
|
|
{ PseudoVNSRL_WI_MF4, VNSRL_WI }, // 6517
|
|
{ PseudoVNSRL_WI_MF4_MASK, VNSRL_WI }, // 6518
|
|
{ PseudoVNSRL_WI_MF8, VNSRL_WI }, // 6519
|
|
{ PseudoVNSRL_WI_MF8_MASK, VNSRL_WI }, // 6520
|
|
{ PseudoVNSRL_WV_M1, VNSRL_WV }, // 6521
|
|
{ PseudoVNSRL_WV_M1_MASK, VNSRL_WV }, // 6522
|
|
{ PseudoVNSRL_WV_M2, VNSRL_WV }, // 6523
|
|
{ PseudoVNSRL_WV_M2_MASK, VNSRL_WV }, // 6524
|
|
{ PseudoVNSRL_WV_M4, VNSRL_WV }, // 6525
|
|
{ PseudoVNSRL_WV_M4_MASK, VNSRL_WV }, // 6526
|
|
{ PseudoVNSRL_WV_MF2, VNSRL_WV }, // 6527
|
|
{ PseudoVNSRL_WV_MF2_MASK, VNSRL_WV }, // 6528
|
|
{ PseudoVNSRL_WV_MF4, VNSRL_WV }, // 6529
|
|
{ PseudoVNSRL_WV_MF4_MASK, VNSRL_WV }, // 6530
|
|
{ PseudoVNSRL_WV_MF8, VNSRL_WV }, // 6531
|
|
{ PseudoVNSRL_WV_MF8_MASK, VNSRL_WV }, // 6532
|
|
{ PseudoVNSRL_WX_M1, VNSRL_WX }, // 6533
|
|
{ PseudoVNSRL_WX_M1_MASK, VNSRL_WX }, // 6534
|
|
{ PseudoVNSRL_WX_M2, VNSRL_WX }, // 6535
|
|
{ PseudoVNSRL_WX_M2_MASK, VNSRL_WX }, // 6536
|
|
{ PseudoVNSRL_WX_M4, VNSRL_WX }, // 6537
|
|
{ PseudoVNSRL_WX_M4_MASK, VNSRL_WX }, // 6538
|
|
{ PseudoVNSRL_WX_MF2, VNSRL_WX }, // 6539
|
|
{ PseudoVNSRL_WX_MF2_MASK, VNSRL_WX }, // 6540
|
|
{ PseudoVNSRL_WX_MF4, VNSRL_WX }, // 6541
|
|
{ PseudoVNSRL_WX_MF4_MASK, VNSRL_WX }, // 6542
|
|
{ PseudoVNSRL_WX_MF8, VNSRL_WX }, // 6543
|
|
{ PseudoVNSRL_WX_MF8_MASK, VNSRL_WX }, // 6544
|
|
{ PseudoVOR_VI_M1, VOR_VI }, // 6545
|
|
{ PseudoVOR_VI_M1_MASK, VOR_VI }, // 6546
|
|
{ PseudoVOR_VI_M2, VOR_VI }, // 6547
|
|
{ PseudoVOR_VI_M2_MASK, VOR_VI }, // 6548
|
|
{ PseudoVOR_VI_M4, VOR_VI }, // 6549
|
|
{ PseudoVOR_VI_M4_MASK, VOR_VI }, // 6550
|
|
{ PseudoVOR_VI_M8, VOR_VI }, // 6551
|
|
{ PseudoVOR_VI_M8_MASK, VOR_VI }, // 6552
|
|
{ PseudoVOR_VI_MF2, VOR_VI }, // 6553
|
|
{ PseudoVOR_VI_MF2_MASK, VOR_VI }, // 6554
|
|
{ PseudoVOR_VI_MF4, VOR_VI }, // 6555
|
|
{ PseudoVOR_VI_MF4_MASK, VOR_VI }, // 6556
|
|
{ PseudoVOR_VI_MF8, VOR_VI }, // 6557
|
|
{ PseudoVOR_VI_MF8_MASK, VOR_VI }, // 6558
|
|
{ PseudoVOR_VV_M1, VOR_VV }, // 6559
|
|
{ PseudoVOR_VV_M1_MASK, VOR_VV }, // 6560
|
|
{ PseudoVOR_VV_M2, VOR_VV }, // 6561
|
|
{ PseudoVOR_VV_M2_MASK, VOR_VV }, // 6562
|
|
{ PseudoVOR_VV_M4, VOR_VV }, // 6563
|
|
{ PseudoVOR_VV_M4_MASK, VOR_VV }, // 6564
|
|
{ PseudoVOR_VV_M8, VOR_VV }, // 6565
|
|
{ PseudoVOR_VV_M8_MASK, VOR_VV }, // 6566
|
|
{ PseudoVOR_VV_MF2, VOR_VV }, // 6567
|
|
{ PseudoVOR_VV_MF2_MASK, VOR_VV }, // 6568
|
|
{ PseudoVOR_VV_MF4, VOR_VV }, // 6569
|
|
{ PseudoVOR_VV_MF4_MASK, VOR_VV }, // 6570
|
|
{ PseudoVOR_VV_MF8, VOR_VV }, // 6571
|
|
{ PseudoVOR_VV_MF8_MASK, VOR_VV }, // 6572
|
|
{ PseudoVOR_VX_M1, VOR_VX }, // 6573
|
|
{ PseudoVOR_VX_M1_MASK, VOR_VX }, // 6574
|
|
{ PseudoVOR_VX_M2, VOR_VX }, // 6575
|
|
{ PseudoVOR_VX_M2_MASK, VOR_VX }, // 6576
|
|
{ PseudoVOR_VX_M4, VOR_VX }, // 6577
|
|
{ PseudoVOR_VX_M4_MASK, VOR_VX }, // 6578
|
|
{ PseudoVOR_VX_M8, VOR_VX }, // 6579
|
|
{ PseudoVOR_VX_M8_MASK, VOR_VX }, // 6580
|
|
{ PseudoVOR_VX_MF2, VOR_VX }, // 6581
|
|
{ PseudoVOR_VX_MF2_MASK, VOR_VX }, // 6582
|
|
{ PseudoVOR_VX_MF4, VOR_VX }, // 6583
|
|
{ PseudoVOR_VX_MF4_MASK, VOR_VX }, // 6584
|
|
{ PseudoVOR_VX_MF8, VOR_VX }, // 6585
|
|
{ PseudoVOR_VX_MF8_MASK, VOR_VX }, // 6586
|
|
{ PseudoVQMACCSU_2x8x2_M1, VQMACCSU_2x8x2 }, // 6587
|
|
{ PseudoVQMACCSU_2x8x2_M2, VQMACCSU_2x8x2 }, // 6588
|
|
{ PseudoVQMACCSU_2x8x2_M4, VQMACCSU_2x8x2 }, // 6589
|
|
{ PseudoVQMACCSU_2x8x2_M8, VQMACCSU_2x8x2 }, // 6590
|
|
{ PseudoVQMACCSU_4x8x4_M1, VQMACCSU_4x8x4 }, // 6591
|
|
{ PseudoVQMACCSU_4x8x4_M2, VQMACCSU_4x8x4 }, // 6592
|
|
{ PseudoVQMACCSU_4x8x4_M4, VQMACCSU_4x8x4 }, // 6593
|
|
{ PseudoVQMACCSU_4x8x4_MF2, VQMACCSU_4x8x4 }, // 6594
|
|
{ PseudoVQMACCUS_2x8x2_M1, VQMACCUS_2x8x2 }, // 6595
|
|
{ PseudoVQMACCUS_2x8x2_M2, VQMACCUS_2x8x2 }, // 6596
|
|
{ PseudoVQMACCUS_2x8x2_M4, VQMACCUS_2x8x2 }, // 6597
|
|
{ PseudoVQMACCUS_2x8x2_M8, VQMACCUS_2x8x2 }, // 6598
|
|
{ PseudoVQMACCUS_4x8x4_M1, VQMACCUS_4x8x4 }, // 6599
|
|
{ PseudoVQMACCUS_4x8x4_M2, VQMACCUS_4x8x4 }, // 6600
|
|
{ PseudoVQMACCUS_4x8x4_M4, VQMACCUS_4x8x4 }, // 6601
|
|
{ PseudoVQMACCUS_4x8x4_MF2, VQMACCUS_4x8x4 }, // 6602
|
|
{ PseudoVQMACCU_2x8x2_M1, VQMACCU_2x8x2 }, // 6603
|
|
{ PseudoVQMACCU_2x8x2_M2, VQMACCU_2x8x2 }, // 6604
|
|
{ PseudoVQMACCU_2x8x2_M4, VQMACCU_2x8x2 }, // 6605
|
|
{ PseudoVQMACCU_2x8x2_M8, VQMACCU_2x8x2 }, // 6606
|
|
{ PseudoVQMACCU_4x8x4_M1, VQMACCU_4x8x4 }, // 6607
|
|
{ PseudoVQMACCU_4x8x4_M2, VQMACCU_4x8x4 }, // 6608
|
|
{ PseudoVQMACCU_4x8x4_M4, VQMACCU_4x8x4 }, // 6609
|
|
{ PseudoVQMACCU_4x8x4_MF2, VQMACCU_4x8x4 }, // 6610
|
|
{ PseudoVQMACC_2x8x2_M1, VQMACC_2x8x2 }, // 6611
|
|
{ PseudoVQMACC_2x8x2_M2, VQMACC_2x8x2 }, // 6612
|
|
{ PseudoVQMACC_2x8x2_M4, VQMACC_2x8x2 }, // 6613
|
|
{ PseudoVQMACC_2x8x2_M8, VQMACC_2x8x2 }, // 6614
|
|
{ PseudoVQMACC_4x8x4_M1, VQMACC_4x8x4 }, // 6615
|
|
{ PseudoVQMACC_4x8x4_M2, VQMACC_4x8x4 }, // 6616
|
|
{ PseudoVQMACC_4x8x4_M4, VQMACC_4x8x4 }, // 6617
|
|
{ PseudoVQMACC_4x8x4_MF2, VQMACC_4x8x4 }, // 6618
|
|
{ PseudoVREDAND_VS_M1_E16, VREDAND_VS }, // 6619
|
|
{ PseudoVREDAND_VS_M1_E16_MASK, VREDAND_VS }, // 6620
|
|
{ PseudoVREDAND_VS_M1_E32, VREDAND_VS }, // 6621
|
|
{ PseudoVREDAND_VS_M1_E32_MASK, VREDAND_VS }, // 6622
|
|
{ PseudoVREDAND_VS_M1_E64, VREDAND_VS }, // 6623
|
|
{ PseudoVREDAND_VS_M1_E64_MASK, VREDAND_VS }, // 6624
|
|
{ PseudoVREDAND_VS_M1_E8, VREDAND_VS }, // 6625
|
|
{ PseudoVREDAND_VS_M1_E8_MASK, VREDAND_VS }, // 6626
|
|
{ PseudoVREDAND_VS_M2_E16, VREDAND_VS }, // 6627
|
|
{ PseudoVREDAND_VS_M2_E16_MASK, VREDAND_VS }, // 6628
|
|
{ PseudoVREDAND_VS_M2_E32, VREDAND_VS }, // 6629
|
|
{ PseudoVREDAND_VS_M2_E32_MASK, VREDAND_VS }, // 6630
|
|
{ PseudoVREDAND_VS_M2_E64, VREDAND_VS }, // 6631
|
|
{ PseudoVREDAND_VS_M2_E64_MASK, VREDAND_VS }, // 6632
|
|
{ PseudoVREDAND_VS_M2_E8, VREDAND_VS }, // 6633
|
|
{ PseudoVREDAND_VS_M2_E8_MASK, VREDAND_VS }, // 6634
|
|
{ PseudoVREDAND_VS_M4_E16, VREDAND_VS }, // 6635
|
|
{ PseudoVREDAND_VS_M4_E16_MASK, VREDAND_VS }, // 6636
|
|
{ PseudoVREDAND_VS_M4_E32, VREDAND_VS }, // 6637
|
|
{ PseudoVREDAND_VS_M4_E32_MASK, VREDAND_VS }, // 6638
|
|
{ PseudoVREDAND_VS_M4_E64, VREDAND_VS }, // 6639
|
|
{ PseudoVREDAND_VS_M4_E64_MASK, VREDAND_VS }, // 6640
|
|
{ PseudoVREDAND_VS_M4_E8, VREDAND_VS }, // 6641
|
|
{ PseudoVREDAND_VS_M4_E8_MASK, VREDAND_VS }, // 6642
|
|
{ PseudoVREDAND_VS_M8_E16, VREDAND_VS }, // 6643
|
|
{ PseudoVREDAND_VS_M8_E16_MASK, VREDAND_VS }, // 6644
|
|
{ PseudoVREDAND_VS_M8_E32, VREDAND_VS }, // 6645
|
|
{ PseudoVREDAND_VS_M8_E32_MASK, VREDAND_VS }, // 6646
|
|
{ PseudoVREDAND_VS_M8_E64, VREDAND_VS }, // 6647
|
|
{ PseudoVREDAND_VS_M8_E64_MASK, VREDAND_VS }, // 6648
|
|
{ PseudoVREDAND_VS_M8_E8, VREDAND_VS }, // 6649
|
|
{ PseudoVREDAND_VS_M8_E8_MASK, VREDAND_VS }, // 6650
|
|
{ PseudoVREDAND_VS_MF2_E16, VREDAND_VS }, // 6651
|
|
{ PseudoVREDAND_VS_MF2_E16_MASK, VREDAND_VS }, // 6652
|
|
{ PseudoVREDAND_VS_MF2_E32, VREDAND_VS }, // 6653
|
|
{ PseudoVREDAND_VS_MF2_E32_MASK, VREDAND_VS }, // 6654
|
|
{ PseudoVREDAND_VS_MF2_E8, VREDAND_VS }, // 6655
|
|
{ PseudoVREDAND_VS_MF2_E8_MASK, VREDAND_VS }, // 6656
|
|
{ PseudoVREDAND_VS_MF4_E16, VREDAND_VS }, // 6657
|
|
{ PseudoVREDAND_VS_MF4_E16_MASK, VREDAND_VS }, // 6658
|
|
{ PseudoVREDAND_VS_MF4_E8, VREDAND_VS }, // 6659
|
|
{ PseudoVREDAND_VS_MF4_E8_MASK, VREDAND_VS }, // 6660
|
|
{ PseudoVREDAND_VS_MF8_E8, VREDAND_VS }, // 6661
|
|
{ PseudoVREDAND_VS_MF8_E8_MASK, VREDAND_VS }, // 6662
|
|
{ PseudoVREDMAXU_VS_M1_E16, VREDMAXU_VS }, // 6663
|
|
{ PseudoVREDMAXU_VS_M1_E16_MASK, VREDMAXU_VS }, // 6664
|
|
{ PseudoVREDMAXU_VS_M1_E32, VREDMAXU_VS }, // 6665
|
|
{ PseudoVREDMAXU_VS_M1_E32_MASK, VREDMAXU_VS }, // 6666
|
|
{ PseudoVREDMAXU_VS_M1_E64, VREDMAXU_VS }, // 6667
|
|
{ PseudoVREDMAXU_VS_M1_E64_MASK, VREDMAXU_VS }, // 6668
|
|
{ PseudoVREDMAXU_VS_M1_E8, VREDMAXU_VS }, // 6669
|
|
{ PseudoVREDMAXU_VS_M1_E8_MASK, VREDMAXU_VS }, // 6670
|
|
{ PseudoVREDMAXU_VS_M2_E16, VREDMAXU_VS }, // 6671
|
|
{ PseudoVREDMAXU_VS_M2_E16_MASK, VREDMAXU_VS }, // 6672
|
|
{ PseudoVREDMAXU_VS_M2_E32, VREDMAXU_VS }, // 6673
|
|
{ PseudoVREDMAXU_VS_M2_E32_MASK, VREDMAXU_VS }, // 6674
|
|
{ PseudoVREDMAXU_VS_M2_E64, VREDMAXU_VS }, // 6675
|
|
{ PseudoVREDMAXU_VS_M2_E64_MASK, VREDMAXU_VS }, // 6676
|
|
{ PseudoVREDMAXU_VS_M2_E8, VREDMAXU_VS }, // 6677
|
|
{ PseudoVREDMAXU_VS_M2_E8_MASK, VREDMAXU_VS }, // 6678
|
|
{ PseudoVREDMAXU_VS_M4_E16, VREDMAXU_VS }, // 6679
|
|
{ PseudoVREDMAXU_VS_M4_E16_MASK, VREDMAXU_VS }, // 6680
|
|
{ PseudoVREDMAXU_VS_M4_E32, VREDMAXU_VS }, // 6681
|
|
{ PseudoVREDMAXU_VS_M4_E32_MASK, VREDMAXU_VS }, // 6682
|
|
{ PseudoVREDMAXU_VS_M4_E64, VREDMAXU_VS }, // 6683
|
|
{ PseudoVREDMAXU_VS_M4_E64_MASK, VREDMAXU_VS }, // 6684
|
|
{ PseudoVREDMAXU_VS_M4_E8, VREDMAXU_VS }, // 6685
|
|
{ PseudoVREDMAXU_VS_M4_E8_MASK, VREDMAXU_VS }, // 6686
|
|
{ PseudoVREDMAXU_VS_M8_E16, VREDMAXU_VS }, // 6687
|
|
{ PseudoVREDMAXU_VS_M8_E16_MASK, VREDMAXU_VS }, // 6688
|
|
{ PseudoVREDMAXU_VS_M8_E32, VREDMAXU_VS }, // 6689
|
|
{ PseudoVREDMAXU_VS_M8_E32_MASK, VREDMAXU_VS }, // 6690
|
|
{ PseudoVREDMAXU_VS_M8_E64, VREDMAXU_VS }, // 6691
|
|
{ PseudoVREDMAXU_VS_M8_E64_MASK, VREDMAXU_VS }, // 6692
|
|
{ PseudoVREDMAXU_VS_M8_E8, VREDMAXU_VS }, // 6693
|
|
{ PseudoVREDMAXU_VS_M8_E8_MASK, VREDMAXU_VS }, // 6694
|
|
{ PseudoVREDMAXU_VS_MF2_E16, VREDMAXU_VS }, // 6695
|
|
{ PseudoVREDMAXU_VS_MF2_E16_MASK, VREDMAXU_VS }, // 6696
|
|
{ PseudoVREDMAXU_VS_MF2_E32, VREDMAXU_VS }, // 6697
|
|
{ PseudoVREDMAXU_VS_MF2_E32_MASK, VREDMAXU_VS }, // 6698
|
|
{ PseudoVREDMAXU_VS_MF2_E8, VREDMAXU_VS }, // 6699
|
|
{ PseudoVREDMAXU_VS_MF2_E8_MASK, VREDMAXU_VS }, // 6700
|
|
{ PseudoVREDMAXU_VS_MF4_E16, VREDMAXU_VS }, // 6701
|
|
{ PseudoVREDMAXU_VS_MF4_E16_MASK, VREDMAXU_VS }, // 6702
|
|
{ PseudoVREDMAXU_VS_MF4_E8, VREDMAXU_VS }, // 6703
|
|
{ PseudoVREDMAXU_VS_MF4_E8_MASK, VREDMAXU_VS }, // 6704
|
|
{ PseudoVREDMAXU_VS_MF8_E8, VREDMAXU_VS }, // 6705
|
|
{ PseudoVREDMAXU_VS_MF8_E8_MASK, VREDMAXU_VS }, // 6706
|
|
{ PseudoVREDMAX_VS_M1_E16, VREDMAX_VS }, // 6707
|
|
{ PseudoVREDMAX_VS_M1_E16_MASK, VREDMAX_VS }, // 6708
|
|
{ PseudoVREDMAX_VS_M1_E32, VREDMAX_VS }, // 6709
|
|
{ PseudoVREDMAX_VS_M1_E32_MASK, VREDMAX_VS }, // 6710
|
|
{ PseudoVREDMAX_VS_M1_E64, VREDMAX_VS }, // 6711
|
|
{ PseudoVREDMAX_VS_M1_E64_MASK, VREDMAX_VS }, // 6712
|
|
{ PseudoVREDMAX_VS_M1_E8, VREDMAX_VS }, // 6713
|
|
{ PseudoVREDMAX_VS_M1_E8_MASK, VREDMAX_VS }, // 6714
|
|
{ PseudoVREDMAX_VS_M2_E16, VREDMAX_VS }, // 6715
|
|
{ PseudoVREDMAX_VS_M2_E16_MASK, VREDMAX_VS }, // 6716
|
|
{ PseudoVREDMAX_VS_M2_E32, VREDMAX_VS }, // 6717
|
|
{ PseudoVREDMAX_VS_M2_E32_MASK, VREDMAX_VS }, // 6718
|
|
{ PseudoVREDMAX_VS_M2_E64, VREDMAX_VS }, // 6719
|
|
{ PseudoVREDMAX_VS_M2_E64_MASK, VREDMAX_VS }, // 6720
|
|
{ PseudoVREDMAX_VS_M2_E8, VREDMAX_VS }, // 6721
|
|
{ PseudoVREDMAX_VS_M2_E8_MASK, VREDMAX_VS }, // 6722
|
|
{ PseudoVREDMAX_VS_M4_E16, VREDMAX_VS }, // 6723
|
|
{ PseudoVREDMAX_VS_M4_E16_MASK, VREDMAX_VS }, // 6724
|
|
{ PseudoVREDMAX_VS_M4_E32, VREDMAX_VS }, // 6725
|
|
{ PseudoVREDMAX_VS_M4_E32_MASK, VREDMAX_VS }, // 6726
|
|
{ PseudoVREDMAX_VS_M4_E64, VREDMAX_VS }, // 6727
|
|
{ PseudoVREDMAX_VS_M4_E64_MASK, VREDMAX_VS }, // 6728
|
|
{ PseudoVREDMAX_VS_M4_E8, VREDMAX_VS }, // 6729
|
|
{ PseudoVREDMAX_VS_M4_E8_MASK, VREDMAX_VS }, // 6730
|
|
{ PseudoVREDMAX_VS_M8_E16, VREDMAX_VS }, // 6731
|
|
{ PseudoVREDMAX_VS_M8_E16_MASK, VREDMAX_VS }, // 6732
|
|
{ PseudoVREDMAX_VS_M8_E32, VREDMAX_VS }, // 6733
|
|
{ PseudoVREDMAX_VS_M8_E32_MASK, VREDMAX_VS }, // 6734
|
|
{ PseudoVREDMAX_VS_M8_E64, VREDMAX_VS }, // 6735
|
|
{ PseudoVREDMAX_VS_M8_E64_MASK, VREDMAX_VS }, // 6736
|
|
{ PseudoVREDMAX_VS_M8_E8, VREDMAX_VS }, // 6737
|
|
{ PseudoVREDMAX_VS_M8_E8_MASK, VREDMAX_VS }, // 6738
|
|
{ PseudoVREDMAX_VS_MF2_E16, VREDMAX_VS }, // 6739
|
|
{ PseudoVREDMAX_VS_MF2_E16_MASK, VREDMAX_VS }, // 6740
|
|
{ PseudoVREDMAX_VS_MF2_E32, VREDMAX_VS }, // 6741
|
|
{ PseudoVREDMAX_VS_MF2_E32_MASK, VREDMAX_VS }, // 6742
|
|
{ PseudoVREDMAX_VS_MF2_E8, VREDMAX_VS }, // 6743
|
|
{ PseudoVREDMAX_VS_MF2_E8_MASK, VREDMAX_VS }, // 6744
|
|
{ PseudoVREDMAX_VS_MF4_E16, VREDMAX_VS }, // 6745
|
|
{ PseudoVREDMAX_VS_MF4_E16_MASK, VREDMAX_VS }, // 6746
|
|
{ PseudoVREDMAX_VS_MF4_E8, VREDMAX_VS }, // 6747
|
|
{ PseudoVREDMAX_VS_MF4_E8_MASK, VREDMAX_VS }, // 6748
|
|
{ PseudoVREDMAX_VS_MF8_E8, VREDMAX_VS }, // 6749
|
|
{ PseudoVREDMAX_VS_MF8_E8_MASK, VREDMAX_VS }, // 6750
|
|
{ PseudoVREDMINU_VS_M1_E16, VREDMINU_VS }, // 6751
|
|
{ PseudoVREDMINU_VS_M1_E16_MASK, VREDMINU_VS }, // 6752
|
|
{ PseudoVREDMINU_VS_M1_E32, VREDMINU_VS }, // 6753
|
|
{ PseudoVREDMINU_VS_M1_E32_MASK, VREDMINU_VS }, // 6754
|
|
{ PseudoVREDMINU_VS_M1_E64, VREDMINU_VS }, // 6755
|
|
{ PseudoVREDMINU_VS_M1_E64_MASK, VREDMINU_VS }, // 6756
|
|
{ PseudoVREDMINU_VS_M1_E8, VREDMINU_VS }, // 6757
|
|
{ PseudoVREDMINU_VS_M1_E8_MASK, VREDMINU_VS }, // 6758
|
|
{ PseudoVREDMINU_VS_M2_E16, VREDMINU_VS }, // 6759
|
|
{ PseudoVREDMINU_VS_M2_E16_MASK, VREDMINU_VS }, // 6760
|
|
{ PseudoVREDMINU_VS_M2_E32, VREDMINU_VS }, // 6761
|
|
{ PseudoVREDMINU_VS_M2_E32_MASK, VREDMINU_VS }, // 6762
|
|
{ PseudoVREDMINU_VS_M2_E64, VREDMINU_VS }, // 6763
|
|
{ PseudoVREDMINU_VS_M2_E64_MASK, VREDMINU_VS }, // 6764
|
|
{ PseudoVREDMINU_VS_M2_E8, VREDMINU_VS }, // 6765
|
|
{ PseudoVREDMINU_VS_M2_E8_MASK, VREDMINU_VS }, // 6766
|
|
{ PseudoVREDMINU_VS_M4_E16, VREDMINU_VS }, // 6767
|
|
{ PseudoVREDMINU_VS_M4_E16_MASK, VREDMINU_VS }, // 6768
|
|
{ PseudoVREDMINU_VS_M4_E32, VREDMINU_VS }, // 6769
|
|
{ PseudoVREDMINU_VS_M4_E32_MASK, VREDMINU_VS }, // 6770
|
|
{ PseudoVREDMINU_VS_M4_E64, VREDMINU_VS }, // 6771
|
|
{ PseudoVREDMINU_VS_M4_E64_MASK, VREDMINU_VS }, // 6772
|
|
{ PseudoVREDMINU_VS_M4_E8, VREDMINU_VS }, // 6773
|
|
{ PseudoVREDMINU_VS_M4_E8_MASK, VREDMINU_VS }, // 6774
|
|
{ PseudoVREDMINU_VS_M8_E16, VREDMINU_VS }, // 6775
|
|
{ PseudoVREDMINU_VS_M8_E16_MASK, VREDMINU_VS }, // 6776
|
|
{ PseudoVREDMINU_VS_M8_E32, VREDMINU_VS }, // 6777
|
|
{ PseudoVREDMINU_VS_M8_E32_MASK, VREDMINU_VS }, // 6778
|
|
{ PseudoVREDMINU_VS_M8_E64, VREDMINU_VS }, // 6779
|
|
{ PseudoVREDMINU_VS_M8_E64_MASK, VREDMINU_VS }, // 6780
|
|
{ PseudoVREDMINU_VS_M8_E8, VREDMINU_VS }, // 6781
|
|
{ PseudoVREDMINU_VS_M8_E8_MASK, VREDMINU_VS }, // 6782
|
|
{ PseudoVREDMINU_VS_MF2_E16, VREDMINU_VS }, // 6783
|
|
{ PseudoVREDMINU_VS_MF2_E16_MASK, VREDMINU_VS }, // 6784
|
|
{ PseudoVREDMINU_VS_MF2_E32, VREDMINU_VS }, // 6785
|
|
{ PseudoVREDMINU_VS_MF2_E32_MASK, VREDMINU_VS }, // 6786
|
|
{ PseudoVREDMINU_VS_MF2_E8, VREDMINU_VS }, // 6787
|
|
{ PseudoVREDMINU_VS_MF2_E8_MASK, VREDMINU_VS }, // 6788
|
|
{ PseudoVREDMINU_VS_MF4_E16, VREDMINU_VS }, // 6789
|
|
{ PseudoVREDMINU_VS_MF4_E16_MASK, VREDMINU_VS }, // 6790
|
|
{ PseudoVREDMINU_VS_MF4_E8, VREDMINU_VS }, // 6791
|
|
{ PseudoVREDMINU_VS_MF4_E8_MASK, VREDMINU_VS }, // 6792
|
|
{ PseudoVREDMINU_VS_MF8_E8, VREDMINU_VS }, // 6793
|
|
{ PseudoVREDMINU_VS_MF8_E8_MASK, VREDMINU_VS }, // 6794
|
|
{ PseudoVREDMIN_VS_M1_E16, VREDMIN_VS }, // 6795
|
|
{ PseudoVREDMIN_VS_M1_E16_MASK, VREDMIN_VS }, // 6796
|
|
{ PseudoVREDMIN_VS_M1_E32, VREDMIN_VS }, // 6797
|
|
{ PseudoVREDMIN_VS_M1_E32_MASK, VREDMIN_VS }, // 6798
|
|
{ PseudoVREDMIN_VS_M1_E64, VREDMIN_VS }, // 6799
|
|
{ PseudoVREDMIN_VS_M1_E64_MASK, VREDMIN_VS }, // 6800
|
|
{ PseudoVREDMIN_VS_M1_E8, VREDMIN_VS }, // 6801
|
|
{ PseudoVREDMIN_VS_M1_E8_MASK, VREDMIN_VS }, // 6802
|
|
{ PseudoVREDMIN_VS_M2_E16, VREDMIN_VS }, // 6803
|
|
{ PseudoVREDMIN_VS_M2_E16_MASK, VREDMIN_VS }, // 6804
|
|
{ PseudoVREDMIN_VS_M2_E32, VREDMIN_VS }, // 6805
|
|
{ PseudoVREDMIN_VS_M2_E32_MASK, VREDMIN_VS }, // 6806
|
|
{ PseudoVREDMIN_VS_M2_E64, VREDMIN_VS }, // 6807
|
|
{ PseudoVREDMIN_VS_M2_E64_MASK, VREDMIN_VS }, // 6808
|
|
{ PseudoVREDMIN_VS_M2_E8, VREDMIN_VS }, // 6809
|
|
{ PseudoVREDMIN_VS_M2_E8_MASK, VREDMIN_VS }, // 6810
|
|
{ PseudoVREDMIN_VS_M4_E16, VREDMIN_VS }, // 6811
|
|
{ PseudoVREDMIN_VS_M4_E16_MASK, VREDMIN_VS }, // 6812
|
|
{ PseudoVREDMIN_VS_M4_E32, VREDMIN_VS }, // 6813
|
|
{ PseudoVREDMIN_VS_M4_E32_MASK, VREDMIN_VS }, // 6814
|
|
{ PseudoVREDMIN_VS_M4_E64, VREDMIN_VS }, // 6815
|
|
{ PseudoVREDMIN_VS_M4_E64_MASK, VREDMIN_VS }, // 6816
|
|
{ PseudoVREDMIN_VS_M4_E8, VREDMIN_VS }, // 6817
|
|
{ PseudoVREDMIN_VS_M4_E8_MASK, VREDMIN_VS }, // 6818
|
|
{ PseudoVREDMIN_VS_M8_E16, VREDMIN_VS }, // 6819
|
|
{ PseudoVREDMIN_VS_M8_E16_MASK, VREDMIN_VS }, // 6820
|
|
{ PseudoVREDMIN_VS_M8_E32, VREDMIN_VS }, // 6821
|
|
{ PseudoVREDMIN_VS_M8_E32_MASK, VREDMIN_VS }, // 6822
|
|
{ PseudoVREDMIN_VS_M8_E64, VREDMIN_VS }, // 6823
|
|
{ PseudoVREDMIN_VS_M8_E64_MASK, VREDMIN_VS }, // 6824
|
|
{ PseudoVREDMIN_VS_M8_E8, VREDMIN_VS }, // 6825
|
|
{ PseudoVREDMIN_VS_M8_E8_MASK, VREDMIN_VS }, // 6826
|
|
{ PseudoVREDMIN_VS_MF2_E16, VREDMIN_VS }, // 6827
|
|
{ PseudoVREDMIN_VS_MF2_E16_MASK, VREDMIN_VS }, // 6828
|
|
{ PseudoVREDMIN_VS_MF2_E32, VREDMIN_VS }, // 6829
|
|
{ PseudoVREDMIN_VS_MF2_E32_MASK, VREDMIN_VS }, // 6830
|
|
{ PseudoVREDMIN_VS_MF2_E8, VREDMIN_VS }, // 6831
|
|
{ PseudoVREDMIN_VS_MF2_E8_MASK, VREDMIN_VS }, // 6832
|
|
{ PseudoVREDMIN_VS_MF4_E16, VREDMIN_VS }, // 6833
|
|
{ PseudoVREDMIN_VS_MF4_E16_MASK, VREDMIN_VS }, // 6834
|
|
{ PseudoVREDMIN_VS_MF4_E8, VREDMIN_VS }, // 6835
|
|
{ PseudoVREDMIN_VS_MF4_E8_MASK, VREDMIN_VS }, // 6836
|
|
{ PseudoVREDMIN_VS_MF8_E8, VREDMIN_VS }, // 6837
|
|
{ PseudoVREDMIN_VS_MF8_E8_MASK, VREDMIN_VS }, // 6838
|
|
{ PseudoVREDOR_VS_M1_E16, VREDOR_VS }, // 6839
|
|
{ PseudoVREDOR_VS_M1_E16_MASK, VREDOR_VS }, // 6840
|
|
{ PseudoVREDOR_VS_M1_E32, VREDOR_VS }, // 6841
|
|
{ PseudoVREDOR_VS_M1_E32_MASK, VREDOR_VS }, // 6842
|
|
{ PseudoVREDOR_VS_M1_E64, VREDOR_VS }, // 6843
|
|
{ PseudoVREDOR_VS_M1_E64_MASK, VREDOR_VS }, // 6844
|
|
{ PseudoVREDOR_VS_M1_E8, VREDOR_VS }, // 6845
|
|
{ PseudoVREDOR_VS_M1_E8_MASK, VREDOR_VS }, // 6846
|
|
{ PseudoVREDOR_VS_M2_E16, VREDOR_VS }, // 6847
|
|
{ PseudoVREDOR_VS_M2_E16_MASK, VREDOR_VS }, // 6848
|
|
{ PseudoVREDOR_VS_M2_E32, VREDOR_VS }, // 6849
|
|
{ PseudoVREDOR_VS_M2_E32_MASK, VREDOR_VS }, // 6850
|
|
{ PseudoVREDOR_VS_M2_E64, VREDOR_VS }, // 6851
|
|
{ PseudoVREDOR_VS_M2_E64_MASK, VREDOR_VS }, // 6852
|
|
{ PseudoVREDOR_VS_M2_E8, VREDOR_VS }, // 6853
|
|
{ PseudoVREDOR_VS_M2_E8_MASK, VREDOR_VS }, // 6854
|
|
{ PseudoVREDOR_VS_M4_E16, VREDOR_VS }, // 6855
|
|
{ PseudoVREDOR_VS_M4_E16_MASK, VREDOR_VS }, // 6856
|
|
{ PseudoVREDOR_VS_M4_E32, VREDOR_VS }, // 6857
|
|
{ PseudoVREDOR_VS_M4_E32_MASK, VREDOR_VS }, // 6858
|
|
{ PseudoVREDOR_VS_M4_E64, VREDOR_VS }, // 6859
|
|
{ PseudoVREDOR_VS_M4_E64_MASK, VREDOR_VS }, // 6860
|
|
{ PseudoVREDOR_VS_M4_E8, VREDOR_VS }, // 6861
|
|
{ PseudoVREDOR_VS_M4_E8_MASK, VREDOR_VS }, // 6862
|
|
{ PseudoVREDOR_VS_M8_E16, VREDOR_VS }, // 6863
|
|
{ PseudoVREDOR_VS_M8_E16_MASK, VREDOR_VS }, // 6864
|
|
{ PseudoVREDOR_VS_M8_E32, VREDOR_VS }, // 6865
|
|
{ PseudoVREDOR_VS_M8_E32_MASK, VREDOR_VS }, // 6866
|
|
{ PseudoVREDOR_VS_M8_E64, VREDOR_VS }, // 6867
|
|
{ PseudoVREDOR_VS_M8_E64_MASK, VREDOR_VS }, // 6868
|
|
{ PseudoVREDOR_VS_M8_E8, VREDOR_VS }, // 6869
|
|
{ PseudoVREDOR_VS_M8_E8_MASK, VREDOR_VS }, // 6870
|
|
{ PseudoVREDOR_VS_MF2_E16, VREDOR_VS }, // 6871
|
|
{ PseudoVREDOR_VS_MF2_E16_MASK, VREDOR_VS }, // 6872
|
|
{ PseudoVREDOR_VS_MF2_E32, VREDOR_VS }, // 6873
|
|
{ PseudoVREDOR_VS_MF2_E32_MASK, VREDOR_VS }, // 6874
|
|
{ PseudoVREDOR_VS_MF2_E8, VREDOR_VS }, // 6875
|
|
{ PseudoVREDOR_VS_MF2_E8_MASK, VREDOR_VS }, // 6876
|
|
{ PseudoVREDOR_VS_MF4_E16, VREDOR_VS }, // 6877
|
|
{ PseudoVREDOR_VS_MF4_E16_MASK, VREDOR_VS }, // 6878
|
|
{ PseudoVREDOR_VS_MF4_E8, VREDOR_VS }, // 6879
|
|
{ PseudoVREDOR_VS_MF4_E8_MASK, VREDOR_VS }, // 6880
|
|
{ PseudoVREDOR_VS_MF8_E8, VREDOR_VS }, // 6881
|
|
{ PseudoVREDOR_VS_MF8_E8_MASK, VREDOR_VS }, // 6882
|
|
{ PseudoVREDSUM_VS_M1_E16, VREDSUM_VS }, // 6883
|
|
{ PseudoVREDSUM_VS_M1_E16_MASK, VREDSUM_VS }, // 6884
|
|
{ PseudoVREDSUM_VS_M1_E32, VREDSUM_VS }, // 6885
|
|
{ PseudoVREDSUM_VS_M1_E32_MASK, VREDSUM_VS }, // 6886
|
|
{ PseudoVREDSUM_VS_M1_E64, VREDSUM_VS }, // 6887
|
|
{ PseudoVREDSUM_VS_M1_E64_MASK, VREDSUM_VS }, // 6888
|
|
{ PseudoVREDSUM_VS_M1_E8, VREDSUM_VS }, // 6889
|
|
{ PseudoVREDSUM_VS_M1_E8_MASK, VREDSUM_VS }, // 6890
|
|
{ PseudoVREDSUM_VS_M2_E16, VREDSUM_VS }, // 6891
|
|
{ PseudoVREDSUM_VS_M2_E16_MASK, VREDSUM_VS }, // 6892
|
|
{ PseudoVREDSUM_VS_M2_E32, VREDSUM_VS }, // 6893
|
|
{ PseudoVREDSUM_VS_M2_E32_MASK, VREDSUM_VS }, // 6894
|
|
{ PseudoVREDSUM_VS_M2_E64, VREDSUM_VS }, // 6895
|
|
{ PseudoVREDSUM_VS_M2_E64_MASK, VREDSUM_VS }, // 6896
|
|
{ PseudoVREDSUM_VS_M2_E8, VREDSUM_VS }, // 6897
|
|
{ PseudoVREDSUM_VS_M2_E8_MASK, VREDSUM_VS }, // 6898
|
|
{ PseudoVREDSUM_VS_M4_E16, VREDSUM_VS }, // 6899
|
|
{ PseudoVREDSUM_VS_M4_E16_MASK, VREDSUM_VS }, // 6900
|
|
{ PseudoVREDSUM_VS_M4_E32, VREDSUM_VS }, // 6901
|
|
{ PseudoVREDSUM_VS_M4_E32_MASK, VREDSUM_VS }, // 6902
|
|
{ PseudoVREDSUM_VS_M4_E64, VREDSUM_VS }, // 6903
|
|
{ PseudoVREDSUM_VS_M4_E64_MASK, VREDSUM_VS }, // 6904
|
|
{ PseudoVREDSUM_VS_M4_E8, VREDSUM_VS }, // 6905
|
|
{ PseudoVREDSUM_VS_M4_E8_MASK, VREDSUM_VS }, // 6906
|
|
{ PseudoVREDSUM_VS_M8_E16, VREDSUM_VS }, // 6907
|
|
{ PseudoVREDSUM_VS_M8_E16_MASK, VREDSUM_VS }, // 6908
|
|
{ PseudoVREDSUM_VS_M8_E32, VREDSUM_VS }, // 6909
|
|
{ PseudoVREDSUM_VS_M8_E32_MASK, VREDSUM_VS }, // 6910
|
|
{ PseudoVREDSUM_VS_M8_E64, VREDSUM_VS }, // 6911
|
|
{ PseudoVREDSUM_VS_M8_E64_MASK, VREDSUM_VS }, // 6912
|
|
{ PseudoVREDSUM_VS_M8_E8, VREDSUM_VS }, // 6913
|
|
{ PseudoVREDSUM_VS_M8_E8_MASK, VREDSUM_VS }, // 6914
|
|
{ PseudoVREDSUM_VS_MF2_E16, VREDSUM_VS }, // 6915
|
|
{ PseudoVREDSUM_VS_MF2_E16_MASK, VREDSUM_VS }, // 6916
|
|
{ PseudoVREDSUM_VS_MF2_E32, VREDSUM_VS }, // 6917
|
|
{ PseudoVREDSUM_VS_MF2_E32_MASK, VREDSUM_VS }, // 6918
|
|
{ PseudoVREDSUM_VS_MF2_E8, VREDSUM_VS }, // 6919
|
|
{ PseudoVREDSUM_VS_MF2_E8_MASK, VREDSUM_VS }, // 6920
|
|
{ PseudoVREDSUM_VS_MF4_E16, VREDSUM_VS }, // 6921
|
|
{ PseudoVREDSUM_VS_MF4_E16_MASK, VREDSUM_VS }, // 6922
|
|
{ PseudoVREDSUM_VS_MF4_E8, VREDSUM_VS }, // 6923
|
|
{ PseudoVREDSUM_VS_MF4_E8_MASK, VREDSUM_VS }, // 6924
|
|
{ PseudoVREDSUM_VS_MF8_E8, VREDSUM_VS }, // 6925
|
|
{ PseudoVREDSUM_VS_MF8_E8_MASK, VREDSUM_VS }, // 6926
|
|
{ PseudoVREDXOR_VS_M1_E16, VREDXOR_VS }, // 6927
|
|
{ PseudoVREDXOR_VS_M1_E16_MASK, VREDXOR_VS }, // 6928
|
|
{ PseudoVREDXOR_VS_M1_E32, VREDXOR_VS }, // 6929
|
|
{ PseudoVREDXOR_VS_M1_E32_MASK, VREDXOR_VS }, // 6930
|
|
{ PseudoVREDXOR_VS_M1_E64, VREDXOR_VS }, // 6931
|
|
{ PseudoVREDXOR_VS_M1_E64_MASK, VREDXOR_VS }, // 6932
|
|
{ PseudoVREDXOR_VS_M1_E8, VREDXOR_VS }, // 6933
|
|
{ PseudoVREDXOR_VS_M1_E8_MASK, VREDXOR_VS }, // 6934
|
|
{ PseudoVREDXOR_VS_M2_E16, VREDXOR_VS }, // 6935
|
|
{ PseudoVREDXOR_VS_M2_E16_MASK, VREDXOR_VS }, // 6936
|
|
{ PseudoVREDXOR_VS_M2_E32, VREDXOR_VS }, // 6937
|
|
{ PseudoVREDXOR_VS_M2_E32_MASK, VREDXOR_VS }, // 6938
|
|
{ PseudoVREDXOR_VS_M2_E64, VREDXOR_VS }, // 6939
|
|
{ PseudoVREDXOR_VS_M2_E64_MASK, VREDXOR_VS }, // 6940
|
|
{ PseudoVREDXOR_VS_M2_E8, VREDXOR_VS }, // 6941
|
|
{ PseudoVREDXOR_VS_M2_E8_MASK, VREDXOR_VS }, // 6942
|
|
{ PseudoVREDXOR_VS_M4_E16, VREDXOR_VS }, // 6943
|
|
{ PseudoVREDXOR_VS_M4_E16_MASK, VREDXOR_VS }, // 6944
|
|
{ PseudoVREDXOR_VS_M4_E32, VREDXOR_VS }, // 6945
|
|
{ PseudoVREDXOR_VS_M4_E32_MASK, VREDXOR_VS }, // 6946
|
|
{ PseudoVREDXOR_VS_M4_E64, VREDXOR_VS }, // 6947
|
|
{ PseudoVREDXOR_VS_M4_E64_MASK, VREDXOR_VS }, // 6948
|
|
{ PseudoVREDXOR_VS_M4_E8, VREDXOR_VS }, // 6949
|
|
{ PseudoVREDXOR_VS_M4_E8_MASK, VREDXOR_VS }, // 6950
|
|
{ PseudoVREDXOR_VS_M8_E16, VREDXOR_VS }, // 6951
|
|
{ PseudoVREDXOR_VS_M8_E16_MASK, VREDXOR_VS }, // 6952
|
|
{ PseudoVREDXOR_VS_M8_E32, VREDXOR_VS }, // 6953
|
|
{ PseudoVREDXOR_VS_M8_E32_MASK, VREDXOR_VS }, // 6954
|
|
{ PseudoVREDXOR_VS_M8_E64, VREDXOR_VS }, // 6955
|
|
{ PseudoVREDXOR_VS_M8_E64_MASK, VREDXOR_VS }, // 6956
|
|
{ PseudoVREDXOR_VS_M8_E8, VREDXOR_VS }, // 6957
|
|
{ PseudoVREDXOR_VS_M8_E8_MASK, VREDXOR_VS }, // 6958
|
|
{ PseudoVREDXOR_VS_MF2_E16, VREDXOR_VS }, // 6959
|
|
{ PseudoVREDXOR_VS_MF2_E16_MASK, VREDXOR_VS }, // 6960
|
|
{ PseudoVREDXOR_VS_MF2_E32, VREDXOR_VS }, // 6961
|
|
{ PseudoVREDXOR_VS_MF2_E32_MASK, VREDXOR_VS }, // 6962
|
|
{ PseudoVREDXOR_VS_MF2_E8, VREDXOR_VS }, // 6963
|
|
{ PseudoVREDXOR_VS_MF2_E8_MASK, VREDXOR_VS }, // 6964
|
|
{ PseudoVREDXOR_VS_MF4_E16, VREDXOR_VS }, // 6965
|
|
{ PseudoVREDXOR_VS_MF4_E16_MASK, VREDXOR_VS }, // 6966
|
|
{ PseudoVREDXOR_VS_MF4_E8, VREDXOR_VS }, // 6967
|
|
{ PseudoVREDXOR_VS_MF4_E8_MASK, VREDXOR_VS }, // 6968
|
|
{ PseudoVREDXOR_VS_MF8_E8, VREDXOR_VS }, // 6969
|
|
{ PseudoVREDXOR_VS_MF8_E8_MASK, VREDXOR_VS }, // 6970
|
|
{ PseudoVREMU_VV_M1_E16, VREMU_VV }, // 6971
|
|
{ PseudoVREMU_VV_M1_E16_MASK, VREMU_VV }, // 6972
|
|
{ PseudoVREMU_VV_M1_E32, VREMU_VV }, // 6973
|
|
{ PseudoVREMU_VV_M1_E32_MASK, VREMU_VV }, // 6974
|
|
{ PseudoVREMU_VV_M1_E64, VREMU_VV }, // 6975
|
|
{ PseudoVREMU_VV_M1_E64_MASK, VREMU_VV }, // 6976
|
|
{ PseudoVREMU_VV_M1_E8, VREMU_VV }, // 6977
|
|
{ PseudoVREMU_VV_M1_E8_MASK, VREMU_VV }, // 6978
|
|
{ PseudoVREMU_VV_M2_E16, VREMU_VV }, // 6979
|
|
{ PseudoVREMU_VV_M2_E16_MASK, VREMU_VV }, // 6980
|
|
{ PseudoVREMU_VV_M2_E32, VREMU_VV }, // 6981
|
|
{ PseudoVREMU_VV_M2_E32_MASK, VREMU_VV }, // 6982
|
|
{ PseudoVREMU_VV_M2_E64, VREMU_VV }, // 6983
|
|
{ PseudoVREMU_VV_M2_E64_MASK, VREMU_VV }, // 6984
|
|
{ PseudoVREMU_VV_M2_E8, VREMU_VV }, // 6985
|
|
{ PseudoVREMU_VV_M2_E8_MASK, VREMU_VV }, // 6986
|
|
{ PseudoVREMU_VV_M4_E16, VREMU_VV }, // 6987
|
|
{ PseudoVREMU_VV_M4_E16_MASK, VREMU_VV }, // 6988
|
|
{ PseudoVREMU_VV_M4_E32, VREMU_VV }, // 6989
|
|
{ PseudoVREMU_VV_M4_E32_MASK, VREMU_VV }, // 6990
|
|
{ PseudoVREMU_VV_M4_E64, VREMU_VV }, // 6991
|
|
{ PseudoVREMU_VV_M4_E64_MASK, VREMU_VV }, // 6992
|
|
{ PseudoVREMU_VV_M4_E8, VREMU_VV }, // 6993
|
|
{ PseudoVREMU_VV_M4_E8_MASK, VREMU_VV }, // 6994
|
|
{ PseudoVREMU_VV_M8_E16, VREMU_VV }, // 6995
|
|
{ PseudoVREMU_VV_M8_E16_MASK, VREMU_VV }, // 6996
|
|
{ PseudoVREMU_VV_M8_E32, VREMU_VV }, // 6997
|
|
{ PseudoVREMU_VV_M8_E32_MASK, VREMU_VV }, // 6998
|
|
{ PseudoVREMU_VV_M8_E64, VREMU_VV }, // 6999
|
|
{ PseudoVREMU_VV_M8_E64_MASK, VREMU_VV }, // 7000
|
|
{ PseudoVREMU_VV_M8_E8, VREMU_VV }, // 7001
|
|
{ PseudoVREMU_VV_M8_E8_MASK, VREMU_VV }, // 7002
|
|
{ PseudoVREMU_VV_MF2_E16, VREMU_VV }, // 7003
|
|
{ PseudoVREMU_VV_MF2_E16_MASK, VREMU_VV }, // 7004
|
|
{ PseudoVREMU_VV_MF2_E32, VREMU_VV }, // 7005
|
|
{ PseudoVREMU_VV_MF2_E32_MASK, VREMU_VV }, // 7006
|
|
{ PseudoVREMU_VV_MF2_E8, VREMU_VV }, // 7007
|
|
{ PseudoVREMU_VV_MF2_E8_MASK, VREMU_VV }, // 7008
|
|
{ PseudoVREMU_VV_MF4_E16, VREMU_VV }, // 7009
|
|
{ PseudoVREMU_VV_MF4_E16_MASK, VREMU_VV }, // 7010
|
|
{ PseudoVREMU_VV_MF4_E8, VREMU_VV }, // 7011
|
|
{ PseudoVREMU_VV_MF4_E8_MASK, VREMU_VV }, // 7012
|
|
{ PseudoVREMU_VV_MF8_E8, VREMU_VV }, // 7013
|
|
{ PseudoVREMU_VV_MF8_E8_MASK, VREMU_VV }, // 7014
|
|
{ PseudoVREMU_VX_M1_E16, VREMU_VX }, // 7015
|
|
{ PseudoVREMU_VX_M1_E16_MASK, VREMU_VX }, // 7016
|
|
{ PseudoVREMU_VX_M1_E32, VREMU_VX }, // 7017
|
|
{ PseudoVREMU_VX_M1_E32_MASK, VREMU_VX }, // 7018
|
|
{ PseudoVREMU_VX_M1_E64, VREMU_VX }, // 7019
|
|
{ PseudoVREMU_VX_M1_E64_MASK, VREMU_VX }, // 7020
|
|
{ PseudoVREMU_VX_M1_E8, VREMU_VX }, // 7021
|
|
{ PseudoVREMU_VX_M1_E8_MASK, VREMU_VX }, // 7022
|
|
{ PseudoVREMU_VX_M2_E16, VREMU_VX }, // 7023
|
|
{ PseudoVREMU_VX_M2_E16_MASK, VREMU_VX }, // 7024
|
|
{ PseudoVREMU_VX_M2_E32, VREMU_VX }, // 7025
|
|
{ PseudoVREMU_VX_M2_E32_MASK, VREMU_VX }, // 7026
|
|
{ PseudoVREMU_VX_M2_E64, VREMU_VX }, // 7027
|
|
{ PseudoVREMU_VX_M2_E64_MASK, VREMU_VX }, // 7028
|
|
{ PseudoVREMU_VX_M2_E8, VREMU_VX }, // 7029
|
|
{ PseudoVREMU_VX_M2_E8_MASK, VREMU_VX }, // 7030
|
|
{ PseudoVREMU_VX_M4_E16, VREMU_VX }, // 7031
|
|
{ PseudoVREMU_VX_M4_E16_MASK, VREMU_VX }, // 7032
|
|
{ PseudoVREMU_VX_M4_E32, VREMU_VX }, // 7033
|
|
{ PseudoVREMU_VX_M4_E32_MASK, VREMU_VX }, // 7034
|
|
{ PseudoVREMU_VX_M4_E64, VREMU_VX }, // 7035
|
|
{ PseudoVREMU_VX_M4_E64_MASK, VREMU_VX }, // 7036
|
|
{ PseudoVREMU_VX_M4_E8, VREMU_VX }, // 7037
|
|
{ PseudoVREMU_VX_M4_E8_MASK, VREMU_VX }, // 7038
|
|
{ PseudoVREMU_VX_M8_E16, VREMU_VX }, // 7039
|
|
{ PseudoVREMU_VX_M8_E16_MASK, VREMU_VX }, // 7040
|
|
{ PseudoVREMU_VX_M8_E32, VREMU_VX }, // 7041
|
|
{ PseudoVREMU_VX_M8_E32_MASK, VREMU_VX }, // 7042
|
|
{ PseudoVREMU_VX_M8_E64, VREMU_VX }, // 7043
|
|
{ PseudoVREMU_VX_M8_E64_MASK, VREMU_VX }, // 7044
|
|
{ PseudoVREMU_VX_M8_E8, VREMU_VX }, // 7045
|
|
{ PseudoVREMU_VX_M8_E8_MASK, VREMU_VX }, // 7046
|
|
{ PseudoVREMU_VX_MF2_E16, VREMU_VX }, // 7047
|
|
{ PseudoVREMU_VX_MF2_E16_MASK, VREMU_VX }, // 7048
|
|
{ PseudoVREMU_VX_MF2_E32, VREMU_VX }, // 7049
|
|
{ PseudoVREMU_VX_MF2_E32_MASK, VREMU_VX }, // 7050
|
|
{ PseudoVREMU_VX_MF2_E8, VREMU_VX }, // 7051
|
|
{ PseudoVREMU_VX_MF2_E8_MASK, VREMU_VX }, // 7052
|
|
{ PseudoVREMU_VX_MF4_E16, VREMU_VX }, // 7053
|
|
{ PseudoVREMU_VX_MF4_E16_MASK, VREMU_VX }, // 7054
|
|
{ PseudoVREMU_VX_MF4_E8, VREMU_VX }, // 7055
|
|
{ PseudoVREMU_VX_MF4_E8_MASK, VREMU_VX }, // 7056
|
|
{ PseudoVREMU_VX_MF8_E8, VREMU_VX }, // 7057
|
|
{ PseudoVREMU_VX_MF8_E8_MASK, VREMU_VX }, // 7058
|
|
{ PseudoVREM_VV_M1_E16, VREM_VV }, // 7059
|
|
{ PseudoVREM_VV_M1_E16_MASK, VREM_VV }, // 7060
|
|
{ PseudoVREM_VV_M1_E32, VREM_VV }, // 7061
|
|
{ PseudoVREM_VV_M1_E32_MASK, VREM_VV }, // 7062
|
|
{ PseudoVREM_VV_M1_E64, VREM_VV }, // 7063
|
|
{ PseudoVREM_VV_M1_E64_MASK, VREM_VV }, // 7064
|
|
{ PseudoVREM_VV_M1_E8, VREM_VV }, // 7065
|
|
{ PseudoVREM_VV_M1_E8_MASK, VREM_VV }, // 7066
|
|
{ PseudoVREM_VV_M2_E16, VREM_VV }, // 7067
|
|
{ PseudoVREM_VV_M2_E16_MASK, VREM_VV }, // 7068
|
|
{ PseudoVREM_VV_M2_E32, VREM_VV }, // 7069
|
|
{ PseudoVREM_VV_M2_E32_MASK, VREM_VV }, // 7070
|
|
{ PseudoVREM_VV_M2_E64, VREM_VV }, // 7071
|
|
{ PseudoVREM_VV_M2_E64_MASK, VREM_VV }, // 7072
|
|
{ PseudoVREM_VV_M2_E8, VREM_VV }, // 7073
|
|
{ PseudoVREM_VV_M2_E8_MASK, VREM_VV }, // 7074
|
|
{ PseudoVREM_VV_M4_E16, VREM_VV }, // 7075
|
|
{ PseudoVREM_VV_M4_E16_MASK, VREM_VV }, // 7076
|
|
{ PseudoVREM_VV_M4_E32, VREM_VV }, // 7077
|
|
{ PseudoVREM_VV_M4_E32_MASK, VREM_VV }, // 7078
|
|
{ PseudoVREM_VV_M4_E64, VREM_VV }, // 7079
|
|
{ PseudoVREM_VV_M4_E64_MASK, VREM_VV }, // 7080
|
|
{ PseudoVREM_VV_M4_E8, VREM_VV }, // 7081
|
|
{ PseudoVREM_VV_M4_E8_MASK, VREM_VV }, // 7082
|
|
{ PseudoVREM_VV_M8_E16, VREM_VV }, // 7083
|
|
{ PseudoVREM_VV_M8_E16_MASK, VREM_VV }, // 7084
|
|
{ PseudoVREM_VV_M8_E32, VREM_VV }, // 7085
|
|
{ PseudoVREM_VV_M8_E32_MASK, VREM_VV }, // 7086
|
|
{ PseudoVREM_VV_M8_E64, VREM_VV }, // 7087
|
|
{ PseudoVREM_VV_M8_E64_MASK, VREM_VV }, // 7088
|
|
{ PseudoVREM_VV_M8_E8, VREM_VV }, // 7089
|
|
{ PseudoVREM_VV_M8_E8_MASK, VREM_VV }, // 7090
|
|
{ PseudoVREM_VV_MF2_E16, VREM_VV }, // 7091
|
|
{ PseudoVREM_VV_MF2_E16_MASK, VREM_VV }, // 7092
|
|
{ PseudoVREM_VV_MF2_E32, VREM_VV }, // 7093
|
|
{ PseudoVREM_VV_MF2_E32_MASK, VREM_VV }, // 7094
|
|
{ PseudoVREM_VV_MF2_E8, VREM_VV }, // 7095
|
|
{ PseudoVREM_VV_MF2_E8_MASK, VREM_VV }, // 7096
|
|
{ PseudoVREM_VV_MF4_E16, VREM_VV }, // 7097
|
|
{ PseudoVREM_VV_MF4_E16_MASK, VREM_VV }, // 7098
|
|
{ PseudoVREM_VV_MF4_E8, VREM_VV }, // 7099
|
|
{ PseudoVREM_VV_MF4_E8_MASK, VREM_VV }, // 7100
|
|
{ PseudoVREM_VV_MF8_E8, VREM_VV }, // 7101
|
|
{ PseudoVREM_VV_MF8_E8_MASK, VREM_VV }, // 7102
|
|
{ PseudoVREM_VX_M1_E16, VREM_VX }, // 7103
|
|
{ PseudoVREM_VX_M1_E16_MASK, VREM_VX }, // 7104
|
|
{ PseudoVREM_VX_M1_E32, VREM_VX }, // 7105
|
|
{ PseudoVREM_VX_M1_E32_MASK, VREM_VX }, // 7106
|
|
{ PseudoVREM_VX_M1_E64, VREM_VX }, // 7107
|
|
{ PseudoVREM_VX_M1_E64_MASK, VREM_VX }, // 7108
|
|
{ PseudoVREM_VX_M1_E8, VREM_VX }, // 7109
|
|
{ PseudoVREM_VX_M1_E8_MASK, VREM_VX }, // 7110
|
|
{ PseudoVREM_VX_M2_E16, VREM_VX }, // 7111
|
|
{ PseudoVREM_VX_M2_E16_MASK, VREM_VX }, // 7112
|
|
{ PseudoVREM_VX_M2_E32, VREM_VX }, // 7113
|
|
{ PseudoVREM_VX_M2_E32_MASK, VREM_VX }, // 7114
|
|
{ PseudoVREM_VX_M2_E64, VREM_VX }, // 7115
|
|
{ PseudoVREM_VX_M2_E64_MASK, VREM_VX }, // 7116
|
|
{ PseudoVREM_VX_M2_E8, VREM_VX }, // 7117
|
|
{ PseudoVREM_VX_M2_E8_MASK, VREM_VX }, // 7118
|
|
{ PseudoVREM_VX_M4_E16, VREM_VX }, // 7119
|
|
{ PseudoVREM_VX_M4_E16_MASK, VREM_VX }, // 7120
|
|
{ PseudoVREM_VX_M4_E32, VREM_VX }, // 7121
|
|
{ PseudoVREM_VX_M4_E32_MASK, VREM_VX }, // 7122
|
|
{ PseudoVREM_VX_M4_E64, VREM_VX }, // 7123
|
|
{ PseudoVREM_VX_M4_E64_MASK, VREM_VX }, // 7124
|
|
{ PseudoVREM_VX_M4_E8, VREM_VX }, // 7125
|
|
{ PseudoVREM_VX_M4_E8_MASK, VREM_VX }, // 7126
|
|
{ PseudoVREM_VX_M8_E16, VREM_VX }, // 7127
|
|
{ PseudoVREM_VX_M8_E16_MASK, VREM_VX }, // 7128
|
|
{ PseudoVREM_VX_M8_E32, VREM_VX }, // 7129
|
|
{ PseudoVREM_VX_M8_E32_MASK, VREM_VX }, // 7130
|
|
{ PseudoVREM_VX_M8_E64, VREM_VX }, // 7131
|
|
{ PseudoVREM_VX_M8_E64_MASK, VREM_VX }, // 7132
|
|
{ PseudoVREM_VX_M8_E8, VREM_VX }, // 7133
|
|
{ PseudoVREM_VX_M8_E8_MASK, VREM_VX }, // 7134
|
|
{ PseudoVREM_VX_MF2_E16, VREM_VX }, // 7135
|
|
{ PseudoVREM_VX_MF2_E16_MASK, VREM_VX }, // 7136
|
|
{ PseudoVREM_VX_MF2_E32, VREM_VX }, // 7137
|
|
{ PseudoVREM_VX_MF2_E32_MASK, VREM_VX }, // 7138
|
|
{ PseudoVREM_VX_MF2_E8, VREM_VX }, // 7139
|
|
{ PseudoVREM_VX_MF2_E8_MASK, VREM_VX }, // 7140
|
|
{ PseudoVREM_VX_MF4_E16, VREM_VX }, // 7141
|
|
{ PseudoVREM_VX_MF4_E16_MASK, VREM_VX }, // 7142
|
|
{ PseudoVREM_VX_MF4_E8, VREM_VX }, // 7143
|
|
{ PseudoVREM_VX_MF4_E8_MASK, VREM_VX }, // 7144
|
|
{ PseudoVREM_VX_MF8_E8, VREM_VX }, // 7145
|
|
{ PseudoVREM_VX_MF8_E8_MASK, VREM_VX }, // 7146
|
|
{ PseudoVREV8_V_M1, VREV8_V }, // 7147
|
|
{ PseudoVREV8_V_M1_MASK, VREV8_V }, // 7148
|
|
{ PseudoVREV8_V_M2, VREV8_V }, // 7149
|
|
{ PseudoVREV8_V_M2_MASK, VREV8_V }, // 7150
|
|
{ PseudoVREV8_V_M4, VREV8_V }, // 7151
|
|
{ PseudoVREV8_V_M4_MASK, VREV8_V }, // 7152
|
|
{ PseudoVREV8_V_M8, VREV8_V }, // 7153
|
|
{ PseudoVREV8_V_M8_MASK, VREV8_V }, // 7154
|
|
{ PseudoVREV8_V_MF2, VREV8_V }, // 7155
|
|
{ PseudoVREV8_V_MF2_MASK, VREV8_V }, // 7156
|
|
{ PseudoVREV8_V_MF4, VREV8_V }, // 7157
|
|
{ PseudoVREV8_V_MF4_MASK, VREV8_V }, // 7158
|
|
{ PseudoVREV8_V_MF8, VREV8_V }, // 7159
|
|
{ PseudoVREV8_V_MF8_MASK, VREV8_V }, // 7160
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M1, VRGATHEREI16_VV }, // 7161
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, VRGATHEREI16_VV }, // 7162
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M2, VRGATHEREI16_VV }, // 7163
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, VRGATHEREI16_VV }, // 7164
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF2, VRGATHEREI16_VV }, // 7165
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, VRGATHEREI16_VV }, // 7166
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF4, VRGATHEREI16_VV }, // 7167
|
|
{ PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, VRGATHEREI16_VV }, // 7168
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M1, VRGATHEREI16_VV }, // 7169
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, VRGATHEREI16_VV }, // 7170
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M2, VRGATHEREI16_VV }, // 7171
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, VRGATHEREI16_VV }, // 7172
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF2, VRGATHEREI16_VV }, // 7173
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, VRGATHEREI16_VV }, // 7174
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF4, VRGATHEREI16_VV }, // 7175
|
|
{ PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, VRGATHEREI16_VV }, // 7176
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M1, VRGATHEREI16_VV }, // 7177
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, VRGATHEREI16_VV }, // 7178
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M2, VRGATHEREI16_VV }, // 7179
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, VRGATHEREI16_VV }, // 7180
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF2, VRGATHEREI16_VV }, // 7181
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, VRGATHEREI16_VV }, // 7182
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF4, VRGATHEREI16_VV }, // 7183
|
|
{ PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, VRGATHEREI16_VV }, // 7184
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M1, VRGATHEREI16_VV }, // 7185
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, VRGATHEREI16_VV }, // 7186
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M2, VRGATHEREI16_VV }, // 7187
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, VRGATHEREI16_VV }, // 7188
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF2, VRGATHEREI16_VV }, // 7189
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, VRGATHEREI16_VV }, // 7190
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF4, VRGATHEREI16_VV }, // 7191
|
|
{ PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, VRGATHEREI16_VV }, // 7192
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M1, VRGATHEREI16_VV }, // 7193
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, VRGATHEREI16_VV }, // 7194
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M2, VRGATHEREI16_VV }, // 7195
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, VRGATHEREI16_VV }, // 7196
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M4, VRGATHEREI16_VV }, // 7197
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, VRGATHEREI16_VV }, // 7198
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_MF2, VRGATHEREI16_VV }, // 7199
|
|
{ PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, VRGATHEREI16_VV }, // 7200
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M1, VRGATHEREI16_VV }, // 7201
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, VRGATHEREI16_VV }, // 7202
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M2, VRGATHEREI16_VV }, // 7203
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, VRGATHEREI16_VV }, // 7204
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M4, VRGATHEREI16_VV }, // 7205
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, VRGATHEREI16_VV }, // 7206
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_MF2, VRGATHEREI16_VV }, // 7207
|
|
{ PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, VRGATHEREI16_VV }, // 7208
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M1, VRGATHEREI16_VV }, // 7209
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, VRGATHEREI16_VV }, // 7210
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M2, VRGATHEREI16_VV }, // 7211
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, VRGATHEREI16_VV }, // 7212
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M4, VRGATHEREI16_VV }, // 7213
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, VRGATHEREI16_VV }, // 7214
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_MF2, VRGATHEREI16_VV }, // 7215
|
|
{ PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, VRGATHEREI16_VV }, // 7216
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M1, VRGATHEREI16_VV }, // 7217
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, VRGATHEREI16_VV }, // 7218
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M2, VRGATHEREI16_VV }, // 7219
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, VRGATHEREI16_VV }, // 7220
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M4, VRGATHEREI16_VV }, // 7221
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, VRGATHEREI16_VV }, // 7222
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_MF2, VRGATHEREI16_VV }, // 7223
|
|
{ PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, VRGATHEREI16_VV }, // 7224
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M1, VRGATHEREI16_VV }, // 7225
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, VRGATHEREI16_VV }, // 7226
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M2, VRGATHEREI16_VV }, // 7227
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, VRGATHEREI16_VV }, // 7228
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M4, VRGATHEREI16_VV }, // 7229
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, VRGATHEREI16_VV }, // 7230
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M8, VRGATHEREI16_VV }, // 7231
|
|
{ PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, VRGATHEREI16_VV }, // 7232
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M1, VRGATHEREI16_VV }, // 7233
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, VRGATHEREI16_VV }, // 7234
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M2, VRGATHEREI16_VV }, // 7235
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, VRGATHEREI16_VV }, // 7236
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M4, VRGATHEREI16_VV }, // 7237
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, VRGATHEREI16_VV }, // 7238
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M8, VRGATHEREI16_VV }, // 7239
|
|
{ PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, VRGATHEREI16_VV }, // 7240
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M1, VRGATHEREI16_VV }, // 7241
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, VRGATHEREI16_VV }, // 7242
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M2, VRGATHEREI16_VV }, // 7243
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, VRGATHEREI16_VV }, // 7244
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M4, VRGATHEREI16_VV }, // 7245
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, VRGATHEREI16_VV }, // 7246
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M8, VRGATHEREI16_VV }, // 7247
|
|
{ PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, VRGATHEREI16_VV }, // 7248
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M1, VRGATHEREI16_VV }, // 7249
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, VRGATHEREI16_VV }, // 7250
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M2, VRGATHEREI16_VV }, // 7251
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, VRGATHEREI16_VV }, // 7252
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M4, VRGATHEREI16_VV }, // 7253
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, VRGATHEREI16_VV }, // 7254
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M8, VRGATHEREI16_VV }, // 7255
|
|
{ PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, VRGATHEREI16_VV }, // 7256
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M2, VRGATHEREI16_VV }, // 7257
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, VRGATHEREI16_VV }, // 7258
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M4, VRGATHEREI16_VV }, // 7259
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, VRGATHEREI16_VV }, // 7260
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M8, VRGATHEREI16_VV }, // 7261
|
|
{ PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, VRGATHEREI16_VV }, // 7262
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M2, VRGATHEREI16_VV }, // 7263
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, VRGATHEREI16_VV }, // 7264
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M4, VRGATHEREI16_VV }, // 7265
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, VRGATHEREI16_VV }, // 7266
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M8, VRGATHEREI16_VV }, // 7267
|
|
{ PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, VRGATHEREI16_VV }, // 7268
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M2, VRGATHEREI16_VV }, // 7269
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, VRGATHEREI16_VV }, // 7270
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M4, VRGATHEREI16_VV }, // 7271
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, VRGATHEREI16_VV }, // 7272
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M8, VRGATHEREI16_VV }, // 7273
|
|
{ PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, VRGATHEREI16_VV }, // 7274
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M2, VRGATHEREI16_VV }, // 7275
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, VRGATHEREI16_VV }, // 7276
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M4, VRGATHEREI16_VV }, // 7277
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, VRGATHEREI16_VV }, // 7278
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M8, VRGATHEREI16_VV }, // 7279
|
|
{ PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, VRGATHEREI16_VV }, // 7280
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_M1, VRGATHEREI16_VV }, // 7281
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, VRGATHEREI16_VV }, // 7282
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF2, VRGATHEREI16_VV }, // 7283
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, VRGATHEREI16_VV }, // 7284
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF4, VRGATHEREI16_VV }, // 7285
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, VRGATHEREI16_VV }, // 7286
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF8, VRGATHEREI16_VV }, // 7287
|
|
{ PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, VRGATHEREI16_VV }, // 7288
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_M1, VRGATHEREI16_VV }, // 7289
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, VRGATHEREI16_VV }, // 7290
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF2, VRGATHEREI16_VV }, // 7291
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, VRGATHEREI16_VV }, // 7292
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF4, VRGATHEREI16_VV }, // 7293
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, VRGATHEREI16_VV }, // 7294
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF8, VRGATHEREI16_VV }, // 7295
|
|
{ PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, VRGATHEREI16_VV }, // 7296
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_M1, VRGATHEREI16_VV }, // 7297
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, VRGATHEREI16_VV }, // 7298
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF2, VRGATHEREI16_VV }, // 7299
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, VRGATHEREI16_VV }, // 7300
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF4, VRGATHEREI16_VV }, // 7301
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, VRGATHEREI16_VV }, // 7302
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF8, VRGATHEREI16_VV }, // 7303
|
|
{ PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, VRGATHEREI16_VV }, // 7304
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF2, VRGATHEREI16_VV }, // 7305
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, VRGATHEREI16_VV }, // 7306
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF4, VRGATHEREI16_VV }, // 7307
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, VRGATHEREI16_VV }, // 7308
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF8, VRGATHEREI16_VV }, // 7309
|
|
{ PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, VRGATHEREI16_VV }, // 7310
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF2, VRGATHEREI16_VV }, // 7311
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, VRGATHEREI16_VV }, // 7312
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF4, VRGATHEREI16_VV }, // 7313
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, VRGATHEREI16_VV }, // 7314
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF8, VRGATHEREI16_VV }, // 7315
|
|
{ PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, VRGATHEREI16_VV }, // 7316
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF4, VRGATHEREI16_VV }, // 7317
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, VRGATHEREI16_VV }, // 7318
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF8, VRGATHEREI16_VV }, // 7319
|
|
{ PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, VRGATHEREI16_VV }, // 7320
|
|
{ PseudoVRGATHER_VI_M1, VRGATHER_VI }, // 7321
|
|
{ PseudoVRGATHER_VI_M1_MASK, VRGATHER_VI }, // 7322
|
|
{ PseudoVRGATHER_VI_M2, VRGATHER_VI }, // 7323
|
|
{ PseudoVRGATHER_VI_M2_MASK, VRGATHER_VI }, // 7324
|
|
{ PseudoVRGATHER_VI_M4, VRGATHER_VI }, // 7325
|
|
{ PseudoVRGATHER_VI_M4_MASK, VRGATHER_VI }, // 7326
|
|
{ PseudoVRGATHER_VI_M8, VRGATHER_VI }, // 7327
|
|
{ PseudoVRGATHER_VI_M8_MASK, VRGATHER_VI }, // 7328
|
|
{ PseudoVRGATHER_VI_MF2, VRGATHER_VI }, // 7329
|
|
{ PseudoVRGATHER_VI_MF2_MASK, VRGATHER_VI }, // 7330
|
|
{ PseudoVRGATHER_VI_MF4, VRGATHER_VI }, // 7331
|
|
{ PseudoVRGATHER_VI_MF4_MASK, VRGATHER_VI }, // 7332
|
|
{ PseudoVRGATHER_VI_MF8, VRGATHER_VI }, // 7333
|
|
{ PseudoVRGATHER_VI_MF8_MASK, VRGATHER_VI }, // 7334
|
|
{ PseudoVRGATHER_VV_M1_E16, VRGATHER_VV }, // 7335
|
|
{ PseudoVRGATHER_VV_M1_E16_MASK, VRGATHER_VV }, // 7336
|
|
{ PseudoVRGATHER_VV_M1_E32, VRGATHER_VV }, // 7337
|
|
{ PseudoVRGATHER_VV_M1_E32_MASK, VRGATHER_VV }, // 7338
|
|
{ PseudoVRGATHER_VV_M1_E64, VRGATHER_VV }, // 7339
|
|
{ PseudoVRGATHER_VV_M1_E64_MASK, VRGATHER_VV }, // 7340
|
|
{ PseudoVRGATHER_VV_M1_E8, VRGATHER_VV }, // 7341
|
|
{ PseudoVRGATHER_VV_M1_E8_MASK, VRGATHER_VV }, // 7342
|
|
{ PseudoVRGATHER_VV_M2_E16, VRGATHER_VV }, // 7343
|
|
{ PseudoVRGATHER_VV_M2_E16_MASK, VRGATHER_VV }, // 7344
|
|
{ PseudoVRGATHER_VV_M2_E32, VRGATHER_VV }, // 7345
|
|
{ PseudoVRGATHER_VV_M2_E32_MASK, VRGATHER_VV }, // 7346
|
|
{ PseudoVRGATHER_VV_M2_E64, VRGATHER_VV }, // 7347
|
|
{ PseudoVRGATHER_VV_M2_E64_MASK, VRGATHER_VV }, // 7348
|
|
{ PseudoVRGATHER_VV_M2_E8, VRGATHER_VV }, // 7349
|
|
{ PseudoVRGATHER_VV_M2_E8_MASK, VRGATHER_VV }, // 7350
|
|
{ PseudoVRGATHER_VV_M4_E16, VRGATHER_VV }, // 7351
|
|
{ PseudoVRGATHER_VV_M4_E16_MASK, VRGATHER_VV }, // 7352
|
|
{ PseudoVRGATHER_VV_M4_E32, VRGATHER_VV }, // 7353
|
|
{ PseudoVRGATHER_VV_M4_E32_MASK, VRGATHER_VV }, // 7354
|
|
{ PseudoVRGATHER_VV_M4_E64, VRGATHER_VV }, // 7355
|
|
{ PseudoVRGATHER_VV_M4_E64_MASK, VRGATHER_VV }, // 7356
|
|
{ PseudoVRGATHER_VV_M4_E8, VRGATHER_VV }, // 7357
|
|
{ PseudoVRGATHER_VV_M4_E8_MASK, VRGATHER_VV }, // 7358
|
|
{ PseudoVRGATHER_VV_M8_E16, VRGATHER_VV }, // 7359
|
|
{ PseudoVRGATHER_VV_M8_E16_MASK, VRGATHER_VV }, // 7360
|
|
{ PseudoVRGATHER_VV_M8_E32, VRGATHER_VV }, // 7361
|
|
{ PseudoVRGATHER_VV_M8_E32_MASK, VRGATHER_VV }, // 7362
|
|
{ PseudoVRGATHER_VV_M8_E64, VRGATHER_VV }, // 7363
|
|
{ PseudoVRGATHER_VV_M8_E64_MASK, VRGATHER_VV }, // 7364
|
|
{ PseudoVRGATHER_VV_M8_E8, VRGATHER_VV }, // 7365
|
|
{ PseudoVRGATHER_VV_M8_E8_MASK, VRGATHER_VV }, // 7366
|
|
{ PseudoVRGATHER_VV_MF2_E16, VRGATHER_VV }, // 7367
|
|
{ PseudoVRGATHER_VV_MF2_E16_MASK, VRGATHER_VV }, // 7368
|
|
{ PseudoVRGATHER_VV_MF2_E32, VRGATHER_VV }, // 7369
|
|
{ PseudoVRGATHER_VV_MF2_E32_MASK, VRGATHER_VV }, // 7370
|
|
{ PseudoVRGATHER_VV_MF2_E8, VRGATHER_VV }, // 7371
|
|
{ PseudoVRGATHER_VV_MF2_E8_MASK, VRGATHER_VV }, // 7372
|
|
{ PseudoVRGATHER_VV_MF4_E16, VRGATHER_VV }, // 7373
|
|
{ PseudoVRGATHER_VV_MF4_E16_MASK, VRGATHER_VV }, // 7374
|
|
{ PseudoVRGATHER_VV_MF4_E8, VRGATHER_VV }, // 7375
|
|
{ PseudoVRGATHER_VV_MF4_E8_MASK, VRGATHER_VV }, // 7376
|
|
{ PseudoVRGATHER_VV_MF8_E8, VRGATHER_VV }, // 7377
|
|
{ PseudoVRGATHER_VV_MF8_E8_MASK, VRGATHER_VV }, // 7378
|
|
{ PseudoVRGATHER_VX_M1, VRGATHER_VX }, // 7379
|
|
{ PseudoVRGATHER_VX_M1_MASK, VRGATHER_VX }, // 7380
|
|
{ PseudoVRGATHER_VX_M2, VRGATHER_VX }, // 7381
|
|
{ PseudoVRGATHER_VX_M2_MASK, VRGATHER_VX }, // 7382
|
|
{ PseudoVRGATHER_VX_M4, VRGATHER_VX }, // 7383
|
|
{ PseudoVRGATHER_VX_M4_MASK, VRGATHER_VX }, // 7384
|
|
{ PseudoVRGATHER_VX_M8, VRGATHER_VX }, // 7385
|
|
{ PseudoVRGATHER_VX_M8_MASK, VRGATHER_VX }, // 7386
|
|
{ PseudoVRGATHER_VX_MF2, VRGATHER_VX }, // 7387
|
|
{ PseudoVRGATHER_VX_MF2_MASK, VRGATHER_VX }, // 7388
|
|
{ PseudoVRGATHER_VX_MF4, VRGATHER_VX }, // 7389
|
|
{ PseudoVRGATHER_VX_MF4_MASK, VRGATHER_VX }, // 7390
|
|
{ PseudoVRGATHER_VX_MF8, VRGATHER_VX }, // 7391
|
|
{ PseudoVRGATHER_VX_MF8_MASK, VRGATHER_VX }, // 7392
|
|
{ PseudoVROL_VV_M1, VROL_VV }, // 7393
|
|
{ PseudoVROL_VV_M1_MASK, VROL_VV }, // 7394
|
|
{ PseudoVROL_VV_M2, VROL_VV }, // 7395
|
|
{ PseudoVROL_VV_M2_MASK, VROL_VV }, // 7396
|
|
{ PseudoVROL_VV_M4, VROL_VV }, // 7397
|
|
{ PseudoVROL_VV_M4_MASK, VROL_VV }, // 7398
|
|
{ PseudoVROL_VV_M8, VROL_VV }, // 7399
|
|
{ PseudoVROL_VV_M8_MASK, VROL_VV }, // 7400
|
|
{ PseudoVROL_VV_MF2, VROL_VV }, // 7401
|
|
{ PseudoVROL_VV_MF2_MASK, VROL_VV }, // 7402
|
|
{ PseudoVROL_VV_MF4, VROL_VV }, // 7403
|
|
{ PseudoVROL_VV_MF4_MASK, VROL_VV }, // 7404
|
|
{ PseudoVROL_VV_MF8, VROL_VV }, // 7405
|
|
{ PseudoVROL_VV_MF8_MASK, VROL_VV }, // 7406
|
|
{ PseudoVROL_VX_M1, VROL_VX }, // 7407
|
|
{ PseudoVROL_VX_M1_MASK, VROL_VX }, // 7408
|
|
{ PseudoVROL_VX_M2, VROL_VX }, // 7409
|
|
{ PseudoVROL_VX_M2_MASK, VROL_VX }, // 7410
|
|
{ PseudoVROL_VX_M4, VROL_VX }, // 7411
|
|
{ PseudoVROL_VX_M4_MASK, VROL_VX }, // 7412
|
|
{ PseudoVROL_VX_M8, VROL_VX }, // 7413
|
|
{ PseudoVROL_VX_M8_MASK, VROL_VX }, // 7414
|
|
{ PseudoVROL_VX_MF2, VROL_VX }, // 7415
|
|
{ PseudoVROL_VX_MF2_MASK, VROL_VX }, // 7416
|
|
{ PseudoVROL_VX_MF4, VROL_VX }, // 7417
|
|
{ PseudoVROL_VX_MF4_MASK, VROL_VX }, // 7418
|
|
{ PseudoVROL_VX_MF8, VROL_VX }, // 7419
|
|
{ PseudoVROL_VX_MF8_MASK, VROL_VX }, // 7420
|
|
{ PseudoVROR_VI_M1, VROR_VI }, // 7421
|
|
{ PseudoVROR_VI_M1_MASK, VROR_VI }, // 7422
|
|
{ PseudoVROR_VI_M2, VROR_VI }, // 7423
|
|
{ PseudoVROR_VI_M2_MASK, VROR_VI }, // 7424
|
|
{ PseudoVROR_VI_M4, VROR_VI }, // 7425
|
|
{ PseudoVROR_VI_M4_MASK, VROR_VI }, // 7426
|
|
{ PseudoVROR_VI_M8, VROR_VI }, // 7427
|
|
{ PseudoVROR_VI_M8_MASK, VROR_VI }, // 7428
|
|
{ PseudoVROR_VI_MF2, VROR_VI }, // 7429
|
|
{ PseudoVROR_VI_MF2_MASK, VROR_VI }, // 7430
|
|
{ PseudoVROR_VI_MF4, VROR_VI }, // 7431
|
|
{ PseudoVROR_VI_MF4_MASK, VROR_VI }, // 7432
|
|
{ PseudoVROR_VI_MF8, VROR_VI }, // 7433
|
|
{ PseudoVROR_VI_MF8_MASK, VROR_VI }, // 7434
|
|
{ PseudoVROR_VV_M1, VROR_VV }, // 7435
|
|
{ PseudoVROR_VV_M1_MASK, VROR_VV }, // 7436
|
|
{ PseudoVROR_VV_M2, VROR_VV }, // 7437
|
|
{ PseudoVROR_VV_M2_MASK, VROR_VV }, // 7438
|
|
{ PseudoVROR_VV_M4, VROR_VV }, // 7439
|
|
{ PseudoVROR_VV_M4_MASK, VROR_VV }, // 7440
|
|
{ PseudoVROR_VV_M8, VROR_VV }, // 7441
|
|
{ PseudoVROR_VV_M8_MASK, VROR_VV }, // 7442
|
|
{ PseudoVROR_VV_MF2, VROR_VV }, // 7443
|
|
{ PseudoVROR_VV_MF2_MASK, VROR_VV }, // 7444
|
|
{ PseudoVROR_VV_MF4, VROR_VV }, // 7445
|
|
{ PseudoVROR_VV_MF4_MASK, VROR_VV }, // 7446
|
|
{ PseudoVROR_VV_MF8, VROR_VV }, // 7447
|
|
{ PseudoVROR_VV_MF8_MASK, VROR_VV }, // 7448
|
|
{ PseudoVROR_VX_M1, VROR_VX }, // 7449
|
|
{ PseudoVROR_VX_M1_MASK, VROR_VX }, // 7450
|
|
{ PseudoVROR_VX_M2, VROR_VX }, // 7451
|
|
{ PseudoVROR_VX_M2_MASK, VROR_VX }, // 7452
|
|
{ PseudoVROR_VX_M4, VROR_VX }, // 7453
|
|
{ PseudoVROR_VX_M4_MASK, VROR_VX }, // 7454
|
|
{ PseudoVROR_VX_M8, VROR_VX }, // 7455
|
|
{ PseudoVROR_VX_M8_MASK, VROR_VX }, // 7456
|
|
{ PseudoVROR_VX_MF2, VROR_VX }, // 7457
|
|
{ PseudoVROR_VX_MF2_MASK, VROR_VX }, // 7458
|
|
{ PseudoVROR_VX_MF4, VROR_VX }, // 7459
|
|
{ PseudoVROR_VX_MF4_MASK, VROR_VX }, // 7460
|
|
{ PseudoVROR_VX_MF8, VROR_VX }, // 7461
|
|
{ PseudoVROR_VX_MF8_MASK, VROR_VX }, // 7462
|
|
{ PseudoVRSUB_VI_M1, VRSUB_VI }, // 7463
|
|
{ PseudoVRSUB_VI_M1_MASK, VRSUB_VI }, // 7464
|
|
{ PseudoVRSUB_VI_M2, VRSUB_VI }, // 7465
|
|
{ PseudoVRSUB_VI_M2_MASK, VRSUB_VI }, // 7466
|
|
{ PseudoVRSUB_VI_M4, VRSUB_VI }, // 7467
|
|
{ PseudoVRSUB_VI_M4_MASK, VRSUB_VI }, // 7468
|
|
{ PseudoVRSUB_VI_M8, VRSUB_VI }, // 7469
|
|
{ PseudoVRSUB_VI_M8_MASK, VRSUB_VI }, // 7470
|
|
{ PseudoVRSUB_VI_MF2, VRSUB_VI }, // 7471
|
|
{ PseudoVRSUB_VI_MF2_MASK, VRSUB_VI }, // 7472
|
|
{ PseudoVRSUB_VI_MF4, VRSUB_VI }, // 7473
|
|
{ PseudoVRSUB_VI_MF4_MASK, VRSUB_VI }, // 7474
|
|
{ PseudoVRSUB_VI_MF8, VRSUB_VI }, // 7475
|
|
{ PseudoVRSUB_VI_MF8_MASK, VRSUB_VI }, // 7476
|
|
{ PseudoVRSUB_VX_M1, VRSUB_VX }, // 7477
|
|
{ PseudoVRSUB_VX_M1_MASK, VRSUB_VX }, // 7478
|
|
{ PseudoVRSUB_VX_M2, VRSUB_VX }, // 7479
|
|
{ PseudoVRSUB_VX_M2_MASK, VRSUB_VX }, // 7480
|
|
{ PseudoVRSUB_VX_M4, VRSUB_VX }, // 7481
|
|
{ PseudoVRSUB_VX_M4_MASK, VRSUB_VX }, // 7482
|
|
{ PseudoVRSUB_VX_M8, VRSUB_VX }, // 7483
|
|
{ PseudoVRSUB_VX_M8_MASK, VRSUB_VX }, // 7484
|
|
{ PseudoVRSUB_VX_MF2, VRSUB_VX }, // 7485
|
|
{ PseudoVRSUB_VX_MF2_MASK, VRSUB_VX }, // 7486
|
|
{ PseudoVRSUB_VX_MF4, VRSUB_VX }, // 7487
|
|
{ PseudoVRSUB_VX_MF4_MASK, VRSUB_VX }, // 7488
|
|
{ PseudoVRSUB_VX_MF8, VRSUB_VX }, // 7489
|
|
{ PseudoVRSUB_VX_MF8_MASK, VRSUB_VX }, // 7490
|
|
{ PseudoVSADDU_VI_M1, VSADDU_VI }, // 7491
|
|
{ PseudoVSADDU_VI_M1_MASK, VSADDU_VI }, // 7492
|
|
{ PseudoVSADDU_VI_M2, VSADDU_VI }, // 7493
|
|
{ PseudoVSADDU_VI_M2_MASK, VSADDU_VI }, // 7494
|
|
{ PseudoVSADDU_VI_M4, VSADDU_VI }, // 7495
|
|
{ PseudoVSADDU_VI_M4_MASK, VSADDU_VI }, // 7496
|
|
{ PseudoVSADDU_VI_M8, VSADDU_VI }, // 7497
|
|
{ PseudoVSADDU_VI_M8_MASK, VSADDU_VI }, // 7498
|
|
{ PseudoVSADDU_VI_MF2, VSADDU_VI }, // 7499
|
|
{ PseudoVSADDU_VI_MF2_MASK, VSADDU_VI }, // 7500
|
|
{ PseudoVSADDU_VI_MF4, VSADDU_VI }, // 7501
|
|
{ PseudoVSADDU_VI_MF4_MASK, VSADDU_VI }, // 7502
|
|
{ PseudoVSADDU_VI_MF8, VSADDU_VI }, // 7503
|
|
{ PseudoVSADDU_VI_MF8_MASK, VSADDU_VI }, // 7504
|
|
{ PseudoVSADDU_VV_M1, VSADDU_VV }, // 7505
|
|
{ PseudoVSADDU_VV_M1_MASK, VSADDU_VV }, // 7506
|
|
{ PseudoVSADDU_VV_M2, VSADDU_VV }, // 7507
|
|
{ PseudoVSADDU_VV_M2_MASK, VSADDU_VV }, // 7508
|
|
{ PseudoVSADDU_VV_M4, VSADDU_VV }, // 7509
|
|
{ PseudoVSADDU_VV_M4_MASK, VSADDU_VV }, // 7510
|
|
{ PseudoVSADDU_VV_M8, VSADDU_VV }, // 7511
|
|
{ PseudoVSADDU_VV_M8_MASK, VSADDU_VV }, // 7512
|
|
{ PseudoVSADDU_VV_MF2, VSADDU_VV }, // 7513
|
|
{ PseudoVSADDU_VV_MF2_MASK, VSADDU_VV }, // 7514
|
|
{ PseudoVSADDU_VV_MF4, VSADDU_VV }, // 7515
|
|
{ PseudoVSADDU_VV_MF4_MASK, VSADDU_VV }, // 7516
|
|
{ PseudoVSADDU_VV_MF8, VSADDU_VV }, // 7517
|
|
{ PseudoVSADDU_VV_MF8_MASK, VSADDU_VV }, // 7518
|
|
{ PseudoVSADDU_VX_M1, VSADDU_VX }, // 7519
|
|
{ PseudoVSADDU_VX_M1_MASK, VSADDU_VX }, // 7520
|
|
{ PseudoVSADDU_VX_M2, VSADDU_VX }, // 7521
|
|
{ PseudoVSADDU_VX_M2_MASK, VSADDU_VX }, // 7522
|
|
{ PseudoVSADDU_VX_M4, VSADDU_VX }, // 7523
|
|
{ PseudoVSADDU_VX_M4_MASK, VSADDU_VX }, // 7524
|
|
{ PseudoVSADDU_VX_M8, VSADDU_VX }, // 7525
|
|
{ PseudoVSADDU_VX_M8_MASK, VSADDU_VX }, // 7526
|
|
{ PseudoVSADDU_VX_MF2, VSADDU_VX }, // 7527
|
|
{ PseudoVSADDU_VX_MF2_MASK, VSADDU_VX }, // 7528
|
|
{ PseudoVSADDU_VX_MF4, VSADDU_VX }, // 7529
|
|
{ PseudoVSADDU_VX_MF4_MASK, VSADDU_VX }, // 7530
|
|
{ PseudoVSADDU_VX_MF8, VSADDU_VX }, // 7531
|
|
{ PseudoVSADDU_VX_MF8_MASK, VSADDU_VX }, // 7532
|
|
{ PseudoVSADD_VI_M1, VSADD_VI }, // 7533
|
|
{ PseudoVSADD_VI_M1_MASK, VSADD_VI }, // 7534
|
|
{ PseudoVSADD_VI_M2, VSADD_VI }, // 7535
|
|
{ PseudoVSADD_VI_M2_MASK, VSADD_VI }, // 7536
|
|
{ PseudoVSADD_VI_M4, VSADD_VI }, // 7537
|
|
{ PseudoVSADD_VI_M4_MASK, VSADD_VI }, // 7538
|
|
{ PseudoVSADD_VI_M8, VSADD_VI }, // 7539
|
|
{ PseudoVSADD_VI_M8_MASK, VSADD_VI }, // 7540
|
|
{ PseudoVSADD_VI_MF2, VSADD_VI }, // 7541
|
|
{ PseudoVSADD_VI_MF2_MASK, VSADD_VI }, // 7542
|
|
{ PseudoVSADD_VI_MF4, VSADD_VI }, // 7543
|
|
{ PseudoVSADD_VI_MF4_MASK, VSADD_VI }, // 7544
|
|
{ PseudoVSADD_VI_MF8, VSADD_VI }, // 7545
|
|
{ PseudoVSADD_VI_MF8_MASK, VSADD_VI }, // 7546
|
|
{ PseudoVSADD_VV_M1, VSADD_VV }, // 7547
|
|
{ PseudoVSADD_VV_M1_MASK, VSADD_VV }, // 7548
|
|
{ PseudoVSADD_VV_M2, VSADD_VV }, // 7549
|
|
{ PseudoVSADD_VV_M2_MASK, VSADD_VV }, // 7550
|
|
{ PseudoVSADD_VV_M4, VSADD_VV }, // 7551
|
|
{ PseudoVSADD_VV_M4_MASK, VSADD_VV }, // 7552
|
|
{ PseudoVSADD_VV_M8, VSADD_VV }, // 7553
|
|
{ PseudoVSADD_VV_M8_MASK, VSADD_VV }, // 7554
|
|
{ PseudoVSADD_VV_MF2, VSADD_VV }, // 7555
|
|
{ PseudoVSADD_VV_MF2_MASK, VSADD_VV }, // 7556
|
|
{ PseudoVSADD_VV_MF4, VSADD_VV }, // 7557
|
|
{ PseudoVSADD_VV_MF4_MASK, VSADD_VV }, // 7558
|
|
{ PseudoVSADD_VV_MF8, VSADD_VV }, // 7559
|
|
{ PseudoVSADD_VV_MF8_MASK, VSADD_VV }, // 7560
|
|
{ PseudoVSADD_VX_M1, VSADD_VX }, // 7561
|
|
{ PseudoVSADD_VX_M1_MASK, VSADD_VX }, // 7562
|
|
{ PseudoVSADD_VX_M2, VSADD_VX }, // 7563
|
|
{ PseudoVSADD_VX_M2_MASK, VSADD_VX }, // 7564
|
|
{ PseudoVSADD_VX_M4, VSADD_VX }, // 7565
|
|
{ PseudoVSADD_VX_M4_MASK, VSADD_VX }, // 7566
|
|
{ PseudoVSADD_VX_M8, VSADD_VX }, // 7567
|
|
{ PseudoVSADD_VX_M8_MASK, VSADD_VX }, // 7568
|
|
{ PseudoVSADD_VX_MF2, VSADD_VX }, // 7569
|
|
{ PseudoVSADD_VX_MF2_MASK, VSADD_VX }, // 7570
|
|
{ PseudoVSADD_VX_MF4, VSADD_VX }, // 7571
|
|
{ PseudoVSADD_VX_MF4_MASK, VSADD_VX }, // 7572
|
|
{ PseudoVSADD_VX_MF8, VSADD_VX }, // 7573
|
|
{ PseudoVSADD_VX_MF8_MASK, VSADD_VX }, // 7574
|
|
{ PseudoVSBC_VVM_M1, VSBC_VVM }, // 7575
|
|
{ PseudoVSBC_VVM_M2, VSBC_VVM }, // 7576
|
|
{ PseudoVSBC_VVM_M4, VSBC_VVM }, // 7577
|
|
{ PseudoVSBC_VVM_M8, VSBC_VVM }, // 7578
|
|
{ PseudoVSBC_VVM_MF2, VSBC_VVM }, // 7579
|
|
{ PseudoVSBC_VVM_MF4, VSBC_VVM }, // 7580
|
|
{ PseudoVSBC_VVM_MF8, VSBC_VVM }, // 7581
|
|
{ PseudoVSBC_VXM_M1, VSBC_VXM }, // 7582
|
|
{ PseudoVSBC_VXM_M2, VSBC_VXM }, // 7583
|
|
{ PseudoVSBC_VXM_M4, VSBC_VXM }, // 7584
|
|
{ PseudoVSBC_VXM_M8, VSBC_VXM }, // 7585
|
|
{ PseudoVSBC_VXM_MF2, VSBC_VXM }, // 7586
|
|
{ PseudoVSBC_VXM_MF4, VSBC_VXM }, // 7587
|
|
{ PseudoVSBC_VXM_MF8, VSBC_VXM }, // 7588
|
|
{ PseudoVSE16_V_M1, VSE16_V }, // 7589
|
|
{ PseudoVSE16_V_M1_MASK, VSE16_V }, // 7590
|
|
{ PseudoVSE16_V_M2, VSE16_V }, // 7591
|
|
{ PseudoVSE16_V_M2_MASK, VSE16_V }, // 7592
|
|
{ PseudoVSE16_V_M4, VSE16_V }, // 7593
|
|
{ PseudoVSE16_V_M4_MASK, VSE16_V }, // 7594
|
|
{ PseudoVSE16_V_M8, VSE16_V }, // 7595
|
|
{ PseudoVSE16_V_M8_MASK, VSE16_V }, // 7596
|
|
{ PseudoVSE16_V_MF2, VSE16_V }, // 7597
|
|
{ PseudoVSE16_V_MF2_MASK, VSE16_V }, // 7598
|
|
{ PseudoVSE16_V_MF4, VSE16_V }, // 7599
|
|
{ PseudoVSE16_V_MF4_MASK, VSE16_V }, // 7600
|
|
{ PseudoVSE32_V_M1, VSE32_V }, // 7601
|
|
{ PseudoVSE32_V_M1_MASK, VSE32_V }, // 7602
|
|
{ PseudoVSE32_V_M2, VSE32_V }, // 7603
|
|
{ PseudoVSE32_V_M2_MASK, VSE32_V }, // 7604
|
|
{ PseudoVSE32_V_M4, VSE32_V }, // 7605
|
|
{ PseudoVSE32_V_M4_MASK, VSE32_V }, // 7606
|
|
{ PseudoVSE32_V_M8, VSE32_V }, // 7607
|
|
{ PseudoVSE32_V_M8_MASK, VSE32_V }, // 7608
|
|
{ PseudoVSE32_V_MF2, VSE32_V }, // 7609
|
|
{ PseudoVSE32_V_MF2_MASK, VSE32_V }, // 7610
|
|
{ PseudoVSE64_V_M1, VSE64_V }, // 7611
|
|
{ PseudoVSE64_V_M1_MASK, VSE64_V }, // 7612
|
|
{ PseudoVSE64_V_M2, VSE64_V }, // 7613
|
|
{ PseudoVSE64_V_M2_MASK, VSE64_V }, // 7614
|
|
{ PseudoVSE64_V_M4, VSE64_V }, // 7615
|
|
{ PseudoVSE64_V_M4_MASK, VSE64_V }, // 7616
|
|
{ PseudoVSE64_V_M8, VSE64_V }, // 7617
|
|
{ PseudoVSE64_V_M8_MASK, VSE64_V }, // 7618
|
|
{ PseudoVSE8_V_M1, VSE8_V }, // 7619
|
|
{ PseudoVSE8_V_M1_MASK, VSE8_V }, // 7620
|
|
{ PseudoVSE8_V_M2, VSE8_V }, // 7621
|
|
{ PseudoVSE8_V_M2_MASK, VSE8_V }, // 7622
|
|
{ PseudoVSE8_V_M4, VSE8_V }, // 7623
|
|
{ PseudoVSE8_V_M4_MASK, VSE8_V }, // 7624
|
|
{ PseudoVSE8_V_M8, VSE8_V }, // 7625
|
|
{ PseudoVSE8_V_M8_MASK, VSE8_V }, // 7626
|
|
{ PseudoVSE8_V_MF2, VSE8_V }, // 7627
|
|
{ PseudoVSE8_V_MF2_MASK, VSE8_V }, // 7628
|
|
{ PseudoVSE8_V_MF4, VSE8_V }, // 7629
|
|
{ PseudoVSE8_V_MF4_MASK, VSE8_V }, // 7630
|
|
{ PseudoVSE8_V_MF8, VSE8_V }, // 7631
|
|
{ PseudoVSE8_V_MF8_MASK, VSE8_V }, // 7632
|
|
{ PseudoVSEXT_VF2_M1, VSEXT_VF2 }, // 7633
|
|
{ PseudoVSEXT_VF2_M1_MASK, VSEXT_VF2 }, // 7634
|
|
{ PseudoVSEXT_VF2_M2, VSEXT_VF2 }, // 7635
|
|
{ PseudoVSEXT_VF2_M2_MASK, VSEXT_VF2 }, // 7636
|
|
{ PseudoVSEXT_VF2_M4, VSEXT_VF2 }, // 7637
|
|
{ PseudoVSEXT_VF2_M4_MASK, VSEXT_VF2 }, // 7638
|
|
{ PseudoVSEXT_VF2_M8, VSEXT_VF2 }, // 7639
|
|
{ PseudoVSEXT_VF2_M8_MASK, VSEXT_VF2 }, // 7640
|
|
{ PseudoVSEXT_VF2_MF2, VSEXT_VF2 }, // 7641
|
|
{ PseudoVSEXT_VF2_MF2_MASK, VSEXT_VF2 }, // 7642
|
|
{ PseudoVSEXT_VF2_MF4, VSEXT_VF2 }, // 7643
|
|
{ PseudoVSEXT_VF2_MF4_MASK, VSEXT_VF2 }, // 7644
|
|
{ PseudoVSEXT_VF4_M1, VSEXT_VF4 }, // 7645
|
|
{ PseudoVSEXT_VF4_M1_MASK, VSEXT_VF4 }, // 7646
|
|
{ PseudoVSEXT_VF4_M2, VSEXT_VF4 }, // 7647
|
|
{ PseudoVSEXT_VF4_M2_MASK, VSEXT_VF4 }, // 7648
|
|
{ PseudoVSEXT_VF4_M4, VSEXT_VF4 }, // 7649
|
|
{ PseudoVSEXT_VF4_M4_MASK, VSEXT_VF4 }, // 7650
|
|
{ PseudoVSEXT_VF4_M8, VSEXT_VF4 }, // 7651
|
|
{ PseudoVSEXT_VF4_M8_MASK, VSEXT_VF4 }, // 7652
|
|
{ PseudoVSEXT_VF4_MF2, VSEXT_VF4 }, // 7653
|
|
{ PseudoVSEXT_VF4_MF2_MASK, VSEXT_VF4 }, // 7654
|
|
{ PseudoVSEXT_VF8_M1, VSEXT_VF8 }, // 7655
|
|
{ PseudoVSEXT_VF8_M1_MASK, VSEXT_VF8 }, // 7656
|
|
{ PseudoVSEXT_VF8_M2, VSEXT_VF8 }, // 7657
|
|
{ PseudoVSEXT_VF8_M2_MASK, VSEXT_VF8 }, // 7658
|
|
{ PseudoVSEXT_VF8_M4, VSEXT_VF8 }, // 7659
|
|
{ PseudoVSEXT_VF8_M4_MASK, VSEXT_VF8 }, // 7660
|
|
{ PseudoVSEXT_VF8_M8, VSEXT_VF8 }, // 7661
|
|
{ PseudoVSEXT_VF8_M8_MASK, VSEXT_VF8 }, // 7662
|
|
{ PseudoVSHA2CH_VV_M1, VSHA2CH_VV }, // 7663
|
|
{ PseudoVSHA2CH_VV_M2, VSHA2CH_VV }, // 7664
|
|
{ PseudoVSHA2CH_VV_M4, VSHA2CH_VV }, // 7665
|
|
{ PseudoVSHA2CH_VV_M8, VSHA2CH_VV }, // 7666
|
|
{ PseudoVSHA2CH_VV_MF2, VSHA2CH_VV }, // 7667
|
|
{ PseudoVSHA2CL_VV_M1, VSHA2CL_VV }, // 7668
|
|
{ PseudoVSHA2CL_VV_M2, VSHA2CL_VV }, // 7669
|
|
{ PseudoVSHA2CL_VV_M4, VSHA2CL_VV }, // 7670
|
|
{ PseudoVSHA2CL_VV_M8, VSHA2CL_VV }, // 7671
|
|
{ PseudoVSHA2CL_VV_MF2, VSHA2CL_VV }, // 7672
|
|
{ PseudoVSHA2MS_VV_M1, VSHA2MS_VV }, // 7673
|
|
{ PseudoVSHA2MS_VV_M2, VSHA2MS_VV }, // 7674
|
|
{ PseudoVSHA2MS_VV_M4, VSHA2MS_VV }, // 7675
|
|
{ PseudoVSHA2MS_VV_M8, VSHA2MS_VV }, // 7676
|
|
{ PseudoVSHA2MS_VV_MF2, VSHA2MS_VV }, // 7677
|
|
{ PseudoVSLIDE1DOWN_VX_M1, VSLIDE1DOWN_VX }, // 7678
|
|
{ PseudoVSLIDE1DOWN_VX_M1_MASK, VSLIDE1DOWN_VX }, // 7679
|
|
{ PseudoVSLIDE1DOWN_VX_M2, VSLIDE1DOWN_VX }, // 7680
|
|
{ PseudoVSLIDE1DOWN_VX_M2_MASK, VSLIDE1DOWN_VX }, // 7681
|
|
{ PseudoVSLIDE1DOWN_VX_M4, VSLIDE1DOWN_VX }, // 7682
|
|
{ PseudoVSLIDE1DOWN_VX_M4_MASK, VSLIDE1DOWN_VX }, // 7683
|
|
{ PseudoVSLIDE1DOWN_VX_M8, VSLIDE1DOWN_VX }, // 7684
|
|
{ PseudoVSLIDE1DOWN_VX_M8_MASK, VSLIDE1DOWN_VX }, // 7685
|
|
{ PseudoVSLIDE1DOWN_VX_MF2, VSLIDE1DOWN_VX }, // 7686
|
|
{ PseudoVSLIDE1DOWN_VX_MF2_MASK, VSLIDE1DOWN_VX }, // 7687
|
|
{ PseudoVSLIDE1DOWN_VX_MF4, VSLIDE1DOWN_VX }, // 7688
|
|
{ PseudoVSLIDE1DOWN_VX_MF4_MASK, VSLIDE1DOWN_VX }, // 7689
|
|
{ PseudoVSLIDE1DOWN_VX_MF8, VSLIDE1DOWN_VX }, // 7690
|
|
{ PseudoVSLIDE1DOWN_VX_MF8_MASK, VSLIDE1DOWN_VX }, // 7691
|
|
{ PseudoVSLIDE1UP_VX_M1, VSLIDE1UP_VX }, // 7692
|
|
{ PseudoVSLIDE1UP_VX_M1_MASK, VSLIDE1UP_VX }, // 7693
|
|
{ PseudoVSLIDE1UP_VX_M2, VSLIDE1UP_VX }, // 7694
|
|
{ PseudoVSLIDE1UP_VX_M2_MASK, VSLIDE1UP_VX }, // 7695
|
|
{ PseudoVSLIDE1UP_VX_M4, VSLIDE1UP_VX }, // 7696
|
|
{ PseudoVSLIDE1UP_VX_M4_MASK, VSLIDE1UP_VX }, // 7697
|
|
{ PseudoVSLIDE1UP_VX_M8, VSLIDE1UP_VX }, // 7698
|
|
{ PseudoVSLIDE1UP_VX_M8_MASK, VSLIDE1UP_VX }, // 7699
|
|
{ PseudoVSLIDE1UP_VX_MF2, VSLIDE1UP_VX }, // 7700
|
|
{ PseudoVSLIDE1UP_VX_MF2_MASK, VSLIDE1UP_VX }, // 7701
|
|
{ PseudoVSLIDE1UP_VX_MF4, VSLIDE1UP_VX }, // 7702
|
|
{ PseudoVSLIDE1UP_VX_MF4_MASK, VSLIDE1UP_VX }, // 7703
|
|
{ PseudoVSLIDE1UP_VX_MF8, VSLIDE1UP_VX }, // 7704
|
|
{ PseudoVSLIDE1UP_VX_MF8_MASK, VSLIDE1UP_VX }, // 7705
|
|
{ PseudoVSLIDEDOWN_VI_M1, VSLIDEDOWN_VI }, // 7706
|
|
{ PseudoVSLIDEDOWN_VI_M1_MASK, VSLIDEDOWN_VI }, // 7707
|
|
{ PseudoVSLIDEDOWN_VI_M2, VSLIDEDOWN_VI }, // 7708
|
|
{ PseudoVSLIDEDOWN_VI_M2_MASK, VSLIDEDOWN_VI }, // 7709
|
|
{ PseudoVSLIDEDOWN_VI_M4, VSLIDEDOWN_VI }, // 7710
|
|
{ PseudoVSLIDEDOWN_VI_M4_MASK, VSLIDEDOWN_VI }, // 7711
|
|
{ PseudoVSLIDEDOWN_VI_M8, VSLIDEDOWN_VI }, // 7712
|
|
{ PseudoVSLIDEDOWN_VI_M8_MASK, VSLIDEDOWN_VI }, // 7713
|
|
{ PseudoVSLIDEDOWN_VI_MF2, VSLIDEDOWN_VI }, // 7714
|
|
{ PseudoVSLIDEDOWN_VI_MF2_MASK, VSLIDEDOWN_VI }, // 7715
|
|
{ PseudoVSLIDEDOWN_VI_MF4, VSLIDEDOWN_VI }, // 7716
|
|
{ PseudoVSLIDEDOWN_VI_MF4_MASK, VSLIDEDOWN_VI }, // 7717
|
|
{ PseudoVSLIDEDOWN_VI_MF8, VSLIDEDOWN_VI }, // 7718
|
|
{ PseudoVSLIDEDOWN_VI_MF8_MASK, VSLIDEDOWN_VI }, // 7719
|
|
{ PseudoVSLIDEDOWN_VX_M1, VSLIDEDOWN_VX }, // 7720
|
|
{ PseudoVSLIDEDOWN_VX_M1_MASK, VSLIDEDOWN_VX }, // 7721
|
|
{ PseudoVSLIDEDOWN_VX_M2, VSLIDEDOWN_VX }, // 7722
|
|
{ PseudoVSLIDEDOWN_VX_M2_MASK, VSLIDEDOWN_VX }, // 7723
|
|
{ PseudoVSLIDEDOWN_VX_M4, VSLIDEDOWN_VX }, // 7724
|
|
{ PseudoVSLIDEDOWN_VX_M4_MASK, VSLIDEDOWN_VX }, // 7725
|
|
{ PseudoVSLIDEDOWN_VX_M8, VSLIDEDOWN_VX }, // 7726
|
|
{ PseudoVSLIDEDOWN_VX_M8_MASK, VSLIDEDOWN_VX }, // 7727
|
|
{ PseudoVSLIDEDOWN_VX_MF2, VSLIDEDOWN_VX }, // 7728
|
|
{ PseudoVSLIDEDOWN_VX_MF2_MASK, VSLIDEDOWN_VX }, // 7729
|
|
{ PseudoVSLIDEDOWN_VX_MF4, VSLIDEDOWN_VX }, // 7730
|
|
{ PseudoVSLIDEDOWN_VX_MF4_MASK, VSLIDEDOWN_VX }, // 7731
|
|
{ PseudoVSLIDEDOWN_VX_MF8, VSLIDEDOWN_VX }, // 7732
|
|
{ PseudoVSLIDEDOWN_VX_MF8_MASK, VSLIDEDOWN_VX }, // 7733
|
|
{ PseudoVSLIDEUP_VI_M1, VSLIDEUP_VI }, // 7734
|
|
{ PseudoVSLIDEUP_VI_M1_MASK, VSLIDEUP_VI }, // 7735
|
|
{ PseudoVSLIDEUP_VI_M2, VSLIDEUP_VI }, // 7736
|
|
{ PseudoVSLIDEUP_VI_M2_MASK, VSLIDEUP_VI }, // 7737
|
|
{ PseudoVSLIDEUP_VI_M4, VSLIDEUP_VI }, // 7738
|
|
{ PseudoVSLIDEUP_VI_M4_MASK, VSLIDEUP_VI }, // 7739
|
|
{ PseudoVSLIDEUP_VI_M8, VSLIDEUP_VI }, // 7740
|
|
{ PseudoVSLIDEUP_VI_M8_MASK, VSLIDEUP_VI }, // 7741
|
|
{ PseudoVSLIDEUP_VI_MF2, VSLIDEUP_VI }, // 7742
|
|
{ PseudoVSLIDEUP_VI_MF2_MASK, VSLIDEUP_VI }, // 7743
|
|
{ PseudoVSLIDEUP_VI_MF4, VSLIDEUP_VI }, // 7744
|
|
{ PseudoVSLIDEUP_VI_MF4_MASK, VSLIDEUP_VI }, // 7745
|
|
{ PseudoVSLIDEUP_VI_MF8, VSLIDEUP_VI }, // 7746
|
|
{ PseudoVSLIDEUP_VI_MF8_MASK, VSLIDEUP_VI }, // 7747
|
|
{ PseudoVSLIDEUP_VX_M1, VSLIDEUP_VX }, // 7748
|
|
{ PseudoVSLIDEUP_VX_M1_MASK, VSLIDEUP_VX }, // 7749
|
|
{ PseudoVSLIDEUP_VX_M2, VSLIDEUP_VX }, // 7750
|
|
{ PseudoVSLIDEUP_VX_M2_MASK, VSLIDEUP_VX }, // 7751
|
|
{ PseudoVSLIDEUP_VX_M4, VSLIDEUP_VX }, // 7752
|
|
{ PseudoVSLIDEUP_VX_M4_MASK, VSLIDEUP_VX }, // 7753
|
|
{ PseudoVSLIDEUP_VX_M8, VSLIDEUP_VX }, // 7754
|
|
{ PseudoVSLIDEUP_VX_M8_MASK, VSLIDEUP_VX }, // 7755
|
|
{ PseudoVSLIDEUP_VX_MF2, VSLIDEUP_VX }, // 7756
|
|
{ PseudoVSLIDEUP_VX_MF2_MASK, VSLIDEUP_VX }, // 7757
|
|
{ PseudoVSLIDEUP_VX_MF4, VSLIDEUP_VX }, // 7758
|
|
{ PseudoVSLIDEUP_VX_MF4_MASK, VSLIDEUP_VX }, // 7759
|
|
{ PseudoVSLIDEUP_VX_MF8, VSLIDEUP_VX }, // 7760
|
|
{ PseudoVSLIDEUP_VX_MF8_MASK, VSLIDEUP_VX }, // 7761
|
|
{ PseudoVSLL_VI_M1, VSLL_VI }, // 7762
|
|
{ PseudoVSLL_VI_M1_MASK, VSLL_VI }, // 7763
|
|
{ PseudoVSLL_VI_M2, VSLL_VI }, // 7764
|
|
{ PseudoVSLL_VI_M2_MASK, VSLL_VI }, // 7765
|
|
{ PseudoVSLL_VI_M4, VSLL_VI }, // 7766
|
|
{ PseudoVSLL_VI_M4_MASK, VSLL_VI }, // 7767
|
|
{ PseudoVSLL_VI_M8, VSLL_VI }, // 7768
|
|
{ PseudoVSLL_VI_M8_MASK, VSLL_VI }, // 7769
|
|
{ PseudoVSLL_VI_MF2, VSLL_VI }, // 7770
|
|
{ PseudoVSLL_VI_MF2_MASK, VSLL_VI }, // 7771
|
|
{ PseudoVSLL_VI_MF4, VSLL_VI }, // 7772
|
|
{ PseudoVSLL_VI_MF4_MASK, VSLL_VI }, // 7773
|
|
{ PseudoVSLL_VI_MF8, VSLL_VI }, // 7774
|
|
{ PseudoVSLL_VI_MF8_MASK, VSLL_VI }, // 7775
|
|
{ PseudoVSLL_VV_M1, VSLL_VV }, // 7776
|
|
{ PseudoVSLL_VV_M1_MASK, VSLL_VV }, // 7777
|
|
{ PseudoVSLL_VV_M2, VSLL_VV }, // 7778
|
|
{ PseudoVSLL_VV_M2_MASK, VSLL_VV }, // 7779
|
|
{ PseudoVSLL_VV_M4, VSLL_VV }, // 7780
|
|
{ PseudoVSLL_VV_M4_MASK, VSLL_VV }, // 7781
|
|
{ PseudoVSLL_VV_M8, VSLL_VV }, // 7782
|
|
{ PseudoVSLL_VV_M8_MASK, VSLL_VV }, // 7783
|
|
{ PseudoVSLL_VV_MF2, VSLL_VV }, // 7784
|
|
{ PseudoVSLL_VV_MF2_MASK, VSLL_VV }, // 7785
|
|
{ PseudoVSLL_VV_MF4, VSLL_VV }, // 7786
|
|
{ PseudoVSLL_VV_MF4_MASK, VSLL_VV }, // 7787
|
|
{ PseudoVSLL_VV_MF8, VSLL_VV }, // 7788
|
|
{ PseudoVSLL_VV_MF8_MASK, VSLL_VV }, // 7789
|
|
{ PseudoVSLL_VX_M1, VSLL_VX }, // 7790
|
|
{ PseudoVSLL_VX_M1_MASK, VSLL_VX }, // 7791
|
|
{ PseudoVSLL_VX_M2, VSLL_VX }, // 7792
|
|
{ PseudoVSLL_VX_M2_MASK, VSLL_VX }, // 7793
|
|
{ PseudoVSLL_VX_M4, VSLL_VX }, // 7794
|
|
{ PseudoVSLL_VX_M4_MASK, VSLL_VX }, // 7795
|
|
{ PseudoVSLL_VX_M8, VSLL_VX }, // 7796
|
|
{ PseudoVSLL_VX_M8_MASK, VSLL_VX }, // 7797
|
|
{ PseudoVSLL_VX_MF2, VSLL_VX }, // 7798
|
|
{ PseudoVSLL_VX_MF2_MASK, VSLL_VX }, // 7799
|
|
{ PseudoVSLL_VX_MF4, VSLL_VX }, // 7800
|
|
{ PseudoVSLL_VX_MF4_MASK, VSLL_VX }, // 7801
|
|
{ PseudoVSLL_VX_MF8, VSLL_VX }, // 7802
|
|
{ PseudoVSLL_VX_MF8_MASK, VSLL_VX }, // 7803
|
|
{ PseudoVSM3C_VI_M1, VSM3C_VI }, // 7804
|
|
{ PseudoVSM3C_VI_M2, VSM3C_VI }, // 7805
|
|
{ PseudoVSM3C_VI_M4, VSM3C_VI }, // 7806
|
|
{ PseudoVSM3C_VI_M8, VSM3C_VI }, // 7807
|
|
{ PseudoVSM3C_VI_MF2, VSM3C_VI }, // 7808
|
|
{ PseudoVSM3ME_VV_M1, VSM3ME_VV }, // 7809
|
|
{ PseudoVSM3ME_VV_M2, VSM3ME_VV }, // 7810
|
|
{ PseudoVSM3ME_VV_M4, VSM3ME_VV }, // 7811
|
|
{ PseudoVSM3ME_VV_M8, VSM3ME_VV }, // 7812
|
|
{ PseudoVSM3ME_VV_MF2, VSM3ME_VV }, // 7813
|
|
{ PseudoVSM4K_VI_M1, VSM4K_VI }, // 7814
|
|
{ PseudoVSM4K_VI_M2, VSM4K_VI }, // 7815
|
|
{ PseudoVSM4K_VI_M4, VSM4K_VI }, // 7816
|
|
{ PseudoVSM4K_VI_M8, VSM4K_VI }, // 7817
|
|
{ PseudoVSM4K_VI_MF2, VSM4K_VI }, // 7818
|
|
{ PseudoVSM4R_VS_M1_M1, VSM4R_VS }, // 7819
|
|
{ PseudoVSM4R_VS_M1_MF2, VSM4R_VS }, // 7820
|
|
{ PseudoVSM4R_VS_M1_MF4, VSM4R_VS }, // 7821
|
|
{ PseudoVSM4R_VS_M1_MF8, VSM4R_VS }, // 7822
|
|
{ PseudoVSM4R_VS_M2_M1, VSM4R_VS }, // 7823
|
|
{ PseudoVSM4R_VS_M2_M2, VSM4R_VS }, // 7824
|
|
{ PseudoVSM4R_VS_M2_MF2, VSM4R_VS }, // 7825
|
|
{ PseudoVSM4R_VS_M2_MF4, VSM4R_VS }, // 7826
|
|
{ PseudoVSM4R_VS_M2_MF8, VSM4R_VS }, // 7827
|
|
{ PseudoVSM4R_VS_M4_M1, VSM4R_VS }, // 7828
|
|
{ PseudoVSM4R_VS_M4_M2, VSM4R_VS }, // 7829
|
|
{ PseudoVSM4R_VS_M4_M4, VSM4R_VS }, // 7830
|
|
{ PseudoVSM4R_VS_M4_MF2, VSM4R_VS }, // 7831
|
|
{ PseudoVSM4R_VS_M4_MF4, VSM4R_VS }, // 7832
|
|
{ PseudoVSM4R_VS_M4_MF8, VSM4R_VS }, // 7833
|
|
{ PseudoVSM4R_VS_M8_M1, VSM4R_VS }, // 7834
|
|
{ PseudoVSM4R_VS_M8_M2, VSM4R_VS }, // 7835
|
|
{ PseudoVSM4R_VS_M8_M4, VSM4R_VS }, // 7836
|
|
{ PseudoVSM4R_VS_M8_MF2, VSM4R_VS }, // 7837
|
|
{ PseudoVSM4R_VS_M8_MF4, VSM4R_VS }, // 7838
|
|
{ PseudoVSM4R_VS_M8_MF8, VSM4R_VS }, // 7839
|
|
{ PseudoVSM4R_VS_MF2_MF2, VSM4R_VS }, // 7840
|
|
{ PseudoVSM4R_VS_MF2_MF4, VSM4R_VS }, // 7841
|
|
{ PseudoVSM4R_VS_MF2_MF8, VSM4R_VS }, // 7842
|
|
{ PseudoVSM4R_VV_M1, VSM4R_VV }, // 7843
|
|
{ PseudoVSM4R_VV_M2, VSM4R_VV }, // 7844
|
|
{ PseudoVSM4R_VV_M4, VSM4R_VV }, // 7845
|
|
{ PseudoVSM4R_VV_M8, VSM4R_VV }, // 7846
|
|
{ PseudoVSM4R_VV_MF2, VSM4R_VV }, // 7847
|
|
{ PseudoVSMUL_VV_M1, VSMUL_VV }, // 7848
|
|
{ PseudoVSMUL_VV_M1_MASK, VSMUL_VV }, // 7849
|
|
{ PseudoVSMUL_VV_M2, VSMUL_VV }, // 7850
|
|
{ PseudoVSMUL_VV_M2_MASK, VSMUL_VV }, // 7851
|
|
{ PseudoVSMUL_VV_M4, VSMUL_VV }, // 7852
|
|
{ PseudoVSMUL_VV_M4_MASK, VSMUL_VV }, // 7853
|
|
{ PseudoVSMUL_VV_M8, VSMUL_VV }, // 7854
|
|
{ PseudoVSMUL_VV_M8_MASK, VSMUL_VV }, // 7855
|
|
{ PseudoVSMUL_VV_MF2, VSMUL_VV }, // 7856
|
|
{ PseudoVSMUL_VV_MF2_MASK, VSMUL_VV }, // 7857
|
|
{ PseudoVSMUL_VV_MF4, VSMUL_VV }, // 7858
|
|
{ PseudoVSMUL_VV_MF4_MASK, VSMUL_VV }, // 7859
|
|
{ PseudoVSMUL_VV_MF8, VSMUL_VV }, // 7860
|
|
{ PseudoVSMUL_VV_MF8_MASK, VSMUL_VV }, // 7861
|
|
{ PseudoVSMUL_VX_M1, VSMUL_VX }, // 7862
|
|
{ PseudoVSMUL_VX_M1_MASK, VSMUL_VX }, // 7863
|
|
{ PseudoVSMUL_VX_M2, VSMUL_VX }, // 7864
|
|
{ PseudoVSMUL_VX_M2_MASK, VSMUL_VX }, // 7865
|
|
{ PseudoVSMUL_VX_M4, VSMUL_VX }, // 7866
|
|
{ PseudoVSMUL_VX_M4_MASK, VSMUL_VX }, // 7867
|
|
{ PseudoVSMUL_VX_M8, VSMUL_VX }, // 7868
|
|
{ PseudoVSMUL_VX_M8_MASK, VSMUL_VX }, // 7869
|
|
{ PseudoVSMUL_VX_MF2, VSMUL_VX }, // 7870
|
|
{ PseudoVSMUL_VX_MF2_MASK, VSMUL_VX }, // 7871
|
|
{ PseudoVSMUL_VX_MF4, VSMUL_VX }, // 7872
|
|
{ PseudoVSMUL_VX_MF4_MASK, VSMUL_VX }, // 7873
|
|
{ PseudoVSMUL_VX_MF8, VSMUL_VX }, // 7874
|
|
{ PseudoVSMUL_VX_MF8_MASK, VSMUL_VX }, // 7875
|
|
{ PseudoVSM_V_B1, VSM_V }, // 7876
|
|
{ PseudoVSM_V_B16, VSM_V }, // 7877
|
|
{ PseudoVSM_V_B2, VSM_V }, // 7878
|
|
{ PseudoVSM_V_B32, VSM_V }, // 7879
|
|
{ PseudoVSM_V_B4, VSM_V }, // 7880
|
|
{ PseudoVSM_V_B64, VSM_V }, // 7881
|
|
{ PseudoVSM_V_B8, VSM_V }, // 7882
|
|
{ PseudoVSOXEI16_V_M1_M1, VSOXEI16_V }, // 7883
|
|
{ PseudoVSOXEI16_V_M1_M1_MASK, VSOXEI16_V }, // 7884
|
|
{ PseudoVSOXEI16_V_M1_M2, VSOXEI16_V }, // 7885
|
|
{ PseudoVSOXEI16_V_M1_M2_MASK, VSOXEI16_V }, // 7886
|
|
{ PseudoVSOXEI16_V_M1_M4, VSOXEI16_V }, // 7887
|
|
{ PseudoVSOXEI16_V_M1_M4_MASK, VSOXEI16_V }, // 7888
|
|
{ PseudoVSOXEI16_V_M1_MF2, VSOXEI16_V }, // 7889
|
|
{ PseudoVSOXEI16_V_M1_MF2_MASK, VSOXEI16_V }, // 7890
|
|
{ PseudoVSOXEI16_V_M2_M1, VSOXEI16_V }, // 7891
|
|
{ PseudoVSOXEI16_V_M2_M1_MASK, VSOXEI16_V }, // 7892
|
|
{ PseudoVSOXEI16_V_M2_M2, VSOXEI16_V }, // 7893
|
|
{ PseudoVSOXEI16_V_M2_M2_MASK, VSOXEI16_V }, // 7894
|
|
{ PseudoVSOXEI16_V_M2_M4, VSOXEI16_V }, // 7895
|
|
{ PseudoVSOXEI16_V_M2_M4_MASK, VSOXEI16_V }, // 7896
|
|
{ PseudoVSOXEI16_V_M2_M8, VSOXEI16_V }, // 7897
|
|
{ PseudoVSOXEI16_V_M2_M8_MASK, VSOXEI16_V }, // 7898
|
|
{ PseudoVSOXEI16_V_M4_M2, VSOXEI16_V }, // 7899
|
|
{ PseudoVSOXEI16_V_M4_M2_MASK, VSOXEI16_V }, // 7900
|
|
{ PseudoVSOXEI16_V_M4_M4, VSOXEI16_V }, // 7901
|
|
{ PseudoVSOXEI16_V_M4_M4_MASK, VSOXEI16_V }, // 7902
|
|
{ PseudoVSOXEI16_V_M4_M8, VSOXEI16_V }, // 7903
|
|
{ PseudoVSOXEI16_V_M4_M8_MASK, VSOXEI16_V }, // 7904
|
|
{ PseudoVSOXEI16_V_M8_M4, VSOXEI16_V }, // 7905
|
|
{ PseudoVSOXEI16_V_M8_M4_MASK, VSOXEI16_V }, // 7906
|
|
{ PseudoVSOXEI16_V_M8_M8, VSOXEI16_V }, // 7907
|
|
{ PseudoVSOXEI16_V_M8_M8_MASK, VSOXEI16_V }, // 7908
|
|
{ PseudoVSOXEI16_V_MF2_M1, VSOXEI16_V }, // 7909
|
|
{ PseudoVSOXEI16_V_MF2_M1_MASK, VSOXEI16_V }, // 7910
|
|
{ PseudoVSOXEI16_V_MF2_M2, VSOXEI16_V }, // 7911
|
|
{ PseudoVSOXEI16_V_MF2_M2_MASK, VSOXEI16_V }, // 7912
|
|
{ PseudoVSOXEI16_V_MF2_MF2, VSOXEI16_V }, // 7913
|
|
{ PseudoVSOXEI16_V_MF2_MF2_MASK, VSOXEI16_V }, // 7914
|
|
{ PseudoVSOXEI16_V_MF2_MF4, VSOXEI16_V }, // 7915
|
|
{ PseudoVSOXEI16_V_MF2_MF4_MASK, VSOXEI16_V }, // 7916
|
|
{ PseudoVSOXEI16_V_MF4_M1, VSOXEI16_V }, // 7917
|
|
{ PseudoVSOXEI16_V_MF4_M1_MASK, VSOXEI16_V }, // 7918
|
|
{ PseudoVSOXEI16_V_MF4_MF2, VSOXEI16_V }, // 7919
|
|
{ PseudoVSOXEI16_V_MF4_MF2_MASK, VSOXEI16_V }, // 7920
|
|
{ PseudoVSOXEI16_V_MF4_MF4, VSOXEI16_V }, // 7921
|
|
{ PseudoVSOXEI16_V_MF4_MF4_MASK, VSOXEI16_V }, // 7922
|
|
{ PseudoVSOXEI16_V_MF4_MF8, VSOXEI16_V }, // 7923
|
|
{ PseudoVSOXEI16_V_MF4_MF8_MASK, VSOXEI16_V }, // 7924
|
|
{ PseudoVSOXEI32_V_M1_M1, VSOXEI32_V }, // 7925
|
|
{ PseudoVSOXEI32_V_M1_M1_MASK, VSOXEI32_V }, // 7926
|
|
{ PseudoVSOXEI32_V_M1_M2, VSOXEI32_V }, // 7927
|
|
{ PseudoVSOXEI32_V_M1_M2_MASK, VSOXEI32_V }, // 7928
|
|
{ PseudoVSOXEI32_V_M1_MF2, VSOXEI32_V }, // 7929
|
|
{ PseudoVSOXEI32_V_M1_MF2_MASK, VSOXEI32_V }, // 7930
|
|
{ PseudoVSOXEI32_V_M1_MF4, VSOXEI32_V }, // 7931
|
|
{ PseudoVSOXEI32_V_M1_MF4_MASK, VSOXEI32_V }, // 7932
|
|
{ PseudoVSOXEI32_V_M2_M1, VSOXEI32_V }, // 7933
|
|
{ PseudoVSOXEI32_V_M2_M1_MASK, VSOXEI32_V }, // 7934
|
|
{ PseudoVSOXEI32_V_M2_M2, VSOXEI32_V }, // 7935
|
|
{ PseudoVSOXEI32_V_M2_M2_MASK, VSOXEI32_V }, // 7936
|
|
{ PseudoVSOXEI32_V_M2_M4, VSOXEI32_V }, // 7937
|
|
{ PseudoVSOXEI32_V_M2_M4_MASK, VSOXEI32_V }, // 7938
|
|
{ PseudoVSOXEI32_V_M2_MF2, VSOXEI32_V }, // 7939
|
|
{ PseudoVSOXEI32_V_M2_MF2_MASK, VSOXEI32_V }, // 7940
|
|
{ PseudoVSOXEI32_V_M4_M1, VSOXEI32_V }, // 7941
|
|
{ PseudoVSOXEI32_V_M4_M1_MASK, VSOXEI32_V }, // 7942
|
|
{ PseudoVSOXEI32_V_M4_M2, VSOXEI32_V }, // 7943
|
|
{ PseudoVSOXEI32_V_M4_M2_MASK, VSOXEI32_V }, // 7944
|
|
{ PseudoVSOXEI32_V_M4_M4, VSOXEI32_V }, // 7945
|
|
{ PseudoVSOXEI32_V_M4_M4_MASK, VSOXEI32_V }, // 7946
|
|
{ PseudoVSOXEI32_V_M4_M8, VSOXEI32_V }, // 7947
|
|
{ PseudoVSOXEI32_V_M4_M8_MASK, VSOXEI32_V }, // 7948
|
|
{ PseudoVSOXEI32_V_M8_M2, VSOXEI32_V }, // 7949
|
|
{ PseudoVSOXEI32_V_M8_M2_MASK, VSOXEI32_V }, // 7950
|
|
{ PseudoVSOXEI32_V_M8_M4, VSOXEI32_V }, // 7951
|
|
{ PseudoVSOXEI32_V_M8_M4_MASK, VSOXEI32_V }, // 7952
|
|
{ PseudoVSOXEI32_V_M8_M8, VSOXEI32_V }, // 7953
|
|
{ PseudoVSOXEI32_V_M8_M8_MASK, VSOXEI32_V }, // 7954
|
|
{ PseudoVSOXEI32_V_MF2_M1, VSOXEI32_V }, // 7955
|
|
{ PseudoVSOXEI32_V_MF2_M1_MASK, VSOXEI32_V }, // 7956
|
|
{ PseudoVSOXEI32_V_MF2_MF2, VSOXEI32_V }, // 7957
|
|
{ PseudoVSOXEI32_V_MF2_MF2_MASK, VSOXEI32_V }, // 7958
|
|
{ PseudoVSOXEI32_V_MF2_MF4, VSOXEI32_V }, // 7959
|
|
{ PseudoVSOXEI32_V_MF2_MF4_MASK, VSOXEI32_V }, // 7960
|
|
{ PseudoVSOXEI32_V_MF2_MF8, VSOXEI32_V }, // 7961
|
|
{ PseudoVSOXEI32_V_MF2_MF8_MASK, VSOXEI32_V }, // 7962
|
|
{ PseudoVSOXEI64_V_M1_M1, VSOXEI64_V }, // 7963
|
|
{ PseudoVSOXEI64_V_M1_M1_MASK, VSOXEI64_V }, // 7964
|
|
{ PseudoVSOXEI64_V_M1_MF2, VSOXEI64_V }, // 7965
|
|
{ PseudoVSOXEI64_V_M1_MF2_MASK, VSOXEI64_V }, // 7966
|
|
{ PseudoVSOXEI64_V_M1_MF4, VSOXEI64_V }, // 7967
|
|
{ PseudoVSOXEI64_V_M1_MF4_MASK, VSOXEI64_V }, // 7968
|
|
{ PseudoVSOXEI64_V_M1_MF8, VSOXEI64_V }, // 7969
|
|
{ PseudoVSOXEI64_V_M1_MF8_MASK, VSOXEI64_V }, // 7970
|
|
{ PseudoVSOXEI64_V_M2_M1, VSOXEI64_V }, // 7971
|
|
{ PseudoVSOXEI64_V_M2_M1_MASK, VSOXEI64_V }, // 7972
|
|
{ PseudoVSOXEI64_V_M2_M2, VSOXEI64_V }, // 7973
|
|
{ PseudoVSOXEI64_V_M2_M2_MASK, VSOXEI64_V }, // 7974
|
|
{ PseudoVSOXEI64_V_M2_MF2, VSOXEI64_V }, // 7975
|
|
{ PseudoVSOXEI64_V_M2_MF2_MASK, VSOXEI64_V }, // 7976
|
|
{ PseudoVSOXEI64_V_M2_MF4, VSOXEI64_V }, // 7977
|
|
{ PseudoVSOXEI64_V_M2_MF4_MASK, VSOXEI64_V }, // 7978
|
|
{ PseudoVSOXEI64_V_M4_M1, VSOXEI64_V }, // 7979
|
|
{ PseudoVSOXEI64_V_M4_M1_MASK, VSOXEI64_V }, // 7980
|
|
{ PseudoVSOXEI64_V_M4_M2, VSOXEI64_V }, // 7981
|
|
{ PseudoVSOXEI64_V_M4_M2_MASK, VSOXEI64_V }, // 7982
|
|
{ PseudoVSOXEI64_V_M4_M4, VSOXEI64_V }, // 7983
|
|
{ PseudoVSOXEI64_V_M4_M4_MASK, VSOXEI64_V }, // 7984
|
|
{ PseudoVSOXEI64_V_M4_MF2, VSOXEI64_V }, // 7985
|
|
{ PseudoVSOXEI64_V_M4_MF2_MASK, VSOXEI64_V }, // 7986
|
|
{ PseudoVSOXEI64_V_M8_M1, VSOXEI64_V }, // 7987
|
|
{ PseudoVSOXEI64_V_M8_M1_MASK, VSOXEI64_V }, // 7988
|
|
{ PseudoVSOXEI64_V_M8_M2, VSOXEI64_V }, // 7989
|
|
{ PseudoVSOXEI64_V_M8_M2_MASK, VSOXEI64_V }, // 7990
|
|
{ PseudoVSOXEI64_V_M8_M4, VSOXEI64_V }, // 7991
|
|
{ PseudoVSOXEI64_V_M8_M4_MASK, VSOXEI64_V }, // 7992
|
|
{ PseudoVSOXEI64_V_M8_M8, VSOXEI64_V }, // 7993
|
|
{ PseudoVSOXEI64_V_M8_M8_MASK, VSOXEI64_V }, // 7994
|
|
{ PseudoVSOXEI8_V_M1_M1, VSOXEI8_V }, // 7995
|
|
{ PseudoVSOXEI8_V_M1_M1_MASK, VSOXEI8_V }, // 7996
|
|
{ PseudoVSOXEI8_V_M1_M2, VSOXEI8_V }, // 7997
|
|
{ PseudoVSOXEI8_V_M1_M2_MASK, VSOXEI8_V }, // 7998
|
|
{ PseudoVSOXEI8_V_M1_M4, VSOXEI8_V }, // 7999
|
|
{ PseudoVSOXEI8_V_M1_M4_MASK, VSOXEI8_V }, // 8000
|
|
{ PseudoVSOXEI8_V_M1_M8, VSOXEI8_V }, // 8001
|
|
{ PseudoVSOXEI8_V_M1_M8_MASK, VSOXEI8_V }, // 8002
|
|
{ PseudoVSOXEI8_V_M2_M2, VSOXEI8_V }, // 8003
|
|
{ PseudoVSOXEI8_V_M2_M2_MASK, VSOXEI8_V }, // 8004
|
|
{ PseudoVSOXEI8_V_M2_M4, VSOXEI8_V }, // 8005
|
|
{ PseudoVSOXEI8_V_M2_M4_MASK, VSOXEI8_V }, // 8006
|
|
{ PseudoVSOXEI8_V_M2_M8, VSOXEI8_V }, // 8007
|
|
{ PseudoVSOXEI8_V_M2_M8_MASK, VSOXEI8_V }, // 8008
|
|
{ PseudoVSOXEI8_V_M4_M4, VSOXEI8_V }, // 8009
|
|
{ PseudoVSOXEI8_V_M4_M4_MASK, VSOXEI8_V }, // 8010
|
|
{ PseudoVSOXEI8_V_M4_M8, VSOXEI8_V }, // 8011
|
|
{ PseudoVSOXEI8_V_M4_M8_MASK, VSOXEI8_V }, // 8012
|
|
{ PseudoVSOXEI8_V_M8_M8, VSOXEI8_V }, // 8013
|
|
{ PseudoVSOXEI8_V_M8_M8_MASK, VSOXEI8_V }, // 8014
|
|
{ PseudoVSOXEI8_V_MF2_M1, VSOXEI8_V }, // 8015
|
|
{ PseudoVSOXEI8_V_MF2_M1_MASK, VSOXEI8_V }, // 8016
|
|
{ PseudoVSOXEI8_V_MF2_M2, VSOXEI8_V }, // 8017
|
|
{ PseudoVSOXEI8_V_MF2_M2_MASK, VSOXEI8_V }, // 8018
|
|
{ PseudoVSOXEI8_V_MF2_M4, VSOXEI8_V }, // 8019
|
|
{ PseudoVSOXEI8_V_MF2_M4_MASK, VSOXEI8_V }, // 8020
|
|
{ PseudoVSOXEI8_V_MF2_MF2, VSOXEI8_V }, // 8021
|
|
{ PseudoVSOXEI8_V_MF2_MF2_MASK, VSOXEI8_V }, // 8022
|
|
{ PseudoVSOXEI8_V_MF4_M1, VSOXEI8_V }, // 8023
|
|
{ PseudoVSOXEI8_V_MF4_M1_MASK, VSOXEI8_V }, // 8024
|
|
{ PseudoVSOXEI8_V_MF4_M2, VSOXEI8_V }, // 8025
|
|
{ PseudoVSOXEI8_V_MF4_M2_MASK, VSOXEI8_V }, // 8026
|
|
{ PseudoVSOXEI8_V_MF4_MF2, VSOXEI8_V }, // 8027
|
|
{ PseudoVSOXEI8_V_MF4_MF2_MASK, VSOXEI8_V }, // 8028
|
|
{ PseudoVSOXEI8_V_MF4_MF4, VSOXEI8_V }, // 8029
|
|
{ PseudoVSOXEI8_V_MF4_MF4_MASK, VSOXEI8_V }, // 8030
|
|
{ PseudoVSOXEI8_V_MF8_M1, VSOXEI8_V }, // 8031
|
|
{ PseudoVSOXEI8_V_MF8_M1_MASK, VSOXEI8_V }, // 8032
|
|
{ PseudoVSOXEI8_V_MF8_MF2, VSOXEI8_V }, // 8033
|
|
{ PseudoVSOXEI8_V_MF8_MF2_MASK, VSOXEI8_V }, // 8034
|
|
{ PseudoVSOXEI8_V_MF8_MF4, VSOXEI8_V }, // 8035
|
|
{ PseudoVSOXEI8_V_MF8_MF4_MASK, VSOXEI8_V }, // 8036
|
|
{ PseudoVSOXEI8_V_MF8_MF8, VSOXEI8_V }, // 8037
|
|
{ PseudoVSOXEI8_V_MF8_MF8_MASK, VSOXEI8_V }, // 8038
|
|
{ PseudoVSOXSEG2EI16_V_M1_M1, VSOXSEG2EI16_V }, // 8039
|
|
{ PseudoVSOXSEG2EI16_V_M1_M1_MASK, VSOXSEG2EI16_V }, // 8040
|
|
{ PseudoVSOXSEG2EI16_V_M1_M2, VSOXSEG2EI16_V }, // 8041
|
|
{ PseudoVSOXSEG2EI16_V_M1_M2_MASK, VSOXSEG2EI16_V }, // 8042
|
|
{ PseudoVSOXSEG2EI16_V_M1_M4, VSOXSEG2EI16_V }, // 8043
|
|
{ PseudoVSOXSEG2EI16_V_M1_M4_MASK, VSOXSEG2EI16_V }, // 8044
|
|
{ PseudoVSOXSEG2EI16_V_M1_MF2, VSOXSEG2EI16_V }, // 8045
|
|
{ PseudoVSOXSEG2EI16_V_M1_MF2_MASK, VSOXSEG2EI16_V }, // 8046
|
|
{ PseudoVSOXSEG2EI16_V_M2_M1, VSOXSEG2EI16_V }, // 8047
|
|
{ PseudoVSOXSEG2EI16_V_M2_M1_MASK, VSOXSEG2EI16_V }, // 8048
|
|
{ PseudoVSOXSEG2EI16_V_M2_M2, VSOXSEG2EI16_V }, // 8049
|
|
{ PseudoVSOXSEG2EI16_V_M2_M2_MASK, VSOXSEG2EI16_V }, // 8050
|
|
{ PseudoVSOXSEG2EI16_V_M2_M4, VSOXSEG2EI16_V }, // 8051
|
|
{ PseudoVSOXSEG2EI16_V_M2_M4_MASK, VSOXSEG2EI16_V }, // 8052
|
|
{ PseudoVSOXSEG2EI16_V_M4_M2, VSOXSEG2EI16_V }, // 8053
|
|
{ PseudoVSOXSEG2EI16_V_M4_M2_MASK, VSOXSEG2EI16_V }, // 8054
|
|
{ PseudoVSOXSEG2EI16_V_M4_M4, VSOXSEG2EI16_V }, // 8055
|
|
{ PseudoVSOXSEG2EI16_V_M4_M4_MASK, VSOXSEG2EI16_V }, // 8056
|
|
{ PseudoVSOXSEG2EI16_V_M8_M4, VSOXSEG2EI16_V }, // 8057
|
|
{ PseudoVSOXSEG2EI16_V_M8_M4_MASK, VSOXSEG2EI16_V }, // 8058
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M1, VSOXSEG2EI16_V }, // 8059
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M1_MASK, VSOXSEG2EI16_V }, // 8060
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M2, VSOXSEG2EI16_V }, // 8061
|
|
{ PseudoVSOXSEG2EI16_V_MF2_M2_MASK, VSOXSEG2EI16_V }, // 8062
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF2, VSOXSEG2EI16_V }, // 8063
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, VSOXSEG2EI16_V }, // 8064
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF4, VSOXSEG2EI16_V }, // 8065
|
|
{ PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, VSOXSEG2EI16_V }, // 8066
|
|
{ PseudoVSOXSEG2EI16_V_MF4_M1, VSOXSEG2EI16_V }, // 8067
|
|
{ PseudoVSOXSEG2EI16_V_MF4_M1_MASK, VSOXSEG2EI16_V }, // 8068
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF2, VSOXSEG2EI16_V }, // 8069
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, VSOXSEG2EI16_V }, // 8070
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF4, VSOXSEG2EI16_V }, // 8071
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, VSOXSEG2EI16_V }, // 8072
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF8, VSOXSEG2EI16_V }, // 8073
|
|
{ PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, VSOXSEG2EI16_V }, // 8074
|
|
{ PseudoVSOXSEG2EI32_V_M1_M1, VSOXSEG2EI32_V }, // 8075
|
|
{ PseudoVSOXSEG2EI32_V_M1_M1_MASK, VSOXSEG2EI32_V }, // 8076
|
|
{ PseudoVSOXSEG2EI32_V_M1_M2, VSOXSEG2EI32_V }, // 8077
|
|
{ PseudoVSOXSEG2EI32_V_M1_M2_MASK, VSOXSEG2EI32_V }, // 8078
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF2, VSOXSEG2EI32_V }, // 8079
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF2_MASK, VSOXSEG2EI32_V }, // 8080
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF4, VSOXSEG2EI32_V }, // 8081
|
|
{ PseudoVSOXSEG2EI32_V_M1_MF4_MASK, VSOXSEG2EI32_V }, // 8082
|
|
{ PseudoVSOXSEG2EI32_V_M2_M1, VSOXSEG2EI32_V }, // 8083
|
|
{ PseudoVSOXSEG2EI32_V_M2_M1_MASK, VSOXSEG2EI32_V }, // 8084
|
|
{ PseudoVSOXSEG2EI32_V_M2_M2, VSOXSEG2EI32_V }, // 8085
|
|
{ PseudoVSOXSEG2EI32_V_M2_M2_MASK, VSOXSEG2EI32_V }, // 8086
|
|
{ PseudoVSOXSEG2EI32_V_M2_M4, VSOXSEG2EI32_V }, // 8087
|
|
{ PseudoVSOXSEG2EI32_V_M2_M4_MASK, VSOXSEG2EI32_V }, // 8088
|
|
{ PseudoVSOXSEG2EI32_V_M2_MF2, VSOXSEG2EI32_V }, // 8089
|
|
{ PseudoVSOXSEG2EI32_V_M2_MF2_MASK, VSOXSEG2EI32_V }, // 8090
|
|
{ PseudoVSOXSEG2EI32_V_M4_M1, VSOXSEG2EI32_V }, // 8091
|
|
{ PseudoVSOXSEG2EI32_V_M4_M1_MASK, VSOXSEG2EI32_V }, // 8092
|
|
{ PseudoVSOXSEG2EI32_V_M4_M2, VSOXSEG2EI32_V }, // 8093
|
|
{ PseudoVSOXSEG2EI32_V_M4_M2_MASK, VSOXSEG2EI32_V }, // 8094
|
|
{ PseudoVSOXSEG2EI32_V_M4_M4, VSOXSEG2EI32_V }, // 8095
|
|
{ PseudoVSOXSEG2EI32_V_M4_M4_MASK, VSOXSEG2EI32_V }, // 8096
|
|
{ PseudoVSOXSEG2EI32_V_M8_M2, VSOXSEG2EI32_V }, // 8097
|
|
{ PseudoVSOXSEG2EI32_V_M8_M2_MASK, VSOXSEG2EI32_V }, // 8098
|
|
{ PseudoVSOXSEG2EI32_V_M8_M4, VSOXSEG2EI32_V }, // 8099
|
|
{ PseudoVSOXSEG2EI32_V_M8_M4_MASK, VSOXSEG2EI32_V }, // 8100
|
|
{ PseudoVSOXSEG2EI32_V_MF2_M1, VSOXSEG2EI32_V }, // 8101
|
|
{ PseudoVSOXSEG2EI32_V_MF2_M1_MASK, VSOXSEG2EI32_V }, // 8102
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF2, VSOXSEG2EI32_V }, // 8103
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, VSOXSEG2EI32_V }, // 8104
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF4, VSOXSEG2EI32_V }, // 8105
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, VSOXSEG2EI32_V }, // 8106
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF8, VSOXSEG2EI32_V }, // 8107
|
|
{ PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, VSOXSEG2EI32_V }, // 8108
|
|
{ PseudoVSOXSEG2EI64_V_M1_M1, VSOXSEG2EI64_V }, // 8109
|
|
{ PseudoVSOXSEG2EI64_V_M1_M1_MASK, VSOXSEG2EI64_V }, // 8110
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF2, VSOXSEG2EI64_V }, // 8111
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF2_MASK, VSOXSEG2EI64_V }, // 8112
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF4, VSOXSEG2EI64_V }, // 8113
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF4_MASK, VSOXSEG2EI64_V }, // 8114
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF8, VSOXSEG2EI64_V }, // 8115
|
|
{ PseudoVSOXSEG2EI64_V_M1_MF8_MASK, VSOXSEG2EI64_V }, // 8116
|
|
{ PseudoVSOXSEG2EI64_V_M2_M1, VSOXSEG2EI64_V }, // 8117
|
|
{ PseudoVSOXSEG2EI64_V_M2_M1_MASK, VSOXSEG2EI64_V }, // 8118
|
|
{ PseudoVSOXSEG2EI64_V_M2_M2, VSOXSEG2EI64_V }, // 8119
|
|
{ PseudoVSOXSEG2EI64_V_M2_M2_MASK, VSOXSEG2EI64_V }, // 8120
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF2, VSOXSEG2EI64_V }, // 8121
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF2_MASK, VSOXSEG2EI64_V }, // 8122
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF4, VSOXSEG2EI64_V }, // 8123
|
|
{ PseudoVSOXSEG2EI64_V_M2_MF4_MASK, VSOXSEG2EI64_V }, // 8124
|
|
{ PseudoVSOXSEG2EI64_V_M4_M1, VSOXSEG2EI64_V }, // 8125
|
|
{ PseudoVSOXSEG2EI64_V_M4_M1_MASK, VSOXSEG2EI64_V }, // 8126
|
|
{ PseudoVSOXSEG2EI64_V_M4_M2, VSOXSEG2EI64_V }, // 8127
|
|
{ PseudoVSOXSEG2EI64_V_M4_M2_MASK, VSOXSEG2EI64_V }, // 8128
|
|
{ PseudoVSOXSEG2EI64_V_M4_M4, VSOXSEG2EI64_V }, // 8129
|
|
{ PseudoVSOXSEG2EI64_V_M4_M4_MASK, VSOXSEG2EI64_V }, // 8130
|
|
{ PseudoVSOXSEG2EI64_V_M4_MF2, VSOXSEG2EI64_V }, // 8131
|
|
{ PseudoVSOXSEG2EI64_V_M4_MF2_MASK, VSOXSEG2EI64_V }, // 8132
|
|
{ PseudoVSOXSEG2EI64_V_M8_M1, VSOXSEG2EI64_V }, // 8133
|
|
{ PseudoVSOXSEG2EI64_V_M8_M1_MASK, VSOXSEG2EI64_V }, // 8134
|
|
{ PseudoVSOXSEG2EI64_V_M8_M2, VSOXSEG2EI64_V }, // 8135
|
|
{ PseudoVSOXSEG2EI64_V_M8_M2_MASK, VSOXSEG2EI64_V }, // 8136
|
|
{ PseudoVSOXSEG2EI64_V_M8_M4, VSOXSEG2EI64_V }, // 8137
|
|
{ PseudoVSOXSEG2EI64_V_M8_M4_MASK, VSOXSEG2EI64_V }, // 8138
|
|
{ PseudoVSOXSEG2EI8_V_M1_M1, VSOXSEG2EI8_V }, // 8139
|
|
{ PseudoVSOXSEG2EI8_V_M1_M1_MASK, VSOXSEG2EI8_V }, // 8140
|
|
{ PseudoVSOXSEG2EI8_V_M1_M2, VSOXSEG2EI8_V }, // 8141
|
|
{ PseudoVSOXSEG2EI8_V_M1_M2_MASK, VSOXSEG2EI8_V }, // 8142
|
|
{ PseudoVSOXSEG2EI8_V_M1_M4, VSOXSEG2EI8_V }, // 8143
|
|
{ PseudoVSOXSEG2EI8_V_M1_M4_MASK, VSOXSEG2EI8_V }, // 8144
|
|
{ PseudoVSOXSEG2EI8_V_M2_M2, VSOXSEG2EI8_V }, // 8145
|
|
{ PseudoVSOXSEG2EI8_V_M2_M2_MASK, VSOXSEG2EI8_V }, // 8146
|
|
{ PseudoVSOXSEG2EI8_V_M2_M4, VSOXSEG2EI8_V }, // 8147
|
|
{ PseudoVSOXSEG2EI8_V_M2_M4_MASK, VSOXSEG2EI8_V }, // 8148
|
|
{ PseudoVSOXSEG2EI8_V_M4_M4, VSOXSEG2EI8_V }, // 8149
|
|
{ PseudoVSOXSEG2EI8_V_M4_M4_MASK, VSOXSEG2EI8_V }, // 8150
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M1, VSOXSEG2EI8_V }, // 8151
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M1_MASK, VSOXSEG2EI8_V }, // 8152
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M2, VSOXSEG2EI8_V }, // 8153
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M2_MASK, VSOXSEG2EI8_V }, // 8154
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M4, VSOXSEG2EI8_V }, // 8155
|
|
{ PseudoVSOXSEG2EI8_V_MF2_M4_MASK, VSOXSEG2EI8_V }, // 8156
|
|
{ PseudoVSOXSEG2EI8_V_MF2_MF2, VSOXSEG2EI8_V }, // 8157
|
|
{ PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, VSOXSEG2EI8_V }, // 8158
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M1, VSOXSEG2EI8_V }, // 8159
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M1_MASK, VSOXSEG2EI8_V }, // 8160
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M2, VSOXSEG2EI8_V }, // 8161
|
|
{ PseudoVSOXSEG2EI8_V_MF4_M2_MASK, VSOXSEG2EI8_V }, // 8162
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF2, VSOXSEG2EI8_V }, // 8163
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, VSOXSEG2EI8_V }, // 8164
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF4, VSOXSEG2EI8_V }, // 8165
|
|
{ PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, VSOXSEG2EI8_V }, // 8166
|
|
{ PseudoVSOXSEG2EI8_V_MF8_M1, VSOXSEG2EI8_V }, // 8167
|
|
{ PseudoVSOXSEG2EI8_V_MF8_M1_MASK, VSOXSEG2EI8_V }, // 8168
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF2, VSOXSEG2EI8_V }, // 8169
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, VSOXSEG2EI8_V }, // 8170
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF4, VSOXSEG2EI8_V }, // 8171
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, VSOXSEG2EI8_V }, // 8172
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF8, VSOXSEG2EI8_V }, // 8173
|
|
{ PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, VSOXSEG2EI8_V }, // 8174
|
|
{ PseudoVSOXSEG3EI16_V_M1_M1, VSOXSEG3EI16_V }, // 8175
|
|
{ PseudoVSOXSEG3EI16_V_M1_M1_MASK, VSOXSEG3EI16_V }, // 8176
|
|
{ PseudoVSOXSEG3EI16_V_M1_M2, VSOXSEG3EI16_V }, // 8177
|
|
{ PseudoVSOXSEG3EI16_V_M1_M2_MASK, VSOXSEG3EI16_V }, // 8178
|
|
{ PseudoVSOXSEG3EI16_V_M1_MF2, VSOXSEG3EI16_V }, // 8179
|
|
{ PseudoVSOXSEG3EI16_V_M1_MF2_MASK, VSOXSEG3EI16_V }, // 8180
|
|
{ PseudoVSOXSEG3EI16_V_M2_M1, VSOXSEG3EI16_V }, // 8181
|
|
{ PseudoVSOXSEG3EI16_V_M2_M1_MASK, VSOXSEG3EI16_V }, // 8182
|
|
{ PseudoVSOXSEG3EI16_V_M2_M2, VSOXSEG3EI16_V }, // 8183
|
|
{ PseudoVSOXSEG3EI16_V_M2_M2_MASK, VSOXSEG3EI16_V }, // 8184
|
|
{ PseudoVSOXSEG3EI16_V_M4_M2, VSOXSEG3EI16_V }, // 8185
|
|
{ PseudoVSOXSEG3EI16_V_M4_M2_MASK, VSOXSEG3EI16_V }, // 8186
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M1, VSOXSEG3EI16_V }, // 8187
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M1_MASK, VSOXSEG3EI16_V }, // 8188
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M2, VSOXSEG3EI16_V }, // 8189
|
|
{ PseudoVSOXSEG3EI16_V_MF2_M2_MASK, VSOXSEG3EI16_V }, // 8190
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF2, VSOXSEG3EI16_V }, // 8191
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, VSOXSEG3EI16_V }, // 8192
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF4, VSOXSEG3EI16_V }, // 8193
|
|
{ PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, VSOXSEG3EI16_V }, // 8194
|
|
{ PseudoVSOXSEG3EI16_V_MF4_M1, VSOXSEG3EI16_V }, // 8195
|
|
{ PseudoVSOXSEG3EI16_V_MF4_M1_MASK, VSOXSEG3EI16_V }, // 8196
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF2, VSOXSEG3EI16_V }, // 8197
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, VSOXSEG3EI16_V }, // 8198
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF4, VSOXSEG3EI16_V }, // 8199
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, VSOXSEG3EI16_V }, // 8200
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF8, VSOXSEG3EI16_V }, // 8201
|
|
{ PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, VSOXSEG3EI16_V }, // 8202
|
|
{ PseudoVSOXSEG3EI32_V_M1_M1, VSOXSEG3EI32_V }, // 8203
|
|
{ PseudoVSOXSEG3EI32_V_M1_M1_MASK, VSOXSEG3EI32_V }, // 8204
|
|
{ PseudoVSOXSEG3EI32_V_M1_M2, VSOXSEG3EI32_V }, // 8205
|
|
{ PseudoVSOXSEG3EI32_V_M1_M2_MASK, VSOXSEG3EI32_V }, // 8206
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF2, VSOXSEG3EI32_V }, // 8207
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF2_MASK, VSOXSEG3EI32_V }, // 8208
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF4, VSOXSEG3EI32_V }, // 8209
|
|
{ PseudoVSOXSEG3EI32_V_M1_MF4_MASK, VSOXSEG3EI32_V }, // 8210
|
|
{ PseudoVSOXSEG3EI32_V_M2_M1, VSOXSEG3EI32_V }, // 8211
|
|
{ PseudoVSOXSEG3EI32_V_M2_M1_MASK, VSOXSEG3EI32_V }, // 8212
|
|
{ PseudoVSOXSEG3EI32_V_M2_M2, VSOXSEG3EI32_V }, // 8213
|
|
{ PseudoVSOXSEG3EI32_V_M2_M2_MASK, VSOXSEG3EI32_V }, // 8214
|
|
{ PseudoVSOXSEG3EI32_V_M2_MF2, VSOXSEG3EI32_V }, // 8215
|
|
{ PseudoVSOXSEG3EI32_V_M2_MF2_MASK, VSOXSEG3EI32_V }, // 8216
|
|
{ PseudoVSOXSEG3EI32_V_M4_M1, VSOXSEG3EI32_V }, // 8217
|
|
{ PseudoVSOXSEG3EI32_V_M4_M1_MASK, VSOXSEG3EI32_V }, // 8218
|
|
{ PseudoVSOXSEG3EI32_V_M4_M2, VSOXSEG3EI32_V }, // 8219
|
|
{ PseudoVSOXSEG3EI32_V_M4_M2_MASK, VSOXSEG3EI32_V }, // 8220
|
|
{ PseudoVSOXSEG3EI32_V_M8_M2, VSOXSEG3EI32_V }, // 8221
|
|
{ PseudoVSOXSEG3EI32_V_M8_M2_MASK, VSOXSEG3EI32_V }, // 8222
|
|
{ PseudoVSOXSEG3EI32_V_MF2_M1, VSOXSEG3EI32_V }, // 8223
|
|
{ PseudoVSOXSEG3EI32_V_MF2_M1_MASK, VSOXSEG3EI32_V }, // 8224
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF2, VSOXSEG3EI32_V }, // 8225
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, VSOXSEG3EI32_V }, // 8226
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF4, VSOXSEG3EI32_V }, // 8227
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, VSOXSEG3EI32_V }, // 8228
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF8, VSOXSEG3EI32_V }, // 8229
|
|
{ PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, VSOXSEG3EI32_V }, // 8230
|
|
{ PseudoVSOXSEG3EI64_V_M1_M1, VSOXSEG3EI64_V }, // 8231
|
|
{ PseudoVSOXSEG3EI64_V_M1_M1_MASK, VSOXSEG3EI64_V }, // 8232
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF2, VSOXSEG3EI64_V }, // 8233
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF2_MASK, VSOXSEG3EI64_V }, // 8234
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF4, VSOXSEG3EI64_V }, // 8235
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF4_MASK, VSOXSEG3EI64_V }, // 8236
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF8, VSOXSEG3EI64_V }, // 8237
|
|
{ PseudoVSOXSEG3EI64_V_M1_MF8_MASK, VSOXSEG3EI64_V }, // 8238
|
|
{ PseudoVSOXSEG3EI64_V_M2_M1, VSOXSEG3EI64_V }, // 8239
|
|
{ PseudoVSOXSEG3EI64_V_M2_M1_MASK, VSOXSEG3EI64_V }, // 8240
|
|
{ PseudoVSOXSEG3EI64_V_M2_M2, VSOXSEG3EI64_V }, // 8241
|
|
{ PseudoVSOXSEG3EI64_V_M2_M2_MASK, VSOXSEG3EI64_V }, // 8242
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF2, VSOXSEG3EI64_V }, // 8243
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF2_MASK, VSOXSEG3EI64_V }, // 8244
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF4, VSOXSEG3EI64_V }, // 8245
|
|
{ PseudoVSOXSEG3EI64_V_M2_MF4_MASK, VSOXSEG3EI64_V }, // 8246
|
|
{ PseudoVSOXSEG3EI64_V_M4_M1, VSOXSEG3EI64_V }, // 8247
|
|
{ PseudoVSOXSEG3EI64_V_M4_M1_MASK, VSOXSEG3EI64_V }, // 8248
|
|
{ PseudoVSOXSEG3EI64_V_M4_M2, VSOXSEG3EI64_V }, // 8249
|
|
{ PseudoVSOXSEG3EI64_V_M4_M2_MASK, VSOXSEG3EI64_V }, // 8250
|
|
{ PseudoVSOXSEG3EI64_V_M4_MF2, VSOXSEG3EI64_V }, // 8251
|
|
{ PseudoVSOXSEG3EI64_V_M4_MF2_MASK, VSOXSEG3EI64_V }, // 8252
|
|
{ PseudoVSOXSEG3EI64_V_M8_M1, VSOXSEG3EI64_V }, // 8253
|
|
{ PseudoVSOXSEG3EI64_V_M8_M1_MASK, VSOXSEG3EI64_V }, // 8254
|
|
{ PseudoVSOXSEG3EI64_V_M8_M2, VSOXSEG3EI64_V }, // 8255
|
|
{ PseudoVSOXSEG3EI64_V_M8_M2_MASK, VSOXSEG3EI64_V }, // 8256
|
|
{ PseudoVSOXSEG3EI8_V_M1_M1, VSOXSEG3EI8_V }, // 8257
|
|
{ PseudoVSOXSEG3EI8_V_M1_M1_MASK, VSOXSEG3EI8_V }, // 8258
|
|
{ PseudoVSOXSEG3EI8_V_M1_M2, VSOXSEG3EI8_V }, // 8259
|
|
{ PseudoVSOXSEG3EI8_V_M1_M2_MASK, VSOXSEG3EI8_V }, // 8260
|
|
{ PseudoVSOXSEG3EI8_V_M2_M2, VSOXSEG3EI8_V }, // 8261
|
|
{ PseudoVSOXSEG3EI8_V_M2_M2_MASK, VSOXSEG3EI8_V }, // 8262
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M1, VSOXSEG3EI8_V }, // 8263
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M1_MASK, VSOXSEG3EI8_V }, // 8264
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M2, VSOXSEG3EI8_V }, // 8265
|
|
{ PseudoVSOXSEG3EI8_V_MF2_M2_MASK, VSOXSEG3EI8_V }, // 8266
|
|
{ PseudoVSOXSEG3EI8_V_MF2_MF2, VSOXSEG3EI8_V }, // 8267
|
|
{ PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, VSOXSEG3EI8_V }, // 8268
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M1, VSOXSEG3EI8_V }, // 8269
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M1_MASK, VSOXSEG3EI8_V }, // 8270
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M2, VSOXSEG3EI8_V }, // 8271
|
|
{ PseudoVSOXSEG3EI8_V_MF4_M2_MASK, VSOXSEG3EI8_V }, // 8272
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF2, VSOXSEG3EI8_V }, // 8273
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, VSOXSEG3EI8_V }, // 8274
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF4, VSOXSEG3EI8_V }, // 8275
|
|
{ PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, VSOXSEG3EI8_V }, // 8276
|
|
{ PseudoVSOXSEG3EI8_V_MF8_M1, VSOXSEG3EI8_V }, // 8277
|
|
{ PseudoVSOXSEG3EI8_V_MF8_M1_MASK, VSOXSEG3EI8_V }, // 8278
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF2, VSOXSEG3EI8_V }, // 8279
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, VSOXSEG3EI8_V }, // 8280
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF4, VSOXSEG3EI8_V }, // 8281
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, VSOXSEG3EI8_V }, // 8282
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF8, VSOXSEG3EI8_V }, // 8283
|
|
{ PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, VSOXSEG3EI8_V }, // 8284
|
|
{ PseudoVSOXSEG4EI16_V_M1_M1, VSOXSEG4EI16_V }, // 8285
|
|
{ PseudoVSOXSEG4EI16_V_M1_M1_MASK, VSOXSEG4EI16_V }, // 8286
|
|
{ PseudoVSOXSEG4EI16_V_M1_M2, VSOXSEG4EI16_V }, // 8287
|
|
{ PseudoVSOXSEG4EI16_V_M1_M2_MASK, VSOXSEG4EI16_V }, // 8288
|
|
{ PseudoVSOXSEG4EI16_V_M1_MF2, VSOXSEG4EI16_V }, // 8289
|
|
{ PseudoVSOXSEG4EI16_V_M1_MF2_MASK, VSOXSEG4EI16_V }, // 8290
|
|
{ PseudoVSOXSEG4EI16_V_M2_M1, VSOXSEG4EI16_V }, // 8291
|
|
{ PseudoVSOXSEG4EI16_V_M2_M1_MASK, VSOXSEG4EI16_V }, // 8292
|
|
{ PseudoVSOXSEG4EI16_V_M2_M2, VSOXSEG4EI16_V }, // 8293
|
|
{ PseudoVSOXSEG4EI16_V_M2_M2_MASK, VSOXSEG4EI16_V }, // 8294
|
|
{ PseudoVSOXSEG4EI16_V_M4_M2, VSOXSEG4EI16_V }, // 8295
|
|
{ PseudoVSOXSEG4EI16_V_M4_M2_MASK, VSOXSEG4EI16_V }, // 8296
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M1, VSOXSEG4EI16_V }, // 8297
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M1_MASK, VSOXSEG4EI16_V }, // 8298
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M2, VSOXSEG4EI16_V }, // 8299
|
|
{ PseudoVSOXSEG4EI16_V_MF2_M2_MASK, VSOXSEG4EI16_V }, // 8300
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF2, VSOXSEG4EI16_V }, // 8301
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, VSOXSEG4EI16_V }, // 8302
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF4, VSOXSEG4EI16_V }, // 8303
|
|
{ PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, VSOXSEG4EI16_V }, // 8304
|
|
{ PseudoVSOXSEG4EI16_V_MF4_M1, VSOXSEG4EI16_V }, // 8305
|
|
{ PseudoVSOXSEG4EI16_V_MF4_M1_MASK, VSOXSEG4EI16_V }, // 8306
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF2, VSOXSEG4EI16_V }, // 8307
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, VSOXSEG4EI16_V }, // 8308
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF4, VSOXSEG4EI16_V }, // 8309
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, VSOXSEG4EI16_V }, // 8310
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF8, VSOXSEG4EI16_V }, // 8311
|
|
{ PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, VSOXSEG4EI16_V }, // 8312
|
|
{ PseudoVSOXSEG4EI32_V_M1_M1, VSOXSEG4EI32_V }, // 8313
|
|
{ PseudoVSOXSEG4EI32_V_M1_M1_MASK, VSOXSEG4EI32_V }, // 8314
|
|
{ PseudoVSOXSEG4EI32_V_M1_M2, VSOXSEG4EI32_V }, // 8315
|
|
{ PseudoVSOXSEG4EI32_V_M1_M2_MASK, VSOXSEG4EI32_V }, // 8316
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF2, VSOXSEG4EI32_V }, // 8317
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF2_MASK, VSOXSEG4EI32_V }, // 8318
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF4, VSOXSEG4EI32_V }, // 8319
|
|
{ PseudoVSOXSEG4EI32_V_M1_MF4_MASK, VSOXSEG4EI32_V }, // 8320
|
|
{ PseudoVSOXSEG4EI32_V_M2_M1, VSOXSEG4EI32_V }, // 8321
|
|
{ PseudoVSOXSEG4EI32_V_M2_M1_MASK, VSOXSEG4EI32_V }, // 8322
|
|
{ PseudoVSOXSEG4EI32_V_M2_M2, VSOXSEG4EI32_V }, // 8323
|
|
{ PseudoVSOXSEG4EI32_V_M2_M2_MASK, VSOXSEG4EI32_V }, // 8324
|
|
{ PseudoVSOXSEG4EI32_V_M2_MF2, VSOXSEG4EI32_V }, // 8325
|
|
{ PseudoVSOXSEG4EI32_V_M2_MF2_MASK, VSOXSEG4EI32_V }, // 8326
|
|
{ PseudoVSOXSEG4EI32_V_M4_M1, VSOXSEG4EI32_V }, // 8327
|
|
{ PseudoVSOXSEG4EI32_V_M4_M1_MASK, VSOXSEG4EI32_V }, // 8328
|
|
{ PseudoVSOXSEG4EI32_V_M4_M2, VSOXSEG4EI32_V }, // 8329
|
|
{ PseudoVSOXSEG4EI32_V_M4_M2_MASK, VSOXSEG4EI32_V }, // 8330
|
|
{ PseudoVSOXSEG4EI32_V_M8_M2, VSOXSEG4EI32_V }, // 8331
|
|
{ PseudoVSOXSEG4EI32_V_M8_M2_MASK, VSOXSEG4EI32_V }, // 8332
|
|
{ PseudoVSOXSEG4EI32_V_MF2_M1, VSOXSEG4EI32_V }, // 8333
|
|
{ PseudoVSOXSEG4EI32_V_MF2_M1_MASK, VSOXSEG4EI32_V }, // 8334
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF2, VSOXSEG4EI32_V }, // 8335
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, VSOXSEG4EI32_V }, // 8336
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF4, VSOXSEG4EI32_V }, // 8337
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, VSOXSEG4EI32_V }, // 8338
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF8, VSOXSEG4EI32_V }, // 8339
|
|
{ PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, VSOXSEG4EI32_V }, // 8340
|
|
{ PseudoVSOXSEG4EI64_V_M1_M1, VSOXSEG4EI64_V }, // 8341
|
|
{ PseudoVSOXSEG4EI64_V_M1_M1_MASK, VSOXSEG4EI64_V }, // 8342
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF2, VSOXSEG4EI64_V }, // 8343
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF2_MASK, VSOXSEG4EI64_V }, // 8344
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF4, VSOXSEG4EI64_V }, // 8345
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF4_MASK, VSOXSEG4EI64_V }, // 8346
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF8, VSOXSEG4EI64_V }, // 8347
|
|
{ PseudoVSOXSEG4EI64_V_M1_MF8_MASK, VSOXSEG4EI64_V }, // 8348
|
|
{ PseudoVSOXSEG4EI64_V_M2_M1, VSOXSEG4EI64_V }, // 8349
|
|
{ PseudoVSOXSEG4EI64_V_M2_M1_MASK, VSOXSEG4EI64_V }, // 8350
|
|
{ PseudoVSOXSEG4EI64_V_M2_M2, VSOXSEG4EI64_V }, // 8351
|
|
{ PseudoVSOXSEG4EI64_V_M2_M2_MASK, VSOXSEG4EI64_V }, // 8352
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF2, VSOXSEG4EI64_V }, // 8353
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF2_MASK, VSOXSEG4EI64_V }, // 8354
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF4, VSOXSEG4EI64_V }, // 8355
|
|
{ PseudoVSOXSEG4EI64_V_M2_MF4_MASK, VSOXSEG4EI64_V }, // 8356
|
|
{ PseudoVSOXSEG4EI64_V_M4_M1, VSOXSEG4EI64_V }, // 8357
|
|
{ PseudoVSOXSEG4EI64_V_M4_M1_MASK, VSOXSEG4EI64_V }, // 8358
|
|
{ PseudoVSOXSEG4EI64_V_M4_M2, VSOXSEG4EI64_V }, // 8359
|
|
{ PseudoVSOXSEG4EI64_V_M4_M2_MASK, VSOXSEG4EI64_V }, // 8360
|
|
{ PseudoVSOXSEG4EI64_V_M4_MF2, VSOXSEG4EI64_V }, // 8361
|
|
{ PseudoVSOXSEG4EI64_V_M4_MF2_MASK, VSOXSEG4EI64_V }, // 8362
|
|
{ PseudoVSOXSEG4EI64_V_M8_M1, VSOXSEG4EI64_V }, // 8363
|
|
{ PseudoVSOXSEG4EI64_V_M8_M1_MASK, VSOXSEG4EI64_V }, // 8364
|
|
{ PseudoVSOXSEG4EI64_V_M8_M2, VSOXSEG4EI64_V }, // 8365
|
|
{ PseudoVSOXSEG4EI64_V_M8_M2_MASK, VSOXSEG4EI64_V }, // 8366
|
|
{ PseudoVSOXSEG4EI8_V_M1_M1, VSOXSEG4EI8_V }, // 8367
|
|
{ PseudoVSOXSEG4EI8_V_M1_M1_MASK, VSOXSEG4EI8_V }, // 8368
|
|
{ PseudoVSOXSEG4EI8_V_M1_M2, VSOXSEG4EI8_V }, // 8369
|
|
{ PseudoVSOXSEG4EI8_V_M1_M2_MASK, VSOXSEG4EI8_V }, // 8370
|
|
{ PseudoVSOXSEG4EI8_V_M2_M2, VSOXSEG4EI8_V }, // 8371
|
|
{ PseudoVSOXSEG4EI8_V_M2_M2_MASK, VSOXSEG4EI8_V }, // 8372
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M1, VSOXSEG4EI8_V }, // 8373
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M1_MASK, VSOXSEG4EI8_V }, // 8374
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M2, VSOXSEG4EI8_V }, // 8375
|
|
{ PseudoVSOXSEG4EI8_V_MF2_M2_MASK, VSOXSEG4EI8_V }, // 8376
|
|
{ PseudoVSOXSEG4EI8_V_MF2_MF2, VSOXSEG4EI8_V }, // 8377
|
|
{ PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, VSOXSEG4EI8_V }, // 8378
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M1, VSOXSEG4EI8_V }, // 8379
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M1_MASK, VSOXSEG4EI8_V }, // 8380
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M2, VSOXSEG4EI8_V }, // 8381
|
|
{ PseudoVSOXSEG4EI8_V_MF4_M2_MASK, VSOXSEG4EI8_V }, // 8382
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF2, VSOXSEG4EI8_V }, // 8383
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, VSOXSEG4EI8_V }, // 8384
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF4, VSOXSEG4EI8_V }, // 8385
|
|
{ PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, VSOXSEG4EI8_V }, // 8386
|
|
{ PseudoVSOXSEG4EI8_V_MF8_M1, VSOXSEG4EI8_V }, // 8387
|
|
{ PseudoVSOXSEG4EI8_V_MF8_M1_MASK, VSOXSEG4EI8_V }, // 8388
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF2, VSOXSEG4EI8_V }, // 8389
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, VSOXSEG4EI8_V }, // 8390
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF4, VSOXSEG4EI8_V }, // 8391
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, VSOXSEG4EI8_V }, // 8392
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF8, VSOXSEG4EI8_V }, // 8393
|
|
{ PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, VSOXSEG4EI8_V }, // 8394
|
|
{ PseudoVSOXSEG5EI16_V_M1_M1, VSOXSEG5EI16_V }, // 8395
|
|
{ PseudoVSOXSEG5EI16_V_M1_M1_MASK, VSOXSEG5EI16_V }, // 8396
|
|
{ PseudoVSOXSEG5EI16_V_M1_MF2, VSOXSEG5EI16_V }, // 8397
|
|
{ PseudoVSOXSEG5EI16_V_M1_MF2_MASK, VSOXSEG5EI16_V }, // 8398
|
|
{ PseudoVSOXSEG5EI16_V_M2_M1, VSOXSEG5EI16_V }, // 8399
|
|
{ PseudoVSOXSEG5EI16_V_M2_M1_MASK, VSOXSEG5EI16_V }, // 8400
|
|
{ PseudoVSOXSEG5EI16_V_MF2_M1, VSOXSEG5EI16_V }, // 8401
|
|
{ PseudoVSOXSEG5EI16_V_MF2_M1_MASK, VSOXSEG5EI16_V }, // 8402
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF2, VSOXSEG5EI16_V }, // 8403
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, VSOXSEG5EI16_V }, // 8404
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF4, VSOXSEG5EI16_V }, // 8405
|
|
{ PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, VSOXSEG5EI16_V }, // 8406
|
|
{ PseudoVSOXSEG5EI16_V_MF4_M1, VSOXSEG5EI16_V }, // 8407
|
|
{ PseudoVSOXSEG5EI16_V_MF4_M1_MASK, VSOXSEG5EI16_V }, // 8408
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF2, VSOXSEG5EI16_V }, // 8409
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, VSOXSEG5EI16_V }, // 8410
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF4, VSOXSEG5EI16_V }, // 8411
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, VSOXSEG5EI16_V }, // 8412
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF8, VSOXSEG5EI16_V }, // 8413
|
|
{ PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, VSOXSEG5EI16_V }, // 8414
|
|
{ PseudoVSOXSEG5EI32_V_M1_M1, VSOXSEG5EI32_V }, // 8415
|
|
{ PseudoVSOXSEG5EI32_V_M1_M1_MASK, VSOXSEG5EI32_V }, // 8416
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF2, VSOXSEG5EI32_V }, // 8417
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF2_MASK, VSOXSEG5EI32_V }, // 8418
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF4, VSOXSEG5EI32_V }, // 8419
|
|
{ PseudoVSOXSEG5EI32_V_M1_MF4_MASK, VSOXSEG5EI32_V }, // 8420
|
|
{ PseudoVSOXSEG5EI32_V_M2_M1, VSOXSEG5EI32_V }, // 8421
|
|
{ PseudoVSOXSEG5EI32_V_M2_M1_MASK, VSOXSEG5EI32_V }, // 8422
|
|
{ PseudoVSOXSEG5EI32_V_M2_MF2, VSOXSEG5EI32_V }, // 8423
|
|
{ PseudoVSOXSEG5EI32_V_M2_MF2_MASK, VSOXSEG5EI32_V }, // 8424
|
|
{ PseudoVSOXSEG5EI32_V_M4_M1, VSOXSEG5EI32_V }, // 8425
|
|
{ PseudoVSOXSEG5EI32_V_M4_M1_MASK, VSOXSEG5EI32_V }, // 8426
|
|
{ PseudoVSOXSEG5EI32_V_MF2_M1, VSOXSEG5EI32_V }, // 8427
|
|
{ PseudoVSOXSEG5EI32_V_MF2_M1_MASK, VSOXSEG5EI32_V }, // 8428
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF2, VSOXSEG5EI32_V }, // 8429
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, VSOXSEG5EI32_V }, // 8430
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF4, VSOXSEG5EI32_V }, // 8431
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, VSOXSEG5EI32_V }, // 8432
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF8, VSOXSEG5EI32_V }, // 8433
|
|
{ PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, VSOXSEG5EI32_V }, // 8434
|
|
{ PseudoVSOXSEG5EI64_V_M1_M1, VSOXSEG5EI64_V }, // 8435
|
|
{ PseudoVSOXSEG5EI64_V_M1_M1_MASK, VSOXSEG5EI64_V }, // 8436
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF2, VSOXSEG5EI64_V }, // 8437
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF2_MASK, VSOXSEG5EI64_V }, // 8438
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF4, VSOXSEG5EI64_V }, // 8439
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF4_MASK, VSOXSEG5EI64_V }, // 8440
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF8, VSOXSEG5EI64_V }, // 8441
|
|
{ PseudoVSOXSEG5EI64_V_M1_MF8_MASK, VSOXSEG5EI64_V }, // 8442
|
|
{ PseudoVSOXSEG5EI64_V_M2_M1, VSOXSEG5EI64_V }, // 8443
|
|
{ PseudoVSOXSEG5EI64_V_M2_M1_MASK, VSOXSEG5EI64_V }, // 8444
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF2, VSOXSEG5EI64_V }, // 8445
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF2_MASK, VSOXSEG5EI64_V }, // 8446
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF4, VSOXSEG5EI64_V }, // 8447
|
|
{ PseudoVSOXSEG5EI64_V_M2_MF4_MASK, VSOXSEG5EI64_V }, // 8448
|
|
{ PseudoVSOXSEG5EI64_V_M4_M1, VSOXSEG5EI64_V }, // 8449
|
|
{ PseudoVSOXSEG5EI64_V_M4_M1_MASK, VSOXSEG5EI64_V }, // 8450
|
|
{ PseudoVSOXSEG5EI64_V_M4_MF2, VSOXSEG5EI64_V }, // 8451
|
|
{ PseudoVSOXSEG5EI64_V_M4_MF2_MASK, VSOXSEG5EI64_V }, // 8452
|
|
{ PseudoVSOXSEG5EI64_V_M8_M1, VSOXSEG5EI64_V }, // 8453
|
|
{ PseudoVSOXSEG5EI64_V_M8_M1_MASK, VSOXSEG5EI64_V }, // 8454
|
|
{ PseudoVSOXSEG5EI8_V_M1_M1, VSOXSEG5EI8_V }, // 8455
|
|
{ PseudoVSOXSEG5EI8_V_M1_M1_MASK, VSOXSEG5EI8_V }, // 8456
|
|
{ PseudoVSOXSEG5EI8_V_MF2_M1, VSOXSEG5EI8_V }, // 8457
|
|
{ PseudoVSOXSEG5EI8_V_MF2_M1_MASK, VSOXSEG5EI8_V }, // 8458
|
|
{ PseudoVSOXSEG5EI8_V_MF2_MF2, VSOXSEG5EI8_V }, // 8459
|
|
{ PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, VSOXSEG5EI8_V }, // 8460
|
|
{ PseudoVSOXSEG5EI8_V_MF4_M1, VSOXSEG5EI8_V }, // 8461
|
|
{ PseudoVSOXSEG5EI8_V_MF4_M1_MASK, VSOXSEG5EI8_V }, // 8462
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF2, VSOXSEG5EI8_V }, // 8463
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, VSOXSEG5EI8_V }, // 8464
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF4, VSOXSEG5EI8_V }, // 8465
|
|
{ PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, VSOXSEG5EI8_V }, // 8466
|
|
{ PseudoVSOXSEG5EI8_V_MF8_M1, VSOXSEG5EI8_V }, // 8467
|
|
{ PseudoVSOXSEG5EI8_V_MF8_M1_MASK, VSOXSEG5EI8_V }, // 8468
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF2, VSOXSEG5EI8_V }, // 8469
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, VSOXSEG5EI8_V }, // 8470
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF4, VSOXSEG5EI8_V }, // 8471
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, VSOXSEG5EI8_V }, // 8472
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF8, VSOXSEG5EI8_V }, // 8473
|
|
{ PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, VSOXSEG5EI8_V }, // 8474
|
|
{ PseudoVSOXSEG6EI16_V_M1_M1, VSOXSEG6EI16_V }, // 8475
|
|
{ PseudoVSOXSEG6EI16_V_M1_M1_MASK, VSOXSEG6EI16_V }, // 8476
|
|
{ PseudoVSOXSEG6EI16_V_M1_MF2, VSOXSEG6EI16_V }, // 8477
|
|
{ PseudoVSOXSEG6EI16_V_M1_MF2_MASK, VSOXSEG6EI16_V }, // 8478
|
|
{ PseudoVSOXSEG6EI16_V_M2_M1, VSOXSEG6EI16_V }, // 8479
|
|
{ PseudoVSOXSEG6EI16_V_M2_M1_MASK, VSOXSEG6EI16_V }, // 8480
|
|
{ PseudoVSOXSEG6EI16_V_MF2_M1, VSOXSEG6EI16_V }, // 8481
|
|
{ PseudoVSOXSEG6EI16_V_MF2_M1_MASK, VSOXSEG6EI16_V }, // 8482
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF2, VSOXSEG6EI16_V }, // 8483
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, VSOXSEG6EI16_V }, // 8484
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF4, VSOXSEG6EI16_V }, // 8485
|
|
{ PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, VSOXSEG6EI16_V }, // 8486
|
|
{ PseudoVSOXSEG6EI16_V_MF4_M1, VSOXSEG6EI16_V }, // 8487
|
|
{ PseudoVSOXSEG6EI16_V_MF4_M1_MASK, VSOXSEG6EI16_V }, // 8488
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF2, VSOXSEG6EI16_V }, // 8489
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, VSOXSEG6EI16_V }, // 8490
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF4, VSOXSEG6EI16_V }, // 8491
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, VSOXSEG6EI16_V }, // 8492
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF8, VSOXSEG6EI16_V }, // 8493
|
|
{ PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, VSOXSEG6EI16_V }, // 8494
|
|
{ PseudoVSOXSEG6EI32_V_M1_M1, VSOXSEG6EI32_V }, // 8495
|
|
{ PseudoVSOXSEG6EI32_V_M1_M1_MASK, VSOXSEG6EI32_V }, // 8496
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF2, VSOXSEG6EI32_V }, // 8497
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF2_MASK, VSOXSEG6EI32_V }, // 8498
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF4, VSOXSEG6EI32_V }, // 8499
|
|
{ PseudoVSOXSEG6EI32_V_M1_MF4_MASK, VSOXSEG6EI32_V }, // 8500
|
|
{ PseudoVSOXSEG6EI32_V_M2_M1, VSOXSEG6EI32_V }, // 8501
|
|
{ PseudoVSOXSEG6EI32_V_M2_M1_MASK, VSOXSEG6EI32_V }, // 8502
|
|
{ PseudoVSOXSEG6EI32_V_M2_MF2, VSOXSEG6EI32_V }, // 8503
|
|
{ PseudoVSOXSEG6EI32_V_M2_MF2_MASK, VSOXSEG6EI32_V }, // 8504
|
|
{ PseudoVSOXSEG6EI32_V_M4_M1, VSOXSEG6EI32_V }, // 8505
|
|
{ PseudoVSOXSEG6EI32_V_M4_M1_MASK, VSOXSEG6EI32_V }, // 8506
|
|
{ PseudoVSOXSEG6EI32_V_MF2_M1, VSOXSEG6EI32_V }, // 8507
|
|
{ PseudoVSOXSEG6EI32_V_MF2_M1_MASK, VSOXSEG6EI32_V }, // 8508
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF2, VSOXSEG6EI32_V }, // 8509
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, VSOXSEG6EI32_V }, // 8510
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF4, VSOXSEG6EI32_V }, // 8511
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, VSOXSEG6EI32_V }, // 8512
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF8, VSOXSEG6EI32_V }, // 8513
|
|
{ PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, VSOXSEG6EI32_V }, // 8514
|
|
{ PseudoVSOXSEG6EI64_V_M1_M1, VSOXSEG6EI64_V }, // 8515
|
|
{ PseudoVSOXSEG6EI64_V_M1_M1_MASK, VSOXSEG6EI64_V }, // 8516
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF2, VSOXSEG6EI64_V }, // 8517
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF2_MASK, VSOXSEG6EI64_V }, // 8518
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF4, VSOXSEG6EI64_V }, // 8519
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF4_MASK, VSOXSEG6EI64_V }, // 8520
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF8, VSOXSEG6EI64_V }, // 8521
|
|
{ PseudoVSOXSEG6EI64_V_M1_MF8_MASK, VSOXSEG6EI64_V }, // 8522
|
|
{ PseudoVSOXSEG6EI64_V_M2_M1, VSOXSEG6EI64_V }, // 8523
|
|
{ PseudoVSOXSEG6EI64_V_M2_M1_MASK, VSOXSEG6EI64_V }, // 8524
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF2, VSOXSEG6EI64_V }, // 8525
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF2_MASK, VSOXSEG6EI64_V }, // 8526
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF4, VSOXSEG6EI64_V }, // 8527
|
|
{ PseudoVSOXSEG6EI64_V_M2_MF4_MASK, VSOXSEG6EI64_V }, // 8528
|
|
{ PseudoVSOXSEG6EI64_V_M4_M1, VSOXSEG6EI64_V }, // 8529
|
|
{ PseudoVSOXSEG6EI64_V_M4_M1_MASK, VSOXSEG6EI64_V }, // 8530
|
|
{ PseudoVSOXSEG6EI64_V_M4_MF2, VSOXSEG6EI64_V }, // 8531
|
|
{ PseudoVSOXSEG6EI64_V_M4_MF2_MASK, VSOXSEG6EI64_V }, // 8532
|
|
{ PseudoVSOXSEG6EI64_V_M8_M1, VSOXSEG6EI64_V }, // 8533
|
|
{ PseudoVSOXSEG6EI64_V_M8_M1_MASK, VSOXSEG6EI64_V }, // 8534
|
|
{ PseudoVSOXSEG6EI8_V_M1_M1, VSOXSEG6EI8_V }, // 8535
|
|
{ PseudoVSOXSEG6EI8_V_M1_M1_MASK, VSOXSEG6EI8_V }, // 8536
|
|
{ PseudoVSOXSEG6EI8_V_MF2_M1, VSOXSEG6EI8_V }, // 8537
|
|
{ PseudoVSOXSEG6EI8_V_MF2_M1_MASK, VSOXSEG6EI8_V }, // 8538
|
|
{ PseudoVSOXSEG6EI8_V_MF2_MF2, VSOXSEG6EI8_V }, // 8539
|
|
{ PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, VSOXSEG6EI8_V }, // 8540
|
|
{ PseudoVSOXSEG6EI8_V_MF4_M1, VSOXSEG6EI8_V }, // 8541
|
|
{ PseudoVSOXSEG6EI8_V_MF4_M1_MASK, VSOXSEG6EI8_V }, // 8542
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF2, VSOXSEG6EI8_V }, // 8543
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, VSOXSEG6EI8_V }, // 8544
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF4, VSOXSEG6EI8_V }, // 8545
|
|
{ PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, VSOXSEG6EI8_V }, // 8546
|
|
{ PseudoVSOXSEG6EI8_V_MF8_M1, VSOXSEG6EI8_V }, // 8547
|
|
{ PseudoVSOXSEG6EI8_V_MF8_M1_MASK, VSOXSEG6EI8_V }, // 8548
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF2, VSOXSEG6EI8_V }, // 8549
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, VSOXSEG6EI8_V }, // 8550
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF4, VSOXSEG6EI8_V }, // 8551
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, VSOXSEG6EI8_V }, // 8552
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF8, VSOXSEG6EI8_V }, // 8553
|
|
{ PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, VSOXSEG6EI8_V }, // 8554
|
|
{ PseudoVSOXSEG7EI16_V_M1_M1, VSOXSEG7EI16_V }, // 8555
|
|
{ PseudoVSOXSEG7EI16_V_M1_M1_MASK, VSOXSEG7EI16_V }, // 8556
|
|
{ PseudoVSOXSEG7EI16_V_M1_MF2, VSOXSEG7EI16_V }, // 8557
|
|
{ PseudoVSOXSEG7EI16_V_M1_MF2_MASK, VSOXSEG7EI16_V }, // 8558
|
|
{ PseudoVSOXSEG7EI16_V_M2_M1, VSOXSEG7EI16_V }, // 8559
|
|
{ PseudoVSOXSEG7EI16_V_M2_M1_MASK, VSOXSEG7EI16_V }, // 8560
|
|
{ PseudoVSOXSEG7EI16_V_MF2_M1, VSOXSEG7EI16_V }, // 8561
|
|
{ PseudoVSOXSEG7EI16_V_MF2_M1_MASK, VSOXSEG7EI16_V }, // 8562
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF2, VSOXSEG7EI16_V }, // 8563
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, VSOXSEG7EI16_V }, // 8564
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF4, VSOXSEG7EI16_V }, // 8565
|
|
{ PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, VSOXSEG7EI16_V }, // 8566
|
|
{ PseudoVSOXSEG7EI16_V_MF4_M1, VSOXSEG7EI16_V }, // 8567
|
|
{ PseudoVSOXSEG7EI16_V_MF4_M1_MASK, VSOXSEG7EI16_V }, // 8568
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF2, VSOXSEG7EI16_V }, // 8569
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, VSOXSEG7EI16_V }, // 8570
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF4, VSOXSEG7EI16_V }, // 8571
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, VSOXSEG7EI16_V }, // 8572
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF8, VSOXSEG7EI16_V }, // 8573
|
|
{ PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, VSOXSEG7EI16_V }, // 8574
|
|
{ PseudoVSOXSEG7EI32_V_M1_M1, VSOXSEG7EI32_V }, // 8575
|
|
{ PseudoVSOXSEG7EI32_V_M1_M1_MASK, VSOXSEG7EI32_V }, // 8576
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF2, VSOXSEG7EI32_V }, // 8577
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF2_MASK, VSOXSEG7EI32_V }, // 8578
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF4, VSOXSEG7EI32_V }, // 8579
|
|
{ PseudoVSOXSEG7EI32_V_M1_MF4_MASK, VSOXSEG7EI32_V }, // 8580
|
|
{ PseudoVSOXSEG7EI32_V_M2_M1, VSOXSEG7EI32_V }, // 8581
|
|
{ PseudoVSOXSEG7EI32_V_M2_M1_MASK, VSOXSEG7EI32_V }, // 8582
|
|
{ PseudoVSOXSEG7EI32_V_M2_MF2, VSOXSEG7EI32_V }, // 8583
|
|
{ PseudoVSOXSEG7EI32_V_M2_MF2_MASK, VSOXSEG7EI32_V }, // 8584
|
|
{ PseudoVSOXSEG7EI32_V_M4_M1, VSOXSEG7EI32_V }, // 8585
|
|
{ PseudoVSOXSEG7EI32_V_M4_M1_MASK, VSOXSEG7EI32_V }, // 8586
|
|
{ PseudoVSOXSEG7EI32_V_MF2_M1, VSOXSEG7EI32_V }, // 8587
|
|
{ PseudoVSOXSEG7EI32_V_MF2_M1_MASK, VSOXSEG7EI32_V }, // 8588
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF2, VSOXSEG7EI32_V }, // 8589
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, VSOXSEG7EI32_V }, // 8590
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF4, VSOXSEG7EI32_V }, // 8591
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, VSOXSEG7EI32_V }, // 8592
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF8, VSOXSEG7EI32_V }, // 8593
|
|
{ PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, VSOXSEG7EI32_V }, // 8594
|
|
{ PseudoVSOXSEG7EI64_V_M1_M1, VSOXSEG7EI64_V }, // 8595
|
|
{ PseudoVSOXSEG7EI64_V_M1_M1_MASK, VSOXSEG7EI64_V }, // 8596
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF2, VSOXSEG7EI64_V }, // 8597
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF2_MASK, VSOXSEG7EI64_V }, // 8598
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF4, VSOXSEG7EI64_V }, // 8599
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF4_MASK, VSOXSEG7EI64_V }, // 8600
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF8, VSOXSEG7EI64_V }, // 8601
|
|
{ PseudoVSOXSEG7EI64_V_M1_MF8_MASK, VSOXSEG7EI64_V }, // 8602
|
|
{ PseudoVSOXSEG7EI64_V_M2_M1, VSOXSEG7EI64_V }, // 8603
|
|
{ PseudoVSOXSEG7EI64_V_M2_M1_MASK, VSOXSEG7EI64_V }, // 8604
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF2, VSOXSEG7EI64_V }, // 8605
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF2_MASK, VSOXSEG7EI64_V }, // 8606
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF4, VSOXSEG7EI64_V }, // 8607
|
|
{ PseudoVSOXSEG7EI64_V_M2_MF4_MASK, VSOXSEG7EI64_V }, // 8608
|
|
{ PseudoVSOXSEG7EI64_V_M4_M1, VSOXSEG7EI64_V }, // 8609
|
|
{ PseudoVSOXSEG7EI64_V_M4_M1_MASK, VSOXSEG7EI64_V }, // 8610
|
|
{ PseudoVSOXSEG7EI64_V_M4_MF2, VSOXSEG7EI64_V }, // 8611
|
|
{ PseudoVSOXSEG7EI64_V_M4_MF2_MASK, VSOXSEG7EI64_V }, // 8612
|
|
{ PseudoVSOXSEG7EI64_V_M8_M1, VSOXSEG7EI64_V }, // 8613
|
|
{ PseudoVSOXSEG7EI64_V_M8_M1_MASK, VSOXSEG7EI64_V }, // 8614
|
|
{ PseudoVSOXSEG7EI8_V_M1_M1, VSOXSEG7EI8_V }, // 8615
|
|
{ PseudoVSOXSEG7EI8_V_M1_M1_MASK, VSOXSEG7EI8_V }, // 8616
|
|
{ PseudoVSOXSEG7EI8_V_MF2_M1, VSOXSEG7EI8_V }, // 8617
|
|
{ PseudoVSOXSEG7EI8_V_MF2_M1_MASK, VSOXSEG7EI8_V }, // 8618
|
|
{ PseudoVSOXSEG7EI8_V_MF2_MF2, VSOXSEG7EI8_V }, // 8619
|
|
{ PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, VSOXSEG7EI8_V }, // 8620
|
|
{ PseudoVSOXSEG7EI8_V_MF4_M1, VSOXSEG7EI8_V }, // 8621
|
|
{ PseudoVSOXSEG7EI8_V_MF4_M1_MASK, VSOXSEG7EI8_V }, // 8622
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF2, VSOXSEG7EI8_V }, // 8623
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, VSOXSEG7EI8_V }, // 8624
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF4, VSOXSEG7EI8_V }, // 8625
|
|
{ PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, VSOXSEG7EI8_V }, // 8626
|
|
{ PseudoVSOXSEG7EI8_V_MF8_M1, VSOXSEG7EI8_V }, // 8627
|
|
{ PseudoVSOXSEG7EI8_V_MF8_M1_MASK, VSOXSEG7EI8_V }, // 8628
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF2, VSOXSEG7EI8_V }, // 8629
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, VSOXSEG7EI8_V }, // 8630
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF4, VSOXSEG7EI8_V }, // 8631
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, VSOXSEG7EI8_V }, // 8632
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF8, VSOXSEG7EI8_V }, // 8633
|
|
{ PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, VSOXSEG7EI8_V }, // 8634
|
|
{ PseudoVSOXSEG8EI16_V_M1_M1, VSOXSEG8EI16_V }, // 8635
|
|
{ PseudoVSOXSEG8EI16_V_M1_M1_MASK, VSOXSEG8EI16_V }, // 8636
|
|
{ PseudoVSOXSEG8EI16_V_M1_MF2, VSOXSEG8EI16_V }, // 8637
|
|
{ PseudoVSOXSEG8EI16_V_M1_MF2_MASK, VSOXSEG8EI16_V }, // 8638
|
|
{ PseudoVSOXSEG8EI16_V_M2_M1, VSOXSEG8EI16_V }, // 8639
|
|
{ PseudoVSOXSEG8EI16_V_M2_M1_MASK, VSOXSEG8EI16_V }, // 8640
|
|
{ PseudoVSOXSEG8EI16_V_MF2_M1, VSOXSEG8EI16_V }, // 8641
|
|
{ PseudoVSOXSEG8EI16_V_MF2_M1_MASK, VSOXSEG8EI16_V }, // 8642
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF2, VSOXSEG8EI16_V }, // 8643
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, VSOXSEG8EI16_V }, // 8644
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF4, VSOXSEG8EI16_V }, // 8645
|
|
{ PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, VSOXSEG8EI16_V }, // 8646
|
|
{ PseudoVSOXSEG8EI16_V_MF4_M1, VSOXSEG8EI16_V }, // 8647
|
|
{ PseudoVSOXSEG8EI16_V_MF4_M1_MASK, VSOXSEG8EI16_V }, // 8648
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF2, VSOXSEG8EI16_V }, // 8649
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, VSOXSEG8EI16_V }, // 8650
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF4, VSOXSEG8EI16_V }, // 8651
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, VSOXSEG8EI16_V }, // 8652
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF8, VSOXSEG8EI16_V }, // 8653
|
|
{ PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, VSOXSEG8EI16_V }, // 8654
|
|
{ PseudoVSOXSEG8EI32_V_M1_M1, VSOXSEG8EI32_V }, // 8655
|
|
{ PseudoVSOXSEG8EI32_V_M1_M1_MASK, VSOXSEG8EI32_V }, // 8656
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF2, VSOXSEG8EI32_V }, // 8657
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF2_MASK, VSOXSEG8EI32_V }, // 8658
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF4, VSOXSEG8EI32_V }, // 8659
|
|
{ PseudoVSOXSEG8EI32_V_M1_MF4_MASK, VSOXSEG8EI32_V }, // 8660
|
|
{ PseudoVSOXSEG8EI32_V_M2_M1, VSOXSEG8EI32_V }, // 8661
|
|
{ PseudoVSOXSEG8EI32_V_M2_M1_MASK, VSOXSEG8EI32_V }, // 8662
|
|
{ PseudoVSOXSEG8EI32_V_M2_MF2, VSOXSEG8EI32_V }, // 8663
|
|
{ PseudoVSOXSEG8EI32_V_M2_MF2_MASK, VSOXSEG8EI32_V }, // 8664
|
|
{ PseudoVSOXSEG8EI32_V_M4_M1, VSOXSEG8EI32_V }, // 8665
|
|
{ PseudoVSOXSEG8EI32_V_M4_M1_MASK, VSOXSEG8EI32_V }, // 8666
|
|
{ PseudoVSOXSEG8EI32_V_MF2_M1, VSOXSEG8EI32_V }, // 8667
|
|
{ PseudoVSOXSEG8EI32_V_MF2_M1_MASK, VSOXSEG8EI32_V }, // 8668
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF2, VSOXSEG8EI32_V }, // 8669
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, VSOXSEG8EI32_V }, // 8670
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF4, VSOXSEG8EI32_V }, // 8671
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, VSOXSEG8EI32_V }, // 8672
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF8, VSOXSEG8EI32_V }, // 8673
|
|
{ PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, VSOXSEG8EI32_V }, // 8674
|
|
{ PseudoVSOXSEG8EI64_V_M1_M1, VSOXSEG8EI64_V }, // 8675
|
|
{ PseudoVSOXSEG8EI64_V_M1_M1_MASK, VSOXSEG8EI64_V }, // 8676
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF2, VSOXSEG8EI64_V }, // 8677
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF2_MASK, VSOXSEG8EI64_V }, // 8678
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF4, VSOXSEG8EI64_V }, // 8679
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF4_MASK, VSOXSEG8EI64_V }, // 8680
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF8, VSOXSEG8EI64_V }, // 8681
|
|
{ PseudoVSOXSEG8EI64_V_M1_MF8_MASK, VSOXSEG8EI64_V }, // 8682
|
|
{ PseudoVSOXSEG8EI64_V_M2_M1, VSOXSEG8EI64_V }, // 8683
|
|
{ PseudoVSOXSEG8EI64_V_M2_M1_MASK, VSOXSEG8EI64_V }, // 8684
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF2, VSOXSEG8EI64_V }, // 8685
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF2_MASK, VSOXSEG8EI64_V }, // 8686
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF4, VSOXSEG8EI64_V }, // 8687
|
|
{ PseudoVSOXSEG8EI64_V_M2_MF4_MASK, VSOXSEG8EI64_V }, // 8688
|
|
{ PseudoVSOXSEG8EI64_V_M4_M1, VSOXSEG8EI64_V }, // 8689
|
|
{ PseudoVSOXSEG8EI64_V_M4_M1_MASK, VSOXSEG8EI64_V }, // 8690
|
|
{ PseudoVSOXSEG8EI64_V_M4_MF2, VSOXSEG8EI64_V }, // 8691
|
|
{ PseudoVSOXSEG8EI64_V_M4_MF2_MASK, VSOXSEG8EI64_V }, // 8692
|
|
{ PseudoVSOXSEG8EI64_V_M8_M1, VSOXSEG8EI64_V }, // 8693
|
|
{ PseudoVSOXSEG8EI64_V_M8_M1_MASK, VSOXSEG8EI64_V }, // 8694
|
|
{ PseudoVSOXSEG8EI8_V_M1_M1, VSOXSEG8EI8_V }, // 8695
|
|
{ PseudoVSOXSEG8EI8_V_M1_M1_MASK, VSOXSEG8EI8_V }, // 8696
|
|
{ PseudoVSOXSEG8EI8_V_MF2_M1, VSOXSEG8EI8_V }, // 8697
|
|
{ PseudoVSOXSEG8EI8_V_MF2_M1_MASK, VSOXSEG8EI8_V }, // 8698
|
|
{ PseudoVSOXSEG8EI8_V_MF2_MF2, VSOXSEG8EI8_V }, // 8699
|
|
{ PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, VSOXSEG8EI8_V }, // 8700
|
|
{ PseudoVSOXSEG8EI8_V_MF4_M1, VSOXSEG8EI8_V }, // 8701
|
|
{ PseudoVSOXSEG8EI8_V_MF4_M1_MASK, VSOXSEG8EI8_V }, // 8702
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF2, VSOXSEG8EI8_V }, // 8703
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, VSOXSEG8EI8_V }, // 8704
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF4, VSOXSEG8EI8_V }, // 8705
|
|
{ PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, VSOXSEG8EI8_V }, // 8706
|
|
{ PseudoVSOXSEG8EI8_V_MF8_M1, VSOXSEG8EI8_V }, // 8707
|
|
{ PseudoVSOXSEG8EI8_V_MF8_M1_MASK, VSOXSEG8EI8_V }, // 8708
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF2, VSOXSEG8EI8_V }, // 8709
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, VSOXSEG8EI8_V }, // 8710
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF4, VSOXSEG8EI8_V }, // 8711
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, VSOXSEG8EI8_V }, // 8712
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF8, VSOXSEG8EI8_V }, // 8713
|
|
{ PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, VSOXSEG8EI8_V }, // 8714
|
|
{ PseudoVSRA_VI_M1, VSRA_VI }, // 8715
|
|
{ PseudoVSRA_VI_M1_MASK, VSRA_VI }, // 8716
|
|
{ PseudoVSRA_VI_M2, VSRA_VI }, // 8717
|
|
{ PseudoVSRA_VI_M2_MASK, VSRA_VI }, // 8718
|
|
{ PseudoVSRA_VI_M4, VSRA_VI }, // 8719
|
|
{ PseudoVSRA_VI_M4_MASK, VSRA_VI }, // 8720
|
|
{ PseudoVSRA_VI_M8, VSRA_VI }, // 8721
|
|
{ PseudoVSRA_VI_M8_MASK, VSRA_VI }, // 8722
|
|
{ PseudoVSRA_VI_MF2, VSRA_VI }, // 8723
|
|
{ PseudoVSRA_VI_MF2_MASK, VSRA_VI }, // 8724
|
|
{ PseudoVSRA_VI_MF4, VSRA_VI }, // 8725
|
|
{ PseudoVSRA_VI_MF4_MASK, VSRA_VI }, // 8726
|
|
{ PseudoVSRA_VI_MF8, VSRA_VI }, // 8727
|
|
{ PseudoVSRA_VI_MF8_MASK, VSRA_VI }, // 8728
|
|
{ PseudoVSRA_VV_M1, VSRA_VV }, // 8729
|
|
{ PseudoVSRA_VV_M1_MASK, VSRA_VV }, // 8730
|
|
{ PseudoVSRA_VV_M2, VSRA_VV }, // 8731
|
|
{ PseudoVSRA_VV_M2_MASK, VSRA_VV }, // 8732
|
|
{ PseudoVSRA_VV_M4, VSRA_VV }, // 8733
|
|
{ PseudoVSRA_VV_M4_MASK, VSRA_VV }, // 8734
|
|
{ PseudoVSRA_VV_M8, VSRA_VV }, // 8735
|
|
{ PseudoVSRA_VV_M8_MASK, VSRA_VV }, // 8736
|
|
{ PseudoVSRA_VV_MF2, VSRA_VV }, // 8737
|
|
{ PseudoVSRA_VV_MF2_MASK, VSRA_VV }, // 8738
|
|
{ PseudoVSRA_VV_MF4, VSRA_VV }, // 8739
|
|
{ PseudoVSRA_VV_MF4_MASK, VSRA_VV }, // 8740
|
|
{ PseudoVSRA_VV_MF8, VSRA_VV }, // 8741
|
|
{ PseudoVSRA_VV_MF8_MASK, VSRA_VV }, // 8742
|
|
{ PseudoVSRA_VX_M1, VSRA_VX }, // 8743
|
|
{ PseudoVSRA_VX_M1_MASK, VSRA_VX }, // 8744
|
|
{ PseudoVSRA_VX_M2, VSRA_VX }, // 8745
|
|
{ PseudoVSRA_VX_M2_MASK, VSRA_VX }, // 8746
|
|
{ PseudoVSRA_VX_M4, VSRA_VX }, // 8747
|
|
{ PseudoVSRA_VX_M4_MASK, VSRA_VX }, // 8748
|
|
{ PseudoVSRA_VX_M8, VSRA_VX }, // 8749
|
|
{ PseudoVSRA_VX_M8_MASK, VSRA_VX }, // 8750
|
|
{ PseudoVSRA_VX_MF2, VSRA_VX }, // 8751
|
|
{ PseudoVSRA_VX_MF2_MASK, VSRA_VX }, // 8752
|
|
{ PseudoVSRA_VX_MF4, VSRA_VX }, // 8753
|
|
{ PseudoVSRA_VX_MF4_MASK, VSRA_VX }, // 8754
|
|
{ PseudoVSRA_VX_MF8, VSRA_VX }, // 8755
|
|
{ PseudoVSRA_VX_MF8_MASK, VSRA_VX }, // 8756
|
|
{ PseudoVSRL_VI_M1, VSRL_VI }, // 8757
|
|
{ PseudoVSRL_VI_M1_MASK, VSRL_VI }, // 8758
|
|
{ PseudoVSRL_VI_M2, VSRL_VI }, // 8759
|
|
{ PseudoVSRL_VI_M2_MASK, VSRL_VI }, // 8760
|
|
{ PseudoVSRL_VI_M4, VSRL_VI }, // 8761
|
|
{ PseudoVSRL_VI_M4_MASK, VSRL_VI }, // 8762
|
|
{ PseudoVSRL_VI_M8, VSRL_VI }, // 8763
|
|
{ PseudoVSRL_VI_M8_MASK, VSRL_VI }, // 8764
|
|
{ PseudoVSRL_VI_MF2, VSRL_VI }, // 8765
|
|
{ PseudoVSRL_VI_MF2_MASK, VSRL_VI }, // 8766
|
|
{ PseudoVSRL_VI_MF4, VSRL_VI }, // 8767
|
|
{ PseudoVSRL_VI_MF4_MASK, VSRL_VI }, // 8768
|
|
{ PseudoVSRL_VI_MF8, VSRL_VI }, // 8769
|
|
{ PseudoVSRL_VI_MF8_MASK, VSRL_VI }, // 8770
|
|
{ PseudoVSRL_VV_M1, VSRL_VV }, // 8771
|
|
{ PseudoVSRL_VV_M1_MASK, VSRL_VV }, // 8772
|
|
{ PseudoVSRL_VV_M2, VSRL_VV }, // 8773
|
|
{ PseudoVSRL_VV_M2_MASK, VSRL_VV }, // 8774
|
|
{ PseudoVSRL_VV_M4, VSRL_VV }, // 8775
|
|
{ PseudoVSRL_VV_M4_MASK, VSRL_VV }, // 8776
|
|
{ PseudoVSRL_VV_M8, VSRL_VV }, // 8777
|
|
{ PseudoVSRL_VV_M8_MASK, VSRL_VV }, // 8778
|
|
{ PseudoVSRL_VV_MF2, VSRL_VV }, // 8779
|
|
{ PseudoVSRL_VV_MF2_MASK, VSRL_VV }, // 8780
|
|
{ PseudoVSRL_VV_MF4, VSRL_VV }, // 8781
|
|
{ PseudoVSRL_VV_MF4_MASK, VSRL_VV }, // 8782
|
|
{ PseudoVSRL_VV_MF8, VSRL_VV }, // 8783
|
|
{ PseudoVSRL_VV_MF8_MASK, VSRL_VV }, // 8784
|
|
{ PseudoVSRL_VX_M1, VSRL_VX }, // 8785
|
|
{ PseudoVSRL_VX_M1_MASK, VSRL_VX }, // 8786
|
|
{ PseudoVSRL_VX_M2, VSRL_VX }, // 8787
|
|
{ PseudoVSRL_VX_M2_MASK, VSRL_VX }, // 8788
|
|
{ PseudoVSRL_VX_M4, VSRL_VX }, // 8789
|
|
{ PseudoVSRL_VX_M4_MASK, VSRL_VX }, // 8790
|
|
{ PseudoVSRL_VX_M8, VSRL_VX }, // 8791
|
|
{ PseudoVSRL_VX_M8_MASK, VSRL_VX }, // 8792
|
|
{ PseudoVSRL_VX_MF2, VSRL_VX }, // 8793
|
|
{ PseudoVSRL_VX_MF2_MASK, VSRL_VX }, // 8794
|
|
{ PseudoVSRL_VX_MF4, VSRL_VX }, // 8795
|
|
{ PseudoVSRL_VX_MF4_MASK, VSRL_VX }, // 8796
|
|
{ PseudoVSRL_VX_MF8, VSRL_VX }, // 8797
|
|
{ PseudoVSRL_VX_MF8_MASK, VSRL_VX }, // 8798
|
|
{ PseudoVSSE16_V_M1, VSSE16_V }, // 8799
|
|
{ PseudoVSSE16_V_M1_MASK, VSSE16_V }, // 8800
|
|
{ PseudoVSSE16_V_M2, VSSE16_V }, // 8801
|
|
{ PseudoVSSE16_V_M2_MASK, VSSE16_V }, // 8802
|
|
{ PseudoVSSE16_V_M4, VSSE16_V }, // 8803
|
|
{ PseudoVSSE16_V_M4_MASK, VSSE16_V }, // 8804
|
|
{ PseudoVSSE16_V_M8, VSSE16_V }, // 8805
|
|
{ PseudoVSSE16_V_M8_MASK, VSSE16_V }, // 8806
|
|
{ PseudoVSSE16_V_MF2, VSSE16_V }, // 8807
|
|
{ PseudoVSSE16_V_MF2_MASK, VSSE16_V }, // 8808
|
|
{ PseudoVSSE16_V_MF4, VSSE16_V }, // 8809
|
|
{ PseudoVSSE16_V_MF4_MASK, VSSE16_V }, // 8810
|
|
{ PseudoVSSE32_V_M1, VSSE32_V }, // 8811
|
|
{ PseudoVSSE32_V_M1_MASK, VSSE32_V }, // 8812
|
|
{ PseudoVSSE32_V_M2, VSSE32_V }, // 8813
|
|
{ PseudoVSSE32_V_M2_MASK, VSSE32_V }, // 8814
|
|
{ PseudoVSSE32_V_M4, VSSE32_V }, // 8815
|
|
{ PseudoVSSE32_V_M4_MASK, VSSE32_V }, // 8816
|
|
{ PseudoVSSE32_V_M8, VSSE32_V }, // 8817
|
|
{ PseudoVSSE32_V_M8_MASK, VSSE32_V }, // 8818
|
|
{ PseudoVSSE32_V_MF2, VSSE32_V }, // 8819
|
|
{ PseudoVSSE32_V_MF2_MASK, VSSE32_V }, // 8820
|
|
{ PseudoVSSE64_V_M1, VSSE64_V }, // 8821
|
|
{ PseudoVSSE64_V_M1_MASK, VSSE64_V }, // 8822
|
|
{ PseudoVSSE64_V_M2, VSSE64_V }, // 8823
|
|
{ PseudoVSSE64_V_M2_MASK, VSSE64_V }, // 8824
|
|
{ PseudoVSSE64_V_M4, VSSE64_V }, // 8825
|
|
{ PseudoVSSE64_V_M4_MASK, VSSE64_V }, // 8826
|
|
{ PseudoVSSE64_V_M8, VSSE64_V }, // 8827
|
|
{ PseudoVSSE64_V_M8_MASK, VSSE64_V }, // 8828
|
|
{ PseudoVSSE8_V_M1, VSSE8_V }, // 8829
|
|
{ PseudoVSSE8_V_M1_MASK, VSSE8_V }, // 8830
|
|
{ PseudoVSSE8_V_M2, VSSE8_V }, // 8831
|
|
{ PseudoVSSE8_V_M2_MASK, VSSE8_V }, // 8832
|
|
{ PseudoVSSE8_V_M4, VSSE8_V }, // 8833
|
|
{ PseudoVSSE8_V_M4_MASK, VSSE8_V }, // 8834
|
|
{ PseudoVSSE8_V_M8, VSSE8_V }, // 8835
|
|
{ PseudoVSSE8_V_M8_MASK, VSSE8_V }, // 8836
|
|
{ PseudoVSSE8_V_MF2, VSSE8_V }, // 8837
|
|
{ PseudoVSSE8_V_MF2_MASK, VSSE8_V }, // 8838
|
|
{ PseudoVSSE8_V_MF4, VSSE8_V }, // 8839
|
|
{ PseudoVSSE8_V_MF4_MASK, VSSE8_V }, // 8840
|
|
{ PseudoVSSE8_V_MF8, VSSE8_V }, // 8841
|
|
{ PseudoVSSE8_V_MF8_MASK, VSSE8_V }, // 8842
|
|
{ PseudoVSSEG2E16_V_M1, VSSEG2E16_V }, // 8843
|
|
{ PseudoVSSEG2E16_V_M1_MASK, VSSEG2E16_V }, // 8844
|
|
{ PseudoVSSEG2E16_V_M2, VSSEG2E16_V }, // 8845
|
|
{ PseudoVSSEG2E16_V_M2_MASK, VSSEG2E16_V }, // 8846
|
|
{ PseudoVSSEG2E16_V_M4, VSSEG2E16_V }, // 8847
|
|
{ PseudoVSSEG2E16_V_M4_MASK, VSSEG2E16_V }, // 8848
|
|
{ PseudoVSSEG2E16_V_MF2, VSSEG2E16_V }, // 8849
|
|
{ PseudoVSSEG2E16_V_MF2_MASK, VSSEG2E16_V }, // 8850
|
|
{ PseudoVSSEG2E16_V_MF4, VSSEG2E16_V }, // 8851
|
|
{ PseudoVSSEG2E16_V_MF4_MASK, VSSEG2E16_V }, // 8852
|
|
{ PseudoVSSEG2E32_V_M1, VSSEG2E32_V }, // 8853
|
|
{ PseudoVSSEG2E32_V_M1_MASK, VSSEG2E32_V }, // 8854
|
|
{ PseudoVSSEG2E32_V_M2, VSSEG2E32_V }, // 8855
|
|
{ PseudoVSSEG2E32_V_M2_MASK, VSSEG2E32_V }, // 8856
|
|
{ PseudoVSSEG2E32_V_M4, VSSEG2E32_V }, // 8857
|
|
{ PseudoVSSEG2E32_V_M4_MASK, VSSEG2E32_V }, // 8858
|
|
{ PseudoVSSEG2E32_V_MF2, VSSEG2E32_V }, // 8859
|
|
{ PseudoVSSEG2E32_V_MF2_MASK, VSSEG2E32_V }, // 8860
|
|
{ PseudoVSSEG2E64_V_M1, VSSEG2E64_V }, // 8861
|
|
{ PseudoVSSEG2E64_V_M1_MASK, VSSEG2E64_V }, // 8862
|
|
{ PseudoVSSEG2E64_V_M2, VSSEG2E64_V }, // 8863
|
|
{ PseudoVSSEG2E64_V_M2_MASK, VSSEG2E64_V }, // 8864
|
|
{ PseudoVSSEG2E64_V_M4, VSSEG2E64_V }, // 8865
|
|
{ PseudoVSSEG2E64_V_M4_MASK, VSSEG2E64_V }, // 8866
|
|
{ PseudoVSSEG2E8_V_M1, VSSEG2E8_V }, // 8867
|
|
{ PseudoVSSEG2E8_V_M1_MASK, VSSEG2E8_V }, // 8868
|
|
{ PseudoVSSEG2E8_V_M2, VSSEG2E8_V }, // 8869
|
|
{ PseudoVSSEG2E8_V_M2_MASK, VSSEG2E8_V }, // 8870
|
|
{ PseudoVSSEG2E8_V_M4, VSSEG2E8_V }, // 8871
|
|
{ PseudoVSSEG2E8_V_M4_MASK, VSSEG2E8_V }, // 8872
|
|
{ PseudoVSSEG2E8_V_MF2, VSSEG2E8_V }, // 8873
|
|
{ PseudoVSSEG2E8_V_MF2_MASK, VSSEG2E8_V }, // 8874
|
|
{ PseudoVSSEG2E8_V_MF4, VSSEG2E8_V }, // 8875
|
|
{ PseudoVSSEG2E8_V_MF4_MASK, VSSEG2E8_V }, // 8876
|
|
{ PseudoVSSEG2E8_V_MF8, VSSEG2E8_V }, // 8877
|
|
{ PseudoVSSEG2E8_V_MF8_MASK, VSSEG2E8_V }, // 8878
|
|
{ PseudoVSSEG3E16_V_M1, VSSEG3E16_V }, // 8879
|
|
{ PseudoVSSEG3E16_V_M1_MASK, VSSEG3E16_V }, // 8880
|
|
{ PseudoVSSEG3E16_V_M2, VSSEG3E16_V }, // 8881
|
|
{ PseudoVSSEG3E16_V_M2_MASK, VSSEG3E16_V }, // 8882
|
|
{ PseudoVSSEG3E16_V_MF2, VSSEG3E16_V }, // 8883
|
|
{ PseudoVSSEG3E16_V_MF2_MASK, VSSEG3E16_V }, // 8884
|
|
{ PseudoVSSEG3E16_V_MF4, VSSEG3E16_V }, // 8885
|
|
{ PseudoVSSEG3E16_V_MF4_MASK, VSSEG3E16_V }, // 8886
|
|
{ PseudoVSSEG3E32_V_M1, VSSEG3E32_V }, // 8887
|
|
{ PseudoVSSEG3E32_V_M1_MASK, VSSEG3E32_V }, // 8888
|
|
{ PseudoVSSEG3E32_V_M2, VSSEG3E32_V }, // 8889
|
|
{ PseudoVSSEG3E32_V_M2_MASK, VSSEG3E32_V }, // 8890
|
|
{ PseudoVSSEG3E32_V_MF2, VSSEG3E32_V }, // 8891
|
|
{ PseudoVSSEG3E32_V_MF2_MASK, VSSEG3E32_V }, // 8892
|
|
{ PseudoVSSEG3E64_V_M1, VSSEG3E64_V }, // 8893
|
|
{ PseudoVSSEG3E64_V_M1_MASK, VSSEG3E64_V }, // 8894
|
|
{ PseudoVSSEG3E64_V_M2, VSSEG3E64_V }, // 8895
|
|
{ PseudoVSSEG3E64_V_M2_MASK, VSSEG3E64_V }, // 8896
|
|
{ PseudoVSSEG3E8_V_M1, VSSEG3E8_V }, // 8897
|
|
{ PseudoVSSEG3E8_V_M1_MASK, VSSEG3E8_V }, // 8898
|
|
{ PseudoVSSEG3E8_V_M2, VSSEG3E8_V }, // 8899
|
|
{ PseudoVSSEG3E8_V_M2_MASK, VSSEG3E8_V }, // 8900
|
|
{ PseudoVSSEG3E8_V_MF2, VSSEG3E8_V }, // 8901
|
|
{ PseudoVSSEG3E8_V_MF2_MASK, VSSEG3E8_V }, // 8902
|
|
{ PseudoVSSEG3E8_V_MF4, VSSEG3E8_V }, // 8903
|
|
{ PseudoVSSEG3E8_V_MF4_MASK, VSSEG3E8_V }, // 8904
|
|
{ PseudoVSSEG3E8_V_MF8, VSSEG3E8_V }, // 8905
|
|
{ PseudoVSSEG3E8_V_MF8_MASK, VSSEG3E8_V }, // 8906
|
|
{ PseudoVSSEG4E16_V_M1, VSSEG4E16_V }, // 8907
|
|
{ PseudoVSSEG4E16_V_M1_MASK, VSSEG4E16_V }, // 8908
|
|
{ PseudoVSSEG4E16_V_M2, VSSEG4E16_V }, // 8909
|
|
{ PseudoVSSEG4E16_V_M2_MASK, VSSEG4E16_V }, // 8910
|
|
{ PseudoVSSEG4E16_V_MF2, VSSEG4E16_V }, // 8911
|
|
{ PseudoVSSEG4E16_V_MF2_MASK, VSSEG4E16_V }, // 8912
|
|
{ PseudoVSSEG4E16_V_MF4, VSSEG4E16_V }, // 8913
|
|
{ PseudoVSSEG4E16_V_MF4_MASK, VSSEG4E16_V }, // 8914
|
|
{ PseudoVSSEG4E32_V_M1, VSSEG4E32_V }, // 8915
|
|
{ PseudoVSSEG4E32_V_M1_MASK, VSSEG4E32_V }, // 8916
|
|
{ PseudoVSSEG4E32_V_M2, VSSEG4E32_V }, // 8917
|
|
{ PseudoVSSEG4E32_V_M2_MASK, VSSEG4E32_V }, // 8918
|
|
{ PseudoVSSEG4E32_V_MF2, VSSEG4E32_V }, // 8919
|
|
{ PseudoVSSEG4E32_V_MF2_MASK, VSSEG4E32_V }, // 8920
|
|
{ PseudoVSSEG4E64_V_M1, VSSEG4E64_V }, // 8921
|
|
{ PseudoVSSEG4E64_V_M1_MASK, VSSEG4E64_V }, // 8922
|
|
{ PseudoVSSEG4E64_V_M2, VSSEG4E64_V }, // 8923
|
|
{ PseudoVSSEG4E64_V_M2_MASK, VSSEG4E64_V }, // 8924
|
|
{ PseudoVSSEG4E8_V_M1, VSSEG4E8_V }, // 8925
|
|
{ PseudoVSSEG4E8_V_M1_MASK, VSSEG4E8_V }, // 8926
|
|
{ PseudoVSSEG4E8_V_M2, VSSEG4E8_V }, // 8927
|
|
{ PseudoVSSEG4E8_V_M2_MASK, VSSEG4E8_V }, // 8928
|
|
{ PseudoVSSEG4E8_V_MF2, VSSEG4E8_V }, // 8929
|
|
{ PseudoVSSEG4E8_V_MF2_MASK, VSSEG4E8_V }, // 8930
|
|
{ PseudoVSSEG4E8_V_MF4, VSSEG4E8_V }, // 8931
|
|
{ PseudoVSSEG4E8_V_MF4_MASK, VSSEG4E8_V }, // 8932
|
|
{ PseudoVSSEG4E8_V_MF8, VSSEG4E8_V }, // 8933
|
|
{ PseudoVSSEG4E8_V_MF8_MASK, VSSEG4E8_V }, // 8934
|
|
{ PseudoVSSEG5E16_V_M1, VSSEG5E16_V }, // 8935
|
|
{ PseudoVSSEG5E16_V_M1_MASK, VSSEG5E16_V }, // 8936
|
|
{ PseudoVSSEG5E16_V_MF2, VSSEG5E16_V }, // 8937
|
|
{ PseudoVSSEG5E16_V_MF2_MASK, VSSEG5E16_V }, // 8938
|
|
{ PseudoVSSEG5E16_V_MF4, VSSEG5E16_V }, // 8939
|
|
{ PseudoVSSEG5E16_V_MF4_MASK, VSSEG5E16_V }, // 8940
|
|
{ PseudoVSSEG5E32_V_M1, VSSEG5E32_V }, // 8941
|
|
{ PseudoVSSEG5E32_V_M1_MASK, VSSEG5E32_V }, // 8942
|
|
{ PseudoVSSEG5E32_V_MF2, VSSEG5E32_V }, // 8943
|
|
{ PseudoVSSEG5E32_V_MF2_MASK, VSSEG5E32_V }, // 8944
|
|
{ PseudoVSSEG5E64_V_M1, VSSEG5E64_V }, // 8945
|
|
{ PseudoVSSEG5E64_V_M1_MASK, VSSEG5E64_V }, // 8946
|
|
{ PseudoVSSEG5E8_V_M1, VSSEG5E8_V }, // 8947
|
|
{ PseudoVSSEG5E8_V_M1_MASK, VSSEG5E8_V }, // 8948
|
|
{ PseudoVSSEG5E8_V_MF2, VSSEG5E8_V }, // 8949
|
|
{ PseudoVSSEG5E8_V_MF2_MASK, VSSEG5E8_V }, // 8950
|
|
{ PseudoVSSEG5E8_V_MF4, VSSEG5E8_V }, // 8951
|
|
{ PseudoVSSEG5E8_V_MF4_MASK, VSSEG5E8_V }, // 8952
|
|
{ PseudoVSSEG5E8_V_MF8, VSSEG5E8_V }, // 8953
|
|
{ PseudoVSSEG5E8_V_MF8_MASK, VSSEG5E8_V }, // 8954
|
|
{ PseudoVSSEG6E16_V_M1, VSSEG6E16_V }, // 8955
|
|
{ PseudoVSSEG6E16_V_M1_MASK, VSSEG6E16_V }, // 8956
|
|
{ PseudoVSSEG6E16_V_MF2, VSSEG6E16_V }, // 8957
|
|
{ PseudoVSSEG6E16_V_MF2_MASK, VSSEG6E16_V }, // 8958
|
|
{ PseudoVSSEG6E16_V_MF4, VSSEG6E16_V }, // 8959
|
|
{ PseudoVSSEG6E16_V_MF4_MASK, VSSEG6E16_V }, // 8960
|
|
{ PseudoVSSEG6E32_V_M1, VSSEG6E32_V }, // 8961
|
|
{ PseudoVSSEG6E32_V_M1_MASK, VSSEG6E32_V }, // 8962
|
|
{ PseudoVSSEG6E32_V_MF2, VSSEG6E32_V }, // 8963
|
|
{ PseudoVSSEG6E32_V_MF2_MASK, VSSEG6E32_V }, // 8964
|
|
{ PseudoVSSEG6E64_V_M1, VSSEG6E64_V }, // 8965
|
|
{ PseudoVSSEG6E64_V_M1_MASK, VSSEG6E64_V }, // 8966
|
|
{ PseudoVSSEG6E8_V_M1, VSSEG6E8_V }, // 8967
|
|
{ PseudoVSSEG6E8_V_M1_MASK, VSSEG6E8_V }, // 8968
|
|
{ PseudoVSSEG6E8_V_MF2, VSSEG6E8_V }, // 8969
|
|
{ PseudoVSSEG6E8_V_MF2_MASK, VSSEG6E8_V }, // 8970
|
|
{ PseudoVSSEG6E8_V_MF4, VSSEG6E8_V }, // 8971
|
|
{ PseudoVSSEG6E8_V_MF4_MASK, VSSEG6E8_V }, // 8972
|
|
{ PseudoVSSEG6E8_V_MF8, VSSEG6E8_V }, // 8973
|
|
{ PseudoVSSEG6E8_V_MF8_MASK, VSSEG6E8_V }, // 8974
|
|
{ PseudoVSSEG7E16_V_M1, VSSEG7E16_V }, // 8975
|
|
{ PseudoVSSEG7E16_V_M1_MASK, VSSEG7E16_V }, // 8976
|
|
{ PseudoVSSEG7E16_V_MF2, VSSEG7E16_V }, // 8977
|
|
{ PseudoVSSEG7E16_V_MF2_MASK, VSSEG7E16_V }, // 8978
|
|
{ PseudoVSSEG7E16_V_MF4, VSSEG7E16_V }, // 8979
|
|
{ PseudoVSSEG7E16_V_MF4_MASK, VSSEG7E16_V }, // 8980
|
|
{ PseudoVSSEG7E32_V_M1, VSSEG7E32_V }, // 8981
|
|
{ PseudoVSSEG7E32_V_M1_MASK, VSSEG7E32_V }, // 8982
|
|
{ PseudoVSSEG7E32_V_MF2, VSSEG7E32_V }, // 8983
|
|
{ PseudoVSSEG7E32_V_MF2_MASK, VSSEG7E32_V }, // 8984
|
|
{ PseudoVSSEG7E64_V_M1, VSSEG7E64_V }, // 8985
|
|
{ PseudoVSSEG7E64_V_M1_MASK, VSSEG7E64_V }, // 8986
|
|
{ PseudoVSSEG7E8_V_M1, VSSEG7E8_V }, // 8987
|
|
{ PseudoVSSEG7E8_V_M1_MASK, VSSEG7E8_V }, // 8988
|
|
{ PseudoVSSEG7E8_V_MF2, VSSEG7E8_V }, // 8989
|
|
{ PseudoVSSEG7E8_V_MF2_MASK, VSSEG7E8_V }, // 8990
|
|
{ PseudoVSSEG7E8_V_MF4, VSSEG7E8_V }, // 8991
|
|
{ PseudoVSSEG7E8_V_MF4_MASK, VSSEG7E8_V }, // 8992
|
|
{ PseudoVSSEG7E8_V_MF8, VSSEG7E8_V }, // 8993
|
|
{ PseudoVSSEG7E8_V_MF8_MASK, VSSEG7E8_V }, // 8994
|
|
{ PseudoVSSEG8E16_V_M1, VSSEG8E16_V }, // 8995
|
|
{ PseudoVSSEG8E16_V_M1_MASK, VSSEG8E16_V }, // 8996
|
|
{ PseudoVSSEG8E16_V_MF2, VSSEG8E16_V }, // 8997
|
|
{ PseudoVSSEG8E16_V_MF2_MASK, VSSEG8E16_V }, // 8998
|
|
{ PseudoVSSEG8E16_V_MF4, VSSEG8E16_V }, // 8999
|
|
{ PseudoVSSEG8E16_V_MF4_MASK, VSSEG8E16_V }, // 9000
|
|
{ PseudoVSSEG8E32_V_M1, VSSEG8E32_V }, // 9001
|
|
{ PseudoVSSEG8E32_V_M1_MASK, VSSEG8E32_V }, // 9002
|
|
{ PseudoVSSEG8E32_V_MF2, VSSEG8E32_V }, // 9003
|
|
{ PseudoVSSEG8E32_V_MF2_MASK, VSSEG8E32_V }, // 9004
|
|
{ PseudoVSSEG8E64_V_M1, VSSEG8E64_V }, // 9005
|
|
{ PseudoVSSEG8E64_V_M1_MASK, VSSEG8E64_V }, // 9006
|
|
{ PseudoVSSEG8E8_V_M1, VSSEG8E8_V }, // 9007
|
|
{ PseudoVSSEG8E8_V_M1_MASK, VSSEG8E8_V }, // 9008
|
|
{ PseudoVSSEG8E8_V_MF2, VSSEG8E8_V }, // 9009
|
|
{ PseudoVSSEG8E8_V_MF2_MASK, VSSEG8E8_V }, // 9010
|
|
{ PseudoVSSEG8E8_V_MF4, VSSEG8E8_V }, // 9011
|
|
{ PseudoVSSEG8E8_V_MF4_MASK, VSSEG8E8_V }, // 9012
|
|
{ PseudoVSSEG8E8_V_MF8, VSSEG8E8_V }, // 9013
|
|
{ PseudoVSSEG8E8_V_MF8_MASK, VSSEG8E8_V }, // 9014
|
|
{ PseudoVSSRA_VI_M1, VSSRA_VI }, // 9015
|
|
{ PseudoVSSRA_VI_M1_MASK, VSSRA_VI }, // 9016
|
|
{ PseudoVSSRA_VI_M2, VSSRA_VI }, // 9017
|
|
{ PseudoVSSRA_VI_M2_MASK, VSSRA_VI }, // 9018
|
|
{ PseudoVSSRA_VI_M4, VSSRA_VI }, // 9019
|
|
{ PseudoVSSRA_VI_M4_MASK, VSSRA_VI }, // 9020
|
|
{ PseudoVSSRA_VI_M8, VSSRA_VI }, // 9021
|
|
{ PseudoVSSRA_VI_M8_MASK, VSSRA_VI }, // 9022
|
|
{ PseudoVSSRA_VI_MF2, VSSRA_VI }, // 9023
|
|
{ PseudoVSSRA_VI_MF2_MASK, VSSRA_VI }, // 9024
|
|
{ PseudoVSSRA_VI_MF4, VSSRA_VI }, // 9025
|
|
{ PseudoVSSRA_VI_MF4_MASK, VSSRA_VI }, // 9026
|
|
{ PseudoVSSRA_VI_MF8, VSSRA_VI }, // 9027
|
|
{ PseudoVSSRA_VI_MF8_MASK, VSSRA_VI }, // 9028
|
|
{ PseudoVSSRA_VV_M1, VSSRA_VV }, // 9029
|
|
{ PseudoVSSRA_VV_M1_MASK, VSSRA_VV }, // 9030
|
|
{ PseudoVSSRA_VV_M2, VSSRA_VV }, // 9031
|
|
{ PseudoVSSRA_VV_M2_MASK, VSSRA_VV }, // 9032
|
|
{ PseudoVSSRA_VV_M4, VSSRA_VV }, // 9033
|
|
{ PseudoVSSRA_VV_M4_MASK, VSSRA_VV }, // 9034
|
|
{ PseudoVSSRA_VV_M8, VSSRA_VV }, // 9035
|
|
{ PseudoVSSRA_VV_M8_MASK, VSSRA_VV }, // 9036
|
|
{ PseudoVSSRA_VV_MF2, VSSRA_VV }, // 9037
|
|
{ PseudoVSSRA_VV_MF2_MASK, VSSRA_VV }, // 9038
|
|
{ PseudoVSSRA_VV_MF4, VSSRA_VV }, // 9039
|
|
{ PseudoVSSRA_VV_MF4_MASK, VSSRA_VV }, // 9040
|
|
{ PseudoVSSRA_VV_MF8, VSSRA_VV }, // 9041
|
|
{ PseudoVSSRA_VV_MF8_MASK, VSSRA_VV }, // 9042
|
|
{ PseudoVSSRA_VX_M1, VSSRA_VX }, // 9043
|
|
{ PseudoVSSRA_VX_M1_MASK, VSSRA_VX }, // 9044
|
|
{ PseudoVSSRA_VX_M2, VSSRA_VX }, // 9045
|
|
{ PseudoVSSRA_VX_M2_MASK, VSSRA_VX }, // 9046
|
|
{ PseudoVSSRA_VX_M4, VSSRA_VX }, // 9047
|
|
{ PseudoVSSRA_VX_M4_MASK, VSSRA_VX }, // 9048
|
|
{ PseudoVSSRA_VX_M8, VSSRA_VX }, // 9049
|
|
{ PseudoVSSRA_VX_M8_MASK, VSSRA_VX }, // 9050
|
|
{ PseudoVSSRA_VX_MF2, VSSRA_VX }, // 9051
|
|
{ PseudoVSSRA_VX_MF2_MASK, VSSRA_VX }, // 9052
|
|
{ PseudoVSSRA_VX_MF4, VSSRA_VX }, // 9053
|
|
{ PseudoVSSRA_VX_MF4_MASK, VSSRA_VX }, // 9054
|
|
{ PseudoVSSRA_VX_MF8, VSSRA_VX }, // 9055
|
|
{ PseudoVSSRA_VX_MF8_MASK, VSSRA_VX }, // 9056
|
|
{ PseudoVSSRL_VI_M1, VSSRL_VI }, // 9057
|
|
{ PseudoVSSRL_VI_M1_MASK, VSSRL_VI }, // 9058
|
|
{ PseudoVSSRL_VI_M2, VSSRL_VI }, // 9059
|
|
{ PseudoVSSRL_VI_M2_MASK, VSSRL_VI }, // 9060
|
|
{ PseudoVSSRL_VI_M4, VSSRL_VI }, // 9061
|
|
{ PseudoVSSRL_VI_M4_MASK, VSSRL_VI }, // 9062
|
|
{ PseudoVSSRL_VI_M8, VSSRL_VI }, // 9063
|
|
{ PseudoVSSRL_VI_M8_MASK, VSSRL_VI }, // 9064
|
|
{ PseudoVSSRL_VI_MF2, VSSRL_VI }, // 9065
|
|
{ PseudoVSSRL_VI_MF2_MASK, VSSRL_VI }, // 9066
|
|
{ PseudoVSSRL_VI_MF4, VSSRL_VI }, // 9067
|
|
{ PseudoVSSRL_VI_MF4_MASK, VSSRL_VI }, // 9068
|
|
{ PseudoVSSRL_VI_MF8, VSSRL_VI }, // 9069
|
|
{ PseudoVSSRL_VI_MF8_MASK, VSSRL_VI }, // 9070
|
|
{ PseudoVSSRL_VV_M1, VSSRL_VV }, // 9071
|
|
{ PseudoVSSRL_VV_M1_MASK, VSSRL_VV }, // 9072
|
|
{ PseudoVSSRL_VV_M2, VSSRL_VV }, // 9073
|
|
{ PseudoVSSRL_VV_M2_MASK, VSSRL_VV }, // 9074
|
|
{ PseudoVSSRL_VV_M4, VSSRL_VV }, // 9075
|
|
{ PseudoVSSRL_VV_M4_MASK, VSSRL_VV }, // 9076
|
|
{ PseudoVSSRL_VV_M8, VSSRL_VV }, // 9077
|
|
{ PseudoVSSRL_VV_M8_MASK, VSSRL_VV }, // 9078
|
|
{ PseudoVSSRL_VV_MF2, VSSRL_VV }, // 9079
|
|
{ PseudoVSSRL_VV_MF2_MASK, VSSRL_VV }, // 9080
|
|
{ PseudoVSSRL_VV_MF4, VSSRL_VV }, // 9081
|
|
{ PseudoVSSRL_VV_MF4_MASK, VSSRL_VV }, // 9082
|
|
{ PseudoVSSRL_VV_MF8, VSSRL_VV }, // 9083
|
|
{ PseudoVSSRL_VV_MF8_MASK, VSSRL_VV }, // 9084
|
|
{ PseudoVSSRL_VX_M1, VSSRL_VX }, // 9085
|
|
{ PseudoVSSRL_VX_M1_MASK, VSSRL_VX }, // 9086
|
|
{ PseudoVSSRL_VX_M2, VSSRL_VX }, // 9087
|
|
{ PseudoVSSRL_VX_M2_MASK, VSSRL_VX }, // 9088
|
|
{ PseudoVSSRL_VX_M4, VSSRL_VX }, // 9089
|
|
{ PseudoVSSRL_VX_M4_MASK, VSSRL_VX }, // 9090
|
|
{ PseudoVSSRL_VX_M8, VSSRL_VX }, // 9091
|
|
{ PseudoVSSRL_VX_M8_MASK, VSSRL_VX }, // 9092
|
|
{ PseudoVSSRL_VX_MF2, VSSRL_VX }, // 9093
|
|
{ PseudoVSSRL_VX_MF2_MASK, VSSRL_VX }, // 9094
|
|
{ PseudoVSSRL_VX_MF4, VSSRL_VX }, // 9095
|
|
{ PseudoVSSRL_VX_MF4_MASK, VSSRL_VX }, // 9096
|
|
{ PseudoVSSRL_VX_MF8, VSSRL_VX }, // 9097
|
|
{ PseudoVSSRL_VX_MF8_MASK, VSSRL_VX }, // 9098
|
|
{ PseudoVSSSEG2E16_V_M1, VSSSEG2E16_V }, // 9099
|
|
{ PseudoVSSSEG2E16_V_M1_MASK, VSSSEG2E16_V }, // 9100
|
|
{ PseudoVSSSEG2E16_V_M2, VSSSEG2E16_V }, // 9101
|
|
{ PseudoVSSSEG2E16_V_M2_MASK, VSSSEG2E16_V }, // 9102
|
|
{ PseudoVSSSEG2E16_V_M4, VSSSEG2E16_V }, // 9103
|
|
{ PseudoVSSSEG2E16_V_M4_MASK, VSSSEG2E16_V }, // 9104
|
|
{ PseudoVSSSEG2E16_V_MF2, VSSSEG2E16_V }, // 9105
|
|
{ PseudoVSSSEG2E16_V_MF2_MASK, VSSSEG2E16_V }, // 9106
|
|
{ PseudoVSSSEG2E16_V_MF4, VSSSEG2E16_V }, // 9107
|
|
{ PseudoVSSSEG2E16_V_MF4_MASK, VSSSEG2E16_V }, // 9108
|
|
{ PseudoVSSSEG2E32_V_M1, VSSSEG2E32_V }, // 9109
|
|
{ PseudoVSSSEG2E32_V_M1_MASK, VSSSEG2E32_V }, // 9110
|
|
{ PseudoVSSSEG2E32_V_M2, VSSSEG2E32_V }, // 9111
|
|
{ PseudoVSSSEG2E32_V_M2_MASK, VSSSEG2E32_V }, // 9112
|
|
{ PseudoVSSSEG2E32_V_M4, VSSSEG2E32_V }, // 9113
|
|
{ PseudoVSSSEG2E32_V_M4_MASK, VSSSEG2E32_V }, // 9114
|
|
{ PseudoVSSSEG2E32_V_MF2, VSSSEG2E32_V }, // 9115
|
|
{ PseudoVSSSEG2E32_V_MF2_MASK, VSSSEG2E32_V }, // 9116
|
|
{ PseudoVSSSEG2E64_V_M1, VSSSEG2E64_V }, // 9117
|
|
{ PseudoVSSSEG2E64_V_M1_MASK, VSSSEG2E64_V }, // 9118
|
|
{ PseudoVSSSEG2E64_V_M2, VSSSEG2E64_V }, // 9119
|
|
{ PseudoVSSSEG2E64_V_M2_MASK, VSSSEG2E64_V }, // 9120
|
|
{ PseudoVSSSEG2E64_V_M4, VSSSEG2E64_V }, // 9121
|
|
{ PseudoVSSSEG2E64_V_M4_MASK, VSSSEG2E64_V }, // 9122
|
|
{ PseudoVSSSEG2E8_V_M1, VSSSEG2E8_V }, // 9123
|
|
{ PseudoVSSSEG2E8_V_M1_MASK, VSSSEG2E8_V }, // 9124
|
|
{ PseudoVSSSEG2E8_V_M2, VSSSEG2E8_V }, // 9125
|
|
{ PseudoVSSSEG2E8_V_M2_MASK, VSSSEG2E8_V }, // 9126
|
|
{ PseudoVSSSEG2E8_V_M4, VSSSEG2E8_V }, // 9127
|
|
{ PseudoVSSSEG2E8_V_M4_MASK, VSSSEG2E8_V }, // 9128
|
|
{ PseudoVSSSEG2E8_V_MF2, VSSSEG2E8_V }, // 9129
|
|
{ PseudoVSSSEG2E8_V_MF2_MASK, VSSSEG2E8_V }, // 9130
|
|
{ PseudoVSSSEG2E8_V_MF4, VSSSEG2E8_V }, // 9131
|
|
{ PseudoVSSSEG2E8_V_MF4_MASK, VSSSEG2E8_V }, // 9132
|
|
{ PseudoVSSSEG2E8_V_MF8, VSSSEG2E8_V }, // 9133
|
|
{ PseudoVSSSEG2E8_V_MF8_MASK, VSSSEG2E8_V }, // 9134
|
|
{ PseudoVSSSEG3E16_V_M1, VSSSEG3E16_V }, // 9135
|
|
{ PseudoVSSSEG3E16_V_M1_MASK, VSSSEG3E16_V }, // 9136
|
|
{ PseudoVSSSEG3E16_V_M2, VSSSEG3E16_V }, // 9137
|
|
{ PseudoVSSSEG3E16_V_M2_MASK, VSSSEG3E16_V }, // 9138
|
|
{ PseudoVSSSEG3E16_V_MF2, VSSSEG3E16_V }, // 9139
|
|
{ PseudoVSSSEG3E16_V_MF2_MASK, VSSSEG3E16_V }, // 9140
|
|
{ PseudoVSSSEG3E16_V_MF4, VSSSEG3E16_V }, // 9141
|
|
{ PseudoVSSSEG3E16_V_MF4_MASK, VSSSEG3E16_V }, // 9142
|
|
{ PseudoVSSSEG3E32_V_M1, VSSSEG3E32_V }, // 9143
|
|
{ PseudoVSSSEG3E32_V_M1_MASK, VSSSEG3E32_V }, // 9144
|
|
{ PseudoVSSSEG3E32_V_M2, VSSSEG3E32_V }, // 9145
|
|
{ PseudoVSSSEG3E32_V_M2_MASK, VSSSEG3E32_V }, // 9146
|
|
{ PseudoVSSSEG3E32_V_MF2, VSSSEG3E32_V }, // 9147
|
|
{ PseudoVSSSEG3E32_V_MF2_MASK, VSSSEG3E32_V }, // 9148
|
|
{ PseudoVSSSEG3E64_V_M1, VSSSEG3E64_V }, // 9149
|
|
{ PseudoVSSSEG3E64_V_M1_MASK, VSSSEG3E64_V }, // 9150
|
|
{ PseudoVSSSEG3E64_V_M2, VSSSEG3E64_V }, // 9151
|
|
{ PseudoVSSSEG3E64_V_M2_MASK, VSSSEG3E64_V }, // 9152
|
|
{ PseudoVSSSEG3E8_V_M1, VSSSEG3E8_V }, // 9153
|
|
{ PseudoVSSSEG3E8_V_M1_MASK, VSSSEG3E8_V }, // 9154
|
|
{ PseudoVSSSEG3E8_V_M2, VSSSEG3E8_V }, // 9155
|
|
{ PseudoVSSSEG3E8_V_M2_MASK, VSSSEG3E8_V }, // 9156
|
|
{ PseudoVSSSEG3E8_V_MF2, VSSSEG3E8_V }, // 9157
|
|
{ PseudoVSSSEG3E8_V_MF2_MASK, VSSSEG3E8_V }, // 9158
|
|
{ PseudoVSSSEG3E8_V_MF4, VSSSEG3E8_V }, // 9159
|
|
{ PseudoVSSSEG3E8_V_MF4_MASK, VSSSEG3E8_V }, // 9160
|
|
{ PseudoVSSSEG3E8_V_MF8, VSSSEG3E8_V }, // 9161
|
|
{ PseudoVSSSEG3E8_V_MF8_MASK, VSSSEG3E8_V }, // 9162
|
|
{ PseudoVSSSEG4E16_V_M1, VSSSEG4E16_V }, // 9163
|
|
{ PseudoVSSSEG4E16_V_M1_MASK, VSSSEG4E16_V }, // 9164
|
|
{ PseudoVSSSEG4E16_V_M2, VSSSEG4E16_V }, // 9165
|
|
{ PseudoVSSSEG4E16_V_M2_MASK, VSSSEG4E16_V }, // 9166
|
|
{ PseudoVSSSEG4E16_V_MF2, VSSSEG4E16_V }, // 9167
|
|
{ PseudoVSSSEG4E16_V_MF2_MASK, VSSSEG4E16_V }, // 9168
|
|
{ PseudoVSSSEG4E16_V_MF4, VSSSEG4E16_V }, // 9169
|
|
{ PseudoVSSSEG4E16_V_MF4_MASK, VSSSEG4E16_V }, // 9170
|
|
{ PseudoVSSSEG4E32_V_M1, VSSSEG4E32_V }, // 9171
|
|
{ PseudoVSSSEG4E32_V_M1_MASK, VSSSEG4E32_V }, // 9172
|
|
{ PseudoVSSSEG4E32_V_M2, VSSSEG4E32_V }, // 9173
|
|
{ PseudoVSSSEG4E32_V_M2_MASK, VSSSEG4E32_V }, // 9174
|
|
{ PseudoVSSSEG4E32_V_MF2, VSSSEG4E32_V }, // 9175
|
|
{ PseudoVSSSEG4E32_V_MF2_MASK, VSSSEG4E32_V }, // 9176
|
|
{ PseudoVSSSEG4E64_V_M1, VSSSEG4E64_V }, // 9177
|
|
{ PseudoVSSSEG4E64_V_M1_MASK, VSSSEG4E64_V }, // 9178
|
|
{ PseudoVSSSEG4E64_V_M2, VSSSEG4E64_V }, // 9179
|
|
{ PseudoVSSSEG4E64_V_M2_MASK, VSSSEG4E64_V }, // 9180
|
|
{ PseudoVSSSEG4E8_V_M1, VSSSEG4E8_V }, // 9181
|
|
{ PseudoVSSSEG4E8_V_M1_MASK, VSSSEG4E8_V }, // 9182
|
|
{ PseudoVSSSEG4E8_V_M2, VSSSEG4E8_V }, // 9183
|
|
{ PseudoVSSSEG4E8_V_M2_MASK, VSSSEG4E8_V }, // 9184
|
|
{ PseudoVSSSEG4E8_V_MF2, VSSSEG4E8_V }, // 9185
|
|
{ PseudoVSSSEG4E8_V_MF2_MASK, VSSSEG4E8_V }, // 9186
|
|
{ PseudoVSSSEG4E8_V_MF4, VSSSEG4E8_V }, // 9187
|
|
{ PseudoVSSSEG4E8_V_MF4_MASK, VSSSEG4E8_V }, // 9188
|
|
{ PseudoVSSSEG4E8_V_MF8, VSSSEG4E8_V }, // 9189
|
|
{ PseudoVSSSEG4E8_V_MF8_MASK, VSSSEG4E8_V }, // 9190
|
|
{ PseudoVSSSEG5E16_V_M1, VSSSEG5E16_V }, // 9191
|
|
{ PseudoVSSSEG5E16_V_M1_MASK, VSSSEG5E16_V }, // 9192
|
|
{ PseudoVSSSEG5E16_V_MF2, VSSSEG5E16_V }, // 9193
|
|
{ PseudoVSSSEG5E16_V_MF2_MASK, VSSSEG5E16_V }, // 9194
|
|
{ PseudoVSSSEG5E16_V_MF4, VSSSEG5E16_V }, // 9195
|
|
{ PseudoVSSSEG5E16_V_MF4_MASK, VSSSEG5E16_V }, // 9196
|
|
{ PseudoVSSSEG5E32_V_M1, VSSSEG5E32_V }, // 9197
|
|
{ PseudoVSSSEG5E32_V_M1_MASK, VSSSEG5E32_V }, // 9198
|
|
{ PseudoVSSSEG5E32_V_MF2, VSSSEG5E32_V }, // 9199
|
|
{ PseudoVSSSEG5E32_V_MF2_MASK, VSSSEG5E32_V }, // 9200
|
|
{ PseudoVSSSEG5E64_V_M1, VSSSEG5E64_V }, // 9201
|
|
{ PseudoVSSSEG5E64_V_M1_MASK, VSSSEG5E64_V }, // 9202
|
|
{ PseudoVSSSEG5E8_V_M1, VSSSEG5E8_V }, // 9203
|
|
{ PseudoVSSSEG5E8_V_M1_MASK, VSSSEG5E8_V }, // 9204
|
|
{ PseudoVSSSEG5E8_V_MF2, VSSSEG5E8_V }, // 9205
|
|
{ PseudoVSSSEG5E8_V_MF2_MASK, VSSSEG5E8_V }, // 9206
|
|
{ PseudoVSSSEG5E8_V_MF4, VSSSEG5E8_V }, // 9207
|
|
{ PseudoVSSSEG5E8_V_MF4_MASK, VSSSEG5E8_V }, // 9208
|
|
{ PseudoVSSSEG5E8_V_MF8, VSSSEG5E8_V }, // 9209
|
|
{ PseudoVSSSEG5E8_V_MF8_MASK, VSSSEG5E8_V }, // 9210
|
|
{ PseudoVSSSEG6E16_V_M1, VSSSEG6E16_V }, // 9211
|
|
{ PseudoVSSSEG6E16_V_M1_MASK, VSSSEG6E16_V }, // 9212
|
|
{ PseudoVSSSEG6E16_V_MF2, VSSSEG6E16_V }, // 9213
|
|
{ PseudoVSSSEG6E16_V_MF2_MASK, VSSSEG6E16_V }, // 9214
|
|
{ PseudoVSSSEG6E16_V_MF4, VSSSEG6E16_V }, // 9215
|
|
{ PseudoVSSSEG6E16_V_MF4_MASK, VSSSEG6E16_V }, // 9216
|
|
{ PseudoVSSSEG6E32_V_M1, VSSSEG6E32_V }, // 9217
|
|
{ PseudoVSSSEG6E32_V_M1_MASK, VSSSEG6E32_V }, // 9218
|
|
{ PseudoVSSSEG6E32_V_MF2, VSSSEG6E32_V }, // 9219
|
|
{ PseudoVSSSEG6E32_V_MF2_MASK, VSSSEG6E32_V }, // 9220
|
|
{ PseudoVSSSEG6E64_V_M1, VSSSEG6E64_V }, // 9221
|
|
{ PseudoVSSSEG6E64_V_M1_MASK, VSSSEG6E64_V }, // 9222
|
|
{ PseudoVSSSEG6E8_V_M1, VSSSEG6E8_V }, // 9223
|
|
{ PseudoVSSSEG6E8_V_M1_MASK, VSSSEG6E8_V }, // 9224
|
|
{ PseudoVSSSEG6E8_V_MF2, VSSSEG6E8_V }, // 9225
|
|
{ PseudoVSSSEG6E8_V_MF2_MASK, VSSSEG6E8_V }, // 9226
|
|
{ PseudoVSSSEG6E8_V_MF4, VSSSEG6E8_V }, // 9227
|
|
{ PseudoVSSSEG6E8_V_MF4_MASK, VSSSEG6E8_V }, // 9228
|
|
{ PseudoVSSSEG6E8_V_MF8, VSSSEG6E8_V }, // 9229
|
|
{ PseudoVSSSEG6E8_V_MF8_MASK, VSSSEG6E8_V }, // 9230
|
|
{ PseudoVSSSEG7E16_V_M1, VSSSEG7E16_V }, // 9231
|
|
{ PseudoVSSSEG7E16_V_M1_MASK, VSSSEG7E16_V }, // 9232
|
|
{ PseudoVSSSEG7E16_V_MF2, VSSSEG7E16_V }, // 9233
|
|
{ PseudoVSSSEG7E16_V_MF2_MASK, VSSSEG7E16_V }, // 9234
|
|
{ PseudoVSSSEG7E16_V_MF4, VSSSEG7E16_V }, // 9235
|
|
{ PseudoVSSSEG7E16_V_MF4_MASK, VSSSEG7E16_V }, // 9236
|
|
{ PseudoVSSSEG7E32_V_M1, VSSSEG7E32_V }, // 9237
|
|
{ PseudoVSSSEG7E32_V_M1_MASK, VSSSEG7E32_V }, // 9238
|
|
{ PseudoVSSSEG7E32_V_MF2, VSSSEG7E32_V }, // 9239
|
|
{ PseudoVSSSEG7E32_V_MF2_MASK, VSSSEG7E32_V }, // 9240
|
|
{ PseudoVSSSEG7E64_V_M1, VSSSEG7E64_V }, // 9241
|
|
{ PseudoVSSSEG7E64_V_M1_MASK, VSSSEG7E64_V }, // 9242
|
|
{ PseudoVSSSEG7E8_V_M1, VSSSEG7E8_V }, // 9243
|
|
{ PseudoVSSSEG7E8_V_M1_MASK, VSSSEG7E8_V }, // 9244
|
|
{ PseudoVSSSEG7E8_V_MF2, VSSSEG7E8_V }, // 9245
|
|
{ PseudoVSSSEG7E8_V_MF2_MASK, VSSSEG7E8_V }, // 9246
|
|
{ PseudoVSSSEG7E8_V_MF4, VSSSEG7E8_V }, // 9247
|
|
{ PseudoVSSSEG7E8_V_MF4_MASK, VSSSEG7E8_V }, // 9248
|
|
{ PseudoVSSSEG7E8_V_MF8, VSSSEG7E8_V }, // 9249
|
|
{ PseudoVSSSEG7E8_V_MF8_MASK, VSSSEG7E8_V }, // 9250
|
|
{ PseudoVSSSEG8E16_V_M1, VSSSEG8E16_V }, // 9251
|
|
{ PseudoVSSSEG8E16_V_M1_MASK, VSSSEG8E16_V }, // 9252
|
|
{ PseudoVSSSEG8E16_V_MF2, VSSSEG8E16_V }, // 9253
|
|
{ PseudoVSSSEG8E16_V_MF2_MASK, VSSSEG8E16_V }, // 9254
|
|
{ PseudoVSSSEG8E16_V_MF4, VSSSEG8E16_V }, // 9255
|
|
{ PseudoVSSSEG8E16_V_MF4_MASK, VSSSEG8E16_V }, // 9256
|
|
{ PseudoVSSSEG8E32_V_M1, VSSSEG8E32_V }, // 9257
|
|
{ PseudoVSSSEG8E32_V_M1_MASK, VSSSEG8E32_V }, // 9258
|
|
{ PseudoVSSSEG8E32_V_MF2, VSSSEG8E32_V }, // 9259
|
|
{ PseudoVSSSEG8E32_V_MF2_MASK, VSSSEG8E32_V }, // 9260
|
|
{ PseudoVSSSEG8E64_V_M1, VSSSEG8E64_V }, // 9261
|
|
{ PseudoVSSSEG8E64_V_M1_MASK, VSSSEG8E64_V }, // 9262
|
|
{ PseudoVSSSEG8E8_V_M1, VSSSEG8E8_V }, // 9263
|
|
{ PseudoVSSSEG8E8_V_M1_MASK, VSSSEG8E8_V }, // 9264
|
|
{ PseudoVSSSEG8E8_V_MF2, VSSSEG8E8_V }, // 9265
|
|
{ PseudoVSSSEG8E8_V_MF2_MASK, VSSSEG8E8_V }, // 9266
|
|
{ PseudoVSSSEG8E8_V_MF4, VSSSEG8E8_V }, // 9267
|
|
{ PseudoVSSSEG8E8_V_MF4_MASK, VSSSEG8E8_V }, // 9268
|
|
{ PseudoVSSSEG8E8_V_MF8, VSSSEG8E8_V }, // 9269
|
|
{ PseudoVSSSEG8E8_V_MF8_MASK, VSSSEG8E8_V }, // 9270
|
|
{ PseudoVSSUBU_VV_M1, VSSUBU_VV }, // 9271
|
|
{ PseudoVSSUBU_VV_M1_MASK, VSSUBU_VV }, // 9272
|
|
{ PseudoVSSUBU_VV_M2, VSSUBU_VV }, // 9273
|
|
{ PseudoVSSUBU_VV_M2_MASK, VSSUBU_VV }, // 9274
|
|
{ PseudoVSSUBU_VV_M4, VSSUBU_VV }, // 9275
|
|
{ PseudoVSSUBU_VV_M4_MASK, VSSUBU_VV }, // 9276
|
|
{ PseudoVSSUBU_VV_M8, VSSUBU_VV }, // 9277
|
|
{ PseudoVSSUBU_VV_M8_MASK, VSSUBU_VV }, // 9278
|
|
{ PseudoVSSUBU_VV_MF2, VSSUBU_VV }, // 9279
|
|
{ PseudoVSSUBU_VV_MF2_MASK, VSSUBU_VV }, // 9280
|
|
{ PseudoVSSUBU_VV_MF4, VSSUBU_VV }, // 9281
|
|
{ PseudoVSSUBU_VV_MF4_MASK, VSSUBU_VV }, // 9282
|
|
{ PseudoVSSUBU_VV_MF8, VSSUBU_VV }, // 9283
|
|
{ PseudoVSSUBU_VV_MF8_MASK, VSSUBU_VV }, // 9284
|
|
{ PseudoVSSUBU_VX_M1, VSSUBU_VX }, // 9285
|
|
{ PseudoVSSUBU_VX_M1_MASK, VSSUBU_VX }, // 9286
|
|
{ PseudoVSSUBU_VX_M2, VSSUBU_VX }, // 9287
|
|
{ PseudoVSSUBU_VX_M2_MASK, VSSUBU_VX }, // 9288
|
|
{ PseudoVSSUBU_VX_M4, VSSUBU_VX }, // 9289
|
|
{ PseudoVSSUBU_VX_M4_MASK, VSSUBU_VX }, // 9290
|
|
{ PseudoVSSUBU_VX_M8, VSSUBU_VX }, // 9291
|
|
{ PseudoVSSUBU_VX_M8_MASK, VSSUBU_VX }, // 9292
|
|
{ PseudoVSSUBU_VX_MF2, VSSUBU_VX }, // 9293
|
|
{ PseudoVSSUBU_VX_MF2_MASK, VSSUBU_VX }, // 9294
|
|
{ PseudoVSSUBU_VX_MF4, VSSUBU_VX }, // 9295
|
|
{ PseudoVSSUBU_VX_MF4_MASK, VSSUBU_VX }, // 9296
|
|
{ PseudoVSSUBU_VX_MF8, VSSUBU_VX }, // 9297
|
|
{ PseudoVSSUBU_VX_MF8_MASK, VSSUBU_VX }, // 9298
|
|
{ PseudoVSSUB_VV_M1, VSSUB_VV }, // 9299
|
|
{ PseudoVSSUB_VV_M1_MASK, VSSUB_VV }, // 9300
|
|
{ PseudoVSSUB_VV_M2, VSSUB_VV }, // 9301
|
|
{ PseudoVSSUB_VV_M2_MASK, VSSUB_VV }, // 9302
|
|
{ PseudoVSSUB_VV_M4, VSSUB_VV }, // 9303
|
|
{ PseudoVSSUB_VV_M4_MASK, VSSUB_VV }, // 9304
|
|
{ PseudoVSSUB_VV_M8, VSSUB_VV }, // 9305
|
|
{ PseudoVSSUB_VV_M8_MASK, VSSUB_VV }, // 9306
|
|
{ PseudoVSSUB_VV_MF2, VSSUB_VV }, // 9307
|
|
{ PseudoVSSUB_VV_MF2_MASK, VSSUB_VV }, // 9308
|
|
{ PseudoVSSUB_VV_MF4, VSSUB_VV }, // 9309
|
|
{ PseudoVSSUB_VV_MF4_MASK, VSSUB_VV }, // 9310
|
|
{ PseudoVSSUB_VV_MF8, VSSUB_VV }, // 9311
|
|
{ PseudoVSSUB_VV_MF8_MASK, VSSUB_VV }, // 9312
|
|
{ PseudoVSSUB_VX_M1, VSSUB_VX }, // 9313
|
|
{ PseudoVSSUB_VX_M1_MASK, VSSUB_VX }, // 9314
|
|
{ PseudoVSSUB_VX_M2, VSSUB_VX }, // 9315
|
|
{ PseudoVSSUB_VX_M2_MASK, VSSUB_VX }, // 9316
|
|
{ PseudoVSSUB_VX_M4, VSSUB_VX }, // 9317
|
|
{ PseudoVSSUB_VX_M4_MASK, VSSUB_VX }, // 9318
|
|
{ PseudoVSSUB_VX_M8, VSSUB_VX }, // 9319
|
|
{ PseudoVSSUB_VX_M8_MASK, VSSUB_VX }, // 9320
|
|
{ PseudoVSSUB_VX_MF2, VSSUB_VX }, // 9321
|
|
{ PseudoVSSUB_VX_MF2_MASK, VSSUB_VX }, // 9322
|
|
{ PseudoVSSUB_VX_MF4, VSSUB_VX }, // 9323
|
|
{ PseudoVSSUB_VX_MF4_MASK, VSSUB_VX }, // 9324
|
|
{ PseudoVSSUB_VX_MF8, VSSUB_VX }, // 9325
|
|
{ PseudoVSSUB_VX_MF8_MASK, VSSUB_VX }, // 9326
|
|
{ PseudoVSUB_VV_M1, VSUB_VV }, // 9327
|
|
{ PseudoVSUB_VV_M1_MASK, VSUB_VV }, // 9328
|
|
{ PseudoVSUB_VV_M2, VSUB_VV }, // 9329
|
|
{ PseudoVSUB_VV_M2_MASK, VSUB_VV }, // 9330
|
|
{ PseudoVSUB_VV_M4, VSUB_VV }, // 9331
|
|
{ PseudoVSUB_VV_M4_MASK, VSUB_VV }, // 9332
|
|
{ PseudoVSUB_VV_M8, VSUB_VV }, // 9333
|
|
{ PseudoVSUB_VV_M8_MASK, VSUB_VV }, // 9334
|
|
{ PseudoVSUB_VV_MF2, VSUB_VV }, // 9335
|
|
{ PseudoVSUB_VV_MF2_MASK, VSUB_VV }, // 9336
|
|
{ PseudoVSUB_VV_MF4, VSUB_VV }, // 9337
|
|
{ PseudoVSUB_VV_MF4_MASK, VSUB_VV }, // 9338
|
|
{ PseudoVSUB_VV_MF8, VSUB_VV }, // 9339
|
|
{ PseudoVSUB_VV_MF8_MASK, VSUB_VV }, // 9340
|
|
{ PseudoVSUB_VX_M1, VSUB_VX }, // 9341
|
|
{ PseudoVSUB_VX_M1_MASK, VSUB_VX }, // 9342
|
|
{ PseudoVSUB_VX_M2, VSUB_VX }, // 9343
|
|
{ PseudoVSUB_VX_M2_MASK, VSUB_VX }, // 9344
|
|
{ PseudoVSUB_VX_M4, VSUB_VX }, // 9345
|
|
{ PseudoVSUB_VX_M4_MASK, VSUB_VX }, // 9346
|
|
{ PseudoVSUB_VX_M8, VSUB_VX }, // 9347
|
|
{ PseudoVSUB_VX_M8_MASK, VSUB_VX }, // 9348
|
|
{ PseudoVSUB_VX_MF2, VSUB_VX }, // 9349
|
|
{ PseudoVSUB_VX_MF2_MASK, VSUB_VX }, // 9350
|
|
{ PseudoVSUB_VX_MF4, VSUB_VX }, // 9351
|
|
{ PseudoVSUB_VX_MF4_MASK, VSUB_VX }, // 9352
|
|
{ PseudoVSUB_VX_MF8, VSUB_VX }, // 9353
|
|
{ PseudoVSUB_VX_MF8_MASK, VSUB_VX }, // 9354
|
|
{ PseudoVSUXEI16_V_M1_M1, VSUXEI16_V }, // 9355
|
|
{ PseudoVSUXEI16_V_M1_M1_MASK, VSUXEI16_V }, // 9356
|
|
{ PseudoVSUXEI16_V_M1_M2, VSUXEI16_V }, // 9357
|
|
{ PseudoVSUXEI16_V_M1_M2_MASK, VSUXEI16_V }, // 9358
|
|
{ PseudoVSUXEI16_V_M1_M4, VSUXEI16_V }, // 9359
|
|
{ PseudoVSUXEI16_V_M1_M4_MASK, VSUXEI16_V }, // 9360
|
|
{ PseudoVSUXEI16_V_M1_MF2, VSUXEI16_V }, // 9361
|
|
{ PseudoVSUXEI16_V_M1_MF2_MASK, VSUXEI16_V }, // 9362
|
|
{ PseudoVSUXEI16_V_M2_M1, VSUXEI16_V }, // 9363
|
|
{ PseudoVSUXEI16_V_M2_M1_MASK, VSUXEI16_V }, // 9364
|
|
{ PseudoVSUXEI16_V_M2_M2, VSUXEI16_V }, // 9365
|
|
{ PseudoVSUXEI16_V_M2_M2_MASK, VSUXEI16_V }, // 9366
|
|
{ PseudoVSUXEI16_V_M2_M4, VSUXEI16_V }, // 9367
|
|
{ PseudoVSUXEI16_V_M2_M4_MASK, VSUXEI16_V }, // 9368
|
|
{ PseudoVSUXEI16_V_M2_M8, VSUXEI16_V }, // 9369
|
|
{ PseudoVSUXEI16_V_M2_M8_MASK, VSUXEI16_V }, // 9370
|
|
{ PseudoVSUXEI16_V_M4_M2, VSUXEI16_V }, // 9371
|
|
{ PseudoVSUXEI16_V_M4_M2_MASK, VSUXEI16_V }, // 9372
|
|
{ PseudoVSUXEI16_V_M4_M4, VSUXEI16_V }, // 9373
|
|
{ PseudoVSUXEI16_V_M4_M4_MASK, VSUXEI16_V }, // 9374
|
|
{ PseudoVSUXEI16_V_M4_M8, VSUXEI16_V }, // 9375
|
|
{ PseudoVSUXEI16_V_M4_M8_MASK, VSUXEI16_V }, // 9376
|
|
{ PseudoVSUXEI16_V_M8_M4, VSUXEI16_V }, // 9377
|
|
{ PseudoVSUXEI16_V_M8_M4_MASK, VSUXEI16_V }, // 9378
|
|
{ PseudoVSUXEI16_V_M8_M8, VSUXEI16_V }, // 9379
|
|
{ PseudoVSUXEI16_V_M8_M8_MASK, VSUXEI16_V }, // 9380
|
|
{ PseudoVSUXEI16_V_MF2_M1, VSUXEI16_V }, // 9381
|
|
{ PseudoVSUXEI16_V_MF2_M1_MASK, VSUXEI16_V }, // 9382
|
|
{ PseudoVSUXEI16_V_MF2_M2, VSUXEI16_V }, // 9383
|
|
{ PseudoVSUXEI16_V_MF2_M2_MASK, VSUXEI16_V }, // 9384
|
|
{ PseudoVSUXEI16_V_MF2_MF2, VSUXEI16_V }, // 9385
|
|
{ PseudoVSUXEI16_V_MF2_MF2_MASK, VSUXEI16_V }, // 9386
|
|
{ PseudoVSUXEI16_V_MF2_MF4, VSUXEI16_V }, // 9387
|
|
{ PseudoVSUXEI16_V_MF2_MF4_MASK, VSUXEI16_V }, // 9388
|
|
{ PseudoVSUXEI16_V_MF4_M1, VSUXEI16_V }, // 9389
|
|
{ PseudoVSUXEI16_V_MF4_M1_MASK, VSUXEI16_V }, // 9390
|
|
{ PseudoVSUXEI16_V_MF4_MF2, VSUXEI16_V }, // 9391
|
|
{ PseudoVSUXEI16_V_MF4_MF2_MASK, VSUXEI16_V }, // 9392
|
|
{ PseudoVSUXEI16_V_MF4_MF4, VSUXEI16_V }, // 9393
|
|
{ PseudoVSUXEI16_V_MF4_MF4_MASK, VSUXEI16_V }, // 9394
|
|
{ PseudoVSUXEI16_V_MF4_MF8, VSUXEI16_V }, // 9395
|
|
{ PseudoVSUXEI16_V_MF4_MF8_MASK, VSUXEI16_V }, // 9396
|
|
{ PseudoVSUXEI32_V_M1_M1, VSUXEI32_V }, // 9397
|
|
{ PseudoVSUXEI32_V_M1_M1_MASK, VSUXEI32_V }, // 9398
|
|
{ PseudoVSUXEI32_V_M1_M2, VSUXEI32_V }, // 9399
|
|
{ PseudoVSUXEI32_V_M1_M2_MASK, VSUXEI32_V }, // 9400
|
|
{ PseudoVSUXEI32_V_M1_MF2, VSUXEI32_V }, // 9401
|
|
{ PseudoVSUXEI32_V_M1_MF2_MASK, VSUXEI32_V }, // 9402
|
|
{ PseudoVSUXEI32_V_M1_MF4, VSUXEI32_V }, // 9403
|
|
{ PseudoVSUXEI32_V_M1_MF4_MASK, VSUXEI32_V }, // 9404
|
|
{ PseudoVSUXEI32_V_M2_M1, VSUXEI32_V }, // 9405
|
|
{ PseudoVSUXEI32_V_M2_M1_MASK, VSUXEI32_V }, // 9406
|
|
{ PseudoVSUXEI32_V_M2_M2, VSUXEI32_V }, // 9407
|
|
{ PseudoVSUXEI32_V_M2_M2_MASK, VSUXEI32_V }, // 9408
|
|
{ PseudoVSUXEI32_V_M2_M4, VSUXEI32_V }, // 9409
|
|
{ PseudoVSUXEI32_V_M2_M4_MASK, VSUXEI32_V }, // 9410
|
|
{ PseudoVSUXEI32_V_M2_MF2, VSUXEI32_V }, // 9411
|
|
{ PseudoVSUXEI32_V_M2_MF2_MASK, VSUXEI32_V }, // 9412
|
|
{ PseudoVSUXEI32_V_M4_M1, VSUXEI32_V }, // 9413
|
|
{ PseudoVSUXEI32_V_M4_M1_MASK, VSUXEI32_V }, // 9414
|
|
{ PseudoVSUXEI32_V_M4_M2, VSUXEI32_V }, // 9415
|
|
{ PseudoVSUXEI32_V_M4_M2_MASK, VSUXEI32_V }, // 9416
|
|
{ PseudoVSUXEI32_V_M4_M4, VSUXEI32_V }, // 9417
|
|
{ PseudoVSUXEI32_V_M4_M4_MASK, VSUXEI32_V }, // 9418
|
|
{ PseudoVSUXEI32_V_M4_M8, VSUXEI32_V }, // 9419
|
|
{ PseudoVSUXEI32_V_M4_M8_MASK, VSUXEI32_V }, // 9420
|
|
{ PseudoVSUXEI32_V_M8_M2, VSUXEI32_V }, // 9421
|
|
{ PseudoVSUXEI32_V_M8_M2_MASK, VSUXEI32_V }, // 9422
|
|
{ PseudoVSUXEI32_V_M8_M4, VSUXEI32_V }, // 9423
|
|
{ PseudoVSUXEI32_V_M8_M4_MASK, VSUXEI32_V }, // 9424
|
|
{ PseudoVSUXEI32_V_M8_M8, VSUXEI32_V }, // 9425
|
|
{ PseudoVSUXEI32_V_M8_M8_MASK, VSUXEI32_V }, // 9426
|
|
{ PseudoVSUXEI32_V_MF2_M1, VSUXEI32_V }, // 9427
|
|
{ PseudoVSUXEI32_V_MF2_M1_MASK, VSUXEI32_V }, // 9428
|
|
{ PseudoVSUXEI32_V_MF2_MF2, VSUXEI32_V }, // 9429
|
|
{ PseudoVSUXEI32_V_MF2_MF2_MASK, VSUXEI32_V }, // 9430
|
|
{ PseudoVSUXEI32_V_MF2_MF4, VSUXEI32_V }, // 9431
|
|
{ PseudoVSUXEI32_V_MF2_MF4_MASK, VSUXEI32_V }, // 9432
|
|
{ PseudoVSUXEI32_V_MF2_MF8, VSUXEI32_V }, // 9433
|
|
{ PseudoVSUXEI32_V_MF2_MF8_MASK, VSUXEI32_V }, // 9434
|
|
{ PseudoVSUXEI64_V_M1_M1, VSUXEI64_V }, // 9435
|
|
{ PseudoVSUXEI64_V_M1_M1_MASK, VSUXEI64_V }, // 9436
|
|
{ PseudoVSUXEI64_V_M1_MF2, VSUXEI64_V }, // 9437
|
|
{ PseudoVSUXEI64_V_M1_MF2_MASK, VSUXEI64_V }, // 9438
|
|
{ PseudoVSUXEI64_V_M1_MF4, VSUXEI64_V }, // 9439
|
|
{ PseudoVSUXEI64_V_M1_MF4_MASK, VSUXEI64_V }, // 9440
|
|
{ PseudoVSUXEI64_V_M1_MF8, VSUXEI64_V }, // 9441
|
|
{ PseudoVSUXEI64_V_M1_MF8_MASK, VSUXEI64_V }, // 9442
|
|
{ PseudoVSUXEI64_V_M2_M1, VSUXEI64_V }, // 9443
|
|
{ PseudoVSUXEI64_V_M2_M1_MASK, VSUXEI64_V }, // 9444
|
|
{ PseudoVSUXEI64_V_M2_M2, VSUXEI64_V }, // 9445
|
|
{ PseudoVSUXEI64_V_M2_M2_MASK, VSUXEI64_V }, // 9446
|
|
{ PseudoVSUXEI64_V_M2_MF2, VSUXEI64_V }, // 9447
|
|
{ PseudoVSUXEI64_V_M2_MF2_MASK, VSUXEI64_V }, // 9448
|
|
{ PseudoVSUXEI64_V_M2_MF4, VSUXEI64_V }, // 9449
|
|
{ PseudoVSUXEI64_V_M2_MF4_MASK, VSUXEI64_V }, // 9450
|
|
{ PseudoVSUXEI64_V_M4_M1, VSUXEI64_V }, // 9451
|
|
{ PseudoVSUXEI64_V_M4_M1_MASK, VSUXEI64_V }, // 9452
|
|
{ PseudoVSUXEI64_V_M4_M2, VSUXEI64_V }, // 9453
|
|
{ PseudoVSUXEI64_V_M4_M2_MASK, VSUXEI64_V }, // 9454
|
|
{ PseudoVSUXEI64_V_M4_M4, VSUXEI64_V }, // 9455
|
|
{ PseudoVSUXEI64_V_M4_M4_MASK, VSUXEI64_V }, // 9456
|
|
{ PseudoVSUXEI64_V_M4_MF2, VSUXEI64_V }, // 9457
|
|
{ PseudoVSUXEI64_V_M4_MF2_MASK, VSUXEI64_V }, // 9458
|
|
{ PseudoVSUXEI64_V_M8_M1, VSUXEI64_V }, // 9459
|
|
{ PseudoVSUXEI64_V_M8_M1_MASK, VSUXEI64_V }, // 9460
|
|
{ PseudoVSUXEI64_V_M8_M2, VSUXEI64_V }, // 9461
|
|
{ PseudoVSUXEI64_V_M8_M2_MASK, VSUXEI64_V }, // 9462
|
|
{ PseudoVSUXEI64_V_M8_M4, VSUXEI64_V }, // 9463
|
|
{ PseudoVSUXEI64_V_M8_M4_MASK, VSUXEI64_V }, // 9464
|
|
{ PseudoVSUXEI64_V_M8_M8, VSUXEI64_V }, // 9465
|
|
{ PseudoVSUXEI64_V_M8_M8_MASK, VSUXEI64_V }, // 9466
|
|
{ PseudoVSUXEI8_V_M1_M1, VSUXEI8_V }, // 9467
|
|
{ PseudoVSUXEI8_V_M1_M1_MASK, VSUXEI8_V }, // 9468
|
|
{ PseudoVSUXEI8_V_M1_M2, VSUXEI8_V }, // 9469
|
|
{ PseudoVSUXEI8_V_M1_M2_MASK, VSUXEI8_V }, // 9470
|
|
{ PseudoVSUXEI8_V_M1_M4, VSUXEI8_V }, // 9471
|
|
{ PseudoVSUXEI8_V_M1_M4_MASK, VSUXEI8_V }, // 9472
|
|
{ PseudoVSUXEI8_V_M1_M8, VSUXEI8_V }, // 9473
|
|
{ PseudoVSUXEI8_V_M1_M8_MASK, VSUXEI8_V }, // 9474
|
|
{ PseudoVSUXEI8_V_M2_M2, VSUXEI8_V }, // 9475
|
|
{ PseudoVSUXEI8_V_M2_M2_MASK, VSUXEI8_V }, // 9476
|
|
{ PseudoVSUXEI8_V_M2_M4, VSUXEI8_V }, // 9477
|
|
{ PseudoVSUXEI8_V_M2_M4_MASK, VSUXEI8_V }, // 9478
|
|
{ PseudoVSUXEI8_V_M2_M8, VSUXEI8_V }, // 9479
|
|
{ PseudoVSUXEI8_V_M2_M8_MASK, VSUXEI8_V }, // 9480
|
|
{ PseudoVSUXEI8_V_M4_M4, VSUXEI8_V }, // 9481
|
|
{ PseudoVSUXEI8_V_M4_M4_MASK, VSUXEI8_V }, // 9482
|
|
{ PseudoVSUXEI8_V_M4_M8, VSUXEI8_V }, // 9483
|
|
{ PseudoVSUXEI8_V_M4_M8_MASK, VSUXEI8_V }, // 9484
|
|
{ PseudoVSUXEI8_V_M8_M8, VSUXEI8_V }, // 9485
|
|
{ PseudoVSUXEI8_V_M8_M8_MASK, VSUXEI8_V }, // 9486
|
|
{ PseudoVSUXEI8_V_MF2_M1, VSUXEI8_V }, // 9487
|
|
{ PseudoVSUXEI8_V_MF2_M1_MASK, VSUXEI8_V }, // 9488
|
|
{ PseudoVSUXEI8_V_MF2_M2, VSUXEI8_V }, // 9489
|
|
{ PseudoVSUXEI8_V_MF2_M2_MASK, VSUXEI8_V }, // 9490
|
|
{ PseudoVSUXEI8_V_MF2_M4, VSUXEI8_V }, // 9491
|
|
{ PseudoVSUXEI8_V_MF2_M4_MASK, VSUXEI8_V }, // 9492
|
|
{ PseudoVSUXEI8_V_MF2_MF2, VSUXEI8_V }, // 9493
|
|
{ PseudoVSUXEI8_V_MF2_MF2_MASK, VSUXEI8_V }, // 9494
|
|
{ PseudoVSUXEI8_V_MF4_M1, VSUXEI8_V }, // 9495
|
|
{ PseudoVSUXEI8_V_MF4_M1_MASK, VSUXEI8_V }, // 9496
|
|
{ PseudoVSUXEI8_V_MF4_M2, VSUXEI8_V }, // 9497
|
|
{ PseudoVSUXEI8_V_MF4_M2_MASK, VSUXEI8_V }, // 9498
|
|
{ PseudoVSUXEI8_V_MF4_MF2, VSUXEI8_V }, // 9499
|
|
{ PseudoVSUXEI8_V_MF4_MF2_MASK, VSUXEI8_V }, // 9500
|
|
{ PseudoVSUXEI8_V_MF4_MF4, VSUXEI8_V }, // 9501
|
|
{ PseudoVSUXEI8_V_MF4_MF4_MASK, VSUXEI8_V }, // 9502
|
|
{ PseudoVSUXEI8_V_MF8_M1, VSUXEI8_V }, // 9503
|
|
{ PseudoVSUXEI8_V_MF8_M1_MASK, VSUXEI8_V }, // 9504
|
|
{ PseudoVSUXEI8_V_MF8_MF2, VSUXEI8_V }, // 9505
|
|
{ PseudoVSUXEI8_V_MF8_MF2_MASK, VSUXEI8_V }, // 9506
|
|
{ PseudoVSUXEI8_V_MF8_MF4, VSUXEI8_V }, // 9507
|
|
{ PseudoVSUXEI8_V_MF8_MF4_MASK, VSUXEI8_V }, // 9508
|
|
{ PseudoVSUXEI8_V_MF8_MF8, VSUXEI8_V }, // 9509
|
|
{ PseudoVSUXEI8_V_MF8_MF8_MASK, VSUXEI8_V }, // 9510
|
|
{ PseudoVSUXSEG2EI16_V_M1_M1, VSUXSEG2EI16_V }, // 9511
|
|
{ PseudoVSUXSEG2EI16_V_M1_M1_MASK, VSUXSEG2EI16_V }, // 9512
|
|
{ PseudoVSUXSEG2EI16_V_M1_M2, VSUXSEG2EI16_V }, // 9513
|
|
{ PseudoVSUXSEG2EI16_V_M1_M2_MASK, VSUXSEG2EI16_V }, // 9514
|
|
{ PseudoVSUXSEG2EI16_V_M1_M4, VSUXSEG2EI16_V }, // 9515
|
|
{ PseudoVSUXSEG2EI16_V_M1_M4_MASK, VSUXSEG2EI16_V }, // 9516
|
|
{ PseudoVSUXSEG2EI16_V_M1_MF2, VSUXSEG2EI16_V }, // 9517
|
|
{ PseudoVSUXSEG2EI16_V_M1_MF2_MASK, VSUXSEG2EI16_V }, // 9518
|
|
{ PseudoVSUXSEG2EI16_V_M2_M1, VSUXSEG2EI16_V }, // 9519
|
|
{ PseudoVSUXSEG2EI16_V_M2_M1_MASK, VSUXSEG2EI16_V }, // 9520
|
|
{ PseudoVSUXSEG2EI16_V_M2_M2, VSUXSEG2EI16_V }, // 9521
|
|
{ PseudoVSUXSEG2EI16_V_M2_M2_MASK, VSUXSEG2EI16_V }, // 9522
|
|
{ PseudoVSUXSEG2EI16_V_M2_M4, VSUXSEG2EI16_V }, // 9523
|
|
{ PseudoVSUXSEG2EI16_V_M2_M4_MASK, VSUXSEG2EI16_V }, // 9524
|
|
{ PseudoVSUXSEG2EI16_V_M4_M2, VSUXSEG2EI16_V }, // 9525
|
|
{ PseudoVSUXSEG2EI16_V_M4_M2_MASK, VSUXSEG2EI16_V }, // 9526
|
|
{ PseudoVSUXSEG2EI16_V_M4_M4, VSUXSEG2EI16_V }, // 9527
|
|
{ PseudoVSUXSEG2EI16_V_M4_M4_MASK, VSUXSEG2EI16_V }, // 9528
|
|
{ PseudoVSUXSEG2EI16_V_M8_M4, VSUXSEG2EI16_V }, // 9529
|
|
{ PseudoVSUXSEG2EI16_V_M8_M4_MASK, VSUXSEG2EI16_V }, // 9530
|
|
{ PseudoVSUXSEG2EI16_V_MF2_M1, VSUXSEG2EI16_V }, // 9531
|
|
{ PseudoVSUXSEG2EI16_V_MF2_M1_MASK, VSUXSEG2EI16_V }, // 9532
|
|
{ PseudoVSUXSEG2EI16_V_MF2_M2, VSUXSEG2EI16_V }, // 9533
|
|
{ PseudoVSUXSEG2EI16_V_MF2_M2_MASK, VSUXSEG2EI16_V }, // 9534
|
|
{ PseudoVSUXSEG2EI16_V_MF2_MF2, VSUXSEG2EI16_V }, // 9535
|
|
{ PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, VSUXSEG2EI16_V }, // 9536
|
|
{ PseudoVSUXSEG2EI16_V_MF2_MF4, VSUXSEG2EI16_V }, // 9537
|
|
{ PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, VSUXSEG2EI16_V }, // 9538
|
|
{ PseudoVSUXSEG2EI16_V_MF4_M1, VSUXSEG2EI16_V }, // 9539
|
|
{ PseudoVSUXSEG2EI16_V_MF4_M1_MASK, VSUXSEG2EI16_V }, // 9540
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF2, VSUXSEG2EI16_V }, // 9541
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, VSUXSEG2EI16_V }, // 9542
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF4, VSUXSEG2EI16_V }, // 9543
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, VSUXSEG2EI16_V }, // 9544
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF8, VSUXSEG2EI16_V }, // 9545
|
|
{ PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, VSUXSEG2EI16_V }, // 9546
|
|
{ PseudoVSUXSEG2EI32_V_M1_M1, VSUXSEG2EI32_V }, // 9547
|
|
{ PseudoVSUXSEG2EI32_V_M1_M1_MASK, VSUXSEG2EI32_V }, // 9548
|
|
{ PseudoVSUXSEG2EI32_V_M1_M2, VSUXSEG2EI32_V }, // 9549
|
|
{ PseudoVSUXSEG2EI32_V_M1_M2_MASK, VSUXSEG2EI32_V }, // 9550
|
|
{ PseudoVSUXSEG2EI32_V_M1_MF2, VSUXSEG2EI32_V }, // 9551
|
|
{ PseudoVSUXSEG2EI32_V_M1_MF2_MASK, VSUXSEG2EI32_V }, // 9552
|
|
{ PseudoVSUXSEG2EI32_V_M1_MF4, VSUXSEG2EI32_V }, // 9553
|
|
{ PseudoVSUXSEG2EI32_V_M1_MF4_MASK, VSUXSEG2EI32_V }, // 9554
|
|
{ PseudoVSUXSEG2EI32_V_M2_M1, VSUXSEG2EI32_V }, // 9555
|
|
{ PseudoVSUXSEG2EI32_V_M2_M1_MASK, VSUXSEG2EI32_V }, // 9556
|
|
{ PseudoVSUXSEG2EI32_V_M2_M2, VSUXSEG2EI32_V }, // 9557
|
|
{ PseudoVSUXSEG2EI32_V_M2_M2_MASK, VSUXSEG2EI32_V }, // 9558
|
|
{ PseudoVSUXSEG2EI32_V_M2_M4, VSUXSEG2EI32_V }, // 9559
|
|
{ PseudoVSUXSEG2EI32_V_M2_M4_MASK, VSUXSEG2EI32_V }, // 9560
|
|
{ PseudoVSUXSEG2EI32_V_M2_MF2, VSUXSEG2EI32_V }, // 9561
|
|
{ PseudoVSUXSEG2EI32_V_M2_MF2_MASK, VSUXSEG2EI32_V }, // 9562
|
|
{ PseudoVSUXSEG2EI32_V_M4_M1, VSUXSEG2EI32_V }, // 9563
|
|
{ PseudoVSUXSEG2EI32_V_M4_M1_MASK, VSUXSEG2EI32_V }, // 9564
|
|
{ PseudoVSUXSEG2EI32_V_M4_M2, VSUXSEG2EI32_V }, // 9565
|
|
{ PseudoVSUXSEG2EI32_V_M4_M2_MASK, VSUXSEG2EI32_V }, // 9566
|
|
{ PseudoVSUXSEG2EI32_V_M4_M4, VSUXSEG2EI32_V }, // 9567
|
|
{ PseudoVSUXSEG2EI32_V_M4_M4_MASK, VSUXSEG2EI32_V }, // 9568
|
|
{ PseudoVSUXSEG2EI32_V_M8_M2, VSUXSEG2EI32_V }, // 9569
|
|
{ PseudoVSUXSEG2EI32_V_M8_M2_MASK, VSUXSEG2EI32_V }, // 9570
|
|
{ PseudoVSUXSEG2EI32_V_M8_M4, VSUXSEG2EI32_V }, // 9571
|
|
{ PseudoVSUXSEG2EI32_V_M8_M4_MASK, VSUXSEG2EI32_V }, // 9572
|
|
{ PseudoVSUXSEG2EI32_V_MF2_M1, VSUXSEG2EI32_V }, // 9573
|
|
{ PseudoVSUXSEG2EI32_V_MF2_M1_MASK, VSUXSEG2EI32_V }, // 9574
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF2, VSUXSEG2EI32_V }, // 9575
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, VSUXSEG2EI32_V }, // 9576
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF4, VSUXSEG2EI32_V }, // 9577
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, VSUXSEG2EI32_V }, // 9578
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF8, VSUXSEG2EI32_V }, // 9579
|
|
{ PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, VSUXSEG2EI32_V }, // 9580
|
|
{ PseudoVSUXSEG2EI64_V_M1_M1, VSUXSEG2EI64_V }, // 9581
|
|
{ PseudoVSUXSEG2EI64_V_M1_M1_MASK, VSUXSEG2EI64_V }, // 9582
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF2, VSUXSEG2EI64_V }, // 9583
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF2_MASK, VSUXSEG2EI64_V }, // 9584
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF4, VSUXSEG2EI64_V }, // 9585
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF4_MASK, VSUXSEG2EI64_V }, // 9586
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF8, VSUXSEG2EI64_V }, // 9587
|
|
{ PseudoVSUXSEG2EI64_V_M1_MF8_MASK, VSUXSEG2EI64_V }, // 9588
|
|
{ PseudoVSUXSEG2EI64_V_M2_M1, VSUXSEG2EI64_V }, // 9589
|
|
{ PseudoVSUXSEG2EI64_V_M2_M1_MASK, VSUXSEG2EI64_V }, // 9590
|
|
{ PseudoVSUXSEG2EI64_V_M2_M2, VSUXSEG2EI64_V }, // 9591
|
|
{ PseudoVSUXSEG2EI64_V_M2_M2_MASK, VSUXSEG2EI64_V }, // 9592
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF2, VSUXSEG2EI64_V }, // 9593
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF2_MASK, VSUXSEG2EI64_V }, // 9594
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF4, VSUXSEG2EI64_V }, // 9595
|
|
{ PseudoVSUXSEG2EI64_V_M2_MF4_MASK, VSUXSEG2EI64_V }, // 9596
|
|
{ PseudoVSUXSEG2EI64_V_M4_M1, VSUXSEG2EI64_V }, // 9597
|
|
{ PseudoVSUXSEG2EI64_V_M4_M1_MASK, VSUXSEG2EI64_V }, // 9598
|
|
{ PseudoVSUXSEG2EI64_V_M4_M2, VSUXSEG2EI64_V }, // 9599
|
|
{ PseudoVSUXSEG2EI64_V_M4_M2_MASK, VSUXSEG2EI64_V }, // 9600
|
|
{ PseudoVSUXSEG2EI64_V_M4_M4, VSUXSEG2EI64_V }, // 9601
|
|
{ PseudoVSUXSEG2EI64_V_M4_M4_MASK, VSUXSEG2EI64_V }, // 9602
|
|
{ PseudoVSUXSEG2EI64_V_M4_MF2, VSUXSEG2EI64_V }, // 9603
|
|
{ PseudoVSUXSEG2EI64_V_M4_MF2_MASK, VSUXSEG2EI64_V }, // 9604
|
|
{ PseudoVSUXSEG2EI64_V_M8_M1, VSUXSEG2EI64_V }, // 9605
|
|
{ PseudoVSUXSEG2EI64_V_M8_M1_MASK, VSUXSEG2EI64_V }, // 9606
|
|
{ PseudoVSUXSEG2EI64_V_M8_M2, VSUXSEG2EI64_V }, // 9607
|
|
{ PseudoVSUXSEG2EI64_V_M8_M2_MASK, VSUXSEG2EI64_V }, // 9608
|
|
{ PseudoVSUXSEG2EI64_V_M8_M4, VSUXSEG2EI64_V }, // 9609
|
|
{ PseudoVSUXSEG2EI64_V_M8_M4_MASK, VSUXSEG2EI64_V }, // 9610
|
|
{ PseudoVSUXSEG2EI8_V_M1_M1, VSUXSEG2EI8_V }, // 9611
|
|
{ PseudoVSUXSEG2EI8_V_M1_M1_MASK, VSUXSEG2EI8_V }, // 9612
|
|
{ PseudoVSUXSEG2EI8_V_M1_M2, VSUXSEG2EI8_V }, // 9613
|
|
{ PseudoVSUXSEG2EI8_V_M1_M2_MASK, VSUXSEG2EI8_V }, // 9614
|
|
{ PseudoVSUXSEG2EI8_V_M1_M4, VSUXSEG2EI8_V }, // 9615
|
|
{ PseudoVSUXSEG2EI8_V_M1_M4_MASK, VSUXSEG2EI8_V }, // 9616
|
|
{ PseudoVSUXSEG2EI8_V_M2_M2, VSUXSEG2EI8_V }, // 9617
|
|
{ PseudoVSUXSEG2EI8_V_M2_M2_MASK, VSUXSEG2EI8_V }, // 9618
|
|
{ PseudoVSUXSEG2EI8_V_M2_M4, VSUXSEG2EI8_V }, // 9619
|
|
{ PseudoVSUXSEG2EI8_V_M2_M4_MASK, VSUXSEG2EI8_V }, // 9620
|
|
{ PseudoVSUXSEG2EI8_V_M4_M4, VSUXSEG2EI8_V }, // 9621
|
|
{ PseudoVSUXSEG2EI8_V_M4_M4_MASK, VSUXSEG2EI8_V }, // 9622
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M1, VSUXSEG2EI8_V }, // 9623
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M1_MASK, VSUXSEG2EI8_V }, // 9624
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M2, VSUXSEG2EI8_V }, // 9625
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M2_MASK, VSUXSEG2EI8_V }, // 9626
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M4, VSUXSEG2EI8_V }, // 9627
|
|
{ PseudoVSUXSEG2EI8_V_MF2_M4_MASK, VSUXSEG2EI8_V }, // 9628
|
|
{ PseudoVSUXSEG2EI8_V_MF2_MF2, VSUXSEG2EI8_V }, // 9629
|
|
{ PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, VSUXSEG2EI8_V }, // 9630
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M1, VSUXSEG2EI8_V }, // 9631
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M1_MASK, VSUXSEG2EI8_V }, // 9632
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M2, VSUXSEG2EI8_V }, // 9633
|
|
{ PseudoVSUXSEG2EI8_V_MF4_M2_MASK, VSUXSEG2EI8_V }, // 9634
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF2, VSUXSEG2EI8_V }, // 9635
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, VSUXSEG2EI8_V }, // 9636
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF4, VSUXSEG2EI8_V }, // 9637
|
|
{ PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, VSUXSEG2EI8_V }, // 9638
|
|
{ PseudoVSUXSEG2EI8_V_MF8_M1, VSUXSEG2EI8_V }, // 9639
|
|
{ PseudoVSUXSEG2EI8_V_MF8_M1_MASK, VSUXSEG2EI8_V }, // 9640
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF2, VSUXSEG2EI8_V }, // 9641
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, VSUXSEG2EI8_V }, // 9642
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF4, VSUXSEG2EI8_V }, // 9643
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, VSUXSEG2EI8_V }, // 9644
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF8, VSUXSEG2EI8_V }, // 9645
|
|
{ PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, VSUXSEG2EI8_V }, // 9646
|
|
{ PseudoVSUXSEG3EI16_V_M1_M1, VSUXSEG3EI16_V }, // 9647
|
|
{ PseudoVSUXSEG3EI16_V_M1_M1_MASK, VSUXSEG3EI16_V }, // 9648
|
|
{ PseudoVSUXSEG3EI16_V_M1_M2, VSUXSEG3EI16_V }, // 9649
|
|
{ PseudoVSUXSEG3EI16_V_M1_M2_MASK, VSUXSEG3EI16_V }, // 9650
|
|
{ PseudoVSUXSEG3EI16_V_M1_MF2, VSUXSEG3EI16_V }, // 9651
|
|
{ PseudoVSUXSEG3EI16_V_M1_MF2_MASK, VSUXSEG3EI16_V }, // 9652
|
|
{ PseudoVSUXSEG3EI16_V_M2_M1, VSUXSEG3EI16_V }, // 9653
|
|
{ PseudoVSUXSEG3EI16_V_M2_M1_MASK, VSUXSEG3EI16_V }, // 9654
|
|
{ PseudoVSUXSEG3EI16_V_M2_M2, VSUXSEG3EI16_V }, // 9655
|
|
{ PseudoVSUXSEG3EI16_V_M2_M2_MASK, VSUXSEG3EI16_V }, // 9656
|
|
{ PseudoVSUXSEG3EI16_V_M4_M2, VSUXSEG3EI16_V }, // 9657
|
|
{ PseudoVSUXSEG3EI16_V_M4_M2_MASK, VSUXSEG3EI16_V }, // 9658
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M1, VSUXSEG3EI16_V }, // 9659
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M1_MASK, VSUXSEG3EI16_V }, // 9660
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M2, VSUXSEG3EI16_V }, // 9661
|
|
{ PseudoVSUXSEG3EI16_V_MF2_M2_MASK, VSUXSEG3EI16_V }, // 9662
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF2, VSUXSEG3EI16_V }, // 9663
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, VSUXSEG3EI16_V }, // 9664
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF4, VSUXSEG3EI16_V }, // 9665
|
|
{ PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, VSUXSEG3EI16_V }, // 9666
|
|
{ PseudoVSUXSEG3EI16_V_MF4_M1, VSUXSEG3EI16_V }, // 9667
|
|
{ PseudoVSUXSEG3EI16_V_MF4_M1_MASK, VSUXSEG3EI16_V }, // 9668
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF2, VSUXSEG3EI16_V }, // 9669
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, VSUXSEG3EI16_V }, // 9670
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF4, VSUXSEG3EI16_V }, // 9671
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, VSUXSEG3EI16_V }, // 9672
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF8, VSUXSEG3EI16_V }, // 9673
|
|
{ PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, VSUXSEG3EI16_V }, // 9674
|
|
{ PseudoVSUXSEG3EI32_V_M1_M1, VSUXSEG3EI32_V }, // 9675
|
|
{ PseudoVSUXSEG3EI32_V_M1_M1_MASK, VSUXSEG3EI32_V }, // 9676
|
|
{ PseudoVSUXSEG3EI32_V_M1_M2, VSUXSEG3EI32_V }, // 9677
|
|
{ PseudoVSUXSEG3EI32_V_M1_M2_MASK, VSUXSEG3EI32_V }, // 9678
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF2, VSUXSEG3EI32_V }, // 9679
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF2_MASK, VSUXSEG3EI32_V }, // 9680
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF4, VSUXSEG3EI32_V }, // 9681
|
|
{ PseudoVSUXSEG3EI32_V_M1_MF4_MASK, VSUXSEG3EI32_V }, // 9682
|
|
{ PseudoVSUXSEG3EI32_V_M2_M1, VSUXSEG3EI32_V }, // 9683
|
|
{ PseudoVSUXSEG3EI32_V_M2_M1_MASK, VSUXSEG3EI32_V }, // 9684
|
|
{ PseudoVSUXSEG3EI32_V_M2_M2, VSUXSEG3EI32_V }, // 9685
|
|
{ PseudoVSUXSEG3EI32_V_M2_M2_MASK, VSUXSEG3EI32_V }, // 9686
|
|
{ PseudoVSUXSEG3EI32_V_M2_MF2, VSUXSEG3EI32_V }, // 9687
|
|
{ PseudoVSUXSEG3EI32_V_M2_MF2_MASK, VSUXSEG3EI32_V }, // 9688
|
|
{ PseudoVSUXSEG3EI32_V_M4_M1, VSUXSEG3EI32_V }, // 9689
|
|
{ PseudoVSUXSEG3EI32_V_M4_M1_MASK, VSUXSEG3EI32_V }, // 9690
|
|
{ PseudoVSUXSEG3EI32_V_M4_M2, VSUXSEG3EI32_V }, // 9691
|
|
{ PseudoVSUXSEG3EI32_V_M4_M2_MASK, VSUXSEG3EI32_V }, // 9692
|
|
{ PseudoVSUXSEG3EI32_V_M8_M2, VSUXSEG3EI32_V }, // 9693
|
|
{ PseudoVSUXSEG3EI32_V_M8_M2_MASK, VSUXSEG3EI32_V }, // 9694
|
|
{ PseudoVSUXSEG3EI32_V_MF2_M1, VSUXSEG3EI32_V }, // 9695
|
|
{ PseudoVSUXSEG3EI32_V_MF2_M1_MASK, VSUXSEG3EI32_V }, // 9696
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF2, VSUXSEG3EI32_V }, // 9697
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, VSUXSEG3EI32_V }, // 9698
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF4, VSUXSEG3EI32_V }, // 9699
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, VSUXSEG3EI32_V }, // 9700
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF8, VSUXSEG3EI32_V }, // 9701
|
|
{ PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, VSUXSEG3EI32_V }, // 9702
|
|
{ PseudoVSUXSEG3EI64_V_M1_M1, VSUXSEG3EI64_V }, // 9703
|
|
{ PseudoVSUXSEG3EI64_V_M1_M1_MASK, VSUXSEG3EI64_V }, // 9704
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF2, VSUXSEG3EI64_V }, // 9705
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF2_MASK, VSUXSEG3EI64_V }, // 9706
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF4, VSUXSEG3EI64_V }, // 9707
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF4_MASK, VSUXSEG3EI64_V }, // 9708
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF8, VSUXSEG3EI64_V }, // 9709
|
|
{ PseudoVSUXSEG3EI64_V_M1_MF8_MASK, VSUXSEG3EI64_V }, // 9710
|
|
{ PseudoVSUXSEG3EI64_V_M2_M1, VSUXSEG3EI64_V }, // 9711
|
|
{ PseudoVSUXSEG3EI64_V_M2_M1_MASK, VSUXSEG3EI64_V }, // 9712
|
|
{ PseudoVSUXSEG3EI64_V_M2_M2, VSUXSEG3EI64_V }, // 9713
|
|
{ PseudoVSUXSEG3EI64_V_M2_M2_MASK, VSUXSEG3EI64_V }, // 9714
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF2, VSUXSEG3EI64_V }, // 9715
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF2_MASK, VSUXSEG3EI64_V }, // 9716
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF4, VSUXSEG3EI64_V }, // 9717
|
|
{ PseudoVSUXSEG3EI64_V_M2_MF4_MASK, VSUXSEG3EI64_V }, // 9718
|
|
{ PseudoVSUXSEG3EI64_V_M4_M1, VSUXSEG3EI64_V }, // 9719
|
|
{ PseudoVSUXSEG3EI64_V_M4_M1_MASK, VSUXSEG3EI64_V }, // 9720
|
|
{ PseudoVSUXSEG3EI64_V_M4_M2, VSUXSEG3EI64_V }, // 9721
|
|
{ PseudoVSUXSEG3EI64_V_M4_M2_MASK, VSUXSEG3EI64_V }, // 9722
|
|
{ PseudoVSUXSEG3EI64_V_M4_MF2, VSUXSEG3EI64_V }, // 9723
|
|
{ PseudoVSUXSEG3EI64_V_M4_MF2_MASK, VSUXSEG3EI64_V }, // 9724
|
|
{ PseudoVSUXSEG3EI64_V_M8_M1, VSUXSEG3EI64_V }, // 9725
|
|
{ PseudoVSUXSEG3EI64_V_M8_M1_MASK, VSUXSEG3EI64_V }, // 9726
|
|
{ PseudoVSUXSEG3EI64_V_M8_M2, VSUXSEG3EI64_V }, // 9727
|
|
{ PseudoVSUXSEG3EI64_V_M8_M2_MASK, VSUXSEG3EI64_V }, // 9728
|
|
{ PseudoVSUXSEG3EI8_V_M1_M1, VSUXSEG3EI8_V }, // 9729
|
|
{ PseudoVSUXSEG3EI8_V_M1_M1_MASK, VSUXSEG3EI8_V }, // 9730
|
|
{ PseudoVSUXSEG3EI8_V_M1_M2, VSUXSEG3EI8_V }, // 9731
|
|
{ PseudoVSUXSEG3EI8_V_M1_M2_MASK, VSUXSEG3EI8_V }, // 9732
|
|
{ PseudoVSUXSEG3EI8_V_M2_M2, VSUXSEG3EI8_V }, // 9733
|
|
{ PseudoVSUXSEG3EI8_V_M2_M2_MASK, VSUXSEG3EI8_V }, // 9734
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M1, VSUXSEG3EI8_V }, // 9735
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M1_MASK, VSUXSEG3EI8_V }, // 9736
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M2, VSUXSEG3EI8_V }, // 9737
|
|
{ PseudoVSUXSEG3EI8_V_MF2_M2_MASK, VSUXSEG3EI8_V }, // 9738
|
|
{ PseudoVSUXSEG3EI8_V_MF2_MF2, VSUXSEG3EI8_V }, // 9739
|
|
{ PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, VSUXSEG3EI8_V }, // 9740
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M1, VSUXSEG3EI8_V }, // 9741
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M1_MASK, VSUXSEG3EI8_V }, // 9742
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M2, VSUXSEG3EI8_V }, // 9743
|
|
{ PseudoVSUXSEG3EI8_V_MF4_M2_MASK, VSUXSEG3EI8_V }, // 9744
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF2, VSUXSEG3EI8_V }, // 9745
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, VSUXSEG3EI8_V }, // 9746
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF4, VSUXSEG3EI8_V }, // 9747
|
|
{ PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, VSUXSEG3EI8_V }, // 9748
|
|
{ PseudoVSUXSEG3EI8_V_MF8_M1, VSUXSEG3EI8_V }, // 9749
|
|
{ PseudoVSUXSEG3EI8_V_MF8_M1_MASK, VSUXSEG3EI8_V }, // 9750
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF2, VSUXSEG3EI8_V }, // 9751
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, VSUXSEG3EI8_V }, // 9752
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF4, VSUXSEG3EI8_V }, // 9753
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, VSUXSEG3EI8_V }, // 9754
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF8, VSUXSEG3EI8_V }, // 9755
|
|
{ PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, VSUXSEG3EI8_V }, // 9756
|
|
{ PseudoVSUXSEG4EI16_V_M1_M1, VSUXSEG4EI16_V }, // 9757
|
|
{ PseudoVSUXSEG4EI16_V_M1_M1_MASK, VSUXSEG4EI16_V }, // 9758
|
|
{ PseudoVSUXSEG4EI16_V_M1_M2, VSUXSEG4EI16_V }, // 9759
|
|
{ PseudoVSUXSEG4EI16_V_M1_M2_MASK, VSUXSEG4EI16_V }, // 9760
|
|
{ PseudoVSUXSEG4EI16_V_M1_MF2, VSUXSEG4EI16_V }, // 9761
|
|
{ PseudoVSUXSEG4EI16_V_M1_MF2_MASK, VSUXSEG4EI16_V }, // 9762
|
|
{ PseudoVSUXSEG4EI16_V_M2_M1, VSUXSEG4EI16_V }, // 9763
|
|
{ PseudoVSUXSEG4EI16_V_M2_M1_MASK, VSUXSEG4EI16_V }, // 9764
|
|
{ PseudoVSUXSEG4EI16_V_M2_M2, VSUXSEG4EI16_V }, // 9765
|
|
{ PseudoVSUXSEG4EI16_V_M2_M2_MASK, VSUXSEG4EI16_V }, // 9766
|
|
{ PseudoVSUXSEG4EI16_V_M4_M2, VSUXSEG4EI16_V }, // 9767
|
|
{ PseudoVSUXSEG4EI16_V_M4_M2_MASK, VSUXSEG4EI16_V }, // 9768
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M1, VSUXSEG4EI16_V }, // 9769
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M1_MASK, VSUXSEG4EI16_V }, // 9770
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M2, VSUXSEG4EI16_V }, // 9771
|
|
{ PseudoVSUXSEG4EI16_V_MF2_M2_MASK, VSUXSEG4EI16_V }, // 9772
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF2, VSUXSEG4EI16_V }, // 9773
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, VSUXSEG4EI16_V }, // 9774
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF4, VSUXSEG4EI16_V }, // 9775
|
|
{ PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, VSUXSEG4EI16_V }, // 9776
|
|
{ PseudoVSUXSEG4EI16_V_MF4_M1, VSUXSEG4EI16_V }, // 9777
|
|
{ PseudoVSUXSEG4EI16_V_MF4_M1_MASK, VSUXSEG4EI16_V }, // 9778
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF2, VSUXSEG4EI16_V }, // 9779
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, VSUXSEG4EI16_V }, // 9780
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF4, VSUXSEG4EI16_V }, // 9781
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, VSUXSEG4EI16_V }, // 9782
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF8, VSUXSEG4EI16_V }, // 9783
|
|
{ PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, VSUXSEG4EI16_V }, // 9784
|
|
{ PseudoVSUXSEG4EI32_V_M1_M1, VSUXSEG4EI32_V }, // 9785
|
|
{ PseudoVSUXSEG4EI32_V_M1_M1_MASK, VSUXSEG4EI32_V }, // 9786
|
|
{ PseudoVSUXSEG4EI32_V_M1_M2, VSUXSEG4EI32_V }, // 9787
|
|
{ PseudoVSUXSEG4EI32_V_M1_M2_MASK, VSUXSEG4EI32_V }, // 9788
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF2, VSUXSEG4EI32_V }, // 9789
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF2_MASK, VSUXSEG4EI32_V }, // 9790
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF4, VSUXSEG4EI32_V }, // 9791
|
|
{ PseudoVSUXSEG4EI32_V_M1_MF4_MASK, VSUXSEG4EI32_V }, // 9792
|
|
{ PseudoVSUXSEG4EI32_V_M2_M1, VSUXSEG4EI32_V }, // 9793
|
|
{ PseudoVSUXSEG4EI32_V_M2_M1_MASK, VSUXSEG4EI32_V }, // 9794
|
|
{ PseudoVSUXSEG4EI32_V_M2_M2, VSUXSEG4EI32_V }, // 9795
|
|
{ PseudoVSUXSEG4EI32_V_M2_M2_MASK, VSUXSEG4EI32_V }, // 9796
|
|
{ PseudoVSUXSEG4EI32_V_M2_MF2, VSUXSEG4EI32_V }, // 9797
|
|
{ PseudoVSUXSEG4EI32_V_M2_MF2_MASK, VSUXSEG4EI32_V }, // 9798
|
|
{ PseudoVSUXSEG4EI32_V_M4_M1, VSUXSEG4EI32_V }, // 9799
|
|
{ PseudoVSUXSEG4EI32_V_M4_M1_MASK, VSUXSEG4EI32_V }, // 9800
|
|
{ PseudoVSUXSEG4EI32_V_M4_M2, VSUXSEG4EI32_V }, // 9801
|
|
{ PseudoVSUXSEG4EI32_V_M4_M2_MASK, VSUXSEG4EI32_V }, // 9802
|
|
{ PseudoVSUXSEG4EI32_V_M8_M2, VSUXSEG4EI32_V }, // 9803
|
|
{ PseudoVSUXSEG4EI32_V_M8_M2_MASK, VSUXSEG4EI32_V }, // 9804
|
|
{ PseudoVSUXSEG4EI32_V_MF2_M1, VSUXSEG4EI32_V }, // 9805
|
|
{ PseudoVSUXSEG4EI32_V_MF2_M1_MASK, VSUXSEG4EI32_V }, // 9806
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF2, VSUXSEG4EI32_V }, // 9807
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, VSUXSEG4EI32_V }, // 9808
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF4, VSUXSEG4EI32_V }, // 9809
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, VSUXSEG4EI32_V }, // 9810
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF8, VSUXSEG4EI32_V }, // 9811
|
|
{ PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, VSUXSEG4EI32_V }, // 9812
|
|
{ PseudoVSUXSEG4EI64_V_M1_M1, VSUXSEG4EI64_V }, // 9813
|
|
{ PseudoVSUXSEG4EI64_V_M1_M1_MASK, VSUXSEG4EI64_V }, // 9814
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF2, VSUXSEG4EI64_V }, // 9815
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF2_MASK, VSUXSEG4EI64_V }, // 9816
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF4, VSUXSEG4EI64_V }, // 9817
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF4_MASK, VSUXSEG4EI64_V }, // 9818
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF8, VSUXSEG4EI64_V }, // 9819
|
|
{ PseudoVSUXSEG4EI64_V_M1_MF8_MASK, VSUXSEG4EI64_V }, // 9820
|
|
{ PseudoVSUXSEG4EI64_V_M2_M1, VSUXSEG4EI64_V }, // 9821
|
|
{ PseudoVSUXSEG4EI64_V_M2_M1_MASK, VSUXSEG4EI64_V }, // 9822
|
|
{ PseudoVSUXSEG4EI64_V_M2_M2, VSUXSEG4EI64_V }, // 9823
|
|
{ PseudoVSUXSEG4EI64_V_M2_M2_MASK, VSUXSEG4EI64_V }, // 9824
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF2, VSUXSEG4EI64_V }, // 9825
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF2_MASK, VSUXSEG4EI64_V }, // 9826
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF4, VSUXSEG4EI64_V }, // 9827
|
|
{ PseudoVSUXSEG4EI64_V_M2_MF4_MASK, VSUXSEG4EI64_V }, // 9828
|
|
{ PseudoVSUXSEG4EI64_V_M4_M1, VSUXSEG4EI64_V }, // 9829
|
|
{ PseudoVSUXSEG4EI64_V_M4_M1_MASK, VSUXSEG4EI64_V }, // 9830
|
|
{ PseudoVSUXSEG4EI64_V_M4_M2, VSUXSEG4EI64_V }, // 9831
|
|
{ PseudoVSUXSEG4EI64_V_M4_M2_MASK, VSUXSEG4EI64_V }, // 9832
|
|
{ PseudoVSUXSEG4EI64_V_M4_MF2, VSUXSEG4EI64_V }, // 9833
|
|
{ PseudoVSUXSEG4EI64_V_M4_MF2_MASK, VSUXSEG4EI64_V }, // 9834
|
|
{ PseudoVSUXSEG4EI64_V_M8_M1, VSUXSEG4EI64_V }, // 9835
|
|
{ PseudoVSUXSEG4EI64_V_M8_M1_MASK, VSUXSEG4EI64_V }, // 9836
|
|
{ PseudoVSUXSEG4EI64_V_M8_M2, VSUXSEG4EI64_V }, // 9837
|
|
{ PseudoVSUXSEG4EI64_V_M8_M2_MASK, VSUXSEG4EI64_V }, // 9838
|
|
{ PseudoVSUXSEG4EI8_V_M1_M1, VSUXSEG4EI8_V }, // 9839
|
|
{ PseudoVSUXSEG4EI8_V_M1_M1_MASK, VSUXSEG4EI8_V }, // 9840
|
|
{ PseudoVSUXSEG4EI8_V_M1_M2, VSUXSEG4EI8_V }, // 9841
|
|
{ PseudoVSUXSEG4EI8_V_M1_M2_MASK, VSUXSEG4EI8_V }, // 9842
|
|
{ PseudoVSUXSEG4EI8_V_M2_M2, VSUXSEG4EI8_V }, // 9843
|
|
{ PseudoVSUXSEG4EI8_V_M2_M2_MASK, VSUXSEG4EI8_V }, // 9844
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M1, VSUXSEG4EI8_V }, // 9845
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M1_MASK, VSUXSEG4EI8_V }, // 9846
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M2, VSUXSEG4EI8_V }, // 9847
|
|
{ PseudoVSUXSEG4EI8_V_MF2_M2_MASK, VSUXSEG4EI8_V }, // 9848
|
|
{ PseudoVSUXSEG4EI8_V_MF2_MF2, VSUXSEG4EI8_V }, // 9849
|
|
{ PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, VSUXSEG4EI8_V }, // 9850
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M1, VSUXSEG4EI8_V }, // 9851
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M1_MASK, VSUXSEG4EI8_V }, // 9852
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M2, VSUXSEG4EI8_V }, // 9853
|
|
{ PseudoVSUXSEG4EI8_V_MF4_M2_MASK, VSUXSEG4EI8_V }, // 9854
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF2, VSUXSEG4EI8_V }, // 9855
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, VSUXSEG4EI8_V }, // 9856
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF4, VSUXSEG4EI8_V }, // 9857
|
|
{ PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, VSUXSEG4EI8_V }, // 9858
|
|
{ PseudoVSUXSEG4EI8_V_MF8_M1, VSUXSEG4EI8_V }, // 9859
|
|
{ PseudoVSUXSEG4EI8_V_MF8_M1_MASK, VSUXSEG4EI8_V }, // 9860
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF2, VSUXSEG4EI8_V }, // 9861
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, VSUXSEG4EI8_V }, // 9862
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF4, VSUXSEG4EI8_V }, // 9863
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, VSUXSEG4EI8_V }, // 9864
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF8, VSUXSEG4EI8_V }, // 9865
|
|
{ PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, VSUXSEG4EI8_V }, // 9866
|
|
{ PseudoVSUXSEG5EI16_V_M1_M1, VSUXSEG5EI16_V }, // 9867
|
|
{ PseudoVSUXSEG5EI16_V_M1_M1_MASK, VSUXSEG5EI16_V }, // 9868
|
|
{ PseudoVSUXSEG5EI16_V_M1_MF2, VSUXSEG5EI16_V }, // 9869
|
|
{ PseudoVSUXSEG5EI16_V_M1_MF2_MASK, VSUXSEG5EI16_V }, // 9870
|
|
{ PseudoVSUXSEG5EI16_V_M2_M1, VSUXSEG5EI16_V }, // 9871
|
|
{ PseudoVSUXSEG5EI16_V_M2_M1_MASK, VSUXSEG5EI16_V }, // 9872
|
|
{ PseudoVSUXSEG5EI16_V_MF2_M1, VSUXSEG5EI16_V }, // 9873
|
|
{ PseudoVSUXSEG5EI16_V_MF2_M1_MASK, VSUXSEG5EI16_V }, // 9874
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF2, VSUXSEG5EI16_V }, // 9875
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, VSUXSEG5EI16_V }, // 9876
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF4, VSUXSEG5EI16_V }, // 9877
|
|
{ PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, VSUXSEG5EI16_V }, // 9878
|
|
{ PseudoVSUXSEG5EI16_V_MF4_M1, VSUXSEG5EI16_V }, // 9879
|
|
{ PseudoVSUXSEG5EI16_V_MF4_M1_MASK, VSUXSEG5EI16_V }, // 9880
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF2, VSUXSEG5EI16_V }, // 9881
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, VSUXSEG5EI16_V }, // 9882
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF4, VSUXSEG5EI16_V }, // 9883
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, VSUXSEG5EI16_V }, // 9884
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF8, VSUXSEG5EI16_V }, // 9885
|
|
{ PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, VSUXSEG5EI16_V }, // 9886
|
|
{ PseudoVSUXSEG5EI32_V_M1_M1, VSUXSEG5EI32_V }, // 9887
|
|
{ PseudoVSUXSEG5EI32_V_M1_M1_MASK, VSUXSEG5EI32_V }, // 9888
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF2, VSUXSEG5EI32_V }, // 9889
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF2_MASK, VSUXSEG5EI32_V }, // 9890
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF4, VSUXSEG5EI32_V }, // 9891
|
|
{ PseudoVSUXSEG5EI32_V_M1_MF4_MASK, VSUXSEG5EI32_V }, // 9892
|
|
{ PseudoVSUXSEG5EI32_V_M2_M1, VSUXSEG5EI32_V }, // 9893
|
|
{ PseudoVSUXSEG5EI32_V_M2_M1_MASK, VSUXSEG5EI32_V }, // 9894
|
|
{ PseudoVSUXSEG5EI32_V_M2_MF2, VSUXSEG5EI32_V }, // 9895
|
|
{ PseudoVSUXSEG5EI32_V_M2_MF2_MASK, VSUXSEG5EI32_V }, // 9896
|
|
{ PseudoVSUXSEG5EI32_V_M4_M1, VSUXSEG5EI32_V }, // 9897
|
|
{ PseudoVSUXSEG5EI32_V_M4_M1_MASK, VSUXSEG5EI32_V }, // 9898
|
|
{ PseudoVSUXSEG5EI32_V_MF2_M1, VSUXSEG5EI32_V }, // 9899
|
|
{ PseudoVSUXSEG5EI32_V_MF2_M1_MASK, VSUXSEG5EI32_V }, // 9900
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF2, VSUXSEG5EI32_V }, // 9901
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, VSUXSEG5EI32_V }, // 9902
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF4, VSUXSEG5EI32_V }, // 9903
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, VSUXSEG5EI32_V }, // 9904
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF8, VSUXSEG5EI32_V }, // 9905
|
|
{ PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, VSUXSEG5EI32_V }, // 9906
|
|
{ PseudoVSUXSEG5EI64_V_M1_M1, VSUXSEG5EI64_V }, // 9907
|
|
{ PseudoVSUXSEG5EI64_V_M1_M1_MASK, VSUXSEG5EI64_V }, // 9908
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF2, VSUXSEG5EI64_V }, // 9909
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF2_MASK, VSUXSEG5EI64_V }, // 9910
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF4, VSUXSEG5EI64_V }, // 9911
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF4_MASK, VSUXSEG5EI64_V }, // 9912
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF8, VSUXSEG5EI64_V }, // 9913
|
|
{ PseudoVSUXSEG5EI64_V_M1_MF8_MASK, VSUXSEG5EI64_V }, // 9914
|
|
{ PseudoVSUXSEG5EI64_V_M2_M1, VSUXSEG5EI64_V }, // 9915
|
|
{ PseudoVSUXSEG5EI64_V_M2_M1_MASK, VSUXSEG5EI64_V }, // 9916
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF2, VSUXSEG5EI64_V }, // 9917
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF2_MASK, VSUXSEG5EI64_V }, // 9918
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF4, VSUXSEG5EI64_V }, // 9919
|
|
{ PseudoVSUXSEG5EI64_V_M2_MF4_MASK, VSUXSEG5EI64_V }, // 9920
|
|
{ PseudoVSUXSEG5EI64_V_M4_M1, VSUXSEG5EI64_V }, // 9921
|
|
{ PseudoVSUXSEG5EI64_V_M4_M1_MASK, VSUXSEG5EI64_V }, // 9922
|
|
{ PseudoVSUXSEG5EI64_V_M4_MF2, VSUXSEG5EI64_V }, // 9923
|
|
{ PseudoVSUXSEG5EI64_V_M4_MF2_MASK, VSUXSEG5EI64_V }, // 9924
|
|
{ PseudoVSUXSEG5EI64_V_M8_M1, VSUXSEG5EI64_V }, // 9925
|
|
{ PseudoVSUXSEG5EI64_V_M8_M1_MASK, VSUXSEG5EI64_V }, // 9926
|
|
{ PseudoVSUXSEG5EI8_V_M1_M1, VSUXSEG5EI8_V }, // 9927
|
|
{ PseudoVSUXSEG5EI8_V_M1_M1_MASK, VSUXSEG5EI8_V }, // 9928
|
|
{ PseudoVSUXSEG5EI8_V_MF2_M1, VSUXSEG5EI8_V }, // 9929
|
|
{ PseudoVSUXSEG5EI8_V_MF2_M1_MASK, VSUXSEG5EI8_V }, // 9930
|
|
{ PseudoVSUXSEG5EI8_V_MF2_MF2, VSUXSEG5EI8_V }, // 9931
|
|
{ PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, VSUXSEG5EI8_V }, // 9932
|
|
{ PseudoVSUXSEG5EI8_V_MF4_M1, VSUXSEG5EI8_V }, // 9933
|
|
{ PseudoVSUXSEG5EI8_V_MF4_M1_MASK, VSUXSEG5EI8_V }, // 9934
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF2, VSUXSEG5EI8_V }, // 9935
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, VSUXSEG5EI8_V }, // 9936
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF4, VSUXSEG5EI8_V }, // 9937
|
|
{ PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, VSUXSEG5EI8_V }, // 9938
|
|
{ PseudoVSUXSEG5EI8_V_MF8_M1, VSUXSEG5EI8_V }, // 9939
|
|
{ PseudoVSUXSEG5EI8_V_MF8_M1_MASK, VSUXSEG5EI8_V }, // 9940
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF2, VSUXSEG5EI8_V }, // 9941
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, VSUXSEG5EI8_V }, // 9942
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF4, VSUXSEG5EI8_V }, // 9943
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, VSUXSEG5EI8_V }, // 9944
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF8, VSUXSEG5EI8_V }, // 9945
|
|
{ PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, VSUXSEG5EI8_V }, // 9946
|
|
{ PseudoVSUXSEG6EI16_V_M1_M1, VSUXSEG6EI16_V }, // 9947
|
|
{ PseudoVSUXSEG6EI16_V_M1_M1_MASK, VSUXSEG6EI16_V }, // 9948
|
|
{ PseudoVSUXSEG6EI16_V_M1_MF2, VSUXSEG6EI16_V }, // 9949
|
|
{ PseudoVSUXSEG6EI16_V_M1_MF2_MASK, VSUXSEG6EI16_V }, // 9950
|
|
{ PseudoVSUXSEG6EI16_V_M2_M1, VSUXSEG6EI16_V }, // 9951
|
|
{ PseudoVSUXSEG6EI16_V_M2_M1_MASK, VSUXSEG6EI16_V }, // 9952
|
|
{ PseudoVSUXSEG6EI16_V_MF2_M1, VSUXSEG6EI16_V }, // 9953
|
|
{ PseudoVSUXSEG6EI16_V_MF2_M1_MASK, VSUXSEG6EI16_V }, // 9954
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF2, VSUXSEG6EI16_V }, // 9955
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, VSUXSEG6EI16_V }, // 9956
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF4, VSUXSEG6EI16_V }, // 9957
|
|
{ PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, VSUXSEG6EI16_V }, // 9958
|
|
{ PseudoVSUXSEG6EI16_V_MF4_M1, VSUXSEG6EI16_V }, // 9959
|
|
{ PseudoVSUXSEG6EI16_V_MF4_M1_MASK, VSUXSEG6EI16_V }, // 9960
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF2, VSUXSEG6EI16_V }, // 9961
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, VSUXSEG6EI16_V }, // 9962
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF4, VSUXSEG6EI16_V }, // 9963
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, VSUXSEG6EI16_V }, // 9964
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF8, VSUXSEG6EI16_V }, // 9965
|
|
{ PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, VSUXSEG6EI16_V }, // 9966
|
|
{ PseudoVSUXSEG6EI32_V_M1_M1, VSUXSEG6EI32_V }, // 9967
|
|
{ PseudoVSUXSEG6EI32_V_M1_M1_MASK, VSUXSEG6EI32_V }, // 9968
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF2, VSUXSEG6EI32_V }, // 9969
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF2_MASK, VSUXSEG6EI32_V }, // 9970
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF4, VSUXSEG6EI32_V }, // 9971
|
|
{ PseudoVSUXSEG6EI32_V_M1_MF4_MASK, VSUXSEG6EI32_V }, // 9972
|
|
{ PseudoVSUXSEG6EI32_V_M2_M1, VSUXSEG6EI32_V }, // 9973
|
|
{ PseudoVSUXSEG6EI32_V_M2_M1_MASK, VSUXSEG6EI32_V }, // 9974
|
|
{ PseudoVSUXSEG6EI32_V_M2_MF2, VSUXSEG6EI32_V }, // 9975
|
|
{ PseudoVSUXSEG6EI32_V_M2_MF2_MASK, VSUXSEG6EI32_V }, // 9976
|
|
{ PseudoVSUXSEG6EI32_V_M4_M1, VSUXSEG6EI32_V }, // 9977
|
|
{ PseudoVSUXSEG6EI32_V_M4_M1_MASK, VSUXSEG6EI32_V }, // 9978
|
|
{ PseudoVSUXSEG6EI32_V_MF2_M1, VSUXSEG6EI32_V }, // 9979
|
|
{ PseudoVSUXSEG6EI32_V_MF2_M1_MASK, VSUXSEG6EI32_V }, // 9980
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF2, VSUXSEG6EI32_V }, // 9981
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, VSUXSEG6EI32_V }, // 9982
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF4, VSUXSEG6EI32_V }, // 9983
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, VSUXSEG6EI32_V }, // 9984
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF8, VSUXSEG6EI32_V }, // 9985
|
|
{ PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, VSUXSEG6EI32_V }, // 9986
|
|
{ PseudoVSUXSEG6EI64_V_M1_M1, VSUXSEG6EI64_V }, // 9987
|
|
{ PseudoVSUXSEG6EI64_V_M1_M1_MASK, VSUXSEG6EI64_V }, // 9988
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF2, VSUXSEG6EI64_V }, // 9989
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF2_MASK, VSUXSEG6EI64_V }, // 9990
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF4, VSUXSEG6EI64_V }, // 9991
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF4_MASK, VSUXSEG6EI64_V }, // 9992
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF8, VSUXSEG6EI64_V }, // 9993
|
|
{ PseudoVSUXSEG6EI64_V_M1_MF8_MASK, VSUXSEG6EI64_V }, // 9994
|
|
{ PseudoVSUXSEG6EI64_V_M2_M1, VSUXSEG6EI64_V }, // 9995
|
|
{ PseudoVSUXSEG6EI64_V_M2_M1_MASK, VSUXSEG6EI64_V }, // 9996
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF2, VSUXSEG6EI64_V }, // 9997
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF2_MASK, VSUXSEG6EI64_V }, // 9998
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF4, VSUXSEG6EI64_V }, // 9999
|
|
{ PseudoVSUXSEG6EI64_V_M2_MF4_MASK, VSUXSEG6EI64_V }, // 10000
|
|
{ PseudoVSUXSEG6EI64_V_M4_M1, VSUXSEG6EI64_V }, // 10001
|
|
{ PseudoVSUXSEG6EI64_V_M4_M1_MASK, VSUXSEG6EI64_V }, // 10002
|
|
{ PseudoVSUXSEG6EI64_V_M4_MF2, VSUXSEG6EI64_V }, // 10003
|
|
{ PseudoVSUXSEG6EI64_V_M4_MF2_MASK, VSUXSEG6EI64_V }, // 10004
|
|
{ PseudoVSUXSEG6EI64_V_M8_M1, VSUXSEG6EI64_V }, // 10005
|
|
{ PseudoVSUXSEG6EI64_V_M8_M1_MASK, VSUXSEG6EI64_V }, // 10006
|
|
{ PseudoVSUXSEG6EI8_V_M1_M1, VSUXSEG6EI8_V }, // 10007
|
|
{ PseudoVSUXSEG6EI8_V_M1_M1_MASK, VSUXSEG6EI8_V }, // 10008
|
|
{ PseudoVSUXSEG6EI8_V_MF2_M1, VSUXSEG6EI8_V }, // 10009
|
|
{ PseudoVSUXSEG6EI8_V_MF2_M1_MASK, VSUXSEG6EI8_V }, // 10010
|
|
{ PseudoVSUXSEG6EI8_V_MF2_MF2, VSUXSEG6EI8_V }, // 10011
|
|
{ PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, VSUXSEG6EI8_V }, // 10012
|
|
{ PseudoVSUXSEG6EI8_V_MF4_M1, VSUXSEG6EI8_V }, // 10013
|
|
{ PseudoVSUXSEG6EI8_V_MF4_M1_MASK, VSUXSEG6EI8_V }, // 10014
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF2, VSUXSEG6EI8_V }, // 10015
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, VSUXSEG6EI8_V }, // 10016
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF4, VSUXSEG6EI8_V }, // 10017
|
|
{ PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, VSUXSEG6EI8_V }, // 10018
|
|
{ PseudoVSUXSEG6EI8_V_MF8_M1, VSUXSEG6EI8_V }, // 10019
|
|
{ PseudoVSUXSEG6EI8_V_MF8_M1_MASK, VSUXSEG6EI8_V }, // 10020
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF2, VSUXSEG6EI8_V }, // 10021
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, VSUXSEG6EI8_V }, // 10022
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF4, VSUXSEG6EI8_V }, // 10023
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, VSUXSEG6EI8_V }, // 10024
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF8, VSUXSEG6EI8_V }, // 10025
|
|
{ PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, VSUXSEG6EI8_V }, // 10026
|
|
{ PseudoVSUXSEG7EI16_V_M1_M1, VSUXSEG7EI16_V }, // 10027
|
|
{ PseudoVSUXSEG7EI16_V_M1_M1_MASK, VSUXSEG7EI16_V }, // 10028
|
|
{ PseudoVSUXSEG7EI16_V_M1_MF2, VSUXSEG7EI16_V }, // 10029
|
|
{ PseudoVSUXSEG7EI16_V_M1_MF2_MASK, VSUXSEG7EI16_V }, // 10030
|
|
{ PseudoVSUXSEG7EI16_V_M2_M1, VSUXSEG7EI16_V }, // 10031
|
|
{ PseudoVSUXSEG7EI16_V_M2_M1_MASK, VSUXSEG7EI16_V }, // 10032
|
|
{ PseudoVSUXSEG7EI16_V_MF2_M1, VSUXSEG7EI16_V }, // 10033
|
|
{ PseudoVSUXSEG7EI16_V_MF2_M1_MASK, VSUXSEG7EI16_V }, // 10034
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF2, VSUXSEG7EI16_V }, // 10035
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, VSUXSEG7EI16_V }, // 10036
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF4, VSUXSEG7EI16_V }, // 10037
|
|
{ PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, VSUXSEG7EI16_V }, // 10038
|
|
{ PseudoVSUXSEG7EI16_V_MF4_M1, VSUXSEG7EI16_V }, // 10039
|
|
{ PseudoVSUXSEG7EI16_V_MF4_M1_MASK, VSUXSEG7EI16_V }, // 10040
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF2, VSUXSEG7EI16_V }, // 10041
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, VSUXSEG7EI16_V }, // 10042
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF4, VSUXSEG7EI16_V }, // 10043
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, VSUXSEG7EI16_V }, // 10044
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF8, VSUXSEG7EI16_V }, // 10045
|
|
{ PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, VSUXSEG7EI16_V }, // 10046
|
|
{ PseudoVSUXSEG7EI32_V_M1_M1, VSUXSEG7EI32_V }, // 10047
|
|
{ PseudoVSUXSEG7EI32_V_M1_M1_MASK, VSUXSEG7EI32_V }, // 10048
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF2, VSUXSEG7EI32_V }, // 10049
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF2_MASK, VSUXSEG7EI32_V }, // 10050
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF4, VSUXSEG7EI32_V }, // 10051
|
|
{ PseudoVSUXSEG7EI32_V_M1_MF4_MASK, VSUXSEG7EI32_V }, // 10052
|
|
{ PseudoVSUXSEG7EI32_V_M2_M1, VSUXSEG7EI32_V }, // 10053
|
|
{ PseudoVSUXSEG7EI32_V_M2_M1_MASK, VSUXSEG7EI32_V }, // 10054
|
|
{ PseudoVSUXSEG7EI32_V_M2_MF2, VSUXSEG7EI32_V }, // 10055
|
|
{ PseudoVSUXSEG7EI32_V_M2_MF2_MASK, VSUXSEG7EI32_V }, // 10056
|
|
{ PseudoVSUXSEG7EI32_V_M4_M1, VSUXSEG7EI32_V }, // 10057
|
|
{ PseudoVSUXSEG7EI32_V_M4_M1_MASK, VSUXSEG7EI32_V }, // 10058
|
|
{ PseudoVSUXSEG7EI32_V_MF2_M1, VSUXSEG7EI32_V }, // 10059
|
|
{ PseudoVSUXSEG7EI32_V_MF2_M1_MASK, VSUXSEG7EI32_V }, // 10060
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF2, VSUXSEG7EI32_V }, // 10061
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, VSUXSEG7EI32_V }, // 10062
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF4, VSUXSEG7EI32_V }, // 10063
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, VSUXSEG7EI32_V }, // 10064
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF8, VSUXSEG7EI32_V }, // 10065
|
|
{ PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, VSUXSEG7EI32_V }, // 10066
|
|
{ PseudoVSUXSEG7EI64_V_M1_M1, VSUXSEG7EI64_V }, // 10067
|
|
{ PseudoVSUXSEG7EI64_V_M1_M1_MASK, VSUXSEG7EI64_V }, // 10068
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF2, VSUXSEG7EI64_V }, // 10069
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF2_MASK, VSUXSEG7EI64_V }, // 10070
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF4, VSUXSEG7EI64_V }, // 10071
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF4_MASK, VSUXSEG7EI64_V }, // 10072
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF8, VSUXSEG7EI64_V }, // 10073
|
|
{ PseudoVSUXSEG7EI64_V_M1_MF8_MASK, VSUXSEG7EI64_V }, // 10074
|
|
{ PseudoVSUXSEG7EI64_V_M2_M1, VSUXSEG7EI64_V }, // 10075
|
|
{ PseudoVSUXSEG7EI64_V_M2_M1_MASK, VSUXSEG7EI64_V }, // 10076
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF2, VSUXSEG7EI64_V }, // 10077
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF2_MASK, VSUXSEG7EI64_V }, // 10078
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF4, VSUXSEG7EI64_V }, // 10079
|
|
{ PseudoVSUXSEG7EI64_V_M2_MF4_MASK, VSUXSEG7EI64_V }, // 10080
|
|
{ PseudoVSUXSEG7EI64_V_M4_M1, VSUXSEG7EI64_V }, // 10081
|
|
{ PseudoVSUXSEG7EI64_V_M4_M1_MASK, VSUXSEG7EI64_V }, // 10082
|
|
{ PseudoVSUXSEG7EI64_V_M4_MF2, VSUXSEG7EI64_V }, // 10083
|
|
{ PseudoVSUXSEG7EI64_V_M4_MF2_MASK, VSUXSEG7EI64_V }, // 10084
|
|
{ PseudoVSUXSEG7EI64_V_M8_M1, VSUXSEG7EI64_V }, // 10085
|
|
{ PseudoVSUXSEG7EI64_V_M8_M1_MASK, VSUXSEG7EI64_V }, // 10086
|
|
{ PseudoVSUXSEG7EI8_V_M1_M1, VSUXSEG7EI8_V }, // 10087
|
|
{ PseudoVSUXSEG7EI8_V_M1_M1_MASK, VSUXSEG7EI8_V }, // 10088
|
|
{ PseudoVSUXSEG7EI8_V_MF2_M1, VSUXSEG7EI8_V }, // 10089
|
|
{ PseudoVSUXSEG7EI8_V_MF2_M1_MASK, VSUXSEG7EI8_V }, // 10090
|
|
{ PseudoVSUXSEG7EI8_V_MF2_MF2, VSUXSEG7EI8_V }, // 10091
|
|
{ PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, VSUXSEG7EI8_V }, // 10092
|
|
{ PseudoVSUXSEG7EI8_V_MF4_M1, VSUXSEG7EI8_V }, // 10093
|
|
{ PseudoVSUXSEG7EI8_V_MF4_M1_MASK, VSUXSEG7EI8_V }, // 10094
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF2, VSUXSEG7EI8_V }, // 10095
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, VSUXSEG7EI8_V }, // 10096
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF4, VSUXSEG7EI8_V }, // 10097
|
|
{ PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, VSUXSEG7EI8_V }, // 10098
|
|
{ PseudoVSUXSEG7EI8_V_MF8_M1, VSUXSEG7EI8_V }, // 10099
|
|
{ PseudoVSUXSEG7EI8_V_MF8_M1_MASK, VSUXSEG7EI8_V }, // 10100
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF2, VSUXSEG7EI8_V }, // 10101
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, VSUXSEG7EI8_V }, // 10102
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF4, VSUXSEG7EI8_V }, // 10103
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, VSUXSEG7EI8_V }, // 10104
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF8, VSUXSEG7EI8_V }, // 10105
|
|
{ PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, VSUXSEG7EI8_V }, // 10106
|
|
{ PseudoVSUXSEG8EI16_V_M1_M1, VSUXSEG8EI16_V }, // 10107
|
|
{ PseudoVSUXSEG8EI16_V_M1_M1_MASK, VSUXSEG8EI16_V }, // 10108
|
|
{ PseudoVSUXSEG8EI16_V_M1_MF2, VSUXSEG8EI16_V }, // 10109
|
|
{ PseudoVSUXSEG8EI16_V_M1_MF2_MASK, VSUXSEG8EI16_V }, // 10110
|
|
{ PseudoVSUXSEG8EI16_V_M2_M1, VSUXSEG8EI16_V }, // 10111
|
|
{ PseudoVSUXSEG8EI16_V_M2_M1_MASK, VSUXSEG8EI16_V }, // 10112
|
|
{ PseudoVSUXSEG8EI16_V_MF2_M1, VSUXSEG8EI16_V }, // 10113
|
|
{ PseudoVSUXSEG8EI16_V_MF2_M1_MASK, VSUXSEG8EI16_V }, // 10114
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF2, VSUXSEG8EI16_V }, // 10115
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, VSUXSEG8EI16_V }, // 10116
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF4, VSUXSEG8EI16_V }, // 10117
|
|
{ PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, VSUXSEG8EI16_V }, // 10118
|
|
{ PseudoVSUXSEG8EI16_V_MF4_M1, VSUXSEG8EI16_V }, // 10119
|
|
{ PseudoVSUXSEG8EI16_V_MF4_M1_MASK, VSUXSEG8EI16_V }, // 10120
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF2, VSUXSEG8EI16_V }, // 10121
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, VSUXSEG8EI16_V }, // 10122
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF4, VSUXSEG8EI16_V }, // 10123
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, VSUXSEG8EI16_V }, // 10124
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF8, VSUXSEG8EI16_V }, // 10125
|
|
{ PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, VSUXSEG8EI16_V }, // 10126
|
|
{ PseudoVSUXSEG8EI32_V_M1_M1, VSUXSEG8EI32_V }, // 10127
|
|
{ PseudoVSUXSEG8EI32_V_M1_M1_MASK, VSUXSEG8EI32_V }, // 10128
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF2, VSUXSEG8EI32_V }, // 10129
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF2_MASK, VSUXSEG8EI32_V }, // 10130
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF4, VSUXSEG8EI32_V }, // 10131
|
|
{ PseudoVSUXSEG8EI32_V_M1_MF4_MASK, VSUXSEG8EI32_V }, // 10132
|
|
{ PseudoVSUXSEG8EI32_V_M2_M1, VSUXSEG8EI32_V }, // 10133
|
|
{ PseudoVSUXSEG8EI32_V_M2_M1_MASK, VSUXSEG8EI32_V }, // 10134
|
|
{ PseudoVSUXSEG8EI32_V_M2_MF2, VSUXSEG8EI32_V }, // 10135
|
|
{ PseudoVSUXSEG8EI32_V_M2_MF2_MASK, VSUXSEG8EI32_V }, // 10136
|
|
{ PseudoVSUXSEG8EI32_V_M4_M1, VSUXSEG8EI32_V }, // 10137
|
|
{ PseudoVSUXSEG8EI32_V_M4_M1_MASK, VSUXSEG8EI32_V }, // 10138
|
|
{ PseudoVSUXSEG8EI32_V_MF2_M1, VSUXSEG8EI32_V }, // 10139
|
|
{ PseudoVSUXSEG8EI32_V_MF2_M1_MASK, VSUXSEG8EI32_V }, // 10140
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF2, VSUXSEG8EI32_V }, // 10141
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, VSUXSEG8EI32_V }, // 10142
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF4, VSUXSEG8EI32_V }, // 10143
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, VSUXSEG8EI32_V }, // 10144
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF8, VSUXSEG8EI32_V }, // 10145
|
|
{ PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, VSUXSEG8EI32_V }, // 10146
|
|
{ PseudoVSUXSEG8EI64_V_M1_M1, VSUXSEG8EI64_V }, // 10147
|
|
{ PseudoVSUXSEG8EI64_V_M1_M1_MASK, VSUXSEG8EI64_V }, // 10148
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF2, VSUXSEG8EI64_V }, // 10149
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF2_MASK, VSUXSEG8EI64_V }, // 10150
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF4, VSUXSEG8EI64_V }, // 10151
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF4_MASK, VSUXSEG8EI64_V }, // 10152
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF8, VSUXSEG8EI64_V }, // 10153
|
|
{ PseudoVSUXSEG8EI64_V_M1_MF8_MASK, VSUXSEG8EI64_V }, // 10154
|
|
{ PseudoVSUXSEG8EI64_V_M2_M1, VSUXSEG8EI64_V }, // 10155
|
|
{ PseudoVSUXSEG8EI64_V_M2_M1_MASK, VSUXSEG8EI64_V }, // 10156
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF2, VSUXSEG8EI64_V }, // 10157
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF2_MASK, VSUXSEG8EI64_V }, // 10158
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF4, VSUXSEG8EI64_V }, // 10159
|
|
{ PseudoVSUXSEG8EI64_V_M2_MF4_MASK, VSUXSEG8EI64_V }, // 10160
|
|
{ PseudoVSUXSEG8EI64_V_M4_M1, VSUXSEG8EI64_V }, // 10161
|
|
{ PseudoVSUXSEG8EI64_V_M4_M1_MASK, VSUXSEG8EI64_V }, // 10162
|
|
{ PseudoVSUXSEG8EI64_V_M4_MF2, VSUXSEG8EI64_V }, // 10163
|
|
{ PseudoVSUXSEG8EI64_V_M4_MF2_MASK, VSUXSEG8EI64_V }, // 10164
|
|
{ PseudoVSUXSEG8EI64_V_M8_M1, VSUXSEG8EI64_V }, // 10165
|
|
{ PseudoVSUXSEG8EI64_V_M8_M1_MASK, VSUXSEG8EI64_V }, // 10166
|
|
{ PseudoVSUXSEG8EI8_V_M1_M1, VSUXSEG8EI8_V }, // 10167
|
|
{ PseudoVSUXSEG8EI8_V_M1_M1_MASK, VSUXSEG8EI8_V }, // 10168
|
|
{ PseudoVSUXSEG8EI8_V_MF2_M1, VSUXSEG8EI8_V }, // 10169
|
|
{ PseudoVSUXSEG8EI8_V_MF2_M1_MASK, VSUXSEG8EI8_V }, // 10170
|
|
{ PseudoVSUXSEG8EI8_V_MF2_MF2, VSUXSEG8EI8_V }, // 10171
|
|
{ PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, VSUXSEG8EI8_V }, // 10172
|
|
{ PseudoVSUXSEG8EI8_V_MF4_M1, VSUXSEG8EI8_V }, // 10173
|
|
{ PseudoVSUXSEG8EI8_V_MF4_M1_MASK, VSUXSEG8EI8_V }, // 10174
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF2, VSUXSEG8EI8_V }, // 10175
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, VSUXSEG8EI8_V }, // 10176
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF4, VSUXSEG8EI8_V }, // 10177
|
|
{ PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, VSUXSEG8EI8_V }, // 10178
|
|
{ PseudoVSUXSEG8EI8_V_MF8_M1, VSUXSEG8EI8_V }, // 10179
|
|
{ PseudoVSUXSEG8EI8_V_MF8_M1_MASK, VSUXSEG8EI8_V }, // 10180
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF2, VSUXSEG8EI8_V }, // 10181
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, VSUXSEG8EI8_V }, // 10182
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF4, VSUXSEG8EI8_V }, // 10183
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, VSUXSEG8EI8_V }, // 10184
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF8, VSUXSEG8EI8_V }, // 10185
|
|
{ PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, VSUXSEG8EI8_V }, // 10186
|
|
{ PseudoVWADDU_VV_M1, VWADDU_VV }, // 10187
|
|
{ PseudoVWADDU_VV_M1_MASK, VWADDU_VV }, // 10188
|
|
{ PseudoVWADDU_VV_M2, VWADDU_VV }, // 10189
|
|
{ PseudoVWADDU_VV_M2_MASK, VWADDU_VV }, // 10190
|
|
{ PseudoVWADDU_VV_M4, VWADDU_VV }, // 10191
|
|
{ PseudoVWADDU_VV_M4_MASK, VWADDU_VV }, // 10192
|
|
{ PseudoVWADDU_VV_MF2, VWADDU_VV }, // 10193
|
|
{ PseudoVWADDU_VV_MF2_MASK, VWADDU_VV }, // 10194
|
|
{ PseudoVWADDU_VV_MF4, VWADDU_VV }, // 10195
|
|
{ PseudoVWADDU_VV_MF4_MASK, VWADDU_VV }, // 10196
|
|
{ PseudoVWADDU_VV_MF8, VWADDU_VV }, // 10197
|
|
{ PseudoVWADDU_VV_MF8_MASK, VWADDU_VV }, // 10198
|
|
{ PseudoVWADDU_VX_M1, VWADDU_VX }, // 10199
|
|
{ PseudoVWADDU_VX_M1_MASK, VWADDU_VX }, // 10200
|
|
{ PseudoVWADDU_VX_M2, VWADDU_VX }, // 10201
|
|
{ PseudoVWADDU_VX_M2_MASK, VWADDU_VX }, // 10202
|
|
{ PseudoVWADDU_VX_M4, VWADDU_VX }, // 10203
|
|
{ PseudoVWADDU_VX_M4_MASK, VWADDU_VX }, // 10204
|
|
{ PseudoVWADDU_VX_MF2, VWADDU_VX }, // 10205
|
|
{ PseudoVWADDU_VX_MF2_MASK, VWADDU_VX }, // 10206
|
|
{ PseudoVWADDU_VX_MF4, VWADDU_VX }, // 10207
|
|
{ PseudoVWADDU_VX_MF4_MASK, VWADDU_VX }, // 10208
|
|
{ PseudoVWADDU_VX_MF8, VWADDU_VX }, // 10209
|
|
{ PseudoVWADDU_VX_MF8_MASK, VWADDU_VX }, // 10210
|
|
{ PseudoVWADDU_WV_M1, VWADDU_WV }, // 10211
|
|
{ PseudoVWADDU_WV_M1_MASK, VWADDU_WV }, // 10212
|
|
{ PseudoVWADDU_WV_M1_MASK_TIED, VWADDU_WV }, // 10213
|
|
{ PseudoVWADDU_WV_M1_TIED, VWADDU_WV }, // 10214
|
|
{ PseudoVWADDU_WV_M2, VWADDU_WV }, // 10215
|
|
{ PseudoVWADDU_WV_M2_MASK, VWADDU_WV }, // 10216
|
|
{ PseudoVWADDU_WV_M2_MASK_TIED, VWADDU_WV }, // 10217
|
|
{ PseudoVWADDU_WV_M2_TIED, VWADDU_WV }, // 10218
|
|
{ PseudoVWADDU_WV_M4, VWADDU_WV }, // 10219
|
|
{ PseudoVWADDU_WV_M4_MASK, VWADDU_WV }, // 10220
|
|
{ PseudoVWADDU_WV_M4_MASK_TIED, VWADDU_WV }, // 10221
|
|
{ PseudoVWADDU_WV_M4_TIED, VWADDU_WV }, // 10222
|
|
{ PseudoVWADDU_WV_MF2, VWADDU_WV }, // 10223
|
|
{ PseudoVWADDU_WV_MF2_MASK, VWADDU_WV }, // 10224
|
|
{ PseudoVWADDU_WV_MF2_MASK_TIED, VWADDU_WV }, // 10225
|
|
{ PseudoVWADDU_WV_MF2_TIED, VWADDU_WV }, // 10226
|
|
{ PseudoVWADDU_WV_MF4, VWADDU_WV }, // 10227
|
|
{ PseudoVWADDU_WV_MF4_MASK, VWADDU_WV }, // 10228
|
|
{ PseudoVWADDU_WV_MF4_MASK_TIED, VWADDU_WV }, // 10229
|
|
{ PseudoVWADDU_WV_MF4_TIED, VWADDU_WV }, // 10230
|
|
{ PseudoVWADDU_WV_MF8, VWADDU_WV }, // 10231
|
|
{ PseudoVWADDU_WV_MF8_MASK, VWADDU_WV }, // 10232
|
|
{ PseudoVWADDU_WV_MF8_MASK_TIED, VWADDU_WV }, // 10233
|
|
{ PseudoVWADDU_WV_MF8_TIED, VWADDU_WV }, // 10234
|
|
{ PseudoVWADDU_WX_M1, VWADDU_WX }, // 10235
|
|
{ PseudoVWADDU_WX_M1_MASK, VWADDU_WX }, // 10236
|
|
{ PseudoVWADDU_WX_M2, VWADDU_WX }, // 10237
|
|
{ PseudoVWADDU_WX_M2_MASK, VWADDU_WX }, // 10238
|
|
{ PseudoVWADDU_WX_M4, VWADDU_WX }, // 10239
|
|
{ PseudoVWADDU_WX_M4_MASK, VWADDU_WX }, // 10240
|
|
{ PseudoVWADDU_WX_MF2, VWADDU_WX }, // 10241
|
|
{ PseudoVWADDU_WX_MF2_MASK, VWADDU_WX }, // 10242
|
|
{ PseudoVWADDU_WX_MF4, VWADDU_WX }, // 10243
|
|
{ PseudoVWADDU_WX_MF4_MASK, VWADDU_WX }, // 10244
|
|
{ PseudoVWADDU_WX_MF8, VWADDU_WX }, // 10245
|
|
{ PseudoVWADDU_WX_MF8_MASK, VWADDU_WX }, // 10246
|
|
{ PseudoVWADD_VV_M1, VWADD_VV }, // 10247
|
|
{ PseudoVWADD_VV_M1_MASK, VWADD_VV }, // 10248
|
|
{ PseudoVWADD_VV_M2, VWADD_VV }, // 10249
|
|
{ PseudoVWADD_VV_M2_MASK, VWADD_VV }, // 10250
|
|
{ PseudoVWADD_VV_M4, VWADD_VV }, // 10251
|
|
{ PseudoVWADD_VV_M4_MASK, VWADD_VV }, // 10252
|
|
{ PseudoVWADD_VV_MF2, VWADD_VV }, // 10253
|
|
{ PseudoVWADD_VV_MF2_MASK, VWADD_VV }, // 10254
|
|
{ PseudoVWADD_VV_MF4, VWADD_VV }, // 10255
|
|
{ PseudoVWADD_VV_MF4_MASK, VWADD_VV }, // 10256
|
|
{ PseudoVWADD_VV_MF8, VWADD_VV }, // 10257
|
|
{ PseudoVWADD_VV_MF8_MASK, VWADD_VV }, // 10258
|
|
{ PseudoVWADD_VX_M1, VWADD_VX }, // 10259
|
|
{ PseudoVWADD_VX_M1_MASK, VWADD_VX }, // 10260
|
|
{ PseudoVWADD_VX_M2, VWADD_VX }, // 10261
|
|
{ PseudoVWADD_VX_M2_MASK, VWADD_VX }, // 10262
|
|
{ PseudoVWADD_VX_M4, VWADD_VX }, // 10263
|
|
{ PseudoVWADD_VX_M4_MASK, VWADD_VX }, // 10264
|
|
{ PseudoVWADD_VX_MF2, VWADD_VX }, // 10265
|
|
{ PseudoVWADD_VX_MF2_MASK, VWADD_VX }, // 10266
|
|
{ PseudoVWADD_VX_MF4, VWADD_VX }, // 10267
|
|
{ PseudoVWADD_VX_MF4_MASK, VWADD_VX }, // 10268
|
|
{ PseudoVWADD_VX_MF8, VWADD_VX }, // 10269
|
|
{ PseudoVWADD_VX_MF8_MASK, VWADD_VX }, // 10270
|
|
{ PseudoVWADD_WV_M1, VWADD_WV }, // 10271
|
|
{ PseudoVWADD_WV_M1_MASK, VWADD_WV }, // 10272
|
|
{ PseudoVWADD_WV_M1_MASK_TIED, VWADD_WV }, // 10273
|
|
{ PseudoVWADD_WV_M1_TIED, VWADD_WV }, // 10274
|
|
{ PseudoVWADD_WV_M2, VWADD_WV }, // 10275
|
|
{ PseudoVWADD_WV_M2_MASK, VWADD_WV }, // 10276
|
|
{ PseudoVWADD_WV_M2_MASK_TIED, VWADD_WV }, // 10277
|
|
{ PseudoVWADD_WV_M2_TIED, VWADD_WV }, // 10278
|
|
{ PseudoVWADD_WV_M4, VWADD_WV }, // 10279
|
|
{ PseudoVWADD_WV_M4_MASK, VWADD_WV }, // 10280
|
|
{ PseudoVWADD_WV_M4_MASK_TIED, VWADD_WV }, // 10281
|
|
{ PseudoVWADD_WV_M4_TIED, VWADD_WV }, // 10282
|
|
{ PseudoVWADD_WV_MF2, VWADD_WV }, // 10283
|
|
{ PseudoVWADD_WV_MF2_MASK, VWADD_WV }, // 10284
|
|
{ PseudoVWADD_WV_MF2_MASK_TIED, VWADD_WV }, // 10285
|
|
{ PseudoVWADD_WV_MF2_TIED, VWADD_WV }, // 10286
|
|
{ PseudoVWADD_WV_MF4, VWADD_WV }, // 10287
|
|
{ PseudoVWADD_WV_MF4_MASK, VWADD_WV }, // 10288
|
|
{ PseudoVWADD_WV_MF4_MASK_TIED, VWADD_WV }, // 10289
|
|
{ PseudoVWADD_WV_MF4_TIED, VWADD_WV }, // 10290
|
|
{ PseudoVWADD_WV_MF8, VWADD_WV }, // 10291
|
|
{ PseudoVWADD_WV_MF8_MASK, VWADD_WV }, // 10292
|
|
{ PseudoVWADD_WV_MF8_MASK_TIED, VWADD_WV }, // 10293
|
|
{ PseudoVWADD_WV_MF8_TIED, VWADD_WV }, // 10294
|
|
{ PseudoVWADD_WX_M1, VWADD_WX }, // 10295
|
|
{ PseudoVWADD_WX_M1_MASK, VWADD_WX }, // 10296
|
|
{ PseudoVWADD_WX_M2, VWADD_WX }, // 10297
|
|
{ PseudoVWADD_WX_M2_MASK, VWADD_WX }, // 10298
|
|
{ PseudoVWADD_WX_M4, VWADD_WX }, // 10299
|
|
{ PseudoVWADD_WX_M4_MASK, VWADD_WX }, // 10300
|
|
{ PseudoVWADD_WX_MF2, VWADD_WX }, // 10301
|
|
{ PseudoVWADD_WX_MF2_MASK, VWADD_WX }, // 10302
|
|
{ PseudoVWADD_WX_MF4, VWADD_WX }, // 10303
|
|
{ PseudoVWADD_WX_MF4_MASK, VWADD_WX }, // 10304
|
|
{ PseudoVWADD_WX_MF8, VWADD_WX }, // 10305
|
|
{ PseudoVWADD_WX_MF8_MASK, VWADD_WX }, // 10306
|
|
{ PseudoVWMACCSU_VV_M1, VWMACCSU_VV }, // 10307
|
|
{ PseudoVWMACCSU_VV_M1_MASK, VWMACCSU_VV }, // 10308
|
|
{ PseudoVWMACCSU_VV_M2, VWMACCSU_VV }, // 10309
|
|
{ PseudoVWMACCSU_VV_M2_MASK, VWMACCSU_VV }, // 10310
|
|
{ PseudoVWMACCSU_VV_M4, VWMACCSU_VV }, // 10311
|
|
{ PseudoVWMACCSU_VV_M4_MASK, VWMACCSU_VV }, // 10312
|
|
{ PseudoVWMACCSU_VV_MF2, VWMACCSU_VV }, // 10313
|
|
{ PseudoVWMACCSU_VV_MF2_MASK, VWMACCSU_VV }, // 10314
|
|
{ PseudoVWMACCSU_VV_MF4, VWMACCSU_VV }, // 10315
|
|
{ PseudoVWMACCSU_VV_MF4_MASK, VWMACCSU_VV }, // 10316
|
|
{ PseudoVWMACCSU_VV_MF8, VWMACCSU_VV }, // 10317
|
|
{ PseudoVWMACCSU_VV_MF8_MASK, VWMACCSU_VV }, // 10318
|
|
{ PseudoVWMACCSU_VX_M1, VWMACCSU_VX }, // 10319
|
|
{ PseudoVWMACCSU_VX_M1_MASK, VWMACCSU_VX }, // 10320
|
|
{ PseudoVWMACCSU_VX_M2, VWMACCSU_VX }, // 10321
|
|
{ PseudoVWMACCSU_VX_M2_MASK, VWMACCSU_VX }, // 10322
|
|
{ PseudoVWMACCSU_VX_M4, VWMACCSU_VX }, // 10323
|
|
{ PseudoVWMACCSU_VX_M4_MASK, VWMACCSU_VX }, // 10324
|
|
{ PseudoVWMACCSU_VX_MF2, VWMACCSU_VX }, // 10325
|
|
{ PseudoVWMACCSU_VX_MF2_MASK, VWMACCSU_VX }, // 10326
|
|
{ PseudoVWMACCSU_VX_MF4, VWMACCSU_VX }, // 10327
|
|
{ PseudoVWMACCSU_VX_MF4_MASK, VWMACCSU_VX }, // 10328
|
|
{ PseudoVWMACCSU_VX_MF8, VWMACCSU_VX }, // 10329
|
|
{ PseudoVWMACCSU_VX_MF8_MASK, VWMACCSU_VX }, // 10330
|
|
{ PseudoVWMACCUS_VX_M1, VWMACCUS_VX }, // 10331
|
|
{ PseudoVWMACCUS_VX_M1_MASK, VWMACCUS_VX }, // 10332
|
|
{ PseudoVWMACCUS_VX_M2, VWMACCUS_VX }, // 10333
|
|
{ PseudoVWMACCUS_VX_M2_MASK, VWMACCUS_VX }, // 10334
|
|
{ PseudoVWMACCUS_VX_M4, VWMACCUS_VX }, // 10335
|
|
{ PseudoVWMACCUS_VX_M4_MASK, VWMACCUS_VX }, // 10336
|
|
{ PseudoVWMACCUS_VX_MF2, VWMACCUS_VX }, // 10337
|
|
{ PseudoVWMACCUS_VX_MF2_MASK, VWMACCUS_VX }, // 10338
|
|
{ PseudoVWMACCUS_VX_MF4, VWMACCUS_VX }, // 10339
|
|
{ PseudoVWMACCUS_VX_MF4_MASK, VWMACCUS_VX }, // 10340
|
|
{ PseudoVWMACCUS_VX_MF8, VWMACCUS_VX }, // 10341
|
|
{ PseudoVWMACCUS_VX_MF8_MASK, VWMACCUS_VX }, // 10342
|
|
{ PseudoVWMACCU_VV_M1, VWMACCU_VV }, // 10343
|
|
{ PseudoVWMACCU_VV_M1_MASK, VWMACCU_VV }, // 10344
|
|
{ PseudoVWMACCU_VV_M2, VWMACCU_VV }, // 10345
|
|
{ PseudoVWMACCU_VV_M2_MASK, VWMACCU_VV }, // 10346
|
|
{ PseudoVWMACCU_VV_M4, VWMACCU_VV }, // 10347
|
|
{ PseudoVWMACCU_VV_M4_MASK, VWMACCU_VV }, // 10348
|
|
{ PseudoVWMACCU_VV_MF2, VWMACCU_VV }, // 10349
|
|
{ PseudoVWMACCU_VV_MF2_MASK, VWMACCU_VV }, // 10350
|
|
{ PseudoVWMACCU_VV_MF4, VWMACCU_VV }, // 10351
|
|
{ PseudoVWMACCU_VV_MF4_MASK, VWMACCU_VV }, // 10352
|
|
{ PseudoVWMACCU_VV_MF8, VWMACCU_VV }, // 10353
|
|
{ PseudoVWMACCU_VV_MF8_MASK, VWMACCU_VV }, // 10354
|
|
{ PseudoVWMACCU_VX_M1, VWMACCU_VX }, // 10355
|
|
{ PseudoVWMACCU_VX_M1_MASK, VWMACCU_VX }, // 10356
|
|
{ PseudoVWMACCU_VX_M2, VWMACCU_VX }, // 10357
|
|
{ PseudoVWMACCU_VX_M2_MASK, VWMACCU_VX }, // 10358
|
|
{ PseudoVWMACCU_VX_M4, VWMACCU_VX }, // 10359
|
|
{ PseudoVWMACCU_VX_M4_MASK, VWMACCU_VX }, // 10360
|
|
{ PseudoVWMACCU_VX_MF2, VWMACCU_VX }, // 10361
|
|
{ PseudoVWMACCU_VX_MF2_MASK, VWMACCU_VX }, // 10362
|
|
{ PseudoVWMACCU_VX_MF4, VWMACCU_VX }, // 10363
|
|
{ PseudoVWMACCU_VX_MF4_MASK, VWMACCU_VX }, // 10364
|
|
{ PseudoVWMACCU_VX_MF8, VWMACCU_VX }, // 10365
|
|
{ PseudoVWMACCU_VX_MF8_MASK, VWMACCU_VX }, // 10366
|
|
{ PseudoVWMACC_VV_M1, VWMACC_VV }, // 10367
|
|
{ PseudoVWMACC_VV_M1_MASK, VWMACC_VV }, // 10368
|
|
{ PseudoVWMACC_VV_M2, VWMACC_VV }, // 10369
|
|
{ PseudoVWMACC_VV_M2_MASK, VWMACC_VV }, // 10370
|
|
{ PseudoVWMACC_VV_M4, VWMACC_VV }, // 10371
|
|
{ PseudoVWMACC_VV_M4_MASK, VWMACC_VV }, // 10372
|
|
{ PseudoVWMACC_VV_MF2, VWMACC_VV }, // 10373
|
|
{ PseudoVWMACC_VV_MF2_MASK, VWMACC_VV }, // 10374
|
|
{ PseudoVWMACC_VV_MF4, VWMACC_VV }, // 10375
|
|
{ PseudoVWMACC_VV_MF4_MASK, VWMACC_VV }, // 10376
|
|
{ PseudoVWMACC_VV_MF8, VWMACC_VV }, // 10377
|
|
{ PseudoVWMACC_VV_MF8_MASK, VWMACC_VV }, // 10378
|
|
{ PseudoVWMACC_VX_M1, VWMACC_VX }, // 10379
|
|
{ PseudoVWMACC_VX_M1_MASK, VWMACC_VX }, // 10380
|
|
{ PseudoVWMACC_VX_M2, VWMACC_VX }, // 10381
|
|
{ PseudoVWMACC_VX_M2_MASK, VWMACC_VX }, // 10382
|
|
{ PseudoVWMACC_VX_M4, VWMACC_VX }, // 10383
|
|
{ PseudoVWMACC_VX_M4_MASK, VWMACC_VX }, // 10384
|
|
{ PseudoVWMACC_VX_MF2, VWMACC_VX }, // 10385
|
|
{ PseudoVWMACC_VX_MF2_MASK, VWMACC_VX }, // 10386
|
|
{ PseudoVWMACC_VX_MF4, VWMACC_VX }, // 10387
|
|
{ PseudoVWMACC_VX_MF4_MASK, VWMACC_VX }, // 10388
|
|
{ PseudoVWMACC_VX_MF8, VWMACC_VX }, // 10389
|
|
{ PseudoVWMACC_VX_MF8_MASK, VWMACC_VX }, // 10390
|
|
{ PseudoVWMULSU_VV_M1, VWMULSU_VV }, // 10391
|
|
{ PseudoVWMULSU_VV_M1_MASK, VWMULSU_VV }, // 10392
|
|
{ PseudoVWMULSU_VV_M2, VWMULSU_VV }, // 10393
|
|
{ PseudoVWMULSU_VV_M2_MASK, VWMULSU_VV }, // 10394
|
|
{ PseudoVWMULSU_VV_M4, VWMULSU_VV }, // 10395
|
|
{ PseudoVWMULSU_VV_M4_MASK, VWMULSU_VV }, // 10396
|
|
{ PseudoVWMULSU_VV_MF2, VWMULSU_VV }, // 10397
|
|
{ PseudoVWMULSU_VV_MF2_MASK, VWMULSU_VV }, // 10398
|
|
{ PseudoVWMULSU_VV_MF4, VWMULSU_VV }, // 10399
|
|
{ PseudoVWMULSU_VV_MF4_MASK, VWMULSU_VV }, // 10400
|
|
{ PseudoVWMULSU_VV_MF8, VWMULSU_VV }, // 10401
|
|
{ PseudoVWMULSU_VV_MF8_MASK, VWMULSU_VV }, // 10402
|
|
{ PseudoVWMULSU_VX_M1, VWMULSU_VX }, // 10403
|
|
{ PseudoVWMULSU_VX_M1_MASK, VWMULSU_VX }, // 10404
|
|
{ PseudoVWMULSU_VX_M2, VWMULSU_VX }, // 10405
|
|
{ PseudoVWMULSU_VX_M2_MASK, VWMULSU_VX }, // 10406
|
|
{ PseudoVWMULSU_VX_M4, VWMULSU_VX }, // 10407
|
|
{ PseudoVWMULSU_VX_M4_MASK, VWMULSU_VX }, // 10408
|
|
{ PseudoVWMULSU_VX_MF2, VWMULSU_VX }, // 10409
|
|
{ PseudoVWMULSU_VX_MF2_MASK, VWMULSU_VX }, // 10410
|
|
{ PseudoVWMULSU_VX_MF4, VWMULSU_VX }, // 10411
|
|
{ PseudoVWMULSU_VX_MF4_MASK, VWMULSU_VX }, // 10412
|
|
{ PseudoVWMULSU_VX_MF8, VWMULSU_VX }, // 10413
|
|
{ PseudoVWMULSU_VX_MF8_MASK, VWMULSU_VX }, // 10414
|
|
{ PseudoVWMULU_VV_M1, VWMULU_VV }, // 10415
|
|
{ PseudoVWMULU_VV_M1_MASK, VWMULU_VV }, // 10416
|
|
{ PseudoVWMULU_VV_M2, VWMULU_VV }, // 10417
|
|
{ PseudoVWMULU_VV_M2_MASK, VWMULU_VV }, // 10418
|
|
{ PseudoVWMULU_VV_M4, VWMULU_VV }, // 10419
|
|
{ PseudoVWMULU_VV_M4_MASK, VWMULU_VV }, // 10420
|
|
{ PseudoVWMULU_VV_MF2, VWMULU_VV }, // 10421
|
|
{ PseudoVWMULU_VV_MF2_MASK, VWMULU_VV }, // 10422
|
|
{ PseudoVWMULU_VV_MF4, VWMULU_VV }, // 10423
|
|
{ PseudoVWMULU_VV_MF4_MASK, VWMULU_VV }, // 10424
|
|
{ PseudoVWMULU_VV_MF8, VWMULU_VV }, // 10425
|
|
{ PseudoVWMULU_VV_MF8_MASK, VWMULU_VV }, // 10426
|
|
{ PseudoVWMULU_VX_M1, VWMULU_VX }, // 10427
|
|
{ PseudoVWMULU_VX_M1_MASK, VWMULU_VX }, // 10428
|
|
{ PseudoVWMULU_VX_M2, VWMULU_VX }, // 10429
|
|
{ PseudoVWMULU_VX_M2_MASK, VWMULU_VX }, // 10430
|
|
{ PseudoVWMULU_VX_M4, VWMULU_VX }, // 10431
|
|
{ PseudoVWMULU_VX_M4_MASK, VWMULU_VX }, // 10432
|
|
{ PseudoVWMULU_VX_MF2, VWMULU_VX }, // 10433
|
|
{ PseudoVWMULU_VX_MF2_MASK, VWMULU_VX }, // 10434
|
|
{ PseudoVWMULU_VX_MF4, VWMULU_VX }, // 10435
|
|
{ PseudoVWMULU_VX_MF4_MASK, VWMULU_VX }, // 10436
|
|
{ PseudoVWMULU_VX_MF8, VWMULU_VX }, // 10437
|
|
{ PseudoVWMULU_VX_MF8_MASK, VWMULU_VX }, // 10438
|
|
{ PseudoVWMUL_VV_M1, VWMUL_VV }, // 10439
|
|
{ PseudoVWMUL_VV_M1_MASK, VWMUL_VV }, // 10440
|
|
{ PseudoVWMUL_VV_M2, VWMUL_VV }, // 10441
|
|
{ PseudoVWMUL_VV_M2_MASK, VWMUL_VV }, // 10442
|
|
{ PseudoVWMUL_VV_M4, VWMUL_VV }, // 10443
|
|
{ PseudoVWMUL_VV_M4_MASK, VWMUL_VV }, // 10444
|
|
{ PseudoVWMUL_VV_MF2, VWMUL_VV }, // 10445
|
|
{ PseudoVWMUL_VV_MF2_MASK, VWMUL_VV }, // 10446
|
|
{ PseudoVWMUL_VV_MF4, VWMUL_VV }, // 10447
|
|
{ PseudoVWMUL_VV_MF4_MASK, VWMUL_VV }, // 10448
|
|
{ PseudoVWMUL_VV_MF8, VWMUL_VV }, // 10449
|
|
{ PseudoVWMUL_VV_MF8_MASK, VWMUL_VV }, // 10450
|
|
{ PseudoVWMUL_VX_M1, VWMUL_VX }, // 10451
|
|
{ PseudoVWMUL_VX_M1_MASK, VWMUL_VX }, // 10452
|
|
{ PseudoVWMUL_VX_M2, VWMUL_VX }, // 10453
|
|
{ PseudoVWMUL_VX_M2_MASK, VWMUL_VX }, // 10454
|
|
{ PseudoVWMUL_VX_M4, VWMUL_VX }, // 10455
|
|
{ PseudoVWMUL_VX_M4_MASK, VWMUL_VX }, // 10456
|
|
{ PseudoVWMUL_VX_MF2, VWMUL_VX }, // 10457
|
|
{ PseudoVWMUL_VX_MF2_MASK, VWMUL_VX }, // 10458
|
|
{ PseudoVWMUL_VX_MF4, VWMUL_VX }, // 10459
|
|
{ PseudoVWMUL_VX_MF4_MASK, VWMUL_VX }, // 10460
|
|
{ PseudoVWMUL_VX_MF8, VWMUL_VX }, // 10461
|
|
{ PseudoVWMUL_VX_MF8_MASK, VWMUL_VX }, // 10462
|
|
{ PseudoVWREDSUMU_VS_M1_E16, VWREDSUMU_VS }, // 10463
|
|
{ PseudoVWREDSUMU_VS_M1_E16_MASK, VWREDSUMU_VS }, // 10464
|
|
{ PseudoVWREDSUMU_VS_M1_E32, VWREDSUMU_VS }, // 10465
|
|
{ PseudoVWREDSUMU_VS_M1_E32_MASK, VWREDSUMU_VS }, // 10466
|
|
{ PseudoVWREDSUMU_VS_M1_E8, VWREDSUMU_VS }, // 10467
|
|
{ PseudoVWREDSUMU_VS_M1_E8_MASK, VWREDSUMU_VS }, // 10468
|
|
{ PseudoVWREDSUMU_VS_M2_E16, VWREDSUMU_VS }, // 10469
|
|
{ PseudoVWREDSUMU_VS_M2_E16_MASK, VWREDSUMU_VS }, // 10470
|
|
{ PseudoVWREDSUMU_VS_M2_E32, VWREDSUMU_VS }, // 10471
|
|
{ PseudoVWREDSUMU_VS_M2_E32_MASK, VWREDSUMU_VS }, // 10472
|
|
{ PseudoVWREDSUMU_VS_M2_E8, VWREDSUMU_VS }, // 10473
|
|
{ PseudoVWREDSUMU_VS_M2_E8_MASK, VWREDSUMU_VS }, // 10474
|
|
{ PseudoVWREDSUMU_VS_M4_E16, VWREDSUMU_VS }, // 10475
|
|
{ PseudoVWREDSUMU_VS_M4_E16_MASK, VWREDSUMU_VS }, // 10476
|
|
{ PseudoVWREDSUMU_VS_M4_E32, VWREDSUMU_VS }, // 10477
|
|
{ PseudoVWREDSUMU_VS_M4_E32_MASK, VWREDSUMU_VS }, // 10478
|
|
{ PseudoVWREDSUMU_VS_M4_E8, VWREDSUMU_VS }, // 10479
|
|
{ PseudoVWREDSUMU_VS_M4_E8_MASK, VWREDSUMU_VS }, // 10480
|
|
{ PseudoVWREDSUMU_VS_M8_E16, VWREDSUMU_VS }, // 10481
|
|
{ PseudoVWREDSUMU_VS_M8_E16_MASK, VWREDSUMU_VS }, // 10482
|
|
{ PseudoVWREDSUMU_VS_M8_E32, VWREDSUMU_VS }, // 10483
|
|
{ PseudoVWREDSUMU_VS_M8_E32_MASK, VWREDSUMU_VS }, // 10484
|
|
{ PseudoVWREDSUMU_VS_M8_E8, VWREDSUMU_VS }, // 10485
|
|
{ PseudoVWREDSUMU_VS_M8_E8_MASK, VWREDSUMU_VS }, // 10486
|
|
{ PseudoVWREDSUMU_VS_MF2_E16, VWREDSUMU_VS }, // 10487
|
|
{ PseudoVWREDSUMU_VS_MF2_E16_MASK, VWREDSUMU_VS }, // 10488
|
|
{ PseudoVWREDSUMU_VS_MF2_E32, VWREDSUMU_VS }, // 10489
|
|
{ PseudoVWREDSUMU_VS_MF2_E32_MASK, VWREDSUMU_VS }, // 10490
|
|
{ PseudoVWREDSUMU_VS_MF2_E8, VWREDSUMU_VS }, // 10491
|
|
{ PseudoVWREDSUMU_VS_MF2_E8_MASK, VWREDSUMU_VS }, // 10492
|
|
{ PseudoVWREDSUMU_VS_MF4_E16, VWREDSUMU_VS }, // 10493
|
|
{ PseudoVWREDSUMU_VS_MF4_E16_MASK, VWREDSUMU_VS }, // 10494
|
|
{ PseudoVWREDSUMU_VS_MF4_E8, VWREDSUMU_VS }, // 10495
|
|
{ PseudoVWREDSUMU_VS_MF4_E8_MASK, VWREDSUMU_VS }, // 10496
|
|
{ PseudoVWREDSUMU_VS_MF8_E8, VWREDSUMU_VS }, // 10497
|
|
{ PseudoVWREDSUMU_VS_MF8_E8_MASK, VWREDSUMU_VS }, // 10498
|
|
{ PseudoVWREDSUM_VS_M1_E16, VWREDSUM_VS }, // 10499
|
|
{ PseudoVWREDSUM_VS_M1_E16_MASK, VWREDSUM_VS }, // 10500
|
|
{ PseudoVWREDSUM_VS_M1_E32, VWREDSUM_VS }, // 10501
|
|
{ PseudoVWREDSUM_VS_M1_E32_MASK, VWREDSUM_VS }, // 10502
|
|
{ PseudoVWREDSUM_VS_M1_E8, VWREDSUM_VS }, // 10503
|
|
{ PseudoVWREDSUM_VS_M1_E8_MASK, VWREDSUM_VS }, // 10504
|
|
{ PseudoVWREDSUM_VS_M2_E16, VWREDSUM_VS }, // 10505
|
|
{ PseudoVWREDSUM_VS_M2_E16_MASK, VWREDSUM_VS }, // 10506
|
|
{ PseudoVWREDSUM_VS_M2_E32, VWREDSUM_VS }, // 10507
|
|
{ PseudoVWREDSUM_VS_M2_E32_MASK, VWREDSUM_VS }, // 10508
|
|
{ PseudoVWREDSUM_VS_M2_E8, VWREDSUM_VS }, // 10509
|
|
{ PseudoVWREDSUM_VS_M2_E8_MASK, VWREDSUM_VS }, // 10510
|
|
{ PseudoVWREDSUM_VS_M4_E16, VWREDSUM_VS }, // 10511
|
|
{ PseudoVWREDSUM_VS_M4_E16_MASK, VWREDSUM_VS }, // 10512
|
|
{ PseudoVWREDSUM_VS_M4_E32, VWREDSUM_VS }, // 10513
|
|
{ PseudoVWREDSUM_VS_M4_E32_MASK, VWREDSUM_VS }, // 10514
|
|
{ PseudoVWREDSUM_VS_M4_E8, VWREDSUM_VS }, // 10515
|
|
{ PseudoVWREDSUM_VS_M4_E8_MASK, VWREDSUM_VS }, // 10516
|
|
{ PseudoVWREDSUM_VS_M8_E16, VWREDSUM_VS }, // 10517
|
|
{ PseudoVWREDSUM_VS_M8_E16_MASK, VWREDSUM_VS }, // 10518
|
|
{ PseudoVWREDSUM_VS_M8_E32, VWREDSUM_VS }, // 10519
|
|
{ PseudoVWREDSUM_VS_M8_E32_MASK, VWREDSUM_VS }, // 10520
|
|
{ PseudoVWREDSUM_VS_M8_E8, VWREDSUM_VS }, // 10521
|
|
{ PseudoVWREDSUM_VS_M8_E8_MASK, VWREDSUM_VS }, // 10522
|
|
{ PseudoVWREDSUM_VS_MF2_E16, VWREDSUM_VS }, // 10523
|
|
{ PseudoVWREDSUM_VS_MF2_E16_MASK, VWREDSUM_VS }, // 10524
|
|
{ PseudoVWREDSUM_VS_MF2_E32, VWREDSUM_VS }, // 10525
|
|
{ PseudoVWREDSUM_VS_MF2_E32_MASK, VWREDSUM_VS }, // 10526
|
|
{ PseudoVWREDSUM_VS_MF2_E8, VWREDSUM_VS }, // 10527
|
|
{ PseudoVWREDSUM_VS_MF2_E8_MASK, VWREDSUM_VS }, // 10528
|
|
{ PseudoVWREDSUM_VS_MF4_E16, VWREDSUM_VS }, // 10529
|
|
{ PseudoVWREDSUM_VS_MF4_E16_MASK, VWREDSUM_VS }, // 10530
|
|
{ PseudoVWREDSUM_VS_MF4_E8, VWREDSUM_VS }, // 10531
|
|
{ PseudoVWREDSUM_VS_MF4_E8_MASK, VWREDSUM_VS }, // 10532
|
|
{ PseudoVWREDSUM_VS_MF8_E8, VWREDSUM_VS }, // 10533
|
|
{ PseudoVWREDSUM_VS_MF8_E8_MASK, VWREDSUM_VS }, // 10534
|
|
{ PseudoVWSLL_VI_M1, VWSLL_VI }, // 10535
|
|
{ PseudoVWSLL_VI_M1_MASK, VWSLL_VI }, // 10536
|
|
{ PseudoVWSLL_VI_M2, VWSLL_VI }, // 10537
|
|
{ PseudoVWSLL_VI_M2_MASK, VWSLL_VI }, // 10538
|
|
{ PseudoVWSLL_VI_M4, VWSLL_VI }, // 10539
|
|
{ PseudoVWSLL_VI_M4_MASK, VWSLL_VI }, // 10540
|
|
{ PseudoVWSLL_VI_MF2, VWSLL_VI }, // 10541
|
|
{ PseudoVWSLL_VI_MF2_MASK, VWSLL_VI }, // 10542
|
|
{ PseudoVWSLL_VI_MF4, VWSLL_VI }, // 10543
|
|
{ PseudoVWSLL_VI_MF4_MASK, VWSLL_VI }, // 10544
|
|
{ PseudoVWSLL_VI_MF8, VWSLL_VI }, // 10545
|
|
{ PseudoVWSLL_VI_MF8_MASK, VWSLL_VI }, // 10546
|
|
{ PseudoVWSLL_VV_M1, VWSLL_VV }, // 10547
|
|
{ PseudoVWSLL_VV_M1_MASK, VWSLL_VV }, // 10548
|
|
{ PseudoVWSLL_VV_M2, VWSLL_VV }, // 10549
|
|
{ PseudoVWSLL_VV_M2_MASK, VWSLL_VV }, // 10550
|
|
{ PseudoVWSLL_VV_M4, VWSLL_VV }, // 10551
|
|
{ PseudoVWSLL_VV_M4_MASK, VWSLL_VV }, // 10552
|
|
{ PseudoVWSLL_VV_MF2, VWSLL_VV }, // 10553
|
|
{ PseudoVWSLL_VV_MF2_MASK, VWSLL_VV }, // 10554
|
|
{ PseudoVWSLL_VV_MF4, VWSLL_VV }, // 10555
|
|
{ PseudoVWSLL_VV_MF4_MASK, VWSLL_VV }, // 10556
|
|
{ PseudoVWSLL_VV_MF8, VWSLL_VV }, // 10557
|
|
{ PseudoVWSLL_VV_MF8_MASK, VWSLL_VV }, // 10558
|
|
{ PseudoVWSLL_VX_M1, VWSLL_VX }, // 10559
|
|
{ PseudoVWSLL_VX_M1_MASK, VWSLL_VX }, // 10560
|
|
{ PseudoVWSLL_VX_M2, VWSLL_VX }, // 10561
|
|
{ PseudoVWSLL_VX_M2_MASK, VWSLL_VX }, // 10562
|
|
{ PseudoVWSLL_VX_M4, VWSLL_VX }, // 10563
|
|
{ PseudoVWSLL_VX_M4_MASK, VWSLL_VX }, // 10564
|
|
{ PseudoVWSLL_VX_MF2, VWSLL_VX }, // 10565
|
|
{ PseudoVWSLL_VX_MF2_MASK, VWSLL_VX }, // 10566
|
|
{ PseudoVWSLL_VX_MF4, VWSLL_VX }, // 10567
|
|
{ PseudoVWSLL_VX_MF4_MASK, VWSLL_VX }, // 10568
|
|
{ PseudoVWSLL_VX_MF8, VWSLL_VX }, // 10569
|
|
{ PseudoVWSLL_VX_MF8_MASK, VWSLL_VX }, // 10570
|
|
{ PseudoVWSUBU_VV_M1, VWSUBU_VV }, // 10571
|
|
{ PseudoVWSUBU_VV_M1_MASK, VWSUBU_VV }, // 10572
|
|
{ PseudoVWSUBU_VV_M2, VWSUBU_VV }, // 10573
|
|
{ PseudoVWSUBU_VV_M2_MASK, VWSUBU_VV }, // 10574
|
|
{ PseudoVWSUBU_VV_M4, VWSUBU_VV }, // 10575
|
|
{ PseudoVWSUBU_VV_M4_MASK, VWSUBU_VV }, // 10576
|
|
{ PseudoVWSUBU_VV_MF2, VWSUBU_VV }, // 10577
|
|
{ PseudoVWSUBU_VV_MF2_MASK, VWSUBU_VV }, // 10578
|
|
{ PseudoVWSUBU_VV_MF4, VWSUBU_VV }, // 10579
|
|
{ PseudoVWSUBU_VV_MF4_MASK, VWSUBU_VV }, // 10580
|
|
{ PseudoVWSUBU_VV_MF8, VWSUBU_VV }, // 10581
|
|
{ PseudoVWSUBU_VV_MF8_MASK, VWSUBU_VV }, // 10582
|
|
{ PseudoVWSUBU_VX_M1, VWSUBU_VX }, // 10583
|
|
{ PseudoVWSUBU_VX_M1_MASK, VWSUBU_VX }, // 10584
|
|
{ PseudoVWSUBU_VX_M2, VWSUBU_VX }, // 10585
|
|
{ PseudoVWSUBU_VX_M2_MASK, VWSUBU_VX }, // 10586
|
|
{ PseudoVWSUBU_VX_M4, VWSUBU_VX }, // 10587
|
|
{ PseudoVWSUBU_VX_M4_MASK, VWSUBU_VX }, // 10588
|
|
{ PseudoVWSUBU_VX_MF2, VWSUBU_VX }, // 10589
|
|
{ PseudoVWSUBU_VX_MF2_MASK, VWSUBU_VX }, // 10590
|
|
{ PseudoVWSUBU_VX_MF4, VWSUBU_VX }, // 10591
|
|
{ PseudoVWSUBU_VX_MF4_MASK, VWSUBU_VX }, // 10592
|
|
{ PseudoVWSUBU_VX_MF8, VWSUBU_VX }, // 10593
|
|
{ PseudoVWSUBU_VX_MF8_MASK, VWSUBU_VX }, // 10594
|
|
{ PseudoVWSUBU_WV_M1, VWSUBU_WV }, // 10595
|
|
{ PseudoVWSUBU_WV_M1_MASK, VWSUBU_WV }, // 10596
|
|
{ PseudoVWSUBU_WV_M1_MASK_TIED, VWSUBU_WV }, // 10597
|
|
{ PseudoVWSUBU_WV_M1_TIED, VWSUBU_WV }, // 10598
|
|
{ PseudoVWSUBU_WV_M2, VWSUBU_WV }, // 10599
|
|
{ PseudoVWSUBU_WV_M2_MASK, VWSUBU_WV }, // 10600
|
|
{ PseudoVWSUBU_WV_M2_MASK_TIED, VWSUBU_WV }, // 10601
|
|
{ PseudoVWSUBU_WV_M2_TIED, VWSUBU_WV }, // 10602
|
|
{ PseudoVWSUBU_WV_M4, VWSUBU_WV }, // 10603
|
|
{ PseudoVWSUBU_WV_M4_MASK, VWSUBU_WV }, // 10604
|
|
{ PseudoVWSUBU_WV_M4_MASK_TIED, VWSUBU_WV }, // 10605
|
|
{ PseudoVWSUBU_WV_M4_TIED, VWSUBU_WV }, // 10606
|
|
{ PseudoVWSUBU_WV_MF2, VWSUBU_WV }, // 10607
|
|
{ PseudoVWSUBU_WV_MF2_MASK, VWSUBU_WV }, // 10608
|
|
{ PseudoVWSUBU_WV_MF2_MASK_TIED, VWSUBU_WV }, // 10609
|
|
{ PseudoVWSUBU_WV_MF2_TIED, VWSUBU_WV }, // 10610
|
|
{ PseudoVWSUBU_WV_MF4, VWSUBU_WV }, // 10611
|
|
{ PseudoVWSUBU_WV_MF4_MASK, VWSUBU_WV }, // 10612
|
|
{ PseudoVWSUBU_WV_MF4_MASK_TIED, VWSUBU_WV }, // 10613
|
|
{ PseudoVWSUBU_WV_MF4_TIED, VWSUBU_WV }, // 10614
|
|
{ PseudoVWSUBU_WV_MF8, VWSUBU_WV }, // 10615
|
|
{ PseudoVWSUBU_WV_MF8_MASK, VWSUBU_WV }, // 10616
|
|
{ PseudoVWSUBU_WV_MF8_MASK_TIED, VWSUBU_WV }, // 10617
|
|
{ PseudoVWSUBU_WV_MF8_TIED, VWSUBU_WV }, // 10618
|
|
{ PseudoVWSUBU_WX_M1, VWSUBU_WX }, // 10619
|
|
{ PseudoVWSUBU_WX_M1_MASK, VWSUBU_WX }, // 10620
|
|
{ PseudoVWSUBU_WX_M2, VWSUBU_WX }, // 10621
|
|
{ PseudoVWSUBU_WX_M2_MASK, VWSUBU_WX }, // 10622
|
|
{ PseudoVWSUBU_WX_M4, VWSUBU_WX }, // 10623
|
|
{ PseudoVWSUBU_WX_M4_MASK, VWSUBU_WX }, // 10624
|
|
{ PseudoVWSUBU_WX_MF2, VWSUBU_WX }, // 10625
|
|
{ PseudoVWSUBU_WX_MF2_MASK, VWSUBU_WX }, // 10626
|
|
{ PseudoVWSUBU_WX_MF4, VWSUBU_WX }, // 10627
|
|
{ PseudoVWSUBU_WX_MF4_MASK, VWSUBU_WX }, // 10628
|
|
{ PseudoVWSUBU_WX_MF8, VWSUBU_WX }, // 10629
|
|
{ PseudoVWSUBU_WX_MF8_MASK, VWSUBU_WX }, // 10630
|
|
{ PseudoVWSUB_VV_M1, VWSUB_VV }, // 10631
|
|
{ PseudoVWSUB_VV_M1_MASK, VWSUB_VV }, // 10632
|
|
{ PseudoVWSUB_VV_M2, VWSUB_VV }, // 10633
|
|
{ PseudoVWSUB_VV_M2_MASK, VWSUB_VV }, // 10634
|
|
{ PseudoVWSUB_VV_M4, VWSUB_VV }, // 10635
|
|
{ PseudoVWSUB_VV_M4_MASK, VWSUB_VV }, // 10636
|
|
{ PseudoVWSUB_VV_MF2, VWSUB_VV }, // 10637
|
|
{ PseudoVWSUB_VV_MF2_MASK, VWSUB_VV }, // 10638
|
|
{ PseudoVWSUB_VV_MF4, VWSUB_VV }, // 10639
|
|
{ PseudoVWSUB_VV_MF4_MASK, VWSUB_VV }, // 10640
|
|
{ PseudoVWSUB_VV_MF8, VWSUB_VV }, // 10641
|
|
{ PseudoVWSUB_VV_MF8_MASK, VWSUB_VV }, // 10642
|
|
{ PseudoVWSUB_VX_M1, VWSUB_VX }, // 10643
|
|
{ PseudoVWSUB_VX_M1_MASK, VWSUB_VX }, // 10644
|
|
{ PseudoVWSUB_VX_M2, VWSUB_VX }, // 10645
|
|
{ PseudoVWSUB_VX_M2_MASK, VWSUB_VX }, // 10646
|
|
{ PseudoVWSUB_VX_M4, VWSUB_VX }, // 10647
|
|
{ PseudoVWSUB_VX_M4_MASK, VWSUB_VX }, // 10648
|
|
{ PseudoVWSUB_VX_MF2, VWSUB_VX }, // 10649
|
|
{ PseudoVWSUB_VX_MF2_MASK, VWSUB_VX }, // 10650
|
|
{ PseudoVWSUB_VX_MF4, VWSUB_VX }, // 10651
|
|
{ PseudoVWSUB_VX_MF4_MASK, VWSUB_VX }, // 10652
|
|
{ PseudoVWSUB_VX_MF8, VWSUB_VX }, // 10653
|
|
{ PseudoVWSUB_VX_MF8_MASK, VWSUB_VX }, // 10654
|
|
{ PseudoVWSUB_WV_M1, VWSUB_WV }, // 10655
|
|
{ PseudoVWSUB_WV_M1_MASK, VWSUB_WV }, // 10656
|
|
{ PseudoVWSUB_WV_M1_MASK_TIED, VWSUB_WV }, // 10657
|
|
{ PseudoVWSUB_WV_M1_TIED, VWSUB_WV }, // 10658
|
|
{ PseudoVWSUB_WV_M2, VWSUB_WV }, // 10659
|
|
{ PseudoVWSUB_WV_M2_MASK, VWSUB_WV }, // 10660
|
|
{ PseudoVWSUB_WV_M2_MASK_TIED, VWSUB_WV }, // 10661
|
|
{ PseudoVWSUB_WV_M2_TIED, VWSUB_WV }, // 10662
|
|
{ PseudoVWSUB_WV_M4, VWSUB_WV }, // 10663
|
|
{ PseudoVWSUB_WV_M4_MASK, VWSUB_WV }, // 10664
|
|
{ PseudoVWSUB_WV_M4_MASK_TIED, VWSUB_WV }, // 10665
|
|
{ PseudoVWSUB_WV_M4_TIED, VWSUB_WV }, // 10666
|
|
{ PseudoVWSUB_WV_MF2, VWSUB_WV }, // 10667
|
|
{ PseudoVWSUB_WV_MF2_MASK, VWSUB_WV }, // 10668
|
|
{ PseudoVWSUB_WV_MF2_MASK_TIED, VWSUB_WV }, // 10669
|
|
{ PseudoVWSUB_WV_MF2_TIED, VWSUB_WV }, // 10670
|
|
{ PseudoVWSUB_WV_MF4, VWSUB_WV }, // 10671
|
|
{ PseudoVWSUB_WV_MF4_MASK, VWSUB_WV }, // 10672
|
|
{ PseudoVWSUB_WV_MF4_MASK_TIED, VWSUB_WV }, // 10673
|
|
{ PseudoVWSUB_WV_MF4_TIED, VWSUB_WV }, // 10674
|
|
{ PseudoVWSUB_WV_MF8, VWSUB_WV }, // 10675
|
|
{ PseudoVWSUB_WV_MF8_MASK, VWSUB_WV }, // 10676
|
|
{ PseudoVWSUB_WV_MF8_MASK_TIED, VWSUB_WV }, // 10677
|
|
{ PseudoVWSUB_WV_MF8_TIED, VWSUB_WV }, // 10678
|
|
{ PseudoVWSUB_WX_M1, VWSUB_WX }, // 10679
|
|
{ PseudoVWSUB_WX_M1_MASK, VWSUB_WX }, // 10680
|
|
{ PseudoVWSUB_WX_M2, VWSUB_WX }, // 10681
|
|
{ PseudoVWSUB_WX_M2_MASK, VWSUB_WX }, // 10682
|
|
{ PseudoVWSUB_WX_M4, VWSUB_WX }, // 10683
|
|
{ PseudoVWSUB_WX_M4_MASK, VWSUB_WX }, // 10684
|
|
{ PseudoVWSUB_WX_MF2, VWSUB_WX }, // 10685
|
|
{ PseudoVWSUB_WX_MF2_MASK, VWSUB_WX }, // 10686
|
|
{ PseudoVWSUB_WX_MF4, VWSUB_WX }, // 10687
|
|
{ PseudoVWSUB_WX_MF4_MASK, VWSUB_WX }, // 10688
|
|
{ PseudoVWSUB_WX_MF8, VWSUB_WX }, // 10689
|
|
{ PseudoVWSUB_WX_MF8_MASK, VWSUB_WX }, // 10690
|
|
{ PseudoVXOR_VI_M1, VXOR_VI }, // 10691
|
|
{ PseudoVXOR_VI_M1_MASK, VXOR_VI }, // 10692
|
|
{ PseudoVXOR_VI_M2, VXOR_VI }, // 10693
|
|
{ PseudoVXOR_VI_M2_MASK, VXOR_VI }, // 10694
|
|
{ PseudoVXOR_VI_M4, VXOR_VI }, // 10695
|
|
{ PseudoVXOR_VI_M4_MASK, VXOR_VI }, // 10696
|
|
{ PseudoVXOR_VI_M8, VXOR_VI }, // 10697
|
|
{ PseudoVXOR_VI_M8_MASK, VXOR_VI }, // 10698
|
|
{ PseudoVXOR_VI_MF2, VXOR_VI }, // 10699
|
|
{ PseudoVXOR_VI_MF2_MASK, VXOR_VI }, // 10700
|
|
{ PseudoVXOR_VI_MF4, VXOR_VI }, // 10701
|
|
{ PseudoVXOR_VI_MF4_MASK, VXOR_VI }, // 10702
|
|
{ PseudoVXOR_VI_MF8, VXOR_VI }, // 10703
|
|
{ PseudoVXOR_VI_MF8_MASK, VXOR_VI }, // 10704
|
|
{ PseudoVXOR_VV_M1, VXOR_VV }, // 10705
|
|
{ PseudoVXOR_VV_M1_MASK, VXOR_VV }, // 10706
|
|
{ PseudoVXOR_VV_M2, VXOR_VV }, // 10707
|
|
{ PseudoVXOR_VV_M2_MASK, VXOR_VV }, // 10708
|
|
{ PseudoVXOR_VV_M4, VXOR_VV }, // 10709
|
|
{ PseudoVXOR_VV_M4_MASK, VXOR_VV }, // 10710
|
|
{ PseudoVXOR_VV_M8, VXOR_VV }, // 10711
|
|
{ PseudoVXOR_VV_M8_MASK, VXOR_VV }, // 10712
|
|
{ PseudoVXOR_VV_MF2, VXOR_VV }, // 10713
|
|
{ PseudoVXOR_VV_MF2_MASK, VXOR_VV }, // 10714
|
|
{ PseudoVXOR_VV_MF4, VXOR_VV }, // 10715
|
|
{ PseudoVXOR_VV_MF4_MASK, VXOR_VV }, // 10716
|
|
{ PseudoVXOR_VV_MF8, VXOR_VV }, // 10717
|
|
{ PseudoVXOR_VV_MF8_MASK, VXOR_VV }, // 10718
|
|
{ PseudoVXOR_VX_M1, VXOR_VX }, // 10719
|
|
{ PseudoVXOR_VX_M1_MASK, VXOR_VX }, // 10720
|
|
{ PseudoVXOR_VX_M2, VXOR_VX }, // 10721
|
|
{ PseudoVXOR_VX_M2_MASK, VXOR_VX }, // 10722
|
|
{ PseudoVXOR_VX_M4, VXOR_VX }, // 10723
|
|
{ PseudoVXOR_VX_M4_MASK, VXOR_VX }, // 10724
|
|
{ PseudoVXOR_VX_M8, VXOR_VX }, // 10725
|
|
{ PseudoVXOR_VX_M8_MASK, VXOR_VX }, // 10726
|
|
{ PseudoVXOR_VX_MF2, VXOR_VX }, // 10727
|
|
{ PseudoVXOR_VX_MF2_MASK, VXOR_VX }, // 10728
|
|
{ PseudoVXOR_VX_MF4, VXOR_VX }, // 10729
|
|
{ PseudoVXOR_VX_MF4_MASK, VXOR_VX }, // 10730
|
|
{ PseudoVXOR_VX_MF8, VXOR_VX }, // 10731
|
|
{ PseudoVXOR_VX_MF8_MASK, VXOR_VX }, // 10732
|
|
{ PseudoVZEXT_VF2_M1, VZEXT_VF2 }, // 10733
|
|
{ PseudoVZEXT_VF2_M1_MASK, VZEXT_VF2 }, // 10734
|
|
{ PseudoVZEXT_VF2_M2, VZEXT_VF2 }, // 10735
|
|
{ PseudoVZEXT_VF2_M2_MASK, VZEXT_VF2 }, // 10736
|
|
{ PseudoVZEXT_VF2_M4, VZEXT_VF2 }, // 10737
|
|
{ PseudoVZEXT_VF2_M4_MASK, VZEXT_VF2 }, // 10738
|
|
{ PseudoVZEXT_VF2_M8, VZEXT_VF2 }, // 10739
|
|
{ PseudoVZEXT_VF2_M8_MASK, VZEXT_VF2 }, // 10740
|
|
{ PseudoVZEXT_VF2_MF2, VZEXT_VF2 }, // 10741
|
|
{ PseudoVZEXT_VF2_MF2_MASK, VZEXT_VF2 }, // 10742
|
|
{ PseudoVZEXT_VF2_MF4, VZEXT_VF2 }, // 10743
|
|
{ PseudoVZEXT_VF2_MF4_MASK, VZEXT_VF2 }, // 10744
|
|
{ PseudoVZEXT_VF4_M1, VZEXT_VF4 }, // 10745
|
|
{ PseudoVZEXT_VF4_M1_MASK, VZEXT_VF4 }, // 10746
|
|
{ PseudoVZEXT_VF4_M2, VZEXT_VF4 }, // 10747
|
|
{ PseudoVZEXT_VF4_M2_MASK, VZEXT_VF4 }, // 10748
|
|
{ PseudoVZEXT_VF4_M4, VZEXT_VF4 }, // 10749
|
|
{ PseudoVZEXT_VF4_M4_MASK, VZEXT_VF4 }, // 10750
|
|
{ PseudoVZEXT_VF4_M8, VZEXT_VF4 }, // 10751
|
|
{ PseudoVZEXT_VF4_M8_MASK, VZEXT_VF4 }, // 10752
|
|
{ PseudoVZEXT_VF4_MF2, VZEXT_VF4 }, // 10753
|
|
{ PseudoVZEXT_VF4_MF2_MASK, VZEXT_VF4 }, // 10754
|
|
{ PseudoVZEXT_VF8_M1, VZEXT_VF8 }, // 10755
|
|
{ PseudoVZEXT_VF8_M1_MASK, VZEXT_VF8 }, // 10756
|
|
{ PseudoVZEXT_VF8_M2, VZEXT_VF8 }, // 10757
|
|
{ PseudoVZEXT_VF8_M2_MASK, VZEXT_VF8 }, // 10758
|
|
{ PseudoVZEXT_VF8_M4, VZEXT_VF8 }, // 10759
|
|
{ PseudoVZEXT_VF8_M4_MASK, VZEXT_VF8 }, // 10760
|
|
{ PseudoVZEXT_VF8_M8, VZEXT_VF8 }, // 10761
|
|
{ PseudoVZEXT_VF8_M8_MASK, VZEXT_VF8 }, // 10762
|
|
};
|
|
|
|
const RISCV_PseudoInfo *RISCV_getPseudoInfo(unsigned Pseudo) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Pseudo);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVPseudosTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVSETable_IMPL
|
|
static const RISCV_VSEPseudo RISCVVSETable[] = {
|
|
{ 0x0, 0x0, 0x0, 0x0, PseudoVSM_V_B8 }, // 0
|
|
{ 0x0, 0x0, 0x0, 0x1, PseudoVSM_V_B16 }, // 1
|
|
{ 0x0, 0x0, 0x0, 0x2, PseudoVSM_V_B32 }, // 2
|
|
{ 0x0, 0x0, 0x0, 0x3, PseudoVSM_V_B64 }, // 3
|
|
{ 0x0, 0x0, 0x0, 0x5, PseudoVSM_V_B1 }, // 4
|
|
{ 0x0, 0x0, 0x0, 0x6, PseudoVSM_V_B2 }, // 5
|
|
{ 0x0, 0x0, 0x0, 0x7, PseudoVSM_V_B4 }, // 6
|
|
{ 0x0, 0x0, 0x3, 0x0, PseudoVSE8_V_M1 }, // 7
|
|
{ 0x0, 0x0, 0x3, 0x1, PseudoVSE8_V_M2 }, // 8
|
|
{ 0x0, 0x0, 0x3, 0x2, PseudoVSE8_V_M4 }, // 9
|
|
{ 0x0, 0x0, 0x3, 0x3, PseudoVSE8_V_M8 }, // 10
|
|
{ 0x0, 0x0, 0x3, 0x5, PseudoVSE8_V_MF8 }, // 11
|
|
{ 0x0, 0x0, 0x3, 0x6, PseudoVSE8_V_MF4 }, // 12
|
|
{ 0x0, 0x0, 0x3, 0x7, PseudoVSE8_V_MF2 }, // 13
|
|
{ 0x0, 0x0, 0x4, 0x0, PseudoVSE16_V_M1 }, // 14
|
|
{ 0x0, 0x0, 0x4, 0x1, PseudoVSE16_V_M2 }, // 15
|
|
{ 0x0, 0x0, 0x4, 0x2, PseudoVSE16_V_M4 }, // 16
|
|
{ 0x0, 0x0, 0x4, 0x3, PseudoVSE16_V_M8 }, // 17
|
|
{ 0x0, 0x0, 0x4, 0x6, PseudoVSE16_V_MF4 }, // 18
|
|
{ 0x0, 0x0, 0x4, 0x7, PseudoVSE16_V_MF2 }, // 19
|
|
{ 0x0, 0x0, 0x5, 0x0, PseudoVSE32_V_M1 }, // 20
|
|
{ 0x0, 0x0, 0x5, 0x1, PseudoVSE32_V_M2 }, // 21
|
|
{ 0x0, 0x0, 0x5, 0x2, PseudoVSE32_V_M4 }, // 22
|
|
{ 0x0, 0x0, 0x5, 0x3, PseudoVSE32_V_M8 }, // 23
|
|
{ 0x0, 0x0, 0x5, 0x7, PseudoVSE32_V_MF2 }, // 24
|
|
{ 0x0, 0x0, 0x6, 0x0, PseudoVSE64_V_M1 }, // 25
|
|
{ 0x0, 0x0, 0x6, 0x1, PseudoVSE64_V_M2 }, // 26
|
|
{ 0x0, 0x0, 0x6, 0x2, PseudoVSE64_V_M4 }, // 27
|
|
{ 0x0, 0x0, 0x6, 0x3, PseudoVSE64_V_M8 }, // 28
|
|
{ 0x0, 0x1, 0x3, 0x0, PseudoVSSE8_V_M1 }, // 29
|
|
{ 0x0, 0x1, 0x3, 0x1, PseudoVSSE8_V_M2 }, // 30
|
|
{ 0x0, 0x1, 0x3, 0x2, PseudoVSSE8_V_M4 }, // 31
|
|
{ 0x0, 0x1, 0x3, 0x3, PseudoVSSE8_V_M8 }, // 32
|
|
{ 0x0, 0x1, 0x3, 0x5, PseudoVSSE8_V_MF8 }, // 33
|
|
{ 0x0, 0x1, 0x3, 0x6, PseudoVSSE8_V_MF4 }, // 34
|
|
{ 0x0, 0x1, 0x3, 0x7, PseudoVSSE8_V_MF2 }, // 35
|
|
{ 0x0, 0x1, 0x4, 0x0, PseudoVSSE16_V_M1 }, // 36
|
|
{ 0x0, 0x1, 0x4, 0x1, PseudoVSSE16_V_M2 }, // 37
|
|
{ 0x0, 0x1, 0x4, 0x2, PseudoVSSE16_V_M4 }, // 38
|
|
{ 0x0, 0x1, 0x4, 0x3, PseudoVSSE16_V_M8 }, // 39
|
|
{ 0x0, 0x1, 0x4, 0x6, PseudoVSSE16_V_MF4 }, // 40
|
|
{ 0x0, 0x1, 0x4, 0x7, PseudoVSSE16_V_MF2 }, // 41
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|
{ 0x0, 0x1, 0x5, 0x0, PseudoVSSE32_V_M1 }, // 42
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|
{ 0x0, 0x1, 0x5, 0x1, PseudoVSSE32_V_M2 }, // 43
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|
{ 0x0, 0x1, 0x5, 0x2, PseudoVSSE32_V_M4 }, // 44
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|
{ 0x0, 0x1, 0x5, 0x3, PseudoVSSE32_V_M8 }, // 45
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|
{ 0x0, 0x1, 0x5, 0x7, PseudoVSSE32_V_MF2 }, // 46
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|
{ 0x0, 0x1, 0x6, 0x0, PseudoVSSE64_V_M1 }, // 47
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|
{ 0x0, 0x1, 0x6, 0x1, PseudoVSSE64_V_M2 }, // 48
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|
{ 0x0, 0x1, 0x6, 0x2, PseudoVSSE64_V_M4 }, // 49
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|
{ 0x0, 0x1, 0x6, 0x3, PseudoVSSE64_V_M8 }, // 50
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|
{ 0x1, 0x0, 0x3, 0x0, PseudoVSE8_V_M1_MASK }, // 51
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{ 0x1, 0x0, 0x3, 0x1, PseudoVSE8_V_M2_MASK }, // 52
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|
{ 0x1, 0x0, 0x3, 0x2, PseudoVSE8_V_M4_MASK }, // 53
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|
{ 0x1, 0x0, 0x3, 0x3, PseudoVSE8_V_M8_MASK }, // 54
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|
{ 0x1, 0x0, 0x3, 0x5, PseudoVSE8_V_MF8_MASK }, // 55
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|
{ 0x1, 0x0, 0x3, 0x6, PseudoVSE8_V_MF4_MASK }, // 56
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|
{ 0x1, 0x0, 0x3, 0x7, PseudoVSE8_V_MF2_MASK }, // 57
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{ 0x1, 0x0, 0x4, 0x0, PseudoVSE16_V_M1_MASK }, // 58
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{ 0x1, 0x0, 0x4, 0x1, PseudoVSE16_V_M2_MASK }, // 59
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|
{ 0x1, 0x0, 0x4, 0x2, PseudoVSE16_V_M4_MASK }, // 60
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{ 0x1, 0x0, 0x4, 0x3, PseudoVSE16_V_M8_MASK }, // 61
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{ 0x1, 0x0, 0x4, 0x6, PseudoVSE16_V_MF4_MASK }, // 62
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|
{ 0x1, 0x0, 0x4, 0x7, PseudoVSE16_V_MF2_MASK }, // 63
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|
{ 0x1, 0x0, 0x5, 0x0, PseudoVSE32_V_M1_MASK }, // 64
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|
{ 0x1, 0x0, 0x5, 0x1, PseudoVSE32_V_M2_MASK }, // 65
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|
{ 0x1, 0x0, 0x5, 0x2, PseudoVSE32_V_M4_MASK }, // 66
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{ 0x1, 0x0, 0x5, 0x3, PseudoVSE32_V_M8_MASK }, // 67
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|
{ 0x1, 0x0, 0x5, 0x7, PseudoVSE32_V_MF2_MASK }, // 68
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|
{ 0x1, 0x0, 0x6, 0x0, PseudoVSE64_V_M1_MASK }, // 69
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|
{ 0x1, 0x0, 0x6, 0x1, PseudoVSE64_V_M2_MASK }, // 70
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|
{ 0x1, 0x0, 0x6, 0x2, PseudoVSE64_V_M4_MASK }, // 71
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|
{ 0x1, 0x0, 0x6, 0x3, PseudoVSE64_V_M8_MASK }, // 72
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|
{ 0x1, 0x1, 0x3, 0x0, PseudoVSSE8_V_M1_MASK }, // 73
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|
{ 0x1, 0x1, 0x3, 0x1, PseudoVSSE8_V_M2_MASK }, // 74
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|
{ 0x1, 0x1, 0x3, 0x2, PseudoVSSE8_V_M4_MASK }, // 75
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|
{ 0x1, 0x1, 0x3, 0x3, PseudoVSSE8_V_M8_MASK }, // 76
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|
{ 0x1, 0x1, 0x3, 0x5, PseudoVSSE8_V_MF8_MASK }, // 77
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|
{ 0x1, 0x1, 0x3, 0x6, PseudoVSSE8_V_MF4_MASK }, // 78
|
|
{ 0x1, 0x1, 0x3, 0x7, PseudoVSSE8_V_MF2_MASK }, // 79
|
|
{ 0x1, 0x1, 0x4, 0x0, PseudoVSSE16_V_M1_MASK }, // 80
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|
{ 0x1, 0x1, 0x4, 0x1, PseudoVSSE16_V_M2_MASK }, // 81
|
|
{ 0x1, 0x1, 0x4, 0x2, PseudoVSSE16_V_M4_MASK }, // 82
|
|
{ 0x1, 0x1, 0x4, 0x3, PseudoVSSE16_V_M8_MASK }, // 83
|
|
{ 0x1, 0x1, 0x4, 0x6, PseudoVSSE16_V_MF4_MASK }, // 84
|
|
{ 0x1, 0x1, 0x4, 0x7, PseudoVSSE16_V_MF2_MASK }, // 85
|
|
{ 0x1, 0x1, 0x5, 0x0, PseudoVSSE32_V_M1_MASK }, // 86
|
|
{ 0x1, 0x1, 0x5, 0x1, PseudoVSSE32_V_M2_MASK }, // 87
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|
{ 0x1, 0x1, 0x5, 0x2, PseudoVSSE32_V_M4_MASK }, // 88
|
|
{ 0x1, 0x1, 0x5, 0x3, PseudoVSSE32_V_M8_MASK }, // 89
|
|
{ 0x1, 0x1, 0x5, 0x7, PseudoVSSE32_V_MF2_MASK }, // 90
|
|
{ 0x1, 0x1, 0x6, 0x0, PseudoVSSE64_V_M1_MASK }, // 91
|
|
{ 0x1, 0x1, 0x6, 0x1, PseudoVSSE64_V_M2_MASK }, // 92
|
|
{ 0x1, 0x1, 0x6, 0x2, PseudoVSSE64_V_M4_MASK }, // 93
|
|
{ 0x1, 0x1, 0x6, 0x3, PseudoVSSE64_V_M8_MASK }, // 94
|
|
};
|
|
|
|
const RISCV_VSEPseudo *RISCV_getVSEPseudo(uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedStridedLog2SEWLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVSETable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVSSEGTable_IMPL
|
|
static const RISCV_VSSEGPseudo RISCVVSSEGTable[] = {
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG2E8_V_M1 }, // 0
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG2E8_V_M2 }, // 1
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, PseudoVSSEG2E8_V_M4 }, // 2
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG2E8_V_MF8 }, // 3
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG2E8_V_MF4 }, // 4
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG2E8_V_MF2 }, // 5
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG2E16_V_M1 }, // 6
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG2E16_V_M2 }, // 7
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, PseudoVSSEG2E16_V_M4 }, // 8
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG2E16_V_MF4 }, // 9
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG2E16_V_MF2 }, // 10
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG2E32_V_M1 }, // 11
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG2E32_V_M2 }, // 12
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, PseudoVSSEG2E32_V_M4 }, // 13
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG2E32_V_MF2 }, // 14
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG2E64_V_M1 }, // 15
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG2E64_V_M2 }, // 16
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x2, PseudoVSSEG2E64_V_M4 }, // 17
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG2E8_V_M1 }, // 18
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG2E8_V_M2 }, // 19
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x2, PseudoVSSSEG2E8_V_M4 }, // 20
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG2E8_V_MF8 }, // 21
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG2E8_V_MF4 }, // 22
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG2E8_V_MF2 }, // 23
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG2E16_V_M1 }, // 24
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG2E16_V_M2 }, // 25
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x2, PseudoVSSSEG2E16_V_M4 }, // 26
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG2E16_V_MF4 }, // 27
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG2E16_V_MF2 }, // 28
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG2E32_V_M1 }, // 29
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG2E32_V_M2 }, // 30
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x2, PseudoVSSSEG2E32_V_M4 }, // 31
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG2E32_V_MF2 }, // 32
|
|
{ 0x2, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG2E64_V_M1 }, // 33
|
|
{ 0x2, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG2E64_V_M2 }, // 34
|
|
{ 0x2, 0x0, 0x1, 0x6, 0x2, PseudoVSSSEG2E64_V_M4 }, // 35
|
|
{ 0x2, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG2E8_V_M1_MASK }, // 36
|
|
{ 0x2, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG2E8_V_M2_MASK }, // 37
|
|
{ 0x2, 0x1, 0x0, 0x3, 0x2, PseudoVSSEG2E8_V_M4_MASK }, // 38
|
|
{ 0x2, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG2E8_V_MF8_MASK }, // 39
|
|
{ 0x2, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG2E8_V_MF4_MASK }, // 40
|
|
{ 0x2, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG2E8_V_MF2_MASK }, // 41
|
|
{ 0x2, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG2E16_V_M1_MASK }, // 42
|
|
{ 0x2, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG2E16_V_M2_MASK }, // 43
|
|
{ 0x2, 0x1, 0x0, 0x4, 0x2, PseudoVSSEG2E16_V_M4_MASK }, // 44
|
|
{ 0x2, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG2E16_V_MF4_MASK }, // 45
|
|
{ 0x2, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG2E16_V_MF2_MASK }, // 46
|
|
{ 0x2, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG2E32_V_M1_MASK }, // 47
|
|
{ 0x2, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG2E32_V_M2_MASK }, // 48
|
|
{ 0x2, 0x1, 0x0, 0x5, 0x2, PseudoVSSEG2E32_V_M4_MASK }, // 49
|
|
{ 0x2, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG2E32_V_MF2_MASK }, // 50
|
|
{ 0x2, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG2E64_V_M1_MASK }, // 51
|
|
{ 0x2, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG2E64_V_M2_MASK }, // 52
|
|
{ 0x2, 0x1, 0x0, 0x6, 0x2, PseudoVSSEG2E64_V_M4_MASK }, // 53
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG2E8_V_M1_MASK }, // 54
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG2E8_V_M2_MASK }, // 55
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x2, PseudoVSSSEG2E8_V_M4_MASK }, // 56
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG2E8_V_MF8_MASK }, // 57
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG2E8_V_MF4_MASK }, // 58
|
|
{ 0x2, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG2E8_V_MF2_MASK }, // 59
|
|
{ 0x2, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG2E16_V_M1_MASK }, // 60
|
|
{ 0x2, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG2E16_V_M2_MASK }, // 61
|
|
{ 0x2, 0x1, 0x1, 0x4, 0x2, PseudoVSSSEG2E16_V_M4_MASK }, // 62
|
|
{ 0x2, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG2E16_V_MF4_MASK }, // 63
|
|
{ 0x2, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG2E16_V_MF2_MASK }, // 64
|
|
{ 0x2, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG2E32_V_M1_MASK }, // 65
|
|
{ 0x2, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG2E32_V_M2_MASK }, // 66
|
|
{ 0x2, 0x1, 0x1, 0x5, 0x2, PseudoVSSSEG2E32_V_M4_MASK }, // 67
|
|
{ 0x2, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG2E32_V_MF2_MASK }, // 68
|
|
{ 0x2, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG2E64_V_M1_MASK }, // 69
|
|
{ 0x2, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG2E64_V_M2_MASK }, // 70
|
|
{ 0x2, 0x1, 0x1, 0x6, 0x2, PseudoVSSSEG2E64_V_M4_MASK }, // 71
|
|
{ 0x3, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG3E8_V_M1 }, // 72
|
|
{ 0x3, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG3E8_V_M2 }, // 73
|
|
{ 0x3, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG3E8_V_MF8 }, // 74
|
|
{ 0x3, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG3E8_V_MF4 }, // 75
|
|
{ 0x3, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG3E8_V_MF2 }, // 76
|
|
{ 0x3, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG3E16_V_M1 }, // 77
|
|
{ 0x3, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG3E16_V_M2 }, // 78
|
|
{ 0x3, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG3E16_V_MF4 }, // 79
|
|
{ 0x3, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG3E16_V_MF2 }, // 80
|
|
{ 0x3, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG3E32_V_M1 }, // 81
|
|
{ 0x3, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG3E32_V_M2 }, // 82
|
|
{ 0x3, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG3E32_V_MF2 }, // 83
|
|
{ 0x3, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG3E64_V_M1 }, // 84
|
|
{ 0x3, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG3E64_V_M2 }, // 85
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG3E8_V_M1 }, // 86
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG3E8_V_M2 }, // 87
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG3E8_V_MF8 }, // 88
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG3E8_V_MF4 }, // 89
|
|
{ 0x3, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG3E8_V_MF2 }, // 90
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG3E16_V_M1 }, // 91
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG3E16_V_M2 }, // 92
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG3E16_V_MF4 }, // 93
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG3E16_V_MF2 }, // 94
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG3E32_V_M1 }, // 95
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG3E32_V_M2 }, // 96
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG3E32_V_MF2 }, // 97
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG3E64_V_M1 }, // 98
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG3E64_V_M2 }, // 99
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG3E8_V_M1_MASK }, // 100
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG3E8_V_M2_MASK }, // 101
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG3E8_V_MF8_MASK }, // 102
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG3E8_V_MF4_MASK }, // 103
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG3E8_V_MF2_MASK }, // 104
|
|
{ 0x3, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG3E16_V_M1_MASK }, // 105
|
|
{ 0x3, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG3E16_V_M2_MASK }, // 106
|
|
{ 0x3, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG3E16_V_MF4_MASK }, // 107
|
|
{ 0x3, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG3E16_V_MF2_MASK }, // 108
|
|
{ 0x3, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG3E32_V_M1_MASK }, // 109
|
|
{ 0x3, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG3E32_V_M2_MASK }, // 110
|
|
{ 0x3, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG3E32_V_MF2_MASK }, // 111
|
|
{ 0x3, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG3E64_V_M1_MASK }, // 112
|
|
{ 0x3, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG3E64_V_M2_MASK }, // 113
|
|
{ 0x3, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG3E8_V_M1_MASK }, // 114
|
|
{ 0x3, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG3E8_V_M2_MASK }, // 115
|
|
{ 0x3, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG3E8_V_MF8_MASK }, // 116
|
|
{ 0x3, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG3E8_V_MF4_MASK }, // 117
|
|
{ 0x3, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG3E8_V_MF2_MASK }, // 118
|
|
{ 0x3, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG3E16_V_M1_MASK }, // 119
|
|
{ 0x3, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG3E16_V_M2_MASK }, // 120
|
|
{ 0x3, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG3E16_V_MF4_MASK }, // 121
|
|
{ 0x3, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG3E16_V_MF2_MASK }, // 122
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG3E32_V_M1_MASK }, // 123
|
|
{ 0x3, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG3E32_V_M2_MASK }, // 124
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{ 0x3, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG3E32_V_MF2_MASK }, // 125
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{ 0x3, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG3E64_V_M1_MASK }, // 126
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{ 0x3, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG3E64_V_M2_MASK }, // 127
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{ 0x4, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG4E8_V_M1 }, // 128
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{ 0x4, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG4E8_V_M2 }, // 129
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{ 0x4, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG4E8_V_MF8 }, // 130
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{ 0x4, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG4E8_V_MF4 }, // 131
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{ 0x4, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG4E8_V_MF2 }, // 132
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{ 0x4, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG4E16_V_M1 }, // 133
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{ 0x4, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG4E16_V_M2 }, // 134
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{ 0x4, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG4E16_V_MF4 }, // 135
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{ 0x4, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG4E16_V_MF2 }, // 136
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{ 0x4, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG4E32_V_M1 }, // 137
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{ 0x4, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG4E32_V_M2 }, // 138
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{ 0x4, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG4E32_V_MF2 }, // 139
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{ 0x4, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG4E64_V_M1 }, // 140
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{ 0x4, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG4E64_V_M2 }, // 141
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{ 0x4, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG4E8_V_M1 }, // 142
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{ 0x4, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG4E8_V_M2 }, // 143
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{ 0x4, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG4E8_V_MF8 }, // 144
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{ 0x4, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG4E8_V_MF4 }, // 145
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{ 0x4, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG4E8_V_MF2 }, // 146
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{ 0x4, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG4E16_V_M1 }, // 147
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{ 0x4, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG4E16_V_M2 }, // 148
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{ 0x4, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG4E16_V_MF4 }, // 149
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{ 0x4, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG4E16_V_MF2 }, // 150
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{ 0x4, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG4E32_V_M1 }, // 151
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{ 0x4, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG4E32_V_M2 }, // 152
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{ 0x4, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG4E32_V_MF2 }, // 153
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{ 0x4, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG4E64_V_M1 }, // 154
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{ 0x4, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG4E64_V_M2 }, // 155
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{ 0x4, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG4E8_V_M1_MASK }, // 156
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{ 0x4, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG4E8_V_M2_MASK }, // 157
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{ 0x4, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG4E8_V_MF8_MASK }, // 158
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{ 0x4, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG4E8_V_MF4_MASK }, // 159
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{ 0x4, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG4E8_V_MF2_MASK }, // 160
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{ 0x4, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG4E16_V_M1_MASK }, // 161
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{ 0x4, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG4E16_V_M2_MASK }, // 162
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{ 0x4, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG4E16_V_MF4_MASK }, // 163
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{ 0x4, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG4E16_V_MF2_MASK }, // 164
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{ 0x4, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG4E32_V_M1_MASK }, // 165
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{ 0x4, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG4E32_V_M2_MASK }, // 166
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{ 0x4, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG4E32_V_MF2_MASK }, // 167
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{ 0x4, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG4E64_V_M1_MASK }, // 168
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{ 0x4, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG4E64_V_M2_MASK }, // 169
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{ 0x4, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG4E8_V_M1_MASK }, // 170
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{ 0x4, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG4E8_V_M2_MASK }, // 171
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{ 0x4, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG4E8_V_MF8_MASK }, // 172
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{ 0x4, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG4E8_V_MF4_MASK }, // 173
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{ 0x4, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG4E8_V_MF2_MASK }, // 174
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{ 0x4, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG4E16_V_M1_MASK }, // 175
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{ 0x4, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG4E16_V_M2_MASK }, // 176
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{ 0x4, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG4E16_V_MF4_MASK }, // 177
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{ 0x4, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG4E16_V_MF2_MASK }, // 178
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{ 0x4, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG4E32_V_M1_MASK }, // 179
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{ 0x4, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG4E32_V_M2_MASK }, // 180
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{ 0x4, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG4E32_V_MF2_MASK }, // 181
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{ 0x4, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG4E64_V_M1_MASK }, // 182
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{ 0x4, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG4E64_V_M2_MASK }, // 183
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{ 0x5, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG5E8_V_M1 }, // 184
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{ 0x5, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG5E8_V_MF8 }, // 185
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{ 0x5, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG5E8_V_MF4 }, // 186
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{ 0x5, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG5E8_V_MF2 }, // 187
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{ 0x5, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG5E16_V_M1 }, // 188
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{ 0x5, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG5E16_V_MF4 }, // 189
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{ 0x5, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG5E16_V_MF2 }, // 190
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{ 0x5, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG5E32_V_M1 }, // 191
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{ 0x5, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG5E32_V_MF2 }, // 192
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{ 0x5, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG5E64_V_M1 }, // 193
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{ 0x5, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG5E8_V_M1 }, // 194
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{ 0x5, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG5E8_V_MF8 }, // 195
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{ 0x5, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG5E8_V_MF4 }, // 196
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{ 0x5, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG5E8_V_MF2 }, // 197
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{ 0x5, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG5E16_V_M1 }, // 198
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{ 0x5, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG5E16_V_MF4 }, // 199
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{ 0x5, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG5E16_V_MF2 }, // 200
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{ 0x5, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG5E32_V_M1 }, // 201
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|
{ 0x5, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG5E32_V_MF2 }, // 202
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|
{ 0x5, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG5E64_V_M1 }, // 203
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|
{ 0x5, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG5E8_V_M1_MASK }, // 204
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{ 0x5, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG5E8_V_MF8_MASK }, // 205
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{ 0x5, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG5E8_V_MF4_MASK }, // 206
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{ 0x5, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG5E8_V_MF2_MASK }, // 207
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{ 0x5, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG5E16_V_M1_MASK }, // 208
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|
{ 0x5, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG5E16_V_MF4_MASK }, // 209
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|
{ 0x5, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG5E16_V_MF2_MASK }, // 210
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|
{ 0x5, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG5E32_V_M1_MASK }, // 211
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{ 0x5, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG5E32_V_MF2_MASK }, // 212
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|
{ 0x5, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG5E64_V_M1_MASK }, // 213
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{ 0x5, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG5E8_V_M1_MASK }, // 214
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|
{ 0x5, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG5E8_V_MF8_MASK }, // 215
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{ 0x5, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG5E8_V_MF4_MASK }, // 216
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|
{ 0x5, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG5E8_V_MF2_MASK }, // 217
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|
{ 0x5, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG5E16_V_M1_MASK }, // 218
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|
{ 0x5, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG5E16_V_MF4_MASK }, // 219
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|
{ 0x5, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG5E16_V_MF2_MASK }, // 220
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|
{ 0x5, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG5E32_V_M1_MASK }, // 221
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|
{ 0x5, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG5E32_V_MF2_MASK }, // 222
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|
{ 0x5, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG5E64_V_M1_MASK }, // 223
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|
{ 0x6, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG6E8_V_M1 }, // 224
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|
{ 0x6, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG6E8_V_MF8 }, // 225
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|
{ 0x6, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG6E8_V_MF4 }, // 226
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|
{ 0x6, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG6E8_V_MF2 }, // 227
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|
{ 0x6, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG6E16_V_M1 }, // 228
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG6E16_V_MF4 }, // 229
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG6E16_V_MF2 }, // 230
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|
{ 0x6, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG6E32_V_M1 }, // 231
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG6E32_V_MF2 }, // 232
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG6E64_V_M1 }, // 233
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG6E8_V_M1 }, // 234
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|
{ 0x6, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG6E8_V_MF8 }, // 235
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG6E8_V_MF4 }, // 236
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|
{ 0x6, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG6E8_V_MF2 }, // 237
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG6E16_V_M1 }, // 238
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG6E16_V_MF4 }, // 239
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG6E16_V_MF2 }, // 240
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG6E32_V_M1 }, // 241
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG6E32_V_MF2 }, // 242
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG6E64_V_M1 }, // 243
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG6E8_V_M1_MASK }, // 244
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG6E8_V_MF8_MASK }, // 245
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG6E8_V_MF4_MASK }, // 246
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG6E8_V_MF2_MASK }, // 247
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG6E16_V_M1_MASK }, // 248
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG6E16_V_MF4_MASK }, // 249
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG6E16_V_MF2_MASK }, // 250
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG6E32_V_M1_MASK }, // 251
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG6E32_V_MF2_MASK }, // 252
|
|
{ 0x6, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG6E64_V_M1_MASK }, // 253
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG6E8_V_M1_MASK }, // 254
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG6E8_V_MF8_MASK }, // 255
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG6E8_V_MF4_MASK }, // 256
|
|
{ 0x6, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG6E8_V_MF2_MASK }, // 257
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG6E16_V_M1_MASK }, // 258
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG6E16_V_MF4_MASK }, // 259
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG6E16_V_MF2_MASK }, // 260
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|
{ 0x6, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG6E32_V_M1_MASK }, // 261
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG6E32_V_MF2_MASK }, // 262
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG6E64_V_M1_MASK }, // 263
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG7E8_V_M1 }, // 264
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG7E8_V_MF8 }, // 265
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG7E8_V_MF4 }, // 266
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG7E8_V_MF2 }, // 267
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG7E16_V_M1 }, // 268
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG7E16_V_MF4 }, // 269
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG7E16_V_MF2 }, // 270
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG7E32_V_M1 }, // 271
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG7E32_V_MF2 }, // 272
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG7E64_V_M1 }, // 273
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG7E8_V_M1 }, // 274
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG7E8_V_MF8 }, // 275
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG7E8_V_MF4 }, // 276
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG7E8_V_MF2 }, // 277
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG7E16_V_M1 }, // 278
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG7E16_V_MF4 }, // 279
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG7E16_V_MF2 }, // 280
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG7E32_V_M1 }, // 281
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG7E32_V_MF2 }, // 282
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG7E64_V_M1 }, // 283
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG7E8_V_M1_MASK }, // 284
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG7E8_V_MF8_MASK }, // 285
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG7E8_V_MF4_MASK }, // 286
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG7E8_V_MF2_MASK }, // 287
|
|
{ 0x7, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG7E16_V_M1_MASK }, // 288
|
|
{ 0x7, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG7E16_V_MF4_MASK }, // 289
|
|
{ 0x7, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG7E16_V_MF2_MASK }, // 290
|
|
{ 0x7, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG7E32_V_M1_MASK }, // 291
|
|
{ 0x7, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG7E32_V_MF2_MASK }, // 292
|
|
{ 0x7, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG7E64_V_M1_MASK }, // 293
|
|
{ 0x7, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG7E8_V_M1_MASK }, // 294
|
|
{ 0x7, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG7E8_V_MF8_MASK }, // 295
|
|
{ 0x7, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG7E8_V_MF4_MASK }, // 296
|
|
{ 0x7, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG7E8_V_MF2_MASK }, // 297
|
|
{ 0x7, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG7E16_V_M1_MASK }, // 298
|
|
{ 0x7, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG7E16_V_MF4_MASK }, // 299
|
|
{ 0x7, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG7E16_V_MF2_MASK }, // 300
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|
{ 0x7, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG7E32_V_M1_MASK }, // 301
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|
{ 0x7, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG7E32_V_MF2_MASK }, // 302
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|
{ 0x7, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG7E64_V_M1_MASK }, // 303
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|
{ 0x8, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG8E8_V_M1 }, // 304
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|
{ 0x8, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG8E8_V_MF8 }, // 305
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|
{ 0x8, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG8E8_V_MF4 }, // 306
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|
{ 0x8, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG8E8_V_MF2 }, // 307
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|
{ 0x8, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG8E16_V_M1 }, // 308
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|
{ 0x8, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG8E16_V_MF4 }, // 309
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|
{ 0x8, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG8E16_V_MF2 }, // 310
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|
{ 0x8, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG8E32_V_M1 }, // 311
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|
{ 0x8, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG8E32_V_MF2 }, // 312
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|
{ 0x8, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG8E64_V_M1 }, // 313
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|
{ 0x8, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG8E8_V_M1 }, // 314
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|
{ 0x8, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG8E8_V_MF8 }, // 315
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|
{ 0x8, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG8E8_V_MF4 }, // 316
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|
{ 0x8, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG8E8_V_MF2 }, // 317
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|
{ 0x8, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG8E16_V_M1 }, // 318
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|
{ 0x8, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG8E16_V_MF4 }, // 319
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|
{ 0x8, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG8E16_V_MF2 }, // 320
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|
{ 0x8, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG8E32_V_M1 }, // 321
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|
{ 0x8, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG8E32_V_MF2 }, // 322
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|
{ 0x8, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG8E64_V_M1 }, // 323
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|
{ 0x8, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG8E8_V_M1_MASK }, // 324
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|
{ 0x8, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG8E8_V_MF8_MASK }, // 325
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|
{ 0x8, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG8E8_V_MF4_MASK }, // 326
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|
{ 0x8, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG8E8_V_MF2_MASK }, // 327
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|
{ 0x8, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG8E16_V_M1_MASK }, // 328
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|
{ 0x8, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG8E16_V_MF4_MASK }, // 329
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|
{ 0x8, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG8E16_V_MF2_MASK }, // 330
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|
{ 0x8, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG8E32_V_M1_MASK }, // 331
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|
{ 0x8, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG8E32_V_MF2_MASK }, // 332
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|
{ 0x8, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG8E64_V_M1_MASK }, // 333
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|
{ 0x8, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG8E8_V_M1_MASK }, // 334
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|
{ 0x8, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG8E8_V_MF8_MASK }, // 335
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|
{ 0x8, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG8E8_V_MF4_MASK }, // 336
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|
{ 0x8, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG8E8_V_MF2_MASK }, // 337
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|
{ 0x8, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG8E16_V_M1_MASK }, // 338
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG8E16_V_MF4_MASK }, // 339
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG8E16_V_MF2_MASK }, // 340
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|
{ 0x8, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG8E32_V_M1_MASK }, // 341
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG8E32_V_MF2_MASK }, // 342
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|
{ 0x8, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG8E64_V_M1_MASK }, // 343
|
|
};
|
|
|
|
const RISCV_VSSEGPseudo *RISCV_getVSSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedStridedLog2SEWLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVSSEGTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVSXSEGTable_IMPL
|
|
static const RISCV_VSXSEGPseudo RISCVVSXSEGTable[] = {
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG2EI8_V_M1_M1 }, // 0
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG2EI8_V_MF8_M1 }, // 1
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG2EI8_V_MF4_M1 }, // 2
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG2EI8_V_MF2_M1 }, // 3
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG2EI8_V_M1_M2 }, // 4
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG2EI8_V_M2_M2 }, // 5
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG2EI8_V_MF4_M2 }, // 6
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG2EI8_V_MF2_M2 }, // 7
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVSUXSEG2EI8_V_M1_M4 }, // 8
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVSUXSEG2EI8_V_M2_M4 }, // 9
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVSUXSEG2EI8_V_M4_M4 }, // 10
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVSUXSEG2EI8_V_MF2_M4 }, // 11
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF8 }, // 12
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF4 }, // 13
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF4 }, // 14
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF2 }, // 15
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF2 }, // 16
|
|
{ 0x2, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG2EI8_V_MF2_MF2 }, // 17
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG2EI16_V_M1_M1 }, // 18
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG2EI16_V_M2_M1 }, // 19
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG2EI16_V_MF4_M1 }, // 20
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG2EI16_V_MF2_M1 }, // 21
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG2EI16_V_M1_M2 }, // 22
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG2EI16_V_M2_M2 }, // 23
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG2EI16_V_M4_M2 }, // 24
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG2EI16_V_MF2_M2 }, // 25
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVSUXSEG2EI16_V_M1_M4 }, // 26
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVSUXSEG2EI16_V_M2_M4 }, // 27
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVSUXSEG2EI16_V_M4_M4 }, // 28
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVSUXSEG2EI16_V_M8_M4 }, // 29
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF8 }, // 30
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF4 }, // 31
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF4 }, // 32
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG2EI16_V_M1_MF2 }, // 33
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF2 }, // 34
|
|
{ 0x2, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF2 }, // 35
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG2EI32_V_M1_M1 }, // 36
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG2EI32_V_M2_M1 }, // 37
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG2EI32_V_M4_M1 }, // 38
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG2EI32_V_MF2_M1 }, // 39
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG2EI32_V_M1_M2 }, // 40
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG2EI32_V_M2_M2 }, // 41
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG2EI32_V_M4_M2 }, // 42
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG2EI32_V_M8_M2 }, // 43
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVSUXSEG2EI32_V_M2_M4 }, // 44
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVSUXSEG2EI32_V_M4_M4 }, // 45
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVSUXSEG2EI32_V_M8_M4 }, // 46
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF8 }, // 47
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG2EI32_V_M1_MF4 }, // 48
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF4 }, // 49
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG2EI32_V_M1_MF2 }, // 50
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG2EI32_V_M2_MF2 }, // 51
|
|
{ 0x2, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF2 }, // 52
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG2EI64_V_M1_M1 }, // 53
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG2EI64_V_M2_M1 }, // 54
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG2EI64_V_M4_M1 }, // 55
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG2EI64_V_M8_M1 }, // 56
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG2EI64_V_M2_M2 }, // 57
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG2EI64_V_M4_M2 }, // 58
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG2EI64_V_M8_M2 }, // 59
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVSUXSEG2EI64_V_M4_M4 }, // 60
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVSUXSEG2EI64_V_M8_M4 }, // 61
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG2EI64_V_M1_MF8 }, // 62
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG2EI64_V_M1_MF4 }, // 63
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG2EI64_V_M2_MF4 }, // 64
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG2EI64_V_M1_MF2 }, // 65
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG2EI64_V_M2_MF2 }, // 66
|
|
{ 0x2, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG2EI64_V_M4_MF2 }, // 67
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG2EI8_V_M1_M1 }, // 68
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG2EI8_V_MF8_M1 }, // 69
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG2EI8_V_MF4_M1 }, // 70
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG2EI8_V_MF2_M1 }, // 71
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG2EI8_V_M1_M2 }, // 72
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG2EI8_V_M2_M2 }, // 73
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG2EI8_V_MF4_M2 }, // 74
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG2EI8_V_MF2_M2 }, // 75
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVSOXSEG2EI8_V_M1_M4 }, // 76
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVSOXSEG2EI8_V_M2_M4 }, // 77
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVSOXSEG2EI8_V_M4_M4 }, // 78
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVSOXSEG2EI8_V_MF2_M4 }, // 79
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF8 }, // 80
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF4 }, // 81
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF4 }, // 82
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF2 }, // 83
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF2 }, // 84
|
|
{ 0x2, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG2EI8_V_MF2_MF2 }, // 85
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG2EI16_V_M1_M1 }, // 86
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG2EI16_V_M2_M1 }, // 87
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG2EI16_V_MF4_M1 }, // 88
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG2EI16_V_MF2_M1 }, // 89
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG2EI16_V_M1_M2 }, // 90
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG2EI16_V_M2_M2 }, // 91
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG2EI16_V_M4_M2 }, // 92
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG2EI16_V_MF2_M2 }, // 93
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVSOXSEG2EI16_V_M1_M4 }, // 94
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVSOXSEG2EI16_V_M2_M4 }, // 95
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVSOXSEG2EI16_V_M4_M4 }, // 96
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVSOXSEG2EI16_V_M8_M4 }, // 97
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF8 }, // 98
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF4 }, // 99
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF4 }, // 100
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG2EI16_V_M1_MF2 }, // 101
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF2 }, // 102
|
|
{ 0x2, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF2 }, // 103
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG2EI32_V_M1_M1 }, // 104
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG2EI32_V_M2_M1 }, // 105
|
|
{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG2EI32_V_M4_M1 }, // 106
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{ 0x2, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG2EI32_V_MF2_M1 }, // 107
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG2EI32_V_M1_M2 }, // 108
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG2EI32_V_M2_M2 }, // 109
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG2EI32_V_M4_M2 }, // 110
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{ 0x2, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG2EI32_V_M8_M2 }, // 111
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{ 0x2, 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVSOXSEG2EI32_V_M2_M4 }, // 112
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{ 0x2, 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVSOXSEG2EI32_V_M4_M4 }, // 113
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{ 0x2, 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVSOXSEG2EI32_V_M8_M4 }, // 114
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{ 0x2, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF8 }, // 115
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{ 0x2, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG2EI32_V_M1_MF4 }, // 116
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{ 0x2, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF4 }, // 117
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{ 0x2, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG2EI32_V_M1_MF2 }, // 118
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{ 0x2, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG2EI32_V_M2_MF2 }, // 119
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{ 0x2, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF2 }, // 120
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG2EI64_V_M1_M1 }, // 121
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG2EI64_V_M2_M1 }, // 122
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG2EI64_V_M4_M1 }, // 123
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{ 0x2, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG2EI64_V_M8_M1 }, // 124
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{ 0x2, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG2EI64_V_M2_M2 }, // 125
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{ 0x2, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG2EI64_V_M4_M2 }, // 126
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{ 0x2, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG2EI64_V_M8_M2 }, // 127
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{ 0x2, 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVSOXSEG2EI64_V_M4_M4 }, // 128
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{ 0x2, 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVSOXSEG2EI64_V_M8_M4 }, // 129
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{ 0x2, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG2EI64_V_M1_MF8 }, // 130
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{ 0x2, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG2EI64_V_M1_MF4 }, // 131
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{ 0x2, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG2EI64_V_M2_MF4 }, // 132
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{ 0x2, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG2EI64_V_M1_MF2 }, // 133
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{ 0x2, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG2EI64_V_M2_MF2 }, // 134
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{ 0x2, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG2EI64_V_M4_MF2 }, // 135
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG2EI8_V_M1_M1_MASK }, // 136
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG2EI8_V_MF8_M1_MASK }, // 137
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG2EI8_V_MF4_M1_MASK }, // 138
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{ 0x2, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG2EI8_V_MF2_M1_MASK }, // 139
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG2EI8_V_M1_M2_MASK }, // 140
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG2EI8_V_M2_M2_MASK }, // 141
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG2EI8_V_MF4_M2_MASK }, // 142
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{ 0x2, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG2EI8_V_MF2_M2_MASK }, // 143
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVSUXSEG2EI8_V_M1_M4_MASK }, // 144
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVSUXSEG2EI8_V_M2_M4_MASK }, // 145
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVSUXSEG2EI8_V_M4_M4_MASK }, // 146
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{ 0x2, 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVSUXSEG2EI8_V_MF2_M4_MASK }, // 147
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{ 0x2, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF8_MASK }, // 148
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{ 0x2, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF4_MASK }, // 149
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{ 0x2, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF4_MASK }, // 150
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{ 0x2, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF2_MASK }, // 151
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{ 0x2, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF2_MASK }, // 152
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{ 0x2, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG2EI8_V_MF2_MF2_MASK }, // 153
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG2EI16_V_M1_M1_MASK }, // 154
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG2EI16_V_M2_M1_MASK }, // 155
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG2EI16_V_MF4_M1_MASK }, // 156
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{ 0x2, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG2EI16_V_MF2_M1_MASK }, // 157
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG2EI16_V_M1_M2_MASK }, // 158
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG2EI16_V_M2_M2_MASK }, // 159
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG2EI16_V_M4_M2_MASK }, // 160
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{ 0x2, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG2EI16_V_MF2_M2_MASK }, // 161
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVSUXSEG2EI16_V_M1_M4_MASK }, // 162
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVSUXSEG2EI16_V_M2_M4_MASK }, // 163
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVSUXSEG2EI16_V_M4_M4_MASK }, // 164
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{ 0x2, 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVSUXSEG2EI16_V_M8_M4_MASK }, // 165
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{ 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF8_MASK }, // 166
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{ 0x2, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF4_MASK }, // 167
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{ 0x2, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF4_MASK }, // 168
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{ 0x2, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG2EI16_V_M1_MF2_MASK }, // 169
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{ 0x2, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF2_MASK }, // 170
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{ 0x2, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF2_MASK }, // 171
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG2EI32_V_M1_M1_MASK }, // 172
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG2EI32_V_M2_M1_MASK }, // 173
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG2EI32_V_M4_M1_MASK }, // 174
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{ 0x2, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG2EI32_V_MF2_M1_MASK }, // 175
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG2EI32_V_M1_M2_MASK }, // 176
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG2EI32_V_M2_M2_MASK }, // 177
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG2EI32_V_M4_M2_MASK }, // 178
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{ 0x2, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG2EI32_V_M8_M2_MASK }, // 179
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{ 0x2, 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVSUXSEG2EI32_V_M2_M4_MASK }, // 180
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{ 0x2, 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVSUXSEG2EI32_V_M4_M4_MASK }, // 181
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{ 0x2, 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVSUXSEG2EI32_V_M8_M4_MASK }, // 182
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{ 0x2, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF8_MASK }, // 183
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{ 0x2, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG2EI32_V_M1_MF4_MASK }, // 184
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{ 0x2, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF4_MASK }, // 185
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{ 0x2, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG2EI32_V_M1_MF2_MASK }, // 186
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{ 0x2, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG2EI32_V_M2_MF2_MASK }, // 187
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{ 0x2, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF2_MASK }, // 188
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{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG2EI64_V_M1_M1_MASK }, // 189
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{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG2EI64_V_M2_M1_MASK }, // 190
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{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG2EI64_V_M4_M1_MASK }, // 191
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{ 0x2, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG2EI64_V_M8_M1_MASK }, // 192
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{ 0x2, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG2EI64_V_M2_M2_MASK }, // 193
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{ 0x2, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG2EI64_V_M4_M2_MASK }, // 194
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{ 0x2, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG2EI64_V_M8_M2_MASK }, // 195
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{ 0x2, 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVSUXSEG2EI64_V_M4_M4_MASK }, // 196
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{ 0x2, 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVSUXSEG2EI64_V_M8_M4_MASK }, // 197
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{ 0x2, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG2EI64_V_M1_MF8_MASK }, // 198
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{ 0x2, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG2EI64_V_M1_MF4_MASK }, // 199
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{ 0x2, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG2EI64_V_M2_MF4_MASK }, // 200
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{ 0x2, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG2EI64_V_M1_MF2_MASK }, // 201
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{ 0x2, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG2EI64_V_M2_MF2_MASK }, // 202
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{ 0x2, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG2EI64_V_M4_MF2_MASK }, // 203
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{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG2EI8_V_M1_M1_MASK }, // 204
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{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG2EI8_V_MF8_M1_MASK }, // 205
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{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG2EI8_V_MF4_M1_MASK }, // 206
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{ 0x2, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG2EI8_V_MF2_M1_MASK }, // 207
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{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG2EI8_V_M1_M2_MASK }, // 208
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{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG2EI8_V_M2_M2_MASK }, // 209
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{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG2EI8_V_MF4_M2_MASK }, // 210
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{ 0x2, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG2EI8_V_MF2_M2_MASK }, // 211
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{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVSOXSEG2EI8_V_M1_M4_MASK }, // 212
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{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVSOXSEG2EI8_V_M2_M4_MASK }, // 213
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{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVSOXSEG2EI8_V_M4_M4_MASK }, // 214
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{ 0x2, 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVSOXSEG2EI8_V_MF2_M4_MASK }, // 215
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{ 0x2, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF8_MASK }, // 216
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{ 0x2, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF4_MASK }, // 217
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{ 0x2, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF4_MASK }, // 218
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{ 0x2, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF2_MASK }, // 219
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{ 0x2, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF2_MASK }, // 220
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{ 0x2, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG2EI8_V_MF2_MF2_MASK }, // 221
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG2EI16_V_M1_M1_MASK }, // 222
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG2EI16_V_M2_M1_MASK }, // 223
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG2EI16_V_MF4_M1_MASK }, // 224
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{ 0x2, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG2EI16_V_MF2_M1_MASK }, // 225
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG2EI16_V_M1_M2_MASK }, // 226
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG2EI16_V_M2_M2_MASK }, // 227
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG2EI16_V_M4_M2_MASK }, // 228
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{ 0x2, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG2EI16_V_MF2_M2_MASK }, // 229
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVSOXSEG2EI16_V_M1_M4_MASK }, // 230
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVSOXSEG2EI16_V_M2_M4_MASK }, // 231
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|
{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVSOXSEG2EI16_V_M4_M4_MASK }, // 232
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{ 0x2, 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVSOXSEG2EI16_V_M8_M4_MASK }, // 233
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{ 0x2, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF8_MASK }, // 234
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{ 0x2, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF4_MASK }, // 235
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{ 0x2, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF4_MASK }, // 236
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|
{ 0x2, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG2EI16_V_M1_MF2_MASK }, // 237
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{ 0x2, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF2_MASK }, // 238
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|
{ 0x2, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF2_MASK }, // 239
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|
{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG2EI32_V_M1_M1_MASK }, // 240
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|
{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG2EI32_V_M2_M1_MASK }, // 241
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|
{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG2EI32_V_M4_M1_MASK }, // 242
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|
{ 0x2, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG2EI32_V_MF2_M1_MASK }, // 243
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|
{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG2EI32_V_M1_M2_MASK }, // 244
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{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG2EI32_V_M2_M2_MASK }, // 245
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{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG2EI32_V_M4_M2_MASK }, // 246
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|
{ 0x2, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG2EI32_V_M8_M2_MASK }, // 247
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{ 0x2, 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVSOXSEG2EI32_V_M2_M4_MASK }, // 248
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{ 0x2, 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVSOXSEG2EI32_V_M4_M4_MASK }, // 249
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{ 0x2, 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVSOXSEG2EI32_V_M8_M4_MASK }, // 250
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{ 0x2, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF8_MASK }, // 251
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{ 0x2, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG2EI32_V_M1_MF4_MASK }, // 252
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{ 0x2, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF4_MASK }, // 253
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{ 0x2, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG2EI32_V_M1_MF2_MASK }, // 254
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{ 0x2, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG2EI32_V_M2_MF2_MASK }, // 255
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{ 0x2, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF2_MASK }, // 256
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG2EI64_V_M1_M1_MASK }, // 257
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG2EI64_V_M2_M1_MASK }, // 258
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG2EI64_V_M4_M1_MASK }, // 259
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{ 0x2, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG2EI64_V_M8_M1_MASK }, // 260
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{ 0x2, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG2EI64_V_M2_M2_MASK }, // 261
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{ 0x2, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG2EI64_V_M4_M2_MASK }, // 262
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{ 0x2, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG2EI64_V_M8_M2_MASK }, // 263
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{ 0x2, 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVSOXSEG2EI64_V_M4_M4_MASK }, // 264
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{ 0x2, 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVSOXSEG2EI64_V_M8_M4_MASK }, // 265
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{ 0x2, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG2EI64_V_M1_MF8_MASK }, // 266
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{ 0x2, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG2EI64_V_M1_MF4_MASK }, // 267
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{ 0x2, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG2EI64_V_M2_MF4_MASK }, // 268
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{ 0x2, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG2EI64_V_M1_MF2_MASK }, // 269
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{ 0x2, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG2EI64_V_M2_MF2_MASK }, // 270
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{ 0x2, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG2EI64_V_M4_MF2_MASK }, // 271
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG3EI8_V_M1_M1 }, // 272
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG3EI8_V_MF8_M1 }, // 273
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG3EI8_V_MF4_M1 }, // 274
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{ 0x3, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG3EI8_V_MF2_M1 }, // 275
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG3EI8_V_M1_M2 }, // 276
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG3EI8_V_M2_M2 }, // 277
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG3EI8_V_MF4_M2 }, // 278
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{ 0x3, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG3EI8_V_MF2_M2 }, // 279
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{ 0x3, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF8 }, // 280
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{ 0x3, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF4 }, // 281
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{ 0x3, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF4 }, // 282
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{ 0x3, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF2 }, // 283
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{ 0x3, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF2 }, // 284
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{ 0x3, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG3EI8_V_MF2_MF2 }, // 285
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG3EI16_V_M1_M1 }, // 286
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG3EI16_V_M2_M1 }, // 287
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG3EI16_V_MF4_M1 }, // 288
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{ 0x3, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG3EI16_V_MF2_M1 }, // 289
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG3EI16_V_M1_M2 }, // 290
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG3EI16_V_M2_M2 }, // 291
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG3EI16_V_M4_M2 }, // 292
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{ 0x3, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG3EI16_V_MF2_M2 }, // 293
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{ 0x3, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF8 }, // 294
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{ 0x3, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF4 }, // 295
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{ 0x3, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF4 }, // 296
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|
{ 0x3, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG3EI16_V_M1_MF2 }, // 297
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{ 0x3, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF2 }, // 298
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{ 0x3, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF2 }, // 299
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|
{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG3EI32_V_M1_M1 }, // 300
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|
{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG3EI32_V_M2_M1 }, // 301
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|
{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG3EI32_V_M4_M1 }, // 302
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|
{ 0x3, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG3EI32_V_MF2_M1 }, // 303
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|
{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG3EI32_V_M1_M2 }, // 304
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|
{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG3EI32_V_M2_M2 }, // 305
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|
{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG3EI32_V_M4_M2 }, // 306
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|
{ 0x3, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG3EI32_V_M8_M2 }, // 307
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|
{ 0x3, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF8 }, // 308
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|
{ 0x3, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG3EI32_V_M1_MF4 }, // 309
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|
{ 0x3, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF4 }, // 310
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|
{ 0x3, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG3EI32_V_M1_MF2 }, // 311
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|
{ 0x3, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG3EI32_V_M2_MF2 }, // 312
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|
{ 0x3, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF2 }, // 313
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|
{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG3EI64_V_M1_M1 }, // 314
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|
{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG3EI64_V_M2_M1 }, // 315
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|
{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG3EI64_V_M4_M1 }, // 316
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|
{ 0x3, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG3EI64_V_M8_M1 }, // 317
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{ 0x3, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG3EI64_V_M2_M2 }, // 318
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|
{ 0x3, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG3EI64_V_M4_M2 }, // 319
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|
{ 0x3, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG3EI64_V_M8_M2 }, // 320
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|
{ 0x3, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG3EI64_V_M1_MF8 }, // 321
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|
{ 0x3, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG3EI64_V_M1_MF4 }, // 322
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{ 0x3, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG3EI64_V_M2_MF4 }, // 323
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|
{ 0x3, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG3EI64_V_M1_MF2 }, // 324
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|
{ 0x3, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG3EI64_V_M2_MF2 }, // 325
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|
{ 0x3, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG3EI64_V_M4_MF2 }, // 326
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG3EI8_V_M1_M1 }, // 327
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG3EI8_V_MF8_M1 }, // 328
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG3EI8_V_MF4_M1 }, // 329
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|
{ 0x3, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG3EI8_V_MF2_M1 }, // 330
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG3EI8_V_M1_M2 }, // 331
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG3EI8_V_M2_M2 }, // 332
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG3EI8_V_MF4_M2 }, // 333
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|
{ 0x3, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG3EI8_V_MF2_M2 }, // 334
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|
{ 0x3, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF8 }, // 335
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|
{ 0x3, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF4 }, // 336
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|
{ 0x3, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF4 }, // 337
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|
{ 0x3, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF2 }, // 338
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|
{ 0x3, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF2 }, // 339
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|
{ 0x3, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG3EI8_V_MF2_MF2 }, // 340
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|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG3EI16_V_M1_M1 }, // 341
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|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG3EI16_V_M2_M1 }, // 342
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|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG3EI16_V_MF4_M1 }, // 343
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|
{ 0x3, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG3EI16_V_MF2_M1 }, // 344
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG3EI16_V_M1_M2 }, // 345
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|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG3EI16_V_M2_M2 }, // 346
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|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG3EI16_V_M4_M2 }, // 347
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG3EI16_V_MF2_M2 }, // 348
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF8 }, // 349
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF4 }, // 350
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|
{ 0x3, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF4 }, // 351
|
|
{ 0x3, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG3EI16_V_M1_MF2 }, // 352
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|
{ 0x3, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF2 }, // 353
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|
{ 0x3, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF2 }, // 354
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|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG3EI32_V_M1_M1 }, // 355
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG3EI32_V_M2_M1 }, // 356
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG3EI32_V_M4_M1 }, // 357
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG3EI32_V_MF2_M1 }, // 358
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG3EI32_V_M1_M2 }, // 359
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG3EI32_V_M2_M2 }, // 360
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|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG3EI32_V_M4_M2 }, // 361
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|
{ 0x3, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG3EI32_V_M8_M2 }, // 362
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|
{ 0x3, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF8 }, // 363
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG3EI32_V_M1_MF4 }, // 364
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|
{ 0x3, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF4 }, // 365
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG3EI32_V_M1_MF2 }, // 366
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG3EI32_V_M2_MF2 }, // 367
|
|
{ 0x3, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF2 }, // 368
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG3EI64_V_M1_M1 }, // 369
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG3EI64_V_M2_M1 }, // 370
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG3EI64_V_M4_M1 }, // 371
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG3EI64_V_M8_M1 }, // 372
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG3EI64_V_M2_M2 }, // 373
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG3EI64_V_M4_M2 }, // 374
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG3EI64_V_M8_M2 }, // 375
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG3EI64_V_M1_MF8 }, // 376
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG3EI64_V_M1_MF4 }, // 377
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG3EI64_V_M2_MF4 }, // 378
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG3EI64_V_M1_MF2 }, // 379
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG3EI64_V_M2_MF2 }, // 380
|
|
{ 0x3, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG3EI64_V_M4_MF2 }, // 381
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG3EI8_V_M1_M1_MASK }, // 382
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG3EI8_V_MF8_M1_MASK }, // 383
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG3EI8_V_MF4_M1_MASK }, // 384
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG3EI8_V_MF2_M1_MASK }, // 385
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG3EI8_V_M1_M2_MASK }, // 386
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG3EI8_V_M2_M2_MASK }, // 387
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG3EI8_V_MF4_M2_MASK }, // 388
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG3EI8_V_MF2_M2_MASK }, // 389
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF8_MASK }, // 390
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF4_MASK }, // 391
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF4_MASK }, // 392
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF2_MASK }, // 393
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF2_MASK }, // 394
|
|
{ 0x3, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG3EI8_V_MF2_MF2_MASK }, // 395
|
|
{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG3EI16_V_M1_M1_MASK }, // 396
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|
{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG3EI16_V_M2_M1_MASK }, // 397
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{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG3EI16_V_MF4_M1_MASK }, // 398
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{ 0x3, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG3EI16_V_MF2_M1_MASK }, // 399
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG3EI16_V_M1_M2_MASK }, // 400
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG3EI16_V_M2_M2_MASK }, // 401
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG3EI16_V_M4_M2_MASK }, // 402
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{ 0x3, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG3EI16_V_MF2_M2_MASK }, // 403
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{ 0x3, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF8_MASK }, // 404
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{ 0x3, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF4_MASK }, // 405
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{ 0x3, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF4_MASK }, // 406
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{ 0x3, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG3EI16_V_M1_MF2_MASK }, // 407
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{ 0x3, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF2_MASK }, // 408
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{ 0x3, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF2_MASK }, // 409
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{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG3EI32_V_M1_M1_MASK }, // 410
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{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG3EI32_V_M2_M1_MASK }, // 411
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{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG3EI32_V_M4_M1_MASK }, // 412
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{ 0x3, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG3EI32_V_MF2_M1_MASK }, // 413
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{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG3EI32_V_M1_M2_MASK }, // 414
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{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG3EI32_V_M2_M2_MASK }, // 415
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{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG3EI32_V_M4_M2_MASK }, // 416
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{ 0x3, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG3EI32_V_M8_M2_MASK }, // 417
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{ 0x3, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF8_MASK }, // 418
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{ 0x3, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG3EI32_V_M1_MF4_MASK }, // 419
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{ 0x3, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF4_MASK }, // 420
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{ 0x3, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG3EI32_V_M1_MF2_MASK }, // 421
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{ 0x3, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG3EI32_V_M2_MF2_MASK }, // 422
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{ 0x3, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF2_MASK }, // 423
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{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG3EI64_V_M1_M1_MASK }, // 424
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{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG3EI64_V_M2_M1_MASK }, // 425
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{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG3EI64_V_M4_M1_MASK }, // 426
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{ 0x3, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG3EI64_V_M8_M1_MASK }, // 427
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{ 0x3, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG3EI64_V_M2_M2_MASK }, // 428
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{ 0x3, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG3EI64_V_M4_M2_MASK }, // 429
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{ 0x3, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG3EI64_V_M8_M2_MASK }, // 430
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{ 0x3, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG3EI64_V_M1_MF8_MASK }, // 431
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{ 0x3, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG3EI64_V_M1_MF4_MASK }, // 432
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{ 0x3, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG3EI64_V_M2_MF4_MASK }, // 433
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{ 0x3, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG3EI64_V_M1_MF2_MASK }, // 434
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{ 0x3, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG3EI64_V_M2_MF2_MASK }, // 435
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{ 0x3, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG3EI64_V_M4_MF2_MASK }, // 436
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{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG3EI8_V_M1_M1_MASK }, // 437
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{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG3EI8_V_MF8_M1_MASK }, // 438
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{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG3EI8_V_MF4_M1_MASK }, // 439
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{ 0x3, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG3EI8_V_MF2_M1_MASK }, // 440
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{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG3EI8_V_M1_M2_MASK }, // 441
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{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG3EI8_V_M2_M2_MASK }, // 442
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{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG3EI8_V_MF4_M2_MASK }, // 443
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{ 0x3, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG3EI8_V_MF2_M2_MASK }, // 444
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{ 0x3, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF8_MASK }, // 445
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{ 0x3, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF4_MASK }, // 446
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{ 0x3, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF4_MASK }, // 447
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{ 0x3, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF2_MASK }, // 448
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|
{ 0x3, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF2_MASK }, // 449
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{ 0x3, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG3EI8_V_MF2_MF2_MASK }, // 450
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|
{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG3EI16_V_M1_M1_MASK }, // 451
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{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG3EI16_V_M2_M1_MASK }, // 452
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{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG3EI16_V_MF4_M1_MASK }, // 453
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|
{ 0x3, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG3EI16_V_MF2_M1_MASK }, // 454
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{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG3EI16_V_M1_M2_MASK }, // 455
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{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG3EI16_V_M2_M2_MASK }, // 456
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{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG3EI16_V_M4_M2_MASK }, // 457
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{ 0x3, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG3EI16_V_MF2_M2_MASK }, // 458
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{ 0x3, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF8_MASK }, // 459
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{ 0x3, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF4_MASK }, // 460
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{ 0x3, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF4_MASK }, // 461
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{ 0x3, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG3EI16_V_M1_MF2_MASK }, // 462
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{ 0x3, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF2_MASK }, // 463
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{ 0x3, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF2_MASK }, // 464
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{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG3EI32_V_M1_M1_MASK }, // 465
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{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG3EI32_V_M2_M1_MASK }, // 466
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{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG3EI32_V_M4_M1_MASK }, // 467
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{ 0x3, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG3EI32_V_MF2_M1_MASK }, // 468
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{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG3EI32_V_M1_M2_MASK }, // 469
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|
{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG3EI32_V_M2_M2_MASK }, // 470
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{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG3EI32_V_M4_M2_MASK }, // 471
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{ 0x3, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG3EI32_V_M8_M2_MASK }, // 472
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|
{ 0x3, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF8_MASK }, // 473
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|
{ 0x3, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG3EI32_V_M1_MF4_MASK }, // 474
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{ 0x3, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF4_MASK }, // 475
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{ 0x3, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG3EI32_V_M1_MF2_MASK }, // 476
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{ 0x3, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG3EI32_V_M2_MF2_MASK }, // 477
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{ 0x3, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF2_MASK }, // 478
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{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG3EI64_V_M1_M1_MASK }, // 479
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{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG3EI64_V_M2_M1_MASK }, // 480
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{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG3EI64_V_M4_M1_MASK }, // 481
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|
{ 0x3, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG3EI64_V_M8_M1_MASK }, // 482
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|
{ 0x3, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG3EI64_V_M2_M2_MASK }, // 483
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|
{ 0x3, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG3EI64_V_M4_M2_MASK }, // 484
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|
{ 0x3, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG3EI64_V_M8_M2_MASK }, // 485
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|
{ 0x3, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG3EI64_V_M1_MF8_MASK }, // 486
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|
{ 0x3, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG3EI64_V_M1_MF4_MASK }, // 487
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|
{ 0x3, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG3EI64_V_M2_MF4_MASK }, // 488
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|
{ 0x3, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG3EI64_V_M1_MF2_MASK }, // 489
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|
{ 0x3, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG3EI64_V_M2_MF2_MASK }, // 490
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|
{ 0x3, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG3EI64_V_M4_MF2_MASK }, // 491
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|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG4EI8_V_M1_M1 }, // 492
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|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG4EI8_V_MF8_M1 }, // 493
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|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG4EI8_V_MF4_M1 }, // 494
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|
{ 0x4, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG4EI8_V_MF2_M1 }, // 495
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|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG4EI8_V_M1_M2 }, // 496
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|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG4EI8_V_M2_M2 }, // 497
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|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG4EI8_V_MF4_M2 }, // 498
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|
{ 0x4, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG4EI8_V_MF2_M2 }, // 499
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|
{ 0x4, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF8 }, // 500
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|
{ 0x4, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF4 }, // 501
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|
{ 0x4, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF4 }, // 502
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|
{ 0x4, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF2 }, // 503
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|
{ 0x4, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF2 }, // 504
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|
{ 0x4, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG4EI8_V_MF2_MF2 }, // 505
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|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG4EI16_V_M1_M1 }, // 506
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|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG4EI16_V_M2_M1 }, // 507
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|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG4EI16_V_MF4_M1 }, // 508
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|
{ 0x4, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG4EI16_V_MF2_M1 }, // 509
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|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG4EI16_V_M1_M2 }, // 510
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|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG4EI16_V_M2_M2 }, // 511
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|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG4EI16_V_M4_M2 }, // 512
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|
{ 0x4, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG4EI16_V_MF2_M2 }, // 513
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|
{ 0x4, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF8 }, // 514
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|
{ 0x4, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF4 }, // 515
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|
{ 0x4, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF4 }, // 516
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|
{ 0x4, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG4EI16_V_M1_MF2 }, // 517
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|
{ 0x4, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF2 }, // 518
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|
{ 0x4, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF2 }, // 519
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|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG4EI32_V_M1_M1 }, // 520
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|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG4EI32_V_M2_M1 }, // 521
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|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG4EI32_V_M4_M1 }, // 522
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|
{ 0x4, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG4EI32_V_MF2_M1 }, // 523
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|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG4EI32_V_M1_M2 }, // 524
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|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG4EI32_V_M2_M2 }, // 525
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|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG4EI32_V_M4_M2 }, // 526
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|
{ 0x4, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG4EI32_V_M8_M2 }, // 527
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|
{ 0x4, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF8 }, // 528
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG4EI32_V_M1_MF4 }, // 529
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|
{ 0x4, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF4 }, // 530
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG4EI32_V_M1_MF2 }, // 531
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG4EI32_V_M2_MF2 }, // 532
|
|
{ 0x4, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF2 }, // 533
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|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG4EI64_V_M1_M1 }, // 534
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|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG4EI64_V_M2_M1 }, // 535
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG4EI64_V_M4_M1 }, // 536
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG4EI64_V_M8_M1 }, // 537
|
|
{ 0x4, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG4EI64_V_M2_M2 }, // 538
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|
{ 0x4, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG4EI64_V_M4_M2 }, // 539
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|
{ 0x4, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG4EI64_V_M8_M2 }, // 540
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|
{ 0x4, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG4EI64_V_M1_MF8 }, // 541
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|
{ 0x4, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG4EI64_V_M1_MF4 }, // 542
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|
{ 0x4, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG4EI64_V_M2_MF4 }, // 543
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|
{ 0x4, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG4EI64_V_M1_MF2 }, // 544
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|
{ 0x4, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG4EI64_V_M2_MF2 }, // 545
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|
{ 0x4, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG4EI64_V_M4_MF2 }, // 546
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|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG4EI8_V_M1_M1 }, // 547
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|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG4EI8_V_MF8_M1 }, // 548
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|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG4EI8_V_MF4_M1 }, // 549
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|
{ 0x4, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG4EI8_V_MF2_M1 }, // 550
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|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG4EI8_V_M1_M2 }, // 551
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|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG4EI8_V_M2_M2 }, // 552
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|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG4EI8_V_MF4_M2 }, // 553
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|
{ 0x4, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG4EI8_V_MF2_M2 }, // 554
|
|
{ 0x4, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF8 }, // 555
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|
{ 0x4, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF4 }, // 556
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|
{ 0x4, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF4 }, // 557
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|
{ 0x4, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF2 }, // 558
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|
{ 0x4, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF2 }, // 559
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|
{ 0x4, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG4EI8_V_MF2_MF2 }, // 560
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|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG4EI16_V_M1_M1 }, // 561
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|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG4EI16_V_M2_M1 }, // 562
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|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG4EI16_V_MF4_M1 }, // 563
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|
{ 0x4, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG4EI16_V_MF2_M1 }, // 564
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|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG4EI16_V_M1_M2 }, // 565
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|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG4EI16_V_M2_M2 }, // 566
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|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG4EI16_V_M4_M2 }, // 567
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|
{ 0x4, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG4EI16_V_MF2_M2 }, // 568
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|
{ 0x4, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF8 }, // 569
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|
{ 0x4, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF4 }, // 570
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|
{ 0x4, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF4 }, // 571
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG4EI16_V_M1_MF2 }, // 572
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF2 }, // 573
|
|
{ 0x4, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF2 }, // 574
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|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG4EI32_V_M1_M1 }, // 575
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG4EI32_V_M2_M1 }, // 576
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG4EI32_V_M4_M1 }, // 577
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG4EI32_V_MF2_M1 }, // 578
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG4EI32_V_M1_M2 }, // 579
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG4EI32_V_M2_M2 }, // 580
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG4EI32_V_M4_M2 }, // 581
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG4EI32_V_M8_M2 }, // 582
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF8 }, // 583
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG4EI32_V_M1_MF4 }, // 584
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF4 }, // 585
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG4EI32_V_M1_MF2 }, // 586
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG4EI32_V_M2_MF2 }, // 587
|
|
{ 0x4, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF2 }, // 588
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG4EI64_V_M1_M1 }, // 589
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG4EI64_V_M2_M1 }, // 590
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG4EI64_V_M4_M1 }, // 591
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG4EI64_V_M8_M1 }, // 592
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG4EI64_V_M2_M2 }, // 593
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG4EI64_V_M4_M2 }, // 594
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG4EI64_V_M8_M2 }, // 595
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG4EI64_V_M1_MF8 }, // 596
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG4EI64_V_M1_MF4 }, // 597
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG4EI64_V_M2_MF4 }, // 598
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG4EI64_V_M1_MF2 }, // 599
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG4EI64_V_M2_MF2 }, // 600
|
|
{ 0x4, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG4EI64_V_M4_MF2 }, // 601
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG4EI8_V_M1_M1_MASK }, // 602
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG4EI8_V_MF8_M1_MASK }, // 603
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG4EI8_V_MF4_M1_MASK }, // 604
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG4EI8_V_MF2_M1_MASK }, // 605
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG4EI8_V_M1_M2_MASK }, // 606
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG4EI8_V_M2_M2_MASK }, // 607
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG4EI8_V_MF4_M2_MASK }, // 608
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG4EI8_V_MF2_M2_MASK }, // 609
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF8_MASK }, // 610
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF4_MASK }, // 611
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF4_MASK }, // 612
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF2_MASK }, // 613
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF2_MASK }, // 614
|
|
{ 0x4, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG4EI8_V_MF2_MF2_MASK }, // 615
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG4EI16_V_M1_M1_MASK }, // 616
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG4EI16_V_M2_M1_MASK }, // 617
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG4EI16_V_MF4_M1_MASK }, // 618
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG4EI16_V_MF2_M1_MASK }, // 619
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG4EI16_V_M1_M2_MASK }, // 620
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG4EI16_V_M2_M2_MASK }, // 621
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG4EI16_V_M4_M2_MASK }, // 622
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG4EI16_V_MF2_M2_MASK }, // 623
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF8_MASK }, // 624
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF4_MASK }, // 625
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF4_MASK }, // 626
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG4EI16_V_M1_MF2_MASK }, // 627
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF2_MASK }, // 628
|
|
{ 0x4, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF2_MASK }, // 629
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG4EI32_V_M1_M1_MASK }, // 630
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG4EI32_V_M2_M1_MASK }, // 631
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG4EI32_V_M4_M1_MASK }, // 632
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG4EI32_V_MF2_M1_MASK }, // 633
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG4EI32_V_M1_M2_MASK }, // 634
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG4EI32_V_M2_M2_MASK }, // 635
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG4EI32_V_M4_M2_MASK }, // 636
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG4EI32_V_M8_M2_MASK }, // 637
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF8_MASK }, // 638
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG4EI32_V_M1_MF4_MASK }, // 639
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF4_MASK }, // 640
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG4EI32_V_M1_MF2_MASK }, // 641
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG4EI32_V_M2_MF2_MASK }, // 642
|
|
{ 0x4, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF2_MASK }, // 643
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG4EI64_V_M1_M1_MASK }, // 644
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG4EI64_V_M2_M1_MASK }, // 645
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG4EI64_V_M4_M1_MASK }, // 646
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG4EI64_V_M8_M1_MASK }, // 647
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG4EI64_V_M2_M2_MASK }, // 648
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG4EI64_V_M4_M2_MASK }, // 649
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG4EI64_V_M8_M2_MASK }, // 650
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG4EI64_V_M1_MF8_MASK }, // 651
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG4EI64_V_M1_MF4_MASK }, // 652
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG4EI64_V_M2_MF4_MASK }, // 653
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG4EI64_V_M1_MF2_MASK }, // 654
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG4EI64_V_M2_MF2_MASK }, // 655
|
|
{ 0x4, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG4EI64_V_M4_MF2_MASK }, // 656
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG4EI8_V_M1_M1_MASK }, // 657
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG4EI8_V_MF8_M1_MASK }, // 658
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG4EI8_V_MF4_M1_MASK }, // 659
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG4EI8_V_MF2_M1_MASK }, // 660
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG4EI8_V_M1_M2_MASK }, // 661
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG4EI8_V_M2_M2_MASK }, // 662
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG4EI8_V_MF4_M2_MASK }, // 663
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG4EI8_V_MF2_M2_MASK }, // 664
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF8_MASK }, // 665
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF4_MASK }, // 666
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF4_MASK }, // 667
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF2_MASK }, // 668
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF2_MASK }, // 669
|
|
{ 0x4, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG4EI8_V_MF2_MF2_MASK }, // 670
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG4EI16_V_M1_M1_MASK }, // 671
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG4EI16_V_M2_M1_MASK }, // 672
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG4EI16_V_MF4_M1_MASK }, // 673
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG4EI16_V_MF2_M1_MASK }, // 674
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG4EI16_V_M1_M2_MASK }, // 675
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG4EI16_V_M2_M2_MASK }, // 676
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG4EI16_V_M4_M2_MASK }, // 677
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG4EI16_V_MF2_M2_MASK }, // 678
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF8_MASK }, // 679
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF4_MASK }, // 680
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF4_MASK }, // 681
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG4EI16_V_M1_MF2_MASK }, // 682
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF2_MASK }, // 683
|
|
{ 0x4, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF2_MASK }, // 684
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG4EI32_V_M1_M1_MASK }, // 685
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG4EI32_V_M2_M1_MASK }, // 686
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG4EI32_V_M4_M1_MASK }, // 687
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG4EI32_V_MF2_M1_MASK }, // 688
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG4EI32_V_M1_M2_MASK }, // 689
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG4EI32_V_M2_M2_MASK }, // 690
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG4EI32_V_M4_M2_MASK }, // 691
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG4EI32_V_M8_M2_MASK }, // 692
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF8_MASK }, // 693
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG4EI32_V_M1_MF4_MASK }, // 694
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF4_MASK }, // 695
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG4EI32_V_M1_MF2_MASK }, // 696
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG4EI32_V_M2_MF2_MASK }, // 697
|
|
{ 0x4, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF2_MASK }, // 698
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG4EI64_V_M1_M1_MASK }, // 699
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG4EI64_V_M2_M1_MASK }, // 700
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG4EI64_V_M4_M1_MASK }, // 701
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG4EI64_V_M8_M1_MASK }, // 702
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG4EI64_V_M2_M2_MASK }, // 703
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG4EI64_V_M4_M2_MASK }, // 704
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG4EI64_V_M8_M2_MASK }, // 705
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG4EI64_V_M1_MF8_MASK }, // 706
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG4EI64_V_M1_MF4_MASK }, // 707
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG4EI64_V_M2_MF4_MASK }, // 708
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG4EI64_V_M1_MF2_MASK }, // 709
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG4EI64_V_M2_MF2_MASK }, // 710
|
|
{ 0x4, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG4EI64_V_M4_MF2_MASK }, // 711
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG5EI8_V_M1_M1 }, // 712
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG5EI8_V_MF8_M1 }, // 713
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG5EI8_V_MF4_M1 }, // 714
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG5EI8_V_MF2_M1 }, // 715
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF8 }, // 716
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF4 }, // 717
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF4 }, // 718
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF2 }, // 719
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF2 }, // 720
|
|
{ 0x5, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG5EI8_V_MF2_MF2 }, // 721
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG5EI16_V_M1_M1 }, // 722
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG5EI16_V_M2_M1 }, // 723
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG5EI16_V_MF4_M1 }, // 724
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG5EI16_V_MF2_M1 }, // 725
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF8 }, // 726
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF4 }, // 727
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF4 }, // 728
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG5EI16_V_M1_MF2 }, // 729
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF2 }, // 730
|
|
{ 0x5, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF2 }, // 731
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG5EI32_V_M1_M1 }, // 732
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG5EI32_V_M2_M1 }, // 733
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG5EI32_V_M4_M1 }, // 734
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG5EI32_V_MF2_M1 }, // 735
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF8 }, // 736
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG5EI32_V_M1_MF4 }, // 737
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF4 }, // 738
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG5EI32_V_M1_MF2 }, // 739
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG5EI32_V_M2_MF2 }, // 740
|
|
{ 0x5, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF2 }, // 741
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG5EI64_V_M1_M1 }, // 742
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG5EI64_V_M2_M1 }, // 743
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG5EI64_V_M4_M1 }, // 744
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG5EI64_V_M8_M1 }, // 745
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG5EI64_V_M1_MF8 }, // 746
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG5EI64_V_M1_MF4 }, // 747
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG5EI64_V_M2_MF4 }, // 748
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG5EI64_V_M1_MF2 }, // 749
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG5EI64_V_M2_MF2 }, // 750
|
|
{ 0x5, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG5EI64_V_M4_MF2 }, // 751
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG5EI8_V_M1_M1 }, // 752
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG5EI8_V_MF8_M1 }, // 753
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG5EI8_V_MF4_M1 }, // 754
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG5EI8_V_MF2_M1 }, // 755
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF8 }, // 756
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF4 }, // 757
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF4 }, // 758
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF2 }, // 759
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF2 }, // 760
|
|
{ 0x5, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG5EI8_V_MF2_MF2 }, // 761
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG5EI16_V_M1_M1 }, // 762
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG5EI16_V_M2_M1 }, // 763
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG5EI16_V_MF4_M1 }, // 764
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG5EI16_V_MF2_M1 }, // 765
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF8 }, // 766
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF4 }, // 767
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF4 }, // 768
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG5EI16_V_M1_MF2 }, // 769
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF2 }, // 770
|
|
{ 0x5, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF2 }, // 771
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG5EI32_V_M1_M1 }, // 772
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG5EI32_V_M2_M1 }, // 773
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG5EI32_V_M4_M1 }, // 774
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG5EI32_V_MF2_M1 }, // 775
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF8 }, // 776
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG5EI32_V_M1_MF4 }, // 777
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF4 }, // 778
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG5EI32_V_M1_MF2 }, // 779
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG5EI32_V_M2_MF2 }, // 780
|
|
{ 0x5, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF2 }, // 781
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG5EI64_V_M1_M1 }, // 782
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG5EI64_V_M2_M1 }, // 783
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG5EI64_V_M4_M1 }, // 784
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG5EI64_V_M8_M1 }, // 785
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG5EI64_V_M1_MF8 }, // 786
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG5EI64_V_M1_MF4 }, // 787
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG5EI64_V_M2_MF4 }, // 788
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG5EI64_V_M1_MF2 }, // 789
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG5EI64_V_M2_MF2 }, // 790
|
|
{ 0x5, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG5EI64_V_M4_MF2 }, // 791
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG5EI8_V_M1_M1_MASK }, // 792
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG5EI8_V_MF8_M1_MASK }, // 793
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG5EI8_V_MF4_M1_MASK }, // 794
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG5EI8_V_MF2_M1_MASK }, // 795
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF8_MASK }, // 796
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF4_MASK }, // 797
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF4_MASK }, // 798
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF2_MASK }, // 799
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF2_MASK }, // 800
|
|
{ 0x5, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG5EI8_V_MF2_MF2_MASK }, // 801
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG5EI16_V_M1_M1_MASK }, // 802
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG5EI16_V_M2_M1_MASK }, // 803
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG5EI16_V_MF4_M1_MASK }, // 804
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG5EI16_V_MF2_M1_MASK }, // 805
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF8_MASK }, // 806
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF4_MASK }, // 807
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF4_MASK }, // 808
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG5EI16_V_M1_MF2_MASK }, // 809
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF2_MASK }, // 810
|
|
{ 0x5, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF2_MASK }, // 811
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG5EI32_V_M1_M1_MASK }, // 812
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG5EI32_V_M2_M1_MASK }, // 813
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG5EI32_V_M4_M1_MASK }, // 814
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG5EI32_V_MF2_M1_MASK }, // 815
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF8_MASK }, // 816
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG5EI32_V_M1_MF4_MASK }, // 817
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF4_MASK }, // 818
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG5EI32_V_M1_MF2_MASK }, // 819
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG5EI32_V_M2_MF2_MASK }, // 820
|
|
{ 0x5, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF2_MASK }, // 821
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG5EI64_V_M1_M1_MASK }, // 822
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG5EI64_V_M2_M1_MASK }, // 823
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG5EI64_V_M4_M1_MASK }, // 824
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG5EI64_V_M8_M1_MASK }, // 825
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG5EI64_V_M1_MF8_MASK }, // 826
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG5EI64_V_M1_MF4_MASK }, // 827
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG5EI64_V_M2_MF4_MASK }, // 828
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG5EI64_V_M1_MF2_MASK }, // 829
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG5EI64_V_M2_MF2_MASK }, // 830
|
|
{ 0x5, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG5EI64_V_M4_MF2_MASK }, // 831
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG5EI8_V_M1_M1_MASK }, // 832
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG5EI8_V_MF8_M1_MASK }, // 833
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG5EI8_V_MF4_M1_MASK }, // 834
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG5EI8_V_MF2_M1_MASK }, // 835
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF8_MASK }, // 836
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF4_MASK }, // 837
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF4_MASK }, // 838
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF2_MASK }, // 839
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF2_MASK }, // 840
|
|
{ 0x5, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG5EI8_V_MF2_MF2_MASK }, // 841
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG5EI16_V_M1_M1_MASK }, // 842
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG5EI16_V_M2_M1_MASK }, // 843
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG5EI16_V_MF4_M1_MASK }, // 844
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG5EI16_V_MF2_M1_MASK }, // 845
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF8_MASK }, // 846
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF4_MASK }, // 847
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF4_MASK }, // 848
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG5EI16_V_M1_MF2_MASK }, // 849
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF2_MASK }, // 850
|
|
{ 0x5, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF2_MASK }, // 851
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG5EI32_V_M1_M1_MASK }, // 852
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG5EI32_V_M2_M1_MASK }, // 853
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG5EI32_V_M4_M1_MASK }, // 854
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG5EI32_V_MF2_M1_MASK }, // 855
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF8_MASK }, // 856
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG5EI32_V_M1_MF4_MASK }, // 857
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF4_MASK }, // 858
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG5EI32_V_M1_MF2_MASK }, // 859
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG5EI32_V_M2_MF2_MASK }, // 860
|
|
{ 0x5, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF2_MASK }, // 861
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG5EI64_V_M1_M1_MASK }, // 862
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG5EI64_V_M2_M1_MASK }, // 863
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG5EI64_V_M4_M1_MASK }, // 864
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG5EI64_V_M8_M1_MASK }, // 865
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG5EI64_V_M1_MF8_MASK }, // 866
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG5EI64_V_M1_MF4_MASK }, // 867
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG5EI64_V_M2_MF4_MASK }, // 868
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG5EI64_V_M1_MF2_MASK }, // 869
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG5EI64_V_M2_MF2_MASK }, // 870
|
|
{ 0x5, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG5EI64_V_M4_MF2_MASK }, // 871
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG6EI8_V_M1_M1 }, // 872
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG6EI8_V_MF8_M1 }, // 873
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG6EI8_V_MF4_M1 }, // 874
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG6EI8_V_MF2_M1 }, // 875
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF8 }, // 876
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF4 }, // 877
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF4 }, // 878
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF2 }, // 879
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF2 }, // 880
|
|
{ 0x6, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG6EI8_V_MF2_MF2 }, // 881
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG6EI16_V_M1_M1 }, // 882
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG6EI16_V_M2_M1 }, // 883
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG6EI16_V_MF4_M1 }, // 884
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG6EI16_V_MF2_M1 }, // 885
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF8 }, // 886
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF4 }, // 887
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF4 }, // 888
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG6EI16_V_M1_MF2 }, // 889
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF2 }, // 890
|
|
{ 0x6, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF2 }, // 891
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG6EI32_V_M1_M1 }, // 892
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG6EI32_V_M2_M1 }, // 893
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG6EI32_V_M4_M1 }, // 894
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG6EI32_V_MF2_M1 }, // 895
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF8 }, // 896
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG6EI32_V_M1_MF4 }, // 897
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF4 }, // 898
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG6EI32_V_M1_MF2 }, // 899
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG6EI32_V_M2_MF2 }, // 900
|
|
{ 0x6, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF2 }, // 901
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG6EI64_V_M1_M1 }, // 902
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG6EI64_V_M2_M1 }, // 903
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG6EI64_V_M4_M1 }, // 904
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG6EI64_V_M8_M1 }, // 905
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG6EI64_V_M1_MF8 }, // 906
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG6EI64_V_M1_MF4 }, // 907
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG6EI64_V_M2_MF4 }, // 908
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG6EI64_V_M1_MF2 }, // 909
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG6EI64_V_M2_MF2 }, // 910
|
|
{ 0x6, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG6EI64_V_M4_MF2 }, // 911
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG6EI8_V_M1_M1 }, // 912
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG6EI8_V_MF8_M1 }, // 913
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG6EI8_V_MF4_M1 }, // 914
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG6EI8_V_MF2_M1 }, // 915
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF8 }, // 916
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF4 }, // 917
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF4 }, // 918
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF2 }, // 919
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF2 }, // 920
|
|
{ 0x6, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG6EI8_V_MF2_MF2 }, // 921
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG6EI16_V_M1_M1 }, // 922
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG6EI16_V_M2_M1 }, // 923
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG6EI16_V_MF4_M1 }, // 924
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG6EI16_V_MF2_M1 }, // 925
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF8 }, // 926
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF4 }, // 927
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF4 }, // 928
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG6EI16_V_M1_MF2 }, // 929
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF2 }, // 930
|
|
{ 0x6, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF2 }, // 931
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG6EI32_V_M1_M1 }, // 932
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG6EI32_V_M2_M1 }, // 933
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG6EI32_V_M4_M1 }, // 934
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG6EI32_V_MF2_M1 }, // 935
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF8 }, // 936
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG6EI32_V_M1_MF4 }, // 937
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF4 }, // 938
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG6EI32_V_M1_MF2 }, // 939
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG6EI32_V_M2_MF2 }, // 940
|
|
{ 0x6, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF2 }, // 941
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG6EI64_V_M1_M1 }, // 942
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG6EI64_V_M2_M1 }, // 943
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG6EI64_V_M4_M1 }, // 944
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG6EI64_V_M8_M1 }, // 945
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG6EI64_V_M1_MF8 }, // 946
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG6EI64_V_M1_MF4 }, // 947
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG6EI64_V_M2_MF4 }, // 948
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG6EI64_V_M1_MF2 }, // 949
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG6EI64_V_M2_MF2 }, // 950
|
|
{ 0x6, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG6EI64_V_M4_MF2 }, // 951
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG6EI8_V_M1_M1_MASK }, // 952
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG6EI8_V_MF8_M1_MASK }, // 953
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG6EI8_V_MF4_M1_MASK }, // 954
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG6EI8_V_MF2_M1_MASK }, // 955
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF8_MASK }, // 956
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF4_MASK }, // 957
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF4_MASK }, // 958
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF2_MASK }, // 959
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF2_MASK }, // 960
|
|
{ 0x6, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG6EI8_V_MF2_MF2_MASK }, // 961
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG6EI16_V_M1_M1_MASK }, // 962
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG6EI16_V_M2_M1_MASK }, // 963
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG6EI16_V_MF4_M1_MASK }, // 964
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG6EI16_V_MF2_M1_MASK }, // 965
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF8_MASK }, // 966
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF4_MASK }, // 967
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF4_MASK }, // 968
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG6EI16_V_M1_MF2_MASK }, // 969
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF2_MASK }, // 970
|
|
{ 0x6, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF2_MASK }, // 971
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG6EI32_V_M1_M1_MASK }, // 972
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG6EI32_V_M2_M1_MASK }, // 973
|
|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG6EI32_V_M4_M1_MASK }, // 974
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|
{ 0x6, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG6EI32_V_MF2_M1_MASK }, // 975
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|
{ 0x6, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF8_MASK }, // 976
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|
{ 0x6, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG6EI32_V_M1_MF4_MASK }, // 977
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|
{ 0x6, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF4_MASK }, // 978
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|
{ 0x6, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG6EI32_V_M1_MF2_MASK }, // 979
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|
{ 0x6, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG6EI32_V_M2_MF2_MASK }, // 980
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|
{ 0x6, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF2_MASK }, // 981
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|
{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG6EI64_V_M1_M1_MASK }, // 982
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|
{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG6EI64_V_M2_M1_MASK }, // 983
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{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG6EI64_V_M4_M1_MASK }, // 984
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{ 0x6, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG6EI64_V_M8_M1_MASK }, // 985
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{ 0x6, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG6EI64_V_M1_MF8_MASK }, // 986
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|
{ 0x6, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG6EI64_V_M1_MF4_MASK }, // 987
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|
{ 0x6, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG6EI64_V_M2_MF4_MASK }, // 988
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|
{ 0x6, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG6EI64_V_M1_MF2_MASK }, // 989
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|
{ 0x6, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG6EI64_V_M2_MF2_MASK }, // 990
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|
{ 0x6, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG6EI64_V_M4_MF2_MASK }, // 991
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|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG6EI8_V_M1_M1_MASK }, // 992
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|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG6EI8_V_MF8_M1_MASK }, // 993
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|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG6EI8_V_MF4_M1_MASK }, // 994
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|
{ 0x6, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG6EI8_V_MF2_M1_MASK }, // 995
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|
{ 0x6, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF8_MASK }, // 996
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|
{ 0x6, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF4_MASK }, // 997
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|
{ 0x6, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF4_MASK }, // 998
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|
{ 0x6, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF2_MASK }, // 999
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|
{ 0x6, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF2_MASK }, // 1000
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|
{ 0x6, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG6EI8_V_MF2_MF2_MASK }, // 1001
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|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG6EI16_V_M1_M1_MASK }, // 1002
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|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG6EI16_V_M2_M1_MASK }, // 1003
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|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG6EI16_V_MF4_M1_MASK }, // 1004
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|
{ 0x6, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG6EI16_V_MF2_M1_MASK }, // 1005
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|
{ 0x6, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF8_MASK }, // 1006
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|
{ 0x6, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF4_MASK }, // 1007
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF4_MASK }, // 1008
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG6EI16_V_M1_MF2_MASK }, // 1009
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF2_MASK }, // 1010
|
|
{ 0x6, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF2_MASK }, // 1011
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG6EI32_V_M1_M1_MASK }, // 1012
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG6EI32_V_M2_M1_MASK }, // 1013
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG6EI32_V_M4_M1_MASK }, // 1014
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG6EI32_V_MF2_M1_MASK }, // 1015
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF8_MASK }, // 1016
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|
{ 0x6, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG6EI32_V_M1_MF4_MASK }, // 1017
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF4_MASK }, // 1018
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG6EI32_V_M1_MF2_MASK }, // 1019
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|
{ 0x6, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG6EI32_V_M2_MF2_MASK }, // 1020
|
|
{ 0x6, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF2_MASK }, // 1021
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG6EI64_V_M1_M1_MASK }, // 1022
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG6EI64_V_M2_M1_MASK }, // 1023
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG6EI64_V_M4_M1_MASK }, // 1024
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG6EI64_V_M8_M1_MASK }, // 1025
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG6EI64_V_M1_MF8_MASK }, // 1026
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG6EI64_V_M1_MF4_MASK }, // 1027
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG6EI64_V_M2_MF4_MASK }, // 1028
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG6EI64_V_M1_MF2_MASK }, // 1029
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG6EI64_V_M2_MF2_MASK }, // 1030
|
|
{ 0x6, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG6EI64_V_M4_MF2_MASK }, // 1031
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG7EI8_V_M1_M1 }, // 1032
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG7EI8_V_MF8_M1 }, // 1033
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG7EI8_V_MF4_M1 }, // 1034
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG7EI8_V_MF2_M1 }, // 1035
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF8 }, // 1036
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF4 }, // 1037
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF4 }, // 1038
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF2 }, // 1039
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF2 }, // 1040
|
|
{ 0x7, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG7EI8_V_MF2_MF2 }, // 1041
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG7EI16_V_M1_M1 }, // 1042
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG7EI16_V_M2_M1 }, // 1043
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG7EI16_V_MF4_M1 }, // 1044
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG7EI16_V_MF2_M1 }, // 1045
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF8 }, // 1046
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF4 }, // 1047
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF4 }, // 1048
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG7EI16_V_M1_MF2 }, // 1049
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF2 }, // 1050
|
|
{ 0x7, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF2 }, // 1051
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG7EI32_V_M1_M1 }, // 1052
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG7EI32_V_M2_M1 }, // 1053
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG7EI32_V_M4_M1 }, // 1054
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG7EI32_V_MF2_M1 }, // 1055
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF8 }, // 1056
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG7EI32_V_M1_MF4 }, // 1057
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF4 }, // 1058
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG7EI32_V_M1_MF2 }, // 1059
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG7EI32_V_M2_MF2 }, // 1060
|
|
{ 0x7, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF2 }, // 1061
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG7EI64_V_M1_M1 }, // 1062
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG7EI64_V_M2_M1 }, // 1063
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG7EI64_V_M4_M1 }, // 1064
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG7EI64_V_M8_M1 }, // 1065
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG7EI64_V_M1_MF8 }, // 1066
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG7EI64_V_M1_MF4 }, // 1067
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG7EI64_V_M2_MF4 }, // 1068
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG7EI64_V_M1_MF2 }, // 1069
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG7EI64_V_M2_MF2 }, // 1070
|
|
{ 0x7, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG7EI64_V_M4_MF2 }, // 1071
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG7EI8_V_M1_M1 }, // 1072
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG7EI8_V_MF8_M1 }, // 1073
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG7EI8_V_MF4_M1 }, // 1074
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG7EI8_V_MF2_M1 }, // 1075
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF8 }, // 1076
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF4 }, // 1077
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF4 }, // 1078
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF2 }, // 1079
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF2 }, // 1080
|
|
{ 0x7, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG7EI8_V_MF2_MF2 }, // 1081
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG7EI16_V_M1_M1 }, // 1082
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG7EI16_V_M2_M1 }, // 1083
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG7EI16_V_MF4_M1 }, // 1084
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG7EI16_V_MF2_M1 }, // 1085
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF8 }, // 1086
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF4 }, // 1087
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF4 }, // 1088
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG7EI16_V_M1_MF2 }, // 1089
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF2 }, // 1090
|
|
{ 0x7, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF2 }, // 1091
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG7EI32_V_M1_M1 }, // 1092
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG7EI32_V_M2_M1 }, // 1093
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG7EI32_V_M4_M1 }, // 1094
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG7EI32_V_MF2_M1 }, // 1095
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF8 }, // 1096
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG7EI32_V_M1_MF4 }, // 1097
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF4 }, // 1098
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG7EI32_V_M1_MF2 }, // 1099
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG7EI32_V_M2_MF2 }, // 1100
|
|
{ 0x7, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF2 }, // 1101
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG7EI64_V_M1_M1 }, // 1102
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG7EI64_V_M2_M1 }, // 1103
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG7EI64_V_M4_M1 }, // 1104
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG7EI64_V_M8_M1 }, // 1105
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG7EI64_V_M1_MF8 }, // 1106
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG7EI64_V_M1_MF4 }, // 1107
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG7EI64_V_M2_MF4 }, // 1108
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG7EI64_V_M1_MF2 }, // 1109
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG7EI64_V_M2_MF2 }, // 1110
|
|
{ 0x7, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG7EI64_V_M4_MF2 }, // 1111
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG7EI8_V_M1_M1_MASK }, // 1112
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG7EI8_V_MF8_M1_MASK }, // 1113
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG7EI8_V_MF4_M1_MASK }, // 1114
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG7EI8_V_MF2_M1_MASK }, // 1115
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF8_MASK }, // 1116
|
|
{ 0x7, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF4_MASK }, // 1117
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{ 0x7, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF4_MASK }, // 1118
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{ 0x7, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF2_MASK }, // 1119
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{ 0x7, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF2_MASK }, // 1120
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{ 0x7, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG7EI8_V_MF2_MF2_MASK }, // 1121
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{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG7EI16_V_M1_M1_MASK }, // 1122
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{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG7EI16_V_M2_M1_MASK }, // 1123
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{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG7EI16_V_MF4_M1_MASK }, // 1124
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{ 0x7, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG7EI16_V_MF2_M1_MASK }, // 1125
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{ 0x7, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF8_MASK }, // 1126
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{ 0x7, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF4_MASK }, // 1127
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{ 0x7, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF4_MASK }, // 1128
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{ 0x7, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG7EI16_V_M1_MF2_MASK }, // 1129
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{ 0x7, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF2_MASK }, // 1130
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{ 0x7, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF2_MASK }, // 1131
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG7EI32_V_M1_M1_MASK }, // 1132
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG7EI32_V_M2_M1_MASK }, // 1133
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG7EI32_V_M4_M1_MASK }, // 1134
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{ 0x7, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG7EI32_V_MF2_M1_MASK }, // 1135
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{ 0x7, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF8_MASK }, // 1136
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{ 0x7, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG7EI32_V_M1_MF4_MASK }, // 1137
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{ 0x7, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF4_MASK }, // 1138
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{ 0x7, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG7EI32_V_M1_MF2_MASK }, // 1139
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{ 0x7, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG7EI32_V_M2_MF2_MASK }, // 1140
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{ 0x7, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF2_MASK }, // 1141
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{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG7EI64_V_M1_M1_MASK }, // 1142
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{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG7EI64_V_M2_M1_MASK }, // 1143
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{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG7EI64_V_M4_M1_MASK }, // 1144
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{ 0x7, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG7EI64_V_M8_M1_MASK }, // 1145
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{ 0x7, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG7EI64_V_M1_MF8_MASK }, // 1146
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{ 0x7, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG7EI64_V_M1_MF4_MASK }, // 1147
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{ 0x7, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG7EI64_V_M2_MF4_MASK }, // 1148
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{ 0x7, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG7EI64_V_M1_MF2_MASK }, // 1149
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{ 0x7, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG7EI64_V_M2_MF2_MASK }, // 1150
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{ 0x7, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG7EI64_V_M4_MF2_MASK }, // 1151
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{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG7EI8_V_M1_M1_MASK }, // 1152
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{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG7EI8_V_MF8_M1_MASK }, // 1153
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{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG7EI8_V_MF4_M1_MASK }, // 1154
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{ 0x7, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG7EI8_V_MF2_M1_MASK }, // 1155
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{ 0x7, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF8_MASK }, // 1156
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{ 0x7, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF4_MASK }, // 1157
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{ 0x7, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF4_MASK }, // 1158
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{ 0x7, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF2_MASK }, // 1159
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{ 0x7, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF2_MASK }, // 1160
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{ 0x7, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG7EI8_V_MF2_MF2_MASK }, // 1161
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{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG7EI16_V_M1_M1_MASK }, // 1162
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{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG7EI16_V_M2_M1_MASK }, // 1163
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{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG7EI16_V_MF4_M1_MASK }, // 1164
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{ 0x7, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG7EI16_V_MF2_M1_MASK }, // 1165
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|
{ 0x7, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF8_MASK }, // 1166
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{ 0x7, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF4_MASK }, // 1167
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{ 0x7, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF4_MASK }, // 1168
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{ 0x7, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG7EI16_V_M1_MF2_MASK }, // 1169
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{ 0x7, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF2_MASK }, // 1170
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{ 0x7, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF2_MASK }, // 1171
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{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG7EI32_V_M1_M1_MASK }, // 1172
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{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG7EI32_V_M2_M1_MASK }, // 1173
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{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG7EI32_V_M4_M1_MASK }, // 1174
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{ 0x7, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG7EI32_V_MF2_M1_MASK }, // 1175
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{ 0x7, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF8_MASK }, // 1176
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{ 0x7, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG7EI32_V_M1_MF4_MASK }, // 1177
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{ 0x7, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF4_MASK }, // 1178
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{ 0x7, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG7EI32_V_M1_MF2_MASK }, // 1179
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{ 0x7, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG7EI32_V_M2_MF2_MASK }, // 1180
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{ 0x7, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF2_MASK }, // 1181
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{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG7EI64_V_M1_M1_MASK }, // 1182
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{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG7EI64_V_M2_M1_MASK }, // 1183
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{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG7EI64_V_M4_M1_MASK }, // 1184
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{ 0x7, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG7EI64_V_M8_M1_MASK }, // 1185
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{ 0x7, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG7EI64_V_M1_MF8_MASK }, // 1186
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{ 0x7, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG7EI64_V_M1_MF4_MASK }, // 1187
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{ 0x7, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG7EI64_V_M2_MF4_MASK }, // 1188
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{ 0x7, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG7EI64_V_M1_MF2_MASK }, // 1189
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{ 0x7, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG7EI64_V_M2_MF2_MASK }, // 1190
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{ 0x7, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG7EI64_V_M4_MF2_MASK }, // 1191
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{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG8EI8_V_M1_M1 }, // 1192
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{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG8EI8_V_MF8_M1 }, // 1193
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{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG8EI8_V_MF4_M1 }, // 1194
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{ 0x8, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG8EI8_V_MF2_M1 }, // 1195
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{ 0x8, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF8 }, // 1196
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{ 0x8, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF4 }, // 1197
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{ 0x8, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF4 }, // 1198
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{ 0x8, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF2 }, // 1199
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{ 0x8, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF2 }, // 1200
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{ 0x8, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG8EI8_V_MF2_MF2 }, // 1201
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{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG8EI16_V_M1_M1 }, // 1202
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{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG8EI16_V_M2_M1 }, // 1203
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{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG8EI16_V_MF4_M1 }, // 1204
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{ 0x8, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG8EI16_V_MF2_M1 }, // 1205
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|
{ 0x8, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF8 }, // 1206
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|
{ 0x8, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF4 }, // 1207
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{ 0x8, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF4 }, // 1208
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{ 0x8, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG8EI16_V_M1_MF2 }, // 1209
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{ 0x8, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF2 }, // 1210
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{ 0x8, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF2 }, // 1211
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{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG8EI32_V_M1_M1 }, // 1212
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{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG8EI32_V_M2_M1 }, // 1213
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{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG8EI32_V_M4_M1 }, // 1214
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{ 0x8, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG8EI32_V_MF2_M1 }, // 1215
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|
{ 0x8, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF8 }, // 1216
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|
{ 0x8, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG8EI32_V_M1_MF4 }, // 1217
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|
{ 0x8, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF4 }, // 1218
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{ 0x8, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG8EI32_V_M1_MF2 }, // 1219
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|
{ 0x8, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG8EI32_V_M2_MF2 }, // 1220
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{ 0x8, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF2 }, // 1221
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|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG8EI64_V_M1_M1 }, // 1222
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|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG8EI64_V_M2_M1 }, // 1223
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|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG8EI64_V_M4_M1 }, // 1224
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|
{ 0x8, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG8EI64_V_M8_M1 }, // 1225
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|
{ 0x8, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG8EI64_V_M1_MF8 }, // 1226
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|
{ 0x8, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG8EI64_V_M1_MF4 }, // 1227
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|
{ 0x8, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG8EI64_V_M2_MF4 }, // 1228
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|
{ 0x8, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG8EI64_V_M1_MF2 }, // 1229
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{ 0x8, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG8EI64_V_M2_MF2 }, // 1230
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|
{ 0x8, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG8EI64_V_M4_MF2 }, // 1231
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG8EI8_V_M1_M1 }, // 1232
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG8EI8_V_MF8_M1 }, // 1233
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG8EI8_V_MF4_M1 }, // 1234
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG8EI8_V_MF2_M1 }, // 1235
|
|
{ 0x8, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF8 }, // 1236
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|
{ 0x8, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF4 }, // 1237
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|
{ 0x8, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF4 }, // 1238
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|
{ 0x8, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF2 }, // 1239
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|
{ 0x8, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF2 }, // 1240
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|
{ 0x8, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG8EI8_V_MF2_MF2 }, // 1241
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG8EI16_V_M1_M1 }, // 1242
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG8EI16_V_M2_M1 }, // 1243
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG8EI16_V_MF4_M1 }, // 1244
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG8EI16_V_MF2_M1 }, // 1245
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF8 }, // 1246
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF4 }, // 1247
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF4 }, // 1248
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG8EI16_V_M1_MF2 }, // 1249
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF2 }, // 1250
|
|
{ 0x8, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF2 }, // 1251
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG8EI32_V_M1_M1 }, // 1252
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG8EI32_V_M2_M1 }, // 1253
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG8EI32_V_M4_M1 }, // 1254
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG8EI32_V_MF2_M1 }, // 1255
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF8 }, // 1256
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG8EI32_V_M1_MF4 }, // 1257
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF4 }, // 1258
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG8EI32_V_M1_MF2 }, // 1259
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG8EI32_V_M2_MF2 }, // 1260
|
|
{ 0x8, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF2 }, // 1261
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG8EI64_V_M1_M1 }, // 1262
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG8EI64_V_M2_M1 }, // 1263
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG8EI64_V_M4_M1 }, // 1264
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG8EI64_V_M8_M1 }, // 1265
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG8EI64_V_M1_MF8 }, // 1266
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG8EI64_V_M1_MF4 }, // 1267
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG8EI64_V_M2_MF4 }, // 1268
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG8EI64_V_M1_MF2 }, // 1269
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG8EI64_V_M2_MF2 }, // 1270
|
|
{ 0x8, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG8EI64_V_M4_MF2 }, // 1271
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG8EI8_V_M1_M1_MASK }, // 1272
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG8EI8_V_MF8_M1_MASK }, // 1273
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG8EI8_V_MF4_M1_MASK }, // 1274
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG8EI8_V_MF2_M1_MASK }, // 1275
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF8_MASK }, // 1276
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF4_MASK }, // 1277
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF4_MASK }, // 1278
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF2_MASK }, // 1279
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF2_MASK }, // 1280
|
|
{ 0x8, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG8EI8_V_MF2_MF2_MASK }, // 1281
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG8EI16_V_M1_M1_MASK }, // 1282
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG8EI16_V_M2_M1_MASK }, // 1283
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG8EI16_V_MF4_M1_MASK }, // 1284
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG8EI16_V_MF2_M1_MASK }, // 1285
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF8_MASK }, // 1286
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF4_MASK }, // 1287
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF4_MASK }, // 1288
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG8EI16_V_M1_MF2_MASK }, // 1289
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF2_MASK }, // 1290
|
|
{ 0x8, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF2_MASK }, // 1291
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG8EI32_V_M1_M1_MASK }, // 1292
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG8EI32_V_M2_M1_MASK }, // 1293
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG8EI32_V_M4_M1_MASK }, // 1294
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG8EI32_V_MF2_M1_MASK }, // 1295
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF8_MASK }, // 1296
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG8EI32_V_M1_MF4_MASK }, // 1297
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF4_MASK }, // 1298
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG8EI32_V_M1_MF2_MASK }, // 1299
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG8EI32_V_M2_MF2_MASK }, // 1300
|
|
{ 0x8, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF2_MASK }, // 1301
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG8EI64_V_M1_M1_MASK }, // 1302
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG8EI64_V_M2_M1_MASK }, // 1303
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG8EI64_V_M4_M1_MASK }, // 1304
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG8EI64_V_M8_M1_MASK }, // 1305
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG8EI64_V_M1_MF8_MASK }, // 1306
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG8EI64_V_M1_MF4_MASK }, // 1307
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG8EI64_V_M2_MF4_MASK }, // 1308
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG8EI64_V_M1_MF2_MASK }, // 1309
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG8EI64_V_M2_MF2_MASK }, // 1310
|
|
{ 0x8, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG8EI64_V_M4_MF2_MASK }, // 1311
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG8EI8_V_M1_M1_MASK }, // 1312
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG8EI8_V_MF8_M1_MASK }, // 1313
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG8EI8_V_MF4_M1_MASK }, // 1314
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG8EI8_V_MF2_M1_MASK }, // 1315
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF8_MASK }, // 1316
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF4_MASK }, // 1317
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF4_MASK }, // 1318
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF2_MASK }, // 1319
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF2_MASK }, // 1320
|
|
{ 0x8, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG8EI8_V_MF2_MF2_MASK }, // 1321
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG8EI16_V_M1_M1_MASK }, // 1322
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG8EI16_V_M2_M1_MASK }, // 1323
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG8EI16_V_MF4_M1_MASK }, // 1324
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG8EI16_V_MF2_M1_MASK }, // 1325
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF8_MASK }, // 1326
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF4_MASK }, // 1327
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF4_MASK }, // 1328
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG8EI16_V_M1_MF2_MASK }, // 1329
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF2_MASK }, // 1330
|
|
{ 0x8, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF2_MASK }, // 1331
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG8EI32_V_M1_M1_MASK }, // 1332
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG8EI32_V_M2_M1_MASK }, // 1333
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG8EI32_V_M4_M1_MASK }, // 1334
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG8EI32_V_MF2_M1_MASK }, // 1335
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF8_MASK }, // 1336
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG8EI32_V_M1_MF4_MASK }, // 1337
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF4_MASK }, // 1338
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG8EI32_V_M1_MF2_MASK }, // 1339
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG8EI32_V_M2_MF2_MASK }, // 1340
|
|
{ 0x8, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF2_MASK }, // 1341
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG8EI64_V_M1_M1_MASK }, // 1342
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG8EI64_V_M2_M1_MASK }, // 1343
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG8EI64_V_M4_M1_MASK }, // 1344
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG8EI64_V_M8_M1_MASK }, // 1345
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG8EI64_V_M1_MF8_MASK }, // 1346
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG8EI64_V_M1_MF4_MASK }, // 1347
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG8EI64_V_M2_MF4_MASK }, // 1348
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG8EI64_V_M1_MF2_MASK }, // 1349
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG8EI64_V_M2_MF2_MASK }, // 1350
|
|
{ 0x8, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG8EI64_V_M4_MF2_MASK }, // 1351
|
|
};
|
|
|
|
const RISCV_VSXSEGPseudo *RISCV_getVSXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedOrderedLog2SEWLMULIndexLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVSXSEGTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_RISCVVSXTable_IMPL
|
|
static const RISCV_VLX_VSXPseudo RISCVVSXTable[] = {
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXEI8_V_M1_M1 }, // 0
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXEI8_V_MF8_M1 }, // 1
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXEI8_V_MF4_M1 }, // 2
|
|
{ 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXEI8_V_MF2_M1 }, // 3
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXEI8_V_M1_M2 }, // 4
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXEI8_V_M2_M2 }, // 5
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXEI8_V_MF4_M2 }, // 6
|
|
{ 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXEI8_V_MF2_M2 }, // 7
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVSUXEI8_V_M1_M4 }, // 8
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVSUXEI8_V_M2_M4 }, // 9
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVSUXEI8_V_M4_M4 }, // 10
|
|
{ 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVSUXEI8_V_MF2_M4 }, // 11
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x0, PseudoVSUXEI8_V_M1_M8 }, // 12
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x1, PseudoVSUXEI8_V_M2_M8 }, // 13
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x2, PseudoVSUXEI8_V_M4_M8 }, // 14
|
|
{ 0x0, 0x0, 0x3, 0x3, 0x3, PseudoVSUXEI8_V_M8_M8 }, // 15
|
|
{ 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXEI8_V_MF8_MF8 }, // 16
|
|
{ 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXEI8_V_MF8_MF4 }, // 17
|
|
{ 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXEI8_V_MF4_MF4 }, // 18
|
|
{ 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXEI8_V_MF8_MF2 }, // 19
|
|
{ 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXEI8_V_MF4_MF2 }, // 20
|
|
{ 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXEI8_V_MF2_MF2 }, // 21
|
|
{ 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXEI16_V_M1_M1 }, // 22
|
|
{ 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXEI16_V_M2_M1 }, // 23
|
|
{ 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXEI16_V_MF4_M1 }, // 24
|
|
{ 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXEI16_V_MF2_M1 }, // 25
|
|
{ 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXEI16_V_M1_M2 }, // 26
|
|
{ 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXEI16_V_M2_M2 }, // 27
|
|
{ 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXEI16_V_M4_M2 }, // 28
|
|
{ 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXEI16_V_MF2_M2 }, // 29
|
|
{ 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVSUXEI16_V_M1_M4 }, // 30
|
|
{ 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVSUXEI16_V_M2_M4 }, // 31
|
|
{ 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVSUXEI16_V_M4_M4 }, // 32
|
|
{ 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVSUXEI16_V_M8_M4 }, // 33
|
|
{ 0x0, 0x0, 0x4, 0x3, 0x1, PseudoVSUXEI16_V_M2_M8 }, // 34
|
|
{ 0x0, 0x0, 0x4, 0x3, 0x2, PseudoVSUXEI16_V_M4_M8 }, // 35
|
|
{ 0x0, 0x0, 0x4, 0x3, 0x3, PseudoVSUXEI16_V_M8_M8 }, // 36
|
|
{ 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXEI16_V_MF4_MF8 }, // 37
|
|
{ 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXEI16_V_MF4_MF4 }, // 38
|
|
{ 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXEI16_V_MF2_MF4 }, // 39
|
|
{ 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXEI16_V_M1_MF2 }, // 40
|
|
{ 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXEI16_V_MF4_MF2 }, // 41
|
|
{ 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXEI16_V_MF2_MF2 }, // 42
|
|
{ 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXEI32_V_M1_M1 }, // 43
|
|
{ 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXEI32_V_M2_M1 }, // 44
|
|
{ 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXEI32_V_M4_M1 }, // 45
|
|
{ 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXEI32_V_MF2_M1 }, // 46
|
|
{ 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXEI32_V_M1_M2 }, // 47
|
|
{ 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXEI32_V_M2_M2 }, // 48
|
|
{ 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXEI32_V_M4_M2 }, // 49
|
|
{ 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXEI32_V_M8_M2 }, // 50
|
|
{ 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVSUXEI32_V_M2_M4 }, // 51
|
|
{ 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVSUXEI32_V_M4_M4 }, // 52
|
|
{ 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVSUXEI32_V_M8_M4 }, // 53
|
|
{ 0x0, 0x0, 0x5, 0x3, 0x2, PseudoVSUXEI32_V_M4_M8 }, // 54
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{ 0x0, 0x0, 0x5, 0x3, 0x3, PseudoVSUXEI32_V_M8_M8 }, // 55
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{ 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXEI32_V_MF2_MF8 }, // 56
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{ 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXEI32_V_M1_MF4 }, // 57
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{ 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXEI32_V_MF2_MF4 }, // 58
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{ 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXEI32_V_M1_MF2 }, // 59
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{ 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXEI32_V_M2_MF2 }, // 60
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{ 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXEI32_V_MF2_MF2 }, // 61
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{ 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXEI64_V_M1_M1 }, // 62
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{ 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXEI64_V_M2_M1 }, // 63
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{ 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXEI64_V_M4_M1 }, // 64
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{ 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXEI64_V_M8_M1 }, // 65
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{ 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXEI64_V_M2_M2 }, // 66
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{ 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXEI64_V_M4_M2 }, // 67
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{ 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXEI64_V_M8_M2 }, // 68
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{ 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVSUXEI64_V_M4_M4 }, // 69
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{ 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVSUXEI64_V_M8_M4 }, // 70
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{ 0x0, 0x0, 0x6, 0x3, 0x3, PseudoVSUXEI64_V_M8_M8 }, // 71
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{ 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXEI64_V_M1_MF8 }, // 72
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{ 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXEI64_V_M1_MF4 }, // 73
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{ 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXEI64_V_M2_MF4 }, // 74
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{ 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXEI64_V_M1_MF2 }, // 75
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{ 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXEI64_V_M2_MF2 }, // 76
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{ 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXEI64_V_M4_MF2 }, // 77
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{ 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXEI8_V_M1_M1 }, // 78
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{ 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXEI8_V_MF8_M1 }, // 79
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{ 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXEI8_V_MF4_M1 }, // 80
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{ 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXEI8_V_MF2_M1 }, // 81
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{ 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXEI8_V_M1_M2 }, // 82
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{ 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXEI8_V_M2_M2 }, // 83
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{ 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXEI8_V_MF4_M2 }, // 84
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{ 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXEI8_V_MF2_M2 }, // 85
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{ 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVSOXEI8_V_M1_M4 }, // 86
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{ 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVSOXEI8_V_M2_M4 }, // 87
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{ 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVSOXEI8_V_M4_M4 }, // 88
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{ 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVSOXEI8_V_MF2_M4 }, // 89
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{ 0x0, 0x1, 0x3, 0x3, 0x0, PseudoVSOXEI8_V_M1_M8 }, // 90
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{ 0x0, 0x1, 0x3, 0x3, 0x1, PseudoVSOXEI8_V_M2_M8 }, // 91
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{ 0x0, 0x1, 0x3, 0x3, 0x2, PseudoVSOXEI8_V_M4_M8 }, // 92
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{ 0x0, 0x1, 0x3, 0x3, 0x3, PseudoVSOXEI8_V_M8_M8 }, // 93
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{ 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXEI8_V_MF8_MF8 }, // 94
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{ 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXEI8_V_MF8_MF4 }, // 95
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{ 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXEI8_V_MF4_MF4 }, // 96
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{ 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXEI8_V_MF8_MF2 }, // 97
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{ 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXEI8_V_MF4_MF2 }, // 98
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{ 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXEI8_V_MF2_MF2 }, // 99
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{ 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXEI16_V_M1_M1 }, // 100
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{ 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXEI16_V_M2_M1 }, // 101
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{ 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXEI16_V_MF4_M1 }, // 102
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{ 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXEI16_V_MF2_M1 }, // 103
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{ 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXEI16_V_M1_M2 }, // 104
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{ 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXEI16_V_M2_M2 }, // 105
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{ 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXEI16_V_M4_M2 }, // 106
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{ 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXEI16_V_MF2_M2 }, // 107
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{ 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVSOXEI16_V_M1_M4 }, // 108
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{ 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVSOXEI16_V_M2_M4 }, // 109
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{ 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVSOXEI16_V_M4_M4 }, // 110
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{ 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVSOXEI16_V_M8_M4 }, // 111
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{ 0x0, 0x1, 0x4, 0x3, 0x1, PseudoVSOXEI16_V_M2_M8 }, // 112
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|
{ 0x0, 0x1, 0x4, 0x3, 0x2, PseudoVSOXEI16_V_M4_M8 }, // 113
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|
{ 0x0, 0x1, 0x4, 0x3, 0x3, PseudoVSOXEI16_V_M8_M8 }, // 114
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|
{ 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXEI16_V_MF4_MF8 }, // 115
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{ 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXEI16_V_MF4_MF4 }, // 116
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{ 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXEI16_V_MF2_MF4 }, // 117
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|
{ 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXEI16_V_M1_MF2 }, // 118
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{ 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXEI16_V_MF4_MF2 }, // 119
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{ 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXEI16_V_MF2_MF2 }, // 120
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{ 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXEI32_V_M1_M1 }, // 121
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{ 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXEI32_V_M2_M1 }, // 122
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{ 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXEI32_V_M4_M1 }, // 123
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|
{ 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXEI32_V_MF2_M1 }, // 124
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|
{ 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXEI32_V_M1_M2 }, // 125
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|
{ 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXEI32_V_M2_M2 }, // 126
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|
{ 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXEI32_V_M4_M2 }, // 127
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|
{ 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXEI32_V_M8_M2 }, // 128
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|
{ 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVSOXEI32_V_M2_M4 }, // 129
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|
{ 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVSOXEI32_V_M4_M4 }, // 130
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|
{ 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVSOXEI32_V_M8_M4 }, // 131
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|
{ 0x0, 0x1, 0x5, 0x3, 0x2, PseudoVSOXEI32_V_M4_M8 }, // 132
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|
{ 0x0, 0x1, 0x5, 0x3, 0x3, PseudoVSOXEI32_V_M8_M8 }, // 133
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|
{ 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXEI32_V_MF2_MF8 }, // 134
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|
{ 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXEI32_V_M1_MF4 }, // 135
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|
{ 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXEI32_V_MF2_MF4 }, // 136
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|
{ 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXEI32_V_M1_MF2 }, // 137
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|
{ 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXEI32_V_M2_MF2 }, // 138
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|
{ 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXEI32_V_MF2_MF2 }, // 139
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|
{ 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXEI64_V_M1_M1 }, // 140
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|
{ 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXEI64_V_M2_M1 }, // 141
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|
{ 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXEI64_V_M4_M1 }, // 142
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|
{ 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXEI64_V_M8_M1 }, // 143
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|
{ 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXEI64_V_M2_M2 }, // 144
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|
{ 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXEI64_V_M4_M2 }, // 145
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|
{ 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXEI64_V_M8_M2 }, // 146
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|
{ 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVSOXEI64_V_M4_M4 }, // 147
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|
{ 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVSOXEI64_V_M8_M4 }, // 148
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|
{ 0x0, 0x1, 0x6, 0x3, 0x3, PseudoVSOXEI64_V_M8_M8 }, // 149
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|
{ 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXEI64_V_M1_MF8 }, // 150
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|
{ 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXEI64_V_M1_MF4 }, // 151
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|
{ 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXEI64_V_M2_MF4 }, // 152
|
|
{ 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXEI64_V_M1_MF2 }, // 153
|
|
{ 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXEI64_V_M2_MF2 }, // 154
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|
{ 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXEI64_V_M4_MF2 }, // 155
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|
{ 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXEI8_V_M1_M1_MASK }, // 156
|
|
{ 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXEI8_V_MF8_M1_MASK }, // 157
|
|
{ 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXEI8_V_MF4_M1_MASK }, // 158
|
|
{ 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXEI8_V_MF2_M1_MASK }, // 159
|
|
{ 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXEI8_V_M1_M2_MASK }, // 160
|
|
{ 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXEI8_V_M2_M2_MASK }, // 161
|
|
{ 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXEI8_V_MF4_M2_MASK }, // 162
|
|
{ 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXEI8_V_MF2_M2_MASK }, // 163
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVSUXEI8_V_M1_M4_MASK }, // 164
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVSUXEI8_V_M2_M4_MASK }, // 165
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVSUXEI8_V_M4_M4_MASK }, // 166
|
|
{ 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVSUXEI8_V_MF2_M4_MASK }, // 167
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x0, PseudoVSUXEI8_V_M1_M8_MASK }, // 168
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x1, PseudoVSUXEI8_V_M2_M8_MASK }, // 169
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x2, PseudoVSUXEI8_V_M4_M8_MASK }, // 170
|
|
{ 0x1, 0x0, 0x3, 0x3, 0x3, PseudoVSUXEI8_V_M8_M8_MASK }, // 171
|
|
{ 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXEI8_V_MF8_MF8_MASK }, // 172
|
|
{ 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXEI8_V_MF8_MF4_MASK }, // 173
|
|
{ 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXEI8_V_MF4_MF4_MASK }, // 174
|
|
{ 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXEI8_V_MF8_MF2_MASK }, // 175
|
|
{ 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXEI8_V_MF4_MF2_MASK }, // 176
|
|
{ 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXEI8_V_MF2_MF2_MASK }, // 177
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXEI16_V_M1_M1_MASK }, // 178
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXEI16_V_M2_M1_MASK }, // 179
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXEI16_V_MF4_M1_MASK }, // 180
|
|
{ 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXEI16_V_MF2_M1_MASK }, // 181
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXEI16_V_M1_M2_MASK }, // 182
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXEI16_V_M2_M2_MASK }, // 183
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXEI16_V_M4_M2_MASK }, // 184
|
|
{ 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXEI16_V_MF2_M2_MASK }, // 185
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVSUXEI16_V_M1_M4_MASK }, // 186
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVSUXEI16_V_M2_M4_MASK }, // 187
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVSUXEI16_V_M4_M4_MASK }, // 188
|
|
{ 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVSUXEI16_V_M8_M4_MASK }, // 189
|
|
{ 0x1, 0x0, 0x4, 0x3, 0x1, PseudoVSUXEI16_V_M2_M8_MASK }, // 190
|
|
{ 0x1, 0x0, 0x4, 0x3, 0x2, PseudoVSUXEI16_V_M4_M8_MASK }, // 191
|
|
{ 0x1, 0x0, 0x4, 0x3, 0x3, PseudoVSUXEI16_V_M8_M8_MASK }, // 192
|
|
{ 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXEI16_V_MF4_MF8_MASK }, // 193
|
|
{ 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXEI16_V_MF4_MF4_MASK }, // 194
|
|
{ 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXEI16_V_MF2_MF4_MASK }, // 195
|
|
{ 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXEI16_V_M1_MF2_MASK }, // 196
|
|
{ 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXEI16_V_MF4_MF2_MASK }, // 197
|
|
{ 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXEI16_V_MF2_MF2_MASK }, // 198
|
|
{ 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXEI32_V_M1_M1_MASK }, // 199
|
|
{ 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXEI32_V_M2_M1_MASK }, // 200
|
|
{ 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXEI32_V_M4_M1_MASK }, // 201
|
|
{ 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXEI32_V_MF2_M1_MASK }, // 202
|
|
{ 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXEI32_V_M1_M2_MASK }, // 203
|
|
{ 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXEI32_V_M2_M2_MASK }, // 204
|
|
{ 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXEI32_V_M4_M2_MASK }, // 205
|
|
{ 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXEI32_V_M8_M2_MASK }, // 206
|
|
{ 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVSUXEI32_V_M2_M4_MASK }, // 207
|
|
{ 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVSUXEI32_V_M4_M4_MASK }, // 208
|
|
{ 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVSUXEI32_V_M8_M4_MASK }, // 209
|
|
{ 0x1, 0x0, 0x5, 0x3, 0x2, PseudoVSUXEI32_V_M4_M8_MASK }, // 210
|
|
{ 0x1, 0x0, 0x5, 0x3, 0x3, PseudoVSUXEI32_V_M8_M8_MASK }, // 211
|
|
{ 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXEI32_V_MF2_MF8_MASK }, // 212
|
|
{ 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXEI32_V_M1_MF4_MASK }, // 213
|
|
{ 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXEI32_V_MF2_MF4_MASK }, // 214
|
|
{ 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXEI32_V_M1_MF2_MASK }, // 215
|
|
{ 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXEI32_V_M2_MF2_MASK }, // 216
|
|
{ 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXEI32_V_MF2_MF2_MASK }, // 217
|
|
{ 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXEI64_V_M1_M1_MASK }, // 218
|
|
{ 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXEI64_V_M2_M1_MASK }, // 219
|
|
{ 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXEI64_V_M4_M1_MASK }, // 220
|
|
{ 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXEI64_V_M8_M1_MASK }, // 221
|
|
{ 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXEI64_V_M2_M2_MASK }, // 222
|
|
{ 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXEI64_V_M4_M2_MASK }, // 223
|
|
{ 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXEI64_V_M8_M2_MASK }, // 224
|
|
{ 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVSUXEI64_V_M4_M4_MASK }, // 225
|
|
{ 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVSUXEI64_V_M8_M4_MASK }, // 226
|
|
{ 0x1, 0x0, 0x6, 0x3, 0x3, PseudoVSUXEI64_V_M8_M8_MASK }, // 227
|
|
{ 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXEI64_V_M1_MF8_MASK }, // 228
|
|
{ 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXEI64_V_M1_MF4_MASK }, // 229
|
|
{ 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXEI64_V_M2_MF4_MASK }, // 230
|
|
{ 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXEI64_V_M1_MF2_MASK }, // 231
|
|
{ 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXEI64_V_M2_MF2_MASK }, // 232
|
|
{ 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXEI64_V_M4_MF2_MASK }, // 233
|
|
{ 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXEI8_V_M1_M1_MASK }, // 234
|
|
{ 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXEI8_V_MF8_M1_MASK }, // 235
|
|
{ 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXEI8_V_MF4_M1_MASK }, // 236
|
|
{ 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXEI8_V_MF2_M1_MASK }, // 237
|
|
{ 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXEI8_V_M1_M2_MASK }, // 238
|
|
{ 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXEI8_V_M2_M2_MASK }, // 239
|
|
{ 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXEI8_V_MF4_M2_MASK }, // 240
|
|
{ 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXEI8_V_MF2_M2_MASK }, // 241
|
|
{ 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVSOXEI8_V_M1_M4_MASK }, // 242
|
|
{ 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVSOXEI8_V_M2_M4_MASK }, // 243
|
|
{ 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVSOXEI8_V_M4_M4_MASK }, // 244
|
|
{ 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVSOXEI8_V_MF2_M4_MASK }, // 245
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x0, PseudoVSOXEI8_V_M1_M8_MASK }, // 246
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x1, PseudoVSOXEI8_V_M2_M8_MASK }, // 247
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x2, PseudoVSOXEI8_V_M4_M8_MASK }, // 248
|
|
{ 0x1, 0x1, 0x3, 0x3, 0x3, PseudoVSOXEI8_V_M8_M8_MASK }, // 249
|
|
{ 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXEI8_V_MF8_MF8_MASK }, // 250
|
|
{ 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXEI8_V_MF8_MF4_MASK }, // 251
|
|
{ 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXEI8_V_MF4_MF4_MASK }, // 252
|
|
{ 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXEI8_V_MF8_MF2_MASK }, // 253
|
|
{ 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXEI8_V_MF4_MF2_MASK }, // 254
|
|
{ 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXEI8_V_MF2_MF2_MASK }, // 255
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXEI16_V_M1_M1_MASK }, // 256
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXEI16_V_M2_M1_MASK }, // 257
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXEI16_V_MF4_M1_MASK }, // 258
|
|
{ 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXEI16_V_MF2_M1_MASK }, // 259
|
|
{ 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXEI16_V_M1_M2_MASK }, // 260
|
|
{ 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXEI16_V_M2_M2_MASK }, // 261
|
|
{ 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXEI16_V_M4_M2_MASK }, // 262
|
|
{ 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXEI16_V_MF2_M2_MASK }, // 263
|
|
{ 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVSOXEI16_V_M1_M4_MASK }, // 264
|
|
{ 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVSOXEI16_V_M2_M4_MASK }, // 265
|
|
{ 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVSOXEI16_V_M4_M4_MASK }, // 266
|
|
{ 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVSOXEI16_V_M8_M4_MASK }, // 267
|
|
{ 0x1, 0x1, 0x4, 0x3, 0x1, PseudoVSOXEI16_V_M2_M8_MASK }, // 268
|
|
{ 0x1, 0x1, 0x4, 0x3, 0x2, PseudoVSOXEI16_V_M4_M8_MASK }, // 269
|
|
{ 0x1, 0x1, 0x4, 0x3, 0x3, PseudoVSOXEI16_V_M8_M8_MASK }, // 270
|
|
{ 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXEI16_V_MF4_MF8_MASK }, // 271
|
|
{ 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXEI16_V_MF4_MF4_MASK }, // 272
|
|
{ 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXEI16_V_MF2_MF4_MASK }, // 273
|
|
{ 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXEI16_V_M1_MF2_MASK }, // 274
|
|
{ 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXEI16_V_MF4_MF2_MASK }, // 275
|
|
{ 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXEI16_V_MF2_MF2_MASK }, // 276
|
|
{ 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXEI32_V_M1_M1_MASK }, // 277
|
|
{ 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXEI32_V_M2_M1_MASK }, // 278
|
|
{ 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXEI32_V_M4_M1_MASK }, // 279
|
|
{ 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXEI32_V_MF2_M1_MASK }, // 280
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXEI32_V_M1_M2_MASK }, // 281
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXEI32_V_M2_M2_MASK }, // 282
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXEI32_V_M4_M2_MASK }, // 283
|
|
{ 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXEI32_V_M8_M2_MASK }, // 284
|
|
{ 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVSOXEI32_V_M2_M4_MASK }, // 285
|
|
{ 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVSOXEI32_V_M4_M4_MASK }, // 286
|
|
{ 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVSOXEI32_V_M8_M4_MASK }, // 287
|
|
{ 0x1, 0x1, 0x5, 0x3, 0x2, PseudoVSOXEI32_V_M4_M8_MASK }, // 288
|
|
{ 0x1, 0x1, 0x5, 0x3, 0x3, PseudoVSOXEI32_V_M8_M8_MASK }, // 289
|
|
{ 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXEI32_V_MF2_MF8_MASK }, // 290
|
|
{ 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXEI32_V_M1_MF4_MASK }, // 291
|
|
{ 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXEI32_V_MF2_MF4_MASK }, // 292
|
|
{ 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXEI32_V_M1_MF2_MASK }, // 293
|
|
{ 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXEI32_V_M2_MF2_MASK }, // 294
|
|
{ 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXEI32_V_MF2_MF2_MASK }, // 295
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXEI64_V_M1_M1_MASK }, // 296
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXEI64_V_M2_M1_MASK }, // 297
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXEI64_V_M4_M1_MASK }, // 298
|
|
{ 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXEI64_V_M8_M1_MASK }, // 299
|
|
{ 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXEI64_V_M2_M2_MASK }, // 300
|
|
{ 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXEI64_V_M4_M2_MASK }, // 301
|
|
{ 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXEI64_V_M8_M2_MASK }, // 302
|
|
{ 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVSOXEI64_V_M4_M4_MASK }, // 303
|
|
{ 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVSOXEI64_V_M8_M4_MASK }, // 304
|
|
{ 0x1, 0x1, 0x6, 0x3, 0x3, PseudoVSOXEI64_V_M8_M8_MASK }, // 305
|
|
{ 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXEI64_V_M1_MF8_MASK }, // 306
|
|
{ 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXEI64_V_M1_MF4_MASK }, // 307
|
|
{ 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXEI64_V_M2_MF4_MASK }, // 308
|
|
{ 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXEI64_V_M1_MF2_MASK }, // 309
|
|
{ 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXEI64_V_M2_MF2_MASK }, // 310
|
|
{ 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXEI64_V_M4_MF2_MASK }, // 311
|
|
};
|
|
|
|
const RISCV_VLX_VSXPseudo *RISCV_getVSXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) {
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedOrderedLog2SEWLMULIndexLMUL);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &RISCVVSXTable[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef GET_SysRegsList_IMPL
|
|
static const RISCV_SysReg SysRegsList[] = {
|
|
{ "fflags", { .raw_val = RISCV_SYSREG_FFLAGS }, "fflags", { .raw_val = RISCV_SYSREG_FFLAGS }, "", 0x1, {0} , false }, // 0
|
|
{ "frm", { .raw_val = RISCV_SYSREG_FRM }, "frm", { .raw_val = RISCV_SYSREG_FRM }, "", 0x2, {0} , false }, // 1
|
|
{ "fcsr", { .raw_val = RISCV_SYSREG_FCSR }, "fcsr", { .raw_val = RISCV_SYSREG_FCSR }, "", 0x3, {0} , false }, // 2
|
|
{ "vstart", { .raw_val = RISCV_SYSREG_VSTART }, "vstart", { .raw_val = RISCV_SYSREG_VSTART }, "", 0x8, {0} , false }, // 3
|
|
{ "vxsat", { .raw_val = RISCV_SYSREG_VXSAT }, "vxsat", { .raw_val = RISCV_SYSREG_VXSAT }, "", 0x9, {0} , false }, // 4
|
|
{ "vxrm", { .raw_val = RISCV_SYSREG_VXRM }, "vxrm", { .raw_val = RISCV_SYSREG_VXRM }, "", 0xA, {0} , false }, // 5
|
|
{ "vcsr", { .raw_val = RISCV_SYSREG_VCSR }, "vcsr", { .raw_val = RISCV_SYSREG_VCSR }, "", 0xF, {0} , false }, // 6
|
|
{ "seed", { .raw_val = RISCV_SYSREG_SEED }, "seed", { .raw_val = RISCV_SYSREG_SEED }, "", 0x15, {0} , false }, // 7
|
|
{ "jvt", { .raw_val = RISCV_SYSREG_JVT }, "jvt", { .raw_val = RISCV_SYSREG_JVT }, "", 0x17, {0} , false }, // 8
|
|
{ "sstatus", { .raw_val = RISCV_SYSREG_SSTATUS }, "sstatus", { .raw_val = RISCV_SYSREG_SSTATUS }, "", 0x100, {0} , false }, // 9
|
|
{ "sie", { .raw_val = RISCV_SYSREG_SIE }, "sie", { .raw_val = RISCV_SYSREG_SIE }, "", 0x104, {0} , false }, // 10
|
|
{ "stvec", { .raw_val = RISCV_SYSREG_STVEC }, "stvec", { .raw_val = RISCV_SYSREG_STVEC }, "", 0x105, {0} , false }, // 11
|
|
{ "scounteren", { .raw_val = RISCV_SYSREG_SCOUNTEREN }, "scounteren", { .raw_val = RISCV_SYSREG_SCOUNTEREN }, "", 0x106, {0} , false }, // 12
|
|
{ "senvcfg", { .raw_val = RISCV_SYSREG_SENVCFG }, "senvcfg", { .raw_val = RISCV_SYSREG_SENVCFG }, "", 0x10A, {0} , false }, // 13
|
|
{ "sstateen0", { .raw_val = RISCV_SYSREG_SSTATEEN0 }, "sstateen0", { .raw_val = RISCV_SYSREG_SSTATEEN0 }, "", 0x10C, {0} , false }, // 14
|
|
{ "sstateen1", { .raw_val = RISCV_SYSREG_SSTATEEN1 }, "sstateen1", { .raw_val = RISCV_SYSREG_SSTATEEN1 }, "", 0x10D, {0} , false }, // 15
|
|
{ "sstateen2", { .raw_val = RISCV_SYSREG_SSTATEEN2 }, "sstateen2", { .raw_val = RISCV_SYSREG_SSTATEEN2 }, "", 0x10E, {0} , false }, // 16
|
|
{ "sstateen3", { .raw_val = RISCV_SYSREG_SSTATEEN3 }, "sstateen3", { .raw_val = RISCV_SYSREG_SSTATEEN3 }, "", 0x10F, {0} , false }, // 17
|
|
{ "sieh", { .raw_val = RISCV_SYSREG_SIEH }, "sieh", { .raw_val = RISCV_SYSREG_SIEH }, "", 0x114, {0} , true }, // 18
|
|
{ "sscratch", { .raw_val = RISCV_SYSREG_SSCRATCH }, "sscratch", { .raw_val = RISCV_SYSREG_SSCRATCH }, "", 0x140, {0} , false }, // 19
|
|
{ "sepc", { .raw_val = RISCV_SYSREG_SEPC }, "sepc", { .raw_val = RISCV_SYSREG_SEPC }, "", 0x141, {0} , false }, // 20
|
|
{ "scause", { .raw_val = RISCV_SYSREG_SCAUSE }, "scause", { .raw_val = RISCV_SYSREG_SCAUSE }, "", 0x142, {0} , false }, // 21
|
|
{ "stval", { .raw_val = RISCV_SYSREG_STVAL }, "stval", { .raw_val = RISCV_SYSREG_STVAL }, "sbadaddr", 0x143, {0} , false }, // 22
|
|
{ "sip", { .raw_val = RISCV_SYSREG_SIP }, "sip", { .raw_val = RISCV_SYSREG_SIP }, "", 0x144, {0} , false }, // 23
|
|
{ "stimecmp", { .raw_val = RISCV_SYSREG_STIMECMP }, "stimecmp", { .raw_val = RISCV_SYSREG_STIMECMP }, "", 0x14D, {0} , false }, // 24
|
|
{ "siselect", { .raw_val = RISCV_SYSREG_SISELECT }, "siselect", { .raw_val = RISCV_SYSREG_SISELECT }, "", 0x150, {0} , false }, // 25
|
|
{ "sireg", { .raw_val = RISCV_SYSREG_SIREG }, "sireg", { .raw_val = RISCV_SYSREG_SIREG }, "", 0x151, {0} , false }, // 26
|
|
{ "siph", { .raw_val = RISCV_SYSREG_SIPH }, "siph", { .raw_val = RISCV_SYSREG_SIPH }, "", 0x154, {0} , true }, // 27
|
|
{ "stopei", { .raw_val = RISCV_SYSREG_STOPEI }, "stopei", { .raw_val = RISCV_SYSREG_STOPEI }, "", 0x15C, {0} , false }, // 28
|
|
{ "stimecmph", { .raw_val = RISCV_SYSREG_STIMECMPH }, "stimecmph", { .raw_val = RISCV_SYSREG_STIMECMPH }, "", 0x15D, {0} , true }, // 29
|
|
{ "satp", { .raw_val = RISCV_SYSREG_SATP }, "satp", { .raw_val = RISCV_SYSREG_SATP }, "sptbr", 0x180, {0} , false }, // 30
|
|
{ "vsstatus", { .raw_val = RISCV_SYSREG_VSSTATUS }, "vsstatus", { .raw_val = RISCV_SYSREG_VSSTATUS }, "", 0x200, {0} , false }, // 31
|
|
{ "vsie", { .raw_val = RISCV_SYSREG_VSIE }, "vsie", { .raw_val = RISCV_SYSREG_VSIE }, "", 0x204, {0} , false }, // 32
|
|
{ "vstvec", { .raw_val = RISCV_SYSREG_VSTVEC }, "vstvec", { .raw_val = RISCV_SYSREG_VSTVEC }, "", 0x205, {0} , false }, // 33
|
|
{ "vsieh", { .raw_val = RISCV_SYSREG_VSIEH }, "vsieh", { .raw_val = RISCV_SYSREG_VSIEH }, "", 0x214, {0} , true }, // 34
|
|
{ "vsscratch", { .raw_val = RISCV_SYSREG_VSSCRATCH }, "vsscratch", { .raw_val = RISCV_SYSREG_VSSCRATCH }, "", 0x240, {0} , false }, // 35
|
|
{ "vsepc", { .raw_val = RISCV_SYSREG_VSEPC }, "vsepc", { .raw_val = RISCV_SYSREG_VSEPC }, "", 0x241, {0} , false }, // 36
|
|
{ "vscause", { .raw_val = RISCV_SYSREG_VSCAUSE }, "vscause", { .raw_val = RISCV_SYSREG_VSCAUSE }, "", 0x242, {0} , false }, // 37
|
|
{ "vstval", { .raw_val = RISCV_SYSREG_VSTVAL }, "vstval", { .raw_val = RISCV_SYSREG_VSTVAL }, "", 0x243, {0} , false }, // 38
|
|
{ "vsip", { .raw_val = RISCV_SYSREG_VSIP }, "vsip", { .raw_val = RISCV_SYSREG_VSIP }, "", 0x244, {0} , false }, // 39
|
|
{ "vstimecmp", { .raw_val = RISCV_SYSREG_VSTIMECMP }, "vstimecmp", { .raw_val = RISCV_SYSREG_VSTIMECMP }, "", 0x24D, {0} , false }, // 40
|
|
{ "vsiselect", { .raw_val = RISCV_SYSREG_VSISELECT }, "vsiselect", { .raw_val = RISCV_SYSREG_VSISELECT }, "", 0x250, {0} , false }, // 41
|
|
{ "vsireg", { .raw_val = RISCV_SYSREG_VSIREG }, "vsireg", { .raw_val = RISCV_SYSREG_VSIREG }, "", 0x251, {0} , false }, // 42
|
|
{ "vsiph", { .raw_val = RISCV_SYSREG_VSIPH }, "vsiph", { .raw_val = RISCV_SYSREG_VSIPH }, "", 0x254, {0} , true }, // 43
|
|
{ "vstopei", { .raw_val = RISCV_SYSREG_VSTOPEI }, "vstopei", { .raw_val = RISCV_SYSREG_VSTOPEI }, "", 0x25C, {0} , false }, // 44
|
|
{ "vstimecmph", { .raw_val = RISCV_SYSREG_VSTIMECMPH }, "vstimecmph", { .raw_val = RISCV_SYSREG_VSTIMECMPH }, "", 0x25D, {0} , true }, // 45
|
|
{ "vsatp", { .raw_val = RISCV_SYSREG_VSATP }, "vsatp", { .raw_val = RISCV_SYSREG_VSATP }, "", 0x280, {0} , false }, // 46
|
|
{ "mstatus", { .raw_val = RISCV_SYSREG_MSTATUS }, "mstatus", { .raw_val = RISCV_SYSREG_MSTATUS }, "", 0x300, {0} , false }, // 47
|
|
{ "misa", { .raw_val = RISCV_SYSREG_MISA }, "misa", { .raw_val = RISCV_SYSREG_MISA }, "", 0x301, {0} , false }, // 48
|
|
{ "medeleg", { .raw_val = RISCV_SYSREG_MEDELEG }, "medeleg", { .raw_val = RISCV_SYSREG_MEDELEG }, "", 0x302, {0} , false }, // 49
|
|
{ "mideleg", { .raw_val = RISCV_SYSREG_MIDELEG }, "mideleg", { .raw_val = RISCV_SYSREG_MIDELEG }, "", 0x303, {0} , false }, // 50
|
|
{ "mie", { .raw_val = RISCV_SYSREG_MIE }, "mie", { .raw_val = RISCV_SYSREG_MIE }, "", 0x304, {0} , false }, // 51
|
|
{ "mtvec", { .raw_val = RISCV_SYSREG_MTVEC }, "mtvec", { .raw_val = RISCV_SYSREG_MTVEC }, "", 0x305, {0} , false }, // 52
|
|
{ "mcounteren", { .raw_val = RISCV_SYSREG_MCOUNTEREN }, "mcounteren", { .raw_val = RISCV_SYSREG_MCOUNTEREN }, "", 0x306, {0} , false }, // 53
|
|
{ "mvien", { .raw_val = RISCV_SYSREG_MVIEN }, "mvien", { .raw_val = RISCV_SYSREG_MVIEN }, "", 0x308, {0} , false }, // 54
|
|
{ "mvip", { .raw_val = RISCV_SYSREG_MVIP }, "mvip", { .raw_val = RISCV_SYSREG_MVIP }, "", 0x309, {0} , false }, // 55
|
|
{ "menvcfg", { .raw_val = RISCV_SYSREG_MENVCFG }, "menvcfg", { .raw_val = RISCV_SYSREG_MENVCFG }, "", 0x30A, {0} , false }, // 56
|
|
{ "mstateen0", { .raw_val = RISCV_SYSREG_MSTATEEN0 }, "mstateen0", { .raw_val = RISCV_SYSREG_MSTATEEN0 }, "", 0x30C, {0} , false }, // 57
|
|
{ "mstateen1", { .raw_val = RISCV_SYSREG_MSTATEEN1 }, "mstateen1", { .raw_val = RISCV_SYSREG_MSTATEEN1 }, "", 0x30D, {0} , false }, // 58
|
|
{ "mstateen2", { .raw_val = RISCV_SYSREG_MSTATEEN2 }, "mstateen2", { .raw_val = RISCV_SYSREG_MSTATEEN2 }, "", 0x30E, {0} , false }, // 59
|
|
{ "mstateen3", { .raw_val = RISCV_SYSREG_MSTATEEN3 }, "mstateen3", { .raw_val = RISCV_SYSREG_MSTATEEN3 }, "", 0x30F, {0} , false }, // 60
|
|
{ "mstatush", { .raw_val = RISCV_SYSREG_MSTATUSH }, "mstatush", { .raw_val = RISCV_SYSREG_MSTATUSH }, "", 0x310, {0} , true }, // 61
|
|
{ "midelegh", { .raw_val = RISCV_SYSREG_MIDELEGH }, "midelegh", { .raw_val = RISCV_SYSREG_MIDELEGH }, "", 0x313, {0} , true }, // 62
|
|
{ "mieh", { .raw_val = RISCV_SYSREG_MIEH }, "mieh", { .raw_val = RISCV_SYSREG_MIEH }, "", 0x314, {0} , true }, // 63
|
|
{ "mvienh", { .raw_val = RISCV_SYSREG_MVIENH }, "mvienh", { .raw_val = RISCV_SYSREG_MVIENH }, "", 0x318, {0} , true }, // 64
|
|
{ "mviph", { .raw_val = RISCV_SYSREG_MVIPH }, "mviph", { .raw_val = RISCV_SYSREG_MVIPH }, "", 0x319, {0} , true }, // 65
|
|
{ "menvcfgh", { .raw_val = RISCV_SYSREG_MENVCFGH }, "menvcfgh", { .raw_val = RISCV_SYSREG_MENVCFGH }, "", 0x31A, {0} , true }, // 66
|
|
{ "mstateen0h", { .raw_val = RISCV_SYSREG_MSTATEEN0H }, "mstateen0h", { .raw_val = RISCV_SYSREG_MSTATEEN0H }, "", 0x31C, {0} , true }, // 67
|
|
{ "mstateen1h", { .raw_val = RISCV_SYSREG_MSTATEEN1H }, "mstateen1h", { .raw_val = RISCV_SYSREG_MSTATEEN1H }, "", 0x31D, {0} , true }, // 68
|
|
{ "mstateen2h", { .raw_val = RISCV_SYSREG_MSTATEEN2H }, "mstateen2h", { .raw_val = RISCV_SYSREG_MSTATEEN2H }, "", 0x31E, {0} , true }, // 69
|
|
{ "mstateen3h", { .raw_val = RISCV_SYSREG_MSTATEEN3H }, "mstateen3h", { .raw_val = RISCV_SYSREG_MSTATEEN3H }, "", 0x31F, {0} , true }, // 70
|
|
{ "mcountinhibit", { .raw_val = RISCV_SYSREG_MCOUNTINHIBIT }, "mucounteren", { .raw_val = RISCV_SYSREG_MUCOUNTEREN }, "", 0x320, {0} , false }, // 71
|
|
{ "mhpmevent3", { .raw_val = RISCV_SYSREG_MHPMEVENT3 }, "mhpmevent3", { .raw_val = RISCV_SYSREG_MHPMEVENT3 }, "", 0x323, {0} , false }, // 72
|
|
{ "mhpmevent4", { .raw_val = RISCV_SYSREG_MHPMEVENT4 }, "mhpmevent4", { .raw_val = RISCV_SYSREG_MHPMEVENT4 }, "", 0x324, {0} , false }, // 73
|
|
{ "mhpmevent5", { .raw_val = RISCV_SYSREG_MHPMEVENT5 }, "mhpmevent5", { .raw_val = RISCV_SYSREG_MHPMEVENT5 }, "", 0x325, {0} , false }, // 74
|
|
{ "mhpmevent6", { .raw_val = RISCV_SYSREG_MHPMEVENT6 }, "mhpmevent6", { .raw_val = RISCV_SYSREG_MHPMEVENT6 }, "", 0x326, {0} , false }, // 75
|
|
{ "mhpmevent7", { .raw_val = RISCV_SYSREG_MHPMEVENT7 }, "mhpmevent7", { .raw_val = RISCV_SYSREG_MHPMEVENT7 }, "", 0x327, {0} , false }, // 76
|
|
{ "mhpmevent8", { .raw_val = RISCV_SYSREG_MHPMEVENT8 }, "mhpmevent8", { .raw_val = RISCV_SYSREG_MHPMEVENT8 }, "", 0x328, {0} , false }, // 77
|
|
{ "mhpmevent9", { .raw_val = RISCV_SYSREG_MHPMEVENT9 }, "mhpmevent9", { .raw_val = RISCV_SYSREG_MHPMEVENT9 }, "", 0x329, {0} , false }, // 78
|
|
{ "mhpmevent10", { .raw_val = RISCV_SYSREG_MHPMEVENT10 }, "mhpmevent10", { .raw_val = RISCV_SYSREG_MHPMEVENT10 }, "", 0x32A, {0} , false }, // 79
|
|
{ "mhpmevent11", { .raw_val = RISCV_SYSREG_MHPMEVENT11 }, "mhpmevent11", { .raw_val = RISCV_SYSREG_MHPMEVENT11 }, "", 0x32B, {0} , false }, // 80
|
|
{ "mhpmevent12", { .raw_val = RISCV_SYSREG_MHPMEVENT12 }, "mhpmevent12", { .raw_val = RISCV_SYSREG_MHPMEVENT12 }, "", 0x32C, {0} , false }, // 81
|
|
{ "mhpmevent13", { .raw_val = RISCV_SYSREG_MHPMEVENT13 }, "mhpmevent13", { .raw_val = RISCV_SYSREG_MHPMEVENT13 }, "", 0x32D, {0} , false }, // 82
|
|
{ "mhpmevent14", { .raw_val = RISCV_SYSREG_MHPMEVENT14 }, "mhpmevent14", { .raw_val = RISCV_SYSREG_MHPMEVENT14 }, "", 0x32E, {0} , false }, // 83
|
|
{ "mhpmevent15", { .raw_val = RISCV_SYSREG_MHPMEVENT15 }, "mhpmevent15", { .raw_val = RISCV_SYSREG_MHPMEVENT15 }, "", 0x32F, {0} , false }, // 84
|
|
{ "mhpmevent16", { .raw_val = RISCV_SYSREG_MHPMEVENT16 }, "mhpmevent16", { .raw_val = RISCV_SYSREG_MHPMEVENT16 }, "", 0x330, {0} , false }, // 85
|
|
{ "mhpmevent17", { .raw_val = RISCV_SYSREG_MHPMEVENT17 }, "mhpmevent17", { .raw_val = RISCV_SYSREG_MHPMEVENT17 }, "", 0x331, {0} , false }, // 86
|
|
{ "mhpmevent18", { .raw_val = RISCV_SYSREG_MHPMEVENT18 }, "mhpmevent18", { .raw_val = RISCV_SYSREG_MHPMEVENT18 }, "", 0x332, {0} , false }, // 87
|
|
{ "mhpmevent19", { .raw_val = RISCV_SYSREG_MHPMEVENT19 }, "mhpmevent19", { .raw_val = RISCV_SYSREG_MHPMEVENT19 }, "", 0x333, {0} , false }, // 88
|
|
{ "mhpmevent20", { .raw_val = RISCV_SYSREG_MHPMEVENT20 }, "mhpmevent20", { .raw_val = RISCV_SYSREG_MHPMEVENT20 }, "", 0x334, {0} , false }, // 89
|
|
{ "mhpmevent21", { .raw_val = RISCV_SYSREG_MHPMEVENT21 }, "mhpmevent21", { .raw_val = RISCV_SYSREG_MHPMEVENT21 }, "", 0x335, {0} , false }, // 90
|
|
{ "mhpmevent22", { .raw_val = RISCV_SYSREG_MHPMEVENT22 }, "mhpmevent22", { .raw_val = RISCV_SYSREG_MHPMEVENT22 }, "", 0x336, {0} , false }, // 91
|
|
{ "mhpmevent23", { .raw_val = RISCV_SYSREG_MHPMEVENT23 }, "mhpmevent23", { .raw_val = RISCV_SYSREG_MHPMEVENT23 }, "", 0x337, {0} , false }, // 92
|
|
{ "mhpmevent24", { .raw_val = RISCV_SYSREG_MHPMEVENT24 }, "mhpmevent24", { .raw_val = RISCV_SYSREG_MHPMEVENT24 }, "", 0x338, {0} , false }, // 93
|
|
{ "mhpmevent25", { .raw_val = RISCV_SYSREG_MHPMEVENT25 }, "mhpmevent25", { .raw_val = RISCV_SYSREG_MHPMEVENT25 }, "", 0x339, {0} , false }, // 94
|
|
{ "mhpmevent26", { .raw_val = RISCV_SYSREG_MHPMEVENT26 }, "mhpmevent26", { .raw_val = RISCV_SYSREG_MHPMEVENT26 }, "", 0x33A, {0} , false }, // 95
|
|
{ "mhpmevent27", { .raw_val = RISCV_SYSREG_MHPMEVENT27 }, "mhpmevent27", { .raw_val = RISCV_SYSREG_MHPMEVENT27 }, "", 0x33B, {0} , false }, // 96
|
|
{ "mhpmevent28", { .raw_val = RISCV_SYSREG_MHPMEVENT28 }, "mhpmevent28", { .raw_val = RISCV_SYSREG_MHPMEVENT28 }, "", 0x33C, {0} , false }, // 97
|
|
{ "mhpmevent29", { .raw_val = RISCV_SYSREG_MHPMEVENT29 }, "mhpmevent29", { .raw_val = RISCV_SYSREG_MHPMEVENT29 }, "", 0x33D, {0} , false }, // 98
|
|
{ "mhpmevent30", { .raw_val = RISCV_SYSREG_MHPMEVENT30 }, "mhpmevent30", { .raw_val = RISCV_SYSREG_MHPMEVENT30 }, "", 0x33E, {0} , false }, // 99
|
|
{ "mhpmevent31", { .raw_val = RISCV_SYSREG_MHPMEVENT31 }, "mhpmevent31", { .raw_val = RISCV_SYSREG_MHPMEVENT31 }, "", 0x33F, {0} , false }, // 100
|
|
{ "mscratch", { .raw_val = RISCV_SYSREG_MSCRATCH }, "mscratch", { .raw_val = RISCV_SYSREG_MSCRATCH }, "", 0x340, {0} , false }, // 101
|
|
{ "mepc", { .raw_val = RISCV_SYSREG_MEPC }, "mepc", { .raw_val = RISCV_SYSREG_MEPC }, "", 0x341, {0} , false }, // 102
|
|
{ "mcause", { .raw_val = RISCV_SYSREG_MCAUSE }, "mcause", { .raw_val = RISCV_SYSREG_MCAUSE }, "", 0x342, {0} , false }, // 103
|
|
{ "mtval", { .raw_val = RISCV_SYSREG_MTVAL }, "mtval", { .raw_val = RISCV_SYSREG_MTVAL }, "mbadaddr", 0x343, {0} , false }, // 104
|
|
{ "mip", { .raw_val = RISCV_SYSREG_MIP }, "mip", { .raw_val = RISCV_SYSREG_MIP }, "", 0x344, {0} , false }, // 105
|
|
{ "mtinst", { .raw_val = RISCV_SYSREG_MTINST }, "mtinst", { .raw_val = RISCV_SYSREG_MTINST }, "", 0x34A, {0} , false }, // 106
|
|
{ "mtval2", { .raw_val = RISCV_SYSREG_MTVAL2 }, "mtval2", { .raw_val = RISCV_SYSREG_MTVAL2 }, "", 0x34B, {0} , false }, // 107
|
|
{ "miselect", { .raw_val = RISCV_SYSREG_MISELECT }, "miselect", { .raw_val = RISCV_SYSREG_MISELECT }, "", 0x350, {0} , false }, // 108
|
|
{ "mireg", { .raw_val = RISCV_SYSREG_MIREG }, "mireg", { .raw_val = RISCV_SYSREG_MIREG }, "", 0x351, {0} , false }, // 109
|
|
{ "miph", { .raw_val = RISCV_SYSREG_MIPH }, "miph", { .raw_val = RISCV_SYSREG_MIPH }, "", 0x354, {0} , true }, // 110
|
|
{ "mtopei", { .raw_val = RISCV_SYSREG_MTOPEI }, "mtopei", { .raw_val = RISCV_SYSREG_MTOPEI }, "", 0x35C, {0} , false }, // 111
|
|
{ "pmpcfg0", { .raw_val = RISCV_SYSREG_PMPCFG0 }, "pmpcfg0", { .raw_val = RISCV_SYSREG_PMPCFG0 }, "", 0x3A0, {0} , false }, // 112
|
|
{ "pmpcfg1", { .raw_val = RISCV_SYSREG_PMPCFG1 }, "pmpcfg1", { .raw_val = RISCV_SYSREG_PMPCFG1 }, "", 0x3A1, {0} , true }, // 113
|
|
{ "pmpcfg2", { .raw_val = RISCV_SYSREG_PMPCFG2 }, "pmpcfg2", { .raw_val = RISCV_SYSREG_PMPCFG2 }, "", 0x3A2, {0} , false }, // 114
|
|
{ "pmpcfg3", { .raw_val = RISCV_SYSREG_PMPCFG3 }, "pmpcfg3", { .raw_val = RISCV_SYSREG_PMPCFG3 }, "", 0x3A3, {0} , true }, // 115
|
|
{ "pmpcfg4", { .raw_val = RISCV_SYSREG_PMPCFG4 }, "pmpcfg4", { .raw_val = RISCV_SYSREG_PMPCFG4 }, "", 0x3A4, {0} , false }, // 116
|
|
{ "pmpcfg5", { .raw_val = RISCV_SYSREG_PMPCFG5 }, "pmpcfg5", { .raw_val = RISCV_SYSREG_PMPCFG5 }, "", 0x3A5, {0} , true }, // 117
|
|
{ "pmpcfg6", { .raw_val = RISCV_SYSREG_PMPCFG6 }, "pmpcfg6", { .raw_val = RISCV_SYSREG_PMPCFG6 }, "", 0x3A6, {0} , false }, // 118
|
|
{ "pmpcfg7", { .raw_val = RISCV_SYSREG_PMPCFG7 }, "pmpcfg7", { .raw_val = RISCV_SYSREG_PMPCFG7 }, "", 0x3A7, {0} , true }, // 119
|
|
{ "pmpcfg8", { .raw_val = RISCV_SYSREG_PMPCFG8 }, "pmpcfg8", { .raw_val = RISCV_SYSREG_PMPCFG8 }, "", 0x3A8, {0} , false }, // 120
|
|
{ "pmpcfg9", { .raw_val = RISCV_SYSREG_PMPCFG9 }, "pmpcfg9", { .raw_val = RISCV_SYSREG_PMPCFG9 }, "", 0x3A9, {0} , true }, // 121
|
|
{ "pmpcfg10", { .raw_val = RISCV_SYSREG_PMPCFG10 }, "pmpcfg10", { .raw_val = RISCV_SYSREG_PMPCFG10 }, "", 0x3AA, {0} , false }, // 122
|
|
{ "pmpcfg11", { .raw_val = RISCV_SYSREG_PMPCFG11 }, "pmpcfg11", { .raw_val = RISCV_SYSREG_PMPCFG11 }, "", 0x3AB, {0} , true }, // 123
|
|
{ "pmpcfg12", { .raw_val = RISCV_SYSREG_PMPCFG12 }, "pmpcfg12", { .raw_val = RISCV_SYSREG_PMPCFG12 }, "", 0x3AC, {0} , false }, // 124
|
|
{ "pmpcfg13", { .raw_val = RISCV_SYSREG_PMPCFG13 }, "pmpcfg13", { .raw_val = RISCV_SYSREG_PMPCFG13 }, "", 0x3AD, {0} , true }, // 125
|
|
{ "pmpcfg14", { .raw_val = RISCV_SYSREG_PMPCFG14 }, "pmpcfg14", { .raw_val = RISCV_SYSREG_PMPCFG14 }, "", 0x3AE, {0} , false }, // 126
|
|
{ "pmpcfg15", { .raw_val = RISCV_SYSREG_PMPCFG15 }, "pmpcfg15", { .raw_val = RISCV_SYSREG_PMPCFG15 }, "", 0x3AF, {0} , true }, // 127
|
|
{ "pmpaddr0", { .raw_val = RISCV_SYSREG_PMPADDR0 }, "pmpaddr0", { .raw_val = RISCV_SYSREG_PMPADDR0 }, "", 0x3B0, {0} , false }, // 128
|
|
{ "pmpaddr1", { .raw_val = RISCV_SYSREG_PMPADDR1 }, "pmpaddr1", { .raw_val = RISCV_SYSREG_PMPADDR1 }, "", 0x3B1, {0} , false }, // 129
|
|
{ "pmpaddr2", { .raw_val = RISCV_SYSREG_PMPADDR2 }, "pmpaddr2", { .raw_val = RISCV_SYSREG_PMPADDR2 }, "", 0x3B2, {0} , false }, // 130
|
|
{ "pmpaddr3", { .raw_val = RISCV_SYSREG_PMPADDR3 }, "pmpaddr3", { .raw_val = RISCV_SYSREG_PMPADDR3 }, "", 0x3B3, {0} , false }, // 131
|
|
{ "pmpaddr4", { .raw_val = RISCV_SYSREG_PMPADDR4 }, "pmpaddr4", { .raw_val = RISCV_SYSREG_PMPADDR4 }, "", 0x3B4, {0} , false }, // 132
|
|
{ "pmpaddr5", { .raw_val = RISCV_SYSREG_PMPADDR5 }, "pmpaddr5", { .raw_val = RISCV_SYSREG_PMPADDR5 }, "", 0x3B5, {0} , false }, // 133
|
|
{ "pmpaddr6", { .raw_val = RISCV_SYSREG_PMPADDR6 }, "pmpaddr6", { .raw_val = RISCV_SYSREG_PMPADDR6 }, "", 0x3B6, {0} , false }, // 134
|
|
{ "pmpaddr7", { .raw_val = RISCV_SYSREG_PMPADDR7 }, "pmpaddr7", { .raw_val = RISCV_SYSREG_PMPADDR7 }, "", 0x3B7, {0} , false }, // 135
|
|
{ "pmpaddr8", { .raw_val = RISCV_SYSREG_PMPADDR8 }, "pmpaddr8", { .raw_val = RISCV_SYSREG_PMPADDR8 }, "", 0x3B8, {0} , false }, // 136
|
|
{ "pmpaddr9", { .raw_val = RISCV_SYSREG_PMPADDR9 }, "pmpaddr9", { .raw_val = RISCV_SYSREG_PMPADDR9 }, "", 0x3B9, {0} , false }, // 137
|
|
{ "pmpaddr10", { .raw_val = RISCV_SYSREG_PMPADDR10 }, "pmpaddr10", { .raw_val = RISCV_SYSREG_PMPADDR10 }, "", 0x3BA, {0} , false }, // 138
|
|
{ "pmpaddr11", { .raw_val = RISCV_SYSREG_PMPADDR11 }, "pmpaddr11", { .raw_val = RISCV_SYSREG_PMPADDR11 }, "", 0x3BB, {0} , false }, // 139
|
|
{ "pmpaddr12", { .raw_val = RISCV_SYSREG_PMPADDR12 }, "pmpaddr12", { .raw_val = RISCV_SYSREG_PMPADDR12 }, "", 0x3BC, {0} , false }, // 140
|
|
{ "pmpaddr13", { .raw_val = RISCV_SYSREG_PMPADDR13 }, "pmpaddr13", { .raw_val = RISCV_SYSREG_PMPADDR13 }, "", 0x3BD, {0} , false }, // 141
|
|
{ "pmpaddr14", { .raw_val = RISCV_SYSREG_PMPADDR14 }, "pmpaddr14", { .raw_val = RISCV_SYSREG_PMPADDR14 }, "", 0x3BE, {0} , false }, // 142
|
|
{ "pmpaddr15", { .raw_val = RISCV_SYSREG_PMPADDR15 }, "pmpaddr15", { .raw_val = RISCV_SYSREG_PMPADDR15 }, "", 0x3BF, {0} , false }, // 143
|
|
{ "pmpaddr16", { .raw_val = RISCV_SYSREG_PMPADDR16 }, "pmpaddr16", { .raw_val = RISCV_SYSREG_PMPADDR16 }, "", 0x3C0, {0} , false }, // 144
|
|
{ "pmpaddr17", { .raw_val = RISCV_SYSREG_PMPADDR17 }, "pmpaddr17", { .raw_val = RISCV_SYSREG_PMPADDR17 }, "", 0x3C1, {0} , false }, // 145
|
|
{ "pmpaddr18", { .raw_val = RISCV_SYSREG_PMPADDR18 }, "pmpaddr18", { .raw_val = RISCV_SYSREG_PMPADDR18 }, "", 0x3C2, {0} , false }, // 146
|
|
{ "pmpaddr19", { .raw_val = RISCV_SYSREG_PMPADDR19 }, "pmpaddr19", { .raw_val = RISCV_SYSREG_PMPADDR19 }, "", 0x3C3, {0} , false }, // 147
|
|
{ "pmpaddr20", { .raw_val = RISCV_SYSREG_PMPADDR20 }, "pmpaddr20", { .raw_val = RISCV_SYSREG_PMPADDR20 }, "", 0x3C4, {0} , false }, // 148
|
|
{ "pmpaddr21", { .raw_val = RISCV_SYSREG_PMPADDR21 }, "pmpaddr21", { .raw_val = RISCV_SYSREG_PMPADDR21 }, "", 0x3C5, {0} , false }, // 149
|
|
{ "pmpaddr22", { .raw_val = RISCV_SYSREG_PMPADDR22 }, "pmpaddr22", { .raw_val = RISCV_SYSREG_PMPADDR22 }, "", 0x3C6, {0} , false }, // 150
|
|
{ "pmpaddr23", { .raw_val = RISCV_SYSREG_PMPADDR23 }, "pmpaddr23", { .raw_val = RISCV_SYSREG_PMPADDR23 }, "", 0x3C7, {0} , false }, // 151
|
|
{ "pmpaddr24", { .raw_val = RISCV_SYSREG_PMPADDR24 }, "pmpaddr24", { .raw_val = RISCV_SYSREG_PMPADDR24 }, "", 0x3C8, {0} , false }, // 152
|
|
{ "pmpaddr25", { .raw_val = RISCV_SYSREG_PMPADDR25 }, "pmpaddr25", { .raw_val = RISCV_SYSREG_PMPADDR25 }, "", 0x3C9, {0} , false }, // 153
|
|
{ "pmpaddr26", { .raw_val = RISCV_SYSREG_PMPADDR26 }, "pmpaddr26", { .raw_val = RISCV_SYSREG_PMPADDR26 }, "", 0x3CA, {0} , false }, // 154
|
|
{ "pmpaddr27", { .raw_val = RISCV_SYSREG_PMPADDR27 }, "pmpaddr27", { .raw_val = RISCV_SYSREG_PMPADDR27 }, "", 0x3CB, {0} , false }, // 155
|
|
{ "pmpaddr28", { .raw_val = RISCV_SYSREG_PMPADDR28 }, "pmpaddr28", { .raw_val = RISCV_SYSREG_PMPADDR28 }, "", 0x3CC, {0} , false }, // 156
|
|
{ "pmpaddr29", { .raw_val = RISCV_SYSREG_PMPADDR29 }, "pmpaddr29", { .raw_val = RISCV_SYSREG_PMPADDR29 }, "", 0x3CD, {0} , false }, // 157
|
|
{ "pmpaddr30", { .raw_val = RISCV_SYSREG_PMPADDR30 }, "pmpaddr30", { .raw_val = RISCV_SYSREG_PMPADDR30 }, "", 0x3CE, {0} , false }, // 158
|
|
{ "pmpaddr31", { .raw_val = RISCV_SYSREG_PMPADDR31 }, "pmpaddr31", { .raw_val = RISCV_SYSREG_PMPADDR31 }, "", 0x3CF, {0} , false }, // 159
|
|
{ "pmpaddr32", { .raw_val = RISCV_SYSREG_PMPADDR32 }, "pmpaddr32", { .raw_val = RISCV_SYSREG_PMPADDR32 }, "", 0x3D0, {0} , false }, // 160
|
|
{ "pmpaddr33", { .raw_val = RISCV_SYSREG_PMPADDR33 }, "pmpaddr33", { .raw_val = RISCV_SYSREG_PMPADDR33 }, "", 0x3D1, {0} , false }, // 161
|
|
{ "pmpaddr34", { .raw_val = RISCV_SYSREG_PMPADDR34 }, "pmpaddr34", { .raw_val = RISCV_SYSREG_PMPADDR34 }, "", 0x3D2, {0} , false }, // 162
|
|
{ "pmpaddr35", { .raw_val = RISCV_SYSREG_PMPADDR35 }, "pmpaddr35", { .raw_val = RISCV_SYSREG_PMPADDR35 }, "", 0x3D3, {0} , false }, // 163
|
|
{ "pmpaddr36", { .raw_val = RISCV_SYSREG_PMPADDR36 }, "pmpaddr36", { .raw_val = RISCV_SYSREG_PMPADDR36 }, "", 0x3D4, {0} , false }, // 164
|
|
{ "pmpaddr37", { .raw_val = RISCV_SYSREG_PMPADDR37 }, "pmpaddr37", { .raw_val = RISCV_SYSREG_PMPADDR37 }, "", 0x3D5, {0} , false }, // 165
|
|
{ "pmpaddr38", { .raw_val = RISCV_SYSREG_PMPADDR38 }, "pmpaddr38", { .raw_val = RISCV_SYSREG_PMPADDR38 }, "", 0x3D6, {0} , false }, // 166
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|
{ "pmpaddr39", { .raw_val = RISCV_SYSREG_PMPADDR39 }, "pmpaddr39", { .raw_val = RISCV_SYSREG_PMPADDR39 }, "", 0x3D7, {0} , false }, // 167
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|
{ "pmpaddr40", { .raw_val = RISCV_SYSREG_PMPADDR40 }, "pmpaddr40", { .raw_val = RISCV_SYSREG_PMPADDR40 }, "", 0x3D8, {0} , false }, // 168
|
|
{ "pmpaddr41", { .raw_val = RISCV_SYSREG_PMPADDR41 }, "pmpaddr41", { .raw_val = RISCV_SYSREG_PMPADDR41 }, "", 0x3D9, {0} , false }, // 169
|
|
{ "pmpaddr42", { .raw_val = RISCV_SYSREG_PMPADDR42 }, "pmpaddr42", { .raw_val = RISCV_SYSREG_PMPADDR42 }, "", 0x3DA, {0} , false }, // 170
|
|
{ "pmpaddr43", { .raw_val = RISCV_SYSREG_PMPADDR43 }, "pmpaddr43", { .raw_val = RISCV_SYSREG_PMPADDR43 }, "", 0x3DB, {0} , false }, // 171
|
|
{ "pmpaddr44", { .raw_val = RISCV_SYSREG_PMPADDR44 }, "pmpaddr44", { .raw_val = RISCV_SYSREG_PMPADDR44 }, "", 0x3DC, {0} , false }, // 172
|
|
{ "pmpaddr45", { .raw_val = RISCV_SYSREG_PMPADDR45 }, "pmpaddr45", { .raw_val = RISCV_SYSREG_PMPADDR45 }, "", 0x3DD, {0} , false }, // 173
|
|
{ "pmpaddr46", { .raw_val = RISCV_SYSREG_PMPADDR46 }, "pmpaddr46", { .raw_val = RISCV_SYSREG_PMPADDR46 }, "", 0x3DE, {0} , false }, // 174
|
|
{ "pmpaddr47", { .raw_val = RISCV_SYSREG_PMPADDR47 }, "pmpaddr47", { .raw_val = RISCV_SYSREG_PMPADDR47 }, "", 0x3DF, {0} , false }, // 175
|
|
{ "pmpaddr48", { .raw_val = RISCV_SYSREG_PMPADDR48 }, "pmpaddr48", { .raw_val = RISCV_SYSREG_PMPADDR48 }, "", 0x3E0, {0} , false }, // 176
|
|
{ "pmpaddr49", { .raw_val = RISCV_SYSREG_PMPADDR49 }, "pmpaddr49", { .raw_val = RISCV_SYSREG_PMPADDR49 }, "", 0x3E1, {0} , false }, // 177
|
|
{ "pmpaddr50", { .raw_val = RISCV_SYSREG_PMPADDR50 }, "pmpaddr50", { .raw_val = RISCV_SYSREG_PMPADDR50 }, "", 0x3E2, {0} , false }, // 178
|
|
{ "pmpaddr51", { .raw_val = RISCV_SYSREG_PMPADDR51 }, "pmpaddr51", { .raw_val = RISCV_SYSREG_PMPADDR51 }, "", 0x3E3, {0} , false }, // 179
|
|
{ "pmpaddr52", { .raw_val = RISCV_SYSREG_PMPADDR52 }, "pmpaddr52", { .raw_val = RISCV_SYSREG_PMPADDR52 }, "", 0x3E4, {0} , false }, // 180
|
|
{ "pmpaddr53", { .raw_val = RISCV_SYSREG_PMPADDR53 }, "pmpaddr53", { .raw_val = RISCV_SYSREG_PMPADDR53 }, "", 0x3E5, {0} , false }, // 181
|
|
{ "pmpaddr54", { .raw_val = RISCV_SYSREG_PMPADDR54 }, "pmpaddr54", { .raw_val = RISCV_SYSREG_PMPADDR54 }, "", 0x3E6, {0} , false }, // 182
|
|
{ "pmpaddr55", { .raw_val = RISCV_SYSREG_PMPADDR55 }, "pmpaddr55", { .raw_val = RISCV_SYSREG_PMPADDR55 }, "", 0x3E7, {0} , false }, // 183
|
|
{ "pmpaddr56", { .raw_val = RISCV_SYSREG_PMPADDR56 }, "pmpaddr56", { .raw_val = RISCV_SYSREG_PMPADDR56 }, "", 0x3E8, {0} , false }, // 184
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|
{ "pmpaddr57", { .raw_val = RISCV_SYSREG_PMPADDR57 }, "pmpaddr57", { .raw_val = RISCV_SYSREG_PMPADDR57 }, "", 0x3E9, {0} , false }, // 185
|
|
{ "pmpaddr58", { .raw_val = RISCV_SYSREG_PMPADDR58 }, "pmpaddr58", { .raw_val = RISCV_SYSREG_PMPADDR58 }, "", 0x3EA, {0} , false }, // 186
|
|
{ "pmpaddr59", { .raw_val = RISCV_SYSREG_PMPADDR59 }, "pmpaddr59", { .raw_val = RISCV_SYSREG_PMPADDR59 }, "", 0x3EB, {0} , false }, // 187
|
|
{ "pmpaddr60", { .raw_val = RISCV_SYSREG_PMPADDR60 }, "pmpaddr60", { .raw_val = RISCV_SYSREG_PMPADDR60 }, "", 0x3EC, {0} , false }, // 188
|
|
{ "pmpaddr61", { .raw_val = RISCV_SYSREG_PMPADDR61 }, "pmpaddr61", { .raw_val = RISCV_SYSREG_PMPADDR61 }, "", 0x3ED, {0} , false }, // 189
|
|
{ "pmpaddr62", { .raw_val = RISCV_SYSREG_PMPADDR62 }, "pmpaddr62", { .raw_val = RISCV_SYSREG_PMPADDR62 }, "", 0x3EE, {0} , false }, // 190
|
|
{ "pmpaddr63", { .raw_val = RISCV_SYSREG_PMPADDR63 }, "pmpaddr63", { .raw_val = RISCV_SYSREG_PMPADDR63 }, "", 0x3EF, {0} , false }, // 191
|
|
{ "scontext", { .raw_val = RISCV_SYSREG_SCONTEXT }, "scontext", { .raw_val = RISCV_SYSREG_SCONTEXT }, "", 0x5A8, {0} , false }, // 192
|
|
{ "hstatus", { .raw_val = RISCV_SYSREG_HSTATUS }, "hstatus", { .raw_val = RISCV_SYSREG_HSTATUS }, "", 0x600, {0} , false }, // 193
|
|
{ "hedeleg", { .raw_val = RISCV_SYSREG_HEDELEG }, "hedeleg", { .raw_val = RISCV_SYSREG_HEDELEG }, "", 0x602, {0} , false }, // 194
|
|
{ "hideleg", { .raw_val = RISCV_SYSREG_HIDELEG }, "hideleg", { .raw_val = RISCV_SYSREG_HIDELEG }, "", 0x603, {0} , false }, // 195
|
|
{ "hie", { .raw_val = RISCV_SYSREG_HIE }, "hie", { .raw_val = RISCV_SYSREG_HIE }, "", 0x604, {0} , false }, // 196
|
|
{ "htimedelta", { .raw_val = RISCV_SYSREG_HTIMEDELTA }, "htimedelta", { .raw_val = RISCV_SYSREG_HTIMEDELTA }, "", 0x605, {0} , false }, // 197
|
|
{ "hcounteren", { .raw_val = RISCV_SYSREG_HCOUNTEREN }, "hcounteren", { .raw_val = RISCV_SYSREG_HCOUNTEREN }, "", 0x606, {0} , false }, // 198
|
|
{ "hgeie", { .raw_val = RISCV_SYSREG_HGEIE }, "hgeie", { .raw_val = RISCV_SYSREG_HGEIE }, "", 0x607, {0} , false }, // 199
|
|
{ "hvien", { .raw_val = RISCV_SYSREG_HVIEN }, "hvien", { .raw_val = RISCV_SYSREG_HVIEN }, "", 0x608, {0} , false }, // 200
|
|
{ "hvictl", { .raw_val = RISCV_SYSREG_HVICTL }, "hvictl", { .raw_val = RISCV_SYSREG_HVICTL }, "", 0x609, {0} , false }, // 201
|
|
{ "henvcfg", { .raw_val = RISCV_SYSREG_HENVCFG }, "henvcfg", { .raw_val = RISCV_SYSREG_HENVCFG }, "", 0x60A, {0} , false }, // 202
|
|
{ "hstateen0", { .raw_val = RISCV_SYSREG_HSTATEEN0 }, "hstateen0", { .raw_val = RISCV_SYSREG_HSTATEEN0 }, "", 0x60C, {0} , false }, // 203
|
|
{ "hstateen1", { .raw_val = RISCV_SYSREG_HSTATEEN1 }, "hstateen1", { .raw_val = RISCV_SYSREG_HSTATEEN1 }, "", 0x60D, {0} , false }, // 204
|
|
{ "hstateen2", { .raw_val = RISCV_SYSREG_HSTATEEN2 }, "hstateen2", { .raw_val = RISCV_SYSREG_HSTATEEN2 }, "", 0x60E, {0} , false }, // 205
|
|
{ "hstateen3", { .raw_val = RISCV_SYSREG_HSTATEEN3 }, "hstateen3", { .raw_val = RISCV_SYSREG_HSTATEEN3 }, "", 0x60F, {0} , false }, // 206
|
|
{ "hidelegh", { .raw_val = RISCV_SYSREG_HIDELEGH }, "hidelegh", { .raw_val = RISCV_SYSREG_HIDELEGH }, "", 0x613, {0} , true }, // 207
|
|
{ "htimedeltah", { .raw_val = RISCV_SYSREG_HTIMEDELTAH }, "htimedeltah", { .raw_val = RISCV_SYSREG_HTIMEDELTAH }, "", 0x615, {0} , true }, // 208
|
|
{ "hvienh", { .raw_val = RISCV_SYSREG_HVIENH }, "hvienh", { .raw_val = RISCV_SYSREG_HVIENH }, "", 0x618, {0} , true }, // 209
|
|
{ "henvcfgh", { .raw_val = RISCV_SYSREG_HENVCFGH }, "henvcfgh", { .raw_val = RISCV_SYSREG_HENVCFGH }, "", 0x61A, {0} , true }, // 210
|
|
{ "hstateen0h", { .raw_val = RISCV_SYSREG_HSTATEEN0H }, "hstateen0h", { .raw_val = RISCV_SYSREG_HSTATEEN0H }, "", 0x61C, {0} , true }, // 211
|
|
{ "hstateen1h", { .raw_val = RISCV_SYSREG_HSTATEEN1H }, "hstateen1h", { .raw_val = RISCV_SYSREG_HSTATEEN1H }, "", 0x61D, {0} , true }, // 212
|
|
{ "hstateen2h", { .raw_val = RISCV_SYSREG_HSTATEEN2H }, "hstateen2h", { .raw_val = RISCV_SYSREG_HSTATEEN2H }, "", 0x61E, {0} , true }, // 213
|
|
{ "hstateen3h", { .raw_val = RISCV_SYSREG_HSTATEEN3H }, "hstateen3h", { .raw_val = RISCV_SYSREG_HSTATEEN3H }, "", 0x61F, {0} , true }, // 214
|
|
{ "htval", { .raw_val = RISCV_SYSREG_HTVAL }, "htval", { .raw_val = RISCV_SYSREG_HTVAL }, "", 0x643, {0} , false }, // 215
|
|
{ "hip", { .raw_val = RISCV_SYSREG_HIP }, "hip", { .raw_val = RISCV_SYSREG_HIP }, "", 0x644, {0} , false }, // 216
|
|
{ "hvip", { .raw_val = RISCV_SYSREG_HVIP }, "hvip", { .raw_val = RISCV_SYSREG_HVIP }, "", 0x645, {0} , false }, // 217
|
|
{ "hviprio1", { .raw_val = RISCV_SYSREG_HVIPRIO1 }, "hviprio1", { .raw_val = RISCV_SYSREG_HVIPRIO1 }, "", 0x646, {0} , false }, // 218
|
|
{ "hviprio2", { .raw_val = RISCV_SYSREG_HVIPRIO2 }, "hviprio2", { .raw_val = RISCV_SYSREG_HVIPRIO2 }, "", 0x647, {0} , false }, // 219
|
|
{ "htinst", { .raw_val = RISCV_SYSREG_HTINST }, "htinst", { .raw_val = RISCV_SYSREG_HTINST }, "", 0x64A, {0} , false }, // 220
|
|
{ "hviph", { .raw_val = RISCV_SYSREG_HVIPH }, "hviph", { .raw_val = RISCV_SYSREG_HVIPH }, "", 0x655, {0} , true }, // 221
|
|
{ "hviprio1h", { .raw_val = RISCV_SYSREG_HVIPRIO1H }, "hviprio1h", { .raw_val = RISCV_SYSREG_HVIPRIO1H }, "", 0x656, {0} , true }, // 222
|
|
{ "hviprio2h", { .raw_val = RISCV_SYSREG_HVIPRIO2H }, "hviprio2h", { .raw_val = RISCV_SYSREG_HVIPRIO2H }, "", 0x657, {0} , true }, // 223
|
|
{ "hgatp", { .raw_val = RISCV_SYSREG_HGATP }, "hgatp", { .raw_val = RISCV_SYSREG_HGATP }, "", 0x680, {0} , false }, // 224
|
|
{ "hcontext", { .raw_val = RISCV_SYSREG_HCONTEXT }, "hcontext", { .raw_val = RISCV_SYSREG_HCONTEXT }, "", 0x6A8, {0} , false }, // 225
|
|
{ "mhpmevent3h", { .raw_val = RISCV_SYSREG_MHPMEVENT3H }, "mhpmevent3h", { .raw_val = RISCV_SYSREG_MHPMEVENT3H }, "", 0x723, {0} , true }, // 226
|
|
{ "mhpmevent4h", { .raw_val = RISCV_SYSREG_MHPMEVENT4H }, "mhpmevent4h", { .raw_val = RISCV_SYSREG_MHPMEVENT4H }, "", 0x724, {0} , true }, // 227
|
|
{ "mhpmevent5h", { .raw_val = RISCV_SYSREG_MHPMEVENT5H }, "mhpmevent5h", { .raw_val = RISCV_SYSREG_MHPMEVENT5H }, "", 0x725, {0} , true }, // 228
|
|
{ "mhpmevent6h", { .raw_val = RISCV_SYSREG_MHPMEVENT6H }, "mhpmevent6h", { .raw_val = RISCV_SYSREG_MHPMEVENT6H }, "", 0x726, {0} , true }, // 229
|
|
{ "mhpmevent7h", { .raw_val = RISCV_SYSREG_MHPMEVENT7H }, "mhpmevent7h", { .raw_val = RISCV_SYSREG_MHPMEVENT7H }, "", 0x727, {0} , true }, // 230
|
|
{ "mhpmevent8h", { .raw_val = RISCV_SYSREG_MHPMEVENT8H }, "mhpmevent8h", { .raw_val = RISCV_SYSREG_MHPMEVENT8H }, "", 0x728, {0} , true }, // 231
|
|
{ "mhpmevent9h", { .raw_val = RISCV_SYSREG_MHPMEVENT9H }, "mhpmevent9h", { .raw_val = RISCV_SYSREG_MHPMEVENT9H }, "", 0x729, {0} , true }, // 232
|
|
{ "mhpmevent10h", { .raw_val = RISCV_SYSREG_MHPMEVENT10H }, "mhpmevent10h", { .raw_val = RISCV_SYSREG_MHPMEVENT10H }, "", 0x72A, {0} , true }, // 233
|
|
{ "mhpmevent11h", { .raw_val = RISCV_SYSREG_MHPMEVENT11H }, "mhpmevent11h", { .raw_val = RISCV_SYSREG_MHPMEVENT11H }, "", 0x72B, {0} , true }, // 234
|
|
{ "mhpmevent12h", { .raw_val = RISCV_SYSREG_MHPMEVENT12H }, "mhpmevent12h", { .raw_val = RISCV_SYSREG_MHPMEVENT12H }, "", 0x72C, {0} , true }, // 235
|
|
{ "mhpmevent13h", { .raw_val = RISCV_SYSREG_MHPMEVENT13H }, "mhpmevent13h", { .raw_val = RISCV_SYSREG_MHPMEVENT13H }, "", 0x72D, {0} , true }, // 236
|
|
{ "mhpmevent14h", { .raw_val = RISCV_SYSREG_MHPMEVENT14H }, "mhpmevent14h", { .raw_val = RISCV_SYSREG_MHPMEVENT14H }, "", 0x72E, {0} , true }, // 237
|
|
{ "mhpmevent15h", { .raw_val = RISCV_SYSREG_MHPMEVENT15H }, "mhpmevent15h", { .raw_val = RISCV_SYSREG_MHPMEVENT15H }, "", 0x72F, {0} , true }, // 238
|
|
{ "mhpmevent16h", { .raw_val = RISCV_SYSREG_MHPMEVENT16H }, "mhpmevent16h", { .raw_val = RISCV_SYSREG_MHPMEVENT16H }, "", 0x730, {0} , true }, // 239
|
|
{ "mhpmevent17h", { .raw_val = RISCV_SYSREG_MHPMEVENT17H }, "mhpmevent17h", { .raw_val = RISCV_SYSREG_MHPMEVENT17H }, "", 0x731, {0} , true }, // 240
|
|
{ "mhpmevent18h", { .raw_val = RISCV_SYSREG_MHPMEVENT18H }, "mhpmevent18h", { .raw_val = RISCV_SYSREG_MHPMEVENT18H }, "", 0x732, {0} , true }, // 241
|
|
{ "mhpmevent19h", { .raw_val = RISCV_SYSREG_MHPMEVENT19H }, "mhpmevent19h", { .raw_val = RISCV_SYSREG_MHPMEVENT19H }, "", 0x733, {0} , true }, // 242
|
|
{ "mhpmevent20h", { .raw_val = RISCV_SYSREG_MHPMEVENT20H }, "mhpmevent20h", { .raw_val = RISCV_SYSREG_MHPMEVENT20H }, "", 0x734, {0} , true }, // 243
|
|
{ "mhpmevent21h", { .raw_val = RISCV_SYSREG_MHPMEVENT21H }, "mhpmevent21h", { .raw_val = RISCV_SYSREG_MHPMEVENT21H }, "", 0x735, {0} , true }, // 244
|
|
{ "mhpmevent22h", { .raw_val = RISCV_SYSREG_MHPMEVENT22H }, "mhpmevent22h", { .raw_val = RISCV_SYSREG_MHPMEVENT22H }, "", 0x736, {0} , true }, // 245
|
|
{ "mhpmevent23h", { .raw_val = RISCV_SYSREG_MHPMEVENT23H }, "mhpmevent23h", { .raw_val = RISCV_SYSREG_MHPMEVENT23H }, "", 0x737, {0} , true }, // 246
|
|
{ "mhpmevent24h", { .raw_val = RISCV_SYSREG_MHPMEVENT24H }, "mhpmevent24h", { .raw_val = RISCV_SYSREG_MHPMEVENT24H }, "", 0x738, {0} , true }, // 247
|
|
{ "mhpmevent25h", { .raw_val = RISCV_SYSREG_MHPMEVENT25H }, "mhpmevent25h", { .raw_val = RISCV_SYSREG_MHPMEVENT25H }, "", 0x739, {0} , true }, // 248
|
|
{ "mhpmevent26h", { .raw_val = RISCV_SYSREG_MHPMEVENT26H }, "mhpmevent26h", { .raw_val = RISCV_SYSREG_MHPMEVENT26H }, "", 0x73A, {0} , true }, // 249
|
|
{ "mhpmevent27h", { .raw_val = RISCV_SYSREG_MHPMEVENT27H }, "mhpmevent27h", { .raw_val = RISCV_SYSREG_MHPMEVENT27H }, "", 0x73B, {0} , true }, // 250
|
|
{ "mhpmevent28h", { .raw_val = RISCV_SYSREG_MHPMEVENT28H }, "mhpmevent28h", { .raw_val = RISCV_SYSREG_MHPMEVENT28H }, "", 0x73C, {0} , true }, // 251
|
|
{ "mhpmevent29h", { .raw_val = RISCV_SYSREG_MHPMEVENT29H }, "mhpmevent29h", { .raw_val = RISCV_SYSREG_MHPMEVENT29H }, "", 0x73D, {0} , true }, // 252
|
|
{ "mhpmevent30h", { .raw_val = RISCV_SYSREG_MHPMEVENT30H }, "mhpmevent30h", { .raw_val = RISCV_SYSREG_MHPMEVENT30H }, "", 0x73E, {0} , true }, // 253
|
|
{ "mhpmevent31h", { .raw_val = RISCV_SYSREG_MHPMEVENT31H }, "mhpmevent31h", { .raw_val = RISCV_SYSREG_MHPMEVENT31H }, "", 0x73F, {0} , true }, // 254
|
|
{ "mseccfg", { .raw_val = RISCV_SYSREG_MSECCFG }, "mseccfg", { .raw_val = RISCV_SYSREG_MSECCFG }, "", 0x747, {0} , false }, // 255
|
|
{ "mseccfgh", { .raw_val = RISCV_SYSREG_MSECCFGH }, "mseccfgh", { .raw_val = RISCV_SYSREG_MSECCFGH }, "", 0x757, {0} , true }, // 256
|
|
{ "tselect", { .raw_val = RISCV_SYSREG_TSELECT }, "tselect", { .raw_val = RISCV_SYSREG_TSELECT }, "", 0x7A0, {0} , false }, // 257
|
|
{ "tdata1", { .raw_val = RISCV_SYSREG_TDATA1 }, "tdata1", { .raw_val = RISCV_SYSREG_TDATA1 }, "", 0x7A1, {0} , false }, // 258
|
|
{ "tdata2", { .raw_val = RISCV_SYSREG_TDATA2 }, "tdata2", { .raw_val = RISCV_SYSREG_TDATA2 }, "", 0x7A2, {0} , false }, // 259
|
|
{ "tdata3", { .raw_val = RISCV_SYSREG_TDATA3 }, "tdata3", { .raw_val = RISCV_SYSREG_TDATA3 }, "", 0x7A3, {0} , false }, // 260
|
|
{ "mcontext", { .raw_val = RISCV_SYSREG_MCONTEXT }, "mcontext", { .raw_val = RISCV_SYSREG_MCONTEXT }, "", 0x7A8, {0} , false }, // 261
|
|
{ "dcsr", { .raw_val = RISCV_SYSREG_DCSR }, "dcsr", { .raw_val = RISCV_SYSREG_DCSR }, "", 0x7B0, {0} , false }, // 262
|
|
{ "dpc", { .raw_val = RISCV_SYSREG_DPC }, "dpc", { .raw_val = RISCV_SYSREG_DPC }, "", 0x7B1, {0} , false }, // 263
|
|
{ "dscratch0", { .raw_val = RISCV_SYSREG_DSCRATCH0 }, "dscratch", { .raw_val = RISCV_SYSREG_DSCRATCH }, "", 0x7B2, {0} , false }, // 264
|
|
{ "dscratch1", { .raw_val = RISCV_SYSREG_DSCRATCH1 }, "dscratch1", { .raw_val = RISCV_SYSREG_DSCRATCH1 }, "", 0x7B3, {0} , false }, // 265
|
|
{ "mcycle", { .raw_val = RISCV_SYSREG_MCYCLE }, "mcycle", { .raw_val = RISCV_SYSREG_MCYCLE }, "", 0xB00, {0} , false }, // 266
|
|
{ "minstret", { .raw_val = RISCV_SYSREG_MINSTRET }, "minstret", { .raw_val = RISCV_SYSREG_MINSTRET }, "", 0xB02, {0} , false }, // 267
|
|
{ "mhpmcounter3", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3 }, "mhpmcounter3", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3 }, "", 0xB03, {0} , false }, // 268
|
|
{ "mhpmcounter4", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4 }, "mhpmcounter4", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4 }, "", 0xB04, {0} , false }, // 269
|
|
{ "mhpmcounter5", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5 }, "mhpmcounter5", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5 }, "", 0xB05, {0} , false }, // 270
|
|
{ "mhpmcounter6", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6 }, "mhpmcounter6", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6 }, "", 0xB06, {0} , false }, // 271
|
|
{ "mhpmcounter7", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7 }, "mhpmcounter7", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7 }, "", 0xB07, {0} , false }, // 272
|
|
{ "mhpmcounter8", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8 }, "mhpmcounter8", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8 }, "", 0xB08, {0} , false }, // 273
|
|
{ "mhpmcounter9", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9 }, "mhpmcounter9", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9 }, "", 0xB09, {0} , false }, // 274
|
|
{ "mhpmcounter10", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10 }, "mhpmcounter10", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10 }, "", 0xB0A, {0} , false }, // 275
|
|
{ "mhpmcounter11", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11 }, "mhpmcounter11", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11 }, "", 0xB0B, {0} , false }, // 276
|
|
{ "mhpmcounter12", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12 }, "mhpmcounter12", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12 }, "", 0xB0C, {0} , false }, // 277
|
|
{ "mhpmcounter13", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13 }, "mhpmcounter13", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13 }, "", 0xB0D, {0} , false }, // 278
|
|
{ "mhpmcounter14", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14 }, "mhpmcounter14", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14 }, "", 0xB0E, {0} , false }, // 279
|
|
{ "mhpmcounter15", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15 }, "mhpmcounter15", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15 }, "", 0xB0F, {0} , false }, // 280
|
|
{ "mhpmcounter16", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16 }, "mhpmcounter16", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16 }, "", 0xB10, {0} , false }, // 281
|
|
{ "mhpmcounter17", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17 }, "mhpmcounter17", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17 }, "", 0xB11, {0} , false }, // 282
|
|
{ "mhpmcounter18", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18 }, "mhpmcounter18", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18 }, "", 0xB12, {0} , false }, // 283
|
|
{ "mhpmcounter19", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19 }, "mhpmcounter19", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19 }, "", 0xB13, {0} , false }, // 284
|
|
{ "mhpmcounter20", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20 }, "mhpmcounter20", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20 }, "", 0xB14, {0} , false }, // 285
|
|
{ "mhpmcounter21", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21 }, "mhpmcounter21", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21 }, "", 0xB15, {0} , false }, // 286
|
|
{ "mhpmcounter22", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22 }, "mhpmcounter22", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22 }, "", 0xB16, {0} , false }, // 287
|
|
{ "mhpmcounter23", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23 }, "mhpmcounter23", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23 }, "", 0xB17, {0} , false }, // 288
|
|
{ "mhpmcounter24", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24 }, "mhpmcounter24", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24 }, "", 0xB18, {0} , false }, // 289
|
|
{ "mhpmcounter25", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25 }, "mhpmcounter25", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25 }, "", 0xB19, {0} , false }, // 290
|
|
{ "mhpmcounter26", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26 }, "mhpmcounter26", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26 }, "", 0xB1A, {0} , false }, // 291
|
|
{ "mhpmcounter27", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27 }, "mhpmcounter27", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27 }, "", 0xB1B, {0} , false }, // 292
|
|
{ "mhpmcounter28", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28 }, "mhpmcounter28", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28 }, "", 0xB1C, {0} , false }, // 293
|
|
{ "mhpmcounter29", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29 }, "mhpmcounter29", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29 }, "", 0xB1D, {0} , false }, // 294
|
|
{ "mhpmcounter30", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30 }, "mhpmcounter30", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30 }, "", 0xB1E, {0} , false }, // 295
|
|
{ "mhpmcounter31", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31 }, "mhpmcounter31", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31 }, "", 0xB1F, {0} , false }, // 296
|
|
{ "mcycleh", { .raw_val = RISCV_SYSREG_MCYCLEH }, "mcycleh", { .raw_val = RISCV_SYSREG_MCYCLEH }, "", 0xB80, {0} , true }, // 297
|
|
{ "minstreth", { .raw_val = RISCV_SYSREG_MINSTRETH }, "minstreth", { .raw_val = RISCV_SYSREG_MINSTRETH }, "", 0xB82, {0} , true }, // 298
|
|
{ "mhpmcounter3h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3H }, "mhpmcounter3h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3H }, "", 0xB83, {0} , true }, // 299
|
|
{ "mhpmcounter4h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4H }, "mhpmcounter4h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4H }, "", 0xB84, {0} , true }, // 300
|
|
{ "mhpmcounter5h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5H }, "mhpmcounter5h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5H }, "", 0xB85, {0} , true }, // 301
|
|
{ "mhpmcounter6h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6H }, "mhpmcounter6h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6H }, "", 0xB86, {0} , true }, // 302
|
|
{ "mhpmcounter7h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7H }, "mhpmcounter7h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7H }, "", 0xB87, {0} , true }, // 303
|
|
{ "mhpmcounter8h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8H }, "mhpmcounter8h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8H }, "", 0xB88, {0} , true }, // 304
|
|
{ "mhpmcounter9h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9H }, "mhpmcounter9h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9H }, "", 0xB89, {0} , true }, // 305
|
|
{ "mhpmcounter10h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10H }, "mhpmcounter10h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10H }, "", 0xB8A, {0} , true }, // 306
|
|
{ "mhpmcounter11h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11H }, "mhpmcounter11h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11H }, "", 0xB8B, {0} , true }, // 307
|
|
{ "mhpmcounter12h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12H }, "mhpmcounter12h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12H }, "", 0xB8C, {0} , true }, // 308
|
|
{ "mhpmcounter13h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13H }, "mhpmcounter13h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13H }, "", 0xB8D, {0} , true }, // 309
|
|
{ "mhpmcounter14h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14H }, "mhpmcounter14h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14H }, "", 0xB8E, {0} , true }, // 310
|
|
{ "mhpmcounter15h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15H }, "mhpmcounter15h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15H }, "", 0xB8F, {0} , true }, // 311
|
|
{ "mhpmcounter16h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16H }, "mhpmcounter16h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16H }, "", 0xB90, {0} , true }, // 312
|
|
{ "mhpmcounter17h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17H }, "mhpmcounter17h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17H }, "", 0xB91, {0} , true }, // 313
|
|
{ "mhpmcounter18h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18H }, "mhpmcounter18h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18H }, "", 0xB92, {0} , true }, // 314
|
|
{ "mhpmcounter19h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19H }, "mhpmcounter19h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19H }, "", 0xB93, {0} , true }, // 315
|
|
{ "mhpmcounter20h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20H }, "mhpmcounter20h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20H }, "", 0xB94, {0} , true }, // 316
|
|
{ "mhpmcounter21h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21H }, "mhpmcounter21h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21H }, "", 0xB95, {0} , true }, // 317
|
|
{ "mhpmcounter22h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22H }, "mhpmcounter22h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22H }, "", 0xB96, {0} , true }, // 318
|
|
{ "mhpmcounter23h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23H }, "mhpmcounter23h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23H }, "", 0xB97, {0} , true }, // 319
|
|
{ "mhpmcounter24h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24H }, "mhpmcounter24h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24H }, "", 0xB98, {0} , true }, // 320
|
|
{ "mhpmcounter25h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25H }, "mhpmcounter25h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25H }, "", 0xB99, {0} , true }, // 321
|
|
{ "mhpmcounter26h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26H }, "mhpmcounter26h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26H }, "", 0xB9A, {0} , true }, // 322
|
|
{ "mhpmcounter27h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27H }, "mhpmcounter27h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27H }, "", 0xB9B, {0} , true }, // 323
|
|
{ "mhpmcounter28h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28H }, "mhpmcounter28h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28H }, "", 0xB9C, {0} , true }, // 324
|
|
{ "mhpmcounter29h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29H }, "mhpmcounter29h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29H }, "", 0xB9D, {0} , true }, // 325
|
|
{ "mhpmcounter30h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30H }, "mhpmcounter30h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30H }, "", 0xB9E, {0} , true }, // 326
|
|
{ "mhpmcounter31h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31H }, "mhpmcounter31h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31H }, "", 0xB9F, {0} , true }, // 327
|
|
{ "cycle", { .raw_val = RISCV_SYSREG_CYCLE }, "cycle", { .raw_val = RISCV_SYSREG_CYCLE }, "", 0xC00, {0} , false }, // 328
|
|
{ "time", { .raw_val = RISCV_SYSREG_TIME }, "time", { .raw_val = RISCV_SYSREG_TIME }, "", 0xC01, {0} , false }, // 329
|
|
{ "instret", { .raw_val = RISCV_SYSREG_INSTRET }, "instret", { .raw_val = RISCV_SYSREG_INSTRET }, "", 0xC02, {0} , false }, // 330
|
|
{ "hpmcounter3", { .raw_val = RISCV_SYSREG_HPMCOUNTER3 }, "hpmcounter3", { .raw_val = RISCV_SYSREG_HPMCOUNTER3 }, "", 0xC03, {0} , false }, // 331
|
|
{ "hpmcounter4", { .raw_val = RISCV_SYSREG_HPMCOUNTER4 }, "hpmcounter4", { .raw_val = RISCV_SYSREG_HPMCOUNTER4 }, "", 0xC04, {0} , false }, // 332
|
|
{ "hpmcounter5", { .raw_val = RISCV_SYSREG_HPMCOUNTER5 }, "hpmcounter5", { .raw_val = RISCV_SYSREG_HPMCOUNTER5 }, "", 0xC05, {0} , false }, // 333
|
|
{ "hpmcounter6", { .raw_val = RISCV_SYSREG_HPMCOUNTER6 }, "hpmcounter6", { .raw_val = RISCV_SYSREG_HPMCOUNTER6 }, "", 0xC06, {0} , false }, // 334
|
|
{ "hpmcounter7", { .raw_val = RISCV_SYSREG_HPMCOUNTER7 }, "hpmcounter7", { .raw_val = RISCV_SYSREG_HPMCOUNTER7 }, "", 0xC07, {0} , false }, // 335
|
|
{ "hpmcounter8", { .raw_val = RISCV_SYSREG_HPMCOUNTER8 }, "hpmcounter8", { .raw_val = RISCV_SYSREG_HPMCOUNTER8 }, "", 0xC08, {0} , false }, // 336
|
|
{ "hpmcounter9", { .raw_val = RISCV_SYSREG_HPMCOUNTER9 }, "hpmcounter9", { .raw_val = RISCV_SYSREG_HPMCOUNTER9 }, "", 0xC09, {0} , false }, // 337
|
|
{ "hpmcounter10", { .raw_val = RISCV_SYSREG_HPMCOUNTER10 }, "hpmcounter10", { .raw_val = RISCV_SYSREG_HPMCOUNTER10 }, "", 0xC0A, {0} , false }, // 338
|
|
{ "hpmcounter11", { .raw_val = RISCV_SYSREG_HPMCOUNTER11 }, "hpmcounter11", { .raw_val = RISCV_SYSREG_HPMCOUNTER11 }, "", 0xC0B, {0} , false }, // 339
|
|
{ "hpmcounter12", { .raw_val = RISCV_SYSREG_HPMCOUNTER12 }, "hpmcounter12", { .raw_val = RISCV_SYSREG_HPMCOUNTER12 }, "", 0xC0C, {0} , false }, // 340
|
|
{ "hpmcounter13", { .raw_val = RISCV_SYSREG_HPMCOUNTER13 }, "hpmcounter13", { .raw_val = RISCV_SYSREG_HPMCOUNTER13 }, "", 0xC0D, {0} , false }, // 341
|
|
{ "hpmcounter14", { .raw_val = RISCV_SYSREG_HPMCOUNTER14 }, "hpmcounter14", { .raw_val = RISCV_SYSREG_HPMCOUNTER14 }, "", 0xC0E, {0} , false }, // 342
|
|
{ "hpmcounter15", { .raw_val = RISCV_SYSREG_HPMCOUNTER15 }, "hpmcounter15", { .raw_val = RISCV_SYSREG_HPMCOUNTER15 }, "", 0xC0F, {0} , false }, // 343
|
|
{ "hpmcounter16", { .raw_val = RISCV_SYSREG_HPMCOUNTER16 }, "hpmcounter16", { .raw_val = RISCV_SYSREG_HPMCOUNTER16 }, "", 0xC10, {0} , false }, // 344
|
|
{ "hpmcounter17", { .raw_val = RISCV_SYSREG_HPMCOUNTER17 }, "hpmcounter17", { .raw_val = RISCV_SYSREG_HPMCOUNTER17 }, "", 0xC11, {0} , false }, // 345
|
|
{ "hpmcounter18", { .raw_val = RISCV_SYSREG_HPMCOUNTER18 }, "hpmcounter18", { .raw_val = RISCV_SYSREG_HPMCOUNTER18 }, "", 0xC12, {0} , false }, // 346
|
|
{ "hpmcounter19", { .raw_val = RISCV_SYSREG_HPMCOUNTER19 }, "hpmcounter19", { .raw_val = RISCV_SYSREG_HPMCOUNTER19 }, "", 0xC13, {0} , false }, // 347
|
|
{ "hpmcounter20", { .raw_val = RISCV_SYSREG_HPMCOUNTER20 }, "hpmcounter20", { .raw_val = RISCV_SYSREG_HPMCOUNTER20 }, "", 0xC14, {0} , false }, // 348
|
|
{ "hpmcounter21", { .raw_val = RISCV_SYSREG_HPMCOUNTER21 }, "hpmcounter21", { .raw_val = RISCV_SYSREG_HPMCOUNTER21 }, "", 0xC15, {0} , false }, // 349
|
|
{ "hpmcounter22", { .raw_val = RISCV_SYSREG_HPMCOUNTER22 }, "hpmcounter22", { .raw_val = RISCV_SYSREG_HPMCOUNTER22 }, "", 0xC16, {0} , false }, // 350
|
|
{ "hpmcounter23", { .raw_val = RISCV_SYSREG_HPMCOUNTER23 }, "hpmcounter23", { .raw_val = RISCV_SYSREG_HPMCOUNTER23 }, "", 0xC17, {0} , false }, // 351
|
|
{ "hpmcounter24", { .raw_val = RISCV_SYSREG_HPMCOUNTER24 }, "hpmcounter24", { .raw_val = RISCV_SYSREG_HPMCOUNTER24 }, "", 0xC18, {0} , false }, // 352
|
|
{ "hpmcounter25", { .raw_val = RISCV_SYSREG_HPMCOUNTER25 }, "hpmcounter25", { .raw_val = RISCV_SYSREG_HPMCOUNTER25 }, "", 0xC19, {0} , false }, // 353
|
|
{ "hpmcounter26", { .raw_val = RISCV_SYSREG_HPMCOUNTER26 }, "hpmcounter26", { .raw_val = RISCV_SYSREG_HPMCOUNTER26 }, "", 0xC1A, {0} , false }, // 354
|
|
{ "hpmcounter27", { .raw_val = RISCV_SYSREG_HPMCOUNTER27 }, "hpmcounter27", { .raw_val = RISCV_SYSREG_HPMCOUNTER27 }, "", 0xC1B, {0} , false }, // 355
|
|
{ "hpmcounter28", { .raw_val = RISCV_SYSREG_HPMCOUNTER28 }, "hpmcounter28", { .raw_val = RISCV_SYSREG_HPMCOUNTER28 }, "", 0xC1C, {0} , false }, // 356
|
|
{ "hpmcounter29", { .raw_val = RISCV_SYSREG_HPMCOUNTER29 }, "hpmcounter29", { .raw_val = RISCV_SYSREG_HPMCOUNTER29 }, "", 0xC1D, {0} , false }, // 357
|
|
{ "hpmcounter30", { .raw_val = RISCV_SYSREG_HPMCOUNTER30 }, "hpmcounter30", { .raw_val = RISCV_SYSREG_HPMCOUNTER30 }, "", 0xC1E, {0} , false }, // 358
|
|
{ "hpmcounter31", { .raw_val = RISCV_SYSREG_HPMCOUNTER31 }, "hpmcounter31", { .raw_val = RISCV_SYSREG_HPMCOUNTER31 }, "", 0xC1F, {0} , false }, // 359
|
|
{ "vl", { .raw_val = RISCV_SYSREG_VL }, "vl", { .raw_val = RISCV_SYSREG_VL }, "", 0xC20, {0} , false }, // 360
|
|
{ "vtype", { .raw_val = RISCV_SYSREG_VTYPE }, "vtype", { .raw_val = RISCV_SYSREG_VTYPE }, "", 0xC21, {0} , false }, // 361
|
|
{ "vlenb", { .raw_val = RISCV_SYSREG_VLENB }, "vlenb", { .raw_val = RISCV_SYSREG_VLENB }, "", 0xC22, {0} , false }, // 362
|
|
{ "cycleh", { .raw_val = RISCV_SYSREG_CYCLEH }, "cycleh", { .raw_val = RISCV_SYSREG_CYCLEH }, "", 0xC80, {0} , true }, // 363
|
|
{ "timeh", { .raw_val = RISCV_SYSREG_TIMEH }, "timeh", { .raw_val = RISCV_SYSREG_TIMEH }, "", 0xC81, {0} , true }, // 364
|
|
{ "instreth", { .raw_val = RISCV_SYSREG_INSTRETH }, "instreth", { .raw_val = RISCV_SYSREG_INSTRETH }, "", 0xC82, {0} , true }, // 365
|
|
{ "hpmcounter3h", { .raw_val = RISCV_SYSREG_HPMCOUNTER3H }, "hpmcounter3h", { .raw_val = RISCV_SYSREG_HPMCOUNTER3H }, "", 0xC83, {0} , true }, // 366
|
|
{ "hpmcounter4h", { .raw_val = RISCV_SYSREG_HPMCOUNTER4H }, "hpmcounter4h", { .raw_val = RISCV_SYSREG_HPMCOUNTER4H }, "", 0xC84, {0} , true }, // 367
|
|
{ "hpmcounter5h", { .raw_val = RISCV_SYSREG_HPMCOUNTER5H }, "hpmcounter5h", { .raw_val = RISCV_SYSREG_HPMCOUNTER5H }, "", 0xC85, {0} , true }, // 368
|
|
{ "hpmcounter6h", { .raw_val = RISCV_SYSREG_HPMCOUNTER6H }, "hpmcounter6h", { .raw_val = RISCV_SYSREG_HPMCOUNTER6H }, "", 0xC86, {0} , true }, // 369
|
|
{ "hpmcounter7h", { .raw_val = RISCV_SYSREG_HPMCOUNTER7H }, "hpmcounter7h", { .raw_val = RISCV_SYSREG_HPMCOUNTER7H }, "", 0xC87, {0} , true }, // 370
|
|
{ "hpmcounter8h", { .raw_val = RISCV_SYSREG_HPMCOUNTER8H }, "hpmcounter8h", { .raw_val = RISCV_SYSREG_HPMCOUNTER8H }, "", 0xC88, {0} , true }, // 371
|
|
{ "hpmcounter9h", { .raw_val = RISCV_SYSREG_HPMCOUNTER9H }, "hpmcounter9h", { .raw_val = RISCV_SYSREG_HPMCOUNTER9H }, "", 0xC89, {0} , true }, // 372
|
|
{ "hpmcounter10h", { .raw_val = RISCV_SYSREG_HPMCOUNTER10H }, "hpmcounter10h", { .raw_val = RISCV_SYSREG_HPMCOUNTER10H }, "", 0xC8A, {0} , true }, // 373
|
|
{ "hpmcounter11h", { .raw_val = RISCV_SYSREG_HPMCOUNTER11H }, "hpmcounter11h", { .raw_val = RISCV_SYSREG_HPMCOUNTER11H }, "", 0xC8B, {0} , true }, // 374
|
|
{ "hpmcounter12h", { .raw_val = RISCV_SYSREG_HPMCOUNTER12H }, "hpmcounter12h", { .raw_val = RISCV_SYSREG_HPMCOUNTER12H }, "", 0xC8C, {0} , true }, // 375
|
|
{ "hpmcounter13h", { .raw_val = RISCV_SYSREG_HPMCOUNTER13H }, "hpmcounter13h", { .raw_val = RISCV_SYSREG_HPMCOUNTER13H }, "", 0xC8D, {0} , true }, // 376
|
|
{ "hpmcounter14h", { .raw_val = RISCV_SYSREG_HPMCOUNTER14H }, "hpmcounter14h", { .raw_val = RISCV_SYSREG_HPMCOUNTER14H }, "", 0xC8E, {0} , true }, // 377
|
|
{ "hpmcounter15h", { .raw_val = RISCV_SYSREG_HPMCOUNTER15H }, "hpmcounter15h", { .raw_val = RISCV_SYSREG_HPMCOUNTER15H }, "", 0xC8F, {0} , true }, // 378
|
|
{ "hpmcounter16h", { .raw_val = RISCV_SYSREG_HPMCOUNTER16H }, "hpmcounter16h", { .raw_val = RISCV_SYSREG_HPMCOUNTER16H }, "", 0xC90, {0} , true }, // 379
|
|
{ "hpmcounter17h", { .raw_val = RISCV_SYSREG_HPMCOUNTER17H }, "hpmcounter17h", { .raw_val = RISCV_SYSREG_HPMCOUNTER17H }, "", 0xC91, {0} , true }, // 380
|
|
{ "hpmcounter18h", { .raw_val = RISCV_SYSREG_HPMCOUNTER18H }, "hpmcounter18h", { .raw_val = RISCV_SYSREG_HPMCOUNTER18H }, "", 0xC92, {0} , true }, // 381
|
|
{ "hpmcounter19h", { .raw_val = RISCV_SYSREG_HPMCOUNTER19H }, "hpmcounter19h", { .raw_val = RISCV_SYSREG_HPMCOUNTER19H }, "", 0xC93, {0} , true }, // 382
|
|
{ "hpmcounter20h", { .raw_val = RISCV_SYSREG_HPMCOUNTER20H }, "hpmcounter20h", { .raw_val = RISCV_SYSREG_HPMCOUNTER20H }, "", 0xC94, {0} , true }, // 383
|
|
{ "hpmcounter21h", { .raw_val = RISCV_SYSREG_HPMCOUNTER21H }, "hpmcounter21h", { .raw_val = RISCV_SYSREG_HPMCOUNTER21H }, "", 0xC95, {0} , true }, // 384
|
|
{ "hpmcounter22h", { .raw_val = RISCV_SYSREG_HPMCOUNTER22H }, "hpmcounter22h", { .raw_val = RISCV_SYSREG_HPMCOUNTER22H }, "", 0xC96, {0} , true }, // 385
|
|
{ "hpmcounter23h", { .raw_val = RISCV_SYSREG_HPMCOUNTER23H }, "hpmcounter23h", { .raw_val = RISCV_SYSREG_HPMCOUNTER23H }, "", 0xC97, {0} , true }, // 386
|
|
{ "hpmcounter24h", { .raw_val = RISCV_SYSREG_HPMCOUNTER24H }, "hpmcounter24h", { .raw_val = RISCV_SYSREG_HPMCOUNTER24H }, "", 0xC98, {0} , true }, // 387
|
|
{ "hpmcounter25h", { .raw_val = RISCV_SYSREG_HPMCOUNTER25H }, "hpmcounter25h", { .raw_val = RISCV_SYSREG_HPMCOUNTER25H }, "", 0xC99, {0} , true }, // 388
|
|
{ "hpmcounter26h", { .raw_val = RISCV_SYSREG_HPMCOUNTER26H }, "hpmcounter26h", { .raw_val = RISCV_SYSREG_HPMCOUNTER26H }, "", 0xC9A, {0} , true }, // 389
|
|
{ "hpmcounter27h", { .raw_val = RISCV_SYSREG_HPMCOUNTER27H }, "hpmcounter27h", { .raw_val = RISCV_SYSREG_HPMCOUNTER27H }, "", 0xC9B, {0} , true }, // 390
|
|
{ "hpmcounter28h", { .raw_val = RISCV_SYSREG_HPMCOUNTER28H }, "hpmcounter28h", { .raw_val = RISCV_SYSREG_HPMCOUNTER28H }, "", 0xC9C, {0} , true }, // 391
|
|
{ "hpmcounter29h", { .raw_val = RISCV_SYSREG_HPMCOUNTER29H }, "hpmcounter29h", { .raw_val = RISCV_SYSREG_HPMCOUNTER29H }, "", 0xC9D, {0} , true }, // 392
|
|
{ "hpmcounter30h", { .raw_val = RISCV_SYSREG_HPMCOUNTER30H }, "hpmcounter30h", { .raw_val = RISCV_SYSREG_HPMCOUNTER30H }, "", 0xC9E, {0} , true }, // 393
|
|
{ "hpmcounter31h", { .raw_val = RISCV_SYSREG_HPMCOUNTER31H }, "hpmcounter31h", { .raw_val = RISCV_SYSREG_HPMCOUNTER31H }, "", 0xC9F, {0} , true }, // 394
|
|
{ "scountovf", { .raw_val = RISCV_SYSREG_SCOUNTOVF }, "scountovf", { .raw_val = RISCV_SYSREG_SCOUNTOVF }, "", 0xDA0, {0} , false }, // 395
|
|
{ "stopi", { .raw_val = RISCV_SYSREG_STOPI }, "stopi", { .raw_val = RISCV_SYSREG_STOPI }, "", 0xDB0, {0} , false }, // 396
|
|
{ "hgeip", { .raw_val = RISCV_SYSREG_HGEIP }, "hgeip", { .raw_val = RISCV_SYSREG_HGEIP }, "", 0xE12, {0} , false }, // 397
|
|
{ "vstopi", { .raw_val = RISCV_SYSREG_VSTOPI }, "vstopi", { .raw_val = RISCV_SYSREG_VSTOPI }, "", 0xEB0, {0} , false }, // 398
|
|
{ "mvendorid", { .raw_val = RISCV_SYSREG_MVENDORID }, "mvendorid", { .raw_val = RISCV_SYSREG_MVENDORID }, "", 0xF11, {0} , false }, // 399
|
|
{ "marchid", { .raw_val = RISCV_SYSREG_MARCHID }, "marchid", { .raw_val = RISCV_SYSREG_MARCHID }, "", 0xF12, {0} , false }, // 400
|
|
{ "mimpid", { .raw_val = RISCV_SYSREG_MIMPID }, "mimpid", { .raw_val = RISCV_SYSREG_MIMPID }, "", 0xF13, {0} , false }, // 401
|
|
{ "mhartid", { .raw_val = RISCV_SYSREG_MHARTID }, "mhartid", { .raw_val = RISCV_SYSREG_MHARTID }, "", 0xF14, {0} , false }, // 402
|
|
{ "mconfigptr", { .raw_val = RISCV_SYSREG_MCONFIGPTR }, "mconfigptr", { .raw_val = RISCV_SYSREG_MCONFIGPTR }, "", 0xF15, {0} , false }, // 403
|
|
{ "mtopi", { .raw_val = RISCV_SYSREG_MTOPI }, "mtopi", { .raw_val = RISCV_SYSREG_MTOPI }, "", 0xFB0, {0} , false }, // 404
|
|
};
|
|
|
|
const RISCV_SysReg *RISCV_lookupSysRegByEncoding(uint16_t Encoding) {
|
|
static const struct IndexType Index[] = {
|
|
{1,0},
|
|
{2,1},
|
|
{3,2},
|
|
{8,3},
|
|
{9,4},
|
|
{10,5},
|
|
{15,6},
|
|
{21,7},
|
|
{23,8},
|
|
{256,9},
|
|
{260,10},
|
|
{261,11},
|
|
{262,12},
|
|
{266,13},
|
|
{268,14},
|
|
{269,15},
|
|
{270,16},
|
|
{271,17},
|
|
{276,18},
|
|
{320,19},
|
|
{321,20},
|
|
{322,21},
|
|
{323,22},
|
|
{324,23},
|
|
{333,24},
|
|
{336,25},
|
|
{337,26},
|
|
{340,27},
|
|
{348,28},
|
|
{349,29},
|
|
{384,30},
|
|
{512,31},
|
|
{516,32},
|
|
{517,33},
|
|
{532,34},
|
|
{576,35},
|
|
{577,36},
|
|
{578,37},
|
|
{579,38},
|
|
{580,39},
|
|
{589,40},
|
|
{592,41},
|
|
{593,42},
|
|
{596,43},
|
|
{604,44},
|
|
{605,45},
|
|
{640,46},
|
|
{768,47},
|
|
{769,48},
|
|
{770,49},
|
|
{771,50},
|
|
{772,51},
|
|
{773,52},
|
|
{774,53},
|
|
{776,54},
|
|
{777,55},
|
|
{778,56},
|
|
{780,57},
|
|
{781,58},
|
|
{782,59},
|
|
{783,60},
|
|
{784,61},
|
|
{787,62},
|
|
{788,63},
|
|
{792,64},
|
|
{793,65},
|
|
{794,66},
|
|
{796,67},
|
|
{797,68},
|
|
{798,69},
|
|
{799,70},
|
|
{800,71},
|
|
{803,72},
|
|
{804,73},
|
|
{805,74},
|
|
{806,75},
|
|
{807,76},
|
|
{808,77},
|
|
{809,78},
|
|
{810,79},
|
|
{811,80},
|
|
{812,81},
|
|
{813,82},
|
|
{814,83},
|
|
{815,84},
|
|
{816,85},
|
|
{817,86},
|
|
{818,87},
|
|
{819,88},
|
|
{820,89},
|
|
{821,90},
|
|
{822,91},
|
|
{823,92},
|
|
{824,93},
|
|
{825,94},
|
|
{826,95},
|
|
{827,96},
|
|
{828,97},
|
|
{829,98},
|
|
{830,99},
|
|
{831,100},
|
|
{832,101},
|
|
{833,102},
|
|
{834,103},
|
|
{835,104},
|
|
{836,105},
|
|
{842,106},
|
|
{843,107},
|
|
{848,108},
|
|
{849,109},
|
|
{852,110},
|
|
{860,111},
|
|
{928,112},
|
|
{929,113},
|
|
{930,114},
|
|
{931,115},
|
|
{932,116},
|
|
{933,117},
|
|
{934,118},
|
|
{935,119},
|
|
{936,120},
|
|
{937,121},
|
|
{938,122},
|
|
{939,123},
|
|
{940,124},
|
|
{941,125},
|
|
{942,126},
|
|
{943,127},
|
|
{944,128},
|
|
{945,129},
|
|
{946,130},
|
|
{947,131},
|
|
{948,132},
|
|
{949,133},
|
|
{950,134},
|
|
{951,135},
|
|
{952,136},
|
|
{953,137},
|
|
{954,138},
|
|
{955,139},
|
|
{956,140},
|
|
{957,141},
|
|
{958,142},
|
|
{959,143},
|
|
{960,144},
|
|
{961,145},
|
|
{962,146},
|
|
{963,147},
|
|
{964,148},
|
|
{965,149},
|
|
{966,150},
|
|
{967,151},
|
|
{968,152},
|
|
{969,153},
|
|
{970,154},
|
|
{971,155},
|
|
{972,156},
|
|
{973,157},
|
|
{974,158},
|
|
{975,159},
|
|
{976,160},
|
|
{977,161},
|
|
{978,162},
|
|
{979,163},
|
|
{980,164},
|
|
{981,165},
|
|
{982,166},
|
|
{983,167},
|
|
{984,168},
|
|
{985,169},
|
|
{986,170},
|
|
{987,171},
|
|
{988,172},
|
|
{989,173},
|
|
{990,174},
|
|
{991,175},
|
|
{992,176},
|
|
{993,177},
|
|
{994,178},
|
|
{995,179},
|
|
{996,180},
|
|
{997,181},
|
|
{998,182},
|
|
{999,183},
|
|
{1000,184},
|
|
{1001,185},
|
|
{1002,186},
|
|
{1003,187},
|
|
{1004,188},
|
|
{1005,189},
|
|
{1006,190},
|
|
{1007,191},
|
|
{1448,192},
|
|
{1536,193},
|
|
{1538,194},
|
|
{1539,195},
|
|
{1540,196},
|
|
{1541,197},
|
|
{1542,198},
|
|
{1543,199},
|
|
{1544,200},
|
|
{1545,201},
|
|
{1546,202},
|
|
{1548,203},
|
|
{1549,204},
|
|
{1550,205},
|
|
{1551,206},
|
|
{1555,207},
|
|
{1557,208},
|
|
{1560,209},
|
|
{1562,210},
|
|
{1564,211},
|
|
{1565,212},
|
|
{1566,213},
|
|
{1567,214},
|
|
{1603,215},
|
|
{1604,216},
|
|
{1605,217},
|
|
{1606,218},
|
|
{1607,219},
|
|
{1610,220},
|
|
{1621,221},
|
|
{1622,222},
|
|
{1623,223},
|
|
{1664,224},
|
|
{1704,225},
|
|
{1827,226},
|
|
{1828,227},
|
|
{1829,228},
|
|
{1830,229},
|
|
{1831,230},
|
|
{1832,231},
|
|
{1833,232},
|
|
{1834,233},
|
|
{1835,234},
|
|
{1836,235},
|
|
{1837,236},
|
|
{1838,237},
|
|
{1839,238},
|
|
{1840,239},
|
|
{1841,240},
|
|
{1842,241},
|
|
{1843,242},
|
|
{1844,243},
|
|
{1845,244},
|
|
{1846,245},
|
|
{1847,246},
|
|
{1848,247},
|
|
{1849,248},
|
|
{1850,249},
|
|
{1851,250},
|
|
{1852,251},
|
|
{1853,252},
|
|
{1854,253},
|
|
{1855,254},
|
|
{1863,255},
|
|
{1879,256},
|
|
{1952,257},
|
|
{1953,258},
|
|
{1954,259},
|
|
{1955,260},
|
|
{1960,261},
|
|
{1968,262},
|
|
{1969,263},
|
|
{1970,264},
|
|
{1971,265},
|
|
{2816,266},
|
|
{2818,267},
|
|
{2819,268},
|
|
{2820,269},
|
|
{2821,270},
|
|
{2822,271},
|
|
{2823,272},
|
|
{2824,273},
|
|
{2825,274},
|
|
{2826,275},
|
|
{2827,276},
|
|
{2828,277},
|
|
{2829,278},
|
|
{2830,279},
|
|
{2831,280},
|
|
{2832,281},
|
|
{2833,282},
|
|
{2834,283},
|
|
{2835,284},
|
|
{2836,285},
|
|
{2837,286},
|
|
{2838,287},
|
|
{2839,288},
|
|
{2840,289},
|
|
{2841,290},
|
|
{2842,291},
|
|
{2843,292},
|
|
{2844,293},
|
|
{2845,294},
|
|
{2846,295},
|
|
{2847,296},
|
|
{2944,297},
|
|
{2946,298},
|
|
{2947,299},
|
|
{2948,300},
|
|
{2949,301},
|
|
{2950,302},
|
|
{2951,303},
|
|
{2952,304},
|
|
{2953,305},
|
|
{2954,306},
|
|
{2955,307},
|
|
{2956,308},
|
|
{2957,309},
|
|
{2958,310},
|
|
{2959,311},
|
|
{2960,312},
|
|
{2961,313},
|
|
{2962,314},
|
|
{2963,315},
|
|
{2964,316},
|
|
{2965,317},
|
|
{2966,318},
|
|
{2967,319},
|
|
{2968,320},
|
|
{2969,321},
|
|
{2970,322},
|
|
{2971,323},
|
|
{2972,324},
|
|
{2973,325},
|
|
{2974,326},
|
|
{2975,327},
|
|
{3072,328},
|
|
{3073,329},
|
|
{3074,330},
|
|
{3075,331},
|
|
{3076,332},
|
|
{3077,333},
|
|
{3078,334},
|
|
{3079,335},
|
|
{3080,336},
|
|
{3081,337},
|
|
{3082,338},
|
|
{3083,339},
|
|
{3084,340},
|
|
{3085,341},
|
|
{3086,342},
|
|
{3087,343},
|
|
{3088,344},
|
|
{3089,345},
|
|
{3090,346},
|
|
{3091,347},
|
|
{3092,348},
|
|
{3093,349},
|
|
{3094,350},
|
|
{3095,351},
|
|
{3096,352},
|
|
{3097,353},
|
|
{3098,354},
|
|
{3099,355},
|
|
{3100,356},
|
|
{3101,357},
|
|
{3102,358},
|
|
{3103,359},
|
|
{3104,360},
|
|
{3105,361},
|
|
{3106,362},
|
|
{3200,363},
|
|
{3201,364},
|
|
{3202,365},
|
|
{3203,366},
|
|
{3204,367},
|
|
{3205,368},
|
|
{3206,369},
|
|
{3207,370},
|
|
{3208,371},
|
|
{3209,372},
|
|
{3210,373},
|
|
{3211,374},
|
|
{3212,375},
|
|
{3213,376},
|
|
{3214,377},
|
|
{3215,378},
|
|
{3216,379},
|
|
{3217,380},
|
|
{3218,381},
|
|
{3219,382},
|
|
{3220,383},
|
|
{3221,384},
|
|
{3222,385},
|
|
{3223,386},
|
|
{3224,387},
|
|
{3225,388},
|
|
{3226,389},
|
|
{3227,390},
|
|
{3228,391},
|
|
{3229,392},
|
|
{3230,393},
|
|
{3231,394},
|
|
{3488,395},
|
|
{3504,396},
|
|
{3602,397},
|
|
{3760,398},
|
|
{3857,399},
|
|
{3858,400},
|
|
{3859,401},
|
|
{3860,402},
|
|
{3861,403},
|
|
{4016,404},
|
|
};
|
|
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &SysRegsList[Index[i].index];
|
|
}
|
|
|
|
const RISCV_SysReg *RISCV_lookupSysRegByAltName(const char * AltName) {
|
|
static const struct IndexTypeStr Index[] = {
|
|
{ "CYCLE", 328 },
|
|
{ "CYCLEH", 363 },
|
|
{ "DCSR", 262 },
|
|
{ "DPC", 263 },
|
|
{ "DSCRATCH", 264 },
|
|
{ "DSCRATCH1", 265 },
|
|
{ "FCSR", 2 },
|
|
{ "FFLAGS", 0 },
|
|
{ "FRM", 1 },
|
|
{ "HCONTEXT", 225 },
|
|
{ "HCOUNTEREN", 198 },
|
|
{ "HEDELEG", 194 },
|
|
{ "HENVCFG", 202 },
|
|
{ "HENVCFGH", 210 },
|
|
{ "HGATP", 224 },
|
|
{ "HGEIE", 199 },
|
|
{ "HGEIP", 397 },
|
|
{ "HIDELEG", 195 },
|
|
{ "HIDELEGH", 207 },
|
|
{ "HIE", 196 },
|
|
{ "HIP", 216 },
|
|
{ "HPMCOUNTER10", 338 },
|
|
{ "HPMCOUNTER10H", 373 },
|
|
{ "HPMCOUNTER11", 339 },
|
|
{ "HPMCOUNTER11H", 374 },
|
|
{ "HPMCOUNTER12", 340 },
|
|
{ "HPMCOUNTER12H", 375 },
|
|
{ "HPMCOUNTER13", 341 },
|
|
{ "HPMCOUNTER13H", 376 },
|
|
{ "HPMCOUNTER14", 342 },
|
|
{ "HPMCOUNTER14H", 377 },
|
|
{ "HPMCOUNTER15", 343 },
|
|
{ "HPMCOUNTER15H", 378 },
|
|
{ "HPMCOUNTER16", 344 },
|
|
{ "HPMCOUNTER16H", 379 },
|
|
{ "HPMCOUNTER17", 345 },
|
|
{ "HPMCOUNTER17H", 380 },
|
|
{ "HPMCOUNTER18", 346 },
|
|
{ "HPMCOUNTER18H", 381 },
|
|
{ "HPMCOUNTER19", 347 },
|
|
{ "HPMCOUNTER19H", 382 },
|
|
{ "HPMCOUNTER20", 348 },
|
|
{ "HPMCOUNTER20H", 383 },
|
|
{ "HPMCOUNTER21", 349 },
|
|
{ "HPMCOUNTER21H", 384 },
|
|
{ "HPMCOUNTER22", 350 },
|
|
{ "HPMCOUNTER22H", 385 },
|
|
{ "HPMCOUNTER23", 351 },
|
|
{ "HPMCOUNTER23H", 386 },
|
|
{ "HPMCOUNTER24", 352 },
|
|
{ "HPMCOUNTER24H", 387 },
|
|
{ "HPMCOUNTER25", 353 },
|
|
{ "HPMCOUNTER25H", 388 },
|
|
{ "HPMCOUNTER26", 354 },
|
|
{ "HPMCOUNTER26H", 389 },
|
|
{ "HPMCOUNTER27", 355 },
|
|
{ "HPMCOUNTER27H", 390 },
|
|
{ "HPMCOUNTER28", 356 },
|
|
{ "HPMCOUNTER28H", 391 },
|
|
{ "HPMCOUNTER29", 357 },
|
|
{ "HPMCOUNTER29H", 392 },
|
|
{ "HPMCOUNTER3", 331 },
|
|
{ "HPMCOUNTER30", 358 },
|
|
{ "HPMCOUNTER30H", 393 },
|
|
{ "HPMCOUNTER31", 359 },
|
|
{ "HPMCOUNTER31H", 394 },
|
|
{ "HPMCOUNTER3H", 366 },
|
|
{ "HPMCOUNTER4", 332 },
|
|
{ "HPMCOUNTER4H", 367 },
|
|
{ "HPMCOUNTER5", 333 },
|
|
{ "HPMCOUNTER5H", 368 },
|
|
{ "HPMCOUNTER6", 334 },
|
|
{ "HPMCOUNTER6H", 369 },
|
|
{ "HPMCOUNTER7", 335 },
|
|
{ "HPMCOUNTER7H", 370 },
|
|
{ "HPMCOUNTER8", 336 },
|
|
{ "HPMCOUNTER8H", 371 },
|
|
{ "HPMCOUNTER9", 337 },
|
|
{ "HPMCOUNTER9H", 372 },
|
|
{ "HSTATEEN0", 203 },
|
|
{ "HSTATEEN0H", 211 },
|
|
{ "HSTATEEN1", 204 },
|
|
{ "HSTATEEN1H", 212 },
|
|
{ "HSTATEEN2", 205 },
|
|
{ "HSTATEEN2H", 213 },
|
|
{ "HSTATEEN3", 206 },
|
|
{ "HSTATEEN3H", 214 },
|
|
{ "HSTATUS", 193 },
|
|
{ "HTIMEDELTA", 197 },
|
|
{ "HTIMEDELTAH", 208 },
|
|
{ "HTINST", 220 },
|
|
{ "HTVAL", 215 },
|
|
{ "HVICTL", 201 },
|
|
{ "HVIEN", 200 },
|
|
{ "HVIENH", 209 },
|
|
{ "HVIP", 217 },
|
|
{ "HVIPH", 221 },
|
|
{ "HVIPRIO1", 218 },
|
|
{ "HVIPRIO1H", 222 },
|
|
{ "HVIPRIO2", 219 },
|
|
{ "HVIPRIO2H", 223 },
|
|
{ "INSTRET", 330 },
|
|
{ "INSTRETH", 365 },
|
|
{ "JVT", 8 },
|
|
{ "MARCHID", 400 },
|
|
{ "MCAUSE", 103 },
|
|
{ "MCONFIGPTR", 403 },
|
|
{ "MCONTEXT", 261 },
|
|
{ "MCOUNTEREN", 53 },
|
|
{ "MCYCLE", 266 },
|
|
{ "MCYCLEH", 297 },
|
|
{ "MEDELEG", 49 },
|
|
{ "MENVCFG", 56 },
|
|
{ "MENVCFGH", 66 },
|
|
{ "MEPC", 102 },
|
|
{ "MHARTID", 402 },
|
|
{ "MHPMCOUNTER10", 275 },
|
|
{ "MHPMCOUNTER10H", 306 },
|
|
{ "MHPMCOUNTER11", 276 },
|
|
{ "MHPMCOUNTER11H", 307 },
|
|
{ "MHPMCOUNTER12", 277 },
|
|
{ "MHPMCOUNTER12H", 308 },
|
|
{ "MHPMCOUNTER13", 278 },
|
|
{ "MHPMCOUNTER13H", 309 },
|
|
{ "MHPMCOUNTER14", 279 },
|
|
{ "MHPMCOUNTER14H", 310 },
|
|
{ "MHPMCOUNTER15", 280 },
|
|
{ "MHPMCOUNTER15H", 311 },
|
|
{ "MHPMCOUNTER16", 281 },
|
|
{ "MHPMCOUNTER16H", 312 },
|
|
{ "MHPMCOUNTER17", 282 },
|
|
{ "MHPMCOUNTER17H", 313 },
|
|
{ "MHPMCOUNTER18", 283 },
|
|
{ "MHPMCOUNTER18H", 314 },
|
|
{ "MHPMCOUNTER19", 284 },
|
|
{ "MHPMCOUNTER19H", 315 },
|
|
{ "MHPMCOUNTER20", 285 },
|
|
{ "MHPMCOUNTER20H", 316 },
|
|
{ "MHPMCOUNTER21", 286 },
|
|
{ "MHPMCOUNTER21H", 317 },
|
|
{ "MHPMCOUNTER22", 287 },
|
|
{ "MHPMCOUNTER22H", 318 },
|
|
{ "MHPMCOUNTER23", 288 },
|
|
{ "MHPMCOUNTER23H", 319 },
|
|
{ "MHPMCOUNTER24", 289 },
|
|
{ "MHPMCOUNTER24H", 320 },
|
|
{ "MHPMCOUNTER25", 290 },
|
|
{ "MHPMCOUNTER25H", 321 },
|
|
{ "MHPMCOUNTER26", 291 },
|
|
{ "MHPMCOUNTER26H", 322 },
|
|
{ "MHPMCOUNTER27", 292 },
|
|
{ "MHPMCOUNTER27H", 323 },
|
|
{ "MHPMCOUNTER28", 293 },
|
|
{ "MHPMCOUNTER28H", 324 },
|
|
{ "MHPMCOUNTER29", 294 },
|
|
{ "MHPMCOUNTER29H", 325 },
|
|
{ "MHPMCOUNTER3", 268 },
|
|
{ "MHPMCOUNTER30", 295 },
|
|
{ "MHPMCOUNTER30H", 326 },
|
|
{ "MHPMCOUNTER31", 296 },
|
|
{ "MHPMCOUNTER31H", 327 },
|
|
{ "MHPMCOUNTER3H", 299 },
|
|
{ "MHPMCOUNTER4", 269 },
|
|
{ "MHPMCOUNTER4H", 300 },
|
|
{ "MHPMCOUNTER5", 270 },
|
|
{ "MHPMCOUNTER5H", 301 },
|
|
{ "MHPMCOUNTER6", 271 },
|
|
{ "MHPMCOUNTER6H", 302 },
|
|
{ "MHPMCOUNTER7", 272 },
|
|
{ "MHPMCOUNTER7H", 303 },
|
|
{ "MHPMCOUNTER8", 273 },
|
|
{ "MHPMCOUNTER8H", 304 },
|
|
{ "MHPMCOUNTER9", 274 },
|
|
{ "MHPMCOUNTER9H", 305 },
|
|
{ "MHPMEVENT10", 79 },
|
|
{ "MHPMEVENT10H", 233 },
|
|
{ "MHPMEVENT11", 80 },
|
|
{ "MHPMEVENT11H", 234 },
|
|
{ "MHPMEVENT12", 81 },
|
|
{ "MHPMEVENT12H", 235 },
|
|
{ "MHPMEVENT13", 82 },
|
|
{ "MHPMEVENT13H", 236 },
|
|
{ "MHPMEVENT14", 83 },
|
|
{ "MHPMEVENT14H", 237 },
|
|
{ "MHPMEVENT15", 84 },
|
|
{ "MHPMEVENT15H", 238 },
|
|
{ "MHPMEVENT16", 85 },
|
|
{ "MHPMEVENT16H", 239 },
|
|
{ "MHPMEVENT17", 86 },
|
|
{ "MHPMEVENT17H", 240 },
|
|
{ "MHPMEVENT18", 87 },
|
|
{ "MHPMEVENT18H", 241 },
|
|
{ "MHPMEVENT19", 88 },
|
|
{ "MHPMEVENT19H", 242 },
|
|
{ "MHPMEVENT20", 89 },
|
|
{ "MHPMEVENT20H", 243 },
|
|
{ "MHPMEVENT21", 90 },
|
|
{ "MHPMEVENT21H", 244 },
|
|
{ "MHPMEVENT22", 91 },
|
|
{ "MHPMEVENT22H", 245 },
|
|
{ "MHPMEVENT23", 92 },
|
|
{ "MHPMEVENT23H", 246 },
|
|
{ "MHPMEVENT24", 93 },
|
|
{ "MHPMEVENT24H", 247 },
|
|
{ "MHPMEVENT25", 94 },
|
|
{ "MHPMEVENT25H", 248 },
|
|
{ "MHPMEVENT26", 95 },
|
|
{ "MHPMEVENT26H", 249 },
|
|
{ "MHPMEVENT27", 96 },
|
|
{ "MHPMEVENT27H", 250 },
|
|
{ "MHPMEVENT28", 97 },
|
|
{ "MHPMEVENT28H", 251 },
|
|
{ "MHPMEVENT29", 98 },
|
|
{ "MHPMEVENT29H", 252 },
|
|
{ "MHPMEVENT3", 72 },
|
|
{ "MHPMEVENT30", 99 },
|
|
{ "MHPMEVENT30H", 253 },
|
|
{ "MHPMEVENT31", 100 },
|
|
{ "MHPMEVENT31H", 254 },
|
|
{ "MHPMEVENT3H", 226 },
|
|
{ "MHPMEVENT4", 73 },
|
|
{ "MHPMEVENT4H", 227 },
|
|
{ "MHPMEVENT5", 74 },
|
|
{ "MHPMEVENT5H", 228 },
|
|
{ "MHPMEVENT6", 75 },
|
|
{ "MHPMEVENT6H", 229 },
|
|
{ "MHPMEVENT7", 76 },
|
|
{ "MHPMEVENT7H", 230 },
|
|
{ "MHPMEVENT8", 77 },
|
|
{ "MHPMEVENT8H", 231 },
|
|
{ "MHPMEVENT9", 78 },
|
|
{ "MHPMEVENT9H", 232 },
|
|
{ "MIDELEG", 50 },
|
|
{ "MIDELEGH", 62 },
|
|
{ "MIE", 51 },
|
|
{ "MIEH", 63 },
|
|
{ "MIMPID", 401 },
|
|
{ "MINSTRET", 267 },
|
|
{ "MINSTRETH", 298 },
|
|
{ "MIP", 105 },
|
|
{ "MIPH", 110 },
|
|
{ "MIREG", 109 },
|
|
{ "MISA", 48 },
|
|
{ "MISELECT", 108 },
|
|
{ "MSCRATCH", 101 },
|
|
{ "MSECCFG", 255 },
|
|
{ "MSECCFGH", 256 },
|
|
{ "MSTATEEN0", 57 },
|
|
{ "MSTATEEN0H", 67 },
|
|
{ "MSTATEEN1", 58 },
|
|
{ "MSTATEEN1H", 68 },
|
|
{ "MSTATEEN2", 59 },
|
|
{ "MSTATEEN2H", 69 },
|
|
{ "MSTATEEN3", 60 },
|
|
{ "MSTATEEN3H", 70 },
|
|
{ "MSTATUS", 47 },
|
|
{ "MSTATUSH", 61 },
|
|
{ "MTINST", 106 },
|
|
{ "MTOPEI", 111 },
|
|
{ "MTOPI", 404 },
|
|
{ "MTVAL", 104 },
|
|
{ "MTVAL2", 107 },
|
|
{ "MTVEC", 52 },
|
|
{ "MUCOUNTEREN", 71 },
|
|
{ "MVENDORID", 399 },
|
|
{ "MVIEN", 54 },
|
|
{ "MVIENH", 64 },
|
|
{ "MVIP", 55 },
|
|
{ "MVIPH", 65 },
|
|
{ "PMPADDR0", 128 },
|
|
{ "PMPADDR1", 129 },
|
|
{ "PMPADDR10", 138 },
|
|
{ "PMPADDR11", 139 },
|
|
{ "PMPADDR12", 140 },
|
|
{ "PMPADDR13", 141 },
|
|
{ "PMPADDR14", 142 },
|
|
{ "PMPADDR15", 143 },
|
|
{ "PMPADDR16", 144 },
|
|
{ "PMPADDR17", 145 },
|
|
{ "PMPADDR18", 146 },
|
|
{ "PMPADDR19", 147 },
|
|
{ "PMPADDR2", 130 },
|
|
{ "PMPADDR20", 148 },
|
|
{ "PMPADDR21", 149 },
|
|
{ "PMPADDR22", 150 },
|
|
{ "PMPADDR23", 151 },
|
|
{ "PMPADDR24", 152 },
|
|
{ "PMPADDR25", 153 },
|
|
{ "PMPADDR26", 154 },
|
|
{ "PMPADDR27", 155 },
|
|
{ "PMPADDR28", 156 },
|
|
{ "PMPADDR29", 157 },
|
|
{ "PMPADDR3", 131 },
|
|
{ "PMPADDR30", 158 },
|
|
{ "PMPADDR31", 159 },
|
|
{ "PMPADDR32", 160 },
|
|
{ "PMPADDR33", 161 },
|
|
{ "PMPADDR34", 162 },
|
|
{ "PMPADDR35", 163 },
|
|
{ "PMPADDR36", 164 },
|
|
{ "PMPADDR37", 165 },
|
|
{ "PMPADDR38", 166 },
|
|
{ "PMPADDR39", 167 },
|
|
{ "PMPADDR4", 132 },
|
|
{ "PMPADDR40", 168 },
|
|
{ "PMPADDR41", 169 },
|
|
{ "PMPADDR42", 170 },
|
|
{ "PMPADDR43", 171 },
|
|
{ "PMPADDR44", 172 },
|
|
{ "PMPADDR45", 173 },
|
|
{ "PMPADDR46", 174 },
|
|
{ "PMPADDR47", 175 },
|
|
{ "PMPADDR48", 176 },
|
|
{ "PMPADDR49", 177 },
|
|
{ "PMPADDR5", 133 },
|
|
{ "PMPADDR50", 178 },
|
|
{ "PMPADDR51", 179 },
|
|
{ "PMPADDR52", 180 },
|
|
{ "PMPADDR53", 181 },
|
|
{ "PMPADDR54", 182 },
|
|
{ "PMPADDR55", 183 },
|
|
{ "PMPADDR56", 184 },
|
|
{ "PMPADDR57", 185 },
|
|
{ "PMPADDR58", 186 },
|
|
{ "PMPADDR59", 187 },
|
|
{ "PMPADDR6", 134 },
|
|
{ "PMPADDR60", 188 },
|
|
{ "PMPADDR61", 189 },
|
|
{ "PMPADDR62", 190 },
|
|
{ "PMPADDR63", 191 },
|
|
{ "PMPADDR7", 135 },
|
|
{ "PMPADDR8", 136 },
|
|
{ "PMPADDR9", 137 },
|
|
{ "PMPCFG0", 112 },
|
|
{ "PMPCFG1", 113 },
|
|
{ "PMPCFG10", 122 },
|
|
{ "PMPCFG11", 123 },
|
|
{ "PMPCFG12", 124 },
|
|
{ "PMPCFG13", 125 },
|
|
{ "PMPCFG14", 126 },
|
|
{ "PMPCFG15", 127 },
|
|
{ "PMPCFG2", 114 },
|
|
{ "PMPCFG3", 115 },
|
|
{ "PMPCFG4", 116 },
|
|
{ "PMPCFG5", 117 },
|
|
{ "PMPCFG6", 118 },
|
|
{ "PMPCFG7", 119 },
|
|
{ "PMPCFG8", 120 },
|
|
{ "PMPCFG9", 121 },
|
|
{ "SATP", 30 },
|
|
{ "SCAUSE", 21 },
|
|
{ "SCONTEXT", 192 },
|
|
{ "SCOUNTEREN", 12 },
|
|
{ "SCOUNTOVF", 395 },
|
|
{ "SEED", 7 },
|
|
{ "SENVCFG", 13 },
|
|
{ "SEPC", 20 },
|
|
{ "SIE", 10 },
|
|
{ "SIEH", 18 },
|
|
{ "SIP", 23 },
|
|
{ "SIPH", 27 },
|
|
{ "SIREG", 26 },
|
|
{ "SISELECT", 25 },
|
|
{ "SSCRATCH", 19 },
|
|
{ "SSTATEEN0", 14 },
|
|
{ "SSTATEEN1", 15 },
|
|
{ "SSTATEEN2", 16 },
|
|
{ "SSTATEEN3", 17 },
|
|
{ "SSTATUS", 9 },
|
|
{ "STIMECMP", 24 },
|
|
{ "STIMECMPH", 29 },
|
|
{ "STOPEI", 28 },
|
|
{ "STOPI", 396 },
|
|
{ "STVAL", 22 },
|
|
{ "STVEC", 11 },
|
|
{ "TDATA1", 258 },
|
|
{ "TDATA2", 259 },
|
|
{ "TDATA3", 260 },
|
|
{ "TIME", 329 },
|
|
{ "TIMEH", 364 },
|
|
{ "TSELECT", 257 },
|
|
{ "VCSR", 6 },
|
|
{ "VL", 360 },
|
|
{ "VLENB", 362 },
|
|
{ "VSATP", 46 },
|
|
{ "VSCAUSE", 37 },
|
|
{ "VSEPC", 36 },
|
|
{ "VSIE", 32 },
|
|
{ "VSIEH", 34 },
|
|
{ "VSIP", 39 },
|
|
{ "VSIPH", 43 },
|
|
{ "VSIREG", 42 },
|
|
{ "VSISELECT", 41 },
|
|
{ "VSSCRATCH", 35 },
|
|
{ "VSSTATUS", 31 },
|
|
{ "VSTART", 3 },
|
|
{ "VSTIMECMP", 40 },
|
|
{ "VSTIMECMPH", 45 },
|
|
{ "VSTOPEI", 44 },
|
|
{ "VSTOPI", 398 },
|
|
{ "VSTVAL", 38 },
|
|
{ "VSTVEC", 33 },
|
|
{ "VTYPE", 361 },
|
|
{ "VXRM", 5 },
|
|
{ "VXSAT", 4 },
|
|
};
|
|
|
|
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), AltName);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &SysRegsList[Index[i].index];
|
|
}
|
|
|
|
const RISCV_SysReg *RISCV_lookupSysRegByDeprecatedName(const char * DeprecatedName) {
|
|
static const struct IndexTypeStr Index[] = {
|
|
{ "", 0 },
|
|
{ "", 1 },
|
|
{ "", 2 },
|
|
{ "", 3 },
|
|
{ "", 4 },
|
|
{ "", 5 },
|
|
{ "", 6 },
|
|
{ "", 7 },
|
|
{ "", 8 },
|
|
{ "", 9 },
|
|
{ "", 10 },
|
|
{ "", 11 },
|
|
{ "", 12 },
|
|
{ "", 13 },
|
|
{ "", 14 },
|
|
{ "", 15 },
|
|
{ "", 16 },
|
|
{ "", 17 },
|
|
{ "", 18 },
|
|
{ "", 19 },
|
|
{ "", 20 },
|
|
{ "", 21 },
|
|
{ "", 23 },
|
|
{ "", 24 },
|
|
{ "", 25 },
|
|
{ "", 26 },
|
|
{ "", 27 },
|
|
{ "", 28 },
|
|
{ "", 29 },
|
|
{ "", 31 },
|
|
{ "", 32 },
|
|
{ "", 33 },
|
|
{ "", 34 },
|
|
{ "", 35 },
|
|
{ "", 36 },
|
|
{ "", 37 },
|
|
{ "", 38 },
|
|
{ "", 39 },
|
|
{ "", 40 },
|
|
{ "", 41 },
|
|
{ "", 42 },
|
|
{ "", 43 },
|
|
{ "", 44 },
|
|
{ "", 45 },
|
|
{ "", 46 },
|
|
{ "", 47 },
|
|
{ "", 48 },
|
|
{ "", 49 },
|
|
{ "", 50 },
|
|
{ "", 51 },
|
|
{ "", 52 },
|
|
{ "", 53 },
|
|
{ "", 54 },
|
|
{ "", 55 },
|
|
{ "", 56 },
|
|
{ "", 57 },
|
|
{ "", 58 },
|
|
{ "", 59 },
|
|
{ "", 60 },
|
|
{ "", 61 },
|
|
{ "", 62 },
|
|
{ "", 63 },
|
|
{ "", 64 },
|
|
{ "", 65 },
|
|
{ "", 66 },
|
|
{ "", 67 },
|
|
{ "", 68 },
|
|
{ "", 69 },
|
|
{ "", 70 },
|
|
{ "", 71 },
|
|
{ "", 72 },
|
|
{ "", 73 },
|
|
{ "", 74 },
|
|
{ "", 75 },
|
|
{ "", 76 },
|
|
{ "", 77 },
|
|
{ "", 78 },
|
|
{ "", 79 },
|
|
{ "", 80 },
|
|
{ "", 81 },
|
|
{ "", 82 },
|
|
{ "", 83 },
|
|
{ "", 84 },
|
|
{ "", 85 },
|
|
{ "", 86 },
|
|
{ "", 87 },
|
|
{ "", 88 },
|
|
{ "", 89 },
|
|
{ "", 90 },
|
|
{ "", 91 },
|
|
{ "", 92 },
|
|
{ "", 93 },
|
|
{ "", 94 },
|
|
{ "", 95 },
|
|
{ "", 96 },
|
|
{ "", 97 },
|
|
{ "", 98 },
|
|
{ "", 99 },
|
|
{ "", 100 },
|
|
{ "", 101 },
|
|
{ "", 102 },
|
|
{ "", 103 },
|
|
{ "", 105 },
|
|
{ "", 106 },
|
|
{ "", 107 },
|
|
{ "", 108 },
|
|
{ "", 109 },
|
|
{ "", 110 },
|
|
{ "", 111 },
|
|
{ "", 112 },
|
|
{ "", 113 },
|
|
{ "", 114 },
|
|
{ "", 115 },
|
|
{ "", 116 },
|
|
{ "", 117 },
|
|
{ "", 118 },
|
|
{ "", 119 },
|
|
{ "", 120 },
|
|
{ "", 121 },
|
|
{ "", 122 },
|
|
{ "", 123 },
|
|
{ "", 124 },
|
|
{ "", 125 },
|
|
{ "", 126 },
|
|
{ "", 127 },
|
|
{ "", 128 },
|
|
{ "", 129 },
|
|
{ "", 130 },
|
|
{ "", 131 },
|
|
{ "", 132 },
|
|
{ "", 133 },
|
|
{ "", 134 },
|
|
{ "", 135 },
|
|
{ "", 136 },
|
|
{ "", 137 },
|
|
{ "", 138 },
|
|
{ "", 139 },
|
|
{ "", 140 },
|
|
{ "", 141 },
|
|
{ "", 142 },
|
|
{ "", 143 },
|
|
{ "", 144 },
|
|
{ "", 145 },
|
|
{ "", 146 },
|
|
{ "", 147 },
|
|
{ "", 148 },
|
|
{ "", 149 },
|
|
{ "", 150 },
|
|
{ "", 151 },
|
|
{ "", 152 },
|
|
{ "", 153 },
|
|
{ "", 154 },
|
|
{ "", 155 },
|
|
{ "", 156 },
|
|
{ "", 157 },
|
|
{ "", 158 },
|
|
{ "", 159 },
|
|
{ "", 160 },
|
|
{ "", 161 },
|
|
{ "", 162 },
|
|
{ "", 163 },
|
|
{ "", 164 },
|
|
{ "", 165 },
|
|
{ "", 166 },
|
|
{ "", 167 },
|
|
{ "", 168 },
|
|
{ "", 169 },
|
|
{ "", 170 },
|
|
{ "", 171 },
|
|
{ "", 172 },
|
|
{ "", 173 },
|
|
{ "", 174 },
|
|
{ "", 175 },
|
|
{ "", 176 },
|
|
{ "", 177 },
|
|
{ "", 178 },
|
|
{ "", 179 },
|
|
{ "", 180 },
|
|
{ "", 181 },
|
|
{ "", 182 },
|
|
{ "", 183 },
|
|
{ "", 184 },
|
|
{ "", 185 },
|
|
{ "", 186 },
|
|
{ "", 187 },
|
|
{ "", 188 },
|
|
{ "", 189 },
|
|
{ "", 190 },
|
|
{ "", 191 },
|
|
{ "", 192 },
|
|
{ "", 193 },
|
|
{ "", 194 },
|
|
{ "", 195 },
|
|
{ "", 196 },
|
|
{ "", 197 },
|
|
{ "", 198 },
|
|
{ "", 199 },
|
|
{ "", 200 },
|
|
{ "", 201 },
|
|
{ "", 202 },
|
|
{ "", 203 },
|
|
{ "", 204 },
|
|
{ "", 205 },
|
|
{ "", 206 },
|
|
{ "", 207 },
|
|
{ "", 208 },
|
|
{ "", 209 },
|
|
{ "", 210 },
|
|
{ "", 211 },
|
|
{ "", 212 },
|
|
{ "", 213 },
|
|
{ "", 214 },
|
|
{ "", 215 },
|
|
{ "", 216 },
|
|
{ "", 217 },
|
|
{ "", 218 },
|
|
{ "", 219 },
|
|
{ "", 220 },
|
|
{ "", 221 },
|
|
{ "", 222 },
|
|
{ "", 223 },
|
|
{ "", 224 },
|
|
{ "", 225 },
|
|
{ "", 226 },
|
|
{ "", 227 },
|
|
{ "", 228 },
|
|
{ "", 229 },
|
|
{ "", 230 },
|
|
{ "", 231 },
|
|
{ "", 232 },
|
|
{ "", 233 },
|
|
{ "", 234 },
|
|
{ "", 235 },
|
|
{ "", 236 },
|
|
{ "", 237 },
|
|
{ "", 238 },
|
|
{ "", 239 },
|
|
{ "", 240 },
|
|
{ "", 241 },
|
|
{ "", 242 },
|
|
{ "", 243 },
|
|
{ "", 244 },
|
|
{ "", 245 },
|
|
{ "", 246 },
|
|
{ "", 247 },
|
|
{ "", 248 },
|
|
{ "", 249 },
|
|
{ "", 250 },
|
|
{ "", 251 },
|
|
{ "", 252 },
|
|
{ "", 253 },
|
|
{ "", 254 },
|
|
{ "", 255 },
|
|
{ "", 256 },
|
|
{ "", 257 },
|
|
{ "", 258 },
|
|
{ "", 259 },
|
|
{ "", 260 },
|
|
{ "", 261 },
|
|
{ "", 262 },
|
|
{ "", 263 },
|
|
{ "", 264 },
|
|
{ "", 265 },
|
|
{ "", 266 },
|
|
{ "", 267 },
|
|
{ "", 268 },
|
|
{ "", 269 },
|
|
{ "", 270 },
|
|
{ "", 271 },
|
|
{ "", 272 },
|
|
{ "", 273 },
|
|
{ "", 274 },
|
|
{ "", 275 },
|
|
{ "", 276 },
|
|
{ "", 277 },
|
|
{ "", 278 },
|
|
{ "", 279 },
|
|
{ "", 280 },
|
|
{ "", 281 },
|
|
{ "", 282 },
|
|
{ "", 283 },
|
|
{ "", 284 },
|
|
{ "", 285 },
|
|
{ "", 286 },
|
|
{ "", 287 },
|
|
{ "", 288 },
|
|
{ "", 289 },
|
|
{ "", 290 },
|
|
{ "", 291 },
|
|
{ "", 292 },
|
|
{ "", 293 },
|
|
{ "", 294 },
|
|
{ "", 295 },
|
|
{ "", 296 },
|
|
{ "", 297 },
|
|
{ "", 298 },
|
|
{ "", 299 },
|
|
{ "", 300 },
|
|
{ "", 301 },
|
|
{ "", 302 },
|
|
{ "", 303 },
|
|
{ "", 304 },
|
|
{ "", 305 },
|
|
{ "", 306 },
|
|
{ "", 307 },
|
|
{ "", 308 },
|
|
{ "", 309 },
|
|
{ "", 310 },
|
|
{ "", 311 },
|
|
{ "", 312 },
|
|
{ "", 313 },
|
|
{ "", 314 },
|
|
{ "", 315 },
|
|
{ "", 316 },
|
|
{ "", 317 },
|
|
{ "", 318 },
|
|
{ "", 319 },
|
|
{ "", 320 },
|
|
{ "", 321 },
|
|
{ "", 322 },
|
|
{ "", 323 },
|
|
{ "", 324 },
|
|
{ "", 325 },
|
|
{ "", 326 },
|
|
{ "", 327 },
|
|
{ "", 328 },
|
|
{ "", 329 },
|
|
{ "", 330 },
|
|
{ "", 331 },
|
|
{ "", 332 },
|
|
{ "", 333 },
|
|
{ "", 334 },
|
|
{ "", 335 },
|
|
{ "", 336 },
|
|
{ "", 337 },
|
|
{ "", 338 },
|
|
{ "", 339 },
|
|
{ "", 340 },
|
|
{ "", 341 },
|
|
{ "", 342 },
|
|
{ "", 343 },
|
|
{ "", 344 },
|
|
{ "", 345 },
|
|
{ "", 346 },
|
|
{ "", 347 },
|
|
{ "", 348 },
|
|
{ "", 349 },
|
|
{ "", 350 },
|
|
{ "", 351 },
|
|
{ "", 352 },
|
|
{ "", 353 },
|
|
{ "", 354 },
|
|
{ "", 355 },
|
|
{ "", 356 },
|
|
{ "", 357 },
|
|
{ "", 358 },
|
|
{ "", 359 },
|
|
{ "", 360 },
|
|
{ "", 361 },
|
|
{ "", 362 },
|
|
{ "", 363 },
|
|
{ "", 364 },
|
|
{ "", 365 },
|
|
{ "", 366 },
|
|
{ "", 367 },
|
|
{ "", 368 },
|
|
{ "", 369 },
|
|
{ "", 370 },
|
|
{ "", 371 },
|
|
{ "", 372 },
|
|
{ "", 373 },
|
|
{ "", 374 },
|
|
{ "", 375 },
|
|
{ "", 376 },
|
|
{ "", 377 },
|
|
{ "", 378 },
|
|
{ "", 379 },
|
|
{ "", 380 },
|
|
{ "", 381 },
|
|
{ "", 382 },
|
|
{ "", 383 },
|
|
{ "", 384 },
|
|
{ "", 385 },
|
|
{ "", 386 },
|
|
{ "", 387 },
|
|
{ "", 388 },
|
|
{ "", 389 },
|
|
{ "", 390 },
|
|
{ "", 391 },
|
|
{ "", 392 },
|
|
{ "", 393 },
|
|
{ "", 394 },
|
|
{ "", 395 },
|
|
{ "", 396 },
|
|
{ "", 397 },
|
|
{ "", 398 },
|
|
{ "", 399 },
|
|
{ "", 400 },
|
|
{ "", 401 },
|
|
{ "", 402 },
|
|
{ "", 403 },
|
|
{ "", 404 },
|
|
{ "MBADADDR", 104 },
|
|
{ "SBADADDR", 22 },
|
|
{ "SPTBR", 30 },
|
|
};
|
|
|
|
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), DeprecatedName);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &SysRegsList[Index[i].index];
|
|
}
|
|
|
|
const RISCV_SysReg *RISCV_lookupSysRegByName(const char * Name) {
|
|
static const struct IndexTypeStr Index[] = {
|
|
{ "CYCLE", 328 },
|
|
{ "CYCLEH", 363 },
|
|
{ "DCSR", 262 },
|
|
{ "DPC", 263 },
|
|
{ "DSCRATCH0", 264 },
|
|
{ "DSCRATCH1", 265 },
|
|
{ "FCSR", 2 },
|
|
{ "FFLAGS", 0 },
|
|
{ "FRM", 1 },
|
|
{ "HCONTEXT", 225 },
|
|
{ "HCOUNTEREN", 198 },
|
|
{ "HEDELEG", 194 },
|
|
{ "HENVCFG", 202 },
|
|
{ "HENVCFGH", 210 },
|
|
{ "HGATP", 224 },
|
|
{ "HGEIE", 199 },
|
|
{ "HGEIP", 397 },
|
|
{ "HIDELEG", 195 },
|
|
{ "HIDELEGH", 207 },
|
|
{ "HIE", 196 },
|
|
{ "HIP", 216 },
|
|
{ "HPMCOUNTER10", 338 },
|
|
{ "HPMCOUNTER10H", 373 },
|
|
{ "HPMCOUNTER11", 339 },
|
|
{ "HPMCOUNTER11H", 374 },
|
|
{ "HPMCOUNTER12", 340 },
|
|
{ "HPMCOUNTER12H", 375 },
|
|
{ "HPMCOUNTER13", 341 },
|
|
{ "HPMCOUNTER13H", 376 },
|
|
{ "HPMCOUNTER14", 342 },
|
|
{ "HPMCOUNTER14H", 377 },
|
|
{ "HPMCOUNTER15", 343 },
|
|
{ "HPMCOUNTER15H", 378 },
|
|
{ "HPMCOUNTER16", 344 },
|
|
{ "HPMCOUNTER16H", 379 },
|
|
{ "HPMCOUNTER17", 345 },
|
|
{ "HPMCOUNTER17H", 380 },
|
|
{ "HPMCOUNTER18", 346 },
|
|
{ "HPMCOUNTER18H", 381 },
|
|
{ "HPMCOUNTER19", 347 },
|
|
{ "HPMCOUNTER19H", 382 },
|
|
{ "HPMCOUNTER20", 348 },
|
|
{ "HPMCOUNTER20H", 383 },
|
|
{ "HPMCOUNTER21", 349 },
|
|
{ "HPMCOUNTER21H", 384 },
|
|
{ "HPMCOUNTER22", 350 },
|
|
{ "HPMCOUNTER22H", 385 },
|
|
{ "HPMCOUNTER23", 351 },
|
|
{ "HPMCOUNTER23H", 386 },
|
|
{ "HPMCOUNTER24", 352 },
|
|
{ "HPMCOUNTER24H", 387 },
|
|
{ "HPMCOUNTER25", 353 },
|
|
{ "HPMCOUNTER25H", 388 },
|
|
{ "HPMCOUNTER26", 354 },
|
|
{ "HPMCOUNTER26H", 389 },
|
|
{ "HPMCOUNTER27", 355 },
|
|
{ "HPMCOUNTER27H", 390 },
|
|
{ "HPMCOUNTER28", 356 },
|
|
{ "HPMCOUNTER28H", 391 },
|
|
{ "HPMCOUNTER29", 357 },
|
|
{ "HPMCOUNTER29H", 392 },
|
|
{ "HPMCOUNTER3", 331 },
|
|
{ "HPMCOUNTER30", 358 },
|
|
{ "HPMCOUNTER30H", 393 },
|
|
{ "HPMCOUNTER31", 359 },
|
|
{ "HPMCOUNTER31H", 394 },
|
|
{ "HPMCOUNTER3H", 366 },
|
|
{ "HPMCOUNTER4", 332 },
|
|
{ "HPMCOUNTER4H", 367 },
|
|
{ "HPMCOUNTER5", 333 },
|
|
{ "HPMCOUNTER5H", 368 },
|
|
{ "HPMCOUNTER6", 334 },
|
|
{ "HPMCOUNTER6H", 369 },
|
|
{ "HPMCOUNTER7", 335 },
|
|
{ "HPMCOUNTER7H", 370 },
|
|
{ "HPMCOUNTER8", 336 },
|
|
{ "HPMCOUNTER8H", 371 },
|
|
{ "HPMCOUNTER9", 337 },
|
|
{ "HPMCOUNTER9H", 372 },
|
|
{ "HSTATEEN0", 203 },
|
|
{ "HSTATEEN0H", 211 },
|
|
{ "HSTATEEN1", 204 },
|
|
{ "HSTATEEN1H", 212 },
|
|
{ "HSTATEEN2", 205 },
|
|
{ "HSTATEEN2H", 213 },
|
|
{ "HSTATEEN3", 206 },
|
|
{ "HSTATEEN3H", 214 },
|
|
{ "HSTATUS", 193 },
|
|
{ "HTIMEDELTA", 197 },
|
|
{ "HTIMEDELTAH", 208 },
|
|
{ "HTINST", 220 },
|
|
{ "HTVAL", 215 },
|
|
{ "HVICTL", 201 },
|
|
{ "HVIEN", 200 },
|
|
{ "HVIENH", 209 },
|
|
{ "HVIP", 217 },
|
|
{ "HVIPH", 221 },
|
|
{ "HVIPRIO1", 218 },
|
|
{ "HVIPRIO1H", 222 },
|
|
{ "HVIPRIO2", 219 },
|
|
{ "HVIPRIO2H", 223 },
|
|
{ "INSTRET", 330 },
|
|
{ "INSTRETH", 365 },
|
|
{ "JVT", 8 },
|
|
{ "MARCHID", 400 },
|
|
{ "MCAUSE", 103 },
|
|
{ "MCONFIGPTR", 403 },
|
|
{ "MCONTEXT", 261 },
|
|
{ "MCOUNTEREN", 53 },
|
|
{ "MCOUNTINHIBIT", 71 },
|
|
{ "MCYCLE", 266 },
|
|
{ "MCYCLEH", 297 },
|
|
{ "MEDELEG", 49 },
|
|
{ "MENVCFG", 56 },
|
|
{ "MENVCFGH", 66 },
|
|
{ "MEPC", 102 },
|
|
{ "MHARTID", 402 },
|
|
{ "MHPMCOUNTER10", 275 },
|
|
{ "MHPMCOUNTER10H", 306 },
|
|
{ "MHPMCOUNTER11", 276 },
|
|
{ "MHPMCOUNTER11H", 307 },
|
|
{ "MHPMCOUNTER12", 277 },
|
|
{ "MHPMCOUNTER12H", 308 },
|
|
{ "MHPMCOUNTER13", 278 },
|
|
{ "MHPMCOUNTER13H", 309 },
|
|
{ "MHPMCOUNTER14", 279 },
|
|
{ "MHPMCOUNTER14H", 310 },
|
|
{ "MHPMCOUNTER15", 280 },
|
|
{ "MHPMCOUNTER15H", 311 },
|
|
{ "MHPMCOUNTER16", 281 },
|
|
{ "MHPMCOUNTER16H", 312 },
|
|
{ "MHPMCOUNTER17", 282 },
|
|
{ "MHPMCOUNTER17H", 313 },
|
|
{ "MHPMCOUNTER18", 283 },
|
|
{ "MHPMCOUNTER18H", 314 },
|
|
{ "MHPMCOUNTER19", 284 },
|
|
{ "MHPMCOUNTER19H", 315 },
|
|
{ "MHPMCOUNTER20", 285 },
|
|
{ "MHPMCOUNTER20H", 316 },
|
|
{ "MHPMCOUNTER21", 286 },
|
|
{ "MHPMCOUNTER21H", 317 },
|
|
{ "MHPMCOUNTER22", 287 },
|
|
{ "MHPMCOUNTER22H", 318 },
|
|
{ "MHPMCOUNTER23", 288 },
|
|
{ "MHPMCOUNTER23H", 319 },
|
|
{ "MHPMCOUNTER24", 289 },
|
|
{ "MHPMCOUNTER24H", 320 },
|
|
{ "MHPMCOUNTER25", 290 },
|
|
{ "MHPMCOUNTER25H", 321 },
|
|
{ "MHPMCOUNTER26", 291 },
|
|
{ "MHPMCOUNTER26H", 322 },
|
|
{ "MHPMCOUNTER27", 292 },
|
|
{ "MHPMCOUNTER27H", 323 },
|
|
{ "MHPMCOUNTER28", 293 },
|
|
{ "MHPMCOUNTER28H", 324 },
|
|
{ "MHPMCOUNTER29", 294 },
|
|
{ "MHPMCOUNTER29H", 325 },
|
|
{ "MHPMCOUNTER3", 268 },
|
|
{ "MHPMCOUNTER30", 295 },
|
|
{ "MHPMCOUNTER30H", 326 },
|
|
{ "MHPMCOUNTER31", 296 },
|
|
{ "MHPMCOUNTER31H", 327 },
|
|
{ "MHPMCOUNTER3H", 299 },
|
|
{ "MHPMCOUNTER4", 269 },
|
|
{ "MHPMCOUNTER4H", 300 },
|
|
{ "MHPMCOUNTER5", 270 },
|
|
{ "MHPMCOUNTER5H", 301 },
|
|
{ "MHPMCOUNTER6", 271 },
|
|
{ "MHPMCOUNTER6H", 302 },
|
|
{ "MHPMCOUNTER7", 272 },
|
|
{ "MHPMCOUNTER7H", 303 },
|
|
{ "MHPMCOUNTER8", 273 },
|
|
{ "MHPMCOUNTER8H", 304 },
|
|
{ "MHPMCOUNTER9", 274 },
|
|
{ "MHPMCOUNTER9H", 305 },
|
|
{ "MHPMEVENT10", 79 },
|
|
{ "MHPMEVENT10H", 233 },
|
|
{ "MHPMEVENT11", 80 },
|
|
{ "MHPMEVENT11H", 234 },
|
|
{ "MHPMEVENT12", 81 },
|
|
{ "MHPMEVENT12H", 235 },
|
|
{ "MHPMEVENT13", 82 },
|
|
{ "MHPMEVENT13H", 236 },
|
|
{ "MHPMEVENT14", 83 },
|
|
{ "MHPMEVENT14H", 237 },
|
|
{ "MHPMEVENT15", 84 },
|
|
{ "MHPMEVENT15H", 238 },
|
|
{ "MHPMEVENT16", 85 },
|
|
{ "MHPMEVENT16H", 239 },
|
|
{ "MHPMEVENT17", 86 },
|
|
{ "MHPMEVENT17H", 240 },
|
|
{ "MHPMEVENT18", 87 },
|
|
{ "MHPMEVENT18H", 241 },
|
|
{ "MHPMEVENT19", 88 },
|
|
{ "MHPMEVENT19H", 242 },
|
|
{ "MHPMEVENT20", 89 },
|
|
{ "MHPMEVENT20H", 243 },
|
|
{ "MHPMEVENT21", 90 },
|
|
{ "MHPMEVENT21H", 244 },
|
|
{ "MHPMEVENT22", 91 },
|
|
{ "MHPMEVENT22H", 245 },
|
|
{ "MHPMEVENT23", 92 },
|
|
{ "MHPMEVENT23H", 246 },
|
|
{ "MHPMEVENT24", 93 },
|
|
{ "MHPMEVENT24H", 247 },
|
|
{ "MHPMEVENT25", 94 },
|
|
{ "MHPMEVENT25H", 248 },
|
|
{ "MHPMEVENT26", 95 },
|
|
{ "MHPMEVENT26H", 249 },
|
|
{ "MHPMEVENT27", 96 },
|
|
{ "MHPMEVENT27H", 250 },
|
|
{ "MHPMEVENT28", 97 },
|
|
{ "MHPMEVENT28H", 251 },
|
|
{ "MHPMEVENT29", 98 },
|
|
{ "MHPMEVENT29H", 252 },
|
|
{ "MHPMEVENT3", 72 },
|
|
{ "MHPMEVENT30", 99 },
|
|
{ "MHPMEVENT30H", 253 },
|
|
{ "MHPMEVENT31", 100 },
|
|
{ "MHPMEVENT31H", 254 },
|
|
{ "MHPMEVENT3H", 226 },
|
|
{ "MHPMEVENT4", 73 },
|
|
{ "MHPMEVENT4H", 227 },
|
|
{ "MHPMEVENT5", 74 },
|
|
{ "MHPMEVENT5H", 228 },
|
|
{ "MHPMEVENT6", 75 },
|
|
{ "MHPMEVENT6H", 229 },
|
|
{ "MHPMEVENT7", 76 },
|
|
{ "MHPMEVENT7H", 230 },
|
|
{ "MHPMEVENT8", 77 },
|
|
{ "MHPMEVENT8H", 231 },
|
|
{ "MHPMEVENT9", 78 },
|
|
{ "MHPMEVENT9H", 232 },
|
|
{ "MIDELEG", 50 },
|
|
{ "MIDELEGH", 62 },
|
|
{ "MIE", 51 },
|
|
{ "MIEH", 63 },
|
|
{ "MIMPID", 401 },
|
|
{ "MINSTRET", 267 },
|
|
{ "MINSTRETH", 298 },
|
|
{ "MIP", 105 },
|
|
{ "MIPH", 110 },
|
|
{ "MIREG", 109 },
|
|
{ "MISA", 48 },
|
|
{ "MISELECT", 108 },
|
|
{ "MSCRATCH", 101 },
|
|
{ "MSECCFG", 255 },
|
|
{ "MSECCFGH", 256 },
|
|
{ "MSTATEEN0", 57 },
|
|
{ "MSTATEEN0H", 67 },
|
|
{ "MSTATEEN1", 58 },
|
|
{ "MSTATEEN1H", 68 },
|
|
{ "MSTATEEN2", 59 },
|
|
{ "MSTATEEN2H", 69 },
|
|
{ "MSTATEEN3", 60 },
|
|
{ "MSTATEEN3H", 70 },
|
|
{ "MSTATUS", 47 },
|
|
{ "MSTATUSH", 61 },
|
|
{ "MTINST", 106 },
|
|
{ "MTOPEI", 111 },
|
|
{ "MTOPI", 404 },
|
|
{ "MTVAL", 104 },
|
|
{ "MTVAL2", 107 },
|
|
{ "MTVEC", 52 },
|
|
{ "MVENDORID", 399 },
|
|
{ "MVIEN", 54 },
|
|
{ "MVIENH", 64 },
|
|
{ "MVIP", 55 },
|
|
{ "MVIPH", 65 },
|
|
{ "PMPADDR0", 128 },
|
|
{ "PMPADDR1", 129 },
|
|
{ "PMPADDR10", 138 },
|
|
{ "PMPADDR11", 139 },
|
|
{ "PMPADDR12", 140 },
|
|
{ "PMPADDR13", 141 },
|
|
{ "PMPADDR14", 142 },
|
|
{ "PMPADDR15", 143 },
|
|
{ "PMPADDR16", 144 },
|
|
{ "PMPADDR17", 145 },
|
|
{ "PMPADDR18", 146 },
|
|
{ "PMPADDR19", 147 },
|
|
{ "PMPADDR2", 130 },
|
|
{ "PMPADDR20", 148 },
|
|
{ "PMPADDR21", 149 },
|
|
{ "PMPADDR22", 150 },
|
|
{ "PMPADDR23", 151 },
|
|
{ "PMPADDR24", 152 },
|
|
{ "PMPADDR25", 153 },
|
|
{ "PMPADDR26", 154 },
|
|
{ "PMPADDR27", 155 },
|
|
{ "PMPADDR28", 156 },
|
|
{ "PMPADDR29", 157 },
|
|
{ "PMPADDR3", 131 },
|
|
{ "PMPADDR30", 158 },
|
|
{ "PMPADDR31", 159 },
|
|
{ "PMPADDR32", 160 },
|
|
{ "PMPADDR33", 161 },
|
|
{ "PMPADDR34", 162 },
|
|
{ "PMPADDR35", 163 },
|
|
{ "PMPADDR36", 164 },
|
|
{ "PMPADDR37", 165 },
|
|
{ "PMPADDR38", 166 },
|
|
{ "PMPADDR39", 167 },
|
|
{ "PMPADDR4", 132 },
|
|
{ "PMPADDR40", 168 },
|
|
{ "PMPADDR41", 169 },
|
|
{ "PMPADDR42", 170 },
|
|
{ "PMPADDR43", 171 },
|
|
{ "PMPADDR44", 172 },
|
|
{ "PMPADDR45", 173 },
|
|
{ "PMPADDR46", 174 },
|
|
{ "PMPADDR47", 175 },
|
|
{ "PMPADDR48", 176 },
|
|
{ "PMPADDR49", 177 },
|
|
{ "PMPADDR5", 133 },
|
|
{ "PMPADDR50", 178 },
|
|
{ "PMPADDR51", 179 },
|
|
{ "PMPADDR52", 180 },
|
|
{ "PMPADDR53", 181 },
|
|
{ "PMPADDR54", 182 },
|
|
{ "PMPADDR55", 183 },
|
|
{ "PMPADDR56", 184 },
|
|
{ "PMPADDR57", 185 },
|
|
{ "PMPADDR58", 186 },
|
|
{ "PMPADDR59", 187 },
|
|
{ "PMPADDR6", 134 },
|
|
{ "PMPADDR60", 188 },
|
|
{ "PMPADDR61", 189 },
|
|
{ "PMPADDR62", 190 },
|
|
{ "PMPADDR63", 191 },
|
|
{ "PMPADDR7", 135 },
|
|
{ "PMPADDR8", 136 },
|
|
{ "PMPADDR9", 137 },
|
|
{ "PMPCFG0", 112 },
|
|
{ "PMPCFG1", 113 },
|
|
{ "PMPCFG10", 122 },
|
|
{ "PMPCFG11", 123 },
|
|
{ "PMPCFG12", 124 },
|
|
{ "PMPCFG13", 125 },
|
|
{ "PMPCFG14", 126 },
|
|
{ "PMPCFG15", 127 },
|
|
{ "PMPCFG2", 114 },
|
|
{ "PMPCFG3", 115 },
|
|
{ "PMPCFG4", 116 },
|
|
{ "PMPCFG5", 117 },
|
|
{ "PMPCFG6", 118 },
|
|
{ "PMPCFG7", 119 },
|
|
{ "PMPCFG8", 120 },
|
|
{ "PMPCFG9", 121 },
|
|
{ "SATP", 30 },
|
|
{ "SCAUSE", 21 },
|
|
{ "SCONTEXT", 192 },
|
|
{ "SCOUNTEREN", 12 },
|
|
{ "SCOUNTOVF", 395 },
|
|
{ "SEED", 7 },
|
|
{ "SENVCFG", 13 },
|
|
{ "SEPC", 20 },
|
|
{ "SIE", 10 },
|
|
{ "SIEH", 18 },
|
|
{ "SIP", 23 },
|
|
{ "SIPH", 27 },
|
|
{ "SIREG", 26 },
|
|
{ "SISELECT", 25 },
|
|
{ "SSCRATCH", 19 },
|
|
{ "SSTATEEN0", 14 },
|
|
{ "SSTATEEN1", 15 },
|
|
{ "SSTATEEN2", 16 },
|
|
{ "SSTATEEN3", 17 },
|
|
{ "SSTATUS", 9 },
|
|
{ "STIMECMP", 24 },
|
|
{ "STIMECMPH", 29 },
|
|
{ "STOPEI", 28 },
|
|
{ "STOPI", 396 },
|
|
{ "STVAL", 22 },
|
|
{ "STVEC", 11 },
|
|
{ "TDATA1", 258 },
|
|
{ "TDATA2", 259 },
|
|
{ "TDATA3", 260 },
|
|
{ "TIME", 329 },
|
|
{ "TIMEH", 364 },
|
|
{ "TSELECT", 257 },
|
|
{ "VCSR", 6 },
|
|
{ "VL", 360 },
|
|
{ "VLENB", 362 },
|
|
{ "VSATP", 46 },
|
|
{ "VSCAUSE", 37 },
|
|
{ "VSEPC", 36 },
|
|
{ "VSIE", 32 },
|
|
{ "VSIEH", 34 },
|
|
{ "VSIP", 39 },
|
|
{ "VSIPH", 43 },
|
|
{ "VSIREG", 42 },
|
|
{ "VSISELECT", 41 },
|
|
{ "VSSCRATCH", 35 },
|
|
{ "VSSTATUS", 31 },
|
|
{ "VSTART", 3 },
|
|
{ "VSTIMECMP", 40 },
|
|
{ "VSTIMECMPH", 45 },
|
|
{ "VSTOPEI", 44 },
|
|
{ "VSTOPI", 398 },
|
|
{ "VSTVAL", 38 },
|
|
{ "VSTVEC", 33 },
|
|
{ "VTYPE", 361 },
|
|
{ "VXRM", 5 },
|
|
{ "VXSAT", 4 },
|
|
};
|
|
|
|
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
|
|
if (i == -1)
|
|
return NULL;
|
|
else
|
|
return &SysRegsList[Index[i].index];
|
|
}
|
|
|
|
#endif
|
|
|
|
#undef GET_RISCVMaskedPseudosTable_DECL
|
|
#undef GET_RISCVMaskedPseudosTable_IMPL
|
|
#undef GET_RISCVOpcodesList_DECL
|
|
#undef GET_RISCVOpcodesList_IMPL
|
|
#undef GET_RISCVTuneInfoTable_DECL
|
|
#undef GET_RISCVTuneInfoTable_IMPL
|
|
#undef GET_RISCVVInversePseudosTable_DECL
|
|
#undef GET_RISCVVInversePseudosTable_IMPL
|
|
#undef GET_RISCVVLETable_DECL
|
|
#undef GET_RISCVVLETable_IMPL
|
|
#undef GET_RISCVVLSEGTable_DECL
|
|
#undef GET_RISCVVLSEGTable_IMPL
|
|
#undef GET_RISCVVLXSEGTable_DECL
|
|
#undef GET_RISCVVLXSEGTable_IMPL
|
|
#undef GET_RISCVVLXTable_DECL
|
|
#undef GET_RISCVVLXTable_IMPL
|
|
#undef GET_RISCVVPseudosTable_DECL
|
|
#undef GET_RISCVVPseudosTable_IMPL
|
|
#undef GET_RISCVVSETable_DECL
|
|
#undef GET_RISCVVSETable_IMPL
|
|
#undef GET_RISCVVSSEGTable_DECL
|
|
#undef GET_RISCVVSSEGTable_IMPL
|
|
#undef GET_RISCVVSXSEGTable_DECL
|
|
#undef GET_RISCVVSXSEGTable_IMPL
|
|
#undef GET_RISCVVSXTable_DECL
|
|
#undef GET_RISCVVSXTable_IMPL
|
|
#undef GET_SysRegsList_DECL
|
|
#undef GET_SysRegsList_IMPL
|