mirror of
https://github.com/open-goal/jak-project
synced 2026-05-25 07:23:19 -04:00
Tyler Wilding
01c70368e3
* lsp: json-rpc example is working, a decent place to start... * lsp: vendor library * lsp: cleanup and time to get started * lsp: commit what i got so far * lsp: example `initialize` payload * lsp: switch to `stdio` * stash * modularize the lsp implementation * lsp: implement first actual LSP feature - function names in outline * lsp: produce document diagnostics * lsp: remove unused third-party lib * lsp: support hovering MIPS instructions in IR files * lsp: basic go-to all-types definition * stash * lsp: cleanup code, just need to add it to the release artifacts * fix some project configuration * fix linux build * lsp: add lsp to PR artifacts and release assets * lsp: address feedback
532 lines
26 KiB
C++
532 lines
26 KiB
C++
#include "mips_instructions.h"
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namespace LSPData {
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const std::vector<MIPSInstruction> MIPS_INSTRUCTION_LIST = {
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{"ee", "ADD", "Add Word"},
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{"ee", "ADDI", "Add Immediate Word"},
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{"ee", "ADDIU", "Add Immediate Unsigned Word"},
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{"ee", "ADDU", "Add Unsigned Word"},
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{"ee", "AND", "And"},
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{"ee", "ANDI", "Add Immediate"},
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{"ee", "BEQ", "Branch on Equal"},
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{"ee", "BEQL", "Branch on Equal Likely"},
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{"ee", "BGEZ", "Branch on Greater Than or Equal to Zero"},
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{"ee", "BGEZAL", "Branch on Greater Than or Equal to Zero and Link"},
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{"ee", "BGEZALL", "Branch on Greater Than or Equal to Zero and Link Likely"},
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{"ee", "BGEZL", "Branch on Greater Than or Equal to Zero Likely"},
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{"ee", "BGTZ", "Branch on Greater Than Zero"},
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{"ee", "BGTZL", "Branch on Greater Than Zero Likely"},
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{"ee", "BLEZ", "Branch on Less Than or Equal to Zero"},
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{"ee", "BLEZL", "Branch on Less Than or Equal to Zero Likely"},
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{"ee", "BLTZ", "Branch on Less Than Zero"},
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{"ee", "BLTZAL", "Branch on Less Than Zero and Link"},
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{"ee", "BLTZALL", "Branch on Less Than Zero and Link Likely"},
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{"ee", "BLTZL", "Branch on Less Than Zero Likely"},
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{"ee", "BNE", "Branch on Not Equal"},
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{"ee", "BNEL", "Branch on Not Equal Likely"},
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{"ee", "BREAK", "Breakpoint"},
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{"ee", "DADD", "Doubleword Add"},
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{"ee", "DADDI", "Doubleword Add Immediate"},
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{"ee", "DADDIU", "Doubleword Add Immediate Unsigned"},
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{"ee", "DADDU", "Doubleword Add Unsigned"},
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{"ee", "DIV", "Divide Word"},
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{"ee", "DIVU", "Divide Unsigned Word"},
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{"ee", "DSLL", "Doubleword Shift Left Logical"},
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{"ee", "DSLL32", "Doubleword Shift Left Logical Plus 32"},
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{"ee", "DSLLV", "Doubleword Shift Left Logical Variable"},
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{"ee", "DSRA", "Doubleword Shift Right Arithmetic"},
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{"ee", "DSRA32", "Doubleword Shift Right Arithmetic Plus 32"},
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{"ee", "DSRAV", "Doubleword Shift Right Arithmetic Variable"},
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{"ee", "DSRL", "Doubleword Shift Right Logical"},
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{"ee", "DSRL32", "Doubleword Shift Right Logical Plus 32"},
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{"ee", "DSRLV", "Doubleword Shift Right Logical Variable"},
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{"ee", "DSUB", "Doubleword Subtract"},
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{"ee", "DSUBU", "Doubleword Subtract Unsigned"},
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{"ee", "J", "Jump"},
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{"ee", "JAL", "Jump and Link"},
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{"ee", "JALR", "Jump and Link Register"},
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{"ee", "JR", "Jump Register"},
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{"ee", "LB", "Load Byte"},
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{"ee", "LBU", "Load Byte Unsigned"},
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{"ee", "LD", "Load Doubleword"},
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{"ee", "LDL", "Load Doubleword Left"},
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{"ee", "LDR", "Load Doubleword Right"},
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{"ee", "LH", "Load Halfword"},
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{"ee", "LHU", "Load Halfword Unsigned"},
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{"ee", "LUI", "Load Upper Immediate"},
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{"ee", "LW", "Load Word"},
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{"ee", "LWL", "Load Word Left"},
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{"ee", "LWR", "Load Word Right"},
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{"ee", "LWU", "Load Word Unsigned"},
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{"ee", "MFHI", "Move from HI Register"},
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{"ee", "MFLO", "Move from LO Register"},
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{"ee", "MOVN", "Move Conditional on Not Zero"},
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{"ee", "MOVZ", "Move Conditional on Zero"},
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{"ee", "MTHI", "Move to HI Register"},
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{"ee", "MTLO", "Move to LO Register"},
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{"ee", "MULT", "Multiply Word"},
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{"ee", "MULTU", "Multiply Unsigned Word"},
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{"ee", "NOR", "Not Or"},
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{"ee", "OR", "Or"},
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{"ee", "ORI", "Or immediate"},
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{"ee", "PREF", "Prefetch"},
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{"ee", "SB", "Store Byte"},
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{"ee", "SD", "Store Doubleword"},
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{"ee", "SDL", "Store Doubleword Left"},
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{"ee", "SDR", "Store Doubleword Right"},
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{"ee", "SH", "Store Halfword"},
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{"ee", "SLL", "Shift Word Left Logical"},
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{"ee", "SLLV", "Shift Word Left Logical Variable"},
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{"ee", "SLT", "Set on Less Than"},
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{"ee", "SLTI", "Set on Less Than Immediate"},
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{"ee", "SLTIU", "Set on Less Than Immediate Unsigned"},
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{"ee", "SLTU", "Set on Less Than Unsigned"},
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{"ee", "SRA", "Shift Word Right Arithmetic"},
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{"ee", "SRAV", "Shift Word Right Arithmetic Variable"},
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{"ee", "SRL", "Shift Word Right Logical"},
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{"ee", "SRLV", "Shift Word Right Logical Variable"},
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{"ee", "SUB", "Subtract Word"},
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{"ee", "SUBU", "Subtract Unsigned Word"},
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{"ee", "SW", "Store Word"},
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{"ee", "SWL", "Store Word Left"},
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{"ee", "SWR", "Store Word Right"},
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{"ee", "SYNC", "Synchronize Shared Memory"},
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{"ee", "SYNC.L", "Synchronize Shared Memory"},
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{"ee", "SYNC.P", "Synchronize Shared Memory"},
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{"ee", "SYSCALL", "System Call"},
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{"ee", "TEQ", "Trap if Equal"},
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{"ee", "TEQI", "Trap if Equal Immediate"},
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{"ee", "TGE", "Trap if Greater or Equal"},
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{"ee", "TGEI", "Trap if Greater or Equal Immediate"},
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{"ee", "TGEIU", "Trap if Greater or Equal Immediate Unsigned"},
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{"ee", "TGEU", "Trap if Greater or Equal Unsigned"},
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{"ee", "TLT", "Trap if Less Than"},
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{"ee", "TLTI", "Trap if Less Than Immediate"},
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{"ee", "TLTIU", "Trap if Less Than Immediate Unsigned"},
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{"ee", "TLTU", "Trap if Less Than Unsigned"},
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{"ee", "TNE", "Trap if Not Equal"},
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{"ee", "TNEI", "Trap if Not Equal Immediate"},
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{"ee", "XOR", "Exclusive OR"},
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{"ee", "XORI", "Exclusive OR Immediate"},
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{"ee", "DIV1", "Divide Word Pipeline 1"},
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{"ee", "DIVU1", "Divide Unsigned Word Pipeline 1"},
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{"ee", "LQ", "Load Quadword"},
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{"ee", "MADD", "Multiply-Add word"},
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{"ee", "MADD1", "Multiply-Add word Pipeline"},
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{"ee", "MADDU", "Multiply-Add Unsigned word"},
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{"ee", "MADDU1", "Multiply-Add Unsigned word Pipeline"},
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{"ee", "MFHI1", "Move From HI1 Register"},
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{"ee", "MFLO1", "Move From LO1 Register"},
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{"ee", "MFSA", "Move from Shift Amount Register"},
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{"ee", "MTHI1", "Move To HI1 Register"},
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{"ee", "MTLO1", "Move To LO1 Register"},
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{"ee", "MTSA", "Move to Shift Amount Register"},
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{"ee", "MTSAB", "Move Byte Count to Shift Amount Register"},
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{"ee", "MTSAH", "Move Halfword Count to Shift Amount Register"},
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{"ee", "MULT", "Multiply Word"},
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{"ee", "MULT1", "Multiply Word Pipeline"},
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{"ee", "MULTU", "Multiply Unsigned Word"},
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{"ee", "MULTU1", "Multiply Unsigned Word Pipeline"},
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{"ee", "PABSH", "Parallel Absolute Halfword"},
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{"ee", "PABSW", "Parallel Absolute Word"},
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{"ee", "PADDB", "Parallel Add Byte"},
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{"ee", "PADDH", "Parallel Add Halfword"},
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{"ee", "PADDSB", "Parallel Add with Signed Saturation Byte"},
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{"ee", "PADDSH", "Parallel Add with Signed Saturation Halfword"},
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{"ee", "PADDSW", "Parallel Add with Signed Saturation Word"},
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{"ee", "PADDUB", "Parallel Add with Unsigned Saturation Byte"},
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{"ee", "PADDUH", "Parallel Add with Unsigned Saturation Halfword"},
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{"ee", "PADDUW", "Parallel Add with Unsigned Saturation Word"},
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{"ee", "PADDW", "Parallel Add Word"},
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{"ee", "PADSBH", "Parallel Add/Subtract Halfword"},
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{"ee", "PAND", "Parallel And"},
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{"ee", "PCEQB", "Parallel Compare for Equal Byte"},
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{"ee", "PCEQH", "Parallel Compare for Equal Halfword"},
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{"ee", "PCEQW", "Parallel Compare for Equal Word"},
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{"ee", "PCGTB", "Parallel Compare for Greater Than Byte"},
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{"ee", "PCGTH", "Parallel Compare for Greater Than Halfword"},
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{"ee", "PCGTW", "Parallel Compare for Greater Than Word"},
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{"ee", "PCPYH", "Parallel Copy Halfword"},
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{"ee", "PCPYLD", "Parallel Copy Lower Doubleword"},
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{"ee", "PCPYUD", "Parallel Copy Upper Doubleword"},
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{"ee", "PDIVBW", "Parallel Divide Broadcast Word"},
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{"ee", "PDIVUW", "Parallel Divide Unsigned Word"},
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{"ee", "PDIVW", "Parallel Divide Word"},
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{"ee", "PEXCH", "Parallel Exchange Center Halfword"},
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{"ee", "PEXCW", "Parallel Exchange Center Word"},
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{"ee", "PEXEH", "Parallel Exchange Even Halfword"},
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{"ee", "PEXEW", "Parallel Exchange Even Word"},
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{"ee", "PEXT5", "Parallel Extend from 5 bits"},
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{"ee", "PEXTLB", "Parallel Extend Lower from Byte"},
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{"ee", "PEXTLH", "Parallel Extend Lower from Halfword"},
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{"ee", "PEXTLW", "Parallel Extend Lower from Word"},
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{"ee", "PEXTUB", "Parallel Extend Upper from Byte"},
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{"ee", "PEXTUH", "Parallel Extend Upper from Halfword"},
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{"ee", "PEXTUW", "Parallel Extend Upper from Word"},
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{"ee", "PHMADH", "Parallel Horizontal Multiply-Add Halfword"},
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{"ee", "PHMSBH", "Parallel Horizontal Multiply-Subtract Halfword"},
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{"ee", "PINTEH", "Parallel Interleave Even Halfword"},
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{"ee", "PINTH", "Parallel Interleave Halfword"},
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{"ee", "PLZCW", "Parallel Leading Zero or one Count Word"},
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{"ee", "PMADDH", "Parallel Multiply-Add Halfword"},
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{"ee", "PMADDUW", "Parallel Multiply-Add Unsigned Word"},
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{"ee", "PMADDW", "Parallel Multiply-Add Word"},
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{"ee", "PMAXH", "Parallel Maximize Halfword"},
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{"ee", "PMAXW", "Parallel Maximize Word"},
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{"ee", "PMFHI", "Parallel Move From HI Register"},
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{"ee", "PMFHL", "Parallel Move From HI/LO Register"},
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{"ee", "PMFHL", "Parallel Move From HI/LO Register"},
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{"ee", "PMFHL", "Parallel Move From HI/LO Register"},
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{"ee", "PMFHL", "Parallel Move From HI/LO Register"},
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{"ee", "PMFHL", "Parallel Move From HI/LO Register"},
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{"ee", "PMFLO", "Parallel Move From LO Register"},
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{"ee", "PMINH", "Parallel Minimize Halfword"},
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{"ee", "PMINW", "Parallel Minimize Word"},
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{"ee", "PMSUBH", "Parallel Multiply-Subtract Halfword"},
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{"ee", "PMSUBW", "Parallel Multiply-Subtract Word"},
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{"ee", "PMTHI", "Parallel Move To HI Register"},
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{"ee", "PMTHL", "Parallel Move To HI/LO Register"},
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{"ee", "PMTLO", "Parallel Move To LO Register"},
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{"ee", "PMULTH", "Parallel Multiply Halfword"},
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{"ee", "PMULTUW", "Parallel Multiply Unsigned Word"},
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{"ee", "PMULTW", "Parallel Multiply Word"},
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{"ee", "PNOR", "Parallel Not Or"},
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{"ee", "POR", "Parallel Or"},
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{"ee", "PPAC5", "Parallel Pack to 5 bits"},
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{"ee", "PPACB", "Parallel Pack to Byte"},
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{"ee", "PPACH", "Parallel Pack to Halfword"},
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{"ee", "PPACW", "Parallel Pack to Word"},
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{"ee", "PREVH", "Parallel Reverse Halfword"},
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{"ee", "PROT3W", "Parallel Rotate 3 Words Left"},
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{"ee", "PSLLH", "Parallel Shift Left Logical Halfword"},
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{"ee", "PSLLVW", "Parallel Shift Left Logical Variable Word"},
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{"ee", "PSLLW", "Parallel Shift Left Logical Word"},
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{"ee", "PSRAH", "Parallel Shift Right Arithmetic Halfword"},
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{"ee", "PSRAVW", "Parallel Shift Right Arithmetic Variable Word"},
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{"ee", "PSRAW", "Parallel Shift Right Arithmetic Word"},
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{"ee", "PSRLH", "Parallel Shift Right Logical Halfword"},
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{"ee", "PSRLVW", "Parallel Shift Right Logical Variable Word"},
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{"ee", "PSRLW", "Parallel Shift Right Logical Word"},
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{"ee", "PSUBB", "Parallel Subtract Byte"},
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{"ee", "PSUBH", "Parallel Subtract Halfword"},
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{"ee", "PSUBSB", "Parallel Subtract with Signed saturation Byte"},
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{"ee", "PSUBSH", "Parallel Subtract with Signed Saturation Halfword"},
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{"ee", "PSUBSW", "Parallel Subtract with Signed Saturation Word"},
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{"ee", "PSUBUB", "Parallel Subtract with Unsigned Saturation Byte"},
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{"ee", "PSUBUH", "Parallel Subtract with Unsigned Saturation Halfword"},
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{"ee", "PSUBUW", "Parallel Subtract with Unsigned Saturation Word"},
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{"ee", "PSUBW", "Parallel Subtract Word"},
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{"ee", "PXOR", "Parallel Exclusive OR"},
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{"ee", "QFSRV", "Quadword Funnel Shift Right Variable"},
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{"ee", "SQ", "Store Quadword"},
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{"ee", "BC0F", "Branch on Coprocessor 0 False"},
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{"ee", "BC0FL", "Branch on Coprocessor 0 False Likely"},
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{"ee", "BC0T", "Branch on Coprocessor 0 True"},
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{"ee", "BC0TL", "Branch on Coprocessor 0 True Likely"},
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{"ee", "cache bfh", "Cache Operation (BTAC Flush)"},
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{"ee", "cache bhinbt", "Cache Operation (Hit Invalidate BTAC)"},
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{"ee", "cache bxlbt", "Cache Operation (Index Load BTAC)"},
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{"ee", "cache bxsbt", "Cache Operation (Index Store BTAC)"},
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{"ee", "cache dhin", "Cache Operation (Hit Invalidate)"},
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{"ee", "cache dhwbin", "Cache Operation (Hit Writeback Invalidate)"},
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{"ee", "cache dhwoin", "Cache Operation (Hit Writeback Without Invalidate)"},
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{"ee", "cache dxin", "Cache Operation (Index Invalidate)"},
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{"ee", "cache dxldt", "Cache Operation (Index Load Data)"},
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{"ee", "cache dxltg", "Cache Operation (Index Load Tag)"},
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{"ee", "cache dxsdt", "Cache Operation (Index Store Data)"},
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{"ee", "cache dxstg", "Cache Operation (Index Store Tag)"},
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{"ee", "cache dxwbin", "Cache Operation (Index Writeback Invalidate)"},
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{"ee", "cache ifl", "Cache Operation (Fill)"},
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{"ee", "cache ihin", "Cache Operation (Hit Invalidate)"},
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{"ee", "cache ixin", "Cache Operation (Index Invalidate)"},
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{"ee", "cache ixldt", "Cache Operation (Index Load Data)"},
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{"ee", "cache ixltg", "Cache Operation (Index Load Tag)"},
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{"ee", "cache ixsdt", "Cache Operation (Index Store Data)"},
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{"ee", "cache ixstg", "Cache Operation (Index Store Tag)"},
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{"ee", "DI", "Disable Interrupt"},
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{"ee", "EI", "Enable Interrupt"},
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{"ee", "ERET", "Exception Return"},
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{"ee", "MFBPC", "Move from Breakpoint Control Register"},
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{"ee", "MFC0", "Move from System Control Coprocessor"},
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{"ee", "MFDAB", "Move from Data Address Breakpoint Register"},
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{"ee", "MFDABM", "Move from Data Address Breakpoint Mask Register"},
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{"ee", "MFDVB", "Move from Data value Breakpoint Register"},
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{"ee", "MFDVBM", "Move from Data Value Breakpoint Mask Register"},
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{"ee", "MFIAB", "Move from Instruction Address Breakpoint Register"},
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{"ee", "MFIABM", "Move from Instruction Address Breakpoint Mask Register"},
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{"ee", "MFPC", "Move from Performance Counter"},
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{"ee", "MFPS", "Move from Performance Event Specifier"},
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{"ee", "MTBPC", "Move to Breakpoint Control Register"},
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{"ee", "MTC0", "Move to System Control Coprocessor"},
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{"ee", "MTDAB", "Move to Data Address Breakpoint Register"},
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{"ee", "MTDABM", "Move to Data Address Breakpoint Mask Register"},
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{"ee", "MTDVB", "Move to Data Value Breakpoint Register"},
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{"ee", "MTDVBM", "Move to Data Value Breakpoint Mask Register"},
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{"ee", "MTIAB", "Move to Instruction Address Breakpoint Register"},
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{"ee", "MTIABM", "Move to Instruction Address Breakpoint Mask Register"},
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{"ee", "MTPC", "Move to Performance Counter"},
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{"ee", "MTPS", "Move to Performance Event Specifier"},
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{"ee", "TLBP", "Probe TLB for Matching Entry"},
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{"ee", "TLBR", "Read Indexed TLB Entry"},
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{"ee", "TLBWI", "Write Index TLB Entry"},
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{"ee", "TLBWR", "Write Random TLB Entry"},
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{"ee", "ABS", "Floating Point Absolute Value"},
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{"ee", "ADD", "Floating Point ADD"},
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{"ee", "ADDA", "Floating Point Add to Accumulator"},
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{"ee", "BC1F", "Branch on FP False"},
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{"ee", "BC1FL", "Branch on FP False Likely"},
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{"ee", "BC1T", "Branch on FP True"},
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{"ee", "BC1TL", "Branch on FP True Likely"},
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{"ee", "C.EQ.S", "Floating Point Compare"},
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{"ee", "c.f.s", "Floating Point Compare"},
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{"ee", "c.le.s", "Floating Point Compare"},
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{"ee", "c.lt.s", "Floating Point Compare"},
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{"ee", "CFC1", "Move Control Word from Floating Point"},
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{"ee", "CTC1", "Move Control Word to Floating Point"},
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{"ee", "CVT", "Fixed-point Convert to Single Floating Point"},
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{"ee", "CVT", "Floating Point Convert to Word Fixed-point"},
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{"ee", "DIV", "Floating Point Divide"},
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{"ee", "LWC1", "Load Word to Floating Point"},
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{"ee", "MADD", "Floating Point Multiply-ADD"},
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{"ee", "MADDA", "Floating Point Multiply-Add"},
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{"ee", "MAX", "Floating Point Maximum"},
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{"ee", "MFC1", "Move Word from Floating Point"},
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{"ee", "MIN", "Floating Point Minimum"},
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{"ee", "MOV", "Floating Point Move"},
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{"ee", "MSUB", "Floating Point Multiply and Subtract"},
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{"ee", "MSUBA", "Floating Point Multiply and Subtract from Accumulator"},
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{"ee", "MTC1", "Move Word to Floating Point"},
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{"ee", "MUL", "Floating Point Multiply"},
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{"ee", "MULA", "Floating Point Multiply to Accumulator"},
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{"ee", "NEG", "Floating Point Negate"},
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{"ee", "RSQRT", "Floating Point Reciprocal Square Root"},
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{"ee", "SQRT", "Floating Point Square Root"},
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{"ee", "SUB", "Floating Point Subtract"},
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{"ee", "SUBA", "Floating Point Subtract to Accumulator"},
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{"ee", "SWC1", "Store Word from Floating Point"},
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{"vu", "ABS", "Absolute Value"},
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{"vu", "ADD", "Add"},
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{"vu", "ADDi", "Add to I Register"},
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{"vu", "ADDq", "Add to Q Register"},
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{"vu", "ADDbc", "Broadcast Add"},
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{"vu", "ADDA", "Add to Accumulator"},
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{"vu", "ADDAi", "Add I Register to Accumulator"},
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{"vu", "ADDAq", "Add Q Register to Accumulator"},
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{"vu", "ADDAbc", "Broadcast Add to Accumulator"},
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{"vu", "CLIP", "Clipping Judgment"},
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{"vu", "FTOI0", "Convert to Fixed Point"},
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{"vu", "FTOI4", "Convert to Fixed Point"},
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{"vu", "FTOI12", "Convert to Fixed Point"},
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{"vu", "FTOI15", "Convert to Fixed Point"},
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{"vu", "ITOF0", "Convert to Floating-Point Number"},
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{"vu", "ITOF4", "Convert to Floating-Point Number"},
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{"vu", "ITOF12", "Convert to Floating-Point Number"},
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{"vu", "ITOF15", "Convert to Floating-Point Number"},
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{"vu", "MADD", "Product Sum"},
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{"vu", "MADDi", "Product Sum with I Register"},
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{"vu", "MADDq", "Product Sum by Q Register"},
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{"vu", "MADDbc", "Broadcast Product Sum"},
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{"vu", "MADDA", "Product Sum to Accumulator"},
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{"vu", "MADDAi", "Product Sum by I register, to Accumulator"},
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{"vu", "MADDAq", "Product Sum by Q Register, to Accumulator"},
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{"vu", "MADDAbc", "Broadcast Product Sum to Accumulator"},
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{"vu", "MAX", "Maximum Value"},
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{"vu", "MAXi", "Maximum Value"},
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{"vu", "MAXbc", "Maximum Value"},
|
|
{"vu", "MINI", "Minimum Value"},
|
|
{"vu", "MINIi", "Minimum Value"},
|
|
{"vu", "MINIbc", "Minimum Value"},
|
|
{"vu", "MSUB", "Multiply and Subtract"},
|
|
{"vu", "MSUBi", "Multiply and Subtract with I Register"},
|
|
{"vu", "MSUBq", "Multiply and Subtract by Q Register"},
|
|
{"vu", "MSUBbc", "Broadcast Multiply and Subtract"},
|
|
{"vu", "MSUBA", "Multiply and Subtract to Accumulator"},
|
|
{"vu", "MSUBAi", "Multiply and Subtract with I Register, to Accumulator"},
|
|
{"vu", "MSUBAq", "Multiply and Subtract by Q Register, to Accumulator"},
|
|
{"vu", "MSUBAbc", "Broadcast Multiply and Subtract to Accumulator"},
|
|
{"vu", "MUL", "Multiply"},
|
|
{"vu", "MULi", "Multiply by I Register"},
|
|
{"vu", "MULq", "Multiply by Q Register"},
|
|
{"vu", "MULbc", "Multiply by Broadcast"},
|
|
{"vu", "MULA", "Multiply to Accumulator"},
|
|
{"vu", "MULAi", "Multiply by I Register, to Accumulator"},
|
|
{"vu", "MULAq", "Multiply by Q Register, to Accumulator"},
|
|
{"vu", "MULAbc", "Broadcast Multiply by broadcast, to Accumulator"},
|
|
{"vu", "NOP", "No Operation"},
|
|
{"vu", "OPMULA", "Vector Outer Product"},
|
|
{"vu", "OPMSUB", "Vector Outer Product"},
|
|
{"vu", "SUB", "Subtract"},
|
|
{"vu", "SUBi", "Subtract I Register"},
|
|
{"vu", "SUBq", "Subtract Q Register"},
|
|
{"vu", "SUBbc", "Broadcast Subtract"},
|
|
{"vu", "SUBA", "Substract to Accumulator"},
|
|
{"vu", "SUBAi", "Subtract I Register to Accumulator"},
|
|
{"vu", "SUBAq", "Subtract Q Register to Accumulator"},
|
|
{"vu", "SUBAbc", "Broadcast Subtract to Accumulator"},
|
|
{"vu", "B", "Unconditional Branch"},
|
|
{"vu", "BAL", "Unconditional Branch with Saving Address"},
|
|
{"vu", "DIV", "Divide"},
|
|
{"vu", "EATAN", "Arctangent"},
|
|
{"vu", "EATANxy", "Arctangent"},
|
|
{"vu", "EATANxz", "Arctangent"},
|
|
{"vu", "EEXP", "Exponent"},
|
|
{"vu", "ELENG", "Length"},
|
|
{"vu", "ERCPR", "Reciprocal Number"},
|
|
{"vu", "ERLENG", "Reciprocal Number of Length"},
|
|
{"vu", "ERSADD", "Reciprocal Number"},
|
|
{"vu", "ERSQRT", "Reciprocal Number of Square Root"},
|
|
{"vu", "ESADD", "Sum of Square Numbers"},
|
|
{"vu", "ESIN", "Sine"},
|
|
{"vu", "ESQRT", "Square Root"},
|
|
{"vu", "ESUM", "Sum of Each Field"},
|
|
{"vu", "FCAND", "Test Clipping Flag"},
|
|
{"vu", "FCEQ", "Test Clipping Flag"},
|
|
{"vu", "FCGET", "Get Clipping Flag"},
|
|
{"vu", "FCOR", "Test Clipping Flag"},
|
|
{"vu", "FCSET", "Setting Clipping Flag"},
|
|
{"vu", "FMAND", "Test MAC Flag Check"},
|
|
{"vu", "FMEQ", "Test MAC Flag Check"},
|
|
{"vu", "FMOR", "Test MAC Flag Check"},
|
|
{"vu", "FSAND", "Test Status Flag Check"},
|
|
{"vu", "FSEQ", "Test Status Flag Check"},
|
|
{"vu", "FSOR", "Test Status Flag"},
|
|
{"vu", "FSSET", "Set Sticky Flags"},
|
|
{"vu", "IADD", "ADD Integer"},
|
|
{"vu", "IADDI", "Add Immediate Value Integer"},
|
|
{"vu", "IADDIU", "Add Immediate Integer"},
|
|
{"vu", "IAND", "Logical Product"},
|
|
{"vu", "IBEQ", "Conditional Branch"},
|
|
{"vu", "IBGEZ", "Conditional Branch"},
|
|
{"vu", "IBGTZ", "Conditional Branch"},
|
|
{"vu", "IBLEZ", "Conditional Branch"},
|
|
{"vu", "IBLTZ", "Conditional Branch"},
|
|
{"vu", "IBNE", "Conditional Branch"},
|
|
{"vu", "ILW", "Integer Load with Offset Specification"},
|
|
{"vu", "ILWR", "Integer Load"},
|
|
{"vu", "IOR", "Logical Sum"},
|
|
{"vu", "ISUB", "Integer Subtract"},
|
|
{"vu", "ISUBIU", "Immediate Value Integer Subtract"},
|
|
{"vu", "ISW", "Integer Store with Offset"},
|
|
{"vu", "ISWR", "Integer Store"},
|
|
{"vu", "JALR", "Unconditional Jump with Address Saving"},
|
|
{"vu", "JR", "Unconditional Jump"},
|
|
{"vu", "LQ", "Load Qword"},
|
|
{"vu", "LQD", "Load Qword with Pre-Decrement"},
|
|
{"vu", "LQI", "Load with Post-Increment"},
|
|
{"vu", "MFIR", "Move from Integer Register to Floating-Point Register"},
|
|
{"vu", "MFP", "Move from P Register to Floating-Point Register"},
|
|
{"vu", "MOVE", "Transfer between Floating-Point Registers"},
|
|
{"vu", "MR32", "Move with Rotate"},
|
|
{"vu", "MTIR", "Move from Floating-Point Register to Integer Register"},
|
|
{"vu", "RGET", "Get Random Number"},
|
|
{"vu", "RINIT", "Random Number Intialize"},
|
|
{"vu", "RNEXT", "Next Random Number"},
|
|
{"vu", "RSQRT", "Square Root Division"},
|
|
{"vu", "RXOR", "Random Number Set"},
|
|
{"vu", "SQ", "Store Qword with Offset"},
|
|
{"vu", "SQD", "Store Qword with Pre-Decrement"},
|
|
{"vu", "SQI", "Store with Post-Increment"},
|
|
{"vu", "SQRT", "Square Root"},
|
|
{"vu", "WAITP", "P Register Syncronize"},
|
|
{"vu", "WAITQ", "Q Register Syncronize"},
|
|
{"vu", "XGKICK", "GIF Control"},
|
|
{"vu", "XITOP", "VIF Control"},
|
|
{"vu", "XTOP", "VIF Control"},
|
|
{"vu", "BC2F", "Branch on COP2 Conditional Signal"},
|
|
{"vu", "BC2FL", "Branch on COP2 Conditional Signal"},
|
|
{"vu", "BC2T", "Branch on COP2 Conditional Signal"},
|
|
{"vu", "BC2TL", "Branch on COP2 Conditional signal"},
|
|
{"vu", "CFC2", "Transfer Integer Data from VU to EE Core"},
|
|
{"vu", "CTC2", "Transfer Integer Data from EE Core to VU"},
|
|
{"vu", "LQC2", "Floating-Point Data Transfer from EE Core to VU"},
|
|
{"vu", "QMFC2", "Floating-Point Data Transfer from VU to EE Core"},
|
|
{"vu", "QMTC2", "Floating-Point Data Transfer from EE Core to VU"},
|
|
{"vu", "SQC2", "Floating-Point Data Transfer from VU to EE Core"},
|
|
{"vu", "VABS", "Absolute Value"},
|
|
{"vu", "VADD", "Add"},
|
|
{"vu", "VADDi", "Add to I Register"},
|
|
{"vu", "VADDq", "Add to Q Register"},
|
|
{"vu", "VADDbc", "Broadcast Add"},
|
|
{"vu", "VADDA", "Add to Accumulator"},
|
|
{"vu", "VADDAi", "Add I Register to Accumulator"},
|
|
{"vu", "VADDAq", "Add Q Register to Accumulator"},
|
|
{"vu", "VADDAbc", "Broadcast Add to Accumulator"},
|
|
{"vu", "VCALLMS", "Start Micro Sub-Routine"},
|
|
{"vu", "VCALLMSR", "Start Micro Sub-Routine by Register"},
|
|
{"vu", "VCLIP", "Clipping Judgment"},
|
|
{"vu", "VDIV", "Divide"},
|
|
{"vu", "VFTOI0", "Conversion to Fixed Point"},
|
|
{"vu", "VFTOI4", "Conversion to Fixed Point"},
|
|
{"vu", "VFTOI12", "Conversion to Fixed Point"},
|
|
{"vu", "VFTOI15", "Conversion to Fixed Point"},
|
|
{"vu", "VIADD", "Add Integer"},
|
|
{"vu", "VIADDI", "Add Immediate Value Integer"},
|
|
{"vu", "VIAND", "Logical Product"},
|
|
{"vu", "VILWR", "Integer Load"},
|
|
{"vu", "VIOR", "Logical Sum"},
|
|
{"vu", "VISUB", "Integer Subtract"},
|
|
{"vu", "VISWR", "Integer Store"},
|
|
{"vu", "VITOF0", "Conversion to Floating-Point Number"},
|
|
{"vu", "VITOF4", "Conversion to Floating-Point Number"},
|
|
{"vu", "VITOF12", "Conversion to Floating-Point Number"},
|
|
{"vu", "VITOF15", "Conversion to Floating-Point Number"},
|
|
{"vu", "VLQD", "Load with Pre-Decrement"},
|
|
{"vu", "VLQI", "Load with Post-Increment"},
|
|
{"vu", "VMADD", "Product Sum"},
|
|
{"vu", "VMADDi", "Product Sum with I Register"},
|
|
{"vu", "VMADDq", "Product Sum with Q Register"},
|
|
{"vu", "VMADDbc", "Broadcast Product Sum"},
|
|
{"vu", "VMADDA", "Product Sum to Accumulator"},
|
|
{"vu", "VMADDAi", "Product Sum with I Register, to Accumulator"},
|
|
{"vu", "VMADDAq", "Product Sum with Q Register, to Accumulator"},
|
|
{"vu", "VMADDAbc", "Broadcast Product Sum to Accumulator"},
|
|
{"vu", "VMAX", "Maximum Value"},
|
|
{"vu", "VMAXi", "Maximum Value"},
|
|
{"vu", "VMAXbc", "Maximum Value"},
|
|
{"vu", "VMFIR", "Transfer from Integer Register to Floating-Point Register"},
|
|
{"vu", "VMINI", "Minimum Value"},
|
|
{"vu", "VMINIi", "Minimum Value"},
|
|
{"vu", "VMINIbc", "Minimum Value"},
|
|
{"vu", "VMOVE", "Transfer between Floating-Point Registers"},
|
|
{"vu", "VMR32", "Vector Rotate"},
|
|
{"vu", "VMSUB", "Multiply and Subtract"},
|
|
{"vu", "VMSUBi", "Multiply and Subtract with I Register"},
|
|
{"vu", "VMSUBq", "Multiply and Subtract Q Register"},
|
|
{"vu", "VMSUBbc", "Broadcast Multiply and Subtract"},
|
|
{"vu", "VMSUBA", "Multiply and Subtract to Accumulator"},
|
|
{"vu", "VMSUBAi", "Multiply and Subtract with I Register, to Accumulator"},
|
|
{"vu", "VMSUBAq", "Multiply and Subtract with Q Register, to Accumulator"},
|
|
{"vu", "VMSUBAbc", "Broadcast Multiply and Subtract to Accumulator"},
|
|
{"vu", "VMTIR", "Transfer from Floating-Point Register to Integer Register"},
|
|
{"vu", "VMUL", "Multiply"},
|
|
{"vu", "VMULi", "Multiply by I Register"},
|
|
{"vu", "VMULq", "Multiply by Q Register"},
|
|
{"vu", "VMULbc", "Broadcast Multiply"},
|
|
{"vu", "VMULA", "Multiply to Accumulator"},
|
|
{"vu", "VMULAi", "Multiply by I Register to Accumulator"},
|
|
{"vu", "VMULAq", "Multiply by Q Register to Accumulator"},
|
|
{"vu", "VMULAbc", "Broadcast Multiply to Accumulator"},
|
|
{"vu", "VNOP", "No Operation"},
|
|
{"vu", "VOPMULA", "Vector Outer Product"},
|
|
{"vu", "VOPMSUB", "Vector Outer Product"},
|
|
{"vu", "VRGET", "Get Random Numbers"},
|
|
{"vu", "VRINIT", "Random Number Initial Set"},
|
|
{"vu", "VRNEXT", "New Random Numbers"},
|
|
{"vu", "VRSQRT", "Square Root Division"},
|
|
{"vu", "VRXOR", "Random Number Set"},
|
|
{"vu", "VSQD", "Store with Pre-Decrement"},
|
|
{"vu", "VSQI", "Store with Post-Increment"},
|
|
{"vu", "VSQRT", "Square Root"},
|
|
{"vu", "VSUB", "Subtract"},
|
|
{"vu", "VSUBi", "Subtract I Register"},
|
|
{"vu", "VSUBq", "Subtract Q Register"},
|
|
{"vu", "VSUBbc", "Broadcast Subtract"},
|
|
{"vu", "VSUBA", "Subtract to Accumulator"},
|
|
{"vu", "VSUBAi", "Subtract I Register to Accumulator"},
|
|
{"vu", "VSUBAq", "Subtract Q Register to Accumulator"},
|
|
{"vu", "VSUBAbc", "Broadcast Subtract to Accumulator"},
|
|
{"vu", "VWAITQ", "Q Register Synchronize"},
|
|
};
|
|
}
|