mirror
/
linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

net: ipa: define COMP_CFG IPA register fields 

Create the ipa_reg_comp_cfg_field_id enumerated type, which
identifies the fields for the COMP_CFG IPA register.

Use IPA_REG_FIELDS() to specify the field mask values defined for
this register, for each supported version of IPA.

Use ipa_reg_bit() to build up the value to be written to this
register rather than using the *_FMASK preprocessor symbols.

Remove the definition of the *_FMASK symbols, along with the inline
functions that were used to encode certain fields whose position
and/or width within the register was dependent on IPA version.

Take this opportunity to represent all one-bit fields using BIT(x)
rather than GENMASK(x, x).

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder 2022-09-26 17:09:23 -05:00 committed by Jakub Kicinski
parent a5ad8956f9
commit 12c7ea7dfd
8 changed files with 160 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/net/ipa/ipa_main.c
View File

@ -257,17 +257,17 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
val = ioread32(ipa->reg_virt + offset);
if (ipa->version == IPA_VERSION_4_0) {
val &= ~IPA_QMB_SELECT_CONS_EN_FMASK;
val &= ~IPA_QMB_SELECT_PROD_EN_FMASK;
val &= ~IPA_QMB_SELECT_GLOBAL_EN_FMASK;
val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_CONS_EN);
val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_PROD_EN);
val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN);
} else if (ipa->version < IPA_VERSION_4_5) {
val |= GSI_MULTI_AXI_MASTERS_DIS_FMASK;
val |= ipa_reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS);
} else {
/* For IPA v4.5 IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN is 0 */
/* For IPA v4.5 FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */
}
val |= GSI_MULTI_INORDER_RD_DIS_FMASK;
val |= GSI_MULTI_INORDER_WR_DIS_FMASK;
val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_RD_DIS);
val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_WR_DIS);
iowrite32(val, ipa->reg_virt + offset);
}

84
drivers/net/ipa/ipa_reg.h
View File

@ -172,63 +172,33 @@ struct ipa_regs {
};
/* COMP_CFG register */
/* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */
#define ENABLE_FMASK GENMASK(0, 0)
/* The next field is present for IPA v4.7+ */
#define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0)
#define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1)
#define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2)
#define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3)
/* The next field is not present for IPA v4.5+ */
#define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4)
/* The next twelve fields are present for IPA v4.0+ */
#define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5)
#define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6)
#define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7)
#define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8)
#define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9)
#define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10)
#define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11)
#define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12)
#define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13)
#define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14)
#define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15)
#define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16)
/* The next five fields are present for IPA v4.9+ */
#define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19)
#define GENQMB_AOOOWR_FMASK GENMASK(20, 20)
#define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21)
#define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30)
#define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31)
/* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */
static inline u32 arbitration_lock_disable_encoded(enum ipa_version version,
u32 mask)
{
WARN_ON(version < IPA_VERSION_4_0);
if (version < IPA_VERSION_4_9)
return u32_encode_bits(mask, GENMASK(20, 17));
if (version == IPA_VERSION_4_9)
return u32_encode_bits(mask, GENMASK(24, 22));
return u32_encode_bits(mask, GENMASK(23, 22));
}
/* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */
static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version,
bool enable)
{
u32 val = enable ? 1 : 0;
WARN_ON(version < IPA_VERSION_4_5);
if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7)
return u32_encode_bits(val, GENMASK(21, 21));
return u32_encode_bits(val, GENMASK(17, 17));
}
enum ipa_reg_comp_cfg_field_id {
COMP_CFG_ENABLE, /* Not IPA v4.0+ */
RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */
GSI_SNOC_BYPASS_DIS,
GEN_QMB_0_SNOC_BYPASS_DIS,
GEN_QMB_1_SNOC_BYPASS_DIS,
IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */
IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */
GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */
GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */
GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */
IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */
QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */
GENQMB_AOOOWR, /* IPA v4.9+ */
IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */
GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */
GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */
ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */
FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
};
/* CLKON_CFG register */
#define RX_FMASK GENMASK(0, 0)

11
drivers/net/ipa/reg/ipa_reg-v3.1.c
View File

@ -7,7 +7,16 @@
#include "../ipa.h"
#include "../ipa_reg.h"
IPA_REG(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_comp_cfg_fmask[] = {
[COMP_CFG_ENABLE] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[IPA_DCMP_FAST_CLK_EN] = BIT(4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044);

11
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
View File

@ -7,7 +7,16 @@
#include "../ipa.h"
#include "../ipa_reg.h"
IPA_REG(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_comp_cfg_fmask[] = {
[COMP_CFG_ENABLE] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[IPA_DCMP_FAST_CLK_EN] = BIT(4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044);

31
drivers/net/ipa/reg/ipa_reg-v4.11.c
View File

@ -7,7 +7,36 @@
#include "../ipa.h"
#include "../ipa_reg.h"
IPA_REG(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
/* Bit 18 reserved */
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22),
/* Bits 24-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044);

24
drivers/net/ipa/reg/ipa_reg-v4.2.c
View File

@ -7,7 +7,29 @@
#include "../ipa.h"
#include "../ipa_reg.h"
IPA_REG(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bit 0 reserved */
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[IPA_DCMP_FAST_CLK_EN] = BIT(4),
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044);

25
drivers/net/ipa/reg/ipa_reg-v4.5.c
View File

@ -7,7 +7,30 @@
#include "../ipa.h"
#include "../ipa_reg.h"
IPA_REG(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_comp_cfg_fmask[] = {
/* Bit 0 reserved */
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
/* Bits 22-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044);

30
drivers/net/ipa/reg/ipa_reg-v4.9.c
View File

@ -7,7 +7,35 @@
#include "../ipa.h"
#include "../ipa_reg.h"
IPA_REG(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22),
/* Bits 25-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044);