ARM: dts: stm32: Add CM4 reserved memory, rproc and IPCC on DHCOR SoM
Add reserved memory nodes for CortexM4 on the STM32MP1 DHCOR SoM, enable rproc to control the CM4 and IPCC mailbox to interact with it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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@ -19,6 +19,48 @@
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device_type = "memory";
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reg = <0xc0000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mcuram2: mcuram2@10000000 {
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compatible = "shared-dma-pool";
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reg = <0x10000000 0x40000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@10040000 {
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compatible = "shared-dma-pool";
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reg = <0x10040000 0x1000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@10041000 {
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compatible = "shared-dma-pool";
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reg = <0x10041000 0x1000>;
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no-map;
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};
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vdev0buffer: vdev0buffer@10042000 {
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compatible = "shared-dma-pool";
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reg = <0x10042000 0x4000>;
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no-map;
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};
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mcuram: mcuram@30000000 {
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compatible = "shared-dma-pool";
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reg = <0x30000000 0x40000>;
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no-map;
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};
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retram: retram@38000000 {
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compatible = "shared-dma-pool";
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reg = <0x38000000 0x10000>;
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no-map;
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};
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};
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};
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&crc1 {
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@ -179,11 +221,25 @@
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};
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};
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&ipcc {
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status = "okay";
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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};
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&m4_rproc {
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memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
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<&vdev0vring1>, <&vdev0buffer>;
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mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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mbox-names = "vq0", "vq1", "shutdown";
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interrupt-parent = <&exti>;
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interrupts = <68 1>;
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status = "okay";
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};
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&pwr_regulators {
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vdd-supply = <&vdd>;
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vdd_3v3_usbfs-supply = <&vdd_usb>;
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