From be8a77c54815b311485a348547ec80803ee9415b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Sep 2014 00:34:29 +0200 Subject: [PATCH 1/6] ARM: dts: rockchip: add operating points and armclk references Add basic OPP entries for current supported Rockchip SoCs. The operating points are currently very conservative, so individual boards may opt to redefine them. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/boot/dts/rk3066a.dtsi | 12 +++++++++++- arch/arm/boot/dts/rk3188.dtsi | 15 ++++++++++++++- arch/arm/boot/dts/rk3288.dtsi | 19 ++++++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ad9c2db59670..8b11fbd58071 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -26,11 +26,21 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1008000 1075000 + 816000 1025000 + 600000 1025000 + 504000 1000000 + 312000 975000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ddaada788b45..ae4f04984d86 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -26,11 +26,24 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 874e66dbb93b..cb18bb457568 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -47,10 +47,27 @@ #address-cells = <1>; #size-cells = <0>; - cpu@500 { + cpu0: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>; + operating-points = < + /* KHz uV */ + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@501 { device_type = "cpu"; From 3adb1327fb020394a10394a5117ac7d2ec5334d3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Sep 2014 00:34:30 +0200 Subject: [PATCH 2/6] ARM: dts: rockchip: add cpu supplies to boards This adds the cpu-supplies to the curie2, radxarock and rk3288-evb-rk808 boards. The rk3288-evb-act8846 variant cannot provide the cpu-regulator at the moment so will get its supply later. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 4 ++++ arch/arm/boot/dts/rk3188-radxarock.dts | 6 +++++- arch/arm/boot/dts/rk3288-evb-rk808.dts | 6 +++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index d5344510c676..baf21ac6ce7f 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -60,6 +60,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 15910c9ddbc7..0950a0524947 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -118,6 +118,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -159,7 +163,7 @@ vdd_arm: REG3 { regulator-name = "VDD_ARM"; regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-always-on; }; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index ff522f8e3df4..d8c775e6d5fe 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -17,6 +17,10 @@ compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; }; +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -44,7 +48,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-name = "vdd_arm"; }; From b3e3a7b25825407144a0178f291b20697f1537fb Mon Sep 17 00:00:00 2001 From: Julien CHAUVEAU Date: Fri, 10 Oct 2014 10:04:13 +0200 Subject: [PATCH 3/6] ARM: dts: rockchip: enable DMA on SPI for rk3066 and rk3188 According to the RK3066 and RK3188 TRM, the two SPI controllers support DMA handshake interface. Add the DMA properties so they can be used when needed. Signed-off-by: Julien CHAUVEAU Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 499468d42ada..9ba92de511ca 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -367,6 +367,8 @@ reg = <0x20070000 0x1000>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -378,6 +380,8 @@ reg = <0x20074000 0x1000>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From 5fe62b83cfed00b10b70593e95ffbeadf77ece78 Mon Sep 17 00:00:00 2001 From: Julien CHAUVEAU Date: Tue, 14 Oct 2014 10:16:37 +0200 Subject: [PATCH 4/6] ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188 Add the I2S/PCM controller nodes and pin controls for rk3066 and rk3188. Signed-off-by: Julien CHAUVEAU Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 81 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 26 +++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 8b11fbd58071..0e99470db772 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -63,6 +63,51 @@ }; }; + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; @@ -415,6 +460,42 @@ ; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + , + , + , + ; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ae4f04984d86..b24e04f6ccc7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -78,6 +78,21 @@ }; }; + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; @@ -408,6 +423,17 @@ ; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; }; }; From cd78d0cd63ebce518b5c342fe6ef1f4613bb039d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 9 Oct 2014 21:50:30 -0700 Subject: [PATCH 5/6] ARM: dts: rockchip: enable init rate for clock We need to initialize PLL rate and some of bus clock rate while kernel init, for there is no other module will do that. Basically on rk3288 we use GPLL for cpu bus, peripheral bus and most of peripheral clock, CPLL for devices who require 50M/200M clock rate, leave NPLL behind for special requirement from display system. The common-clock-framework will help us to select best source for child clocks after we init the PLLs propriety. Signed-off-by: Kever Yang Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cb18bb457568..b53e833e5667 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -472,6 +472,16 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <500000000>, <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; }; grf: syscon@ff770000 { From 11bd57b82e6802765d1a1b33405bbaff82615d65 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Fri, 24 Oct 2014 14:42:06 -0700 Subject: [PATCH 6/6] ARM: dts: rockchip: Add SPI DMA into rk3288.dtsi Now that SPI DMA has been fixed on rk3288 we can enable it. Signed-off-by: Doug Anderson Signed-off-by: Alexandru M Stan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index b53e833e5667..cfc43789cac6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -194,6 +194,8 @@ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 11>, <&dmac_peri 12>; + dma-names = "tx", "rx"; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; @@ -207,6 +209,8 @@ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 13>, <&dmac_peri 14>; + dma-names = "tx", "rx"; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; @@ -220,6 +224,8 @@ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 15>, <&dmac_peri 16>; + dma-names = "tx", "rx"; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;