dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
Convert mediatek,dsi.txt to mediatek,dsi.yaml format Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220504091923.2219-2-rex-bc.chen@mediatek.com/ Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
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Xinlei Lee
Chun-Kuang Hu
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22ffb89ee3
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Mediatek DSI Device
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===================
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The Mediatek DSI function block is a sink of the display subsystem and can
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drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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channel output.
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Required properties:
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- compatible: "mediatek,<chip>-dsi"
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- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: must contain "engine", "digital", and "hs"
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- phys: phandle link to the MIPI D-PHY controller.
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- phy-names: must contain "dphy"
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- port: Output port node with endpoint definitions as described in
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Documentation/devicetree/bindings/graph.txt. This port should be connected
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to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
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Optional properties:
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- resets: list of phandle + reset specifier pair, as described in [1].
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[1] Documentation/devicetree/bindings/reset/reset.txt
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MIPI TX Configuration Module
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============================
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See phy/mediatek,dsi-phy.yaml
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Example:
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mipi_tx0: mipi-dphy@10215000 {
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compatible = "mediatek,mt8173-mipi-tx";
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reg = <0 0x10215000 0 0x1000>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx0_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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drive-strength-microamp = <4600>;
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nvmem-cells= <&mipi_tx_calibration>;
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nvmem-cell-names = "calibration-data";
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};
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dsi0: dsi@1401b000 {
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compatible = "mediatek,mt8173-dsi";
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reg = <0 0x1401b000 0 0x1000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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port {
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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@ -0,0 +1,115 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek DSI Controller Device Tree Bindings
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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- Jitao Shi <jitao.shi@mediatek.com>
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- Xinlei Lee <xinlei.lee@mediatek.com>
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description: |
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The MediaTek DSI function block is a sink of the display subsystem and can
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drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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channel output.
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allOf:
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- $ref: /schemas/display/dsi-controller.yaml#
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properties:
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compatible:
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enum:
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- mediatek,mt2701-dsi
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- mediatek,mt7623-dsi
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- mediatek,mt8167-dsi
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- mediatek,mt8173-dsi
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- mediatek,mt8183-dsi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Engine Clock
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- description: Digital Clock
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- description: HS Clock
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clock-names:
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items:
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- const: engine
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- const: digital
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- const: hs
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resets:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: dphy
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output port node. This port should be connected to the input
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port of an attached DSI panel or DSI-to-eDP encoder chip.
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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- clock-names
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- phys
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- phy-names
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- port
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt8183-resets.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dsi0: dsi@14014000 {
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compatible = "mediatek,mt8183-dsi";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DSI0_MM>,
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<&mmsys CLK_MM_DSI0_IF>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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port {
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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...
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