Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"This is going to rebuild more than drm as it adds a new helper to
list.h for doing bulk updates. Seemed like a reasonable addition to
me.
Otherwise the usual merge window stuff lots of i915 and amdgpu, not so
much nouveau, and piles of everything else.
Core:
- Adds a new list.h helper for doing bulk list updates for TTM.
- Don't leak fb address in smem_start to userspace (comes with EXPORT
workaround for people using mali out of tree hacks)
- udmabuf device to turn memfd regions into dma-buf
- Per-plane blend mode property
- ref/unref replacements with get/put
- fbdev conflicting framebuffers code cleaned up
- host-endian format variants
- panel orientation quirk for Acer One 10
bridge:
- TI SN65DSI86 chip support
vkms:
- GEM support.
- Cursor support
amdgpu:
- Merge amdkfd and amdgpu into one module
- CEC over DP AUX support
- Picasso APU support + VCN dynamic powergating
- Raven2 APU support
- Vega20 enablement + kfd support
- ACP powergating improvements
- ABGR/XBGR display support
- VCN jpeg support
- xGMI support
- DC i2c/aux cleanup
- Ycbcr 4:2:0 support
- GPUVM improvements
- Powerplay and powerplay endian fixes
- Display underflow fixes
vmwgfx:
- Move vmwgfx specific TTM code to vmwgfx
- Split out vmwgfx buffer/resource validation code
- Atomic operation rework
bochs:
- use more helpers
- format/byteorder improvements
qxl:
- use more helpers
i915:
- GGTT coherency getparam
- Turn off resource streamer API
- More Icelake enablement + DMC firmware
- Full PPGTT for Ivybridge, Haswell and Valleyview
- DDB distribution based on resolution
- Limited range DP display support
nouveau:
- CEC over DP AUX support
- Initial HDMI 2.0 support
virtio-gpu:
- vmap support for PRIME objects
tegra:
- Initial Tegra194 support
- DMA/IOMMU integration fixes
msm:
- a6xx perf improvements + clock prefix
- GPU preemption optimisations
- a6xx devfreq support
- cursor support
rockchip:
- PX30 support
- rgb output interface support
mediatek:
- HDMI output support on mt2701 and mt7623
rcar-du:
- Interlaced modes on Gen3
- LVDS on R8A77980
- D3 and E3 SoC support
hisilicon:
- misc fixes
mxsfb:
- runtime pm support
sun4i:
- R40 TCON support
- Allwinner A64 support
- R40 HDMI support
omapdrm:
- Driver rework changing display pipeline ordering to use common code
- DMM memory barrier and irq fixes
- Errata workarounds
exynos:
- out-bridge support for LVDS bridge driver
- Samsung 16x16 tiled format support
- Plane alpha and pixel blend mode support
tilcdc:
- suspend/resume update
mali-dp:
- misc updates"
* tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits)
firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.
drm/i915/icl: Fix signal_levels
drm/i915/icl: Fix DDI/TC port clk_off bits
drm/i915/icl: create function to identify combophy port
drm/i915/gen9+: Fix initial readout for Y tiled framebuffers
drm/i915: Large page offsets for pread/pwrite
drm/i915/selftests: Disable shrinker across mmap-exhaustion
drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode
drm/i915: Fix intel_dp_mst_best_encoder()
drm/i915: Skip vcpi allocation for MSTB ports that are gone
drm/i915: Don't unset intel_connector->mst_port
drm/i915: Only reset seqno if actually idle
drm/i915: Use the correct crtc when sanitizing plane mapping
drm/i915: Restore vblank interrupts earlier
drm/i915: Check fb stride against plane max stride
drm/amdgpu/vcn:Fix uninitialized symbol error
drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003)
drm/amd/amdgpu: Fix debugfs error handling
drm/amdgpu: Update gc_9_0 golden settings.
drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields
...
This commit is contained in:
Linus Torvalds
@@ -665,6 +665,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
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/* Subquery id: Query GFX RLC SRLS firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
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/* Subquery id: Query DMCU firmware version */
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#define AMDGPU_INFO_FW_DMCU 0x12
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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/* the used VRAM size */
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@@ -30,11 +30,50 @@
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extern "C" {
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#endif
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/**
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* DOC: overview
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*
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* In the DRM subsystem, framebuffer pixel formats are described using the
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* fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
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* fourcc code, a Format Modifier may optionally be provided, in order to
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* further describe the buffer's format - for example tiling or compression.
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*
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* Format Modifiers
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* ----------------
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*
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* Format modifiers are used in conjunction with a fourcc code, forming a
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* unique fourcc:modifier pair. This format:modifier pair must fully define the
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* format and data layout of the buffer, and should be the only way to describe
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* that particular buffer.
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*
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* Having multiple fourcc:modifier pairs which describe the same layout should
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* be avoided, as such aliases run the risk of different drivers exposing
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* different names for the same data format, forcing userspace to understand
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* that they are aliases.
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*
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* Format modifiers may change any property of the buffer, including the number
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* of planes and/or the required allocation size. Format modifiers are
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* vendor-namespaced, and as such the relationship between a fourcc code and a
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* modifier is specific to the modifer being used. For example, some modifiers
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* may preserve meaning - such as number of planes - from the fourcc code,
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* whereas others may not.
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*
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* Vendors should document their modifier usage in as much detail as
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* possible, to ensure maximum compatibility across devices, drivers and
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* applications.
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*
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* The authoritative list of format modifier codes is found in
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* `include/uapi/drm/drm_fourcc.h`
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*/
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#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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((__u32)(c) << 16) | ((__u32)(d) << 24))
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#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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/* Reserve 0 for the invalid format specifier */
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#define DRM_FORMAT_INVALID 0
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/* color index */
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#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
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@@ -299,6 +338,15 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/*
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* Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
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*
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* This is a simple tiled layout using tiles of 16x16 pixels in a row-major
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* layout. For YCbCr formats Cb/Cr components are taken in such a way that
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* they correspond to their 16x16 luma block.
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
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/*
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* Qualcomm Compressed Format
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*
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@@ -186,8 +186,9 @@ extern "C" {
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/*
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* DRM_MODE_REFLECT_<axis>
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*
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* Signals that the contents of a drm plane is reflected in the <axis> axis,
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* Signals that the contents of a drm plane is reflected along the <axis> axis,
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* in the same way as mirroring.
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* See kerneldoc chapter "Plane Composition Properties" for more details.
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*
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* This define is provided as a convenience, looking up the property id
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* using the name->prop id lookup is the preferred method.
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@@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait {
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*/
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#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
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/*
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* Once upon a time we supposed that writes through the GGTT would be
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* immediately in physical memory (once flushed out of the CPU path). However,
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* on a few different processors and chipsets, this is not necessarily the case
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* as the writes appear to be buffered internally. Thus a read of the backing
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* storage (physical memory) via a different path (with different physical tags
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* to the indirect write via the GGTT) will see stale values from before
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* the GGTT write. Inside the kernel, we can for the most part keep track of
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* the different read/write domains in use (e.g. set-domain), but the assumption
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* of coherency is baked into the ABI, hence reporting its true state in this
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* parameter.
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*
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* Reports true when writes via mmap_gtt are immediately visible following an
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* lfence to flush the WCB.
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*
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* Reports false when writes via mmap_gtt are indeterminately delayed in an in
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* internal buffer and are _not_ immediately visible to third parties accessing
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* directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
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* communications channel when reporting false is strongly disadvised.
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*/
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#define I915_PARAM_MMAP_GTT_COHERENT 52
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typedef struct drm_i915_getparam {
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__s32 param;
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/*
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@@ -82,6 +82,14 @@ struct kfd_ioctl_set_cu_mask_args {
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__u64 cu_mask_ptr; /* to KFD */
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};
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struct kfd_ioctl_get_queue_wave_state_args {
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uint64_t ctl_stack_address; /* to KFD */
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uint32_t ctl_stack_used_size; /* from KFD */
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uint32_t save_area_used_size; /* from KFD */
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uint32_t queue_id; /* to KFD */
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uint32_t pad;
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};
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/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
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#define KFD_IOC_CACHE_POLICY_COHERENT 0
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#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
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@@ -475,7 +483,10 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
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#define AMDKFD_IOC_SET_CU_MASK \
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AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
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#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
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AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
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#define AMDKFD_COMMAND_START 0x01
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#define AMDKFD_COMMAND_END 0x1B
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#define AMDKFD_COMMAND_END 0x1C
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#endif
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33
include/uapi/linux/udmabuf.h
Normal file
33
include/uapi/linux/udmabuf.h
Normal file
@@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_LINUX_UDMABUF_H
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#define _UAPI_LINUX_UDMABUF_H
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#define UDMABUF_FLAGS_CLOEXEC 0x01
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struct udmabuf_create {
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__u32 memfd;
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__u32 flags;
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__u64 offset;
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__u64 size;
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};
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struct udmabuf_create_item {
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__u32 memfd;
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__u32 __pad;
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__u64 offset;
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__u64 size;
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};
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struct udmabuf_create_list {
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__u32 flags;
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__u32 count;
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struct udmabuf_create_item list[];
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};
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#define UDMABUF_CREATE _IOW('u', 0x42, struct udmabuf_create)
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#define UDMABUF_CREATE_LIST _IOW('u', 0x43, struct udmabuf_create_list)
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#endif /* _UAPI_LINUX_UDMABUF_H */
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