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Merge branch 'linus' into x86/kconfig

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This commit is contained in:
Ingo Molnar
2008-06-16 11:28:04 +02:00
parent 1ac9701816 066519068a
commit 7aaaec38fc
1984 changed files with 41887 additions and 20335 deletions
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1
include/acpi/processor.h
View File

@@ -319,6 +319,7 @@ static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr)
#endif /* CONFIG_CPU_FREQ */
/* in processor_throttling.c */
int acpi_processor_tstate_has_changed(struct acpi_processor *pr);
int acpi_processor_get_throttling_info(struct acpi_processor *pr);
extern int acpi_processor_set_throttling(struct acpi_processor *pr, int state);
extern struct file_operations acpi_processor_throttling_fops;

2
include/asm-alpha/barrier.h
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@@ -24,7 +24,7 @@ __asm__ __volatile__("mb": : :"memory")
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#define smp_read_barrier_depends() do { } while (0)
#endif
#define set_mb(var, value) \

4
include/asm-alpha/param.h
View File

@@ -5,8 +5,12 @@
hardware ignores reprogramming. We also need userland buy-in to the
change in HZ, since this is visible in the wait4 resources etc. */
#ifdef __KERNEL__
#define HZ CONFIG_HZ
#define USER_HZ HZ
#else
#define HZ 1024
#endif
#define EXEC_PAGESIZE 8192

21
include/asm-alpha/pgtable.h
View File

@@ -287,17 +287,34 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; }
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
/*
* The smp_read_barrier_depends() in the following functions are required to
* order the load of *dir (the pointer in the top level page table) with any
* subsequent load of the returned pmd_t *ret (ret is data dependent on *dir).
*
* If this ordering is not enforced, the CPU might load an older value of
* *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
* more details.
*
* Note that we never change the mm->pgd pointer after the task is running, so
* pgd_offset does not require such a barrier.
*/
/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
{
return (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
smp_read_barrier_depends(); /* see above */
return ret;
}
/* Find an entry in the third-level page table.. */
extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
{
return (pte_t *) pmd_page_vaddr(*dir)
pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
+ ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
smp_read_barrier_depends(); /* see above */
return ret;
}
#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))

2
include/asm-arm/arch-at91/io.h
View File

@@ -21,8 +21,6 @@
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/io.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) ((void __iomem *)(a))

2
include/asm-arm/arch-omap/board-palmte.h
View File

@@ -14,8 +14,6 @@
#ifndef __OMAP_BOARD_PALMTE_H
#define __OMAP_BOARD_PALMTE_H
#include <asm/arch/gpio.h>
#define PALMTE_USBDETECT_GPIO 0
#define PALMTE_USB_OR_DC_GPIO 1
#define PALMTE_TSC_GPIO 4

5
include/asm-arm/arch-omap/clock.h
View File

@@ -73,6 +73,8 @@ struct clk {
#endif
};
struct cpufreq_frequency_table;
struct clk_functions {
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
@@ -83,6 +85,9 @@ struct clk_functions {
void (*clk_allow_idle)(struct clk *clk);
void (*clk_deny_idle)(struct clk *clk);
void (*clk_disable_unused)(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
#endif
};
extern unsigned int mpurate;

4
include/asm-arm/arch-omap/common.h
View File

@@ -47,4 +47,8 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
}
#endif
void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_343x(void);
#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

2
include/asm-arm/arch-omap/control.h
View File

@@ -80,7 +80,7 @@
#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074
#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)

1
include/asm-arm/arch-omap/entry-macro.S
View File

@@ -8,6 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/irqs.h>
#if defined(CONFIG_ARCH_OMAP1)

1
include/asm-arm/arch-omap/gpio.h
View File

@@ -26,7 +26,6 @@
#ifndef __ASM_ARCH_OMAP_GPIO_H
#define __ASM_ARCH_OMAP_GPIO_H
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/io.h>

1
include/asm-arm/arch-omap/hardware.h
View File

@@ -41,7 +41,6 @@
#include <asm/types.h>
#include <asm/arch/cpu.h>
#endif
#include <asm/arch/io.h>
#include <asm/arch/serial.h>
/*

24
include/asm-arm/arch-omap/mmc.h
View File

@@ -15,21 +15,16 @@
#include <linux/device.h>
#include <linux/mmc/host.h>
#include <asm/arch/board.h>
#define OMAP_MMC_MAX_SLOTS 2
struct omap_mmc_platform_data {
struct omap_mmc_conf conf;
unsigned enabled:1;
/* number of slots on board */
unsigned nr_slots:2;
/* nomux means "standard" muxing is wrong on this board, and that
* board-specific code handled it before common init logic.
*/
unsigned nomux:1;
/* 4 wire signaling is optional, and is only used for SD/SDIO and
* MMCv4 */
unsigned wire4:1;
/* set if your board has components or wiring that limits the
* maximum frequency on the MMC bus */
unsigned int max_freq;
@@ -40,6 +35,11 @@ struct omap_mmc_platform_data {
* not supported */
int (* init)(struct device *dev);
void (* cleanup)(struct device *dev);
void (* shutdown)(struct device *dev);
/* To handle board related suspend/resume functionality for MMC */
int (*suspend)(struct device *dev, int slot);
int (*resume)(struct device *dev, int slot);
struct omap_mmc_slot_data {
int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
@@ -56,13 +56,19 @@ struct omap_mmc_platform_data {
const char *name;
u32 ocr_mask;
/* Card detection IRQs */
int card_detect_irq;
int (* card_detect)(int irq);
unsigned int ban_openended:1;
} slots[OMAP_MMC_MAX_SLOTS];
};
extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info);
/* called from board-specific card detection service routine */
extern void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected);
extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
#endif

1
include/asm-arm/arch-pxa/mfp-pxa27x.h
View File

@@ -112,6 +112,7 @@
#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
/* I2C */
#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1)

9
include/asm-arm/arch-pxa/pxa2xx-gpio.h
View File

@@ -134,7 +134,11 @@
#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
#define GPIO96_FFRXD 96 /* FFUART recieve */
#define GPIO98_FFRTS 98 /* FFUART request to send */
#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
#define GPIO99_FFTXD 99 /* FFUART transmit data */
#define GPIO100_FFCTS 100 /* FFUART Clear to send */
#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
@@ -316,6 +320,8 @@
#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN)
#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT)
#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
@@ -324,8 +330,11 @@
#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN)
#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT)
#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT)
#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)

5
include/asm-arm/arch-pxa/regs-lcd.h
View File

@@ -1,5 +1,8 @@
#ifndef __ASM_ARCH_REGS_LCD_H
#define __ASM_ARCH_REGS_LCD_H
#include <asm/arch/bitfield.h>
/*
* LCD Controller Registers and Bits Definitions
*/
@@ -69,7 +72,7 @@
#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
#define LCCR0_PDD_S 12
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
#define LCCR0_LCDT (1 << 22) /* LCD panel type */
#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */

4
include/asm-arm/arch-sa1100/collie.h
View File

@@ -34,9 +34,12 @@
#define COLLIE_GPIO_ON_KEY GPIO_GPIO (0)
#define COLLIE_GPIO_AC_IN GPIO_GPIO (1)
#define COLLIE_GPIO_SDIO_INT GPIO_GPIO (11)
#define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14)
#define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15)
#define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16)
#define COLLIE_GPIO_nMIC_ON GPIO_GPIO (17)
#define COLLIE_GPIO_nREMOCON_ON GPIO_GPIO (18)
#define COLLIE_GPIO_CO GPIO_GPIO (20)
#define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21)
#define COLLIE_GPIO_CF_CD GPIO_GPIO (22)
@@ -49,6 +52,7 @@
#define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0
#define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1
#define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11
#define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14
#define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15
#define COLLIE_IRQ_GPIO_CO IRQ_GPIO20

2
include/asm-arm/arch-sa1100/irqs.h
View File

@@ -141,7 +141,7 @@
#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17)
#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18)
#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19)
#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20)
#define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20)
#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21)
/*

19
include/asm-arm/hardware/locomo.h
View File

@@ -58,6 +58,11 @@
#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
#define LOCOMO_SPICT 0x04 /* SPI mode control */
#define LOCOMO_SPIST 0x08 /* SPI status */
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
#define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
#define LOCOMO_SPI_RFR (1) /* read buffer bit */
#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
@@ -66,16 +71,12 @@
#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
#define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
#define LOCOMO_SPI_RFR (1) /* read buffer bit */
/* GPIO */
#define LOCOMO_GPD 0x90 /* GPIO direction */
#define LOCOMO_GPE 0x94 /* GPIO input enable */
#define LOCOMO_GPL 0x98 /* GPIO level */
#define LOCOMO_GPO 0x9c /* GPIO out data setteing */
#define LOCOMO_GPO 0x9c /* GPIO out data setting */
#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
@@ -96,6 +97,9 @@
#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
#define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14)
#define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15)
/* Start the definitions of the devices. Each device has an initial
* base address and a series of offsets from that base address. */
@@ -122,7 +126,7 @@
/* Audio controller */
#define LOCOMO_AUDIO 0x54
#define LOCOMO_ACC 0x00 /* Audio clock */
#define LOCOMO_PAIF 0x7C /* PCM audio interface */
#define LOCOMO_PAIF 0xD0 /* PCM audio interface */
/* Audio clock */
#define LOCOMO_ACC_XON 0x80
#define LOCOMO_ACC_XEN 0x40
@@ -162,7 +166,7 @@ extern struct bus_type locomo_bus_type;
#define LOCOMO_DEVID_AUDIO 3
#define LOCOMO_DEVID_LED 4
#define LOCOMO_DEVID_UART 5
#define LOCOMO_DEVID_SPI 6
#define LOCOMO_DEVID_SPI 6
struct locomo_dev {
struct device dev;
@@ -204,7 +208,6 @@ int locomo_gpio_read_level(struct device *dev, unsigned int bits);
int locomo_gpio_read_output(struct device *dev, unsigned int bits);
void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
/* M62332 control function */
void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);

4
include/asm-arm/page.h
View File

@@ -179,10 +179,10 @@ typedef unsigned long pgprot_t;
#endif /* STRICT_MM_TYPECHECKS */
typedef struct page *pgtable_t;
#endif /* CONFIG_MMU */
typedef struct page *pgtable_t;
#include <asm/memory.h>
#endif /* !__ASSEMBLY__ */

1
include/asm-arm/pgtable-nommu.h
View File

@@ -16,7 +16,6 @@
#include <linux/slab.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/io.h>
/*
* Trivial page table functions.

2
include/asm-arm/spinlock.h
View File

@@ -142,7 +142,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
}
/* write_can_lock - would write_trylock() succeed? */
#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
#define __raw_write_can_lock(x) ((x)->lock == 0)
/*
* Read locks are a bit more hairy:

29
include/asm-arm/system.h
View File

@@ -48,20 +48,6 @@
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
#else
#define read_cpuid(reg) (processor_id)
#endif
/*
* This is used to ensure the compiler did actually allocate the register we
* asked it for some inline assembly sequences. Apparently we can't trust
@@ -78,6 +64,21 @@
#include <linux/stringify.h>
#include <linux/irqflags.h>
#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
#else
extern unsigned int processor_id;
#define read_cpuid(reg) (processor_id)
#endif
/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID

11
include/asm-blackfin/bfin-global.h
View File

@@ -37,7 +37,9 @@
#include <linux/linkage.h>
#include <linux/types.h>
#if defined(CONFIG_DMA_UNCACHED_2M)
#if defined(CONFIG_DMA_UNCACHED_4M)
# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
#elif defined(CONFIG_DMA_UNCACHED_2M)
# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
#elif defined(CONFIG_DMA_UNCACHED_1M)
# define DMA_UNCACHED_REGION (1024 * 1024)
@@ -103,13 +105,6 @@ extern int sram_free(const void*);
extern void *sram_alloc_with_lsl(size_t, unsigned long);
extern int sram_free_with_lsl(const void*);
extern void led_on(int);
extern void led_off(int);
extern void led_toggle(int);
extern void led_disp_num(int);
extern void led_toggle_num(int);
extern void init_leds(void);
extern const char bfin_board_name[];
extern unsigned long wall_jiffies;

29
include/asm-blackfin/checksum.h
View File

@@ -15,7 +15,7 @@
*
* it's best to have buff aligned on a 32-bit boundary
*/
unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
__wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* the same as csum_partial, but copies from src while it
@@ -25,8 +25,8 @@ unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
* better 64-bit) boundary
*/
unsigned int csum_partial_copy(const unsigned char *src, unsigned char *dst,
int len, int sum);
__wsum csum_partial_copy(const void *src, void *dst,
int len, __wsum sum);
/*
* the same as csum_partial_copy, but copies from user space.
@@ -35,20 +35,19 @@ unsigned int csum_partial_copy(const unsigned char *src, unsigned char *dst,
* better 64-bit) boundary
*/
extern unsigned int csum_partial_copy_from_user(const unsigned char *src,
unsigned char *dst, int len,
int sum, int *csum_err);
extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
int len, __wsum sum, int *csum_err);
#define csum_partial_copy_nocheck(src, dst, len, sum) \
csum_partial_copy((src), (dst), (len), (sum))
unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl);
__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
/*
* Fold a partial checksum
*/
static inline unsigned int csum_fold(unsigned int sum)
static inline __sum16 csum_fold(__wsum sum)
{
while (sum >> 16)
sum = (sum & 0xffff) + (sum >> 16);
@@ -60,9 +59,9 @@ static inline unsigned int csum_fold(unsigned int sum)
* returns a 16-bit checksum, already complemented
*/
static inline unsigned int
csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len,
unsigned short proto, unsigned int sum)
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
__asm__ ("%0 = %0 + %1;\n\t"
@@ -84,9 +83,9 @@ csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len,
return (sum);
}
static inline unsigned short int
csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
unsigned short proto, unsigned int sum)
static inline __sum16
csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
}
@@ -96,6 +95,6 @@ csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
* in icmp.c
*/
extern unsigned short ip_compute_csum(const unsigned char *buff, int len);
extern __sum16 ip_compute_csum(const void *buff, int len);
#endif /* _BFIN_CHECKSUM_H */

1
include/asm-blackfin/gpio.h
View File

@@ -437,7 +437,6 @@ void gpio_set_value(unsigned gpio, int arg);
int gpio_get_value(unsigned gpio);
#ifndef BF548_FAMILY
#define gpio_get_value(gpio) get_gpio_data(gpio)
#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
#endif

2
include/asm-blackfin/io.h
View File

@@ -117,10 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr)
extern void outsb(unsigned long port, const void *addr, unsigned long count);
extern void outsw(unsigned long port, const void *addr, unsigned long count);
extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
extern void outsl(unsigned long port, const void *addr, unsigned long count);
extern void insb(unsigned long port, void *addr, unsigned long count);
extern void insw(unsigned long port, void *addr, unsigned long count);
extern void insw_8(unsigned long port, void *addr, unsigned long count);
extern void insl(unsigned long port, void *addr, unsigned long count);
extern void insl_16(unsigned long port, void *addr, unsigned long count);

5
include/asm-blackfin/mach-bf527/anomaly.h
View File

@@ -15,12 +15,16 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
@@ -92,7 +96,6 @@
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)

6
include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS

8
include/asm-blackfin/mach-bf527/blackfin.h
View File

@@ -39,22 +39,22 @@
#include "defBF522.h"
#include "anomaly.h"
#if defined(CONFIG_BF527)
#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
#include "defBF527.h"
#endif
#if defined(CONFIG_BF525)
#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
#include "defBF525.h"
#endif
#if !defined(__ASSEMBLY__)
#include "cdefBF522.h"
#if defined(CONFIG_BF527)
#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
#include "cdefBF527.h"
#endif
#if defined(CONFIG_BF525)
#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
#include "cdefBF525.h"
#endif
#endif

31
include/asm-blackfin/mach-bf533/anomaly.h
View File

@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf533/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
@@ -176,6 +176,21 @@
#define ANOMALY_05000315 (1)
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* PPI Does Not Start Properly In Specific Mode */
#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
@@ -249,20 +264,6 @@
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
/* Internal Voltage Regulator may not start up */
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* PPI Does Not Start Properly In Specific Mode */
#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0)

6
include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN

10
include/asm-blackfin/mach-bf537/anomaly.h
View File

@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf537/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
@@ -132,8 +132,8 @@
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
/* New Feature: UART Remains Enabled after UART Boot */
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -145,12 +145,10 @@
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000158 (0)

6
include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS

2
include/asm-blackfin/mach-bf548/anomaly.h
View File

@@ -75,6 +75,8 @@
#define ANOMALY_05000365 (1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */

6
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
View File

@@ -57,6 +57,12 @@
#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS

2
include/asm-blackfin/mach-bf561/anomaly.h
View File

@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf561/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/

6
include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN

8
include/asm-blackfin/mach-bf561/dma.h
View File

@@ -25,11 +25,11 @@
#define CH_MEM_STREAM1_SRC 27 /* RX */
#define CH_MEM_STREAM2_DEST 28
#define CH_MEM_STREAM2_SRC 29
#define CH_MEM_STREAM3_SRC 30
#define CH_MEM_STREAM3_DEST 31
#define CH_MEM_STREAM3_DEST 30
#define CH_MEM_STREAM3_SRC 31
#define CH_IMEM_STREAM0_DEST 32
#define CH_IMEM_STREAM0_SRC 33
#define CH_IMEM_STREAM1_SRC 34
#define CH_IMEM_STREAM1_DEST 35
#define CH_IMEM_STREAM1_DEST 34
#define CH_IMEM_STREAM1_SRC 35
#endif

5
include/asm-blackfin/serial.h Normal file
View File

@@ -0,0 +1,5 @@
/*
* include/asm-blackfin/serial.h
*/
#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH

2
include/asm-frv/checksum.h
View File

@@ -75,7 +75,7 @@ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
: "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (inc), "=&r"(tmp)
: "0" (sum), "1" (iph), "2" (ihl), "3" (4),
"m"(*(volatile struct { int _[100]; } *)iph)
: "icc0", "icc1"
: "icc0", "icc1", "memory"
);
return (__force __sum16)~sum;

7
include/asm-frv/mem-layout.h
View File

@@ -31,6 +31,13 @@
#define PAGE_MASK (~(PAGE_SIZE-1))
/*
* the slab must be aligned such that load- and store-double instructions don't
* fault if used
*/
#define ARCH_KMALLOC_MINALIGN 8
#define ARCH_SLAB_MINALIGN 8
/*****************************************************************************/
/*
* virtual memory layout from kernel's point of view

2
include/asm-frv/system.h
View File

@@ -179,7 +179,7 @@ do { \
#define mb() asm volatile ("membar" : : :"memory")
#define rmb() asm volatile ("membar" : : :"memory")
#define wmb() asm volatile ("membar" : : :"memory")
#define read_barrier_depends() barrier()
#define read_barrier_depends() do { } while (0)
#ifdef CONFIG_SMP
#define smp_mb() mb()

6
include/asm-generic/gpio.h
View File

@@ -1,8 +1,12 @@
#ifndef _ASM_GENERIC_GPIO_H
#define _ASM_GENERIC_GPIO_H
#include <linux/types.h>
#ifdef CONFIG_HAVE_GPIO_LIB
#include <linux/compiler.h>
/* Platforms may implement their GPIO interface with library code,
* at a small performance cost for non-inlined operations and some
* extra memory (for code and for per-GPIO table entries).
@@ -74,7 +78,7 @@ struct gpio_chip {
extern const char *gpiochip_is_requested(struct gpio_chip *chip,
unsigned offset);
extern int __init __must_check gpiochip_reserve(int start, int ngpio);
extern int __must_check gpiochip_reserve(int start, int ngpio);
/* add/remove chips */
extern int gpiochip_add(struct gpio_chip *chip);

2
include/asm-h8300/cacheflush.h
View File

@@ -3,7 +3,7 @@
*/
#ifndef _ASM_H8300_CACHEFLUSH_H
#define _AMS_H8300_CACHEFLUSH_H
#define _ASM_H8300_CACHEFLUSH_H
/*
* Cache handling functions

8
include/asm-h8300/param.h
View File

@@ -1,14 +1,12 @@
#ifndef _H8300_PARAM_H
#define _H8300_PARAM_H
#ifndef HZ
#define HZ CONFIG_HZ
#endif
#ifdef __KERNEL__
#define HZ CONFIG_HZ
#define USER_HZ HZ
#define CLOCKS_PER_SEC (USER_HZ)
#else
#define HZ 100
#endif
#define EXEC_PAGESIZE 4096

12
include/asm-ia64/kvm.h
View File

@@ -22,14 +22,13 @@
*/
#include <asm/types.h>
#include <asm/fpu.h>
#include <linux/ioctl.h>
/* Architectural interrupt line count. */
#define KVM_NR_INTERRUPTS 256
#define KVM_IOAPIC_NUM_PINS 24
#define KVM_IOAPIC_NUM_PINS 48
struct kvm_ioapic_state {
__u64 base_address;
@@ -61,6 +60,13 @@ struct kvm_ioapic_state {
#define KVM_CONTEXT_SIZE 8*1024
struct kvm_fpreg {
union {
unsigned long bits[2];
long double __dummy; /* force 16-byte alignment */
} u;
};
union context {
/* 8K size */
char dummy[KVM_CONTEXT_SIZE];
@@ -77,7 +83,7 @@ union context {
unsigned long ibr[8];
unsigned long dbr[8];
unsigned long pkr[8];
struct ia64_fpreg fr[128];
struct kvm_fpreg fr[128];
};
};

2
include/asm-ia64/machvec.h
View File

@@ -126,6 +126,8 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *);
# include <asm/machvec_hpzx1_swiotlb.h>
# elif defined (CONFIG_IA64_SGI_SN2)
# include <asm/machvec_sn2.h>
# elif defined (CONFIG_IA64_SGI_UV)
# include <asm/machvec_uv.h>
# elif defined (CONFIG_IA64_GENERIC)
# ifdef MACHVEC_PLATFORM_HEADER

26
include/asm-ia64/machvec_uv.h Normal file
View File

@@ -0,0 +1,26 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV Core Functions
*
* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_MACHVEC_UV_H
#define _ASM_IA64_MACHVEC_UV_H
extern ia64_mv_setup_t uv_setup;
/*
* This stuff has dual use!
*
* For a generic kernel, the macros are used to initialize the
* platform's machvec structure. When compiling a non-generic kernel,
* the macros are used directly.
*/
#define platform_name "uv"
#define platform_setup uv_setup
#endif /* _ASM_IA64_MACHVEC_UV_H */

1
include/asm-ia64/patch.h
View File

@@ -21,6 +21,7 @@ extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel
extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end);
extern void ia64_patch_vtop (unsigned long start, unsigned long end);
extern void ia64_patch_phys_stack_reg(unsigned long val);
extern void ia64_patch_rse (unsigned long start, unsigned long end);
extern void ia64_patch_gate (void);
#endif /* _ASM_IA64_PATCH_H */

2
include/asm-ia64/ptrace.h
View File

@@ -76,7 +76,7 @@
# define KERNEL_STACK_SIZE_ORDER 0
#endif
#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 15) & ~15)
#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31)
#define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE)
#define KERNEL_STACK_SIZE IA64_STK_OFFSET

1
include/asm-ia64/sections.h
View File

@@ -10,6 +10,7 @@
extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
extern char __start___rse_patchlist[], __end___rse_patchlist[];
extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[];
extern char __start_gate_section[];

309
include/asm-ia64/uv/uv_hub.h Normal file
View File

@@ -0,0 +1,309 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV architectural definitions
*
* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef __ASM_IA64_UV_HUB_H__
#define __ASM_IA64_UV_HUB_H__
#include <linux/numa.h>
#include <linux/percpu.h>
#include <asm/types.h>
#include <asm/percpu.h>
/*
* Addressing Terminology
*
* M - The low M bits of a physical address represent the offset
* into the blade local memory. RAM memory on a blade is physically
* contiguous (although various IO spaces may punch holes in
* it)..
*
* N - Number of bits in the node portion of a socket physical
* address.
*
* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
* routers always have low bit of 1, C/MBricks have low bit
* equal to 0. Most addressing macros that target UV hub chips
* right shift the NASID by 1 to exclude the always-zero bit.
* NASIDs contain up to 15 bits.
*
* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
* of nasids.
*
* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
* of the nasid for socket usage.
*
*
* NumaLink Global Physical Address Format:
* +--------------------------------+---------------------+
* |00..000| GNODE | NodeOffset |
* +--------------------------------+---------------------+
* |<-------53 - M bits --->|<--------M bits ----->
*
* M - number of node offset bits (35 .. 40)
*
*
* Memory/UV-HUB Processor Socket Address Format:
* +----------------+---------------+---------------------+
* |00..000000000000| PNODE | NodeOffset |
* +----------------+---------------+---------------------+
* <--- N bits --->|<--------M bits ----->
*
* M - number of node offset bits (35 .. 40)
* N - number of PNODE bits (0 .. 10)
*
* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
* The actual values are configuration dependent and are set at
* boot time. M & N values are set by the hardware/BIOS at boot.
*/
/*
* Maximum number of bricks in all partitions and in all coherency domains.
* This is the total number of bricks accessible in the numalink fabric. It
* includes all C & M bricks. Routers are NOT included.
*
* This value is also the value of the maximum number of non-router NASIDs
* in the numalink fabric.
*
* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
*/
#define UV_MAX_NUMALINK_BLADES 16384
/*
* Maximum number of C/Mbricks within a software SSI (hardware may support
* more).
*/
#define UV_MAX_SSI_BLADES 1
/*
* The largest possible NASID of a C or M brick (+ 2)
*/
#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
/*
* The following defines attributes of the HUB chip. These attributes are
* frequently referenced and are kept in the per-cpu data areas of each cpu.
* They are kept together in a struct to minimize cache misses.
*/
struct uv_hub_info_s {
unsigned long global_mmr_base;
unsigned long gpa_mask;
unsigned long gnode_upper;
unsigned long lowmem_remap_top;
unsigned long lowmem_remap_base;
unsigned short pnode;
unsigned short pnode_mask;
unsigned short coherency_domain_number;
unsigned short numa_blade_id;
unsigned char blade_processor_id;
unsigned char m_val;
unsigned char n_val;
};
DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
/*
* Local & Global MMR space macros.
* Note: macros are intended to be used ONLY by inline functions
* in this file - not by other kernel code.
* n - NASID (full 15-bit global nasid)
* g - GNODE (full 15-bit global nasid, right shifted 1)
* p - PNODE (local part of nsids, right shifted 1)
*/
#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
#define UV_LOCAL_MMR_BASE 0xf4000000UL
#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
/*
* Macros for converting between kernel virtual addresses, socket local physical
* addresses, and UV global physical addresses.
* Note: use the standard __pa() & __va() macros for converting
* between socket virtual and socket physical addresses.
*/
/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
if (paddr < uv_hub_info->lowmem_remap_top)
paddr += uv_hub_info->lowmem_remap_base;
return paddr | uv_hub_info->gnode_upper;
}
/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
return __pa(v) | uv_hub_info->gnode_upper;
}
/* socket virtual --> UV global physical address */
static inline void *uv_vgpa(void *v)
{
return (void *)uv_gpa(v);
}
/* UV global physical address --> socket virtual */
static inline void *uv_va(unsigned long gpa)
{
return __va(gpa & uv_hub_info->gpa_mask);
}
/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
}
/*
* Access global MMRs using the low memory MMR32 space. This region supports
* faster MMR access but not all MMRs are accessible in this space.
*/
static inline unsigned long *uv_global_mmr32_address(int pnode,
unsigned long offset)
{
return __va(UV_GLOBAL_MMR32_BASE |
UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}
static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
unsigned long val)
{
*uv_global_mmr32_address(pnode, offset) = val;
}
static inline unsigned long uv_read_global_mmr32(int pnode,
unsigned long offset)
{
return *uv_global_mmr32_address(pnode, offset);
}
/*
* Access Global MMR space using the MMR space located at the top of physical
* memory.
*/
static inline unsigned long *uv_global_mmr64_address(int pnode,
unsigned long offset)
{
return __va(UV_GLOBAL_MMR64_BASE |
UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}
static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
unsigned long val)
{
*uv_global_mmr64_address(pnode, offset) = val;
}
static inline unsigned long uv_read_global_mmr64(int pnode,
unsigned long offset)
{
return *uv_global_mmr64_address(pnode, offset);
}
/*
* Access hub local MMRs. Faster than using global space but only local MMRs
* are accessible.
*/
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
return __va(UV_LOCAL_MMR_BASE | offset);
}
static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
return *uv_local_mmr_address(offset);
}
static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
*uv_local_mmr_address(offset) = val;
}
/*
* Structures and definitions for converting between cpu, node, pnode, and blade
* numbers.
*/
/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
return smp_processor_id();
}
/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
return 0;
}
/* Convert a cpu number to the the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
return 0;
}
/* Convert linux node number to the UV blade number */
static inline int uv_node_to_blade_id(int nid)
{
return 0;
}
/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
return 0;
}
/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
return num_possible_cpus();
}
/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
return num_online_cpus();
}
/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
return 0;
}
/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
return 0;
}
/* Maximum possible number of blades */
static inline int uv_num_possible_blades(void)
{
return 1;
}
#endif /* __ASM_IA64_UV_HUB__ */

266
include/asm-ia64/uv/uv_mmrs.h Normal file
View File

@@ -0,0 +1,266 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV MMR definitions
*
* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef __ASM_IA64_UV_MMRS__
#define __ASM_IA64_UV_MMRS__
/*
* AUTO GENERATED - Do not edit
*/
#define UV_MMR_ENABLE (1UL << 63)
/* ========================================================================= */
/* UVH_NODE_ID */
/* ========================================================================= */
#define UVH_NODE_ID 0x0UL
#define UVH_NODE_ID_FORCE1_SHFT 0
#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
#define UVH_NODE_ID_MANUFACTURER_SHFT 1
#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
#define UVH_NODE_ID_PART_NUMBER_SHFT 12
#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
#define UVH_NODE_ID_REVISION_SHFT 28
#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
#define UVH_NODE_ID_NODE_ID_SHFT 32
#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
#define UVH_NODE_ID_NI_PORT_SHFT 56
#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
union uvh_node_id_u {
unsigned long v;
struct uvh_node_id_s {
unsigned long force1 : 1; /* RO */
unsigned long manufacturer : 11; /* RO */
unsigned long part_number : 16; /* RO */
unsigned long revision : 4; /* RO */
unsigned long node_id : 15; /* RW */
unsigned long rsvd_47 : 1; /* */
unsigned long nodes_per_bit : 7; /* RW */
unsigned long rsvd_55 : 1; /* */
unsigned long ni_port : 4; /* RO */
unsigned long rsvd_60_63 : 4; /* */
} s;
};
/* ========================================================================= */
/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
unsigned long v;
struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
unsigned long rsvd_0_23 : 24; /* */
unsigned long dest_base : 22; /* RW */
unsigned long rsvd_46_63: 18; /* */
} s;
};
/* ========================================================================= */
/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
unsigned long v;
struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
unsigned long rsvd_0_23 : 24; /* */
unsigned long dest_base : 22; /* RW */
unsigned long rsvd_46_63: 18; /* */
} s;
};
/* ========================================================================= */
/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
unsigned long v;
struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
unsigned long rsvd_0_23 : 24; /* */
unsigned long dest_base : 22; /* RW */
unsigned long rsvd_46_63: 18; /* */
} s;
};
/* ========================================================================= */
/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
/* ========================================================================= */
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
union uvh_rh_gam_gru_overlay_config_mmr_u {
unsigned long v;
struct uvh_rh_gam_gru_overlay_config_mmr_s {
unsigned long rsvd_0_27: 28; /* */
unsigned long base : 18; /* RW */
unsigned long gr4 : 1; /* RW */
unsigned long rsvd_47_51: 5; /* */
unsigned long n_gru : 4; /* RW */
unsigned long rsvd_56_62: 7; /* */
unsigned long enable : 1; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
/* ========================================================================= */
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
union uvh_rh_gam_mmr_overlay_config_mmr_u {
unsigned long v;
struct uvh_rh_gam_mmr_overlay_config_mmr_s {
unsigned long rsvd_0_25: 26; /* */
unsigned long base : 20; /* RW */
unsigned long dual_hub : 1; /* RW */
unsigned long rsvd_47_62: 16; /* */
unsigned long enable : 1; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_RTC */
/* ========================================================================= */
#define UVH_RTC 0x28000UL
#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
union uvh_rtc_u {
unsigned long v;
struct uvh_rtc_s {
unsigned long real_time_clock : 56; /* RW */
unsigned long rsvd_56_63 : 8; /* */
} s;
};
/* ========================================================================= */
/* UVH_SI_ADDR_MAP_CONFIG */
/* ========================================================================= */
#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
union uvh_si_addr_map_config_u {
unsigned long v;
struct uvh_si_addr_map_config_s {
unsigned long m_skt : 6; /* RW */
unsigned long rsvd_6_7: 2; /* */
unsigned long n_skt : 4; /* RW */
unsigned long rsvd_12_63: 52; /* */
} s;
};
/* ========================================================================= */
/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
/* ========================================================================= */
#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
union uvh_si_alias0_overlay_config_u {
unsigned long v;
struct uvh_si_alias0_overlay_config_s {
unsigned long rsvd_0_23: 24; /* */
unsigned long base : 8; /* RW */
unsigned long rsvd_32_47: 16; /* */
unsigned long m_alias : 5; /* RW */
unsigned long rsvd_53_62: 10; /* */
unsigned long enable : 1; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
/* ========================================================================= */
#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
union uvh_si_alias1_overlay_config_u {
unsigned long v;
struct uvh_si_alias1_overlay_config_s {
unsigned long rsvd_0_23: 24; /* */
unsigned long base : 8; /* RW */
unsigned long rsvd_32_47: 16; /* */
unsigned long m_alias : 5; /* RW */
unsigned long rsvd_53_62: 10; /* */
unsigned long enable : 1; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
/* ========================================================================= */
#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
union uvh_si_alias2_overlay_config_u {
unsigned long v;
struct uvh_si_alias2_overlay_config_s {
unsigned long rsvd_0_23: 24; /* */
unsigned long base : 8; /* RW */
unsigned long rsvd_32_47: 16; /* */
unsigned long m_alias : 5; /* RW */
unsigned long rsvd_53_62: 10; /* */
unsigned long enable : 1; /* RW */
} s;
};
#endif /* __ASM_IA64_UV_MMRS__ */

2
include/asm-m32r/uaccess.h
View File

@@ -14,6 +14,7 @@
#include <linux/errno.h>
#include <linux/thread_info.h>
#include <asm/page.h>
#include <asm/setup.h>
#define VERIFY_READ 0
#define VERIFY_WRITE 1
@@ -106,7 +107,6 @@ static inline void set_fs(mm_segment_t s)
#else
static inline int access_ok(int type, const void *addr, unsigned long size)
{
extern unsigned long memory_start, memory_end;
unsigned long val = (unsigned long)addr;
return ((val >= memory_start) && ((val + size) < memory_end));

45
include/asm-m68k/bitops.h
View File

@@ -410,8 +410,49 @@ static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#define ext2_find_next_bit(addr, size, off) \
generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == 0UL) {
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (ext2_test_bit(res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for one in first longword */
for (res = bit; res < 32; res++)
if (ext2_test_bit(res, p))
return (p - addr) * 32 + res;
p++;
}
/* No set bit yet, search remaining full bytes for a set bit */
res = ext2_find_first_bit(p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#endif /* __KERNEL__ */

4
include/asm-m68k/bug.h
View File

@@ -7,7 +7,7 @@
#ifndef CONFIG_SUN3
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
asm volatile("illegal"); \
__builtin_trap(); \
} while (0)
#else
#define BUG() do { \
@@ -17,7 +17,7 @@
#endif
#else
#define BUG() do { \
asm volatile("illegal"); \
__builtin_trap(); \
} while (0)
#endif

44
include/asm-m68k/io.h
View File

@@ -91,20 +91,20 @@ extern unsigned long gg2_isa_base;
#undef MULTI_ISA
#endif
#define Q40_ISA (1)
#define GG2_ISA (2)
#define AG_ISA (3)
#define ISA_TYPE_Q40 (1)
#define ISA_TYPE_GG2 (2)
#define ISA_TYPE_AG (3)
#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
#define ISA_TYPE Q40_ISA
#define ISA_TYPE ISA_TYPE_Q40
#define ISA_SEX 0
#endif
#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
#define ISA_TYPE AG_ISA
#define ISA_TYPE ISA_TYPE_AG
#define ISA_SEX 1
#endif
#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
#define ISA_TYPE GG2_ISA
#define ISA_TYPE ISA_TYPE_GG2
#define ISA_SEX 0
#endif
@@ -126,13 +126,13 @@ static inline u8 __iomem *isa_itb(unsigned long addr)
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case Q40_ISA: return (u8 __iomem *)Q40_ISA_IO_B(addr);
case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr);
#endif
#ifdef CONFIG_GG2
case GG2_ISA: return (u8 __iomem *)GG2_ISA_IO_B(addr);
case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_IO_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case AG_ISA: return (u8 __iomem *)AG_ISA_IO_B(addr);
case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
@@ -142,13 +142,13 @@ static inline u16 __iomem *isa_itw(unsigned long addr)
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case Q40_ISA: return (u16 __iomem *)Q40_ISA_IO_W(addr);
case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr);
#endif
#ifdef CONFIG_GG2
case GG2_ISA: return (u16 __iomem *)GG2_ISA_IO_W(addr);
case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_IO_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case AG_ISA: return (u16 __iomem *)AG_ISA_IO_W(addr);
case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
@@ -158,7 +158,7 @@ static inline u32 __iomem *isa_itl(unsigned long addr)
switch(ISA_TYPE)
{
#ifdef CONFIG_AMIGA_PCMCIA
case AG_ISA: return (u32 __iomem *)AG_ISA_IO_W(addr);
case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr);
#endif
default: return 0; /* avoid warnings, just in case */
}
@@ -168,13 +168,13 @@ static inline u8 __iomem *isa_mtb(unsigned long addr)
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case Q40_ISA: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_GG2
case GG2_ISA: return (u8 __iomem *)GG2_ISA_MEM_B(addr);
case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case AG_ISA: return (u8 __iomem *)addr;
case ISA_TYPE_AG: return (u8 __iomem *)addr;
#endif
default: return NULL; /* avoid warnings, just in case */
}
@@ -184,13 +184,13 @@ static inline u16 __iomem *isa_mtw(unsigned long addr)
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case Q40_ISA: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_GG2
case GG2_ISA: return (u16 __iomem *)GG2_ISA_MEM_W(addr);
case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case AG_ISA: return (u16 __iomem *)addr;
case ISA_TYPE_AG: return (u16 __iomem *)addr;
#endif
default: return NULL; /* avoid warnings, just in case */
}
@@ -218,13 +218,13 @@ static inline void isa_delay(void)
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case Q40_ISA: isa_outb(0,0x80); break;
case ISA_TYPE_Q40: isa_outb(0,0x80); break;
#endif
#ifdef CONFIG_GG2
case GG2_ISA: break;
case ISA_TYPE_GG2: break;
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case AG_ISA: break;
case ISA_TYPE_AG: break;
#endif
default: break; /* avoid warnings */
}

2
include/asm-m68k/setup.h
View File

@@ -248,7 +248,7 @@ extern unsigned long m68k_machtype;
#ifndef __ASSEMBLY__
extern unsigned long m68k_cputype;
extern unsigned long m68k_fputype;
extern unsigned long m68k_mmutype; /* Not really used yet */
extern unsigned long m68k_mmutype;
#ifdef CONFIG_VME
extern unsigned long vme_brdtype;
#endif

6
include/asm-m68k/uaccess.h
View File

@@ -14,7 +14,11 @@
#define VERIFY_WRITE 1
/* We let the MMU do all checking */
#define access_ok(type,addr,size) 1
static inline int access_ok(int type, const void __user *addr,
unsigned long size)
{
return 1;
}
/*
* The exception table consists of pairs of addresses: the first is the

14
include/asm-mips/bitops.h
View File

@@ -558,11 +558,13 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
__clear_bit(nr, addr);
}
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
static inline int __ilog2(unsigned long x)
static inline unsigned long __fls(unsigned long x)
{
int lz;
@@ -591,13 +593,6 @@ static inline int __ilog2(unsigned long x)
return 63 - lz;
}
static inline unsigned long __fls(unsigned long x)
{
return __ilog2(x);
}
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
/*
* __ffs - find first bit in word.
* @word: The word to search
@@ -607,7 +602,7 @@ static inline unsigned long __fls(unsigned long x)
*/
static inline unsigned long __ffs(unsigned long word)
{
return __ilog2(word & -word);
return __fls(word & -word);
}
/*
@@ -654,6 +649,7 @@ static inline int ffs(int word)
#else
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/fls64.h>

4
include/asm-mips/compiler.h
View File

@@ -9,10 +9,10 @@
#define _ASM_COMPILER_H
#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
#define GCC_IMM_ASM "n"
#define GCC_IMM_ASM() "n"
#define GCC_REG_ACCUM "$0"
#else
#define GCC_IMM_ASM "rn"
#define GCC_IMM_ASM() "rn"
#define GCC_REG_ACCUM "accum"
#endif

2
include/asm-mips/gic.h
View File

@@ -330,7 +330,7 @@
#define GIC_SH_RMASK_OFS 0x0300
#define GIC_CLR_INTR_MASK(intr, val) \
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS 0x0000

1622
include/asm-mips/mach-au1x00/au1000.h
View File

File diff suppressed because it is too large Load Diff

175
include/asm-mips/mach-au1x00/au1000_dma.h
View File

@@ -1,11 +1,10 @@
/*
* BRIEF MODULE DESCRIPTION
* Defines for using and allocating dma channels on the Alchemy
* Au1000 mips processor.
* Defines for using and allocating DMA channels on the Alchemy
* Au1x00 MIPS processors.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -31,7 +30,7 @@
#ifndef __ASM_AU1000_DMA_H
#define __ASM_AU1000_DMA_H
#include <asm/io.h> /* need byte IO */
#include <linux/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
@@ -50,36 +49,36 @@
#define DMA_DAH_MASK (0x0f << 20)
#define DMA_DID_BIT 16
#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
#define DMA_DS (1<<15)
#define DMA_BE (1<<13)
#define DMA_DR (1<<12)
#define DMA_TS8 (1<<11)
#define DMA_DS (1 << 15)
#define DMA_BE (1 << 13)
#define DMA_DR (1 << 12)
#define DMA_TS8 (1 << 11)
#define DMA_DW_BIT 9
#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
#define DMA_DW8 (0 << DMA_DW_BIT)
#define DMA_DW16 (1 << DMA_DW_BIT)
#define DMA_DW32 (2 << DMA_DW_BIT)
#define DMA_NC (1<<8)
#define DMA_IE (1<<7)
#define DMA_HALT (1<<6)
#define DMA_GO (1<<5)
#define DMA_AB (1<<4)
#define DMA_D1 (1<<3)
#define DMA_BE1 (1<<2)
#define DMA_D0 (1<<1)
#define DMA_BE0 (1<<0)
#define DMA_NC (1 << 8)
#define DMA_IE (1 << 7)
#define DMA_HALT (1 << 6)
#define DMA_GO (1 << 5)
#define DMA_AB (1 << 4)
#define DMA_D1 (1 << 3)
#define DMA_BE1 (1 << 2)
#define DMA_D0 (1 << 1)
#define DMA_BE0 (1 << 0)
#define DMA_PERIPHERAL_ADDR 0x00000008
#define DMA_BUFFER0_START 0x0000000C
#define DMA_BUFFER1_START 0x00000014
#define DMA_BUFFER0_COUNT 0x00000010
#define DMA_BUFFER1_COUNT 0x00000018
#define DMA_BAH_BIT 16
#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
#define DMA_COUNT_BIT 0
#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
#define DMA_PERIPHERAL_ADDR 0x00000008
#define DMA_BUFFER0_START 0x0000000C
#define DMA_BUFFER1_START 0x00000014
#define DMA_BUFFER0_COUNT 0x00000010
#define DMA_BUFFER1_COUNT 0x00000018
#define DMA_BAH_BIT 16
#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
#define DMA_COUNT_BIT 0
#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
/* DMA Device ID's follow */
/* DMA Device IDs follow */
enum {
DMA_ID_UART0_TX = 0,
DMA_ID_UART0_RX,
@@ -110,7 +109,8 @@ enum {
};
struct dma_chan {
int dev_id; // this channel is allocated if >=0, free otherwise
int dev_id; /* this channel is allocated if >= 0, */
/* free otherwise */
unsigned int io;
const char *dev_str;
int irq;
@@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
extern void dump_au1000_dma_channel(unsigned int dmanr);
extern spinlock_t au1000_dma_spin_lock;
static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
{
if (dmanr >= NUM_AU1000_DMA_CHANNELS
|| au1000_dma_table[dmanr].dev_id < 0)
if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
au1000_dma_table[dmanr].dev_id < 0)
return NULL;
return &au1000_dma_table[dmanr];
}
static __inline__ unsigned long claim_dma_lock(void)
static inline unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&au1000_dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
static inline void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
}
@@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags)
/*
* Set the DMA buffer enable bits in the mode register.
*/
static __inline__ void enable_dma_buffer0(unsigned int dmanr)
static inline void enable_dma_buffer0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffer1(unsigned int dmanr)
static inline void enable_dma_buffer1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffers(unsigned int dmanr)
static inline void enable_dma_buffers(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
}
static __inline__ void start_dma(unsigned int dmanr)
static inline void start_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_GO, chan->io + DMA_MODE_SET);
}
#define DMA_HALT_POLL 0x5000
static __inline__ void halt_dma(unsigned int dmanr)
static inline void halt_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
int i;
if (!chan)
return;
au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
// poll the halt bit
/* Poll the halt bit */
for (i = 0; i < DMA_HALT_POLL; i++)
if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
break;
@@ -205,55 +210,57 @@ static __inline__ void halt_dma(unsigned int dmanr)
printk(KERN_INFO "halt_dma: HALT poll expired!\n");
}
static __inline__ void disable_dma(unsigned int dmanr)
static inline void disable_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
halt_dma(dmanr);
// now we can disable the buffers
/* Now we can disable the buffers */
au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
}
static __inline__ int dma_halted(unsigned int dmanr)
static inline int dma_halted(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
}
/* initialize a DMA channel */
static __inline__ void init_dma(unsigned int dmanr)
/* Initialize a DMA channel. */
static inline void init_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
u32 mode;
if (!chan)
return;
disable_dma(dmanr);
// set device FIFO address
au_writel(CPHYSADDR(chan->fifo_addr),
chan->io + DMA_PERIPHERAL_ADDR);
/* Set device FIFO address */
au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
if (chan->irq)
mode |= DMA_IE;
au_writel(~mode, chan->io + DMA_MODE_CLEAR);
au_writel(mode, chan->io + DMA_MODE_SET);
au_writel(mode, chan->io + DMA_MODE_SET);
}
/*
* set mode for a specific DMA channel
* Set mode for a specific DMA channel
*/
static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
/*
@@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
chan->mode |= mode;
}
static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
static inline unsigned int get_dma_mode(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
return chan->mode;
}
static __inline__ int get_dma_active_buffer(unsigned int dmanr)
static inline int get_dma_active_buffer(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
}
/*
* set the device FIFO address for a specific DMA channel - only
* Set the device FIFO address for a specific DMA channel - only
* applicable to GPO4 and GPO5. All the other devices have fixed
* FIFO addresses.
*/
static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
unsigned int a)
static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
if (chan->mode & DMA_DS) /* second bank of device ids */
if (chan->mode & DMA_DS) /* second bank of device IDs */
return;
if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
@@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
/*
* Clear the DMA buffer done bits in the mode register.
*/
static __inline__ void clear_dma_done0(unsigned int dmanr)
static inline void clear_dma_done0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
}
static __inline__ void clear_dma_done1(unsigned int dmanr)
static inline void clear_dma_done1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
@@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr)
/*
* This does nothing - not applicable to Au1000 DMA.
*/
static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
static inline void set_dma_page(unsigned int dmanr, char pagenr)
{
}
/*
* Set Buffer 0 transfer address for specific DMA channel.
*/
static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER0_START);
@@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
/*
* Set Buffer 1 transfer address for specific DMA channel.
*/
static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER1_START);
@@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
/*
* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
*/
static __inline__ void set_dma_count0(unsigned int dmanr,
unsigned int count)
static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr,
/*
* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
*/
static __inline__ void set_dma_count1(unsigned int dmanr,
unsigned int count)
static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr,
/*
* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
*/
static __inline__ void set_dma_count(unsigned int dmanr,
unsigned int count)
static inline void set_dma_count(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -396,35 +409,36 @@ static __inline__ void set_dma_count(unsigned int dmanr,
* Returns which buffer has its done bit set in the mode register.
* Returns -1 if neither or both done bits set.
*/
static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
}
/*
* Returns the DMA channel's Buffer Done IRQ number.
*/
static __inline__ int get_dma_done_irq(unsigned int dmanr)
static inline int get_dma_done_irq(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
return chan->irq;
}
/*
* Get DMA residue count. Returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
static inline int get_dma_residue(unsigned int dmanr)
{
int curBufCntReg, count;
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
@@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
}
#endif /* __ASM_AU1000_DMA_H */

18
include/asm-mips/mach-au1x00/au1000_gpio.h
View File

@@ -2,12 +2,12 @@
* FILE NAME au1000_gpio.h
*
* BRIEF MODULE DESCRIPTION
* API to Alchemy Au1000 GPIO device.
* API to Alchemy Au1xx0 GPIO device.
*
* Author: MontaVista Software, Inc. <source@mvista.com>
* Steve Longerbeam <stevel@mvista.com>
* Steve Longerbeam
*
* Copyright 2001 MontaVista Software Inc.
* Copyright 2001, 2008 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -37,12 +37,12 @@
#define AU1000GPIO_IOC_MAGIC 'A'
#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
#ifdef __KERNEL__
extern u32 get_au1000_avail_gpio_mask(void);

2
include/asm-mips/mach-au1x00/au1550_spi.h
View File

@@ -1,5 +1,5 @@
/*
* au1550_spi.h - au1550 psc spi controller driver - platform data struct
* au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
*/
#ifndef _AU1550_SPI_H_

4
include/asm-mips/mach-au1x00/au1xxx.h
View File

@@ -23,10 +23,10 @@
#ifndef _AU1XXX_H_
#define _AU1XXX_H_
#include <asm/mach-au1x00/au1000.h>
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#include <asm/mach-db1x00/db1x00.h>
#elif defined(CONFIG_MIPS_PB1550)

154
include/asm-mips/mach-au1x00/au1xxx_dbdma.h
View File

@@ -28,17 +28,18 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
* seen in the AU1550 part.
/*
* Specifics for the Au1xxx Descriptor-Based DMA Controller,
* first seen in the AU1550 part.
*/
#ifndef _AU1000_DBDMA_H_
#define _AU1000_DBDMA_H_
#ifndef _LANGUAGE_ASSEMBLY
/* The DMA base addresses.
* The Channels are every 256 bytes (0x0100) from the channel 0 base.
/*
* The DMA base addresses.
* The channels are every 256 bytes (0x0100) from the channel 0 base.
* Interrupt status/enable is bits 15:0 for channels 15 to zero.
*/
#define DDMA_GLOBAL_BASE 0xb4003000
@@ -51,16 +52,14 @@ typedef volatile struct dbdma_global {
u32 ddma_inten;
} dbdma_global_t;
/* General Configuration.
*/
/* General Configuration. */
#define DDMA_CONFIG_AF (1 << 2)
#define DDMA_CONFIG_AH (1 << 1)
#define DDMA_CONFIG_AL (1 << 0)
#define DDMA_THROTTLE_EN (1 << 31)
/* The structure of a DMA Channel.
*/
/* The structure of a DMA Channel. */
typedef volatile struct au1xxx_dma_channel {
u32 ddma_cfg; /* See below */
u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
@@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel {
u32 ddma_irq; /* If bit 0 set, interrupt pending */
u32 ddma_stat; /* See below */
u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
/* Remainder, up to the 256 byte boundary, is reserved.
*/
/* Remainder, up to the 256 byte boundary, is reserved. */
} au1x_dma_chan_t;
#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
@@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel {
#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
#define DDMA_CFG_EN (1 << 0) /* Channel enable */
/* Always set when descriptor processing done, regardless of
/*
* Always set when descriptor processing done, regardless of
* interrupt enable state. Reflected in global intstat, don't
* clear this until global intstat is read/used.
*/
@@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel {
#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
#define DDMA_STAT_H (1 << 0) /* Channel Halted */
/* "Standard" DDMA Descriptor.
/*
* "Standard" DDMA Descriptor.
* Must be 32-byte aligned.
*/
typedef volatile struct au1xxx_ddma_desc {
@@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc {
u32 dscr_dest1; /* See below */
u32 dscr_stat; /* completion status */
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
/* First 32bytes are HW specific!!!
Lets have some SW data following.. make sure its 32bytes
/*
* First 32 bytes are HW specific!!!
* Lets have some SW data following -- make sure it's 32 bytes.
*/
u32 sw_status;
u32 sw_context;
@@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
#define SW_STATUS_INUSE (1<<0)
#define SW_STATUS_INUSE (1 << 0)
/* Command 0 device IDs.
*/
/* Command 0 device IDs. */
#ifdef CONFIG_SOC_AU1550
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
@@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
#define DSCR_NDEV_IDS 32
/* THis macro is used to find/create custom device types */
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
/* This macro is used to find/create custom device types */
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
((d) & 0xFF))
#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
/* Source/Destination transfer width.
*/
/* Source/Destination transfer width. */
#define DSCR_CMD0_BYTE 0
#define DSCR_CMD0_HALFWORD 1
#define DSCR_CMD0_WORD 2
@@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
/* DDMA Descriptor Type.
*/
/* DDMA Descriptor Type. */
#define DSCR_CMD0_STANDARD 0
#define DSCR_CMD0_LITERAL 1
#define DSCR_CMD0_CMP_BRANCH 2
#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
/* Status Instruction.
*/
/* Status Instruction. */
#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
@@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
/* Descriptor Command 1
*/
/* Descriptor Command 1. */
#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
/* Flag description.
*/
/* Flag description. */
#define DSCR_CMD1_FL_MEM_STRIDE0 0
#define DSCR_CMD1_FL_MEM_STRIDE1 1
#define DSCR_CMD1_FL_MEM_STRIDE2 2
#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
/* Source1, 1-dimensional stride.
*/
/* Source1, 1-dimensional stride. */
#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
@@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
/* Dest1, 1-dimensional stride.
*/
/* Dest1, 1-dimensional stride. */
#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
@@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
/* The next descriptor pointer.
*/
/* The next descriptor pointer. */
#define DSCR_NXTPTR_MASK (0x07ffffff)
#define DSCR_NXTPTR(x) ((x) >> 5)
#define DSCR_GET_NXTPTR(x) ((x) << 5)
#define DSCR_NXTPTR_MS (1 << 27)
/* The number of DBDMA channels.
*/
/* The number of DBDMA channels. */
#define NUM_DBDMA_CHANS 16
/*
* Ddma API definitions
* DDMA API definitions
* FIXME: may not fit to this header file
*/
typedef struct dbdma_device_table {
u32 dev_id;
u32 dev_flags;
u32 dev_tsize;
u32 dev_devwidth;
u32 dev_physaddr; /* If FIFO */
u32 dev_intlevel;
u32 dev_intpolarity;
u32 dev_id;
u32 dev_flags;
u32 dev_tsize;
u32 dev_devwidth;
u32 dev_physaddr; /* If FIFO */
u32 dev_intlevel;
u32 dev_intpolarity;
} dbdev_tab_t;
@@ -316,44 +307,41 @@ typedef struct dbdma_chan_config {
au1x_ddma_desc_t *chan_desc_base;
au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
void *chan_callparam;
void (*chan_callback)(int, void *);
void (*chan_callback)(int, void *);
} chan_tab_t;
#define DEV_FLAGS_INUSE (1 << 0)
#define DEV_FLAGS_ANYUSE (1 << 1)
#define DEV_FLAGS_OUT (1 << 2)
#define DEV_FLAGS_IN (1 << 3)
#define DEV_FLAGS_BURSTABLE (1 << 4)
#define DEV_FLAGS_BURSTABLE (1 << 4)
#define DEV_FLAGS_SYNC (1 << 5)
/* end Ddma API definitions */
/* end DDMA API definitions */
/* External functions for drivers to use.
*/
/* Use this to allocate a dbdma channel. The device ids are one of the
* DSCR_CMD0 devices IDs, which is usually redefined to a more
* meaningful name. The 'callback' is called during dma completion
/*
* External functions for drivers to use.
* Use this to allocate a DBDMA channel. The device IDs are one of
* the DSCR_CMD0 devices IDs, which is usually redefined to a more
* meaningful name. The 'callback' is called during DMA completion
* interrupt.
*/
extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
void (*callback)(int, void *), void *callparam);
void (*callback)(int, void *),
void *callparam);
#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
/* Set the device width of a in/out fifo.
*/
/* Set the device width of an in/out FIFO. */
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
/* Allocate a ring of descriptors for dbdma.
*/
/* Allocate a ring of descriptors for DBDMA. */
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
/* Put buffers on source/destination descriptors.
*/
/* Put buffers on source/destination descriptors. */
u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
/* Get a buffer from the destination descriptor.
*/
/* Get a buffer from the destination descriptor. */
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
void au1xxx_dbdma_stop(u32 chanid);
@@ -364,29 +352,35 @@ u32 au1xxx_get_dma_residue(u32 chanid);
void au1xxx_dbdma_chan_free(u32 chanid);
void au1xxx_dbdma_dump(u32 chanid);
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
extern void au1xxx_ddma_del_device(u32 devid);
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
/*
Some compatibilty macros --
Needed to make changes to API without breaking existing drivers
*/
#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
* Some compatibilty macros -- needed to make changes to API
* without breaking existing drivers.
*/
#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
#define put_source_flags(chanid, buf, nbytes, flags) \
au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
#define put_dest_flags(chanid, buf, nbytes, flags) \
au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
/*
* Flags for the put_source/put_dest functions.
*/
#define DDMA_FLAGS_IE (1<<0)
#define DDMA_FLAGS_NOIE (1<<1)
#define DDMA_FLAGS_IE (1 << 0)
#define DDMA_FLAGS_NOIE (1 << 1)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* _AU1000_DBDMA_H_ */

251
include/asm-mips/mach-au1x00/au1xxx_ide.h
View File

@@ -31,167 +31,164 @@
*/
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
#define DMA_WAIT_TIMEOUT 100
#define NUM_DESCRIPTORS PRD_ENTRIES
#define DMA_WAIT_TIMEOUT 100
#define NUM_DESCRIPTORS PRD_ENTRIES
#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
#define NUM_DESCRIPTORS 2
#define NUM_DESCRIPTORS 2
#endif
#ifndef AU1XXX_ATA_RQSIZE
#define AU1XXX_ATA_RQSIZE 128
#define AU1XXX_ATA_RQSIZE 128
#endif
/* Disable Burstable-Support for DBDMA */
#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
#endif
#ifdef CONFIG_PM
/*
* This will enable the device to be powered up when write() or read()
* is called. If this is not defined, the driver will return -EBUSY.
*/
* This will enable the device to be powered up when write() or read()
* is called. If this is not defined, the driver will return -EBUSY.
*/
#define WAKE_ON_ACCESS 1
typedef struct
{
spinlock_t lock; /* Used to block on state transitions */
au1xxx_power_dev_t *dev; /* Power Managers device structure */
unsigned stopped; /* USed to signaling device is stopped */
typedef struct {
spinlock_t lock; /* Used to block on state transitions */
au1xxx_power_dev_t *dev; /* Power Managers device structure */
unsigned stopped; /* Used to signal device is stopped */
} pm_state;
#endif
typedef struct
{
u32 tx_dev_id, rx_dev_id, target_dev_id;
u32 tx_chan, rx_chan;
void *tx_desc_head, *rx_desc_head;
ide_hwif_t *hwif;
typedef struct {
u32 tx_dev_id, rx_dev_id, target_dev_id;
u32 tx_chan, rx_chan;
void *tx_desc_head, *rx_desc_head;
ide_hwif_t *hwif;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
ide_drive_t *drive;
struct dbdma_cmd *dma_table_cpu;
dma_addr_t dma_table_dma;
ide_drive_t *drive;
struct dbdma_cmd *dma_table_cpu;
dma_addr_t dma_table_dma;
#endif
int irq;
u32 regbase;
#ifdef CONFIG_PM
pm_state pm;
pm_state pm;
#endif
} _auide_hwif;
/*******************************************************************************
* PIO Mode timing calculation : *
* *
* Static Bus Spec ATA Spec *
* Tcsoe = t1 *
* Toecs = t9 *
* Twcs = t9 *
* Tcsh = t2i | t2 *
* Tcsoff = t2i | t2 *
* Twp = t2 *
* Tcsw = t1 *
* Tpm = 0 *
* Ta = t1+t2 *
*******************************************************************************/
/******************************************************************************/
/* PIO Mode timing calculation : */
/* */
/* Static Bus Spec ATA Spec */
/* Tcsoe = t1 */
/* Toecs = t9 */
/* Twcs = t9 */
/* Tcsh = t2i | t2 */
/* Tcsoff = t2i | t2 */
/* Twp = t2 */
/* Tcsw = t1 */
/* Tpm = 0 */
/* Ta = t1+t2 */
/******************************************************************************/
#define TCSOE_MASK (0x07<<29)
#define TOECS_MASK (0x07<<26)
#define TWCS_MASK (0x07<<28)
#define TCSH_MASK (0x0F<<24)
#define TCSOFF_MASK (0x07<<20)
#define TWP_MASK (0x3F<<14)
#define TCSW_MASK (0x0F<<10)
#define TPM_MASK (0x0F<<6)
#define TA_MASK (0x3F<<0)
#define TS_MASK (1<<8)
#define TCSOE_MASK (0x07 << 29)
#define TOECS_MASK (0x07 << 26)
#define TWCS_MASK (0x07 << 28)
#define TCSH_MASK (0x0F << 24)
#define TCSOFF_MASK (0x07 << 20)
#define TWP_MASK (0x3F << 14)
#define TCSW_MASK (0x0F << 10)
#define TPM_MASK (0x0F << 6)
#define TA_MASK (0x3F << 0)
#define TS_MASK (1 << 8)
/* Timing parameters PIO mode 0 */
#define SBC_IDE_PIO0_TCSOE (0x04<<29)
#define SBC_IDE_PIO0_TOECS (0x01<<26)
#define SBC_IDE_PIO0_TWCS (0x02<<28)
#define SBC_IDE_PIO0_TCSH (0x08<<24)
#define SBC_IDE_PIO0_TCSOFF (0x07<<20)
#define SBC_IDE_PIO0_TWP (0x10<<14)
#define SBC_IDE_PIO0_TCSW (0x04<<10)
#define SBC_IDE_PIO0_TPM (0x0<<6)
#define SBC_IDE_PIO0_TA (0x15<<0)
#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
#define SBC_IDE_PIO0_TOECS (0x01 << 26)
#define SBC_IDE_PIO0_TWCS (0x02 << 28)
#define SBC_IDE_PIO0_TCSH (0x08 << 24)
#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
#define SBC_IDE_PIO0_TWP (0x10 << 14)
#define SBC_IDE_PIO0_TCSW (0x04 << 10)
#define SBC_IDE_PIO0_TPM (0x00 << 6)
#define SBC_IDE_PIO0_TA (0x15 << 0)
/* Timing parameters PIO mode 1 */
#define SBC_IDE_PIO1_TCSOE (0x03<<29)
#define SBC_IDE_PIO1_TOECS (0x01<<26)
#define SBC_IDE_PIO1_TWCS (0x01<<28)
#define SBC_IDE_PIO1_TCSH (0x06<<24)
#define SBC_IDE_PIO1_TCSOFF (0x06<<20)
#define SBC_IDE_PIO1_TWP (0x08<<14)
#define SBC_IDE_PIO1_TCSW (0x03<<10)
#define SBC_IDE_PIO1_TPM (0x00<<6)
#define SBC_IDE_PIO1_TA (0x0B<<0)
#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
#define SBC_IDE_PIO1_TOECS (0x01 << 26)
#define SBC_IDE_PIO1_TWCS (0x01 << 28)
#define SBC_IDE_PIO1_TCSH (0x06 << 24)
#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
#define SBC_IDE_PIO1_TWP (0x08 << 14)
#define SBC_IDE_PIO1_TCSW (0x03 << 10)
#define SBC_IDE_PIO1_TPM (0x00 << 6)
#define SBC_IDE_PIO1_TA (0x0B << 0)
/* Timing parameters PIO mode 2 */
#define SBC_IDE_PIO2_TCSOE (0x05<<29)
#define SBC_IDE_PIO2_TOECS (0x01<<26)
#define SBC_IDE_PIO2_TWCS (0x01<<28)
#define SBC_IDE_PIO2_TCSH (0x07<<24)
#define SBC_IDE_PIO2_TCSOFF (0x07<<20)
#define SBC_IDE_PIO2_TWP (0x1F<<14)
#define SBC_IDE_PIO2_TCSW (0x05<<10)
#define SBC_IDE_PIO2_TPM (0x00<<6)
#define SBC_IDE_PIO2_TA (0x22<<0)
#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
#define SBC_IDE_PIO2_TOECS (0x01 << 26)
#define SBC_IDE_PIO2_TWCS (0x01 << 28)
#define SBC_IDE_PIO2_TCSH (0x07 << 24)
#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
#define SBC_IDE_PIO2_TWP (0x1F << 14)
#define SBC_IDE_PIO2_TCSW (0x05 << 10)
#define SBC_IDE_PIO2_TPM (0x00 << 6)
#define SBC_IDE_PIO2_TA (0x22 << 0)
/* Timing parameters PIO mode 3 */
#define SBC_IDE_PIO3_TCSOE (0x05<<29)
#define SBC_IDE_PIO3_TOECS (0x01<<26)
#define SBC_IDE_PIO3_TWCS (0x01<<28)
#define SBC_IDE_PIO3_TCSH (0x0D<<24)
#define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
#define SBC_IDE_PIO3_TWP (0x15<<14)
#define SBC_IDE_PIO3_TCSW (0x05<<10)
#define SBC_IDE_PIO3_TPM (0x00<<6)
#define SBC_IDE_PIO3_TA (0x1A<<0)
#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
#define SBC_IDE_PIO3_TOECS (0x01 << 26)
#define SBC_IDE_PIO3_TWCS (0x01 << 28)
#define SBC_IDE_PIO3_TCSH (0x0D << 24)
#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
#define SBC_IDE_PIO3_TWP (0x15 << 14)
#define SBC_IDE_PIO3_TCSW (0x05 << 10)
#define SBC_IDE_PIO3_TPM (0x00 << 6)
#define SBC_IDE_PIO3_TA (0x1A << 0)
/* Timing parameters PIO mode 4 */
#define SBC_IDE_PIO4_TCSOE (0x04<<29)
#define SBC_IDE_PIO4_TOECS (0x01<<26)
#define SBC_IDE_PIO4_TWCS (0x01<<28)
#define SBC_IDE_PIO4_TCSH (0x04<<24)
#define SBC_IDE_PIO4_TCSOFF (0x04<<20)
#define SBC_IDE_PIO4_TWP (0x0D<<14)
#define SBC_IDE_PIO4_TCSW (0x03<<10)
#define SBC_IDE_PIO4_TPM (0x00<<6)
#define SBC_IDE_PIO4_TA (0x12<<0)
#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
#define SBC_IDE_PIO4_TOECS (0x01 << 26)
#define SBC_IDE_PIO4_TWCS (0x01 << 28)
#define SBC_IDE_PIO4_TCSH (0x04 << 24)
#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
#define SBC_IDE_PIO4_TWP (0x0D << 14)
#define SBC_IDE_PIO4_TCSW (0x03 << 10)
#define SBC_IDE_PIO4_TPM (0x00 << 6)
#define SBC_IDE_PIO4_TA (0x12 << 0)
/* Timing parameters MDMA mode 0 */
#define SBC_IDE_MDMA0_TCSOE (0x03<<29)
#define SBC_IDE_MDMA0_TOECS (0x01<<26)
#define SBC_IDE_MDMA0_TWCS (0x01<<28)
#define SBC_IDE_MDMA0_TCSH (0x07<<24)
#define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
#define SBC_IDE_MDMA0_TWP (0x0C<<14)
#define SBC_IDE_MDMA0_TCSW (0x03<<10)
#define SBC_IDE_MDMA0_TPM (0x00<<6)
#define SBC_IDE_MDMA0_TA (0x0F<<0)
#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
#define SBC_IDE_MDMA0_TWP (0x0C << 14)
#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
#define SBC_IDE_MDMA0_TPM (0x00 << 6)
#define SBC_IDE_MDMA0_TA (0x0F << 0)
/* Timing parameters MDMA mode 1 */
#define SBC_IDE_MDMA1_TCSOE (0x05<<29)
#define SBC_IDE_MDMA1_TOECS (0x01<<26)
#define SBC_IDE_MDMA1_TWCS (0x01<<28)
#define SBC_IDE_MDMA1_TCSH (0x05<<24)
#define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
#define SBC_IDE_MDMA1_TWP (0x0F<<14)
#define SBC_IDE_MDMA1_TCSW (0x05<<10)
#define SBC_IDE_MDMA1_TPM (0x00<<6)
#define SBC_IDE_MDMA1_TA (0x15<<0)
#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
#define SBC_IDE_MDMA1_TWP (0x0F << 14)
#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
#define SBC_IDE_MDMA1_TPM (0x00 << 6)
#define SBC_IDE_MDMA1_TA (0x15 << 0)
/* Timing parameters MDMA mode 2 */
#define SBC_IDE_MDMA2_TCSOE (0x04<<29)
#define SBC_IDE_MDMA2_TOECS (0x01<<26)
#define SBC_IDE_MDMA2_TWCS (0x01<<28)
#define SBC_IDE_MDMA2_TCSH (0x04<<24)
#define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
#define SBC_IDE_MDMA2_TWP (0x0D<<14)
#define SBC_IDE_MDMA2_TCSW (0x04<<10)
#define SBC_IDE_MDMA2_TPM (0x00<<6)
#define SBC_IDE_MDMA2_TA (0x12<<0)
#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
#define SBC_IDE_MDMA2_TWP (0x0D << 14)
#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
#define SBC_IDE_MDMA2_TPM (0x00 << 6)
#define SBC_IDE_MDMA2_TA (0x12 << 0)
#define SBC_IDE_TIMING(mode) \
SBC_IDE_##mode##_TWCS | \
SBC_IDE_##mode##_TCSH | \
SBC_IDE_##mode##_TCSOFF | \
SBC_IDE_##mode##_TWP | \
SBC_IDE_##mode##_TCSW | \
SBC_IDE_##mode##_TPM | \
SBC_IDE_##mode##_TA
(SBC_IDE_##mode##_TWCS | \
SBC_IDE_##mode##_TCSH | \
SBC_IDE_##mode##_TCSOFF | \
SBC_IDE_##mode##_TWP | \
SBC_IDE_##mode##_TCSW | \
SBC_IDE_##mode##_TPM | \
SBC_IDE_##mode##_TA)

127
include/asm-mips/mach-au1x00/au1xxx_psc.h
View File

@@ -33,7 +33,6 @@
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
/* The PSC base addresses. */
#ifdef CONFIG_SOC_AU1550
#define PSC0_BASE_ADDR 0xb1a00000
@@ -47,8 +46,8 @@
#define PSC1_BASE_ADDR 0xb1b00000
#endif
/* The PSC select and control registers are common to
* all protocols.
/*
* The PSC select and control registers are common to all protocols.
*/
#define PSC_SEL_OFFSET 0x00000000
#define PSC_CTRL_OFFSET 0x00000004
@@ -59,18 +58,17 @@
#define PSC_SEL_CLK_SERCLK (2 << 4)
#define PSC_SEL_PS_MASK 0x00000007
#define PSC_SEL_PS_DISABLED (0)
#define PSC_SEL_PS_SPIMODE (2)
#define PSC_SEL_PS_I2SMODE (3)
#define PSC_SEL_PS_AC97MODE (4)
#define PSC_SEL_PS_SMBUSMODE (5)
#define PSC_SEL_PS_DISABLED 0
#define PSC_SEL_PS_SPIMODE 2
#define PSC_SEL_PS_I2SMODE 3
#define PSC_SEL_PS_AC97MODE 4
#define PSC_SEL_PS_SMBUSMODE 5
#define PSC_CTRL_DISABLE (0)
#define PSC_CTRL_SUSPEND (2)
#define PSC_CTRL_ENABLE (3)
#define PSC_CTRL_DISABLE 0
#define PSC_CTRL_SUSPEND 2
#define PSC_CTRL_ENABLE 3
/* AC97 Registers.
*/
/* AC97 Registers. */
#define PSC_AC97CFG_OFFSET 0x00000008
#define PSC_AC97MSK_OFFSET 0x0000000c
#define PSC_AC97PCR_OFFSET 0x00000010
@@ -95,8 +93,7 @@
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
/* AC97 Config Register.
*/
/* AC97 Config Register. */
#define PSC_AC97CFG_RT_MASK (3 << 30)
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
@@ -118,20 +115,19 @@
#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
#define PSC_AC97CFG_GE_ENABLE (1)
/* Enable slots 3-12.
*/
/* Enable slots 3-12. */
#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
/*
* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
* The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
* arithmetic in the macro.
*/
#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
/* AC97 Mask Register.
*/
/* AC97 Mask Register. */
#define PSC_AC97MSK_GR (1 << 25)
#define PSC_AC97MSK_CD (1 << 24)
#define PSC_AC97MSK_RR (1 << 13)
@@ -148,8 +144,7 @@
PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
PSC_AC97MSK_RD | PSC_AC97MSK_TD)
/* AC97 Protocol Control Register.
*/
/* AC97 Protocol Control Register. */
#define PSC_AC97PCR_RC (1 << 6)
#define PSC_AC97PCR_RP (1 << 5)
#define PSC_AC97PCR_RS (1 << 4)
@@ -157,8 +152,7 @@
#define PSC_AC97PCR_TP (1 << 1)
#define PSC_AC97PCR_TS (1 << 0)
/* AC97 Status register (read only).
*/
/* AC97 Status register (read only). */
#define PSC_AC97STAT_CB (1 << 26)
#define PSC_AC97STAT_CP (1 << 25)
#define PSC_AC97STAT_CR (1 << 24)
@@ -174,8 +168,7 @@
#define PSC_AC97STAT_DR (1 << 1)
#define PSC_AC97STAT_SR (1 << 0)
/* AC97 Event Register.
*/
/* AC97 Event Register. */
#define PSC_AC97EVNT_GR (1 << 25)
#define PSC_AC97EVNT_CD (1 << 24)
#define PSC_AC97EVNT_RR (1 << 13)
@@ -187,22 +180,18 @@
#define PSC_AC97EVNT_RD (1 << 5)
#define PSC_AC97EVNT_TD (1 << 4)
/* CODEC Command Register.
*/
/* CODEC Command Register. */
#define PSC_AC97CDC_RD (1 << 25)
#define PSC_AC97CDC_ID_MASK (3 << 23)
#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
/* AC97 Reset Control Register.
*/
/* AC97 Reset Control Register. */
#define PSC_AC97RST_RST (1 << 1)
#define PSC_AC97RST_SNC (1 << 0)
/* PSC in I2S Mode.
*/
/* PSC in I2S Mode. */
typedef struct psc_i2s {
u32 psc_sel;
u32 psc_ctrl;
@@ -215,8 +204,7 @@ typedef struct psc_i2s {
u32 psc_i2sudf;
} psc_i2s_t;
/* I2S Config Register.
*/
/* I2S Config Register. */
#define PSC_I2SCFG_RT_MASK (3 << 30)
#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
@@ -247,8 +235,7 @@ typedef struct psc_i2s {
#define PSC_I2SCFG_MLJ (1 << 10)
#define PSC_I2SCFG_XM (1 << 9)
/* The word length equation is simply LEN+1.
*/
/* The word length equation is simply LEN+1. */
#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
@@ -256,8 +243,7 @@ typedef struct psc_i2s {
#define PSC_I2SCFG_MLF (1 << 1)
#define PSC_I2SCFG_MS (1 << 0)
/* I2S Mask Register.
*/
/* I2S Mask Register. */
#define PSC_I2SMSK_RR (1 << 13)
#define PSC_I2SMSK_RO (1 << 12)
#define PSC_I2SMSK_RU (1 << 11)
@@ -271,8 +257,7 @@ typedef struct psc_i2s {
PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
PSC_I2SMSK_RD | PSC_I2SMSK_TD)
/* I2S Protocol Control Register.
*/
/* I2S Protocol Control Register. */
#define PSC_I2SPCR_RC (1 << 6)
#define PSC_I2SPCR_RP (1 << 5)
#define PSC_I2SPCR_RS (1 << 4)
@@ -280,8 +265,7 @@ typedef struct psc_i2s {
#define PSC_I2SPCR_TP (1 << 1)
#define PSC_I2SPCR_TS (1 << 0)
/* I2S Status register (read only).
*/
/* I2S Status register (read only). */
#define PSC_I2SSTAT_RF (1 << 13)
#define PSC_I2SSTAT_RE (1 << 12)
#define PSC_I2SSTAT_RR (1 << 11)
@@ -294,8 +278,7 @@ typedef struct psc_i2s {
#define PSC_I2SSTAT_DR (1 << 1)
#define PSC_I2SSTAT_SR (1 << 0)
/* I2S Event Register.
*/
/* I2S Event Register. */
#define PSC_I2SEVNT_RR (1 << 13)
#define PSC_I2SEVNT_RO (1 << 12)
#define PSC_I2SEVNT_RU (1 << 11)
@@ -305,8 +288,7 @@ typedef struct psc_i2s {
#define PSC_I2SEVNT_RD (1 << 5)
#define PSC_I2SEVNT_TD (1 << 4)
/* PSC in SPI Mode.
*/
/* PSC in SPI Mode. */
typedef struct psc_spi {
u32 psc_sel;
u32 psc_ctrl;
@@ -318,8 +300,7 @@ typedef struct psc_spi {
u32 psc_spitxrx;
} psc_spi_t;
/* SPI Config Register.
*/
/* SPI Config Register. */
#define PSC_SPICFG_RT_MASK (3 << 30)
#define PSC_SPICFG_RT_FIFO1 (0 << 30)
#define PSC_SPICFG_RT_FIFO2 (1 << 30)
@@ -355,8 +336,7 @@ typedef struct psc_spi {
#define PSC_SPICFG_MLF (1 << 1)
#define PSC_SPICFG_MO (1 << 0)
/* SPI Mask Register.
*/
/* SPI Mask Register. */
#define PSC_SPIMSK_MM (1 << 16)
#define PSC_SPIMSK_RR (1 << 13)
#define PSC_SPIMSK_RO (1 << 12)
@@ -371,16 +351,14 @@ typedef struct psc_spi {
PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
PSC_SPIMSK_MD)
/* SPI Protocol Control Register.
*/
/* SPI Protocol Control Register. */
#define PSC_SPIPCR_RC (1 << 6)
#define PSC_SPIPCR_SP (1 << 5)
#define PSC_SPIPCR_SS (1 << 4)
#define PSC_SPIPCR_TC (1 << 2)
#define PSC_SPIPCR_MS (1 << 0)
/* SPI Status register (read only).
*/
/* SPI Status register (read only). */
#define PSC_SPISTAT_RF (1 << 13)
#define PSC_SPISTAT_RE (1 << 12)
#define PSC_SPISTAT_RR (1 << 11)
@@ -393,8 +371,7 @@ typedef struct psc_spi {
#define PSC_SPISTAT_DR (1 << 1)
#define PSC_SPISTAT_SR (1 << 0)
/* SPI Event Register.
*/
/* SPI Event Register. */
#define PSC_SPIEVNT_MM (1 << 16)
#define PSC_SPIEVNT_RR (1 << 13)
#define PSC_SPIEVNT_RO (1 << 12)
@@ -405,13 +382,11 @@ typedef struct psc_spi {
#define PSC_SPIEVNT_SD (1 << 5)
#define PSC_SPIEVNT_MD (1 << 4)
/* Transmit register control.
*/
/* Transmit register control. */
#define PSC_SPITXRX_LC (1 << 29)
#define PSC_SPITXRX_SR (1 << 28)
/* PSC in SMBus (I2C) Mode.
*/
/* PSC in SMBus (I2C) Mode. */
typedef struct psc_smb {
u32 psc_sel;
u32 psc_ctrl;
@@ -424,8 +399,7 @@ typedef struct psc_smb {
u32 psc_smbtmr;
} psc_smb_t;
/* SMBus Config Register.
*/
/* SMBus Config Register. */
#define PSC_SMBCFG_RT_MASK (3 << 30)
#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
@@ -452,8 +426,7 @@ typedef struct psc_smb {
#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
/* SMBus Mask Register.
*/
/* SMBus Mask Register. */
#define PSC_SMBMSK_DN (1 << 30)
#define PSC_SMBMSK_AN (1 << 29)
#define PSC_SMBMSK_AL (1 << 28)
@@ -471,13 +444,11 @@ typedef struct psc_smb {
PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
PSC_SMBMSK_MD)
/* SMBus Protocol Control Register.
*/
/* SMBus Protocol Control Register. */
#define PSC_SMBPCR_DC (1 << 2)
#define PSC_SMBPCR_MS (1 << 0)
/* SMBus Status register (read only).
*/
/* SMBus Status register (read only). */
#define PSC_SMBSTAT_BB (1 << 28)
#define PSC_SMBSTAT_RF (1 << 13)
#define PSC_SMBSTAT_RE (1 << 12)
@@ -491,8 +462,7 @@ typedef struct psc_smb {
#define PSC_SMBSTAT_DR (1 << 1)
#define PSC_SMBSTAT_SR (1 << 0)
/* SMBus Event Register.
*/
/* SMBus Event Register. */
#define PSC_SMBEVNT_DN (1 << 30)
#define PSC_SMBEVNT_AN (1 << 29)
#define PSC_SMBEVNT_AL (1 << 28)
@@ -510,15 +480,13 @@ typedef struct psc_smb {
PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
PSC_SMBEVNT_MD)
/* Transmit register control.
*/
/* Transmit register control. */
#define PSC_SMBTXRX_RSR (1 << 28)
#define PSC_SMBTXRX_STP (1 << 29)
#define PSC_SMBTXRX_DATAMASK (0xff)
#define PSC_SMBTXRX_DATAMASK 0xff
/* SMBus protocol timers register.
*/
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
/* SMBus protocol timers register. */
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
@@ -526,5 +494,4 @@ typedef struct psc_smb {
#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
#endif /* _AU1000_PSC_H_ */

73
include/asm-mips/mach-db1x00/db1200.h
View File

@@ -1,6 +1,6 @@
/*
* AMD Alchemy DB1200 Referrence Board
* Board Registers defines.
* AMD Alchemy DBAu1200 Reference Board
* Board register defines.
*
* ########################################################################
*
@@ -27,26 +27,25 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
// This is defined in au1000.h with bogus value
#undef AU1X00_EXTERNAL_INT
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
/* SPI and SMB are muxed on the Pb1200 board.
Refer to board documentation.
/*
* SPI and SMB are muxed on the DBAu1200 board.
* Refer to board documentation.
*/
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/* AC97 and I2S are muxed on the Pb1200 board.
Refer to board documentation.
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/*
* AC'97 and I2S are muxed on the DBAu1200 board.
* Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
#define BCSR_KSEG1_ADDR 0xB9800000
#define BCSR_KSEG1_ADDR 0xB9800000
typedef volatile struct
{
@@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
@@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
#define BCSR_RESETS_TV 0x0010
/* not resets but in the same register */
#define BCSR_RESETS_PWMR1mUX 0x0800
/* Not resets but in the same register */
#define BCSR_RESETS_PWMR1MUX 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
@@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
#define BCSR_INT_DC 0x0040
#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
@@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x20000000
#define NAND_PHYS_ADDR 0x20000000
/*
* External Interrupts for Pb1200 as of 8/6/2004.
* External Interrupts for DBAu1200 as of 8/6/2004.
* Bit positions in the CPLD registers can be calculated by taking
* the interrupt define and subtracting the DB1200_INT_BEGIN value.
*
@@ -211,23 +210,21 @@ enum external_pb1200_ints {
};
/* For drivers/pcmcia/au1000_db1x00.c */
/* PCMCIA Db1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/*
* DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
*/
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#define BOARD_PC0_INT DB1200_PC0_INT
#define BOARD_PC1_INT DB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
#define BOARD_PC0_INT DB1200_PC0_INT
#define BOARD_PC1_INT DB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
/* Nand chip select */
/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_DB1200_H */

83
include/asm-mips/mach-db1x00/db1x00.h
View File

@@ -1,9 +1,8 @@
/*
* AMD Alchemy DB1x00 Reference Boards
* AMD Alchemy DBAu1x00 Reference Boards
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
*
* ########################################################################
@@ -32,26 +31,26 @@
#ifdef CONFIG_MIPS_DB1550
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define BCSR_KSEG1_ADDR 0xAF000000
#define NAND_PHYS_ADDR 0x20000000
#define BCSR_KSEG1_ADDR 0xAF000000
#define NAND_PHYS_ADDR 0x20000000
#else
#define BCSR_KSEG1_ADDR 0xAE000000
#endif
/*
* Overlay data structure of the Db1x00 board registers.
* Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
* Overlay data structure of the DBAu1x00 board registers.
* Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
*/
typedef volatile struct
{
@@ -138,18 +137,19 @@ typedef volatile struct
#define BCSR_SWRESET_RESET 0x0080
/* PCMCIA Db1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* PCMCIA DBAu1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
/* SD controller macros */
/*
* Detect card.
* SD controller macros
*/
/* Detect card. */
#define mmc_card_inserted(_n_, _res_) \
do { \
BCSR * const bcsr = (BCSR *)0xAE000000; \
@@ -176,10 +176,10 @@ typedef volatile struct
unsigned long mmc_pwr, mmc_wp, board_specific; \
if ((_n_)) { \
mmc_pwr = BCSR_BOARD_SD1_PWR; \
mmc_wp = BCSR_BOARD_SD1_WP; \
mmc_wp = BCSR_BOARD_SD1_WP; \
} else { \
mmc_pwr = BCSR_BOARD_SD0_PWR; \
mmc_wp = BCSR_BOARD_SD0_WP; \
mmc_wp = BCSR_BOARD_SD0_WP; \
} \
board_specific = au_readl((unsigned long)(&bcsr->specific)); \
if (!(board_specific & mmc_wp)) {/* low means card present */ \
@@ -190,17 +190,19 @@ typedef volatile struct
} while (0)
/* NAND defines */
/* Timing values as described in databook, * ns value stripped of
/*
* NAND defines
*
* Timing values as described in databook, * ns value stripped of the
* lower 2 bits.
* These defines are here rather than an SOC1550 generic file because
* These defines are here rather than an Au1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -208,16 +210,15 @@ typedef volatile struct
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
#define NAND_CS 1
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 1
/* should be done by yamon */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
/* Should be done by YAMON */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_DB1X00_H */

181
include/asm-mips/mach-pb1x00/pb1000.h
View File

@@ -1,9 +1,8 @@
/*
* Alchemy Semi PB1000 Referrence Board
* Alchemy Semi Pb1000 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -28,145 +27,61 @@
#define __ASM_PB1000_H
/* PCMCIA PB1000 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
#define PB1000_PCR 0xBE000000
# define PCR_SLOT_0_VPP0 (1<<0)
# define PCR_SLOT_0_VPP1 (1<<1)
# define PCR_SLOT_0_VCC0 (1<<2)
# define PCR_SLOT_0_VCC1 (1<<3)
# define PCR_SLOT_0_RST (1<<4)
#define PB1000_PCR 0xBE000000
# define PCR_SLOT_0_VPP0 (1 << 0)
# define PCR_SLOT_0_VPP1 (1 << 1)
# define PCR_SLOT_0_VCC0 (1 << 2)
# define PCR_SLOT_0_VCC1 (1 << 3)
# define PCR_SLOT_0_RST (1 << 4)
# define PCR_SLOT_1_VPP0 (1 << 8)
# define PCR_SLOT_1_VPP1 (1 << 9)
# define PCR_SLOT_1_VCC0 (1 << 10)
# define PCR_SLOT_1_VCC1 (1 << 11)
# define PCR_SLOT_1_RST (1 << 12)
# define PCR_SLOT_1_VPP0 (1<<8)
# define PCR_SLOT_1_VPP1 (1<<9)
# define PCR_SLOT_1_VCC0 (1<<10)
# define PCR_SLOT_1_VCC1 (1<<11)
# define PCR_SLOT_1_RST (1<<12)
#define PB1000_MDR 0xBE000004
# define MDR_PI (1 << 5) /* PCMCIA int latch */
# define MDR_EPI (1 << 14) /* enable PCMCIA int */
# define MDR_CPI (1 << 15) /* clear PCMCIA int */
#define PB1000_MDR 0xBE000004
# define MDR_PI (1<<5) /* pcmcia int latch */
# define MDR_EPI (1<<14) /* enable pcmcia int */
# define MDR_CPI (1<<15) /* clear pcmcia int */
#define PB1000_ACR1 0xBE000008
# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
# define ACR1_SLOT_0_READY (1 << 2) /* ready */
# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
# define ACR1_SLOT_1_READY (1 << 10) /* ready */
# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
#define PB1000_ACR1 0xBE000008
# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
# define ACR1_SLOT_0_READY (1<<2) /* ready */
# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
# define ACR1_SLOT_1_READY (1<<10) /* ready */
# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
#define CPLD_AUX0 0xBE00000C
#define CPLD_AUX1 0xBE000010
#define CPLD_AUX2 0xBE000014
#define CPLD_AUX0 0xBE00000C
#define CPLD_AUX1 0xBE000010
#define CPLD_AUX2 0xBE000014
/* Voltage levels */
/* VPPEN1 - VPPEN0 */
#define VPP_GND ((0<<1) | (0<<0))
#define VPP_5V ((1<<1) | (0<<0))
#define VPP_3V ((0<<1) | (1<<0))
#define VPP_12V ((0<<1) | (1<<0))
#define VPP_HIZ ((1<<1) | (1<<0))
#define VPP_GND ((0 << 1) | (0 << 0))
#define VPP_5V ((1 << 1) | (0 << 0))
#define VPP_3V ((0 << 1) | (1 << 0))
#define VPP_12V ((0 << 1) | (1 << 0))
#define VPP_HIZ ((1 << 1) | (1 << 0))
/* VCCEN1 - VCCEN0 */
#define VCC_3V ((0<<1) | (1<<0))
#define VCC_5V ((1<<1) | (0<<0))
#define VCC_HIZ ((0<<1) | (0<<0))
#define VCC_3V ((0 << 1) | (1 << 0))
#define VCC_5V ((1 << 1) | (0 << 0))
#define VCC_HIZ ((0 << 1) | (0 << 0))
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
/* PCI PB1000 specific defines */
/* The reason these defines are here instead of au1000.h is because
* the Au1000 does not have a PCI bus controller so the PCI implementation
* on the some of the older Pb1000 boards was very board specific.
*/
#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
#define SDRAM_DEVID 0xBA010000
#define SDRAM_CMD 0xBA010004
#define SDRAM_CLASS 0xBA010008
#define SDRAM_MISC 0xBA01000C
#define SDRAM_MBAR 0xBA010010
#define PCI_IO_DATA_PORT 0xBA800000
#define PCI_IO_ADDR 0xBE00001C
#define PCI_INT_ACK 0xBBC00000
#define PCI_IO_READ 0xBBC00020
#define PCI_IO_WRITE 0xBBC00030
#define PCI_BRIDGE_CONFIG 0xBE000018
#define PCI_IO_START 0x10000000
#define PCI_IO_END 0x1000ffff
#define PCI_MEM_START 0x18000000
#define PCI_MEM_END 0x18ffffff
#define PCI_FIRST_DEVFN 0
#define PCI_LAST_DEVFN 1
static inline u8 au_pci_io_readb(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xff);
}
static inline u16 au_pci_io_readw(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xffff);
}
static inline u32 au_pci_io_readl(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
return readl(PCI_IO_DATA_PORT);
}
static inline void au_pci_io_writeb(u8 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
static inline void au_pci_io_writew(u16 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
static inline void au_pci_io_writel(u32 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
static inline void set_sdram_extbyte(void)
{
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
}
static inline void set_slot_extbyte(void)
{
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
}
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#endif /* __ASM_PB1000_H */

96
include/asm-mips/mach-pb1x00/pb1100.h
View File

@@ -1,9 +1,8 @@
/*
* Alchemy Semi PB1100 Referrence Board
* Alchemy Semi Pb1100 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -27,59 +26,60 @@
#ifndef __ASM_PB1100_H
#define __ASM_PB1100_H
#define PB1100_IDENT 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
# define PB1100_ROM_SEL (1<<15)
# define PB1100_ROM_SIZ (1<<14)
# define PB1100_SWAP_BOOT (1<<13)
# define PB1100_FLASH_WP (1<<12)
# define PB1100_ROM_H_STS (1<<11)
# define PB1100_ROM_L_STS (1<<10)
# define PB1100_FLASH_H_STS (1<<9)
# define PB1100_FLASH_L_STS (1<<8)
# define PB1100_SRAM_SIZ (1<<7)
# define PB1100_TSC_BUSY (1<<6)
# define PB1100_PCMCIA_VS_MASK (3<<4)
# define PB1100_RS232_CD (1<<3)
# define PB1100_RS232_CTS (1<<2)
# define PB1100_RS232_DSR (1<<1)
# define PB1100_RS232_RI (1<<0)
#define PB1100_IDENT 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
# define PB1100_ROM_SEL (1 << 15)
# define PB1100_ROM_SIZ (1 << 14)
# define PB1100_SWAP_BOOT (1 << 13)
# define PB1100_FLASH_WP (1 << 12)
# define PB1100_ROM_H_STS (1 << 11)
# define PB1100_ROM_L_STS (1 << 10)
# define PB1100_FLASH_H_STS (1 << 9)
# define PB1100_FLASH_L_STS (1 << 8)
# define PB1100_SRAM_SIZ (1 << 7)
# define PB1100_TSC_BUSY (1 << 6)
# define PB1100_PCMCIA_VS_MASK (3 << 4)
# define PB1100_RS232_CD (1 << 3)
# define PB1100_RS232_CTS (1 << 2)
# define PB1100_RS232_DSR (1 << 1)
# define PB1100_RS232_RI (1 << 0)
#define PB1100_IRDA_RS232 0xAE00000C
# define PB1100_IRDA_FULL (0<<14) /* full power */
# define PB1100_IRDA_SHUTDOWN (1<<14)
# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
# define PB1100_IRDA_FIR (1<<13)
#define PB1100_IRDA_RS232 0xAE00000C
# define PB1100_IRDA_FULL (0 << 14) /* full power */
# define PB1100_IRDA_SHUTDOWN (1 << 14)
# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
# define PB1100_IRDA_FIR (1 << 13)
#define PCMCIA_BOARD_REG 0xAE000010
# define PB1100_SD_WP1_RO (1<<15) /* read only */
# define PB1100_SD_WP0_RO (1<<14) /* read only */
# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
# define PB1100_SEL_SD_CONN1 (1<<9)
# define PB1100_SEL_SD_CONN0 (1<<8)
# define PC_DEASSERT_RST (1<<7)
# define PC_DRV_EN (1<<4)
#define PCMCIA_BOARD_REG 0xAE000010
# define PB1100_SD_WP1_RO (1 << 15) /* read only */
# define PB1100_SD_WP0_RO (1 << 14) /* read only */
# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
# define PB1100_SEL_SD_CONN1 (1 << 9)
# define PB1100_SEL_SD_CONN0 (1 << 8)
# define PC_DEASSERT_RST (1 << 7)
# define PC_DRV_EN (1 << 4)
#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
#define PB1100_RST_VDDI 0xAE00001C
# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
# define PB1100_VDDI_MASK (0x1F)
#define PB1100_RST_VDDI 0xAE00001C
# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
# define PB1100_VDDI_MASK 0x1F
#define PB1100_LEDS 0xAE000018
#define PB1100_LEDS 0xAE000018
/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
* 7:0 is the LED Display's decimal points.
/*
* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
* 7:0 is the LED Display's decimal points.
*/
#define PB1100_HEX_LED 0xAE000018
#define PB1100_HEX_LED 0xAE000018
/* PCMCIA PB1100 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* PCMCIA Pb1100 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1100_H */

93
include/asm-mips/mach-pb1x00/pb1200.h
View File

@@ -1,5 +1,5 @@
/*
* AMD Alchemy PB1200 Referrence Board
* AMD Alchemy Pb1200 Referrence Board
* Board Registers defines.
*
* ########################################################################
@@ -27,21 +27,20 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
// This is defined in au1000.h with bogus value
#undef AU1X00_EXTERNAL_INT
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
/* SPI and SMB are muxed on the Pb1200 board.
Refer to board documentation.
/*
* SPI and SMB are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/* AC97 and I2S are muxed on the Pb1200 board.
Refer to board documentation.
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/*
* AC97 and I2S are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_SD1WP 0x0800
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_SD1WP 0x0800
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
/* not resets but in the same register */
#define BCSR_RESETS_WSCFSM 0x0800
#define BCSR_RESETS_WSCFSM 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
#define BCSR_RESETS_SD1MUX 0x8000
#define BCSR_RESETS_SD1MUX 0x8000
#define BCSR_PCMCIA_PC0VPP 0x0003
#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
#define BCSR_INT_DC 0x0040
#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_SD1INSERT 0x4000
#define BCSR_INT_SD1EJECT 0x8000
/* PCMCIA Db1x00 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
#define SMC91C111_PHYS_ADDR 0x0D000300
#define SMC91C111_INT PB1200_ETH_INT
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x1C000000
#define NAND_PHYS_ADDR 0x1C000000
/* Timing values as described in databook, * ns value stripped of
/*
* Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an SOC1200 generic file because
* These defines are here rather than an Au1200 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
/*
* External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
PB1200_INT_END = PB1200_INT_BEGIN + 15
};
/* For drivers/pcmcia/au1000_db1x00.c */
#define BOARD_PC0_INT PB1200_PC0_INT
#define BOARD_PC1_INT PB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
/*
* Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
*/
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* Nand chip select */
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#define BOARD_PC0_INT PB1200_PC0_INT
#define BOARD_PC1_INT PB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_PB1200_H */

38
include/asm-mips/mach-pb1x00/pb1500.h
View File

@@ -1,9 +1,8 @@
/*
* Alchemy Semi PB1500 Referrence Board
* Alchemy Semi Pb1500 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -27,25 +26,24 @@
#ifndef __ASM_PB1500_H
#define __ASM_PB1500_H
#define IDENT_BOARD_REG 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
#define PCI_BOARD_REG 0xAE000010
#define PCMCIA_BOARD_REG 0xAE000010
# define PC_DEASSERT_RST 0x80
# define PC_DRV_EN 0x10
#define PB1500_G_CONTROL 0xAE000014
#define PB1500_RST_VDDI 0xAE00001C
#define PB1500_LEDS 0xAE000018
#define IDENT_BOARD_REG 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
#define PCI_BOARD_REG 0xAE000010
#define PCMCIA_BOARD_REG 0xAE000010
#define PC_DEASSERT_RST 0x80
#define PC_DRV_EN 0x10
#define PB1500_G_CONTROL 0xAE000014
#define PB1500_RST_VDDI 0xAE00001C
#define PB1500_LEDS 0xAE000018
#define PB1500_HEX_LED 0xAF000004
#define PB1500_HEX_LED_BLANK 0xAF000008
#define PB1500_HEX_LED 0xAF000004
#define PB1500_HEX_LED_BLANK 0xAF000008
/* PCMCIA PB1500 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
/* PCMCIA Pb1500 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1500_H */

51
include/asm-mips/mach-pb1x00/pb1550.h
View File

@@ -30,15 +30,15 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define BCSR_PHYS_ADDR 0xAF000000
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define BCSR_SYSTEM_POWEROFF 0x4000
#define BCSR_SYSTEM_RESET 0x8000
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define PB1550_USER_ONLY
#endif
/* Timing values as described in databook, * ns value stripped of
/*
* Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an SOC1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 1
/* should be done by yamon */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
/* Should be done by YAMON */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_PB1550_H */

3
include/asm-mips/mipsregs.h
View File

@@ -765,6 +765,9 @@ do { \
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
#define read_c0_random() __read_32bit_c0_register($1, 0)
#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)

3
include/asm-mips/pgtable.h
View File

@@ -239,9 +239,10 @@ static inline pte_t pte_mkdirty(pte_t pte)
static inline pte_t pte_mkyoung(pte_t pte)
{
pte.pte_low |= _PAGE_ACCESSED;
if (pte.pte_low & _PAGE_READ)
if (pte.pte_low & _PAGE_READ) {
pte.pte_low |= _PAGE_SILENT_READ;
pte.pte_high |= _PAGE_SILENT_READ;
}
return pte;
}
#else

6
include/asm-mips/rtlx.h
View File

@@ -3,7 +3,7 @@
*
*/
#ifndef __ASM_RTLX_H
#ifndef __ASM_RTLX_H_
#define __ASM_RTLX_H_
#include <irq.h>
@@ -29,13 +29,13 @@ extern unsigned int rtlx_read_poll(int index, int can_sleep);
extern unsigned int rtlx_write_poll(int index);
enum rtlx_state {
RTLX_STATE_UNUSED,
RTLX_STATE_UNUSED = 0,
RTLX_STATE_INITIALISED,
RTLX_STATE_REMOTE_READY,
RTLX_STATE_OPENED
};
#define RTLX_BUFFER_SIZE 1024
#define RTLX_BUFFER_SIZE 2048
/* each channel supports read and write.
linux (vpe0) reads lx_buffer and writes rt_buffer

2
include/asm-mn10300/ipcbuf.h
View File

@@ -1,4 +1,4 @@
#ifndef _ASM_IPCBUF_H_
#ifndef _ASM_IPCBUF_H
#define _ASM_IPCBUF_H
/*

6
include/asm-parisc/assembly.h
View File

@@ -31,9 +31,8 @@
#define STREGM std,ma
#define SHRREG shrd
#define SHLREG shld
#define ADDIB addib,*
#define CMPB cmpb,*
#define ANDCM andcm,*
#define COND(x) * ## x
#define RP_OFFSET 16
#define FRAME_SIZE 128
#define CALLEE_REG_FRAME_SIZE 144
@@ -46,9 +45,8 @@
#define STREGM stwm
#define SHRREG shr
#define SHLREG shlw
#define ADDIB addib,
#define CMPB cmpb,
#define ANDCM andcm
#define COND(x) x
#define RP_OFFSET 20
#define FRAME_SIZE 64
#define CALLEE_REG_FRAME_SIZE 128

2
include/asm-parisc/checksum.h
View File

@@ -65,7 +65,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
"2:\n"
: "=r" (sum), "=r" (iph), "=r" (ihl)
: "1" (iph), "2" (ihl)
: "r19", "r20", "r21" );
: "r19", "r20", "r21", "memory");
return (__force __sum16)sum;
}

51
include/asm-parisc/ioctl.h
View File

@@ -32,21 +32,6 @@
* NOTE: This limits the max parameter size to 16kB -1 !
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 14
#define _IOC_DIRBITS 2
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
/*
* Direction bits.
*/
@@ -54,40 +39,6 @@
#define _IOC_WRITE 2U
#define _IOC_READ 1U
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
/* provoke compile error for invalid uses of size argument */
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) \
((sizeof(t) == sizeof(t[1]) && \
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
sizeof(t) : __invalid_size_argument_for_IOC)
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
/* used to decode ioctl numbers.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
/* ...and for the drivers/sound files... */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#include <asm-generic/ioctl.h>
#endif /* _ASM_PARISC_IOCTL_H */

4
include/asm-parisc/ioctls.h
View File

@@ -46,6 +46,10 @@
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID _IOR('T', 20, int) /* Return the session ID of FD */
#define TCGETS2 _IOR('T',0x2A, struct termios2)
#define TCSETS2 _IOW('T',0x2B, struct termios2)
#define TCSETSW2 _IOW('T',0x2C, struct termios2)
#define TCSETSF2 _IOW('T',0x2D, struct termios2)
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */

5
include/asm-parisc/termbits.h
View File

@@ -141,6 +141,7 @@ struct ktermios {
#define HUPCL 0002000
#define CLOCAL 0004000
#define CBAUDEX 0010000
#define BOTHER 0010000
#define B57600 0010001
#define B115200 0010002
#define B230400 0010003
@@ -156,10 +157,12 @@ struct ktermios {
#define B3000000 0010015
#define B3500000 0010016
#define B4000000 0010017
#define CIBAUD 002003600000 /* input baud rate (not used) */
#define CIBAUD 002003600000 /* input baud rate */
#define CMSPAR 010000000000 /* mark or space (stick) parity */
#define CRTSCTS 020000000000 /* flow control */
#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
/* c_lflag bits */
#define ISIG 0000001

6
include/asm-parisc/termios.h
View File

@@ -80,8 +80,10 @@ struct termio {
copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
})
#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
#endif /* __KERNEL__ */

12
include/asm-powerpc/io.h
View File

@@ -100,7 +100,7 @@ static inline type name(const volatile type __iomem *addr) \
{ \
type ret; \
__asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \
: "=r" (ret) : "r" (addr), "m" (*addr)); \
: "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
return ret; \
}
@@ -108,8 +108,8 @@ static inline type name(const volatile type __iomem *addr) \
static inline void name(volatile type __iomem *addr, type val) \
{ \
__asm__ __volatile__("sync;" insn \
: "=m" (*addr) : "r" (val), "r" (addr)); \
IO_SET_SYNC_FLAG(); \
: "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
IO_SET_SYNC_FLAG(); \
}
@@ -333,7 +333,8 @@ static inline unsigned int name(unsigned int port) \
" .long 3b,5b\n" \
".previous" \
: "=&r" (x) \
: "r" (port + _IO_BASE)); \
: "r" (port + _IO_BASE) \
: "memory"); \
return x; \
}
@@ -350,7 +351,8 @@ static inline void name(unsigned int val, unsigned int port) \
" .long 0b,2b\n" \
" .long 1b,2b\n" \
".previous" \
: : "r" (val), "r" (port + _IO_BASE)); \
: : "r" (val), "r" (port + _IO_BASE) \
: "memory"); \
}
__do_in_asm(_rec_inb, "lbzx")

1
include/asm-powerpc/kvm_ppc.h
View File

@@ -57,6 +57,7 @@ extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
extern int kvmppc_emulate_instruction(struct kvm_run *run,
struct kvm_vcpu *vcpu);
extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn,
u64 asid, u32 flags);

1
include/asm-powerpc/mmu-hash64.h
View File

@@ -177,6 +177,7 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
extern int mmu_linear_psize;
extern int mmu_virtual_psize;
extern int mmu_vmalloc_psize;
extern int mmu_vmemmap_psize;
extern int mmu_io_psize;
extern int mmu_kernel_ssize;
extern int mmu_highuser_ssize;

3
include/asm-powerpc/mpic.h
View File

@@ -428,12 +428,11 @@ extern void mpic_init(struct mpic *mpic);
*/
/* Change/Read the priority of an interrupt. Default is 8 for irqs and
/* Change the priority of an interrupt. Default is 8 for irqs and
* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
* IPI number is then the offset'ed (linux irq number mapped to the IPI)
*/
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
extern unsigned int mpic_irq_get_priority(unsigned int irq);
/* Setup a non-boot CPU */
extern void mpic_setup_this_cpu(void);

10
include/asm-powerpc/pgtable-ppc64.h
View File

@@ -65,15 +65,15 @@
#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
#define VMEMMAP_REGION_ID (0xfUL)
#define USER_REGION_ID (0UL)
/*
* Defines the address of the vmemap area, in the top 16th of the
* kernel region.
* Defines the address of the vmemap area, in its own region
*/
#define VMEMMAP_BASE (ASM_CONST(CONFIG_KERNEL_START) + \
(0xfUL << (REGION_SHIFT - 4)))
#define vmemmap ((struct page *)VMEMMAP_BASE)
#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
#define vmemmap ((struct page *)VMEMMAP_BASE)
/*
* Common bits in a linux-style PTE. These match the bits in the

4
include/asm-powerpc/uaccess.h
View File

@@ -380,7 +380,7 @@ static inline unsigned long __copy_from_user_inatomic(void *to,
const void __user *from, unsigned long n)
{
if (__builtin_constant_p(n) && (n <= 8)) {
unsigned long ret;
unsigned long ret = 1;
switch (n) {
case 1:
@@ -406,7 +406,7 @@ static inline unsigned long __copy_to_user_inatomic(void __user *to,
const void *from, unsigned long n)
{
if (__builtin_constant_p(n) && (n <= 8)) {
unsigned long ret;
unsigned long ret = 1;
switch (n) {
case 1:

2
include/asm-ppc/system.h
View File

@@ -178,7 +178,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
}
extern inline void * xchg_ptr(void * m, void * val)
static inline void * xchg_ptr(void * m, void * val)
{
return (void *) xchg_u32(m, (unsigned long) val);
}

4
include/asm-s390/debug.h
View File

@@ -120,10 +120,10 @@ debug_entry_t* debug_exception_common(debug_info_t* id, int level,
/* Debug Feature API: */
debug_info_t* debug_register(char* name, int pages, int nr_areas,
debug_info_t *debug_register(const char *name, int pages, int nr_areas,
int buf_size);
debug_info_t *debug_register_mode(char *name, int pages, int nr_areas,
debug_info_t *debug_register_mode(const char *name, int pages, int nr_areas,
int buf_size, mode_t mode, uid_t uid,
gid_t gid);

8
include/asm-s390/system.h
View File

@@ -315,14 +315,14 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
asm volatile( \
" lctlg %1,%2,0(%0)\n" \
: : "a" (&array), "i" (low), "i" (high), \
"m" (*(addrtype *)(array))); \
"m" (*(addrtype *)(&array))); \
})
#define __ctl_store(array, low, high) ({ \
typedef struct { char _[sizeof(array)]; } addrtype; \
asm volatile( \
" stctg %2,%3,0(%1)\n" \
: "=m" (*(addrtype *)(array)) \
: "=m" (*(addrtype *)(&array)) \
: "a" (&array), "i" (low), "i" (high)); \
})
@@ -333,14 +333,14 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
asm volatile( \
" lctl %1,%2,0(%0)\n" \
: : "a" (&array), "i" (low), "i" (high), \
"m" (*(addrtype *)(array))); \
"m" (*(addrtype *)(&array))); \
})
#define __ctl_store(array, low, high) ({ \
typedef struct { char _[sizeof(array)]; } addrtype; \
asm volatile( \
" stctl %2,%3,0(%1)\n" \
: "=m" (*(addrtype *)(array)) \
: "=m" (*(addrtype *)(&array)) \
: "a" (&array), "i" (low), "i" (high)); \
})

10
include/asm-s390/types.h
View File

@@ -10,9 +10,9 @@
#define _S390_TYPES_H
#ifndef __s390x__
# include <asm-generic/int-l64.h>
#else
# include <asm-generic/int-ll64.h>
#else
# include <asm-generic/int-l64.h>
#endif
#ifndef __ASSEMBLY__
@@ -40,7 +40,13 @@ typedef __signed__ long saddr_t;
#ifndef __ASSEMBLY__
typedef u64 dma64_addr_t;
#ifdef __s390x__
/* DMA addresses come in 32-bit and 64-bit flavours. */
typedef u64 dma_addr_t;
#else
typedef u32 dma_addr_t;
#endif
#ifndef __s390x__
typedef union {

2
include/asm-sh/checksum_32.h
View File

@@ -109,7 +109,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
will assume they contain their original values. */
: "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
: "1" (iph), "2" (ihl)
: "t");
: "t", "memory");
return csum_fold(sum);
}

14
include/asm-sh/kgdb.h
View File

@@ -66,18 +66,4 @@ extern int setjmp(jmp_buf __jmpb);
/* Forced breakpoint */
#define breakpoint() __asm__ __volatile__("trapa #0x3c")
/* Taken from sh-stub.c of GDB 4.18 */
static const char hexchars[] = "0123456789abcdef";
/* Get high hex bits */
static inline char highhex(const int x)
{
return hexchars[(x >> 4) & 0xf];
}
/* Get low hex bits */
static inline char lowhex(const int x)
{
return hexchars[x & 0xf];
}
#endif

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