Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-v updates from Palmer Dabbelt: - Support for pointer masking in userspace - Support for probing vector misaligned access performance - Support for qspinlock on systems with Zacas and Zabha * tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits) RISC-V: Remove unnecessary include from compat.h riscv: Fix default misaligned access trap riscv: Add qspinlock support dt-bindings: riscv: Add Ziccrse ISA extension description riscv: Add ISA extension parsing for Ziccrse asm-generic: ticket-lock: Add separate ticket-lock.h asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock riscv: Implement xchg8/16() using Zabha riscv: Implement arch_cmpxchg128() using Zacas riscv: Improve zacas fully-ordered cmpxchg() riscv: Implement cmpxchg8/16() using Zabha dt-bindings: riscv: Add Zabha ISA extension description riscv: Implement cmpxchg32/64() using Zacas riscv: Do not fail to build on byte/halfword operations with Zawrs riscv: Move cpufeature.h macros into their own header KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests riscv: hwprobe: Export the Supm ISA extension riscv: selftests: Add a pointer masking test riscv: Allow ptrace control of the tagged address ABI ...
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@@ -451,6 +451,7 @@ typedef struct elf64_shdr {
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#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
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#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
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#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
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#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */
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#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
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#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
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#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
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@@ -230,7 +230,7 @@ struct prctl_mm_map {
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# define PR_PAC_APDBKEY (1UL << 3)
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# define PR_PAC_APGAKEY (1UL << 4)
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/* Tagged user address controls for arm64 */
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/* Tagged user address controls for arm64 and RISC-V */
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#define PR_SET_TAGGED_ADDR_CTRL 55
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#define PR_GET_TAGGED_ADDR_CTRL 56
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# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
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@@ -244,6 +244,9 @@ struct prctl_mm_map {
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# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
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/* Unused; kept only for source compatibility */
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# define PR_MTE_TCF_SHIFT 1
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/* RISC-V pointer masking tag length */
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# define PR_PMLEN_SHIFT 24
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# define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT)
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/* Control reclaim behavior when allocating memory */
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#define PR_SET_IO_FLUSHER 57
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