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mt6795: 

- add add system timer node
 
 mt7986a:
 - add wifi support
 
 mt8183:
 - add MDP3 and keypad
 
 mt8186:
 - basic support for the Evaluation Board including, i2c, usb and uart.
 
 mt8192:
 - add nodes to support PWM, MIPI transciever, display with GCE and DSI.
 
 mt8195:
 - disable nodes not used on all boards
 - Add support for CPU freq, clocks, power domain controller, spmi, scp.
 - Enable audio decoder, DSP, IOMMU, mailbox.
 - Add display nodes for vdosys0.
 - On Cherry based chromebooks, enable the system companion processor,
   Cross EC, Google Security Chip, secondary MMC controller, trackpad and
   a few regulators.
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Merge tag 'v6.0-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt6795:
- add add system timer node

mt7986a:
- add wifi support

mt8183:
- add MDP3 and keypad

mt8186:
- basic support for the Evaluation Board including, i2c, usb and uart.

mt8192:
- add nodes to support PWM, MIPI transciever, display with GCE and DSI.

mt8195:
- disable nodes not used on all boards
- Add support for CPU freq, clocks, power domain controller, spmi, scp.
- Enable audio decoder, DSP, IOMMU, mailbox.
- Add display nodes for vdosys0.
- On Cherry based chromebooks, enable the system companion processor,
  Cross EC, Google Security Chip, secondary MMC controller, trackpad and
  a few regulators.

* tag 'v6.0-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (34 commits)
  arm64: dts: mediatek: mt6795: Add CPUX system timer node
  arm64: dts: mt7986: add built-in Wi-Fi device nodes
  arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus
  arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpad
  arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller
  arm64: dts: mediatek: cherry: Add keyboard mapping for the top row
  arm64: dts: mediatek: cherry: Add Google Security Chip (GSC) TPM
  arm64: dts: mediatek: cherry: Wire up the ChromeOS Embedded Controller
  arm64: dts: mediatek: cherry: Enable the System Companion Processor
  arm64: dts: mediatek: Fix build warnings of mt8173 vcodec nodes
  arm64: dts: mediatek: Add missing xHCI clocks for mt8192 and mt8195
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mediatek: Add mmsys #reset-cells property for mt8192
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add pwm node
  arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile
  arm64: dts: mt8195: Add display node for vdosys0
  arm64: dts: mt8195: Add gce node
  arm64: dts: mt8195: Add iommu and smi nodes
  ...

Link: https://lore.kernel.org/r/3b915692-c8a9-c508-5a4a-0fdb49355e99@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-09-23 16:19:55 +02:00
parent 9d88bf08e4 5ebb14aa5a
commit 9cc2df424a
14 changed files with 2765 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/mediatek/Makefile
View File

@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb

8
arch/arm64/boot/dts/mediatek/mt6795.dtsi
View File

@ -230,6 +230,14 @@
reg = <0 0x10200620 0 0x20>;
};
systimer: timer@10200670 {
compatible = "mediatek,mt6795-systimer";
reg = <0 0x10200670 0 0x10>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clock-names = "clk13m";
};
gic: interrupt-controller@10221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

38
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
View File

@ -115,6 +115,13 @@
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&pio {
uart1_pins: uart1-pins {
mux {
@ -129,4 +136,35 @@
groups = "uart2";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA";
drive-strength = <4>;
};
};
};

23
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>
/ {
interrupt-parent = <&gic>;
@ -70,6 +71,11 @@
reg = <0 0x43000000 0 0x30000>;
no-map;
};
wmcpu_emi: wmcpu-reserved@4fc00000 {
no-map;
reg = <0 0x4fc00000 0 0x00100000>;
};
};
timer {
@ -261,6 +267,23 @@
#size-cells = <0>;
status = "disabled";
};
wifi: wifi@18000000 {
compatible = "mediatek,mt7986-wmac";
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wmcpu_emi>;
};
};
};

40
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
View File

@ -98,3 +98,43 @@
};
};
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&pio {
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA";
drive-strength = <4>;
};
};
};

3
arch/arm64/boot/dts/mediatek/mt8167.dtsi
View File

@ -36,9 +36,8 @@
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
spm: power-controller {
compatible = "mediatek,mt8167-power-controller";

7
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@ -444,9 +444,8 @@
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
@ -1468,7 +1467,7 @@
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
};
jpegdec: jpegdec@18004000 {
@ -1519,7 +1518,7 @@
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents =
<&topckgen CLK_TOP_VCODECPLL_370P5>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
};
};
};

21
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "mt8183.dtsi"
#include "mt6358.dtsi"
@ -122,6 +123,18 @@
clock-frequency = <100000>;
};
&keyboard {
pinctrl-names = "default";
pinctrl-0 = <&keyboard_pins>;
status = "okay";
linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_VOLUMEDOWN)
MATRIX_KEY(0x01, 0x00, KEY_VOLUMEUP)>;
keypad,num-rows = <2>;
keypad,num-columns = <1>;
debounce-delay-ms = <32>;
mediatek,keys-per-group = <2>;
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
@ -226,6 +239,14 @@
};
};
keyboard_pins: keyboard {
pins_keyboard {
pinmux = <PINMUX_GPIO91__FUNC_KPROW1>,
<PINMUX_GPIO92__FUNC_KPROW0>,
<PINMUX_GPIO93__FUNC_KPCOL0>;
};
};
mmc0_pins_default: mmc0-pins-default {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,

75
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -761,9 +761,8 @@
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
@ -943,6 +942,15 @@
clock-names = "spi", "wrap";
};
keyboard: keyboard@10010000 {
compatible = "mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk26m>;
clock-names = "kpd";
status = "disabled";
};
scp: scp@10500000 {
compatible = "mediatek,mt8183-scp";
reg = <0 0x10500000 0 0x80000>,
@ -1691,6 +1699,60 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
mdp3-rdma0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
};
mdp3-rsz0@14003000 {
compatible = "mediatek,mt8183-mdp3-rsz";
reg = <0 0x14003000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
<CMDQ_EVENT_MDP_RSZ0_EOF>;
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
};
mdp3-rsz1@14004000 {
compatible = "mediatek,mt8183-mdp3-rsz";
reg = <0 0x14004000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
<CMDQ_EVENT_MDP_RSZ1_EOF>;
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
};
mdp3-wrot0@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
};
mdp3-wdma@14006000 {
compatible = "mediatek,mt8183-mdp3-wdma";
reg = <0 0x14006000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
<CMDQ_EVENT_MDP_WDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WDMA0>;
iommus = <&iommu M4U_PORT_MDP_WDMA0>;
};
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
@ -1834,6 +1896,15 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
mdp3-ccorr@1401c000 {
compatible = "mediatek,mt8183-mdp3-ccorr";
reg = <0 0x1401c000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
<CMDQ_EVENT_MDP_CCORR_EOF>;
clocks = <&mmsys CLK_MM_MDP_CCORR>;
};
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;

220
arch/arm64/boot/dts/mediatek/mt8186-evb.dts Normal file
View File

@ -0,0 +1,220 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (C) 2022 MediaTek Inc.
*/
/dts-v1/;
#include "mt8186.dtsi"
/ {
model = "MediaTek MT8186 evaluation board";
compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:921600n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-internal-delay-ns = <8000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-internal-delay-ns = <10000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
};
&i2c5 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
};
&i2c6 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pins>;
};
&i2c8 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_pins>;
};
&i2c9 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c9_pins>;
};
&pio {
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO128__FUNC_SDA0>,
<PINMUX_GPIO127__FUNC_SCL0>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c1_pins: i2c1-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO130__FUNC_SDA1>,
<PINMUX_GPIO129__FUNC_SCL1>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c2_pins: i2c2-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO132__FUNC_SDA2>,
<PINMUX_GPIO131__FUNC_SCL2>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c3_pins: i2c3-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO134__FUNC_SDA3>,
<PINMUX_GPIO133__FUNC_SCL3>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c4_pins: i2c4-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO136__FUNC_SDA4>,
<PINMUX_GPIO135__FUNC_SCL4>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c5_pins: i2c5-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO138__FUNC_SDA5>,
<PINMUX_GPIO137__FUNC_SCL5>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c6_pins: i2c6-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO140__FUNC_SDA6>,
<PINMUX_GPIO139__FUNC_SCL6>;
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c7_pins: i2c7-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO142__FUNC_SDA7>,
<PINMUX_GPIO141__FUNC_SCL7>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c8_pins: i2c8-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO144__FUNC_SDA8>,
<PINMUX_GPIO143__FUNC_SCL8>;
bias-disable;
drive-strength-microamp = <1000>;
input-enable;
};
};
i2c9_pins: i2c9-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO146__FUNC_SDA9>,
<PINMUX_GPIO145__FUNC_SCL9>;
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
drive-strength-microamp = <1000>;
input-enable;
};
};
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&uart0 {
status = "okay";
};

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arch/arm64/boot/dts/mediatek/mt8186.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/clock/mt8186-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8186-pinfunc.h>
#include <dt-bindings/power/mt8186-power.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt8186-resets.h>
/ {
compatible = "mediatek,mt8186";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
};
cluster1 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2050000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2050000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
idle-states {
entry-method = "psci";
cpu_off_l: cpu-off-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <1600>;
};
cpu_off_b: cpu-off-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <1400>;
};
cluster_off_l: cluster-off-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010001>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <250>;
min-residency-us = <2100>;
};
cluster_off_b: cluster-off-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010001>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <250>;
min-residency-us = <1900>;
};
};
l2_0: l2-cache0 {
compatible = "cache";
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
};
};
clk13m: oscillator-13m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
clock-output-names = "clk13m";
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>,
<0 0x0c040000 0 0x200000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu6 &cpu7>;
};
};
};
mcusys: syscon@c53a000 {
compatible = "mediatek,mt8186-mcusys", "syscon";
reg = <0 0xc53a000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8186-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8186-infracfg_ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8186-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt8186-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x0200>,
<0 0x10002200 0 0x0200>,
<0 0x10002400 0 0x0200>,
<0 0x10002600 0 0x0200>,
<0 0x10002a00 0 0x0200>,
<0 0x10002c00 0 0x0200>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
"iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 185>;
interrupt-controller;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8186-wdt",
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x1000>;
#reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8186-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8186-pwrap", "syscon";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
clock-names = "spi", "wrap";
};
systimer: timer@10017000 {
compatible = "mediatek,mt8186-timer",
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk13m>;
};
scp: scp@10500000 {
compatible = "mediatek,mt8186-scp";
reg = <0 0x10500000 0 0x40000>,
<0 0x105c0000 0 0x19080>;
reg-names = "sram", "cfg";
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
};
nor_flash: spi@11000000 {
compatible = "mediatek,mt8186-nor";
reg = <0 0x11000000 0 0x1000>;
clocks = <&topckgen CLK_TOP_SPINOR>,
<&infracfg_ao CLK_INFRA_AO_SPINOR>,
<&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
<&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
clock-names = "spi", "sf", "axi", "axi_s";
assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
auxadc: adc@11001000 {
compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
reg = <0 0x11001000 0 0x1000>;
#io-channel-cells = <1>;
clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
clock-names = "main";
};
uart0: serial@11002000 {
compatible = "mediatek,mt8186-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt8186-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11007000 0 0x1000>,
<0 0x10200100 0 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11008000 0 0x1000>,
<0 0x10200200 0 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11009000 0 0x1000>,
<0 0x10200300 0 0x180>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x1100f000 0 0x1000>,
<0 0x10200480 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@11011000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11011000 0 0x1000>,
<0 0x10200580 0 0x180>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@11016000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11016000 0 0x1000>,
<0 0x10200700 0 0x100>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@1100d000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x1100d000 0 0x1000>,
<0 0x10200800 0 0x100>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@11004000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11004000 0 0x1000>,
<0 0x10200900 0 0x180>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@11005000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11005000 0 0x1000>,
<0 0x10200A80 0 0x180>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
#pwm-cells = <2>;
clocks = <&topckgen CLK_TOP_DISP_PWM>,
<&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
clock-names = "main", "mm";
status = "disabled";
};
spi1: spi@11010000 {
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi2: spi@11012000 {
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi3: spi@11013000 {
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi4: spi@11014000 {
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11014000 0 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi5: spi@11015000 {
compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11015000 0 0x1000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
imp_iic_wrap: clock-controller@11017000 {
compatible = "mediatek,mt8186-imp_iic_wrap";
reg = <0 0x11017000 0 0x1000>;
#clock-cells = <1>;
};
uart2: serial@11018000 {
compatible = "mediatek,mt8186-uart",
"mediatek,mt6577-uart";
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c9: i2c@11019000 {
compatible = "mediatek,mt8186-i2c";
reg = <0 0x11019000 0 0x1000>,
<0 0x10200c00 0 0x180>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
<&infracfg_ao CLK_INFRA_AO_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11cd0000 0 0x1000>;
clocks = <&topckgen CLK_TOP_MSDC50_0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
clock-names = "source", "hclk", "source_cg";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11c90000 0 0x1000>;
clocks = <&topckgen CLK_TOP_MSDC30_1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
status = "disabled";
};
u3phy0: t-phy@11c80000 {
compatible = "mediatek,mt8186-tphy",
"mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x11c80000 0x1000>;
status = "disabled";
u2port1: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
};
u3port1: usb-phy@700 {
reg = <0x700 0x900>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
};
};
u3phy1: t-phy@11ca0000 {
compatible = "mediatek,mt8186-tphy",
"mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x11ca0000 0x1000>;
status = "disabled";
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,discth = <0x8>;
};
};
efuse: efuse@11cb0000 {
compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
reg = <0 0x11cb0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
mipi_tx0: dsi-phy@11cc0000 {
compatible = "mediatek,mt8183-mipi-tx";
reg = <0 0x11cc0000 0 0x1000>;
clocks = <&clk26m>;
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "mipi_tx0_pll";
status = "disabled";
};
mfgsys: clock-controller@13000000 {
compatible = "mediatek,mt8186-mfgsys";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8186-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wpesys: clock-controller@14020000 {
compatible = "mediatek,mt8186-wpesys";
reg = <0 0x14020000 0 0x1000>;
#clock-cells = <1>;
};
imgsys1: clock-controller@15020000 {
compatible = "mediatek,mt8186-imgsys1";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8186-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8186-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
#clock-cells = <1>;
};
vencsys: clock-controller@17000000 {
compatible = "mediatek,mt8186-vencsys";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8186-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8186-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawb: clock-controller@1a06f000 {
compatible = "mediatek,mt8186-camsys_rawb";
reg = <0 0x1a06f000 0 0x1000>;
#clock-cells = <1>;
};
mdpsys: clock-controller@1b000000 {
compatible = "mediatek,mt8186-mdpsys";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
ipesys: clock-controller@1c000000 {
compatible = "mediatek,mt8186-ipesys";
reg = <0 0x1c000000 0 0x1000>;
#clock-cells = <1>;
};
};
};

200
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -6,12 +6,14 @@
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
/ {
compatible = "mediatek,mt8192";
@ -19,6 +21,14 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
ovl0 = &ovl0;
ovl-2l0 = &ovl_2l0;
ovl-2l2 = &ovl_2l2;
rdma0 = &rdma0;
rdma4 = &rdma4;
};
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -306,9 +316,8 @@
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
@ -553,6 +562,15 @@
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
gce: mailbox@10228000 {
compatible = "mediatek,mt8192-gce";
reg = <0 0x10228000 0 0x4000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <2>;
clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce";
};
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
@ -599,6 +617,17 @@
status = "disabled";
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
#pwm-cells = <2>;
clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
<&infracfg CLK_INFRA_DISP_PWM>;
clock-names = "main", "mm";
status = "disabled";
};
spi1: spi@11010000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@ -724,9 +753,12 @@
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
<&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&infracfg CLK_INFRA_SSUSB>,
<&infracfg CLK_INFRA_SSUSB_XHCI>,
<&apmixedsys CLK_APMIXED_USBPLL>;
clock-names = "sys_ck", "xhci_ck", "ref_ck";
<&apmixedsys CLK_APMIXED_USBPLL>,
<&clk26m>,
<&clk26m>,
<&infracfg CLK_INFRA_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
"xhci_ck";
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x420 102>;
status = "disabled";
@ -1084,6 +1116,16 @@
};
};
mipi_tx0: dsi-phy@11e50000 {
compatible = "mediatek,mt8183-mipi-tx";
reg = <0 0x11e50000 0 0x1000>;
clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "mipi_tx0_pll";
status = "disabled";
};
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@ -1166,6 +1208,20 @@
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
mutex: mutex@14001000 {
compatible = "mediatek,mt8192-disp-mutex";
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
smi_common: smi@14002000 {
@ -1199,6 +1255,140 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
ovl0: ovl@14005000 {
compatible = "mediatek,mt8192-disp-ovl";
reg = <0 0x14005000 0 0x1000>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
};
ovl_2l0: ovl@14006000 {
compatible = "mediatek,mt8192-disp-ovl-2l";
reg = <0 0x14006000 0 0x1000>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
};
rdma0: rdma@14007000 {
compatible = "mediatek,mt8192-disp-rdma",
"mediatek,mt8183-disp-rdma";
reg = <0 0x14007000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
mediatek,rdma-fifo-size = <5120>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
};
color0: color@14009000 {
compatible = "mediatek,mt8192-disp-color",
"mediatek,mt8173-disp-color";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ccorr0: ccorr@1400a000 {
compatible = "mediatek,mt8192-disp-ccorr";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
aal0: aal@1400b000 {
compatible = "mediatek,mt8192-disp-aal",
"mediatek,mt8183-disp-aal";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
gamma0: gamma@1400c000 {
compatible = "mediatek,mt8192-disp-gamma",
"mediatek,mt8183-disp-gamma";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
postmask0: postmask@1400d000 {
compatible = "mediatek,mt8192-disp-postmask";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
dither0: dither@1400e000 {
compatible = "mediatek,mt8192-disp-dither",
"mediatek,mt8183-disp-dither";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
dsi0: dsi@14010000 {
compatible = "mediatek,mt8183-dsi";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DSI0>,
<&mmsys CLK_MM_DSI_DSI0>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx0>;
phy-names = "dphy";
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
status = "disabled";
port {
dsi_out: endpoint { };
};
};
ovl_2l2: ovl@14014000 {
compatible = "mediatek,mt8192-disp-ovl-2l";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
};
rdma4: rdma@14015000 {
compatible = "mediatek,mt8192-disp-rdma",
"mediatek,mt8183-disp-rdma";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA4>;
iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
dpi0: dpi@14016000 {
compatible = "mediatek,mt8192-dpi";
reg = <0 0x14016000 0 0x1000>;

256
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>
#include "mt8195.dtsi"
#include "mt6359.dtsi"
@ -17,6 +18,7 @@
i2c5 = &i2c5;
i2c7 = &i2c7;
mmc0 = &mmc0;
mmc1 = &mmc1;
serial0 = &uart0;
};
@ -104,6 +106,18 @@
enable-active-high;
regulator-always-on;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
};
&i2c0 {
@ -121,6 +135,16 @@
i2c-scl-internal-delay-ns = <12500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
vcc-supply = <&pp3300_s3>;
wakeup-source;
};
};
&i2c2 {
@ -137,6 +161,14 @@
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
tpm@50 {
compatible = "google,cr50";
reg = <0x50>;
interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&cr50_int>;
};
};
&i2c4 {
@ -207,6 +239,24 @@
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
};
&mmc1 {
status = "okay";
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
max-frequency = <200000000>;
no-mmc;
no-sdio;
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>;
pinctrl-1 = <&mmc1_pins_default>;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
};
/* for CPU-L */
&mt6359_vcore_buck_reg {
regulator-always-on;
@ -414,6 +464,21 @@
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_MISO";
cr50_int: cr50-irq-default-pins {
pins-gsc-ap-int-odl {
pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
input-enable;
};
};
cros_ec_int: cros-ec-irq-default-pins {
pins-ec-ap-int-odl {
pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
input-enable;
};
};
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
@ -540,6 +605,32 @@
};
};
mmc1_pins_detect: mmc1-detect-pins {
pins-insert {
pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
bias-pull-up;
};
};
mmc1_pins_default: mmc1-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
nor_pins_default: nor-default-pins {
pins-ck-io {
pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
@ -600,6 +691,14 @@
};
};
scp_pins: scp-default-pins {
pins-vreq {
pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
bias-disable;
input-enable;
};
};
spi0_pins: spi0-default-pins {
pins-cs-mosi-clk {
pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
@ -622,6 +721,14 @@
};
};
trackpad_pins: trackpad-default-pins {
pins-int-n {
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
input-enable;
bias-pull-up;
};
};
touchscreen_pins: touchscreen-default-pins {
pins-int-n {
pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
@ -643,12 +750,128 @@
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&scp {
status = "okay";
firmware-name = "mediatek/mt8195/scp.img";
memory-region = <&scp_mem>;
pinctrl-names = "default";
pinctrl-0 = <&scp_pins>;
cros-ec-rpmsg {
compatible = "google,cros-ec-rpmsg";
mediatek,rpmsg-name = "cros-ec-rpmsg";
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
mediatek,pad-select = <0>;
cros_ec: ec@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "google,cros-ec-spi";
reg = <0>;
interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cros_ec_int>;
spi-max-frequency = <3000000>;
keyboard-backlight {
compatible = "google,cros-kbd-led-backlight";
};
i2c_tunnel: i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
google,remote-bus = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
mt_pmic_vmc_ldo_reg: regulator@0 {
compatible = "google,cros-ec-regulator";
reg = <0>;
regulator-name = "mt_pmic_vmc_ldo";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
};
mt_pmic_vmch_ldo_reg: regulator@1 {
compatible = "google,cros-ec-regulator";
reg = <1>;
regulator-name = "mt_pmic_vmch_ldo";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
};
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
#size-cells = <0>;
usb_c0: connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "host";
try-power-role = "source";
};
usb_c1: connector@1 {
compatible = "usb-c-connector";
reg = <1>;
power-role = "dual";
data-role = "host";
try-power-role = "source";
};
};
};
};
&spmi {
#address-cells = <2>;
#size-cells = <0>;
mt6315@6 {
compatible = "mediatek,mt6315-regulator";
reg = <0x6 SPMI_USID>;
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
};
};
mt6315@7 {
compatible = "mediatek,mt6315-regulator";
reg = <0x7 SPMI_USID>;
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <625000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
};
};
};
&u3phy0 {
@ -700,3 +923,36 @@
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
#include <arm/cros-ec-keyboard.dtsi>
#include <arm/cros-ec-sbs.dtsi>
&keyboard_controller {
function-row-physmap = <
MATRIX_KEY(0x00, 0x02, 0) /* T1 */
MATRIX_KEY(0x03, 0x02, 0) /* T2 */
MATRIX_KEY(0x02, 0x02, 0) /* T3 */
MATRIX_KEY(0x01, 0x02, 0) /* T4 */
MATRIX_KEY(0x03, 0x04, 0) /* T5 */
MATRIX_KEY(0x02, 0x04, 0) /* T6 */
MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
>;
linux,keymap = <
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
MATRIX_KEY(0x01, 0x02, KEY_SCALE)
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_MUTE)
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
CROS_STD_MAIN_KEYMAP
>;
};

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arch/arm64/boot/dts/mediatek/mt8195.dtsi
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