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Merge branch 'linus' into core/printk

Browse Source 
Conflicts:

	kernel/printk.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
2008-07-10 08:17:14 +02:00
parent e17ba73b0e 6329d3021b
commit 9e4144abf8
1450 changed files with 33805 additions and 14614 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/acpi/processor.h
View File

@@ -319,6 +319,7 @@ static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr)
#endif /* CONFIG_CPU_FREQ */
/* in processor_throttling.c */
int acpi_processor_tstate_has_changed(struct acpi_processor *pr);
int acpi_processor_get_throttling_info(struct acpi_processor *pr);
extern int acpi_processor_set_throttling(struct acpi_processor *pr, int state);
extern struct file_operations acpi_processor_throttling_fops;

2
include/asm-alpha/core_mcpcia.h
View File

@@ -261,7 +261,7 @@ struct el_MCPCIA_uncorrected_frame_mcheck {
}
#endif
static inline int __mcpcia_is_mmio(unsigned long addr)
extern inline int __mcpcia_is_mmio(unsigned long addr)
{
return (addr & 0x80000000UL) == 0;
}

14
include/asm-alpha/core_t2.h
View File

@@ -356,13 +356,13 @@ struct el_t2_frame_corrected {
#define vip volatile int *
#define vuip volatile unsigned int *
static inline u8 t2_inb(unsigned long addr)
extern inline u8 t2_inb(unsigned long addr)
{
long result = *(vip) ((addr << 5) + T2_IO + 0x00);
return __kernel_extbl(result, addr & 3);
}
static inline void t2_outb(u8 b, unsigned long addr)
extern inline void t2_outb(u8 b, unsigned long addr)
{
unsigned long w;
@@ -371,13 +371,13 @@ static inline void t2_outb(u8 b, unsigned long addr)
mb();
}
static inline u16 t2_inw(unsigned long addr)
extern inline u16 t2_inw(unsigned long addr)
{
long result = *(vip) ((addr << 5) + T2_IO + 0x08);
return __kernel_extwl(result, addr & 3);
}
static inline void t2_outw(u16 b, unsigned long addr)
extern inline void t2_outw(u16 b, unsigned long addr)
{
unsigned long w;
@@ -386,12 +386,12 @@ static inline void t2_outw(u16 b, unsigned long addr)
mb();
}
static inline u32 t2_inl(unsigned long addr)
extern inline u32 t2_inl(unsigned long addr)
{
return *(vuip) ((addr << 5) + T2_IO + 0x18);
}
static inline void t2_outl(u32 b, unsigned long addr)
extern inline void t2_outl(u32 b, unsigned long addr)
{
*(vuip) ((addr << 5) + T2_IO + 0x18) = b;
mb();
@@ -435,7 +435,7 @@ static inline void t2_outl(u32 b, unsigned long addr)
set_hae(msb); \
}
static DEFINE_SPINLOCK(t2_hae_lock);
extern spinlock_t t2_hae_lock;
/*
* NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since

6
include/asm-alpha/io.h
View File

@@ -35,7 +35,7 @@
* register not being up-to-date with respect to the hardware
* value.
*/
static inline void __set_hae(unsigned long new_hae)
extern inline void __set_hae(unsigned long new_hae)
{
unsigned long flags;
local_irq_save(flags);
@@ -49,7 +49,7 @@ static inline void __set_hae(unsigned long new_hae)
local_irq_restore(flags);
}
static inline void set_hae(unsigned long new_hae)
extern inline void set_hae(unsigned long new_hae)
{
if (new_hae != alpha_mv.hae_cache)
__set_hae(new_hae);
@@ -176,7 +176,7 @@ REMAP2(u64, writeq, volatile)
#undef REMAP1
#undef REMAP2
static inline void __iomem *generic_ioportmap(unsigned long a)
extern inline void __iomem *generic_ioportmap(unsigned long a)
{
return alpha_mv.mv_ioportmap(a);
}

6
include/asm-alpha/mmu_context.h
View File

@@ -23,7 +23,7 @@
#endif
extern inline unsigned long
static inline unsigned long
__reload_thread(struct pcb_struct *pcb)
{
register unsigned long a0 __asm__("$16");
@@ -114,7 +114,7 @@ extern unsigned long last_asn;
#define __MMU_EXTERN_INLINE
#endif
static inline unsigned long
extern inline unsigned long
__get_new_mm_context(struct mm_struct *mm, long cpu)
{
unsigned long asn = cpu_last_asn(cpu);
@@ -226,7 +226,7 @@ ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
# endif
#endif
extern inline int
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
int i;

74
include/asm-alpha/percpu.h
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@@ -1,6 +1,78 @@
#ifndef __ALPHA_PERCPU_H
#define __ALPHA_PERCPU_H
#include <linux/compiler.h>
#include <linux/threads.h>
#include <asm-generic/percpu.h>
/*
* Determine the real variable name from the name visible in the
* kernel sources.
*/
#define per_cpu_var(var) per_cpu__##var
#ifdef CONFIG_SMP
/*
* per_cpu_offset() is the offset that has to be added to a
* percpu variable to get to the instance for a certain processor.
*/
extern unsigned long __per_cpu_offset[NR_CPUS];
#define per_cpu_offset(x) (__per_cpu_offset[x])
#define __my_cpu_offset per_cpu_offset(raw_smp_processor_id())
#ifdef CONFIG_DEBUG_PREEMPT
#define my_cpu_offset per_cpu_offset(smp_processor_id())
#else
#define my_cpu_offset __my_cpu_offset
#endif
#ifndef MODULE
#define SHIFT_PERCPU_PTR(var, offset) RELOC_HIDE(&per_cpu_var(var), (offset))
#define PER_CPU_ATTRIBUTES
#else
/*
* To calculate addresses of locally defined variables, GCC uses 32-bit
* displacement from the GP. Which doesn't work for per cpu variables in
* modules, as an offset to the kernel per cpu area is way above 4G.
*
* This forces allocation of a GOT entry for per cpu variable using
* ldq instruction with a 'literal' relocation.
*/
#define SHIFT_PERCPU_PTR(var, offset) ({ \
extern int simple_identifier_##var(void); \
unsigned long __ptr, tmp_gp; \
asm ( "br %1, 1f \n\
1: ldgp %1, 0(%1) \n\
ldq %0, per_cpu__" #var"(%1)\t!literal" \
: "=&r"(__ptr), "=&r"(tmp_gp)); \
(typeof(&per_cpu_var(var)))(__ptr + (offset)); })
#define PER_CPU_ATTRIBUTES __used
#endif /* MODULE */
/*
* A percpu variable may point to a discarded regions. The following are
* established ways to produce a usable pointer from the percpu variable
* offset.
*/
#define per_cpu(var, cpu) \
(*SHIFT_PERCPU_PTR(var, per_cpu_offset(cpu)))
#define __get_cpu_var(var) \
(*SHIFT_PERCPU_PTR(var, my_cpu_offset))
#define __raw_get_cpu_var(var) \
(*SHIFT_PERCPU_PTR(var, __my_cpu_offset))
#else /* ! SMP */
#define per_cpu(var, cpu) (*((void)(cpu), &per_cpu_var(var)))
#define __get_cpu_var(var) per_cpu_var(var)
#define __raw_get_cpu_var(var) per_cpu_var(var)
#define PER_CPU_ATTRIBUTES
#endif /* SMP */
#define DECLARE_PER_CPU(type, name) extern __typeof__(type) per_cpu_var(name)
#endif /* __ALPHA_PERCPU_H */

10
include/asm-alpha/system.h
View File

@@ -184,7 +184,7 @@ enum amask_enum {
__amask; })
#define __CALL_PAL_R0(NAME, TYPE) \
static inline TYPE NAME(void) \
extern inline TYPE NAME(void) \
{ \
register TYPE __r0 __asm__("$0"); \
__asm__ __volatile__( \
@@ -196,7 +196,7 @@ static inline TYPE NAME(void) \
}
#define __CALL_PAL_W1(NAME, TYPE0) \
static inline void NAME(TYPE0 arg0) \
extern inline void NAME(TYPE0 arg0) \
{ \
register TYPE0 __r16 __asm__("$16") = arg0; \
__asm__ __volatile__( \
@@ -207,7 +207,7 @@ static inline void NAME(TYPE0 arg0) \
}
#define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \
static inline void NAME(TYPE0 arg0, TYPE1 arg1) \
extern inline void NAME(TYPE0 arg0, TYPE1 arg1) \
{ \
register TYPE0 __r16 __asm__("$16") = arg0; \
register TYPE1 __r17 __asm__("$17") = arg1; \
@@ -219,7 +219,7 @@ static inline void NAME(TYPE0 arg0, TYPE1 arg1) \
}
#define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \
static inline RTYPE NAME(TYPE0 arg0) \
extern inline RTYPE NAME(TYPE0 arg0) \
{ \
register RTYPE __r0 __asm__("$0"); \
register TYPE0 __r16 __asm__("$16") = arg0; \
@@ -232,7 +232,7 @@ static inline RTYPE NAME(TYPE0 arg0) \
}
#define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \
static inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
extern inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
{ \
register RTYPE __r0 __asm__("$0"); \
register TYPE0 __r16 __asm__("$16") = arg0; \

6
include/asm-alpha/vga.h
View File

@@ -13,7 +13,7 @@
#define VT_BUF_HAVE_MEMSETW
#define VT_BUF_HAVE_MEMCPYW
extern inline void scr_writew(u16 val, volatile u16 *addr)
static inline void scr_writew(u16 val, volatile u16 *addr)
{
if (__is_ioaddr(addr))
__raw_writew(val, (volatile u16 __iomem *) addr);
@@ -21,7 +21,7 @@ extern inline void scr_writew(u16 val, volatile u16 *addr)
*addr = val;
}
extern inline u16 scr_readw(volatile const u16 *addr)
static inline u16 scr_readw(volatile const u16 *addr)
{
if (__is_ioaddr(addr))
return __raw_readw((volatile const u16 __iomem *) addr);
@@ -29,7 +29,7 @@ extern inline u16 scr_readw(volatile const u16 *addr)
return *addr;
}
extern inline void scr_memsetw(u16 *s, u16 c, unsigned int count)
static inline void scr_memsetw(u16 *s, u16 c, unsigned int count)
{
if (__is_ioaddr(s))
memsetw_io((u16 __iomem *) s, c, count);

2
include/asm-arm/arch-at91/io.h
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@@ -21,8 +21,6 @@
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/io.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) ((void __iomem *)(a))

2
include/asm-arm/arch-omap/board-palmte.h
View File

@@ -14,8 +14,6 @@
#ifndef __OMAP_BOARD_PALMTE_H
#define __OMAP_BOARD_PALMTE_H
#include <asm/arch/gpio.h>
#define PALMTE_USBDETECT_GPIO 0
#define PALMTE_USB_OR_DC_GPIO 1
#define PALMTE_TSC_GPIO 4

5
include/asm-arm/arch-omap/clock.h
View File

@@ -73,6 +73,8 @@ struct clk {
#endif
};
struct cpufreq_frequency_table;
struct clk_functions {
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
@@ -83,6 +85,9 @@ struct clk_functions {
void (*clk_allow_idle)(struct clk *clk);
void (*clk_deny_idle)(struct clk *clk);
void (*clk_disable_unused)(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
#endif
};
extern unsigned int mpurate;

1
include/asm-arm/arch-omap/entry-macro.S
View File

@@ -8,6 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/irqs.h>
#if defined(CONFIG_ARCH_OMAP1)

1
include/asm-arm/arch-omap/gpio.h
View File

@@ -26,7 +26,6 @@
#ifndef __ASM_ARCH_OMAP_GPIO_H
#define __ASM_ARCH_OMAP_GPIO_H
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/io.h>

1
include/asm-arm/arch-omap/hardware.h
View File

@@ -41,7 +41,6 @@
#include <asm/types.h>
#include <asm/arch/cpu.h>
#endif
#include <asm/arch/io.h>
#include <asm/arch/serial.h>
/*

1
include/asm-arm/arch-pxa/mfp-pxa27x.h
View File

@@ -112,6 +112,7 @@
#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
/* I2C */
#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1)

9
include/asm-arm/arch-pxa/pxa2xx-gpio.h
View File

@@ -134,7 +134,11 @@
#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
#define GPIO96_FFRXD 96 /* FFUART recieve */
#define GPIO98_FFRTS 98 /* FFUART request to send */
#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
#define GPIO99_FFTXD 99 /* FFUART transmit data */
#define GPIO100_FFCTS 100 /* FFUART Clear to send */
#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
@@ -316,6 +320,8 @@
#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN)
#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT)
#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
@@ -324,8 +330,11 @@
#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN)
#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT)
#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT)
#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)

5
include/asm-arm/arch-pxa/regs-lcd.h
View File

@@ -1,5 +1,8 @@
#ifndef __ASM_ARCH_REGS_LCD_H
#define __ASM_ARCH_REGS_LCD_H
#include <asm/arch/bitfield.h>
/*
* LCD Controller Registers and Bits Definitions
*/
@@ -69,7 +72,7 @@
#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
#define LCCR0_PDD_S 12
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
#define LCCR0_LCDT (1 << 22) /* LCD panel type */
#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */

4
include/asm-arm/arch-sa1100/collie.h
View File

@@ -34,9 +34,12 @@
#define COLLIE_GPIO_ON_KEY GPIO_GPIO (0)
#define COLLIE_GPIO_AC_IN GPIO_GPIO (1)
#define COLLIE_GPIO_SDIO_INT GPIO_GPIO (11)
#define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14)
#define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15)
#define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16)
#define COLLIE_GPIO_nMIC_ON GPIO_GPIO (17)
#define COLLIE_GPIO_nREMOCON_ON GPIO_GPIO (18)
#define COLLIE_GPIO_CO GPIO_GPIO (20)
#define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21)
#define COLLIE_GPIO_CF_CD GPIO_GPIO (22)
@@ -49,6 +52,7 @@
#define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0
#define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1
#define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11
#define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14
#define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15
#define COLLIE_IRQ_GPIO_CO IRQ_GPIO20

4
include/asm-arm/page.h
View File

@@ -179,10 +179,10 @@ typedef unsigned long pgprot_t;
#endif /* STRICT_MM_TYPECHECKS */
typedef struct page *pgtable_t;
#endif /* CONFIG_MMU */
typedef struct page *pgtable_t;
#include <asm/memory.h>
#endif /* !__ASSEMBLY__ */

1
include/asm-arm/pgtable-nommu.h
View File

@@ -16,7 +16,6 @@
#include <linux/slab.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/io.h>
/*
* Trivial page table functions.

2
include/asm-arm/spinlock.h
View File

@@ -142,7 +142,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
}
/* write_can_lock - would write_trylock() succeed? */
#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
#define __raw_write_can_lock(x) ((x)->lock == 0)
/*
* Read locks are a bit more hairy:

29
include/asm-arm/system.h
View File

@@ -48,20 +48,6 @@
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
#else
#define read_cpuid(reg) (processor_id)
#endif
/*
* This is used to ensure the compiler did actually allocate the register we
* asked it for some inline assembly sequences. Apparently we can't trust
@@ -78,6 +64,21 @@
#include <linux/stringify.h>
#include <linux/irqflags.h>
#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
#else
extern unsigned int processor_id;
#define read_cpuid(reg) (processor_id)
#endif
/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID

7
include/asm-blackfin/bfin-global.h
View File

@@ -105,13 +105,6 @@ extern int sram_free(const void*);
extern void *sram_alloc_with_lsl(size_t, unsigned long);
extern int sram_free_with_lsl(const void*);
extern void led_on(int);
extern void led_off(int);
extern void led_toggle(int);
extern void led_disp_num(int);
extern void led_toggle_num(int);
extern void init_leds(void);
extern const char bfin_board_name[];
extern unsigned long wall_jiffies;

5
include/asm-blackfin/mach-bf527/anomaly.h
View File

@@ -15,12 +15,16 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
@@ -92,7 +96,6 @@
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)

8
include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
@@ -90,7 +96,7 @@ struct bfin_serial_port {
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct work_struct cts_workqueue;
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif

31
include/asm-blackfin/mach-bf533/anomaly.h
View File

@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf533/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
@@ -176,6 +176,21 @@
#define ANOMALY_05000315 (1)
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* PPI Does Not Start Properly In Specific Mode */
#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
@@ -249,20 +264,6 @@
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
/* Internal Voltage Regulator may not start up */
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* PPI Does Not Start Properly In Specific Mode */
#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0)

8
include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
@@ -82,7 +88,7 @@ struct bfin_serial_port {
# endif
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct work_struct cts_workqueue;
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif

10
include/asm-blackfin/mach-bf537/anomaly.h
View File

@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf537/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
@@ -132,8 +132,8 @@
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
/* New Feature: UART Remains Enabled after UART Boot */
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -145,12 +145,10 @@
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000158 (0)

8
include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
@@ -90,7 +96,7 @@ struct bfin_serial_port {
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct work_struct cts_workqueue;
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif

2
include/asm-blackfin/mach-bf548/anomaly.h
View File

@@ -75,6 +75,8 @@
#define ANOMALY_05000365 (1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */

12
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
View File

@@ -57,6 +57,12 @@
#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
@@ -93,7 +99,7 @@ struct bfin_serial_port {
struct work_struct tx_dma_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct work_struct cts_workqueue;
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif
@@ -181,7 +187,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
#ifdef CONFIG_BFIN_UART1_CTSRTS
peripheral_request(P_UART1_RTS, DRIVER_NAME);
peripheral_request(P_UART1_CTS DRIVER_NAME);
peripheral_request(P_UART1_CTS, DRIVER_NAME);
#endif
#endif
@@ -196,7 +202,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
#ifdef CONFIG_BFIN_UART3_CTSRTS
peripheral_request(P_UART3_RTS, DRIVER_NAME);
peripheral_request(P_UART3_CTS DRIVER_NAME);
peripheral_request(P_UART3_CTS, DRIVER_NAME);
#endif
#endif
SSYNC();

2
include/asm-blackfin/mach-bf561/anomaly.h
View File

@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf561/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/

8
include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
View File

@@ -53,6 +53,12 @@
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
@@ -82,7 +88,7 @@ struct bfin_serial_port {
# endif
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
struct work_struct cts_workqueue;
struct timer_list cts_timer;
int cts_pin;
int rts_pin;
#endif

2
include/asm-frv/checksum.h
View File

@@ -75,7 +75,7 @@ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
: "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (inc), "=&r"(tmp)
: "0" (sum), "1" (iph), "2" (ihl), "3" (4),
"m"(*(volatile struct { int _[100]; } *)iph)
: "icc0", "icc1"
: "icc0", "icc1", "memory"
);
return (__force __sum16)~sum;

7
include/asm-frv/mem-layout.h
View File

@@ -31,6 +31,13 @@
#define PAGE_MASK (~(PAGE_SIZE-1))
/*
* the slab must be aligned such that load- and store-double instructions don't
* fault if used
*/
#define ARCH_KMALLOC_MINALIGN 8
#define ARCH_SLAB_MINALIGN 8
/*****************************************************************************/
/*
* virtual memory layout from kernel's point of view

2
include/asm-generic/Kbuild.asm
View File

@@ -1,6 +1,6 @@
header-y += kvm.h
ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h)
ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/a.out.h),)
unifdef-y += a.out.h
endif
unifdef-y += auxvec.h

2
include/asm-generic/atomic.h
View File

@@ -2,7 +2,7 @@
#define _ASM_GENERIC_ATOMIC_H
/*
* Copyright (C) 2005 Silicon Graphics, Inc.
* Christoph Lameter <clameter@sgi.com>
* Christoph Lameter
*
* Allows to provide arch independent atomic definitions without the need to
* edit all arch specific atomic.h files.

6
include/asm-generic/gpio.h
View File

@@ -1,8 +1,12 @@
#ifndef _ASM_GENERIC_GPIO_H
#define _ASM_GENERIC_GPIO_H
#include <linux/types.h>
#ifdef CONFIG_HAVE_GPIO_LIB
#include <linux/compiler.h>
/* Platforms may implement their GPIO interface with library code,
* at a small performance cost for non-inlined operations and some
* extra memory (for code and for per-GPIO table entries).
@@ -74,7 +78,7 @@ struct gpio_chip {
extern const char *gpiochip_is_requested(struct gpio_chip *chip,
unsigned offset);
extern int __init __must_check gpiochip_reserve(int start, int ngpio);
extern int __must_check gpiochip_reserve(int start, int ngpio);
/* add/remove chips */
extern int gpiochip_add(struct gpio_chip *chip);

2
include/asm-h8300/cacheflush.h
View File

@@ -3,7 +3,7 @@
*/
#ifndef _ASM_H8300_CACHEFLUSH_H
#define _AMS_H8300_CACHEFLUSH_H
#define _ASM_H8300_CACHEFLUSH_H
/*
* Cache handling functions

1
include/asm-ia64/patch.h
View File

@@ -21,6 +21,7 @@ extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel
extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end);
extern void ia64_patch_vtop (unsigned long start, unsigned long end);
extern void ia64_patch_phys_stack_reg(unsigned long val);
extern void ia64_patch_rse (unsigned long start, unsigned long end);
extern void ia64_patch_gate (void);
#endif /* _ASM_IA64_PATCH_H */

2
include/asm-ia64/ptrace.h
View File

@@ -76,7 +76,7 @@
# define KERNEL_STACK_SIZE_ORDER 0
#endif
#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 15) & ~15)
#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31)
#define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE)
#define KERNEL_STACK_SIZE IA64_STK_OFFSET

1
include/asm-ia64/sections.h
View File

@@ -10,6 +10,7 @@
extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
extern char __start___rse_patchlist[], __end___rse_patchlist[];
extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[];
extern char __start_gate_section[];

7
include/asm-ia64/sn/simulator.h
View File

@@ -8,7 +8,7 @@
#ifndef _ASM_IA64_SN_SIMULATOR_H
#define _ASM_IA64_SN_SIMULATOR_H
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
#define SNMAGIC 0xaeeeeeee8badbeefL
#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
@@ -16,5 +16,10 @@
#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
#else
#define IS_MEDUSA() 0
#define SIMULATOR_SLEEP()
#define IS_RUNNING_ON_SIMULATOR() 0
#endif
#endif /* _ASM_IA64_SN_SIMULATOR_H */

2
include/asm-m32r/uaccess.h
View File

@@ -14,6 +14,7 @@
#include <linux/errno.h>
#include <linux/thread_info.h>
#include <asm/page.h>
#include <asm/setup.h>
#define VERIFY_READ 0
#define VERIFY_WRITE 1
@@ -106,7 +107,6 @@ static inline void set_fs(mm_segment_t s)
#else
static inline int access_ok(int type, const void *addr, unsigned long size)
{
extern unsigned long memory_start, memory_end;
unsigned long val = (unsigned long)addr;
return ((val >= memory_start) && ((val + size) < memory_end));

45
include/asm-m68k/bitops.h
View File

@@ -410,8 +410,49 @@ static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#define ext2_find_next_bit(addr, size, off) \
generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == 0UL) {
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (ext2_test_bit(res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for one in first longword */
for (res = bit; res < 32; res++)
if (ext2_test_bit(res, p))
return (p - addr) * 32 + res;
p++;
}
/* No set bit yet, search remaining full bytes for a set bit */
res = ext2_find_first_bit(p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#endif /* __KERNEL__ */

4
include/asm-mips/atomic.h
View File

@@ -283,10 +283,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
" beqz %0, 2f \n"
" subu %0, %1, %3 \n"
" .set reorder \n"
"1: \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
@@ -664,10 +664,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
" beqz %0, 2f \n"
" dsubu %0, %1, %3 \n"
" .set reorder \n"
"1: \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)

4
include/asm-mips/cpu-info.h
View File

@@ -56,7 +56,7 @@ struct cpuinfo_mips {
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
int core; /* physical core number */
#if defined(CONFIG_MIPS_MT_SMTC)
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered
* to be a "CPU" for the purposes of scheduling, but
@@ -64,7 +64,7 @@ struct cpuinfo_mips {
* to all TCs within the same VPE.
*/
int vpe_id; /* Virtual Processor number */
#endif /* CONFIG_MIPS_MT */
#endif
#ifdef CONFIG_MIPS_MT_SMTC
int tc_id; /* Thread Context number */
#endif

6
include/asm-mips/gic.h
View File

@@ -24,8 +24,8 @@
#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr))
#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS)
#define REGP(base, phys) REG32((unsigned int)(base) + (phys))
#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
/* Accessors */
#define GIC_REG(segment, offset) \
@@ -330,7 +330,7 @@
#define GIC_SH_RMASK_OFS 0x0300
#define GIC_CLR_INTR_MASK(intr, val) \
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS 0x0000

4
include/asm-mips/lasat/serial.h
View File

@@ -4,10 +4,10 @@
#define LASAT_BASE_BAUD_100 (7372800 / 16)
#define LASAT_UART_REGS_BASE_100 0x1c8b0000
#define LASAT_UART_REGS_SHIFT_100 2
#define LASATINT_UART_100 8
#define LASATINT_UART_100 16
/* * LASAT 200 boards serial configuration */
#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
#define LASAT_UART_REGS_SHIFT_200 3
#define LASATINT_UART_200 13
#define LASATINT_UART_200 21

3
include/asm-mips/mach-au1x00/au1000.h
View File

@@ -615,6 +615,7 @@ enum soc_au1500_ints {
AU1000_RTC_MATCH1_INT,
AU1000_RTC_MATCH2_INT,
AU1500_PCI_ERR_INT,
AU1500_RESERVED_INT,
AU1000_USB_DEV_REQ_INT,
AU1000_USB_DEV_SUS_INT,
AU1000_USB_HOST_INT,
@@ -1036,7 +1037,7 @@ enum soc_au1200_ints {
#define USBD_INTSTAT 0xB020001C
# define USBDEV_INT_SOF (1 << 12)
# define USBDEV_INT_HF_BIT 6
# define USBDEV_INT_HF_MASK 0x3f << USBDEV_INT_HF_BIT)
# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
# define USBDEV_INT_CMPLT_BIT 0
# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
#define USBD_CONFIG 0xB0200020

1
include/asm-mips/mach-au1x00/au1xxx_dbdma.h
View File

@@ -355,6 +355,7 @@ void au1xxx_dbdma_dump(u32 chanid);
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
extern void au1xxx_ddma_del_device(u32 devid);
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
/*

3
include/asm-mips/mipsregs.h
View File

@@ -765,6 +765,9 @@ do { \
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
#define read_c0_random() __read_32bit_c0_register($1, 0)
#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)

2
include/asm-mips/pgtable-bits.h
View File

@@ -134,6 +134,4 @@
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
#endif /* _ASM_PGTABLE_BITS_H */

3
include/asm-mips/pgtable.h
View File

@@ -239,9 +239,10 @@ static inline pte_t pte_mkdirty(pte_t pte)
static inline pte_t pte_mkyoung(pte_t pte)
{
pte.pte_low |= _PAGE_ACCESSED;
if (pte.pte_low & _PAGE_READ)
if (pte.pte_low & _PAGE_READ) {
pte.pte_low |= _PAGE_SILENT_READ;
pte.pte_high |= _PAGE_SILENT_READ;
}
return pte;
}
#else

2
include/asm-mips/rtlx.h
View File

@@ -3,7 +3,7 @@
*
*/
#ifndef __ASM_RTLX_H
#ifndef __ASM_RTLX_H_
#define __ASM_RTLX_H_
#include <irq.h>

2
include/asm-mn10300/ipcbuf.h
View File

@@ -1,4 +1,4 @@
#ifndef _ASM_IPCBUF_H_
#ifndef _ASM_IPCBUF_H
#define _ASM_IPCBUF_H
/*

2
include/asm-parisc/checksum.h
View File

@@ -65,7 +65,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
"2:\n"
: "=r" (sum), "=r" (iph), "=r" (ihl)
: "1" (iph), "2" (ihl)
: "r19", "r20", "r21" );
: "r19", "r20", "r21", "memory");
return (__force __sum16)sum;
}

1
include/asm-powerpc/Kbuild
View File

@@ -1,6 +1,5 @@
include include/asm-generic/Kbuild.asm
header-y += a.out.h
header-y += auxvec.h
header-y += ioctls.h
header-y += mman.h

6
include/asm-powerpc/hugetlb.h
View File

@@ -49,12 +49,6 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
ptep_set_wrprotect(mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep,
pte_t pte, int dirty)

12
include/asm-powerpc/io.h
View File

@@ -100,7 +100,7 @@ static inline type name(const volatile type __iomem *addr) \
{ \
type ret; \
__asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \
: "=r" (ret) : "r" (addr), "m" (*addr)); \
: "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
return ret; \
}
@@ -108,8 +108,8 @@ static inline type name(const volatile type __iomem *addr) \
static inline void name(volatile type __iomem *addr, type val) \
{ \
__asm__ __volatile__("sync;" insn \
: "=m" (*addr) : "r" (val), "r" (addr)); \
IO_SET_SYNC_FLAG(); \
: "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
IO_SET_SYNC_FLAG(); \
}
@@ -333,7 +333,8 @@ static inline unsigned int name(unsigned int port) \
" .long 3b,5b\n" \
".previous" \
: "=&r" (x) \
: "r" (port + _IO_BASE)); \
: "r" (port + _IO_BASE) \
: "memory"); \
return x; \
}
@@ -350,7 +351,8 @@ static inline void name(unsigned int val, unsigned int port) \
" .long 0b,2b\n" \
" .long 1b,2b\n" \
".previous" \
: : "r" (val), "r" (port + _IO_BASE)); \
: : "r" (val), "r" (port + _IO_BASE) \
: "memory"); \
}
__do_in_asm(_rec_inb, "lbzx")

1
include/asm-powerpc/kvm_ppc.h
View File

@@ -57,6 +57,7 @@ extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
extern int kvmppc_emulate_instruction(struct kvm_run *run,
struct kvm_vcpu *vcpu);
extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn,
u64 asid, u32 flags);

12
include/asm-powerpc/mediabay.h
View File

@@ -17,8 +17,6 @@
#define MB_POWER 6 /* media bay contains a Power device (???) */
#define MB_NO 7 /* media bay contains nothing */
int check_media_bay(struct device_node *which_bay, int what);
/* Number of bays in the machine or 0 */
extern int media_bay_count;
@@ -29,6 +27,16 @@ int check_media_bay_by_base(unsigned long base, int what);
/* called by IDE PMAC host driver to register IDE controller for media bay */
int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
int irq, ide_hwif_t *hwif);
int check_media_bay(struct device_node *which_bay, int what);
#else
static inline int check_media_bay(struct device_node *which_bay, int what)
{
return -ENODEV;
}
#endif
#endif /* __KERNEL__ */

3
include/asm-powerpc/mpic.h
View File

@@ -428,12 +428,11 @@ extern void mpic_init(struct mpic *mpic);
*/
/* Change/Read the priority of an interrupt. Default is 8 for irqs and
/* Change the priority of an interrupt. Default is 8 for irqs and
* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
* IPI number is then the offset'ed (linux irq number mapped to the IPI)
*/
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
extern unsigned int mpic_irq_get_priority(unsigned int irq);
/* Setup a non-boot CPU */
extern void mpic_setup_this_cpu(void);

10
include/asm-powerpc/pgtable-ppc64.h
View File

@@ -314,6 +314,16 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
}
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
unsigned long old;
if ((pte_val(*ptep) & _PAGE_RW) == 0)
return;
old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
}
/*
* We currently remove entries from the hashtable regardless of whether
* the entry was young or dirty. The generic routines only flush if the

1
include/asm-powerpc/spu.h
View File

@@ -131,7 +131,6 @@ struct spu {
u64 flags;
u64 class_0_pending;
u64 class_0_dar;
u64 class_0_dsisr;
u64 class_1_dar;
u64 class_1_dsisr;
size_t ls_size;

2
include/asm-powerpc/spu_csa.h
View File

@@ -254,7 +254,7 @@ struct spu_state {
u64 spu_chnldata_RW[32];
u32 spu_mailbox_data[4];
u32 pu_mailbox_data[1];
u64 class_0_dar, class_0_dsisr, class_0_pending;
u64 class_0_dar, class_0_pending;
u64 class_1_dar, class_1_dsisr;
unsigned long suspend_time;
spinlock_t register_lock;

2
include/asm-powerpc/system.h
View File

@@ -34,7 +34,7 @@
* SMP since it is only used to order updates to system memory.
*/
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
#define read_barrier_depends() do { } while(0)

5
include/asm-s390/pgtable.h
View File

@@ -223,6 +223,9 @@ extern char empty_zero_page[PAGE_SIZE];
#define _PAGE_SPECIAL 0x004 /* SW associated with special page */
#define __HAVE_ARCH_PTE_SPECIAL
/* Set of bits not changed in pte_modify */
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL)
/* Six different types of pages. */
#define _PAGE_TYPE_EMPTY 0x400
#define _PAGE_TYPE_NONE 0x401
@@ -681,7 +684,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
*/
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
pte_val(pte) &= PAGE_MASK;
pte_val(pte) &= _PAGE_CHG_MASK;
pte_val(pte) |= pgprot_val(newprot);
return pte;
}

8
include/asm-s390/system.h
View File

@@ -315,14 +315,14 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
asm volatile( \
" lctlg %1,%2,0(%0)\n" \
: : "a" (&array), "i" (low), "i" (high), \
"m" (*(addrtype *)(array))); \
"m" (*(addrtype *)(&array))); \
})
#define __ctl_store(array, low, high) ({ \
typedef struct { char _[sizeof(array)]; } addrtype; \
asm volatile( \
" stctg %2,%3,0(%1)\n" \
: "=m" (*(addrtype *)(array)) \
: "=m" (*(addrtype *)(&array)) \
: "a" (&array), "i" (low), "i" (high)); \
})
@@ -333,14 +333,14 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
asm volatile( \
" lctl %1,%2,0(%0)\n" \
: : "a" (&array), "i" (low), "i" (high), \
"m" (*(addrtype *)(array))); \
"m" (*(addrtype *)(&array))); \
})
#define __ctl_store(array, low, high) ({ \
typedef struct { char _[sizeof(array)]; } addrtype; \
asm volatile( \
" stctl %2,%3,0(%1)\n" \
: "=m" (*(addrtype *)(array)) \
: "=m" (*(addrtype *)(&array)) \
: "a" (&array), "i" (low), "i" (high)); \
})

6
include/asm-s390/types.h
View File

@@ -40,7 +40,13 @@ typedef __signed__ long saddr_t;
#ifndef __ASSEMBLY__
typedef u64 dma64_addr_t;
#ifdef __s390x__
/* DMA addresses come in 32-bit and 64-bit flavours. */
typedef u64 dma_addr_t;
#else
typedef u32 dma_addr_t;
#endif
#ifndef __s390x__
typedef union {

2
include/asm-sh/checksum_32.h
View File

@@ -109,7 +109,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
will assume they contain their original values. */
: "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
: "1" (iph), "2" (ihl)
: "t");
: "t", "memory");
return csum_fold(sum);
}

66
include/asm-sparc64/io.h
View File

@@ -24,7 +24,8 @@ static inline u8 _inb(unsigned long addr)
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -35,7 +36,8 @@ static inline u16 _inw(unsigned long addr)
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -46,7 +48,8 @@ static inline u32 _inl(unsigned long addr)
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -55,21 +58,24 @@ static inline void _outb(u8 b, unsigned long addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
static inline void _outw(u16 w, unsigned long addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
static inline void _outl(u32 l, unsigned long addr)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define inb(__addr) (_inb((unsigned long)(__addr)))
@@ -128,7 +134,8 @@ static inline u8 _readb(const volatile void __iomem *addr)
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -137,7 +144,8 @@ static inline u16 _readw(const volatile void __iomem *addr)
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -147,7 +155,8 @@ static inline u32 _readl(const volatile void __iomem *addr)
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -157,7 +166,8 @@ static inline u64 _readq(const volatile void __iomem *addr)
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
@@ -166,28 +176,32 @@ static inline void _writeb(u8 b, volatile void __iomem *addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
static inline void _writew(u16 w, volatile void __iomem *addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
static inline void _writel(u32 l, volatile void __iomem *addr)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
static inline void _writeq(u64 q, volatile void __iomem *addr)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
: /* no outputs */
: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define readb(__addr) _readb(__addr)
@@ -299,7 +313,8 @@ static inline u8 _sbus_readb(const volatile void __iomem *addr)
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret;
}
@@ -310,7 +325,8 @@ static inline u16 _sbus_readw(const volatile void __iomem *addr)
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret;
}
@@ -321,7 +337,8 @@ static inline u32 _sbus_readl(const volatile void __iomem *addr)
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret;
}
@@ -332,7 +349,8 @@ static inline u64 _sbus_readq(const volatile void __iomem *addr)
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
return ret;
}
@@ -341,28 +359,32 @@ static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
}
static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
}
static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
}
static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
: "memory");
}
#define sbus_readb(__addr) _sbus_readb(__addr)

8
include/asm-sparc64/ptrace.h
View File

@@ -126,6 +126,8 @@ struct sparc_trapf {
#define TRACEREG32_SZ sizeof(struct pt_regs32)
#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
#ifdef __KERNEL__
struct global_reg_snapshot {
unsigned long tstate;
unsigned long tpc;
@@ -137,8 +139,6 @@ struct global_reg_snapshot {
unsigned long pad2;
};
#ifdef __KERNEL__
#define __ARCH_WANT_COMPAT_SYS_PTRACE
#define force_successful_syscall_return() \
@@ -306,6 +306,8 @@ extern void __show_regs(struct pt_regs *);
#define SF_XARG5 0x58
#define SF_XXARG 0x5c
#ifdef __KERNEL__
/* global_reg_snapshot offsets */
#define GR_SNAP_TSTATE 0x00
#define GR_SNAP_TPC 0x08
@@ -316,6 +318,8 @@ extern void __show_regs(struct pt_regs *);
#define GR_SNAP_PAD1 0x30
#define GR_SNAP_PAD2 0x38
#endif /* __KERNEL__ */
/* Stuff for the ptrace system call */
#define PTRACE_SPARC_DETACH 11
#define PTRACE_GETREGS 12

12
include/asm-um/mmu_context.h
View File

@@ -22,16 +22,10 @@ extern void force_flush_all(void);
static inline void activate_mm(struct mm_struct *old, struct mm_struct *new)
{
/*
* This is called by fs/exec.c and fs/aio.c. In the first case, for an
* exec, we don't need to do anything as we're called from userspace
* and thus going to use a new host PID. In the second, we're called
* from a kernel thread, and thus need to go doing the mmap's on the
* host. Since they're very expensive, we want to avoid that as far as
* possible.
* This is called by fs/exec.c and sys_unshare()
* when the new ->mm is used for the first time.
*/
if (old != new && (current->flags & PF_BORROWED_MM))
__switch_mm(&new->context.id);
__switch_mm(&new->context.id);
arch_dup_mmap(old, new);
}

2
include/asm-v850/clinkage.h
View File

@@ -11,7 +11,7 @@
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __CLINKAGE_H__
#ifndef __V850_CLINKAGE_H__
#define __V850_CLINKAGE_H__
#include <asm/macrology.h>

4
include/asm-x86/geode.h
View File

@@ -112,8 +112,8 @@ extern int geode_get_dev_base(unsigned int dev);
#define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
#define VSA_VR_SIGNATURE 0x0003
#define VSA_VR_MEM_SIZE 0x0200
#define VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
#define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
#define GSW_VSA_SIG 0x534d /* General Software signature */
/* GPIO */
#define GPIO_OUTPUT_VAL 0x00

2
include/asm-x86/i387.h
View File

@@ -193,6 +193,8 @@ static inline int restore_i387(struct _fpstate __user *buf)
#else /* CONFIG_X86_32 */
extern void finit(void);
static inline void tolerant_fwait(void)
{
asm volatile("fnclex ; fwait");

4
include/asm-x86/kvm_host.h
View File

@@ -18,6 +18,7 @@
#include <linux/kvm_para.h>
#include <linux/kvm_types.h>
#include <asm/pvclock-abi.h>
#include <asm/desc.h>
#define KVM_MAX_VCPUS 16
@@ -282,7 +283,8 @@ struct kvm_vcpu_arch {
struct x86_emulate_ctxt emulate_ctxt;
gpa_t time;
struct kvm_vcpu_time_info hv_clock;
struct pvclock_vcpu_time_info hv_clock;
unsigned int hv_clock_tsc_khz;
unsigned int time_offset;
struct page *time_page;
};

33
include/asm-x86/kvm_para.h
View File

@@ -48,24 +48,6 @@ struct kvm_mmu_op_release_pt {
#ifdef __KERNEL__
#include <asm/processor.h>
/* xen binary-compatible interface. See xen headers for details */
struct kvm_vcpu_time_info {
uint32_t version;
uint32_t pad0;
uint64_t tsc_timestamp;
uint64_t system_time;
uint32_t tsc_to_system_mul;
int8_t tsc_shift;
int8_t pad[3];
} __attribute__((__packed__)); /* 32 bytes */
struct kvm_wall_clock {
uint32_t wc_version;
uint32_t wc_sec;
uint32_t wc_nsec;
} __attribute__((__packed__));
extern void kvmclock_init(void);
@@ -89,7 +71,8 @@ static inline long kvm_hypercall0(unsigned int nr)
long ret;
asm volatile(KVM_HYPERCALL
: "=a"(ret)
: "a"(nr));
: "a"(nr)
: "memory");
return ret;
}
@@ -98,7 +81,8 @@ static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
long ret;
asm volatile(KVM_HYPERCALL
: "=a"(ret)
: "a"(nr), "b"(p1));
: "a"(nr), "b"(p1)
: "memory");
return ret;
}
@@ -108,7 +92,8 @@ static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
long ret;
asm volatile(KVM_HYPERCALL
: "=a"(ret)
: "a"(nr), "b"(p1), "c"(p2));
: "a"(nr), "b"(p1), "c"(p2)
: "memory");
return ret;
}
@@ -118,7 +103,8 @@ static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
long ret;
asm volatile(KVM_HYPERCALL
: "=a"(ret)
: "a"(nr), "b"(p1), "c"(p2), "d"(p3));
: "a"(nr), "b"(p1), "c"(p2), "d"(p3)
: "memory");
return ret;
}
@@ -129,7 +115,8 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
long ret;
asm volatile(KVM_HYPERCALL
: "=a"(ret)
: "a"(nr), "b"(p1), "c"(p2), "d"(p3), "S"(p4));
: "a"(nr), "b"(p1), "c"(p2), "d"(p3), "S"(p4)
: "memory");
return ret;
}

2
include/asm-x86/msr.h
View File

@@ -18,7 +18,7 @@ static inline unsigned long long native_read_tscp(unsigned int *aux)
unsigned long low, high;
asm volatile(".byte 0x0f,0x01,0xf9"
: "=a" (low), "=d" (high), "=c" (*aux));
return low | ((u64)high >> 32);
return low | ((u64)high << 32);
}
/*

3
include/asm-x86/page_32.h
View File

@@ -14,7 +14,8 @@
#define __PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL)
#ifdef CONFIG_X86_PAE
#define __PHYSICAL_MASK_SHIFT 36
/* 44=32+12, the limit we can fit into an unsigned long pfn */
#define __PHYSICAL_MASK_SHIFT 44
#define __VIRTUAL_MASK_SHIFT 32
#define PAGETABLE_LEVELS 3

42
include/asm-x86/pvclock-abi.h Normal file
View File

@@ -0,0 +1,42 @@
#ifndef _ASM_X86_PVCLOCK_ABI_H_
#define _ASM_X86_PVCLOCK_ABI_H_
#ifndef __ASSEMBLY__
/*
* These structs MUST NOT be changed.
* They are the ABI between hypervisor and guest OS.
* Both Xen and KVM are using this.
*
* pvclock_vcpu_time_info holds the system time and the tsc timestamp
* of the last update. So the guest can use the tsc delta to get a
* more precise system time. There is one per virtual cpu.
*
* pvclock_wall_clock references the point in time when the system
* time was zero (usually boot time), thus the guest calculates the
* current wall clock by adding the system time.
*
* Protocol for the "version" fields is: hypervisor raises it (making
* it uneven) before it starts updating the fields and raises it again
* (making it even) when it is done. Thus the guest can make sure the
* time values it got are consistent by checking the version before
* and after reading them.
*/
struct pvclock_vcpu_time_info {
u32 version;
u32 pad0;
u64 tsc_timestamp;
u64 system_time;
u32 tsc_to_system_mul;
s8 tsc_shift;
u8 pad[3];
} __attribute__((__packed__)); /* 32 bytes */
struct pvclock_wall_clock {
u32 version;
u32 sec;
u32 nsec;
} __attribute__((__packed__));
#endif /* __ASSEMBLY__ */
#endif /* _ASM_X86_PVCLOCK_ABI_H_ */

13
include/asm-x86/pvclock.h Normal file
View File

@@ -0,0 +1,13 @@
#ifndef _ASM_X86_PVCLOCK_H_
#define _ASM_X86_PVCLOCK_H_
#include <linux/clocksource.h>
#include <asm/pvclock-abi.h>
/* some helper functions for xen and kvm pv clock sources */
cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src);
void pvclock_read_wallclock(struct pvclock_wall_clock *wall,
struct pvclock_vcpu_time_info *vcpu,
struct timespec *ts);
#endif /* _ASM_X86_PVCLOCK_H_ */

13
include/asm-x86/tlbflush.h
View File

@@ -22,12 +22,23 @@ static inline void __native_flush_tlb(void)
static inline void __native_flush_tlb_global(void)
{
unsigned long cr4 = read_cr4();
unsigned long flags;
unsigned long cr4;
/*
* Read-modify-write to CR4 - protect it from preemption and
* from interrupts. (Use the raw variant because this code can
* be called from deep inside debugging code.)
*/
raw_local_irq_save(flags);
cr4 = read_cr4();
/* clear PGE */
write_cr4(cr4 & ~X86_CR4_PGE);
/* write old PGE again and flush TLBs */
write_cr4(cr4);
raw_local_irq_restore(flags);
}
static inline void __native_flush_tlb_single(unsigned long addr)

4
include/asm-x86/xen/page.h
View File

@@ -150,13 +150,9 @@ static inline pte_t __pte_ma(pteval_t x)
return (pte_t) { .pte = x };
}
#ifdef CONFIG_X86_PAE
#define pmd_val_ma(v) ((v).pmd)
#define pud_val_ma(v) ((v).pgd.pgd)
#define __pmd_ma(x) ((pmd_t) { (x) } )
#else /* !X86_PAE */
#define pmd_val_ma(v) ((v).pud.pgd.pgd)
#endif /* CONFIG_X86_PAE */
#define pgd_val_ma(x) ((x).pgd)

3
include/linux/Kbuild
View File

@@ -166,6 +166,9 @@ unifdef-y += acct.h
unifdef-y += adb.h
unifdef-y += adfs_fs.h
unifdef-y += agpgart.h
ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/a.out.h),)
unifdef-y += a.out.h
endif
unifdef-y += apm_bios.h
unifdef-y += atalk.h
unifdef-y += atmdev.h

8
include/linux/a.out.h
View File

@@ -1,8 +1,6 @@
#ifndef __A_OUT_GNU_H__
#define __A_OUT_GNU_H__
#ifdef CONFIG_ARCH_SUPPORTS_AOUT
#define __GNU_EXEC_MACROS__
#ifndef __STRUCT_EXEC_OVERRIDE__
@@ -277,10 +275,4 @@ struct relocation_info
#endif /* no N_RELOCATION_INFO_DECLARED. */
#endif /*__ASSEMBLY__ */
#else /* CONFIG_ARCH_SUPPORTS_AOUT */
#ifndef __ASSEMBLY__
struct exec {
};
#endif
#endif /* CONFIG_ARCH_SUPPORTS_AOUT */
#endif /* __A_OUT_GNU_H__ */

16
include/linux/agp_backend.h
View File

@@ -30,14 +30,6 @@
#ifndef _AGP_BACKEND_H
#define _AGP_BACKEND_H 1
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
enum chipset_type {
NOT_SUPPORTED,
SUPPORTED,
@@ -57,7 +49,7 @@ struct agp_kern_info {
size_t aper_size;
int max_memory; /* In pages */
int current_memory;
int cant_use_aperture;
bool cant_use_aperture;
unsigned long page_mask;
struct vm_operations_struct *vm_ops;
};
@@ -83,9 +75,9 @@ struct agp_memory {
off_t pg_start;
u32 type;
u32 physical;
u8 is_bound;
u8 is_flushed;
u8 vmalloc_flag;
bool is_bound;
bool is_flushed;
bool vmalloc_flag;
};
#define AGP_NORMAL_MEMORY 0

4
include/linux/agpgart.h
View File

@@ -206,8 +206,8 @@ struct agp_front_data {
struct agp_controller *current_controller;
struct agp_controller *controllers;
struct agp_file_private *file_priv_list;
u8 used_by_controller;
u8 backend_acquired;
bool used_by_controller;
bool backend_acquired;
};
#endif /* __KERNEL__ */

2
include/linux/audit.h
View File

@@ -571,7 +571,7 @@ extern void audit_log_lost(const char *message);
extern int audit_update_lsm_rules(void);
/* Private API (for audit.c only) */
extern int audit_filter_user(struct netlink_skb_parms *cb, int type);
extern int audit_filter_user(struct netlink_skb_parms *cb);
extern int audit_filter_type(int type);
extern int audit_receive_filter(int type, int pid, int uid, int seq,
void *data, size_t datasz, uid_t loginuid,

1
include/linux/bitrev.h
View File

@@ -10,6 +10,7 @@ static inline u8 bitrev8(u8 byte)
return byte_rev_table[byte];
}
extern u16 bitrev16(u16 in);
extern u32 bitrev32(u32 in);
#endif /* _LINUX_BITREV_H */

26
include/linux/blktrace_api.h
View File

@@ -55,6 +55,7 @@ enum blktrace_act {
enum blktrace_notify {
__BLK_TN_PROCESS = 0, /* establish pid/name mapping */
__BLK_TN_TIMESTAMP, /* include system clock */
__BLK_TN_MESSAGE, /* Character string message */
};
@@ -79,6 +80,7 @@ enum blktrace_notify {
#define BLK_TN_PROCESS (__BLK_TN_PROCESS | BLK_TC_ACT(BLK_TC_NOTIFY))
#define BLK_TN_TIMESTAMP (__BLK_TN_TIMESTAMP | BLK_TC_ACT(BLK_TC_NOTIFY))
#define BLK_TN_MESSAGE (__BLK_TN_MESSAGE | BLK_TC_ACT(BLK_TC_NOTIFY))
#define BLK_IO_TRACE_MAGIC 0x65617400
#define BLK_IO_TRACE_VERSION 0x07
@@ -119,6 +121,7 @@ struct blk_trace {
int trace_state;
struct rchan *rchan;
unsigned long *sequence;
unsigned char *msg_data;
u16 act_mask;
u64 start_lba;
u64 end_lba;
@@ -149,7 +152,28 @@ extern void blk_trace_shutdown(struct request_queue *);
extern void __blk_add_trace(struct blk_trace *, sector_t, int, int, u32, int, int, void *);
extern int do_blk_trace_setup(struct request_queue *q,
char *name, dev_t dev, struct blk_user_trace_setup *buts);
extern void __trace_note_message(struct blk_trace *, const char *fmt, ...);
/**
* blk_add_trace_msg - Add a (simple) message to the blktrace stream
* @q: queue the io is for
* @fmt: format to print message in
* args... Variable argument list for format
*
* Description:
* Records a (simple) message onto the blktrace stream.
*
* NOTE: BLK_TN_MAX_MSG characters are output at most.
* NOTE: Can not use 'static inline' due to presence of var args...
*
**/
#define blk_add_trace_msg(q, fmt, ...) \
do { \
struct blk_trace *bt = (q)->blk_trace; \
if (unlikely(bt)) \
__trace_note_message(bt, fmt, ##__VA_ARGS__); \
} while (0)
#define BLK_TN_MAX_MSG 128
/**
* blk_add_trace_rq - Add a trace for a request oriented action
@@ -299,6 +323,8 @@ extern int blk_trace_remove(struct request_queue *q);
#define blk_trace_setup(q, name, dev, arg) (-ENOTTY)
#define blk_trace_startstop(q, start) (-ENOTTY)
#define blk_trace_remove(q) (-ENOTTY)
#define blk_add_trace_msg(q, fmt, ...) do { } while (0)
#endif /* CONFIG_BLK_DEV_IO_TRACE */
#endif /* __KERNEL__ */
#endif

2
include/linux/bootmem.h
View File

@@ -94,7 +94,7 @@ extern unsigned long init_bootmem_node(pg_data_t *pgdat,
unsigned long freepfn,
unsigned long startpfn,
unsigned long endpfn);
extern void reserve_bootmem_node(pg_data_t *pgdat,
extern int reserve_bootmem_node(pg_data_t *pgdat,
unsigned long physaddr,
unsigned long size,
int flags);

31
include/linux/capability.h
View File

@@ -31,11 +31,11 @@ struct task_struct;
#define _LINUX_CAPABILITY_VERSION_1 0x19980330
#define _LINUX_CAPABILITY_U32S_1 1
#define _LINUX_CAPABILITY_VERSION_2 0x20071026
#define _LINUX_CAPABILITY_VERSION_2 0x20071026 /* deprecated - use v3 */
#define _LINUX_CAPABILITY_U32S_2 2
#define _LINUX_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_2
#define _LINUX_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_2
#define _LINUX_CAPABILITY_VERSION_3 0x20080522
#define _LINUX_CAPABILITY_U32S_3 2
typedef struct __user_cap_header_struct {
__u32 version;
@@ -77,10 +77,23 @@ struct vfs_cap_data {
} data[VFS_CAP_U32];
};
#ifdef __KERNEL__
#ifndef __KERNEL__
/*
* Backwardly compatible definition for source code - trapped in a
* 32-bit world. If you find you need this, please consider using
* libcap to untrap yourself...
*/
#define _LINUX_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_1
#define _LINUX_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_1
#else
#define _KERNEL_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_3
#define _KERNEL_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_3
typedef struct kernel_cap_struct {
__u32 cap[_LINUX_CAPABILITY_U32S];
__u32 cap[_KERNEL_CAPABILITY_U32S];
} kernel_cap_t;
#define _USER_CAP_HEADER_SIZE (sizeof(struct __user_cap_header_struct))
@@ -351,7 +364,7 @@ typedef struct kernel_cap_struct {
*/
#define CAP_FOR_EACH_U32(__capi) \
for (__capi = 0; __capi < _LINUX_CAPABILITY_U32S; ++__capi)
for (__capi = 0; __capi < _KERNEL_CAPABILITY_U32S; ++__capi)
# define CAP_FS_MASK_B0 (CAP_TO_MASK(CAP_CHOWN) \
| CAP_TO_MASK(CAP_DAC_OVERRIDE) \
@@ -361,7 +374,7 @@ typedef struct kernel_cap_struct {
# define CAP_FS_MASK_B1 (CAP_TO_MASK(CAP_MAC_OVERRIDE))
#if _LINUX_CAPABILITY_U32S != 2
#if _KERNEL_CAPABILITY_U32S != 2
# error Fix up hand-coded capability macro initializers
#else /* HAND-CODED capability initializers */
@@ -372,7 +385,7 @@ typedef struct kernel_cap_struct {
# define CAP_NFSD_SET ((kernel_cap_t){{ CAP_FS_MASK_B0|CAP_TO_MASK(CAP_SYS_RESOURCE), \
CAP_FS_MASK_B1 } })
#endif /* _LINUX_CAPABILITY_U32S != 2 */
#endif /* _KERNEL_CAPABILITY_U32S != 2 */
#define CAP_INIT_INH_SET CAP_EMPTY_SET
@@ -488,6 +501,8 @@ extern const kernel_cap_t __cap_empty_set;
extern const kernel_cap_t __cap_full_set;
extern const kernel_cap_t __cap_init_eff_set;
kernel_cap_t cap_set_effective(const kernel_cap_t pE_new);
int capable(int cap);
int __capable(struct task_struct *t, int cap);

2
include/linux/cfag12864b.h
View File

@@ -4,7 +4,7 @@
* Description: cfag12864b LCD driver header
* License: GPLv2
*
* Author: Copyright (C) Miguel Ojeda Sandonis <maxextreme@gmail.com>
* Author: Copyright (C) Miguel Ojeda Sandonis
* Date: 2006-10-12
*
* This program is free software; you can redistribute it and/or modify

1
include/linux/cpuidle.h
View File

@@ -82,6 +82,7 @@ struct cpuidle_state_kobj {
};
struct cpuidle_device {
unsigned int registered:1;
unsigned int enabled:1;
unsigned int cpu;

4
include/linux/cpumask.h
View File

@@ -353,6 +353,10 @@ static inline void __cpus_fold(cpumask_t *dstp, const cpumask_t *origp,
for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)
#endif /* NR_CPUS */
#define next_cpu_nr(n, src) next_cpu(n, src)
#define cpus_weight_nr(cpumask) cpus_weight(cpumask)
#define for_each_cpu_mask_nr(cpu, mask) for_each_cpu_mask(cpu, mask)
/*
* The following particular system cpumasks and operations manage
* possible, present and online cpus. Each of them is a fixed size

2
include/linux/dcache.h
View File

@@ -300,7 +300,7 @@ extern int d_validate(struct dentry *, struct dentry *);
extern char *dynamic_dname(struct dentry *, char *, int, const char *, ...);
extern char *__d_path(const struct path *path, struct path *root, char *, int);
extern char *d_path(struct path *, char *, int);
extern char *d_path(const struct path *, char *, int);
extern char *dentry_path(struct dentry *, char *, int);
/* Allocation counts.. */

10
include/linux/debug_locks.h
View File

@@ -1,6 +1,8 @@
#ifndef __LINUX_DEBUG_LOCKING_H
#define __LINUX_DEBUG_LOCKING_H
#include <linux/kernel.h>
struct task_struct;
extern int debug_locks;
@@ -11,14 +13,6 @@ extern int debug_locks_silent;
*/
extern int debug_locks_off(void);
/*
* In the debug case we carry the caller's instruction pointer into
* other functions, but we dont want the function argument overhead
* in the nondebug case - hence these macros:
*/
#define _RET_IP_ (unsigned long)__builtin_return_address(0)
#define _THIS_IP_ ({ __label__ __here; __here: (unsigned long)&&__here; })
#define DEBUG_LOCKS_WARN_ON(c) \
({ \
int __ret = 0; \

3
include/linux/device.h
View File

@@ -385,6 +385,9 @@ static inline const char *dev_name(struct device *dev)
return dev->bus_id;
}
extern int dev_set_name(struct device *dev, const char *name, ...)
__attribute__((format(printf, 2, 3)));
#ifdef CONFIG_NUMA
static inline int dev_to_node(struct device *dev)
{

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