net: phy: Add dts support for Motorcomm yt8521 gigabit ethernet phy
Add dts support for Motorcomm yt8521 gigabit ethernet phy. Add ytphy_rgmii_clk_delay_config function to support dst config for the delay of rgmii clk. This funciont is common for yt8521, yt8531s and yt8531. This patch has been verified on AM335x platform. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Frank Sae
David S. Miller
parent
4869a146cd
commit
a6e68f0f87
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@ -10,6 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#define PHY_ID_YT8511 0x0000010a
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#define PHY_ID_YT8521 0x0000011a
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@ -187,21 +188,9 @@
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* 1b1 use inverted tx_clk_rgmii.
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*/
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#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14)
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/* TX Gig-E Delay is bits 3:0, default 0x1
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* TX Fast-E Delay is bits 7:4, default 0xf
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* RX Delay is bits 13:10, default 0x0
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* Delay = 150ps * N
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* On = 2250ps, off = 0ps
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*/
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#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10)
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#define YT8521_RC1R_RX_DELAY_EN (0xF << 10)
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#define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10)
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#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
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#define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4)
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#define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4)
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#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
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#define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0)
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#define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0)
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#define YT8521_RC1R_RGMII_0_000_NS 0
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#define YT8521_RC1R_RGMII_0_150_NS 1
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#define YT8521_RC1R_RGMII_0_300_NS 2
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@ -274,6 +263,10 @@
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/* Extended Register end */
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#define YTPHY_DTS_OUTPUT_CLK_DIS 0
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#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
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#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
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struct yt8521_priv {
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/* combo_advertising is used for case of YT8521 in combo mode,
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* this means that yt8521 may work in utp or fiber mode which depends
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@ -640,6 +633,142 @@ static int yt8521_write_page(struct phy_device *phydev, int page)
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return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
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};
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/**
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* struct ytphy_cfg_reg_map - map a config value to a register value
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* @cfg: value in device configuration
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* @reg: value in the register
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*/
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struct ytphy_cfg_reg_map {
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u32 cfg;
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u32 reg;
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};
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static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
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/* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */
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{ 0, YT8521_RC1R_RGMII_0_000_NS },
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{ 150, YT8521_RC1R_RGMII_0_150_NS },
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{ 300, YT8521_RC1R_RGMII_0_300_NS },
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{ 450, YT8521_RC1R_RGMII_0_450_NS },
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{ 600, YT8521_RC1R_RGMII_0_600_NS },
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{ 750, YT8521_RC1R_RGMII_0_750_NS },
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{ 900, YT8521_RC1R_RGMII_0_900_NS },
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{ 1050, YT8521_RC1R_RGMII_1_050_NS },
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{ 1200, YT8521_RC1R_RGMII_1_200_NS },
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{ 1350, YT8521_RC1R_RGMII_1_350_NS },
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{ 1500, YT8521_RC1R_RGMII_1_500_NS },
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{ 1650, YT8521_RC1R_RGMII_1_650_NS },
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{ 1800, YT8521_RC1R_RGMII_1_800_NS },
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{ 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
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{ 2100, YT8521_RC1R_RGMII_2_100_NS },
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{ 2250, YT8521_RC1R_RGMII_2_250_NS },
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/* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */
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{ 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS },
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{ 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS },
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{ 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS },
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{ 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS },
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{ 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS },
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{ 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS },
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{ 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS },
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{ 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS },
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{ 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS },
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{ 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS },
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{ 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS },
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{ 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS },
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{ 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS },
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{ 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS },
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{ 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS },
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{ 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS }
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};
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static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
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const char *prop_name,
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const struct ytphy_cfg_reg_map *tbl,
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int tb_size,
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u16 *rxc_dly_en,
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u32 dflt)
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{
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struct device_node *node = phydev->mdio.dev.of_node;
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int tb_size_half = tb_size / 2;
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u32 val;
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int i;
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if (of_property_read_u32(node, prop_name, &val))
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goto err_dts_val;
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/* when rxc_dly_en is NULL, it is get the delay for tx, only half of
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* tb_size is valid.
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*/
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if (!rxc_dly_en)
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tb_size = tb_size_half;
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for (i = 0; i < tb_size; i++) {
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if (tbl[i].cfg == val) {
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if (rxc_dly_en && i < tb_size_half)
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*rxc_dly_en = 0;
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return tbl[i].reg;
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}
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}
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phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n",
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val, prop_name, dflt);
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err_dts_val:
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/* when rxc_dly_en is not NULL, it is get the delay for rx.
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* The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
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* so YT8521_CCR_RXC_DLY_EN should not be set.
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*/
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if (rxc_dly_en)
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*rxc_dly_en = 0;
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return dflt;
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}
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static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
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{
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int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
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u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN;
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u32 rx_reg, tx_reg;
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u16 mask, val = 0;
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int ret;
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rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps",
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ytphy_rgmii_delays, tb_size,
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&rxc_dly_en,
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YT8521_RC1R_RGMII_1_950_NS);
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tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps",
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ytphy_rgmii_delays, tb_size, NULL,
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YT8521_RC1R_RGMII_1_950_NS);
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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rxc_dly_en = 0;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg);
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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rxc_dly_en = 0;
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val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) |
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FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
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break;
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default: /* do not support other modes */
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return -EOPNOTSUPP;
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}
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ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
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YT8521_CCR_RXC_DLY_EN, rxc_dly_en);
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if (ret < 0)
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return ret;
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/* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */
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mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK;
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return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val);
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}
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/**
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* yt8521_probe() - read chip config then set suitable polling_mode
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* @phydev: a pointer to a &struct phy_device
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@ -648,9 +777,12 @@ static int yt8521_write_page(struct phy_device *phydev, int page)
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*/
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static int yt8521_probe(struct phy_device *phydev)
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{
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struct device_node *node = phydev->mdio.dev.of_node;
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struct device *dev = &phydev->mdio.dev;
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struct yt8521_priv *priv;
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int chip_config;
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u16 mask, val;
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u32 freq;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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@ -695,7 +827,45 @@ static int yt8521_probe(struct phy_device *phydev)
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return ret;
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}
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return 0;
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if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
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freq = YTPHY_DTS_OUTPUT_CLK_DIS;
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if (phydev->drv->phy_id == PHY_ID_YT8521) {
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switch (freq) {
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case YTPHY_DTS_OUTPUT_CLK_DIS:
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mask = YT8521_SCR_SYNCE_ENABLE;
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val = 0;
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break;
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case YTPHY_DTS_OUTPUT_CLK_25M:
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mask = YT8521_SCR_SYNCE_ENABLE |
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YT8521_SCR_CLK_SRC_MASK |
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YT8521_SCR_CLK_FRE_SEL_125M;
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val = YT8521_SCR_SYNCE_ENABLE |
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FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
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YT8521_SCR_CLK_SRC_REF_25M);
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break;
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case YTPHY_DTS_OUTPUT_CLK_125M:
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mask = YT8521_SCR_SYNCE_ENABLE |
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YT8521_SCR_CLK_SRC_MASK |
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YT8521_SCR_CLK_FRE_SEL_125M;
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val = YT8521_SCR_SYNCE_ENABLE |
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YT8521_SCR_CLK_FRE_SEL_125M |
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FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
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YT8521_SCR_CLK_SRC_PLL_125M);
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break;
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default:
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phydev_warn(phydev, "Freq err:%u\n", freq);
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return -EINVAL;
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}
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} else if (phydev->drv->phy_id == PHY_ID_YT8531S) {
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return 0;
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} else {
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phydev_warn(phydev, "PHY id err\n");
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return -EINVAL;
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}
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return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
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val);
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}
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/**
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@ -1180,61 +1350,36 @@ static int yt8521_resume(struct phy_device *phydev)
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*/
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static int yt8521_config_init(struct phy_device *phydev)
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{
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struct device_node *node = phydev->mdio.dev.of_node;
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int old_page;
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int ret = 0;
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u16 val;
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old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
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if (old_page < 0)
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goto err_restore_page;
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS;
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val |= YT8521_RC1R_RX_DELAY_DIS;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS;
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val |= YT8521_RC1R_RX_DELAY_EN;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN;
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val |= YT8521_RC1R_RX_DELAY_DIS;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN;
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val |= YT8521_RC1R_RX_DELAY_EN;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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break;
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default: /* do not support other modes */
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ret = -EOPNOTSUPP;
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goto err_restore_page;
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}
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/* set rgmii delay mode */
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
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ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG,
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(YT8521_RC1R_RX_DELAY_MASK |
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YT8521_RC1R_FE_TX_DELAY_MASK |
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YT8521_RC1R_GE_TX_DELAY_MASK),
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val);
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ret = ytphy_rgmii_clk_delay_config(phydev);
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if (ret < 0)
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goto err_restore_page;
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}
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/* disable auto sleep */
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ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
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YT8521_ESC1R_SLEEP_SW, 0);
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if (ret < 0)
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goto err_restore_page;
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/* enable RXC clock when no wire plug */
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ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
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YT8521_CGR_RX_CLK_EN, 0);
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if (ret < 0)
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goto err_restore_page;
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if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
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/* disable auto sleep */
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ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
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YT8521_ESC1R_SLEEP_SW, 0);
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if (ret < 0)
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goto err_restore_page;
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}
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if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
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/* enable RXC clock when no wire plug */
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ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
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YT8521_CGR_RX_CLK_EN, 0);
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if (ret < 0)
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goto err_restore_page;
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}
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err_restore_page:
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return phy_restore_page(phydev, old_page, ret);
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}
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