From 7fa307524a4d721d4a04523018509882c5414e72 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:37 +0100 Subject: [PATCH 01/47] arm64: tegra: Fixup SYSRAM references The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9ac4f0140700..5f8132884be0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1771,7 +1771,7 @@ iommus = <&smmu TEGRA186_SID_BPMP>; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 851e049b3519..8d29b7fdb044 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2467,7 +2467,7 @@ compatible = "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f0efb3a62804..28961ed31d87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -122,20 +122,20 @@ }; }; - sysram@40000000 { + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; - cpu_bpmp_tx: shmem@4e000 { + cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: shmem@4f000 { + cpu_bpmp_rx: sram@4f000 { reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; @@ -146,7 +146,7 @@ compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From e537adde131bd4cf426e6d77f99060ca302e2f08 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:38 +0100 Subject: [PATCH 02/47] arm64: tegra: Add clock for Tegra234 RTC The RTC device requires a clock. Add it. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 28961ed31d87..400c01acc19f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -93,6 +93,8 @@ reg = <0x0c2a0000 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_CLK_32K>; + clock-names = "rtc"; status = "disabled"; }; From 98094be152d34f8014ca67fbdc210e5261c4b09d Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:39 +0100 Subject: [PATCH 03/47] arm64: tegra: Update Tegra234 BPMP channel addresses On final Tegra234 systems, shared memory for communication with BPMP is located at offset 0x70000 in SYSRAM. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 400c01acc19f..844cab44aee6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -126,19 +126,19 @@ sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; + reg = <0x0 0x40000000 0x0 0x80000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; + ranges = <0x0 0x0 0x40000000 0x80000>; - cpu_bpmp_tx: sram@4e000 { - reg = <0x4e000 0x1000>; + cpu_bpmp_tx: sram@70000 { + reg = <0x70000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: sram@4f000 { - reg = <0x4f000 0x1000>; + cpu_bpmp_rx: sram@71000 { + reg = <0x71000 0x1000>; label = "cpu-bpmp-rx"; pool; }; From e086d82d4f3e867a02a4ef4c245fc4f506173bbb Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:40 +0100 Subject: [PATCH 04/47] arm64: tegra: Fill in properties for Tegra234 eMMC Add missing properties to the eMMC controller, as required to use it on actual hardware. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 844cab44aee6..ffe300356e85 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -40,11 +40,24 @@ compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; interrupts = ; - clocks = <&bpmp TEGRA234_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA234_CLK_SDMMC4>, + <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, + <&bpmp TEGRA234_CLK_PLLC4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; resets = <&bpmp TEGRA234_RESET_SDMMC4>; reset-names = "sdhci"; - dma-coherent; + nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x14>; + nvidia,dqs-trim = <40>; + supports-cqe; status = "disabled"; }; From 06ad2ec4e5f84030ce6554d3859d6c21849bd5a3 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:41 +0100 Subject: [PATCH 05/47] arm64: tegra: Add Tegra234 TCU device Add a device for TCU (Tegra Combined UART) used for serial console. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index ffe300356e85..bd3a01142704 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -192,6 +192,14 @@ method = "smc"; }; + tcu: serial { + compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From f0e1266818f58ab5e687b3aec53d0689c7dc7db0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Dec 2021 17:02:05 +0100 Subject: [PATCH 06/47] arm64: tegra: Add main and AON GPIO controllers on Tegra234 These two controllers expose general purpose I/O pins that can be used to control or monitor a variety of signals. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 74 ++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index bd3a01142704..f715671f0333 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -25,6 +25,65 @@ status = "okay"; }; + gpio: gpio@2200000 { + compatible = "nvidia,tegra234-gpio"; + reg-names = "security", "gpio"; + reg = <0x02200000 0x10000>, + <0x02210000 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x10000>; @@ -111,6 +170,21 @@ status = "disabled"; }; + gpio_aon: gpio@c2f0000 { + compatible = "nvidia,tegra234-gpio-aon"; + reg-names = "security", "gpio"; + reg = <0x0c2f0000 0x1000>, + <0x0c2f1000 0x1000>; + interrupts = , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; reg = <0x0c360000 0x10000>, From a12cf5c339b082a93767b3fa5c85059b8269ab45 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 14:19:04 +0100 Subject: [PATCH 07/47] arm64: tegra: Describe Tegra234 CPU hierarchy The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches with each cluster having an additional 256 KiB unified L2 cache and a 2 MiB L3 cache. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++- 1 file changed, 363 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f715671f0333..b60e4f6f0658 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -252,12 +252,373 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0_0: cpu@0 { + compatible = "arm,cortex-a78"; device_type = "cpu"; - reg = <0x000>; + reg = <0x00000>; enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_0>; }; + + cpu0_1: cpu@100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_1>; + }; + + cpu0_2: cpu@200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_2>; + }; + + cpu0_3: cpu@300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_3>; + }; + + cpu1_0: cpu@10000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_0>; + }; + + cpu1_1: cpu@10100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_1>; + }; + + cpu1_2: cpu@10200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_2>; + }; + + cpu1_3: cpu@10300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_3>; + }; + + cpu2_0: cpu@20000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_0>; + }; + + cpu2_1: cpu@20100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_1>; + }; + + cpu2_2: cpu@20200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_2>; + }; + + cpu2_3: cpu@20300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_3>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0_0>; + }; + + core1 { + cpu = <&cpu0_1>; + }; + + core2 { + cpu = <&cpu0_2>; + }; + + core3 { + cpu = <&cpu0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1_0>; + }; + + core1 { + cpu = <&cpu1_1>; + }; + + core2 { + cpu = <&cpu1_2>; + }; + + core3 { + cpu = <&cpu1_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2_0>; + }; + + core1 { + cpu = <&cpu2_1>; + }; + + core2 { + cpu = <&cpu2_2>; + }; + + core3 { + cpu = <&cpu2_3>; + }; + }; + }; + + l2c0_0: l2-cache00 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_1: l2-cache01 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_2: l2-cache02 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_3: l2-cache03 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c1_0: l2-cache10 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_1: l2-cache11 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_2: l2-cache12 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_3: l2-cache13 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c2_0: l2-cache20 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_1: l2-cache21 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_2: l2-cache22 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_3: l2-cache23 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l3c0: l3-cache0 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3c1: l3-cache1 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3c2: l3-cache2 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + }; + + pmu { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + status = "okay"; }; psci { From 533337d5c843650043771503221774f3dffbead0 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:42 +0100 Subject: [PATCH 08/47] arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support The Jetson AGX Orin Developer Kit is a continuation of the Jetson Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 25 +++++++++++++++++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 24 ++++++++++++++++++ .../boot/dts/nvidia/tegra234-p3737-0000.dtsi | 5 ++++ 4 files changed, 55 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index c80f7dc2935e..ea3f338fd013 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -12,3 +12,4 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi new file mode 100644 index 000000000000..d3c936822186 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234.dtsi" + +/ { + model = "NVIDIA Jetson AGX Orin"; + compatible = "nvidia,p3701-0000", "nvidia,tegra234"; + + bus@0 { + mmc@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + only-1-8-v; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts new file mode 100644 index 000000000000..efbbb878ba5a --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra234-p3701-0000.dtsi" +#include "tegra234-p3737-0000.dtsi" + +/ { + model = "NVIDIA Jetson AGX Orin Developer Kit"; + compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234"; + + aliases { + mmc3 = "/bus@0/mmc@3460000"; + serial0 = &tcu; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + serial { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi new file mode 100644 index 000000000000..a85993c85e45 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3737-0000"; +}; From ff21087e6131e7d81c17d5b34bd786866ca90553 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Tue, 16 Nov 2021 17:32:36 +0530 Subject: [PATCH 09/47] arm64: tegra: Add support to enumerate SD in UHS mode Add support to enumerate SD in UHS mode on Tegra194. Add required device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic pad voltage switching and enumerate SD card in UHS-I modes. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8d29b7fdb044..3b424496384e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -893,6 +894,9 @@ <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = @@ -904,6 +908,10 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; nvidia,default-tap = <0x9>; nvidia,default-trim = <0x5>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -920,6 +928,9 @@ <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_SDMMC3>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc3_3v3>; + pinctrl-1 = <&sdmmc3_1v8>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; @@ -932,6 +943,10 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; nvidia,default-tap = <0x9>; nvidia,default-trim = <0x5>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -1472,6 +1487,25 @@ #interrupt-cells = <2>; interrupt-controller; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = ; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = ; + }; + }; smmu: iommu@12000000 { From f7eb2785728442cc349a68965bc3c9a869274336 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 17 Nov 2021 09:56:08 +0000 Subject: [PATCH 10/47] arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194 Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 +++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 54 ++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 5f8132884be0..fe588666bcfc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1538,6 +1538,21 @@ iommus = <&smmu TEGRA186_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; + dsib: dsi@15400000 { compatible = "nvidia,tegra186-dsi"; reg = <0x15400000 0x10000>; @@ -1569,6 +1584,21 @@ iommus = <&smmu TEGRA186_SID_NVDEC>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; + sor0: sor@15540000 { compatible = "nvidia,tegra186-sor"; reg = <0x15540000 0x10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3b424496384e..c97febf90ead 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1739,6 +1739,22 @@ iommus = <&smmu TEGRA194_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra194-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA194_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_NVJPG>; + dma-coherent; + }; + nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; reg = <0x15480000 0x00040000>; @@ -1758,6 +1774,25 @@ nvidia,host1x-class = <0xf0>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC>; + dma-coherent; + + nvidia,host1x-class = <0x21>; + }; + dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; reg = <0x155c0000 0x10000>; @@ -1894,6 +1929,25 @@ }; }; + nvenc@15a80000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x15a80000 0x00040000>; + clocks = <&bpmp TEGRA194_CLK_NVENC1>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC1>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC1>; + dma-coherent; + + nvidia,host1x-class = <0x22>; + }; + sor0: sor@15b00000 { compatible = "nvidia,tegra194-sor"; reg = <0x15b00000 0x40000>; From e762232f946679b6be60244d78079aa12cc5ed68 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 1 Dec 2021 15:57:16 +0000 Subject: [PATCH 11/47] arm64: tegra: Add ISO SMMU controller for Tegra194 The display controllers are attached to a separate ARM SMMU instance that is dedicated to servicing isochronous memory clients. Add this ISO instance of the ARM SMMU to device tree. Please note that the display controllers are not hooked up to this SMMU yet, because we are still missing a means to transition framebuffers used by the bootloader to the kernel. This based upon an initial patch by Thierry Reding . Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c97febf90ead..f9b1900088ad 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1508,6 +1508,82 @@ }; + iommu@10000000 { + compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; + reg = <0x10000000 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + smmu: iommu@12000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; reg = <0x12000000 0x800000>, From 4cc3e3e164c02c6f2fce38f2098a1fe1256ea58d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:58:55 +0100 Subject: [PATCH 12/47] arm64: tegra: Rename top-level clocks Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 8a51751526ee..ecd58bd2770f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1023,7 +1023,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 6077d572d828..d3e622c4a439 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -301,7 +301,7 @@ vqmmc-supply = <&vdd_1v8>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 58aa0518965e..0a70daeffd85 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -40,7 +40,7 @@ non-removable; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 41beab626d95..ed73c3a0c140 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1586,7 +1586,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 030f264eccd5..cbd8cda48f37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1645,7 +1645,7 @@ }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 131c064d6991..43ff5e4bda19 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1726,7 +1726,7 @@ }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; From 097e01c61015e41975873a1e51e3106456aa581a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 18:02:18 +0100 Subject: [PATCH 13/47] arm64: tegra: Rename top-level regulators Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 26 +++++++------- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 6 ++-- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3668-0000.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 30 ++++++++-------- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 36 +++++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 18 +++++----- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 16 ++++----- 12 files changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index ecd58bd2770f..c84ed1cb9a8c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1057,7 +1057,7 @@ ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-vdd-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <19000000>; @@ -1066,7 +1066,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1076,7 +1076,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1086,7 +1086,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-vdd-3v3-run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1098,7 +1098,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-vdd-3v3-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1106,7 +1106,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-vdd-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vin-supply = <&vdd_mux>; }; - vdd_usb1_vbus: regulator@6 { + vdd_usb1_vbus: regulator-vdd-usb1-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1127,7 +1127,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@7 { + vdd_usb3_vbus: regulator-vdd-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1138,7 +1138,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@8 { + vdd_3v3_panel: regulator-vdd-3v3-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1148,7 +1148,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@9 { + vdd_hdmi_pll: regulator-vdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; regulator-min-microvolt = <1050000>; @@ -1157,7 +1157,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@10 { + vdd_5v0_hdmi: regulator-vdd-5v0-hdmi { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1167,7 +1167,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_5v0_ts: regulator@11 { + vdd_5v0_ts: regulator-vdd-5v0-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS"; regulator-min-microvolt = <5000000>; @@ -1178,7 +1178,7 @@ enable-active-high; }; - vdd_3v3_lp0: regulator@12 { + vdd_3v3_lp0: regulator-vdd-3v3-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 52fa258533e6..2883049c4edf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -2250,7 +2250,7 @@ }; }; - vdd_sd: regulator@100 { + vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "SD_CARD_SW_PWR"; regulator-min-microvolt = <3300000>; @@ -2262,7 +2262,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@101 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -2274,7 +2274,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb0: regulator@102 { + vdd_usb0: regulator-vdd-usb0 { compatible = "regulator-fixed"; regulator-name = "VDD_USB0"; regulator-min-microvolt = <5000000>; @@ -2286,7 +2286,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1: regulator@103 { + vdd_usb1: regulator-vdd-usb1 { compatible = "regulator-fixed"; regulator-name = "VDD_USB1"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index fcd71bfc6707..4917b43995b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -393,7 +393,7 @@ method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -402,7 +402,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -411,7 +411,7 @@ regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index af33fe93e1d6..28d59792eaa1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -593,7 +593,7 @@ method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -602,7 +602,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -611,7 +611,7 @@ regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; @@ -623,7 +623,7 @@ vin-supply = <&vdd_1v8>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c4058ee36fec..ad217cac2b28 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -317,7 +317,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VIN_SYS_5V0"; regulator-min-microvolt = <5000000>; @@ -326,7 +326,7 @@ regulator-boot-on; }; - vdd_hdmi: regulator@1 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -335,7 +335,7 @@ enable-active-high; }; - vdd_3v3_pcie: regulator@2 { + vdd_3v3_pcie: regulator-vdd-3v3-pcie { compatible = "regulator-fixed"; regulator-name = "PEX_3V3"; regulator-min-microvolt = <3300000>; @@ -345,7 +345,7 @@ enable-active-high; }; - vdd_12v_pcie: regulator@3 { + vdd_12v_pcie: regulator-vdd-12v-pcie { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; regulator-min-microvolt = <1200000>; @@ -354,7 +354,7 @@ regulator-boot-on; }; - vdd_5v_sata: regulator@4 { + vdd_5v_sata: regulator-vdd-5v0-sata { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SATA"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index a055f17218bb..8d3999cd1af2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2000,7 +2000,7 @@ }; }; - vdd_5v0_sys: regulator@100 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SYS"; regulator-min-microvolt = <5000000>; @@ -2009,7 +2009,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@101 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -2018,7 +2018,7 @@ regulator-boot-on; }; - vdd_3v3_ao: regulator@102 { + vdd_3v3_ao: regulator-vdd-3v3-ao { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_AO"; regulator-min-microvolt = <3300000>; @@ -2027,7 +2027,7 @@ regulator-boot-on; }; - vdd_1v8: regulator@103 { + vdd_1v8: regulator-vdd-1v8 { compatible = "regulator-fixed"; regulator-name = "VDD_1V8"; regulator-min-microvolt = <1800000>; @@ -2036,7 +2036,7 @@ regulator-boot-on; }; - vdd_hdmi: regulator@104 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi index 14da4206ea66..8c2c709dd54c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi @@ -20,7 +20,7 @@ }; }; - vdd_3v3_sd: regulator@0 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index d3e622c4a439..75eb743a7242 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -336,7 +336,7 @@ method = "smc"; }; - vdd_gpu: regulator@100 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index d8409c1b4380..34276a84c68a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1555,7 +1555,7 @@ }; }; - vdd_sys_mux: regulator@0 { + vdd_sys_mux: regulator-vdd-sys-mux { compatible = "regulator-fixed"; regulator-name = "VDD_SYS_MUX"; regulator-min-microvolt = <5000000>; @@ -1564,7 +1564,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -1576,7 +1576,7 @@ vin-supply = <&vdd_sys_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -1591,7 +1591,7 @@ regulator-disable-ramp-delay = <10000>; }; - vdd_5v0_io: regulator@3 { + vdd_5v0_io: regulator-vdd-5v0-io { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_IO_SYS"; regulator-min-microvolt = <5000000>; @@ -1600,7 +1600,7 @@ regulator-boot-on; }; - vdd_3v3_sd: regulator@4 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; @@ -1613,7 +1613,7 @@ regulator-disable-ramp-delay = <4880>; }; - vdd_dsi_csi: regulator@5 { + vdd_dsi_csi: regulator-vdd-dsi-csi { compatible = "regulator-fixed"; regulator-name = "AVDD_DSI_CSI_1V2"; regulator-min-microvolt = <1200000>; @@ -1621,7 +1621,7 @@ vin-supply = <&vdd_sys_1v2>; }; - vdd_3v3_dis: regulator@6 { + vdd_3v3_dis: regulator-vdd-3v3-dis { compatible = "regulator-fixed"; regulator-name = "VDD_DIS_3V3_LCD"; regulator-min-microvolt = <3300000>; @@ -1632,7 +1632,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_1v8_dis: regulator@7 { + vdd_1v8_dis: regulator-vdd-1v8-dis { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_1V8_DIS"; regulator-min-microvolt = <1800000>; @@ -1643,7 +1643,7 @@ vin-supply = <&vdd_1v8>; }; - vdd_5v0_rtl: regulator@8 { + vdd_5v0_rtl: regulator-vdd-5v0-rtl { compatible = "regulator-fixed"; regulator-name = "RTL_5V"; regulator-min-microvolt = <5000000>; @@ -1653,7 +1653,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb_vbus: regulator@9 { + vdd_usb_vbus: regulator-vdd-usb-vbus { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN1"; regulator-min-microvolt = <5000000>; @@ -1663,7 +1663,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_hdmi: regulator@10 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -1673,7 +1673,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cam_1v2: regulator@11 { + vdd_cam_1v2: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v2"; regulator-min-microvolt = <1200000>; @@ -1683,7 +1683,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_2v8: regulator@12 { + vdd_cam_2v8: regulator-vdd-cam-2v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-2v8"; regulator-min-microvolt = <2800000>; @@ -1693,7 +1693,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_1v8: regulator@13 { + vdd_cam_1v8: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v8"; regulator-min-microvolt = <1800000>; @@ -1703,7 +1703,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_usb_vbus_otg: regulator@14 { + vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN0"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index ed73c3a0c140..5cfbc0394173 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1635,7 +1635,7 @@ method = "smc"; }; - battery_reg: regulator@0 { + battery_reg: regulator-vdd-ac-bat { compatible = "regulator-fixed"; regulator-name = "vdd-ac-bat"; regulator-min-microvolt = <5000000>; @@ -1643,7 +1643,7 @@ regulator-always-on; }; - vdd_3v3: regulator@1 { + vdd_3v3: regulator-vdd-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd-3v3"; regulator-enable-ramp-delay = <160>; @@ -1655,7 +1655,7 @@ enable-active-high; }; - max77620_gpio7: regulator@2 { + max77620_gpio7: regulator-max77620-gpio7 { compatible = "regulator-fixed"; regulator-name = "max77620-gpio7"; regulator-enable-ramp-delay = <240>; @@ -1669,7 +1669,7 @@ enable-active-high; }; - lcd_bl_en: regulator@3 { + lcd_bl_en: regulator-lcd-bl-en { compatible = "regulator-fixed"; regulator-name = "lcd-bl-en"; regulator-min-microvolt = <1800000>; @@ -1680,7 +1680,7 @@ enable-active-high; }; - en_vdd_sd: regulator@4 { + en_vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "en-vdd-sd"; regulator-enable-ramp-delay = <472>; @@ -1692,7 +1692,7 @@ enable-active-high; }; - en_vdd_cam: regulator@5 { + en_vdd_cam: regulator-vdd-cam { compatible = "regulator-fixed"; regulator-name = "en-vdd-cam"; regulator-min-microvolt = <1800000>; @@ -1702,7 +1702,7 @@ enable-active-high; }; - vdd_sys_boost: regulator@6 { + vdd_sys_boost: regulator-vdd-sys-boost { compatible = "regulator-fixed"; regulator-name = "vdd-sys-boost"; regulator-enable-ramp-delay = <3090>; @@ -1714,7 +1714,7 @@ enable-active-high; }; - vdd_hdmi: regulator@7 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd-hdmi"; regulator-enable-ramp-delay = <468>; @@ -1727,21 +1727,21 @@ enable-active-high; }; - en_vdd_cpu_fixed: regulator@8 { + en_vdd_cpu_fixed: regulator-vdd-cpu-fixed { compatible = "regulator-fixed"; regulator-name = "vdd-cpu-fixed"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - vdd_aux_3v3: regulator@9 { + vdd_aux_3v3: regulator-vdd-aux-3v3 { compatible = "regulator-fixed"; regulator-name = "aux-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vdd_snsr_pm: regulator@10 { + vdd_snsr_pm: regulator-vdd-snsr-pm { compatible = "regulator-fixed"; regulator-name = "snsr_pm"; regulator-min-microvolt = <3300000>; @@ -1750,7 +1750,7 @@ enable-active-high; }; - vdd_usb_5v0: regulator@11 { + vdd_usb_5v0: regulator-vdd-usb-5v0 { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd-usb-5v0"; @@ -1761,7 +1761,7 @@ enable-active-high; }; - vdd_cdc_1v2_aud: regulator@101 { + vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd_cdc_1v2_aud"; @@ -1772,7 +1772,7 @@ enable-active-high; }; - vdd_disp_3v0: regulator@12 { + vdd_disp_3v0: regulator-vdd-disp-3v0 { compatible = "regulator-fixed"; regulator-name = "vdd-disp-3v0"; regulator-enable-ramp-delay = <232>; @@ -1784,7 +1784,7 @@ enable-active-high; }; - vdd_fan: regulator@13 { + vdd_fan: regulator-vdd-fan { compatible = "regulator-fixed"; regulator-name = "vdd-fan"; regulator-enable-ramp-delay = <284>; @@ -1795,7 +1795,7 @@ enable-active-high; }; - usb_vbus1: regulator@14 { + usb_vbus1: regulator-usb-vbus1 { compatible = "regulator-fixed"; regulator-name = "usb-vbus1"; regulator-min-microvolt = <5000000>; @@ -1806,7 +1806,7 @@ gpio-open-drain; }; - usb_vbus2: regulator@15 { + usb_vbus2: regulator-usb-vbus2 { compatible = "regulator-fixed"; regulator-name = "usb-vbus2"; regulator-min-microvolt = <5000000>; @@ -1817,7 +1817,7 @@ gpio-open-drain; }; - vdd_3v3_eth: regulator@16 { + vdd_3v3_eth: regulator-vdd-3v3-eth { compatible = "regulator-fixed"; regulator-name = "vdd-3v3-eth-a02"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index cbd8cda48f37..283b50febb6f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1762,7 +1762,7 @@ method = "smc"; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; @@ -1772,7 +1772,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; @@ -1789,7 +1789,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_sd: regulator@2 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; @@ -1802,7 +1802,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi-5v0 { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; @@ -1812,7 +1812,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_hub_3v3: regulator@4 { + vdd_hub_3v3: regulator-vdd-hub-3v3 { compatible = "regulator-fixed"; regulator-name = "VDD_HUB_3V3"; @@ -1825,7 +1825,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cpu: regulator@5 { + vdd_cpu: regulator-vdd-cpu { compatible = "regulator-fixed"; regulator-name = "VDD_CPU"; @@ -1840,7 +1840,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_gpu: regulator@6 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; @@ -1855,7 +1855,7 @@ vin-supply = <&vdd_5v0_sys>; }; - avdd_io_edp_1v05: regulator@7 { + avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { compatible = "regulator-fixed"; regulator-name = "AVDD_IO_EDP_1V05"; @@ -1868,7 +1868,7 @@ vin-supply = <&avdd_1v05_pll>; }; - vdd_5v0_usb: regulator@8 { + vdd_5v0_usb: regulator-vdd-5v-usb { compatible = "regulator-fixed"; regulator-name = "VDD_5V_USB"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 43ff5e4bda19..6d59c28ff2a3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1807,7 +1807,7 @@ method = "smc"; }; - ppvar_sys: regulator@0 { + ppvar_sys: regulator-ppvar-sys { compatible = "regulator-fixed"; regulator-name = "PPVAR_SYS"; regulator-min-microvolt = <4400000>; @@ -1815,7 +1815,7 @@ regulator-always-on; }; - pplcd_vdd: regulator@1 { + pplcd_vdd: regulator-pplcd-vdd { compatible = "regulator-fixed"; regulator-name = "PPLCD_VDD"; regulator-min-microvolt = <4400000>; @@ -1825,7 +1825,7 @@ regulator-boot-on; }; - pp3000_always: regulator@2 { + pp3000_always: regulator-pp3000-always { compatible = "regulator-fixed"; regulator-name = "PP3000_ALWAYS"; regulator-min-microvolt = <3000000>; @@ -1833,7 +1833,7 @@ regulator-always-on; }; - pp3300: regulator@3 { + pp3300: regulator-pp3000 { compatible = "regulator-fixed"; regulator-name = "PP3300"; regulator-min-microvolt = <3300000>; @@ -1843,7 +1843,7 @@ enable-active-high; }; - pp5000: regulator@4 { + pp5000: regulator-pp5000 { compatible = "regulator-fixed"; regulator-name = "PP5000"; regulator-min-microvolt = <5000000>; @@ -1851,7 +1851,7 @@ regulator-always-on; }; - pp1800_lcdio: regulator@5 { + pp1800_lcdio: regulator-pp1800-lcdio { compatible = "regulator-fixed"; regulator-name = "PP1800_LCDIO"; regulator-min-microvolt = <1800000>; @@ -1861,7 +1861,7 @@ regulator-boot-on; }; - pp1800_cam: regulator@6 { + pp1800_cam: regulator-pp1800-cam { compatible = "regulator-fixed"; regulator-name = "PP1800_CAM"; regulator-min-microvolt = <1800000>; @@ -1870,7 +1870,7 @@ enable-active-high; }; - usbc_vbus: regulator@7 { + usbc_vbus: regulator-usbc-vbus { compatible = "regulator-fixed"; regulator-name = "USBC_VBUS"; regulator-min-microvolt = <5000000>; From bd1fefcbdd8f1791c9a0e8dd169006c2a466cf17 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Mar 2020 16:45:38 +0100 Subject: [PATCH 14/47] arm64: tegra: Add native timer support on Tegra186 The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index fe588666bcfc..855ae6b705a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -508,6 +508,22 @@ }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; From 2c6fd24dcbf0a8cfb066ca886579a4a8b2275054 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:10:00 +0100 Subject: [PATCH 15/47] arm64: tegra: Fix unit-addresses on Norrin The AS3722 pinmux device tree node doesn't have a "reg" property and therefore must not have a unit-address, so drop it. While at it, add missing unit-addresses for the charger and smart battery IC's on the ChromeOS embedded controller's I2C tunnel bus. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index c84ed1cb9a8c..f9604968c01f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -564,7 +564,7 @@ pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; - as3722_default: pinmux@0 { + as3722_default: pinmux { gpio0 { pins = "gpio0"; function = "gpio"; @@ -770,7 +770,7 @@ google,remote-bus = <0>; - charger: bq24735 { + charger: bq24735@9 { compatible = "ti,bq24735"; reg = <0x9>; interrupt-parent = <&gpio>; @@ -781,7 +781,7 @@ GPIO_ACTIVE_HIGH>; }; - battery: smart-battery { + battery: smart-battery@b { compatible = "sbs,sbs-battery"; reg = <0xb>; sbs,i2c-retry-count = <2>; From 64b407827670f9bd5fe08a4ed10732349339c572 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:11:53 +0100 Subject: [PATCH 16/47] arm64: tegra: Remove unsupported properties on Norrin The Tegra PMC device tree bindings don't support the "#wake-cells" and "nvidia,reset-gpio" properties, so remove them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index f9604968c01f..f16acb4cabaa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -885,14 +885,12 @@ pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; - #wake-cells = <3>; nvidia,cpu-pwr-good-time = <500>; nvidia,cpu-pwr-off-time = <300>; nvidia,core-pwr-good-time = <641 3845>; nvidia,core-pwr-off-time = <61036>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; - nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; }; usb@70090000 { From bb43b219c88c4d1fe7154af787024b885edd45f8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:13:37 +0100 Subject: [PATCH 17/47] arm64: tegra: Fix compatible string for Tegra132 timer The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 63aa3129d8fc..95bdcc8f31c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -210,7 +210,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , From ed9e9a6eb118daa25c0dc04fd5fae55bf8a5356a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:17:07 +0100 Subject: [PATCH 18/47] arm64: tegra: Add OPP tables on Tegra132 Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra132-peripherals-opp.dtsi | 426 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra132.dtsi | 13 +- 2 files changed, 438 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi new file mode 100644 index 000000000000..66ffb7f8aaa7 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible = "operating-points-v2"; + + opp-12750000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp-12750000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp-12750000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp-12750000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp-20400000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp-20400000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp-20400000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp-20400000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-40800000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp-40800000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp-40800000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp-68000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp-68000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp-102000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp-102000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + opp-suspend; + }; + + opp-204000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + opp-suspend; + }; + + opp-204000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + opp-suspend; + }; + + opp-204000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + opp-suspend; + }; + + opp-264000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp-264000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp-264000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp-264000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp-300000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp-300000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp-300000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp-348000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp-348000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp-348000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp-348000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp-396000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp-396000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp-396000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp-528000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp-528000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp-528000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp-528000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp-600000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp-600000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp-600000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp-600000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp-792000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp-792000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp-792000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp-924000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp-20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 95bdcc8f31c9..7f5cbcd63a25 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra132-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra132", "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -244,6 +246,10 @@ clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { @@ -607,15 +613,20 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc"; + compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; }; sata@70020000 { From 92564257d7af8959eb1d5ba7ead6881c931e8bc3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:19:26 +0100 Subject: [PATCH 19/47] arm64: tegra: Fix Tegra132 I2C compatible string list The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 7f5cbcd63a25..0e8903027f04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -400,7 +400,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -415,7 +415,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -430,7 +430,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -445,7 +445,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -460,7 +460,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -475,7 +475,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; From 9f27a6c421163541bc3354b573283e50f24a7c95 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:20:25 +0100 Subject: [PATCH 20/47] arm64: tegra: Drop unused AHCI clocks on Tegra132 The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0e8903027f04..16673d3bf6f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -635,10 +635,8 @@ <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; From fce5d0731616549b9fc2c992b5896f7717fffdd4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:21:18 +0100 Subject: [PATCH 21/47] arm64: tegra: Sort Tegra132 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 16673d3bf6f9..e41671fcd7e3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -674,8 +674,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -683,7 +683,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From fe57ff5365c9aef12e80ee51e38d0ea6bb17b255 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:24:20 +0100 Subject: [PATCH 22/47] arm64: tegra: Rename thermal zones nodes The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 11 ++++--- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 32 +++++++++---------- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 27 +++++++--------- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 6 ++-- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 6 ++-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 30 +++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++--- 8 files changed, 58 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index e41671fcd7e3..3673f79adf1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -895,7 +895,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -923,7 +923,8 @@ }; }; }; - mem { + + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -950,7 +951,8 @@ */ }; }; - gpu { + + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -978,7 +980,8 @@ }; }; }; - pllx { + + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 28d59792eaa1..33e707ef883b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -633,7 +633,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -687,21 +687,7 @@ }; }; - gpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - gpu_alert0: critical { - temperature = <99000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -714,6 +700,20 @@ }; }; }; + + gpu-thermal { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + gpu_alert0: critical { + temperature = <99000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; aconnect@2900000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 855ae6b705a8..a5c19e4b39c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1976,12 +1976,12 @@ }; thermal-zones { - a57 { + /* Cortex-A57 cluster */ + cpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; trips { critical { @@ -1995,12 +1995,12 @@ }; }; - denver { + /* Denver cluster */ + aux-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; trips { critical { @@ -2014,12 +2014,11 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; trips { critical { @@ -2033,12 +2032,11 @@ }; }; - pll { + pll-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; trips { critical { @@ -2052,12 +2050,11 @@ }; }; - always_on { + ao-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; trips { critical { diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 9f34871b8f60..b79d7d89cf62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -2097,7 +2097,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2151,7 +2151,7 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2165,7 +2165,7 @@ }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 8d3999cd1af2..76d94ecd1cfe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2103,7 +2103,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2157,7 +2157,7 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2171,7 +2171,7 @@ }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f9b1900088ad..0ea613715c6f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2903,39 +2903,33 @@ }; thermal-zones { - cpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_CPU>; + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; status = "disabled"; }; - gpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_GPU>; + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; status = "disabled"; }; - aux { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AUX>; + aux-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; status = "disabled"; }; - pllx { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_PLLX>; + pllx-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; status = "disabled"; }; - ao { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AO>; + ao-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; status = "disabled"; }; - tj { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 283b50febb6f..9e60ebf2f5c0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1684,7 +1684,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu_trip_critical: critical { temperature = <96500>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ccdc0dec4e59..af9237ad03c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1981,7 +1981,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2010,7 +2010,7 @@ }; }; - mem { + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -2056,7 +2056,7 @@ }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2085,7 +2085,7 @@ }; }; - pllx { + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; From 4b5ae31fb75655d6270a160a3ebafc48474f597d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:25:50 +0100 Subject: [PATCH 23/47] arm64: tegra: Rename power-monitor input nodes Child nodes of the TI INA3221 power monitor device tree node should be called input@* according to the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++------ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 12 ++++++------ .../dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 2883049c4edf..c4dee05f330c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -1945,19 +1945,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_MUX"; shunt-resistor-micro-ohms = <20000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_5V0_IO_SYS"; shunt-resistor-micro-ohms = <5000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V3_SYS"; shunt-resistor-micro-ohms = <10000>; @@ -1970,19 +1970,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_3V3_IO_SLP"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_1V8_IO"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_M2_IN"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 4917b43995b0..3d8878c0ec03 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -73,19 +73,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_SYS_GPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_SOC"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V8_WIFI"; shunt-resistor-micro-ohms = <10000>; @@ -98,19 +98,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_CPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_5V0_DDR"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 33e707ef883b..6cc51083adb7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -81,22 +81,22 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5>; }; - channel@1 { + input@1 { reg = <1>; label = "VDD_CPU_GPU"; shunt-resistor-micro-ohms = <5>; }; - channel@2 { + input@2 { reg = <2>; label = "VDD_SOC"; - shunt-resistor-micro-ohms = <>; + shunt-resistor-micro-ohms = <5>; }; }; }; From 548c9c5aaf85bb157b1a87fdc558e3767f5f0bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:27:11 +0100 Subject: [PATCH 24/47] arm64: tegra: Fix Tegra186 compatible string list The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a5c19e4b39c5..21f823ea08c6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -585,7 +585,7 @@ }; gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03160000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -598,7 +598,7 @@ }; cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03180000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -612,7 +612,7 @@ /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03190000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -629,7 +629,7 @@ /* controlled by BPMP, should not be enabled */ pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031a0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -643,7 +643,7 @@ /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -659,7 +659,7 @@ }; gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -672,7 +672,7 @@ }; gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1089,7 +1089,7 @@ }; gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1102,7 +1102,7 @@ }; gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = ; #address-cells = <1>; From 2b14cbd643feea5fc17c6e8bead4e71088c69acd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:28:29 +0100 Subject: [PATCH 25/47] arm64: tegra: Adjust length of CCPLEX cluster MMIO region The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 21f823ea08c6..c91afff1b757 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1215,7 +1215,7 @@ ccplex@e000000 { compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x3fffff>; + reg = <0x0 0x0e000000 0x0 0x400000>; nvidia,bpmp = <&bpmp>; }; From e7445ab7dc5160540930912fae02660601b6de80 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:36:35 +0100 Subject: [PATCH 26/47] arm64: tegra: Drop unit-address for audio card graph endpoints Audio graph endpoints don't have a "reg" property, so they shouldn't have a unit-address either. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index b79d7d89cf62..2478ece9e67c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1031,7 +1031,7 @@ i2s6_port: port@1 { reg = <1>; - i2s6_dap_ep: endpoint@0 { + i2s6_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 76d94ecd1cfe..6d4ed67ffeda 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -989,7 +989,7 @@ i2s5_port: port@1 { reg = <1>; - i2s5_dap_ep: endpoint@0 { + i2s5_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9e60ebf2f5c0..260de1122aa3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -688,7 +688,7 @@ i2s4_port: port@1 { reg = <1>; - i2s4_dap_ep: endpoint@0 { + i2s4_dap_ep: endpoint { dai-format = "i2s"; /* Placeholder for external Codec */ }; @@ -706,7 +706,7 @@ port@0 { reg = <0>; - dmic1_cif_ep: endpoint@0 { + dmic1_cif_ep: endpoint { remote-endpoint = <&xbar_dmic1_ep>; }; }; @@ -714,7 +714,7 @@ dmic1_port: port@1 { reg = <1>; - dmic1_dap_ep: endpoint@0 { + dmic1_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; @@ -731,7 +731,7 @@ port@0 { reg = <0>; - dmic2_cif_ep: endpoint@0 { + dmic2_cif_ep: endpoint { remote-endpoint = <&xbar_dmic2_ep>; }; }; @@ -739,7 +739,7 @@ dmic2_port: port@1 { reg = <1>; - dmic2_dap_ep: endpoint@0 { + dmic2_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; From 56797e625910497ef2a2dd40b76be2633a86f726 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:39:20 +0100 Subject: [PATCH 27/47] arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips The standard "jedec," vendor prefix should be used for SPI NOR flash chips. This allows the right DT schema to be picked for validation. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 6d4ed67ffeda..1323fa9b8301 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1878,7 +1878,7 @@ status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <102000000>; spi-tx-bus-width = <4>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 260de1122aa3..9fc4a8f46250 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1637,7 +1637,7 @@ status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; spi-tx-bus-width = <2>; From 2fcb87970e4282a227e09108d479e860b5b9faf0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:40:59 +0100 Subject: [PATCH 28/47] arm64: tegra: Drop unsupported nvidia,lpdr property The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property, so drop them from the device trees that have listed them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0ea613715c6f..5e1cbb788937 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -536,7 +536,6 @@ pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; @@ -548,7 +547,6 @@ clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; From cd6157c1978c84d4fd9b9cedc736fc7b5fce4d09 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:43:20 +0100 Subject: [PATCH 29/47] arm64: tegra: Fix Tegra194 HSP compatible string The HSP instances on Tegra194 are not fully compatible with the version found on Tegra186, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5e1cbb788937..d7fd6bdd131a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1195,7 +1195,7 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; interrupts = , , @@ -1373,7 +1373,7 @@ }; hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; interrupts = , , From 1ff75059077c0d37edb936d9232f76a74704be41 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:47:47 +0100 Subject: [PATCH 30/47] arm64: tegra: Drop unused properties for Tegra194 PCIe The num-viewport property is never used and can be dropped, whereas the "iommus" property is not needed since we use "iommu-map-mask" and "iommu-map" already. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d7fd6bdd131a..bb51ccdb324d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2169,7 +2169,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <1>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; @@ -2202,7 +2201,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE1>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2223,7 +2221,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <2>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; @@ -2256,7 +2253,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE2>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2277,7 +2273,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <3>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; @@ -2310,7 +2305,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE3>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2331,7 +2325,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; - num-viewport = <8>; linux,pci-domain = <4>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; @@ -2364,7 +2357,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2385,7 +2377,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <0>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; @@ -2418,7 +2409,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2439,7 +2429,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <5>; pinctrl-names = "default"; @@ -2476,7 +2465,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2516,7 +2504,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2556,7 +2543,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2599,7 +2585,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; From c453cc9e9e1afbb3c3c2bc2579e4cc2c8ee7641c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:50:44 +0100 Subject: [PATCH 31/47] arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock The "core_m" clock is not documented in the Tegra194 PCIe device tree bindings, so remove it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bb51ccdb324d..bb88d32e553e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2434,9 +2434,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; - clock-names = "core", "core_m"; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, <&bpmp TEGRA194_RESET_PEX1_CORE_5>; From 99d9bde5b4ab05c98f6c2c5e8fb276d3b7072be3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:51:54 +0100 Subject: [PATCH 32/47] arm64: tegra: Rename TCU node to "serial" The TCU is basically a serial port (albeit a fancy one), so it should be named "serial". Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bb88d32e553e..abea546cb072 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2877,7 +2877,7 @@ iommus = <&smmu TEGRA194_SID_APE>; }; - tcu: tcu { + tcu: serial { compatible = "nvidia,tegra194-tcu"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; From 1dcf00ae8205ee2fdbc0c55c41c486f287d20739 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:53:28 +0100 Subject: [PATCH 33/47] arm64: tegra: Remove unsupported regulator properties Remove the unsupported "regulator-disable-ramp-delay" properties which ended up in various DTS files for some reason. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 -- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 11 ----------- 2 files changed, 13 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 34276a84c68a..21d7e653ea5b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1588,7 +1588,6 @@ vin-supply = <&vdd_sys_mux>; regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; }; vdd_5v0_io: regulator-vdd-5v0-io { @@ -1610,7 +1609,6 @@ vin-supply = <&vdd_3v3_sys>; regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; }; vdd_dsi_csi: regulator-vdd-dsi-csi { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9fc4a8f46250..542f51c07781 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -266,7 +266,6 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1170000>; regulator-enable-ramp-delay = <146>; - regulator-disable-ramp-delay = <4080>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -282,7 +281,6 @@ regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <145800>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -298,7 +296,6 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <32000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <350>; regulator-always-on; @@ -314,7 +311,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <242>; - regulator-disable-ramp-delay = <118000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <360>; regulator-always-on; @@ -330,7 +326,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-enable-ramp-delay = <26>; - regulator-disable-ramp-delay = <626>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-always-on; @@ -346,7 +341,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -360,7 +354,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <62>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -378,7 +371,6 @@ regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <610>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-disable-active-discharge; @@ -403,7 +395,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <24>; - regulator-disable-ramp-delay = <2768>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -417,7 +408,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <1160>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -1779,7 +1769,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; regulator-always-on; regulator-boot-on; From 635fb5d4cb2590f3f655f05f880cefabf1cb43dd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:54:48 +0100 Subject: [PATCH 34/47] arm64: tegra: Rename GPIO hog nodes to match schema GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 5cfbc0394173..10347b6e6e84 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1383,7 +1383,7 @@ }; }; - gpio@0 { + hog-0 { gpio-hog; output-high; gpios = <2 GPIO_ACTIVE_HIGH>, From 31bc882c03d447b7ae5c28ed5480467ee714fd91 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:41:53 +0100 Subject: [PATCH 35/47] arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 3 --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 5 ----- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 2e17df6f20ad..328fbfec4ee8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -11,11 +11,8 @@ pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 21d7e653ea5b..4b43b89a9651 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1361,11 +1361,6 @@ dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; avdd-usb-supply = <&vdd_3v3_sys>; - /* XXX what are these? */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; From 54215999f30bf7672c302b34c91db76eed525b5e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:43:03 +0100 Subject: [PATCH 36/47] arm64: tegra: smaug: Remove extra PLL power supplies for XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the XUSB controller device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 6d59c28ff2a3..a263d51882ee 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1642,10 +1642,6 @@ dvddio-pex-supply = <&avddio_1v05>; hvddio-pex-supply = <&pp1800>; avdd-usb-supply = <&pp3300>; - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; status = "okay"; }; From 9c1b3ef8e204ca952d0304d4b92fa54de8b9815a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:56:11 +0100 Subject: [PATCH 37/47] arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 542f51c07781..72c2dc3c14ea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -30,11 +30,8 @@ pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { @@ -446,11 +443,6 @@ avdd-usb-supply = <&vdd_3v3_sys>; dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; - /* these really belong to the XUSB pad controller */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; }; From 28a44b900e572ecb163cc4e042365b7df6e0fad3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:01:37 +0100 Subject: [PATCH 38/47] arm64: tegra: Add missing TSEC properties on Tegra210 Add missing interrupts, clocks, clock-names, reset and reset-names properties for the TSEC blocks found on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index af9237ad03c1..a49a12fd84b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -181,6 +181,12 @@ tsec@54100000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54100000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSEC>; + clock-names = "tsec"; + resets = <&tegra_car 83>; + reset-names = "tsec"; + status = "disabled"; }; dc@54200000 { @@ -283,6 +289,11 @@ tsec@54500000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSECB>; + clock-names = "tsec"; + resets = <&tegra_car 206>; + reset-names = "tsec"; status = "disabled"; }; From f2ef6a9180f38f7b6f633a90126d27e8a669a688 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:05:32 +0100 Subject: [PATCH 39/47] arm64: tegra: Sort Tegra210 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a49a12fd84b1..aa768ea108fe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1026,8 +1026,8 @@ <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA210_CLK_PLL_U_480M>, @@ -1035,7 +1035,7 @@ <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From 02752947367289e8bfd0f09f9c4a5acfb0ac3602 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:06:19 +0100 Subject: [PATCH 40/47] arm64: tegra: Remove unused only-1-8-v properties The only-1-8-v property is not support by an DT schema, so drop it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d3c936822186..d95a542c0bca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -11,7 +11,6 @@ status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts index b5d9a5526272..5804acfc428a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -26,7 +26,6 @@ status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { From 553f07360e23b2e17b26be2fcd9ebfc0c14d0e24 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Dec 2021 16:29:11 +0100 Subject: [PATCH 41/47] arm64: tegra: Rename Ethernet PHY nodes Name the Ethernet PHY device tree nodes as expected by the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 3d8878c0ec03..aff857df25cf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 6cc51083adb7..4631504c3c7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio_aon>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index ad217cac2b28..a7d7cfd66379 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -39,7 +39,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index f16b0aa8a374..0bd66f9c620b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -36,7 +36,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; From a52280c844c0549b16418dc7e70bdf46a66072eb Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 25 Oct 2021 12:08:42 +0100 Subject: [PATCH 42/47] arm64: tegra: Add dma-coherent for Tegra194 VIC DMA operations for the Tegra194 Video Image Compositor (VIC) are coherent and so populate the 'dma-coherent' property. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index abea546cb072..aeb79660c58e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1811,6 +1811,7 @@ <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_VIC>; + dma-coherent; }; nvjpg@15380000 { From c2fee44399af4fda2dd8070cfb96cd6de2385442 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Thu, 16 Dec 2021 15:16:10 +0530 Subject: [PATCH 43/47] arm64: tegra: Update SDMMC4 speeds for Tegra194 Add required device-tree properties to populate all speed modes supported by SDMMC4 instance of Tegra194 SDHCI controller. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index aeb79660c58e..c830f508de42 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -976,6 +976,11 @@ nvidia,default-tap = <0x8>; nvidia,default-trim = <0x14>; nvidia,dqs-trim = <40>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; supports-cqe; status = "disabled"; }; From cc9396676c1bc4414fa62514daadfece55ef3cfb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:49 +0100 Subject: [PATCH 44/47] arm64: tegra: Add EMC general interrupt on Tegra194 Add the missing EMC general interrupt for the external memory controller on Tegra194. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c830f508de42..3c4acfca459d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -592,6 +592,7 @@ compatible = "nvidia,tegra194-emc"; reg = <0x0 0x02c60000 0x0 0x90000>, <0x0 0x01780000 0x0 0x80000>; + interrupts = ; clocks = <&bpmp TEGRA194_CLK_EMC>; clock-names = "emc"; From eed280dfe91d84d6b9ad62e47d1b69aa8d9b4db2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:50 +0100 Subject: [PATCH 45/47] arm64: tegra: Add memory controller on Tegra234 This adds the memory controller and the embedded external memory controller found on the Tegra234 SoC. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index b60e4f6f0658..59ad115369bd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include / { @@ -84,6 +85,54 @@ gpio-controller; }; + mc: memory-controller@2c00000 { + compatible = "nvidia,tegra234-mc"; + reg = <0x02c00000 0x100000>, + <0x02b80000 0x040000>, + <0x01700000 0x100000>; + interrupts = ; + #interconnect-cells = <1>; + status = "okay"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + + /* + * Bit 39 of addresses passing through the memory + * controller selects the XBAR format used when memory + * is accessed. This is used to transparently access + * memory in the XBAR format used by the discrete GPU + * (bit 39 set) or Tegra (bit 39 clear). + * + * As a consequence, the operating system must ensure + * that bit 39 is never used implicitly, for example + * via an I/O virtual address mapping of an IOMMU. If + * devices require access to the XBAR switch, their + * drivers must set this bit explicitly. + * + * Limit the DMA range for memory clients to [38:0]. + */ + dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra234-emc"; + reg = <0x0 0x02c60000 0x0 0x90000>, + <0x0 0x01780000 0x0 0x80000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_EMC>; + clock-names = "emc"; + status = "okay"; + + #interconnect-cells = <0>; + + nvidia,bpmp = <&bpmp>; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x10000>; From 6de481e5ab0d69cddbc7c20e8471a950313d4e07 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:51 +0100 Subject: [PATCH 46/47] arm64: tegra: Hook up MMC and BPMP to memory controller Use the interconnects property to hook up the MMC and BPMP to the memory controller. This is needed to set the correct bus-level DMA mask, which is a prerequisite for adding IOMMU support. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 59ad115369bd..6b6f15804a1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -156,6 +156,9 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; resets = <&bpmp TEGRA234_RESET_SDMMC4>; reset-names = "sdhci"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, + <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; + interconnect-names = "dma-mem", "write"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -288,6 +291,11 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; From 914ed1f56581f99094035f1cc989ab4498104e94 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:53:08 +0100 Subject: [PATCH 47/47] arm64: tegra: Add host1x hotflush reset on Tegra210 Add the host1x memory client hotflush reset on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index aa768ea108fe..218a2b32200f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -93,8 +93,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA210_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; + reset-names = "host1x", "mc"; #address-cells = <2>; #size-cells = <2>;