From b08e569abc91f525834deda751d6ddd1ffe4ab5a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:14 +0100 Subject: [PATCH 01/22] dt-bindings: altera: document existing Cyclone 5 board compatibles Several Cyclone 5 SoCFPGA based boards have additional board compatibles which are not documented in the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/altera.yaml | 30 +++++++++++++++---- 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index c15c92fdf2ed..0d62c2bde053 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -13,12 +13,30 @@ properties: $nodename: const: "/" compatible: - items: - - enum: - - altr,socfpga-cyclone5 - - altr,socfpga-arria5 - - altr,socfpga-arria10 - - const: altr,socfpga + oneOf: + - description: Arria 5 boards + items: + - const: altr,socfpga-arria5 + - const: altr,socfpga + + - description: Arria 10 boards + items: + - const: altr,socfpga-arria10 + - const: altr,socfpga + + - description: Cyclone 5 boards + items: + - enum: + - altr,socfpga-cyclone5-socdk + - denx,mcvevk + - ebv,socrates + - macnica,sodia + - novtech,chameleon96 + - samtec,vining + - terasic,de0-atlas + - terasic,socfpga-cyclone5-sockit + - const: altr,socfpga-cyclone5 + - const: altr,socfpga additionalProperties: true From 8227e63ddf8d1b208f5d0fd58aeb5fec9ab57330 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:15 +0100 Subject: [PATCH 02/22] dt-bindings: altera: document Arria 5 based board compatibles Add new compatible for Arria 5 based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 0d62c2bde053..3d7a2f699279 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -16,6 +16,8 @@ properties: oneOf: - description: Arria 5 boards items: + - enum: + - altr,socfpga-arria5-socdk - const: altr,socfpga-arria5 - const: altr,socfpga From 15dc346c7a1940cf438495162fedf29d86924fa4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:16 +0100 Subject: [PATCH 03/22] dt-bindings: altera: document Arria 10 based board compatibles Add new compatible for Arria 10 based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 3d7a2f699279..963c83904010 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -23,6 +23,9 @@ properties: - description: Arria 10 boards items: + - enum: + - altr,socfpga-arria10-socdk + - enclustra,mercury-aa1 - const: altr,socfpga-arria10 - const: altr,socfpga From 53d50b4f6fa8a6da4ff6fe6cf58a88a92fa15acb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:31:17 +0100 Subject: [PATCH 04/22] dt-bindings: altera: document VT compatibles Add new compatible for SoCFPGA VT boards/designs. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 963c83904010..f4e07a21aaf5 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -43,6 +43,11 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: SoCFPGA VT + items: + - const: altr,socfpga-vt + - const: altr,socfpga + additionalProperties: true ... From f8aa14dd365ab3f0608931503dab3e8665226b25 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:32 +0100 Subject: [PATCH 05/22] dt-bindings: altera: document Stratix 10 based board compatibles Add new compatible for Stratix 10 based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index f4e07a21aaf5..5e2017c0a051 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -43,6 +43,12 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Stratix 10 boards + items: + - enum: + - altr,socfpga-stratix10-socdk + - const: altr,socfpga-stratix10 + - description: SoCFPGA VT items: - const: altr,socfpga-vt From abca30aa14b1ec3d96547ec71d690aa1169cc4e6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:46 +0100 Subject: [PATCH 06/22] dt-bindings: intel: document Agilex based board compatibles Add new compatible for Agilex based boards. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../bindings/arm/intel,socfpga.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml new file mode 100644 index 000000000000..6e043459fcd5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + +additionalProperties: true + +... From ad7f9f3ad1bc7403d0b6d655d92fa7b4b1899629 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:47 +0100 Subject: [PATCH 07/22] dt-bindings: clock: intel,stratix10: convert to dtschema Convert the Intel Stratix 10 clock controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../bindings/clock/intc_stratix10.txt | 20 ----------- .../bindings/clock/intel,stratix10.yaml | 35 +++++++++++++++++++ 2 files changed, 35 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/intc_stratix10.txt create mode 100644 Documentation/devicetree/bindings/clock/intel,stratix10.yaml diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt deleted file mode 100644 index 9f4ec5cb5c6b..000000000000 --- a/Documentation/devicetree/bindings/clock/intc_stratix10.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be - "intel,stratix10-clkmgr" - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - -- #clock-cells : from common clock binding, shall be set to 1. - -Example: - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/intel,stratix10.yaml b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml new file mode 100644 index 000000000000..f506e3db9782 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Stratix10 platform clock controller binding + +maintainers: + - Dinh Nguyen + +properties: + compatible: + const: intel,stratix10-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@ffd10000 { + compatible = "intel,stratix10-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; From 0d108c397005f533a56528de792978676a51a0ac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:49 +0100 Subject: [PATCH 08/22] ARM: dts: arria5: add board compatible for SoCFPGA DK The Altera SoCFPGA Arria V SoC Development Kit is a board with Arria 5, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 1b02d46496a8..0e03011d0247 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -7,7 +7,7 @@ / { model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; + compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; From b6662bf5a3b017886304aea519339b0fb14d3870 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:50 +0100 Subject: [PATCH 09/22] ARM: dts: arria10: add board compatible for Mercury AA1 The Enclustra Mercury AA1 is a module with Arria 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts index 2a3364b26361..a75c059b6727 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts @@ -6,7 +6,7 @@ / { model = "Enclustra Mercury AA1"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; From 40b01ca3c7bd154d88171fb1c70f2e9e9a86613c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:51 +0100 Subject: [PATCH 10/22] ARM: dts: arria10: add board compatible for SoCFPGA DK The Altera SoCFPGA Arria 10 SoC Development Kit is a board with Arria 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 7edebe20e859..ec7365444a3b 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -6,7 +6,7 @@ / { model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; From 1c0bd03532507afb9c185eee376306477d44a053 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:52 +0100 Subject: [PATCH 11/22] arm64: dts: stratix10: add board compatible for SoCFPGA DK The Altera SoCFPGA Stratix 10 SoC Development Kit is a board with Stratix 10, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 46e558ab7729..12392292c62c 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index bbc3db42d6e8..2d53a06deab5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; From 79f1db278f82301b940e91d1b47da3b71b0b3d68 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:53 +0100 Subject: [PATCH 12/22] arm64: dts: stratix10: move ARM timer out of SoC node The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dt.yaml: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 13, 3848], [1, 14, 3848], [1, 11, 3848], [1, 10, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../boot/dts/altera/socfpga_stratix10.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 3ec301bd08a9..505542b75a36 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -77,6 +77,16 @@ method = "smc"; }; + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + interrupt-parent = <&intc>; + }; + intc: interrupt-controller@fffc1000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -406,15 +416,6 @@ reg = <0xffd12000 0x228>; }; - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - timer0: timer0@ffc03000 { compatible = "snps,dw-apb-timer"; interrupts = <0 113 4>; From 8b794ab20780b09ec0384c03ef02169fa35d40dd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:54 +0100 Subject: [PATCH 13/22] arm64: dts: stratix10: align mmc node names with dtschema The Synopsys DW MSHC bindings require node name to be 'mmc': dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 505542b75a36..4124021768b1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -296,7 +296,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; From 327a96a1cb26b8674aac9863b016f6110fb44fa0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:55 +0100 Subject: [PATCH 14/22] arm64: dts: stratix10: align regulator node names with dtschema The devicetree specification requires that node name should be generic. The dtschema complains if name does not match pattern, so make the 0.33 V regulator node name more generic. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 12392292c62c..5159cd5771dc 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -44,7 +44,7 @@ reg = <0 0 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 2d53a06deab5..0ab676c639a1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -44,7 +44,7 @@ reg = <0 0 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; From 50ae688a08a77260249cb5022a441b8a87903405 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:56 +0100 Subject: [PATCH 15/22] arm64: dts: agilex: add board compatible for SoCFPGA DK The Intel SoCFPGA Agilex 10 SoC Development Kit is a board with Agilex, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 0f7a0ba344be..ea37ba7ccff9 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -6,6 +6,7 @@ / { model = "SoCFPGA Agilex SoCDK"; + compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index 57f83481f551..51f83f96ec65 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -6,6 +6,7 @@ / { model = "SoCFPGA Agilex SoCDK"; + compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; From fae3aa6c82f588214e3ffaf4408dd99d4894048b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:57 +0100 Subject: [PATCH 16/22] arm64: dts: agilex: add board compatible for N5X DK The Intel SoCFPGA N5X SoC Development Kit is a board with Agilex, so it needs its own compatible. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index f3c1310dae0a..5609d8df6729 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -6,6 +6,7 @@ / { model = "eASIC N5X SoCDK"; + compatible = "intel,n5x-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; From 9ffc4e03dce02be1275b5577275426a48696502d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Dec 2021 14:35:58 +0100 Subject: [PATCH 17/22] arm64: dts: agilex: align mmc node names with dtschema The Synopsys DW MSHC bindings require node name to be 'mmc': dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 0dd2d2ee765a..63dd4e69c962 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -300,7 +300,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; From 814927744e4e401d938ea8dc036cb048721ac32b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Jan 2022 18:41:57 +0100 Subject: [PATCH 18/22] arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema Align the LED node names with dtschema to silence dtbs_check warnings like: leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index ea37ba7ccff9..26cd3c121757 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -21,17 +21,17 @@ leds { compatible = "gpio-leds"; - hps0 { + led0 { label = "hps_led0"; gpios = <&portb 20 GPIO_ACTIVE_HIGH>; }; - hps1 { + led1 { label = "hps_led1"; gpios = <&portb 19 GPIO_ACTIVE_HIGH>; }; - hps2 { + led2 { label = "hps_led2"; gpios = <&portb 21 GPIO_ACTIVE_HIGH>; }; From 180be1b7a387af184d9eabd14fde82cd932219c3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:34 +0100 Subject: [PATCH 19/22] arm64: dts: stratix10: align pl330 node name with dtschema Fixes dtbs_check warnings like: pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 4124021768b1..da032a6f71da 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -333,7 +333,7 @@ reg = <0xffe00000 0x100000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = <0 81 4>, From e3e4ffe1139fffbe10c2ee060aa7fa438c9baf47 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jan 2022 18:55:35 +0100 Subject: [PATCH 20/22] arm64: dts: agilex: align pl330 node name with dtschema Fixes dtbs_check warnings like: pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 63dd4e69c962..1f4618c1062e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -337,7 +337,7 @@ reg = <0xffe00000 0x40000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = , From bd702d3a859b579354798a0ae0df281ed6148fe4 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 31 Jan 2022 10:05:31 -0600 Subject: [PATCH 21/22] ARM: dts: socfpga: arria10: align regulator node with dtschema Fixes dtbs_check warnings like: '3-3-v-regulator' does not match any of the regexes: '.*-names$' Cc: Krzysztof Kozlowski Reported-by: kernel test robot Signed-off-by: Dinh Nguyen --- v2: fix compile error --- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 0e03011d0247..7f5458d8fccc 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -50,7 +50,7 @@ }; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; From 0f7b715101f097cd1784272f67a8c3f570d7958f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 1 Feb 2022 11:12:08 -0600 Subject: [PATCH 22/22] ARM: dts: socfpga: cyclone5: align regulator node with dtschema Fixes dtbs_check warnings like: '3-3-v-regulator' does not match any of the regexes: '.*-names$' Cc: Krzysztof Kozlowski :wq Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts index f6561766d83f..76262f1e5e03 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts @@ -24,7 +24,7 @@ reg = <0x0 0x20000000>; /* 512MB */ }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts index 67076e1b1c7f..c8f051fb2bf6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -24,7 +24,7 @@ ethernet0 = &gmac1; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 51bb436784e2..253ef139181d 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -50,7 +50,7 @@ }; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index cae9ddd5ed38..3dd99c7c95e0 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -111,7 +111,7 @@ }; }; - regulator_3_3v: vcc3p3-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts index 3f7aa7bf0863..b0003f350e65 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -26,7 +26,7 @@ ethernet0 = &gmac1; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>;