clk: qcom: camcc-sdm845: move clock parent tables down
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211228045415.20543-10-dmitry.baryshkov@linaro.org
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@ -25,22 +25,6 @@ enum {
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P_CAM_CC_PLL3_OUT_EVEN,
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};
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static const struct parent_map cam_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
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{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
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{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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};
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static const char * const cam_cc_parent_names_0[] = {
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"bi_tcxo",
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"cam_cc_pll2_out_even",
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"cam_cc_pll1_out_even",
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"cam_cc_pll3_out_even",
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"cam_cc_pll0_out_even",
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};
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static struct clk_alpha_pll cam_cc_pll0 = {
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.offset = 0x0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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@ -159,6 +143,22 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
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},
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};
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static const struct parent_map cam_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
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{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
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{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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};
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static const char * const cam_cc_parent_names_0[] = {
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"bi_tcxo",
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"cam_cc_pll2_out_even",
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"cam_cc_pll1_out_even",
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"cam_cc_pll3_out_even",
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"cam_cc_pll0_out_even",
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};
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static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
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