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drm/amd/display: Fix null timing generator resource 

[Why]
For some customer blending transition cases, the
available pipe for second stream is a pipe index that is
greater than the number of timing generators, which
can cause a problem in acquire_first_free_pipe since it
assumes same index for pipe and timing generator

[How]
Added logic to use last timing generator index
if the pipe index is greater than number of timing generators.

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Bernstein 2018-07-30 17:43:23 -04:00 committed by Alex Deucher
parent 8bc3812d0b
commit c1127df951
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -1885,6 +1885,12 @@ static int acquire_first_free_pipe(
pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
pipe_ctx->pipe_idx = i;
if (i >= pool->timing_generator_count) {
int tg_inst = pool->timing_generator_count - 1;
pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
pipe_ctx->stream_res.opp = pool->opps[tg_inst];
}
pipe_ctx->stream = stream;
return i;