drm/amd/pm: refine smu 13.0.5 pp table code
Based on smu 13.0.5 features, refine pp table code. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yifan Zhang
Alex Deucher
parent
f728eb3a50
commit
cefbe72496
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@ -57,8 +57,6 @@
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static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
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MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
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MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
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MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1),
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MSG_MAP(DisableGfxOff, PPSMC_MSG_DisableGfxOff, 1),
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MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
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MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
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MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
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@ -227,22 +225,6 @@ static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
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return !!(feature_enabled & SMC_DPM_FEATURE);
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}
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static int smu_v13_0_5_post_smu_init(struct smu_context *smu)
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{
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/*
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struct amdgpu_device *adev = smu->adev;
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*/
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int ret = 0;
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/* allow message will be sent after enable gfxoff on smu 13.0.5 */
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/*
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
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if (ret)
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dev_err(adev->dev, "Failed to Enable GfxOff!\n");
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*/
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return ret;
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}
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static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
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{
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int ret = 0;
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@ -314,30 +296,6 @@ static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
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case METRICS_VOLTAGE_VDDSOC:
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*value = metrics->Voltage[1];
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break;
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#if 0
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case METRICS_SS_APU_SHARE:
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/* return the percentage of APU power with respect to APU's power limit.
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* percentage is reported, this isn't boost value. Smartshift power
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* boost/shift is only when the percentage is more than 100.
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*/
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if (metrics->StapmOpnLimit > 0)
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*value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
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else
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*value = 0;
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break;
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case METRICS_SS_DGPU_SHARE:
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/* return the percentage of dGPU power with respect to dGPU's power limit.
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* percentage is reported, this isn't boost value. Smartshift power
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* boost/shift is only when the percentage is more than 100.
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*/
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if ((metrics->dGpuPower > 0) &&
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(metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
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*value = (metrics->dGpuPower * 100) /
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(metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
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else
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*value = 0;
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break;
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#endif
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default:
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*value = UINT_MAX;
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break;
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@ -503,12 +461,6 @@ static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
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gpu_metrics->temperature_gfx = metrics.GfxTemperature;
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gpu_metrics->temperature_soc = metrics.SocTemperature;
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/*
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memcpy(&gpu_metrics->temperature_core[0],
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&metrics.CoreTemperature[0],
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sizeof(uint16_t) * 8);
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gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
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*/
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gpu_metrics->average_gfx_activity = metrics.GfxActivity;
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gpu_metrics->average_mm_activity = metrics.UvdActivity;
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@ -516,28 +468,13 @@ static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
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gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
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gpu_metrics->average_gfx_power = metrics.Power[0];
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gpu_metrics->average_soc_power = metrics.Power[1];
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/*
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memcpy(&gpu_metrics->average_core_power[0],
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&metrics.CorePower[0],
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sizeof(uint16_t) * 8);
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*/
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gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
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gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
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gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
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gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
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gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
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gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
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/*
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memcpy(&gpu_metrics->current_coreclk[0],
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&metrics.CoreFrequency[0],
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sizeof(uint16_t) * 8);
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gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
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*/
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gpu_metrics->throttle_status = metrics.ThrottlerStatus;
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gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
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*table = (void *)gpu_metrics;
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@ -652,9 +589,11 @@ static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
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case SMU_MCLK:
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member_type = METRICS_AVERAGE_UCLK;
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break;
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case SMU_FCLK:
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case SMU_GFXCLK:
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case SMU_SCLK:
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return smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_GetFclkFrequency, 0, value);
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SMU_MSG_GetGfxclkFrequency, 0, value);
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break;
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default:
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return -EINVAL;
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}
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@ -891,14 +830,6 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
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msg_set_min = SMU_MSG_SetHardMinGfxClk;
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msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
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break;
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case SMU_FCLK:
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msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
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msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
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break;
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case SMU_SOCCLK:
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msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
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msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
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break;
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case SMU_VCLK:
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case SMU_DCLK:
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msg_set_min = SMU_MSG_SetHardMinVcn;
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@ -925,6 +856,7 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
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{
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int i, size = 0, ret = 0;
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uint32_t cur_value = 0, value = 0, count = 0;
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uint32_t min = 0, max = 0;
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smu_cmn_get_sysfs_buf(&buf, &size);
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@ -945,7 +877,6 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
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case SMU_VCLK:
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case SMU_DCLK:
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case SMU_MCLK:
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case SMU_FCLK:
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ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
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if (ret)
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goto print_clk_out;
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@ -963,6 +894,27 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
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cur_value == value ? "*" : "");
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}
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break;
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case SMU_GFXCLK:
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case SMU_SCLK:
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ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
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if (ret)
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goto print_clk_out;
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min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
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max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
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if (cur_value == max)
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i = 2;
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else if (cur_value == min)
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i = 0;
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else
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i = 1;
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size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
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i == 0 ? "*" : "");
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size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
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i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
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i == 1 ? "*" : "");
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size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
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i == 2 ? "*" : "");
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break;
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default:
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break;
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}
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@ -971,6 +923,7 @@ print_clk_out:
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return size;
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}
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static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type, uint32_t mask)
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{
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@ -982,8 +935,6 @@ static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
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soft_max_level = mask ? (fls(mask) - 1) : 0;
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switch (clk_type) {
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case SMU_SOCCLK:
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case SMU_FCLK:
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case SMU_VCLK:
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case SMU_DCLK:
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ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
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@ -1012,31 +963,19 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t sclk_min = 0, sclk_max = 0;
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uint32_t fclk_min = 0, fclk_max = 0;
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uint32_t socclk_min = 0, socclk_max = 0;
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int ret = 0;
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_HIGH:
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
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sclk_min = sclk_max;
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fclk_min = fclk_max;
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socclk_min = socclk_max;
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
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sclk_max = sclk_min;
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fclk_max = fclk_min;
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socclk_max = socclk_min;
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
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smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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@ -1064,24 +1003,6 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
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smu->gfx_actual_soft_max_freq = sclk_max;
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}
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if (fclk_min && fclk_max) {
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ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
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SMU_FCLK,
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fclk_min,
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fclk_max);
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if (ret)
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return ret;
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}
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if (socclk_min && socclk_max) {
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ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
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SMU_SOCCLK,
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socclk_min,
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socclk_max);
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if (ret)
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return ret;
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}
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return ret;
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}
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@ -1117,7 +1038,6 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
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.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
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.set_driver_table_location = smu_v13_0_set_driver_table_location,
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.gfx_off_control = smu_v13_0_gfx_off_control,
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.post_init = smu_v13_0_5_post_smu_init,
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.mode2_reset = smu_v13_0_5_mode2_reset,
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.get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
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.od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
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@ -24,5 +24,6 @@
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#define __SMU_V13_0_5_PPT_H__
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extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);
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#define SMU_13_0_5_UMD_PSTATE_GFXCLK 1100
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#endif
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