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Merge branch 'topic/vmaster-update' into topic/docbook-fix

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This commit is contained in:
Takashi Iwai
2009-03-09 15:21:57 +01:00
parent 33dbe61140 79c7cdd544
commit efdcd41b4e
3052 changed files with 100994 additions and 38430 deletions
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2
include/acpi/actbl.h
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@@ -245,7 +245,7 @@ struct acpi_table_fadt {
#define ACPI_FADT_POWER_BUTTON (1<<4) /* 04: Power button is handled as a generic feature */
#define ACPI_FADT_SLEEP_BUTTON (1<<5) /* 05: Sleep button is handled as a generic feature, or not present */
#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: RTC wakeup stat not in fixed register space */
#define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: RTC wakeup stat not possible from S4 */
#define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: RTC wakeup possible from S4 */
#define ACPI_FADT_32BIT_TIMER (1<<8) /* 08: tmr_val is 32 bits 0=24-bits */
#define ACPI_FADT_DOCKING_SUPPORTED (1<<9) /* 09: Docking supported */
#define ACPI_FADT_RESET_REGISTER (1<<10) /* 10: System reset via the FADT RESET_REG supported */

2
include/acpi/pdc_intel.h
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@@ -14,6 +14,7 @@
#define ACPI_PDC_SMP_T_SWCOORD (0x0080)
#define ACPI_PDC_C_C1_FFH (0x0100)
#define ACPI_PDC_C_C2C3_FFH (0x0200)
#define ACPI_PDC_SMP_P_HWCOORD (0x0800)
#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
ACPI_PDC_C_C1_HALT | \
@@ -22,6 +23,7 @@
#define ACPI_PDC_EST_CAPABILITY_SWSMP (ACPI_PDC_SMP_C1PT | \
ACPI_PDC_C_C1_HALT | \
ACPI_PDC_SMP_P_SWCOORD | \
ACPI_PDC_SMP_P_HWCOORD | \
ACPI_PDC_P_FFH)
#define ACPI_PDC_C_CAPABILITY_SMP (ACPI_PDC_SMP_C2C3 | \

1
include/asm-frv/Kbuild
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@@ -3,4 +3,3 @@ include include/asm-generic/Kbuild.asm
header-y += registers.h
unifdef-y += termios.h
unifdef-y += swab.h

1
include/asm-frv/byteorder.h
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@@ -1,7 +1,6 @@
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
#include <asm/swab.h>
#include <linux/byteorder/big_endian.h>
#endif /* _ASM_BYTEORDER_H */

2
include/asm-frv/pgtable.h
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@@ -478,7 +478,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
#define __swp_type(x) (((x).val >> 2) & 0x1f)
#define __swp_offset(x) ((x).val >> 8)
#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 8) })
#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte })
#define __pte_to_swp_entry(_pte) ((swp_entry_t) { (_pte).pte })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
static inline int pte_file(pte_t pte)

1
include/asm-generic/Kbuild.asm
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@@ -31,6 +31,7 @@ unifdef-y += socket.h
unifdef-y += sockios.h
unifdef-y += stat.h
unifdef-y += statfs.h
unifdef-y += swab.h
unifdef-y += termbits.h
unifdef-y += termios.h
unifdef-y += types.h

2
include/asm-generic/bitops/__ffs.h
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@@ -9,7 +9,7 @@
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline unsigned long __ffs(unsigned long word)
static __always_inline unsigned long __ffs(unsigned long word)
{
int num = 0;

2
include/asm-generic/bitops/__fls.h
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@@ -9,7 +9,7 @@
*
* Undefined if no set bit exists, so code should check against 0 first.
*/
static inline unsigned long __fls(unsigned long word)
static __always_inline unsigned long __fls(unsigned long word)
{
int num = BITS_PER_LONG - 1;

2
include/asm-generic/bitops/fls.h
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@@ -9,7 +9,7 @@
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static inline int fls(int x)
static __always_inline int fls(int x)
{
int r = 32;

4
include/asm-generic/bitops/fls64.h
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@@ -15,7 +15,7 @@
* at position 64.
*/
#if BITS_PER_LONG == 32
static inline int fls64(__u64 x)
static __always_inline int fls64(__u64 x)
{
__u32 h = x >> 32;
if (h)
@@ -23,7 +23,7 @@ static inline int fls64(__u64 x)
return fls(x);
}
#elif BITS_PER_LONG == 64
static inline int fls64(__u64 x)
static __always_inline int fls64(__u64 x)
{
if (x == 0)
return 0;

4
include/asm-generic/pgtable.h
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@@ -301,7 +301,7 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm,
* track_pfn_vma_new is called when a _new_ pfn mapping is being established
* for physical range indicated by pfn and size.
*/
static inline int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot,
static inline int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot,
unsigned long pfn, unsigned long size)
{
return 0;
@@ -332,7 +332,7 @@ static inline void untrack_pfn_vma(struct vm_area_struct *vma,
{
}
#else
extern int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot,
extern int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot,
unsigned long pfn, unsigned long size);
extern int track_pfn_vma_copy(struct vm_area_struct *vma);
extern void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn,

14
include/asm-generic/rtc.h
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@@ -42,7 +42,7 @@ static inline unsigned char rtc_is_updating(void)
return uip;
}
static inline unsigned int get_rtc_time(struct rtc_time *time)
static inline unsigned int __get_rtc_time(struct rtc_time *time)
{
unsigned char ctrl;
unsigned long flags;
@@ -108,8 +108,12 @@ static inline unsigned int get_rtc_time(struct rtc_time *time)
return RTC_24H;
}
#ifndef get_rtc_time
#define get_rtc_time __get_rtc_time
#endif
/* Set the current date and time in the real time clock. */
static inline int set_rtc_time(struct rtc_time *time)
static inline int __set_rtc_time(struct rtc_time *time)
{
unsigned long flags;
unsigned char mon, day, hrs, min, sec;
@@ -190,11 +194,15 @@ static inline int set_rtc_time(struct rtc_time *time)
return 0;
}
#ifndef set_rtc_time
#define set_rtc_time __set_rtc_time
#endif
static inline unsigned int get_rtc_ss(void)
{
struct rtc_time h;
get_rtc_time(&h);
__get_rtc_time(&h);
return h.tm_sec;
}

1
include/asm-m32r/Kbuild
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@@ -1,2 +1 @@
include include/asm-generic/Kbuild.asm
unifdef-y += swab.h

2
include/asm-m32r/byteorder.h
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@@ -1,8 +1,6 @@
#ifndef _ASM_M32R_BYTEORDER_H
#define _ASM_M32R_BYTEORDER_H
#include <asm/swab.h>
#if defined(__LITTLE_ENDIAN__)
# include <linux/byteorder/little_endian.h>
#else

3
include/asm-m68k/Kbuild
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@@ -1,3 +0,0 @@
include include/asm-generic/Kbuild.asm
header-y += cachectl.h
unifdef-y += swab.h

67
include/asm-m68k/a.out-core.h
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@@ -1,67 +0,0 @@
/* a.out coredump register dumper
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_A_OUT_CORE_H
#define _ASM_A_OUT_CORE_H
#ifdef __KERNEL__
#include <linux/user.h>
#include <linux/elfcore.h>
/*
* fill in the user structure for an a.out core dump
*/
static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
{
struct switch_stack *sw;
/* changed the size calculations - should hopefully work better. lbt */
dump->magic = CMAGIC;
dump->start_code = 0;
dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
dump->u_dsize = ((unsigned long) (current->mm->brk +
(PAGE_SIZE-1))) >> PAGE_SHIFT;
dump->u_dsize -= dump->u_tsize;
dump->u_ssize = 0;
if (dump->start_stack < TASK_SIZE)
dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
dump->u_ar0 = offsetof(struct user, regs);
sw = ((struct switch_stack *)regs) - 1;
dump->regs.d1 = regs->d1;
dump->regs.d2 = regs->d2;
dump->regs.d3 = regs->d3;
dump->regs.d4 = regs->d4;
dump->regs.d5 = regs->d5;
dump->regs.d6 = sw->d6;
dump->regs.d7 = sw->d7;
dump->regs.a0 = regs->a0;
dump->regs.a1 = regs->a1;
dump->regs.a2 = regs->a2;
dump->regs.a3 = sw->a3;
dump->regs.a4 = sw->a4;
dump->regs.a5 = sw->a5;
dump->regs.a6 = sw->a6;
dump->regs.d0 = regs->d0;
dump->regs.orig_d0 = regs->orig_d0;
dump->regs.stkadj = regs->stkadj;
dump->regs.sr = regs->sr;
dump->regs.pc = regs->pc;
dump->regs.fmtvec = (regs->format << 12) | regs->vector;
/* dump floating point stuff */
dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
}
#endif /* __KERNEL__ */
#endif /* _ASM_A_OUT_CORE_H */

20
include/asm-m68k/a.out.h
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@@ -1,20 +0,0 @@
#ifndef __M68K_A_OUT_H__
#define __M68K_A_OUT_H__
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#endif /* __M68K_A_OUT_H__ */

44
include/asm-m68k/adb_iop.h
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@@ -1,44 +0,0 @@
/*
* ADB through the IOP
* Written by Joshua M. Thompson
*/
/* IOP number and channel number for ADB */
#define ADB_IOP IOP_NUM_ISM
#define ADB_CHAN 2
/* From the A/UX headers...maybe important, maybe not */
#define ADB_IOP_LISTEN 0x01
#define ADB_IOP_TALK 0x02
#define ADB_IOP_EXISTS 0x04
#define ADB_IOP_FLUSH 0x08
#define ADB_IOP_RESET 0x10
#define ADB_IOP_INT 0x20
#define ADB_IOP_POLL 0x40
#define ADB_IOP_UNINT 0x80
#define AIF_RESET 0x00
#define AIF_FLUSH 0x01
#define AIF_LISTEN 0x08
#define AIF_TALK 0x0C
/* Flag bits in struct adb_iopmsg */
#define ADB_IOP_EXPLICIT 0x80 /* nonzero if explicit command */
#define ADB_IOP_AUTOPOLL 0x40 /* auto/SRQ polling enabled */
#define ADB_IOP_SRQ 0x04 /* SRQ detected */
#define ADB_IOP_TIMEOUT 0x02 /* nonzero if timeout */
#ifndef __ASSEMBLY__
struct adb_iopmsg {
__u8 flags; /* ADB flags */
__u8 count; /* no. of data bytes */
__u8 cmd; /* ADB command */
__u8 data[8]; /* ADB data */
__u8 spare[21]; /* spare */
};
#endif /* __ASSEMBLY__ */

350
include/asm-m68k/amigahw.h
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@@ -1,350 +0,0 @@
/*
** asm-m68k/amigahw.h -- This header defines some macros and pointers for
** the various Amiga custom hardware registers.
** The naming conventions used here conform to those
** used in the Amiga Hardware Reference Manual, 3rd Edition
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 9/24/92 by Greg Harp
*/
#ifndef _M68K_AMIGAHW_H
#define _M68K_AMIGAHW_H
#include <linux/ioport.h>
/*
* Different Amiga models
*/
#define AMI_UNKNOWN (0)
#define AMI_500 (1)
#define AMI_500PLUS (2)
#define AMI_600 (3)
#define AMI_1000 (4)
#define AMI_1200 (5)
#define AMI_2000 (6)
#define AMI_2500 (7)
#define AMI_3000 (8)
#define AMI_3000T (9)
#define AMI_3000PLUS (10)
#define AMI_4000 (11)
#define AMI_4000T (12)
#define AMI_CDTV (13)
#define AMI_CD32 (14)
#define AMI_DRACO (15)
/*
* Chipsets
*/
extern unsigned long amiga_chipset;
#define CS_STONEAGE (0)
#define CS_OCS (1)
#define CS_ECS (2)
#define CS_AGA (3)
/*
* Miscellaneous
*/
extern unsigned long amiga_eclock; /* 700 kHz E Peripheral Clock */
extern unsigned long amiga_colorclock; /* 3.5 MHz Color Clock */
extern unsigned long amiga_chip_size; /* Chip RAM Size (bytes) */
extern unsigned char amiga_vblank; /* VBLANK Frequency */
#define AMIGAHW_DECLARE(name) unsigned name : 1
#define AMIGAHW_SET(name) (amiga_hw_present.name = 1)
#define AMIGAHW_PRESENT(name) (amiga_hw_present.name)
struct amiga_hw_present {
/* video hardware */
AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */
AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */
AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */
/* sound hardware */
AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */
/* disk storage interfaces */
AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */
AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */
AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */
AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */
AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */
AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */
/* other I/O hardware */
AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */
AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */
AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */
AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */
/* real time clocks */
AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */
AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */
/* supporting hardware */
AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */
AMIGAHW_DECLARE(PAULA); /* Paula (8364) */
AMIGAHW_DECLARE(DENISE); /* Denise (8362) */
AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */
AMIGAHW_DECLARE(LISA); /* Lisa (8375) */
AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */
AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */
AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */
AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */
AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */
AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */
AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */
AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */
AMIGAHW_DECLARE(GG2_ISA); /* GG2 Zorro2ISA Bridge */
AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */
AMIGAHW_DECLARE(ZORRO3); /* Zorro III */
};
extern struct amiga_hw_present amiga_hw_present;
struct CUSTOM {
unsigned short bltddat;
unsigned short dmaconr;
unsigned short vposr;
unsigned short vhposr;
unsigned short dskdatr;
unsigned short joy0dat;
unsigned short joy1dat;
unsigned short clxdat;
unsigned short adkconr;
unsigned short pot0dat;
unsigned short pot1dat;
unsigned short potgor;
unsigned short serdatr;
unsigned short dskbytr;
unsigned short intenar;
unsigned short intreqr;
unsigned char *dskptr;
unsigned short dsklen;
unsigned short dskdat;
unsigned short refptr;
unsigned short vposw;
unsigned short vhposw;
unsigned short copcon;
unsigned short serdat;
unsigned short serper;
unsigned short potgo;
unsigned short joytest;
unsigned short strequ;
unsigned short strvbl;
unsigned short strhor;
unsigned short strlong;
unsigned short bltcon0;
unsigned short bltcon1;
unsigned short bltafwm;
unsigned short bltalwm;
unsigned char *bltcpt;
unsigned char *bltbpt;
unsigned char *bltapt;
unsigned char *bltdpt;
unsigned short bltsize;
unsigned char pad2d;
unsigned char bltcon0l;
unsigned short bltsizv;
unsigned short bltsizh;
unsigned short bltcmod;
unsigned short bltbmod;
unsigned short bltamod;
unsigned short bltdmod;
unsigned short spare2[4];
unsigned short bltcdat;
unsigned short bltbdat;
unsigned short bltadat;
unsigned short spare3[3];
unsigned short deniseid;
unsigned short dsksync;
unsigned short *cop1lc;
unsigned short *cop2lc;
unsigned short copjmp1;
unsigned short copjmp2;
unsigned short copins;
unsigned short diwstrt;
unsigned short diwstop;
unsigned short ddfstrt;
unsigned short ddfstop;
unsigned short dmacon;
unsigned short clxcon;
unsigned short intena;
unsigned short intreq;
unsigned short adkcon;
struct {
unsigned short *audlc;
unsigned short audlen;
unsigned short audper;
unsigned short audvol;
unsigned short auddat;
unsigned short audspare[2];
} aud[4];
unsigned char *bplpt[8];
unsigned short bplcon0;
unsigned short bplcon1;
unsigned short bplcon2;
unsigned short bplcon3;
unsigned short bpl1mod;
unsigned short bpl2mod;
unsigned short bplcon4;
unsigned short clxcon2;
unsigned short bpldat[8];
unsigned char *sprpt[8];
struct {
unsigned short pos;
unsigned short ctl;
unsigned short dataa;
unsigned short datab;
} spr[8];
unsigned short color[32];
unsigned short htotal;
unsigned short hsstop;
unsigned short hbstrt;
unsigned short hbstop;
unsigned short vtotal;
unsigned short vsstop;
unsigned short vbstrt;
unsigned short vbstop;
unsigned short sprhstrt;
unsigned short sprhstop;
unsigned short bplhstrt;
unsigned short bplhstop;
unsigned short hhposw;
unsigned short hhposr;
unsigned short beamcon0;
unsigned short hsstrt;
unsigned short vsstrt;
unsigned short hcenter;
unsigned short diwhigh;
unsigned short spare4[11];
unsigned short fmode;
};
/*
* DMA register bits
*/
#define DMAF_SETCLR (0x8000)
#define DMAF_AUD0 (0x0001)
#define DMAF_AUD1 (0x0002)
#define DMAF_AUD2 (0x0004)
#define DMAF_AUD3 (0x0008)
#define DMAF_DISK (0x0010)
#define DMAF_SPRITE (0x0020)
#define DMAF_BLITTER (0x0040)
#define DMAF_COPPER (0x0080)
#define DMAF_RASTER (0x0100)
#define DMAF_MASTER (0x0200)
#define DMAF_BLITHOG (0x0400)
#define DMAF_BLTNZERO (0x2000)
#define DMAF_BLTDONE (0x4000)
#define DMAF_ALL (0x01FF)
struct CIA {
unsigned char pra; char pad0[0xff];
unsigned char prb; char pad1[0xff];
unsigned char ddra; char pad2[0xff];
unsigned char ddrb; char pad3[0xff];
unsigned char talo; char pad4[0xff];
unsigned char tahi; char pad5[0xff];
unsigned char tblo; char pad6[0xff];
unsigned char tbhi; char pad7[0xff];
unsigned char todlo; char pad8[0xff];
unsigned char todmid; char pad9[0xff];
unsigned char todhi; char pada[0x1ff];
unsigned char sdr; char padb[0xff];
unsigned char icr; char padc[0xff];
unsigned char cra; char padd[0xff];
unsigned char crb; char pade[0xff];
};
#define zTwoBase (0x80000000)
#define ZTWO_PADDR(x) (((unsigned long)(x))-zTwoBase)
#define ZTWO_VADDR(x) (((unsigned long)(x))+zTwoBase)
#define CUSTOM_PHYSADDR (0xdff000)
#define amiga_custom ((*(volatile struct CUSTOM *)(zTwoBase+CUSTOM_PHYSADDR)))
#define CIAA_PHYSADDR (0xbfe001)
#define CIAB_PHYSADDR (0xbfd000)
#define ciaa ((*(volatile struct CIA *)(zTwoBase + CIAA_PHYSADDR)))
#define ciab ((*(volatile struct CIA *)(zTwoBase + CIAB_PHYSADDR)))
#define CHIP_PHYSADDR (0x000000)
void amiga_chip_init (void);
void *amiga_chip_alloc(unsigned long size, const char *name);
void *amiga_chip_alloc_res(unsigned long size, struct resource *res);
void amiga_chip_free(void *ptr);
unsigned long amiga_chip_avail( void ); /*MILAN*/
extern volatile unsigned short amiga_audio_min_period;
static inline void amifb_video_off(void)
{
if (amiga_chipset == CS_ECS || amiga_chipset == CS_AGA) {
/* program Denise/Lisa for a higher maximum play rate */
amiga_custom.htotal = 113; /* 31 kHz */
amiga_custom.vtotal = 223; /* 70 Hz */
amiga_custom.beamcon0 = 0x4390; /* HARDDIS, VAR{BEAM,VSY,HSY,CSY}EN */
/* suspend the monitor */
amiga_custom.hsstrt = amiga_custom.hsstop = 116;
amiga_custom.vsstrt = amiga_custom.vsstop = 226;
amiga_audio_min_period = 57;
}
}
struct tod3000 {
unsigned int :28, second2:4; /* lower digit */
unsigned int :28, second1:4; /* upper digit */
unsigned int :28, minute2:4; /* lower digit */
unsigned int :28, minute1:4; /* upper digit */
unsigned int :28, hour2:4; /* lower digit */
unsigned int :28, hour1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, day2:4; /* lower digit */
unsigned int :28, day1:4; /* upper digit */
unsigned int :28, month2:4; /* lower digit */
unsigned int :28, month1:4; /* upper digit */
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, cntrl1:4; /* control-byte 1 */
unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD3000_CNTRL1_HOLD 0
#define TOD3000_CNTRL1_FREE 9
#define tod_3000 ((*(volatile struct tod3000 *)(zTwoBase+0xDC0000)))
struct tod2000 {
unsigned int :28, second2:4; /* lower digit */
unsigned int :28, second1:4; /* upper digit */
unsigned int :28, minute2:4; /* lower digit */
unsigned int :28, minute1:4; /* upper digit */
unsigned int :28, hour2:4; /* lower digit */
unsigned int :28, hour1:4; /* upper digit */
unsigned int :28, day2:4; /* lower digit */
unsigned int :28, day1:4; /* upper digit */
unsigned int :28, month2:4; /* lower digit */
unsigned int :28, month1:4; /* upper digit */
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, cntrl1:4; /* control-byte 1 */
unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD2000_CNTRL1_HOLD (1<<0)
#define TOD2000_CNTRL1_BUSY (1<<1)
#define TOD2000_CNTRL3_24HMODE (1<<2)
#define TOD2000_HOUR1_PM (1<<2)
#define tod_2000 ((*(volatile struct tod2000 *)(zTwoBase+0xDC0000)))
#endif /* _M68K_AMIGAHW_H */

113
include/asm-m68k/amigaints.h
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/*
** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 10/2/92 by Greg Harp
*/
#ifndef _ASMm68k_AMIGAINTS_H_
#define _ASMm68k_AMIGAINTS_H_
#include <asm/irq.h>
/*
** Amiga Interrupt sources.
**
*/
#define AUTO_IRQS (8)
#define AMI_STD_IRQS (14)
#define CIA_IRQS (5)
#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
/* builtin serial port interrupts */
#define IRQ_AMIGA_TBE (IRQ_USER+0)
#define IRQ_AMIGA_RBF (IRQ_USER+11)
/* floppy disk interrupts */
#define IRQ_AMIGA_DSKBLK (IRQ_USER+1)
#define IRQ_AMIGA_DSKSYN (IRQ_USER+12)
/* software interrupts */
#define IRQ_AMIGA_SOFT (IRQ_USER+2)
/* interrupts from external hardware */
#define IRQ_AMIGA_PORTS IRQ_AUTO_2
#define IRQ_AMIGA_EXTER IRQ_AUTO_6
/* copper interrupt */
#define IRQ_AMIGA_COPPER (IRQ_USER+4)
/* vertical blanking interrupt */
#define IRQ_AMIGA_VERTB (IRQ_USER+5)
/* Blitter done interrupt */
#define IRQ_AMIGA_BLIT (IRQ_USER+6)
/* Audio interrupts */
#define IRQ_AMIGA_AUD0 (IRQ_USER+7)
#define IRQ_AMIGA_AUD1 (IRQ_USER+8)
#define IRQ_AMIGA_AUD2 (IRQ_USER+9)
#define IRQ_AMIGA_AUD3 (IRQ_USER+10)
/* CIA interrupt sources */
#define IRQ_AMIGA_CIAA (IRQ_USER+14)
#define IRQ_AMIGA_CIAA_TA (IRQ_USER+14)
#define IRQ_AMIGA_CIAA_TB (IRQ_USER+15)
#define IRQ_AMIGA_CIAA_ALRM (IRQ_USER+16)
#define IRQ_AMIGA_CIAA_SP (IRQ_USER+17)
#define IRQ_AMIGA_CIAA_FLG (IRQ_USER+18)
#define IRQ_AMIGA_CIAB (IRQ_USER+19)
#define IRQ_AMIGA_CIAB_TA (IRQ_USER+19)
#define IRQ_AMIGA_CIAB_TB (IRQ_USER+20)
#define IRQ_AMIGA_CIAB_ALRM (IRQ_USER+21)
#define IRQ_AMIGA_CIAB_SP (IRQ_USER+22)
#define IRQ_AMIGA_CIAB_FLG (IRQ_USER+23)
/* INTREQR masks */
#define IF_SETCLR 0x8000 /* set/clr bit */
#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
#define IF_DSKSYN 0x1000 /* disk sync interrupt */
#define IF_RBF 0x0800 /* serial receive buffer full interrupt */
#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
#define IF_BLIT 0x0040 /* blitter done interrupt */
#define IF_VERTB 0x0020 /* vertical blanking interrupt */
#define IF_COPER 0x0010 /* copper interrupt */
#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
#define IF_SOFT 0x0004 /* software initiated interrupt */
#define IF_DSKBLK 0x0002 /* diskblock DMA finished */
#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
/* CIA interrupt control register bits */
#define CIA_ICR_TA 0x01
#define CIA_ICR_TB 0x02
#define CIA_ICR_ALRM 0x04
#define CIA_ICR_SP 0x08
#define CIA_ICR_FLG 0x10
#define CIA_ICR_ALL 0x1f
#define CIA_ICR_SETCLR 0x80
extern void amiga_init_IRQ(void);
/* to access the interrupt control registers of CIA's use only
** these functions, they behave exactly like the amiga os routines
*/
extern struct ciabase ciaa_base, ciab_base;
extern void cia_init_IRQ(struct ciabase *base);
extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask);
extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask);
#endif /* asm-m68k/amigaints.h */

107
include/asm-m68k/amigayle.h
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/*
** asm-m68k/amigayle.h -- This header defines the registers of the gayle chip
** found on the Amiga 1200
** This information was found by disassembling card.resource,
** so the definitions may not be 100% correct
** anyone has an official doc ?
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 11/28/97 by Alain Malek
*/
#ifndef _M68K_AMIGAYLE_H_
#define _M68K_AMIGAYLE_H_
#include <linux/types.h>
#include <asm/amigahw.h>
/* memory layout */
#define GAYLE_RAM (0x600000+zTwoBase)
#define GAYLE_RAMSIZE (0x400000)
#define GAYLE_ATTRIBUTE (0xa00000+zTwoBase)
#define GAYLE_ATTRIBUTESIZE (0x020000)
#define GAYLE_IO (0xa20000+zTwoBase) /* 16bit and even 8bit registers */
#define GAYLE_IOSIZE (0x010000)
#define GAYLE_IO_8BITODD (0xa30000+zTwoBase) /* odd 8bit registers */
/* offset for accessing odd IO registers */
#define GAYLE_ODD (GAYLE_IO_8BITODD-GAYLE_IO-1)
/* GAYLE registers */
struct GAYLE {
u_char cardstatus;
u_char pad0[0x1000-1];
u_char intreq;
u_char pad1[0x1000-1];
u_char inten;
u_char pad2[0x1000-1];
u_char config;
u_char pad3[0x1000-1];
};
#define GAYLE_ADDRESS (0xda8000) /* gayle main registers base address */
#define GAYLE_RESET (0xa40000) /* write 0x00 to start reset,
read 1 byte to stop reset */
#define gayle (*(volatile struct GAYLE *)(zTwoBase+GAYLE_ADDRESS))
#define gayle_reset (*(volatile u_char *)(zTwoBase+GAYLE_RESET))
#define gayle_attribute ((volatile u_char *)(GAYLE_ATTRIBUTE))
#if 0
#define gayle_inb(a) readb( GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
#define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
#define gayle_inw(a) readw( GAYLE_IO+(a) )
#define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
#endif
/* GAYLE_CARDSTATUS bit def */
#define GAYLE_CS_CCDET 0x40 /* credit card detect */
#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
#define GAYLE_CS_SC 0x20 /* credit card status change */
#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
#define GAYLE_CS_DA 0x10 /* digital audio */
#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
#define GAYLE_CS_BSY 0x04 /* credit card busy */
#define GAYLE_CS_IRQ 0x04 /* interrupt request */
/* GAYLE_IRQ bit def */
#define GAYLE_IRQ_IDE 0x80
#define GAYLE_IRQ_CCDET 0x40
#define GAYLE_IRQ_BVD1 0x20
#define GAYLE_IRQ_SC 0x20
#define GAYLE_IRQ_BVD2 0x10
#define GAYLE_IRQ_DA 0x10
#define GAYLE_IRQ_WR 0x08
#define GAYLE_IRQ_BSY 0x04
#define GAYLE_IRQ_IRQ 0x04
#define GAYLE_IRQ_IDEACK1 0x02
#define GAYLE_IRQ_IDEACK0 0x01
/* GAYLE_CONFIG bit def
(bit 0-1 for program voltage, bit 2-3 for access speed */
#define GAYLE_CFG_0V 0x00
#define GAYLE_CFG_5V 0x01
#define GAYLE_CFG_12V 0x02
#define GAYLE_CFG_100NS 0x08
#define GAYLE_CFG_150NS 0x04
#define GAYLE_CFG_250NS 0x00
#define GAYLE_CFG_720NS 0x0c
#endif /* asm-m68k/amigayle.h */

110
include/asm-m68k/amipcmcia.h
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/*
** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 12/10/97 by Alain Malek
*/
#ifndef __AMIGA_PCMCIA_H__
#define __AMIGA_PCMCIA_H__
#include <asm/amigayle.h>
/* prototypes */
void pcmcia_reset(void);
int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len);
void pcmcia_program_voltage(int voltage);
void pcmcia_access_speed(int speed);
void pcmcia_write_enable(void);
void pcmcia_write_disable(void);
static inline u_char pcmcia_read_status(void)
{
return (gayle.cardstatus & 0x7c);
}
static inline u_char pcmcia_get_intreq(void)
{
return (gayle.intreq);
}
static inline void pcmcia_ack_int(u_char intreq)
{
gayle.intreq = 0xf8;
}
static inline void pcmcia_enable_irq(void)
{
gayle.inten |= GAYLE_IRQ_IRQ;
}
static inline void pcmcia_disable_irq(void)
{
gayle.inten &= ~GAYLE_IRQ_IRQ;
}
#define PCMCIA_INSERTED (gayle.cardstatus & GAYLE_CS_CCDET)
/* valid voltages for pcmcia_ProgramVoltage */
#define PCMCIA_0V 0
#define PCMCIA_5V 5
#define PCMCIA_12V 12
/* valid speeds for pcmcia_AccessSpeed */
#define PCMCIA_SPEED_100NS 100
#define PCMCIA_SPEED_150NS 150
#define PCMCIA_SPEED_250NS 250
#define PCMCIA_SPEED_720NS 720
/* PCMCIA Tuple codes */
#define CISTPL_NULL 0x00
#define CISTPL_DEVICE 0x01
#define CISTPL_LONGLINK_CB 0x02
#define CISTPL_CONFIG_CB 0x04
#define CISTPL_CFTABLE_ENTRY_CB 0x05
#define CISTPL_LONGLINK_MFC 0x06
#define CISTPL_BAR 0x07
#define CISTPL_CHECKSUM 0x10
#define CISTPL_LONGLINK_A 0x11
#define CISTPL_LONGLINK_C 0x12
#define CISTPL_LINKTARGET 0x13
#define CISTPL_NO_LINK 0x14
#define CISTPL_VERS_1 0x15
#define CISTPL_ALTSTR 0x16
#define CISTPL_DEVICE_A 0x17
#define CISTPL_JEDEC_C 0x18
#define CISTPL_JEDEC_A 0x19
#define CISTPL_CONFIG 0x1a
#define CISTPL_CFTABLE_ENTRY 0x1b
#define CISTPL_DEVICE_OC 0x1c
#define CISTPL_DEVICE_OA 0x1d
#define CISTPL_DEVICE_GEO 0x1e
#define CISTPL_DEVICE_GEO_A 0x1f
#define CISTPL_MANFID 0x20
#define CISTPL_FUNCID 0x21
#define CISTPL_FUNCE 0x22
#define CISTPL_SWIL 0x23
#define CISTPL_END 0xff
/* FUNCID */
#define CISTPL_FUNCID_MULTI 0x00
#define CISTPL_FUNCID_MEMORY 0x01
#define CISTPL_FUNCID_SERIAL 0x02
#define CISTPL_FUNCID_PARALLEL 0x03
#define CISTPL_FUNCID_FIXED 0x04
#define CISTPL_FUNCID_VIDEO 0x05
#define CISTPL_FUNCID_NETWORK 0x06
#define CISTPL_FUNCID_AIMS 0x07
#define CISTPL_FUNCID_SCSI 0x08
#endif

248
include/asm-m68k/apollodma.h
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/*
* linux/include/asm/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
*/
#ifndef _ASM_APOLLO_DMA_H
#define _ASM_APOLLO_DMA_H
#include <asm/apollohw.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
#define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE)))
/*
* NOTES about DMA transfers:
*
* controller 1: channels 0-3, byte operations, ports 00-1F
* controller 2: channels 4-7, word operations, ports C0-DF
*
* - ALL registers are 8 bits only, regardless of transfer size
* - channel 4 is not used - cascades 1 into 2.
* - channels 0-3 are byte - addresses/counts are for physical bytes
* - channels 5-7 are word - addresses/counts are for physical words
* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
* - transfer count loaded to registers is 1 less than actual count
* - controller 2 offsets are all even (2x offsets for controller 1)
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
* DMA transfers are limited to the lower 16MB of _physical_ memory.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
* Address mapping for channels 0-3:
*
* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
*
* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
* the hardware level, so odd-byte transfers aren't possible).
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
* and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
#define MAX_DMA_CHANNELS 8
/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */
#define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */
#define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */
#define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
#define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */
#define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
#define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
#define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */
#define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
#define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
#define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
#define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
#define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
#define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
#define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
#define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
#define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */
#define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
#define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */
#define DMA_ADDR_1 (IO_DMA1_BASE+0x02)
#define DMA_ADDR_2 (IO_DMA1_BASE+0x04)
#define DMA_ADDR_3 (IO_DMA1_BASE+0x06)
#define DMA_ADDR_4 (IO_DMA2_BASE+0x00)
#define DMA_ADDR_5 (IO_DMA2_BASE+0x04)
#define DMA_ADDR_6 (IO_DMA2_BASE+0x08)
#define DMA_ADDR_7 (IO_DMA2_BASE+0x0C)
#define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */
#define DMA_CNT_1 (IO_DMA1_BASE+0x03)
#define DMA_CNT_2 (IO_DMA1_BASE+0x05)
#define DMA_CNT_3 (IO_DMA1_BASE+0x07)
#define DMA_CNT_4 (IO_DMA2_BASE+0x02)
#define DMA_CNT_5 (IO_DMA2_BASE+0x06)
#define DMA_CNT_6 (IO_DMA2_BASE+0x0A)
#define DMA_CNT_7 (IO_DMA2_BASE+0x0E)
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
#define DMA_8BIT 0
#define DMA_16BIT 1
#define DMA_BUSMASTER 2
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr, DMA1_MASK_REG);
else
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
static __inline__ void disable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(0, DMA1_CLEAR_FF_REG);
else
dma_outb(0, DMA2_CLEAR_FF_REG);
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
if (dmanr<=3)
dma_outb(mode | dmanr, DMA1_MODE_REG);
else
dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
if (dmanr <= 3) {
dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
} else {
dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
}
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
} else {
dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr<=3)? count : (count<<1);
}
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
/* These are in arch/m68k/apollo/dma.c: */
extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
extern void dma_unmap_page(unsigned short dma_addr);
#endif /* _ASM_APOLLO_DMA_H */

108
include/asm-m68k/apollohw.h
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/* apollohw.h : some structures to access apollo HW */
#ifndef _ASMm68k_APOLLOHW_H_
#define _ASMm68k_APOLLOHW_H_
#include <linux/types.h>
/*
apollo models
*/
extern u_long apollo_model;
#define APOLLO_UNKNOWN (0)
#define APOLLO_DN3000 (1)
#define APOLLO_DN3010 (2)
#define APOLLO_DN3500 (3)
#define APOLLO_DN4000 (4)
#define APOLLO_DN4500 (5)
/*
see scn2681 data sheet for more info.
member names are read_write.
*/
#define DECLARE_2681_FIELD(x) unsigned char x; unsigned char dummy##x
struct SCN2681 {
DECLARE_2681_FIELD(mra);
DECLARE_2681_FIELD(sra_csra);
DECLARE_2681_FIELD(BRGtest_cra);
DECLARE_2681_FIELD(rhra_thra);
DECLARE_2681_FIELD(ipcr_acr);
DECLARE_2681_FIELD(isr_imr);
DECLARE_2681_FIELD(ctu_ctur);
DECLARE_2681_FIELD(ctl_ctlr);
DECLARE_2681_FIELD(mrb);
DECLARE_2681_FIELD(srb_csrb);
DECLARE_2681_FIELD(tst_crb);
DECLARE_2681_FIELD(rhrb_thrb);
DECLARE_2681_FIELD(reserved);
DECLARE_2681_FIELD(ip_opcr);
DECLARE_2681_FIELD(startCnt_setOutBit);
DECLARE_2681_FIELD(stopCnt_resetOutBit);
};
#if 0
struct mc146818 {
unsigned int second1:4, second2:4, alarm_second1:4, alarm_second2:4,
minute1:4, minute2:4, alarm_minute1:4, alarm_minute2:4;
unsigned int hours1:4, hours2:4, alarm_hours1:4, alarm_hours2:4,
day_of_week1:4, day_of_week2:4, day_of_month1:4, day_of_month2:4;
unsigned int month1:4, month2:4, year1:4, year2:4, :16;
};
#endif
struct mc146818 {
unsigned char second, alarm_second;
unsigned char minute, alarm_minute;
unsigned char hours, alarm_hours;
unsigned char day_of_week, day_of_month;
unsigned char month, year;
};
#define IO_BASE 0x80000000
extern u_long sio01_physaddr;
extern u_long sio23_physaddr;
extern u_long rtc_physaddr;
extern u_long pica_physaddr;
extern u_long picb_physaddr;
extern u_long cpuctrl_physaddr;
extern u_long timer_physaddr;
#define SAU7_SIO01_PHYSADDR 0x10400
#define SAU7_SIO23_PHYSADDR 0x10500
#define SAU7_RTC_PHYSADDR 0x10900
#define SAU7_PICA 0x11000
#define SAU7_PICB 0x11100
#define SAU7_CPUCTRL 0x10100
#define SAU7_TIMER 0x010800
#define SAU8_SIO01_PHYSADDR 0x8400
#define SAU8_RTC_PHYSADDR 0x8900
#define SAU8_PICA 0x9400
#define SAU8_PICB 0x9500
#define SAU8_CPUCTRL 0x8100
#define SAU8_TIMER 0x8800
#define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
#define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
#define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
#define pica (IO_BASE + pica_physaddr)
#define picb (IO_BASE + picb_physaddr)
#define timer (IO_BASE + timer_physaddr)
#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
#define IRQ_APOLLO IRQ_USER
#endif

12
include/asm-m68k/atafd.h
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@@ -1,12 +0,0 @@
#ifndef _ASM_M68K_FD_H
#define _ASM_M68K_FD_H
/* Definitions for the Atari Floppy driver */
struct atari_format_descr {
int track; /* to be formatted */
int head; /* "" "" */
int sect_offset; /* offset of first sector */
};
#endif

79
include/asm-m68k/atafdreg.h
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@@ -1,79 +0,0 @@
#ifndef _LINUX_FDREG_H
#define _LINUX_FDREG_H
/*
** WD1772 stuff
*/
/* register codes */
#define FDCSELREG_STP (0x80) /* command/status register */
#define FDCSELREG_TRA (0x82) /* track register */
#define FDCSELREG_SEC (0x84) /* sector register */
#define FDCSELREG_DTA (0x86) /* data register */
/* register names for FDC_READ/WRITE macros */
#define FDCREG_CMD 0
#define FDCREG_STATUS 0
#define FDCREG_TRACK 2
#define FDCREG_SECTOR 4
#define FDCREG_DATA 6
/* command opcodes */
#define FDCCMD_RESTORE (0x00) /* - */
#define FDCCMD_SEEK (0x10) /* | */
#define FDCCMD_STEP (0x20) /* | TYP 1 Commands */
#define FDCCMD_STIN (0x40) /* | */
#define FDCCMD_STOT (0x60) /* - */
#define FDCCMD_RDSEC (0x80) /* - TYP 2 Commands */
#define FDCCMD_WRSEC (0xa0) /* - " */
#define FDCCMD_RDADR (0xc0) /* - */
#define FDCCMD_RDTRA (0xe0) /* | TYP 3 Commands */
#define FDCCMD_WRTRA (0xf0) /* - */
#define FDCCMD_FORCI (0xd0) /* - TYP 4 Command */
/* command modifier bits */
#define FDCCMDADD_SR6 (0x00) /* step rate settings */
#define FDCCMDADD_SR12 (0x01)
#define FDCCMDADD_SR2 (0x02)
#define FDCCMDADD_SR3 (0x03)
#define FDCCMDADD_V (0x04) /* verify */
#define FDCCMDADD_H (0x08) /* wait for spin-up */
#define FDCCMDADD_U (0x10) /* update track register */
#define FDCCMDADD_M (0x10) /* multiple sector access */
#define FDCCMDADD_E (0x04) /* head settling flag */
#define FDCCMDADD_P (0x02) /* precompensation off */
#define FDCCMDADD_A0 (0x01) /* DAM flag */
/* status register bits */
#define FDCSTAT_MOTORON (0x80) /* motor on */
#define FDCSTAT_WPROT (0x40) /* write protected (FDCCMD_WR*) */
#define FDCSTAT_SPINUP (0x20) /* motor speed stable (Type I) */
#define FDCSTAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
#define FDCSTAT_RECNF (0x10) /* record not found */
#define FDCSTAT_CRC (0x08) /* CRC error */
#define FDCSTAT_TR00 (0x04) /* Track 00 flag (Type I) */
#define FDCSTAT_LOST (0x04) /* Lost Data (Type II+III) */
#define FDCSTAT_IDX (0x02) /* Index status (Type I) */
#define FDCSTAT_DRQ (0x02) /* DRQ status (Type II+III) */
#define FDCSTAT_BUSY (0x01) /* FDC is busy */
/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
#define DSKSIDE (0x01)
#define DSKDRVNONE (0x06)
#define DSKDRV0 (0x02)
#define DSKDRV1 (0x04)
/* step rates */
#define FDCSTEP_6 0x00
#define FDCSTEP_12 0x01
#define FDCSTEP_2 0x02
#define FDCSTEP_3 0x03
#endif

22
include/asm-m68k/atari_joystick.h
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@@ -1,22 +0,0 @@
#ifndef _LINUX_ATARI_JOYSTICK_H
#define _LINUX_ATARI_JOYSTICK_H
/*
* linux/include/linux/atari_joystick.h
* header file for Atari Joystick driver
* by Robert de Vries (robert@and.nl) on 19Jul93
*/
void atari_joystick_interrupt(char*);
int atari_joystick_init(void);
extern int atari_mouse_buttons;
struct joystick_status {
char fire;
char dir;
int ready;
int active;
wait_queue_head_t wait;
};
#endif

22
include/asm-m68k/atari_stdma.h
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@@ -1,22 +0,0 @@
#ifndef _atari_stdma_h
#define _atari_stdma_h
#include <linux/interrupt.h>
/***************************** Prototypes *****************************/
void stdma_lock(irq_handler_t handler, void *data);
void stdma_release( void );
int stdma_others_waiting( void );
int stdma_islocked( void );
void *stdma_locked_by( void );
void stdma_init( void );
/************************* End of Prototypes **************************/
#endif /* _atari_stdma_h */

17
include/asm-m68k/atari_stram.h
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@@ -1,17 +0,0 @@
#ifndef _M68K_ATARI_STRAM_H
#define _M68K_ATARI_STRAM_H
/*
* Functions for Atari ST-RAM management
*/
/* public interface */
void *atari_stram_alloc(long size, const char *owner);
void atari_stram_free(void *);
/* functions called internally by other parts of the kernel */
void atari_stram_init(void);
void atari_stram_reserve_pages(void *start_mem);
void atari_stram_mem_init_hook (void);
#endif /*_M68K_ATARI_STRAM_H */

807
include/asm-m68k/atarihw.h
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@@ -1,807 +0,0 @@
/*
** linux/atarihw.h -- This header defines some macros and pointers for
** the various Atari custom hardware registers.
**
** Copyright 1994 by Björn Brauel
**
** 5/1/94 Roman Hodek:
** Added definitions for TT specific chips.
**
** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
** Finally added definitions for the matrix/codec and the DSP56001 host
** interface.
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _LINUX_ATARIHW_H_
#define _LINUX_ATARIHW_H_
#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/raw_io.h>
extern u_long atari_mch_cookie;
extern u_long atari_mch_type;
extern u_long atari_switches;
extern int atari_rtc_year_offset;
extern int atari_dont_touch_floppy_select;
/* convenience macros for testing machine type */
#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
(atari_mch_cookie & 0xffff) == 0)
#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
(atari_mch_cookie & 0xffff) == 0x10)
#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
/* values for atari_switches */
#define ATARI_SWITCH_IKBD 0x01
#define ATARI_SWITCH_MIDI 0x02
#define ATARI_SWITCH_SND6 0x04
#define ATARI_SWITCH_SND7 0x08
#define ATARI_SWITCH_OVSC_SHIFT 16
#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MASK 0xffff0000
/*
* Define several Hardware-Chips for indication so that for the ATARI we do
* no longer decide whether it is a Falcon or other machine . It's just
* important what hardware the machine uses
*/
/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
#define ATARIHW_DECLARE(name) unsigned name : 1
#define ATARIHW_SET(name) (atari_hw_present.name = 1)
#define ATARIHW_PRESENT(name) (atari_hw_present.name)
struct atari_hw_present {
/* video hardware */
ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
/* sound hardware */
ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
/* disk storage interfaces */
ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
ATARIHW_DECLARE(IDE); /* IDE Interface */
ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
/* other I/O hardware */
ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
without it... but who knows?) */
ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
and Falcon */
ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
/* DMA */
ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
/* real time clocks */
ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
/* supporting hardware */
ATARIHW_DECLARE(SCU); /* System Control Unit */
ATARIHW_DECLARE(BLITTER); /* Blitter */
ATARIHW_DECLARE(VME); /* VME Bus */
ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
};
extern struct atari_hw_present atari_hw_present;
/* Reading the MFP port register gives a machine independent delay, since the
* MFP always has a 8 MHz clock. This avoids problems with the varying length
* of nops on various machines. Somebody claimed that the tstb takes 600 ns.
*/
#define MFPDELAY() \
__asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" );
/* Do cache push/invalidate for DMA read/write. This function obeys the
* snooping on some machines (Medusa) and processors: The Medusa itself can
* snoop, but only the '040 can source data from its cache to DMA writes i.e.,
* reads from memory). Both '040 and '060 invalidate cache entries on snooped
* DMA reads (i.e., writes to memory).
*/
#define atari_readb raw_inb
#define atari_writeb raw_outb
#define atari_inb_p raw_inb
#define atari_outb_p raw_outb
#include <linux/mm.h>
#include <asm/cacheflush.h>
static inline void dma_cache_maintenance( unsigned long paddr,
unsigned long len,
int writeflag )
{
if (writeflag) {
if (!MACH_IS_MEDUSA || CPU_IS_060)
cache_push( paddr, len );
}
else {
if (!MACH_IS_MEDUSA)
cache_clear( paddr, len );
}
}
/*
** Shifter
*/
#define ST_LOW 0
#define ST_MID 1
#define ST_HIGH 2
#define TT_LOW 7
#define TT_MID 4
#define TT_HIGH 6
#define SHF_BAS (0xffff8200)
struct SHIFTER
{
u_char pad1;
u_char bas_hi;
u_char pad2;
u_char bas_md;
u_char pad3;
u_char volatile vcounthi;
u_char pad4;
u_char volatile vcountmid;
u_char pad5;
u_char volatile vcountlow;
u_char volatile syncmode;
u_char pad6;
u_char pad7;
u_char bas_lo;
};
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
#define SHF_FBAS (0xffff820e)
struct SHIFTER_F030
{
u_short off_next;
u_short scn_width;
};
# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
#define SHF_TBAS (0xffff8200)
struct SHIFTER_TT {
u_char char_dummy0;
u_char bas_hi; /* video mem base addr, high and mid byte */
u_char char_dummy1;
u_char bas_md;
u_char char_dummy2;
u_char vcount_hi; /* pointer to currently displayed byte */
u_char char_dummy3;
u_char vcount_md;
u_char char_dummy4;
u_char vcount_lo;
u_short st_sync; /* ST compatible sync mode register, unused */
u_char char_dummy5;
u_char bas_lo; /* video mem addr, low byte */
u_char char_dummy6[2+3*16];
/* $ffff8240: */
u_short color_reg[16]; /* 16 color registers */
u_char st_shiftmode; /* ST compatible shift mode register, unused */
u_char char_dummy7;
u_short tt_shiftmode; /* TT shift mode register */
};
#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
/* values for shifter_tt->tt_shiftmode */
#define TT_SHIFTER_STLOW 0x0000
#define TT_SHIFTER_STMID 0x0100
#define TT_SHIFTER_STHIGH 0x0200
#define TT_SHIFTER_TTLOW 0x0700
#define TT_SHIFTER_TTMID 0x0400
#define TT_SHIFTER_TTHIGH 0x0600
#define TT_SHIFTER_MODEMASK 0x0700
#define TT_SHIFTER_NUMMODE 0x0008
#define TT_SHIFTER_PALETTE_MASK 0x000f
#define TT_SHIFTER_GRAYMODE 0x1000
/* 256 TT palette registers */
#define TT_PALETTE_BASE (0xffff8400)
#define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
#define TT_PALETTE_RED_MASK 0x0f00
#define TT_PALETTE_GREEN_MASK 0x00f0
#define TT_PALETTE_BLUE_MASK 0x000f
/*
** Falcon030 VIDEL Video Controller
** for description see File 'linux\tools\atari\hardware.txt
*/
#define f030_col ((u_long *) 0xffff9800)
#define f030_xreg ((u_short*) 0xffff8282)
#define f030_yreg ((u_short*) 0xffff82a2)
#define f030_creg ((u_short*) 0xffff82c0)
#define f030_sreg ((u_short*) 0xffff8260)
#define f030_mreg ((u_short*) 0xffff820a)
#define f030_linewidth ((u_short*) 0xffff820e)
#define f030_hscroll ((u_char*) 0xffff8265)
#define VIDEL_BAS (0xffff8260)
struct VIDEL {
u_short st_shift;
u_short pad1;
u_char xoffset_s;
u_char xoffset;
u_short f_shift;
u_char pad2[0x1a];
u_short hht;
u_short hbb;
u_short hbe;
u_short hdb;
u_short hde;
u_short hss;
u_char pad3[0x14];
u_short vft;
u_short vbb;
u_short vbe;
u_short vdb;
u_short vde;
u_short vss;
u_char pad4[0x12];
u_short control;
u_short mode;
};
#define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
/*
** DMA/WD1772 Disk Controller
*/
#define FWD_BAS (0xffff8604)
struct DMA_WD
{
u_short fdc_acces_seccount;
u_short dma_mode_status;
u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
u_char dma_hi;
u_char char_dummy2;
u_char dma_md;
u_char char_dummy3;
u_char dma_lo;
u_short fdc_speed;
};
# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
/* alias */
#define st_dma dma_wd
/* The two highest bytes of an extended DMA as a short; this is a must
* for the Medusa.
*/
#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
/*
** YM2149 Sound Chip
** access in bytes
*/
#define YM_BAS (0xffff8800)
struct SOUND_YM
{
u_char rd_data_reg_sel;
u_char char_dummy1;
u_char wd_data;
};
#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
/* TT SCSI DMA */
#define TT_SCSI_DMA_BAS (0xffff8700)
struct TT_DMA {
u_char char_dummy0;
u_char dma_addr_hi;
u_char char_dummy1;
u_char dma_addr_hmd;
u_char char_dummy2;
u_char dma_addr_lmd;
u_char char_dummy3;
u_char dma_addr_lo;
u_char char_dummy4;
u_char dma_cnt_hi;
u_char char_dummy5;
u_char dma_cnt_hmd;
u_char char_dummy6;
u_char dma_cnt_lmd;
u_char char_dummy7;
u_char dma_cnt_lo;
u_long dma_restdata;
u_short dma_ctrl;
};
#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
/* TT SCSI Controller 5380 */
#define TT_5380_BAS (0xffff8781)
struct TT_5380 {
u_char scsi_data;
u_char char_dummy1;
u_char scsi_icr;
u_char char_dummy2;
u_char scsi_mode;
u_char char_dummy3;
u_char scsi_tcr;
u_char char_dummy4;
u_char scsi_idstat;
u_char char_dummy5;
u_char scsi_dmastat;
u_char char_dummy6;
u_char scsi_targrcv;
u_char char_dummy7;
u_char scsi_inircv;
};
#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
#define tt_scsi_regp ((volatile char *)TT_5380_BAS)
/*
** Falcon DMA Sound Subsystem
*/
#define MATRIX_BASE (0xffff8930)
struct MATRIX
{
u_short source;
u_short destination;
u_char external_frequency_divider;
u_char internal_frequency_divider;
};
#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
#define CODEC_BASE (0xffff8936)
struct CODEC
{
u_char tracks;
u_char input_source;
#define CODEC_SOURCE_ADC 1
#define CODEC_SOURCE_MATRIX 2
u_char adc_source;
#define ADC_SOURCE_RIGHT_PSG 1
#define ADC_SOURCE_LEFT_PSG 2
u_char gain;
#define CODEC_GAIN_RIGHT 0x0f
#define CODEC_GAIN_LEFT 0xf0
u_char attenuation;
#define CODEC_ATTENUATION_RIGHT 0x0f
#define CODEC_ATTENUATION_LEFT 0xf0
u_char unused1;
u_char status;
#define CODEC_OVERFLOW_RIGHT 1
#define CODEC_OVERFLOW_LEFT 2
u_char unused2, unused3, unused4, unused5;
u_char gpio_directions;
#define GPIO_IN 0
#define GPIO_OUT 1
u_char unused6;
u_char gpio_data;
};
#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
/*
** Falcon Blitter
*/
#define BLT_BAS (0xffff8a00)
struct BLITTER
{
u_short halftone[16];
u_short src_x_inc;
u_short src_y_inc;
u_long src_address;
u_short endmask1;
u_short endmask2;
u_short endmask3;
u_short dst_x_inc;
u_short dst_y_inc;
u_long dst_address;
u_short wd_per_line;
u_short ln_per_bb;
u_short hlf_op_reg;
u_short log_op_reg;
u_short lin_nm_reg;
u_short skew_reg;
};
# define blitter ((*(volatile struct BLITTER *)BLT_BAS))
/*
** SCC Z8530
*/
#define SCC_BAS (0xffff8c81)
struct SCC
{
u_char cha_a_ctrl;
u_char char_dummy1;
u_char cha_a_data;
u_char char_dummy2;
u_char cha_b_ctrl;
u_char char_dummy3;
u_char cha_b_data;
};
# define scc ((*(volatile struct SCC*)SCC_BAS))
/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
# define st_escc ((*(volatile struct SCC*)0xfffffa31))
# define st_escc_dsr ((*(volatile char *)0xfffffa39))
/* TT SCC DMA Controller (same chip as SCSI DMA) */
#define TT_SCC_DMA_BAS (0xffff8c00)
#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
/*
** VIDEL Palette Register
*/
#define FPL_BAS (0xffff9800)
struct VIDEL_PALETTE
{
u_long reg[256];
};
# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
/*
** Falcon DSP Host Interface
*/
#define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
struct DSP56K_HOST_INTERFACE {
u_char icr;
#define DSP56K_ICR_RREQ 0x01
#define DSP56K_ICR_TREQ 0x02
#define DSP56K_ICR_HF0 0x08
#define DSP56K_ICR_HF1 0x10
#define DSP56K_ICR_HM0 0x20
#define DSP56K_ICR_HM1 0x40
#define DSP56K_ICR_INIT 0x80
u_char cvr;
#define DSP56K_CVR_HV_MASK 0x1f
#define DSP56K_CVR_HC 0x80
u_char isr;
#define DSP56K_ISR_RXDF 0x01
#define DSP56K_ISR_TXDE 0x02
#define DSP56K_ISR_TRDY 0x04
#define DSP56K_ISR_HF2 0x08
#define DSP56K_ISR_HF3 0x10
#define DSP56K_ISR_DMA 0x40
#define DSP56K_ISR_HREQ 0x80
u_char ivr;
union {
u_char b[4];
u_short w[2];
u_long l;
} data;
};
#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
/*
** MFP 68901
*/
#define MFP_BAS (0xfffffa01)
struct MFP
{
u_char par_dt_reg;
u_char char_dummy1;
u_char active_edge;
u_char char_dummy2;
u_char data_dir;
u_char char_dummy3;
u_char int_en_a;
u_char char_dummy4;
u_char int_en_b;
u_char char_dummy5;
u_char int_pn_a;
u_char char_dummy6;
u_char int_pn_b;
u_char char_dummy7;
u_char int_sv_a;
u_char char_dummy8;
u_char int_sv_b;
u_char char_dummy9;
u_char int_mk_a;
u_char char_dummy10;
u_char int_mk_b;
u_char char_dummy11;
u_char vec_adr;
u_char char_dummy12;
u_char tim_ct_a;
u_char char_dummy13;
u_char tim_ct_b;
u_char char_dummy14;
u_char tim_ct_cd;
u_char char_dummy15;
u_char tim_dt_a;
u_char char_dummy16;
u_char tim_dt_b;
u_char char_dummy17;
u_char tim_dt_c;
u_char char_dummy18;
u_char tim_dt_d;
u_char char_dummy19;
u_char sync_char;
u_char char_dummy20;
u_char usart_ctr;
u_char char_dummy21;
u_char rcv_stat;
u_char char_dummy22;
u_char trn_stat;
u_char char_dummy23;
u_char usart_dta;
};
# define mfp ((*(volatile struct MFP*)MFP_BAS))
/* TT's second MFP */
#define TT_MFP_BAS (0xfffffa81)
# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
/* TT System Control Unit */
#define TT_SCU_BAS (0xffff8e01)
struct TT_SCU {
u_char sys_mask;
u_char char_dummy1;
u_char sys_stat;
u_char char_dummy2;
u_char softint;
u_char char_dummy3;
u_char vmeint;
u_char char_dummy4;
u_char gp_reg1;
u_char char_dummy5;
u_char gp_reg2;
u_char char_dummy6;
u_char vme_mask;
u_char char_dummy7;
u_char vme_stat;
};
#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
/* TT real time clock */
#define TT_RTC_BAS (0xffff8961)
struct TT_RTC {
u_char regsel;
u_char dummy;
u_char data;
};
#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
/*
** ACIA 6850
*/
/* constants for the ACIA registers */
/* baudrate selection and reset (Baudrate = clock/factor) */
#define ACIA_DIV1 0
#define ACIA_DIV16 1
#define ACIA_DIV64 2
#define ACIA_RESET 3
/* character format */
#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
/* transmit control */
#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
/* receive control */
#define ACIA_RID (0<<7) /* RxINT disabled */
#define ACIA_RIE (1<<7) /* RxINT enabled */
/* status fields of the ACIA */
#define ACIA_RDRF 1 /* Receive Data Register Full */
#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
#define ACIA_DCD (1<<2) /* Data Carrier Detect */
#define ACIA_CTS (1<<3) /* Clear To Send */
#define ACIA_FE (1<<4) /* Framing Error */
#define ACIA_OVRN (1<<5) /* Receiver Overrun */
#define ACIA_PE (1<<6) /* Parity Error */
#define ACIA_IRQ (1<<7) /* Interrupt Request */
#define ACIA_BAS (0xfffffc00)
struct ACIA
{
u_char key_ctrl;
u_char char_dummy1;
u_char key_data;
u_char char_dummy2;
u_char mid_ctrl;
u_char char_dummy3;
u_char mid_data;
};
# define acia ((*(volatile struct ACIA*)ACIA_BAS))
#define TT_DMASND_BAS (0xffff8900)
struct TT_DMASND {
u_char int_ctrl; /* Falcon: Interrupt control */
u_char ctrl;
u_char pad2;
u_char bas_hi;
u_char pad3;
u_char bas_mid;
u_char pad4;
u_char bas_low;
u_char pad5;
u_char addr_hi;
u_char pad6;
u_char addr_mid;
u_char pad7;
u_char addr_low;
u_char pad8;
u_char end_hi;
u_char pad9;
u_char end_mid;
u_char pad10;
u_char end_low;
u_char pad11[12];
u_char track_select; /* Falcon */
u_char mode;
u_char pad12[14];
/* Falcon only: */
u_short cbar_src;
u_short cbar_dst;
u_char ext_div;
u_char int_div;
u_char rec_track_select;
u_char dac_src;
u_char adc_src;
u_char input_gain;
u_short output_atten;
};
# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
#define DMASND_MFP_INT_REPLAY 0x01
#define DMASND_MFP_INT_RECORD 0x02
#define DMASND_TIMERA_INT_REPLAY 0x04
#define DMASND_TIMERA_INT_RECORD 0x08
#define DMASND_CTRL_OFF 0x00
#define DMASND_CTRL_ON 0x01
#define DMASND_CTRL_REPEAT 0x02
#define DMASND_CTRL_RECORD_ON 0x10
#define DMASND_CTRL_RECORD_OFF 0x00
#define DMASND_CTRL_RECORD_REPEAT 0x20
#define DMASND_CTRL_SELECT_REPLAY 0x00
#define DMASND_CTRL_SELECT_RECORD 0x80
#define DMASND_MODE_MONO 0x80
#define DMASND_MODE_STEREO 0x00
#define DMASND_MODE_8BIT 0x00
#define DMASND_MODE_16BIT 0x40 /* Falcon only */
#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
#define DMASND_MODE_12KHZ 0x01
#define DMASND_MODE_25KHZ 0x02
#define DMASND_MODE_50KHZ 0x03
#define DMASNDSetBase(bufstart) \
do { \
tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
} while( 0 )
#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
(tt_dmasnd.addr_mid << 8) + \
(tt_dmasnd.addr_low))
#define DMASNDSetEnd(bufend) \
do { \
tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
} while( 0 )
#define TT_MICROWIRE_BAS (0xffff8922)
struct TT_MICROWIRE {
u_short data;
u_short mask;
};
# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
#define MW_LM1992_ADDR 0x0400
#define MW_LM1992_VOLUME(dB) \
(0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
#define MW_LM1992_BALLEFT(dB) \
(0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
#define MW_LM1992_BALRIGHT(dB) \
(0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
#define MW_LM1992_TREBLE(dB) \
(0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
#define MW_LM1992_BASS(dB) \
(0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
#define MW_LM1992_PSG_LOW 0x000
#define MW_LM1992_PSG_HIGH 0x001
#define MW_LM1992_PSG_OFF 0x002
#define MSTE_RTC_BAS (0xfffffc21)
struct MSTE_RTC {
u_char sec_ones;
u_char dummy1;
u_char sec_tens;
u_char dummy2;
u_char min_ones;
u_char dummy3;
u_char min_tens;
u_char dummy4;
u_char hr_ones;
u_char dummy5;
u_char hr_tens;
u_char dummy6;
u_char weekday;
u_char dummy7;
u_char day_ones;
u_char dummy8;
u_char day_tens;
u_char dummy9;
u_char mon_ones;
u_char dummy10;
u_char mon_tens;
u_char dummy11;
u_char year_ones;
u_char dummy12;
u_char year_tens;
u_char dummy13;
u_char mode;
u_char dummy14;
u_char test;
u_char dummy15;
u_char reset;
};
#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
#endif /* linux/atarihw.h */

204
include/asm-m68k/atariints.h
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/*
** atariints.h -- Atari Linux interrupt handling structs and prototypes
**
** Copyright 1994 by Björn Brauel
**
** 5/2/94 Roman Hodek:
** TT interrupt definitions added.
**
** 12/02/96: (Roman)
** Adapted to new int handling scheme (see ataints.c); revised numbering
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _LINUX_ATARIINTS_H_
#define _LINUX_ATARIINTS_H_
#include <asm/irq.h>
#include <asm/atarihw.h>
/*
** Atari Interrupt sources.
**
*/
#define STMFP_SOURCE_BASE 8
#define TTMFP_SOURCE_BASE 24
#define SCC_SOURCE_BASE 40
#define VME_SOURCE_BASE 56
#define VME_MAX_SOURCES 16
#define NUM_ATARI_SOURCES (VME_SOURCE_BASE+VME_MAX_SOURCES-STMFP_SOURCE_BASE)
/* convert vector number to int source number */
#define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
/* convert irq_handler index to vector number */
#define IRQ_SOURCE_TO_VECTOR(i) ((i) + ((i) < 8 ? 0x18 : (0x40-8)))
/* interrupt service types */
#define IRQ_TYPE_SLOW 0
#define IRQ_TYPE_FAST 1
#define IRQ_TYPE_PRIO 2
/* ST-MFP interrupts */
#define IRQ_MFP_BUSY (8)
#define IRQ_MFP_DCD (9)
#define IRQ_MFP_CTS (10)
#define IRQ_MFP_GPU (11)
#define IRQ_MFP_TIMD (12)
#define IRQ_MFP_TIMC (13)
#define IRQ_MFP_ACIA (14)
#define IRQ_MFP_FDC (15)
#define IRQ_MFP_ACSI IRQ_MFP_FDC
#define IRQ_MFP_FSCSI IRQ_MFP_FDC
#define IRQ_MFP_IDE IRQ_MFP_FDC
#define IRQ_MFP_TIMB (16)
#define IRQ_MFP_SERERR (17)
#define IRQ_MFP_SEREMPT (18)
#define IRQ_MFP_RECERR (19)
#define IRQ_MFP_RECFULL (20)
#define IRQ_MFP_TIMA (21)
#define IRQ_MFP_RI (22)
#define IRQ_MFP_MMD (23)
/* TT-MFP interrupts */
#define IRQ_TT_MFP_IO0 (24)
#define IRQ_TT_MFP_IO1 (25)
#define IRQ_TT_MFP_SCC (26)
#define IRQ_TT_MFP_RI (27)
#define IRQ_TT_MFP_TIMD (28)
#define IRQ_TT_MFP_TIMC (29)
#define IRQ_TT_MFP_DRVRDY (30)
#define IRQ_TT_MFP_SCSIDMA (31)
#define IRQ_TT_MFP_TIMB (32)
#define IRQ_TT_MFP_SERERR (33)
#define IRQ_TT_MFP_SEREMPT (34)
#define IRQ_TT_MFP_RECERR (35)
#define IRQ_TT_MFP_RECFULL (36)
#define IRQ_TT_MFP_TIMA (37)
#define IRQ_TT_MFP_RTC (38)
#define IRQ_TT_MFP_SCSI (39)
/* SCC interrupts */
#define IRQ_SCCB_TX (40)
#define IRQ_SCCB_STAT (42)
#define IRQ_SCCB_RX (44)
#define IRQ_SCCB_SPCOND (46)
#define IRQ_SCCA_TX (48)
#define IRQ_SCCA_STAT (50)
#define IRQ_SCCA_RX (52)
#define IRQ_SCCA_SPCOND (54)
#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
#define MFP_ENABLE 0
#define MFP_PENDING 1
#define MFP_SERVICE 2
#define MFP_MASK 3
/* Utility functions for setting/clearing bits in the interrupt registers of
* the MFP. 'type' should be constant, if 'irq' is constant, too, code size is
* reduced. set_mfp_bit() is nonsense for PENDING and SERVICE registers. */
static inline int get_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = 1 << (irq & 7);
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
return( *reg & mask );
}
static inline void set_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = 1 << (irq & 7);
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
__asm__ __volatile__ ( "orb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
}
static inline void clear_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = ~(1 << (irq & 7));
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
if (type == MFP_PENDING || type == MFP_SERVICE)
__asm__ __volatile__ ( "moveb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
else
__asm__ __volatile__ ( "andb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
}
/*
* {en,dis}able_irq have the usual semantics of temporary blocking the
* interrupt, but not loosing requests that happen between disabling and
* enabling. This is done with the MFP mask registers.
*/
static inline void atari_enable_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
set_mfp_bit( irq, MFP_MASK );
}
static inline void atari_disable_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_MASK );
}
/*
* In opposite to {en,dis}able_irq, requests between turn{off,on}_irq are not
* "stored"
*/
static inline void atari_turnon_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
set_mfp_bit( irq, MFP_ENABLE );
}
static inline void atari_turnoff_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_ENABLE );
clear_mfp_bit( irq, MFP_PENDING );
}
static inline void atari_clear_pending_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_PENDING );
}
static inline int atari_irq_pending( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return( 0 );
return( get_mfp_bit( irq, MFP_PENDING ) );
}
unsigned long atari_register_vme_int( void );
void atari_unregister_vme_int( unsigned long );
#endif /* linux/atariints.h */

46
include/asm-m68k/atarikb.h
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/*
** atarikb.h -- This header contains the prototypes of functions of
** the intelligent keyboard of the Atari needed by the
** mouse and joystick drivers.
**
** Copyright 1994 by Robert de Vries
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 20 Feb 1994 by Robert de Vries
*/
#ifndef _LINUX_ATARIKB_H
#define _LINUX_ATARIKB_H
void ikbd_write(const char *, int);
void ikbd_mouse_button_action(int mode);
void ikbd_mouse_rel_pos(void);
void ikbd_mouse_abs_pos(int xmax, int ymax);
void ikbd_mouse_kbd_mode(int dx, int dy);
void ikbd_mouse_thresh(int x, int y);
void ikbd_mouse_scale(int x, int y);
void ikbd_mouse_pos_get(int *x, int *y);
void ikbd_mouse_pos_set(int x, int y);
void ikbd_mouse_y0_bot(void);
void ikbd_mouse_y0_top(void);
void ikbd_mouse_disable(void);
void ikbd_joystick_event_on(void);
void ikbd_joystick_event_off(void);
void ikbd_joystick_get_state(void);
void ikbd_joystick_disable(void);
/* Hook for MIDI serial driver */
extern void (*atari_MIDI_interrupt_hook) (void);
/* Hook for mouse driver */
extern void (*atari_mouse_interrupt_hook) (char *);
/* Hook for keyboard inputdev driver */
extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char);
/* Hook for mouse inputdev driver */
extern void (*atari_input_mouse_interrupt_hook) (char *);
int atari_keyb_init(void);
#endif /* _LINUX_ATARIKB_H */

196
include/asm-m68k/atomic.h
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#ifndef __ARCH_M68K_ATOMIC__
#define __ARCH_M68K_ATOMIC__
#include <linux/types.h>
#include <asm/system.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
/*
* We do not have SMP m68k systems, so we don't have to deal with that.
*/
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v, i) (((v)->counter) = i)
static inline void atomic_add(int i, atomic_t *v)
{
__asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i));
}
static inline void atomic_sub(int i, atomic_t *v)
{
__asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i));
}
static inline void atomic_inc(atomic_t *v)
{
__asm__ __volatile__("addql #1,%0" : "+m" (*v));
}
static inline void atomic_dec(atomic_t *v)
{
__asm__ __volatile__("subql #1,%0" : "+m" (*v));
}
static inline int atomic_dec_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
static inline int atomic_inc_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
#ifdef CONFIG_RMW_INSNS
static inline int atomic_add_return(int i, atomic_t *v)
{
int t, tmp;
__asm__ __volatile__(
"1: movel %2,%1\n"
" addl %3,%1\n"
" casl %2,%1,%0\n"
" jne 1b"
: "+m" (*v), "=&d" (t), "=&d" (tmp)
: "g" (i), "2" (atomic_read(v)));
return t;
}
static inline int atomic_sub_return(int i, atomic_t *v)
{
int t, tmp;
__asm__ __volatile__(
"1: movel %2,%1\n"
" subl %3,%1\n"
" casl %2,%1,%0\n"
" jne 1b"
: "+m" (*v), "=&d" (t), "=&d" (tmp)
: "g" (i), "2" (atomic_read(v)));
return t;
}
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
#else /* !CONFIG_RMW_INSNS */
static inline int atomic_add_return(int i, atomic_t * v)
{
unsigned long flags;
int t;
local_irq_save(flags);
t = atomic_read(v);
t += i;
atomic_set(v, t);
local_irq_restore(flags);
return t;
}
static inline int atomic_sub_return(int i, atomic_t * v)
{
unsigned long flags;
int t;
local_irq_save(flags);
t = atomic_read(v);
t -= i;
atomic_set(v, t);
local_irq_restore(flags);
return t;
}
static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
unsigned long flags;
int prev;
local_irq_save(flags);
prev = atomic_read(v);
if (prev == old)
atomic_set(v, new);
local_irq_restore(flags);
return prev;
}
static inline int atomic_xchg(atomic_t *v, int new)
{
unsigned long flags;
int prev;
local_irq_save(flags);
prev = atomic_read(v);
atomic_set(v, new);
local_irq_restore(flags);
return prev;
}
#endif /* !CONFIG_RMW_INSNS */
#define atomic_dec_return(v) atomic_sub_return(1, (v))
#define atomic_inc_return(v) atomic_add_return(1, (v))
static inline int atomic_sub_and_test(int i, atomic_t *v)
{
char c;
__asm__ __volatile__("subl %2,%1; seq %0" : "=d" (c), "+m" (*v): "g" (i));
return c != 0;
}
static inline int atomic_add_negative(int i, atomic_t *v)
{
char c;
__asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i));
return c != 0;
}
static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
}
static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
}
static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
for (;;) {
if (unlikely(c == (u)))
break;
old = atomic_cmpxchg((v), c, c + (a));
if (likely(old == c))
break;
c = old;
}
return c != (u);
}
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
/* Atomic operations are already serializing */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#include <asm-generic/atomic.h>
#endif /* __ARCH_M68K_ATOMIC __ */

4
include/asm-m68k/auxvec.h
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@@ -1,4 +0,0 @@
#ifndef __ASMm68k_AUXVEC_H
#define __ASMm68k_AUXVEC_H
#endif

464
include/asm-m68k/bitops.h
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@@ -1,464 +0,0 @@
#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
/*
* Copyright 1992, Linus Torvalds.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <linux/compiler.h>
/*
* Require 68020 or better.
*
* They use the standard big-endian m680x0 bit ordering.
*/
#define test_and_set_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_test_and_set_bit(nr, vaddr) : \
__generic_test_and_set_bit(nr, vaddr))
#define __test_and_set_bit(nr,vaddr) test_and_set_bit(nr,vaddr)
static inline int __constant_test_and_set_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bset %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int __generic_test_and_set_bit(int nr, unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
return retval;
}
#define set_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_set_bit(nr, vaddr) : \
__generic_set_bit(nr, vaddr))
#define __set_bit(nr,vaddr) set_bit(nr,vaddr)
static inline void __constant_set_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bset %1,%0"
: "+m" (*p) : "di" (nr & 7));
}
static inline void __generic_set_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfset %1{%0:#1}"
: : "d" (nr^31), "o" (*vaddr) : "memory");
}
#define test_and_clear_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_test_and_clear_bit(nr, vaddr) : \
__generic_test_and_clear_bit(nr, vaddr))
#define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr)
static inline int __constant_test_and_clear_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bclr %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int __generic_test_and_clear_bit(int nr, unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
return retval;
}
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
#define clear_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_clear_bit(nr, vaddr) : \
__generic_clear_bit(nr, vaddr))
#define __clear_bit(nr,vaddr) clear_bit(nr,vaddr)
static inline void __constant_clear_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bclr %1,%0"
: "+m" (*p) : "di" (nr & 7));
}
static inline void __generic_clear_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfclr %1{%0:#1}"
: : "d" (nr^31), "o" (*vaddr) : "memory");
}
#define test_and_change_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_test_and_change_bit(nr, vaddr) : \
__generic_test_and_change_bit(nr, vaddr))
#define __test_and_change_bit(nr,vaddr) test_and_change_bit(nr,vaddr)
#define __change_bit(nr,vaddr) change_bit(nr,vaddr)
static inline int __constant_test_and_change_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bchg %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int __generic_test_and_change_bit(int nr, unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
return retval;
}
#define change_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_change_bit(nr, vaddr) : \
__generic_change_bit(nr, vaddr))
static inline void __constant_change_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bchg %1,%0"
: "+m" (*p) : "di" (nr & 7));
}
static inline void __generic_change_bit(int nr, unsigned long *vaddr)
{
__asm__ __volatile__ ("bfchg %1{%0:#1}"
: : "d" (nr^31), "o" (*vaddr) : "memory");
}
static inline int test_bit(int nr, const unsigned long *vaddr)
{
return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
}
static inline int find_first_zero_bit(const unsigned long *vaddr,
unsigned size)
{
const unsigned long *p = vaddr;
int res = 32;
unsigned long num;
if (!size)
return 0;
size = (size + 31) >> 5;
while (!(num = ~*p++)) {
if (!--size)
goto out;
}
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
res ^= 31;
out:
return ((long)p - (long)vaddr - 4) * 8 + res;
}
static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
int offset)
{
const unsigned long *p = vaddr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
unsigned long num = ~*p++ & (~0UL << bit);
offset -= bit;
/* Look for zero in first longword */
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
if (res < 32)
return offset + (res ^ 31);
offset += 32;
}
/* No zero yet, search remaining full bytes for a zero */
res = find_first_zero_bit(p, size - ((long)p - (long)vaddr) * 8);
return offset + res;
}
static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
{
const unsigned long *p = vaddr;
int res = 32;
unsigned long num;
if (!size)
return 0;
size = (size + 31) >> 5;
while (!(num = *p++)) {
if (!--size)
goto out;
}
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
res ^= 31;
out:
return ((long)p - (long)vaddr - 4) * 8 + res;
}
static inline int find_next_bit(const unsigned long *vaddr, int size,
int offset)
{
const unsigned long *p = vaddr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
unsigned long num = *p++ & (~0UL << bit);
offset -= bit;
/* Look for one in first longword */
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
if (res < 32)
return offset + (res ^ 31);
offset += 32;
}
/* No one yet, search remaining full bytes for a one */
res = find_first_bit(p, size - ((long)p - (long)vaddr) * 8);
return offset + res;
}
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
static inline unsigned long ffz(unsigned long word)
{
int res;
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (~word & -~word));
return res ^ 31;
}
#ifdef __KERNEL__
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static inline int ffs(int x)
{
int cnt;
asm ("bfffo %1{#0:#0},%0" : "=d" (cnt) : "dm" (x & -x));
return 32 - cnt;
}
#define __ffs(x) (ffs(x) - 1)
/*
* fls: find last bit set.
*/
static inline int fls(int x)
{
int cnt;
asm ("bfffo %1{#0,#0},%0" : "=d" (cnt) : "dm" (x));
return 32 - cnt;
}
static inline int __fls(int x)
{
return fls(x) - 1;
}
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
/* Bitmap functions for the minix filesystem */
static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size)
{
const unsigned short *p = vaddr, *addr = vaddr;
int res;
unsigned short num;
if (!size)
return 0;
size = (size >> 4) + ((size & 15) > 0);
while (*p++ == 0xffff)
{
if (--size == 0)
return (p - addr) << 4;
}
num = ~*--p;
__asm__ __volatile__ ("bfffo %1{#16,#16},%0"
: "=d" (res) : "d" (num & -num));
return ((p - addr) << 4) + (res ^ 31);
}
#define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr))
#define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr))
#define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr))
static inline int minix_test_bit(int nr, const void *vaddr)
{
const unsigned short *p = vaddr;
return (p[nr >> 4] & (1U << (nr & 15))) != 0;
}
/* Bitmap functions for the ext2 filesystem. */
#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 24, (unsigned long *)(addr))
#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr))
#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
static inline int ext2_test_bit(int nr, const void *vaddr)
{
const unsigned char *p = vaddr;
return (p[nr >> 3] & (1U << (nr & 7))) != 0;
}
static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == ~0UL)
{
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (!ext2_test_bit (res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for zero in first longword */
for (res = bit; res < 32; res++)
if (!ext2_test_bit (res, p))
return (p - addr) * 32 + res;
p++;
}
/* No zero yet, search remaining full bytes for a zero */
res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == 0UL) {
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (ext2_test_bit(res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for one in first longword */
for (res = bit; res < 32; res++)
if (ext2_test_bit(res, p))
return (p - addr) * 32 + res;
p++;
}
/* No set bit yet, search remaining full bytes for a set bit */
res = ext2_find_first_bit(p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#endif /* __KERNEL__ */
#endif /* _M68K_BITOPS_H */

32
include/asm-m68k/blinken.h
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/*
** asm/blinken.h -- m68k blinkenlights support (currently hp300 only)
**
** (c) 1998 Phil Blundell <philb@gnu.org>
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _M68K_BLINKEN_H
#define _M68K_BLINKEN_H
#include <asm/setup.h>
#include <asm/io.h>
#define HP300_LEDS 0xf001ffff
extern unsigned char ledstate;
static __inline__ void blinken_leds(int on, int off)
{
if (MACH_IS_HP300)
{
ledstate |= on;
ledstate &= ~off;
out_8(HP300_LEDS, ~ledstate);
}
}
#endif

378
include/asm-m68k/bootinfo.h
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@@ -1,378 +0,0 @@
/*
** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 09/29/92 by Greg Harp
**
** 5/2/94 Roman Hodek:
** Added bi_atari part of the machine dependent union bi_un; for now it
** contains just a model field to distinguish between TT and Falcon.
** 26/7/96 Roman Zippel:
** Renamed to setup.h; added some useful macros to allow gcc some
** optimizations if possible.
** 5/10/96 Geert Uytterhoeven:
** Redesign of the boot information structure; renamed to bootinfo.h again
** 27/11/96 Geert Uytterhoeven:
** Backwards compatibility with bootinfo interface version 1.0
*/
#ifndef _M68K_BOOTINFO_H
#define _M68K_BOOTINFO_H
/*
* Bootinfo definitions
*
* This is an easily parsable and extendable structure containing all
* information to be passed from the bootstrap to the kernel.
*
* This way I hope to keep all future changes back/forewards compatible.
* Thus, keep your fingers crossed...
*
* This structure is copied right after the kernel bss by the bootstrap
* routine.
*/
#ifndef __ASSEMBLY__
struct bi_record {
unsigned short tag; /* tag ID */
unsigned short size; /* size of record (in bytes) */
unsigned long data[0]; /* data */
};
#endif /* __ASSEMBLY__ */
/*
* Tag Definitions
*
* Machine independent tags start counting from 0x0000
* Machine dependent tags start counting from 0x8000
*/
#define BI_LAST 0x0000 /* last record (sentinel) */
#define BI_MACHTYPE 0x0001 /* machine type (u_long) */
#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */
#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */
#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */
#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
/* (struct mem_info) */
#define BI_RAMDISK 0x0006 /* ramdisk address and size */
/* (struct mem_info) */
#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
/* (string) */
/*
* Amiga-specific tags
*/
#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */
#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */
/* (struct ConfigDev) */
#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */
#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */
#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */
#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */
#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */
#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */
/*
* Atari-specific tags
*/
#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */
#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */
/* (values are ATARI_MACH_* defines */
/* mch_cookie values (upper word) */
#define ATARI_MCH_ST 0
#define ATARI_MCH_STE 1
#define ATARI_MCH_TT 2
#define ATARI_MCH_FALCON 3
/* mch_type values */
#define ATARI_MACH_NORMAL 0 /* no special machine type */
#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */
#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */
#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */
/*
* VME-specific tags
*/
#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */
#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */
/* BI_VME_TYPE codes */
#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */
#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */
#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */
#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */
#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */
#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */
#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */
#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */
#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */
/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on
* Motorola VME boards. Contains board number, Bug version, board
* configuration options, etc. See include/asm/mvme16xhw.h for details.
*/
/*
* Macintosh-specific tags (all u_long)
*/
#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
#define BI_MAC_VADDR 0x8001 /* Mac video base address */
#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
#define BI_MAC_BTIME 0x8007 /* Mac boot time */
#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
/*
* Macintosh hardware profile data - unused, see macintosh.h for
* resonable type values
*/
#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
/*
* Mac: compatibility with old booter data format (temporarily)
* Fields unused with the new bootinfo can be deleted now; instead of
* adding new fields the struct might be splitted into a hardware address
* part and a hardware type part
*/
#ifndef __ASSEMBLY__
struct mac_booter_data
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long args;
unsigned long boottime;
unsigned long gmtbias;
unsigned long bootver;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long serialmf;
unsigned long serialhsk;
unsigned long serialgpi;
unsigned long printmf;
unsigned long printhsk;
unsigned long printgpi;
unsigned long cpuid;
unsigned long rombase;
unsigned long adbdelay;
unsigned long timedbra;
};
extern struct mac_booter_data
mac_bi_data;
#endif
/*
* Apollo-specific tags
*/
#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */
/*
* HP300-specific tags
*/
#define BI_HP300_MODEL 0x8000 /* model (u_long) */
#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */
#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */
/*
* Stuff for bootinfo interface versioning
*
* At the start of kernel code, a 'struct bootversion' is located.
* bootstrap checks for a matching version of the interface before booting
* a kernel, to avoid user confusion if kernel and bootstrap don't work
* together :-)
*
* If incompatible changes are made to the bootinfo interface, the major
* number below should be stepped (and the minor reset to 0) for the
* appropriate machine. If a change is backward-compatible, the minor
* should be stepped. "Backwards-compatible" means that booting will work,
* but certain features may not.
*/
#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */
#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor))
#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
#define BI_VERSION_MINOR(v) ((v) & 0xffff)
#ifndef __ASSEMBLY__
struct bootversion {
unsigned short branch;
unsigned long magic;
struct {
unsigned long machtype;
unsigned long version;
} machversions[0];
};
#endif /* __ASSEMBLY__ */
#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 )
#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#ifdef BOOTINFO_COMPAT_1_0
/*
* Backwards compatibility with bootinfo interface version 1.0
*/
#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#include <linux/zorro.h>
#define COMPAT_NUM_AUTO 16
struct compat_bi_Amiga {
int model;
int num_autocon;
struct ConfigDev autocon[COMPAT_NUM_AUTO];
unsigned long chip_size;
unsigned char vblank;
unsigned char psfreq;
unsigned long eclock;
unsigned long chipset;
unsigned long hw_present;
};
struct compat_bi_Atari {
unsigned long hw_present;
unsigned long mch_cookie;
};
#ifndef __ASSEMBLY__
struct compat_bi_Macintosh
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long args;
unsigned long boottime;
unsigned long gmtbias;
unsigned long bootver;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long serialmf;
unsigned long serialhsk;
unsigned long serialgpi;
unsigned long printmf;
unsigned long printhsk;
unsigned long printgpi;
unsigned long cpuid;
unsigned long rombase;
unsigned long adbdelay;
unsigned long timedbra;
};
#endif
struct compat_mem_info {
unsigned long addr;
unsigned long size;
};
#define COMPAT_NUM_MEMINFO 4
#define COMPAT_CPUB_68020 0
#define COMPAT_CPUB_68030 1
#define COMPAT_CPUB_68040 2
#define COMPAT_CPUB_68060 3
#define COMPAT_FPUB_68881 5
#define COMPAT_FPUB_68882 6
#define COMPAT_FPUB_68040 7
#define COMPAT_FPUB_68060 8
#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020)
#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030)
#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040)
#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060)
#define COMPAT_CPU_MASK (31)
#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881)
#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882)
#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040)
#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060)
#define COMPAT_FPU_MASK (0xfe0)
#define COMPAT_CL_SIZE (256)
struct compat_bootinfo {
unsigned long machtype;
unsigned long cputype;
struct compat_mem_info memory[COMPAT_NUM_MEMINFO];
int num_memory;
unsigned long ramdisk_size;
unsigned long ramdisk_addr;
char command_line[COMPAT_CL_SIZE];
union {
struct compat_bi_Amiga bi_ami;
struct compat_bi_Atari bi_ata;
struct compat_bi_Macintosh bi_mac;
} bi_un;
};
#define bi_amiga bi_un.bi_ami
#define bi_atari bi_un.bi_ata
#define bi_mac bi_un.bi_mac
#endif /* BOOTINFO_COMPAT_1_0 */
#endif /* _M68K_BOOTINFO_H */

29
include/asm-m68k/bug.h
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@@ -1,29 +0,0 @@
#ifndef _M68K_BUG_H
#define _M68K_BUG_H
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
#ifndef CONFIG_SUN3
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
__builtin_trap(); \
} while (0)
#else
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
panic("BUG!"); \
} while (0)
#endif
#else
#define BUG() do { \
__builtin_trap(); \
} while (0)
#endif
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif

14
include/asm-m68k/bugs.h
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@@ -1,14 +0,0 @@
/*
* include/asm-m68k/bugs.h
*
* Copyright (C) 1994 Linus Torvalds
*/
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */

150
include/asm-m68k/bvme6000hw.h
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@@ -1,150 +0,0 @@
#ifndef _M68K_BVME6000HW_H_
#define _M68K_BVME6000HW_H_
#include <asm/irq.h>
/*
* PIT structure
*/
#define BVME_PIT_BASE 0xffa00000
typedef struct {
unsigned char
pad_a[3], pgcr,
pad_b[3], psrr,
pad_c[3], paddr,
pad_d[3], pbddr,
pad_e[3], pcddr,
pad_f[3], pivr,
pad_g[3], pacr,
pad_h[3], pbcr,
pad_i[3], padr,
pad_j[3], pbdr,
pad_k[3], paar,
pad_l[3], pbar,
pad_m[3], pcdr,
pad_n[3], psr,
pad_o[3], res1,
pad_p[3], res2,
pad_q[3], tcr,
pad_r[3], tivr,
pad_s[3], res3,
pad_t[3], cprh,
pad_u[3], cprm,
pad_v[3], cprl,
pad_w[3], res4,
pad_x[3], crh,
pad_y[3], crm,
pad_z[3], crl,
pad_A[3], tsr,
pad_B[3], res5;
} PitRegs_t, *PitRegsPtr;
#define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
#define BVME_RTC_BASE 0xff900000
typedef struct {
unsigned char
pad_a[3], msr,
pad_b[3], t0cr_rtmr,
pad_c[3], t1cr_omr,
pad_d[3], pfr_icr0,
pad_e[3], irr_icr1,
pad_f[3], bcd_tenms,
pad_g[3], bcd_sec,
pad_h[3], bcd_min,
pad_i[3], bcd_hr,
pad_j[3], bcd_dom,
pad_k[3], bcd_mth,
pad_l[3], bcd_year,
pad_m[3], bcd_ujcc,
pad_n[3], bcd_hjcc,
pad_o[3], bcd_dow,
pad_p[3], t0lsb,
pad_q[3], t0msb,
pad_r[3], t1lsb,
pad_s[3], t1msb,
pad_t[3], cmp_sec,
pad_u[3], cmp_min,
pad_v[3], cmp_hr,
pad_w[3], cmp_dom,
pad_x[3], cmp_mth,
pad_y[3], cmp_dow,
pad_z[3], sav_sec,
pad_A[3], sav_min,
pad_B[3], sav_hr,
pad_C[3], sav_dom,
pad_D[3], sav_mth,
pad_E[3], ram,
pad_F[3], test;
} RtcRegs_t, *RtcPtr_t;
#define BVME_I596_BASE 0xff100000
#define BVME_ETHIRQ_REG 0xff20000b
#define BVME_LOCAL_IRQ_STAT 0xff20000f
#define BVME_ETHERR 0x02
#define BVME_ABORT_STATUS 0x08
#define BVME_NCR53C710_BASE 0xff000000
#define BVME_SCC_A_ADDR 0xffb0000b
#define BVME_SCC_B_ADDR 0xffb00003
#define BVME_SCC_RTxC 7372800
#define BVME_CONFIG_REG 0xff500003
#define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
#define BVME_CONFIG_SW1 0x08
#define BVME_CONFIG_SW2 0x04
#define BVME_CONFIG_SW3 0x02
#define BVME_CONFIG_SW4 0x01
#define BVME_IRQ_TYPE_PRIO 0
#define BVME_IRQ_PRN (IRQ_USER+20)
#define BVME_IRQ_TIMER (IRQ_USER+25)
#define BVME_IRQ_I596 IRQ_AUTO_2
#define BVME_IRQ_SCSI IRQ_AUTO_3
#define BVME_IRQ_RTC IRQ_AUTO_6
#define BVME_IRQ_ABORT IRQ_AUTO_7
/* SCC interrupts */
#define BVME_IRQ_SCC_BASE IRQ_USER
#define BVME_IRQ_SCCB_TX IRQ_USER
#define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
#define BVME_IRQ_SCCB_RX (IRQ_USER+4)
#define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
#define BVME_IRQ_SCCA_TX (IRQ_USER+8)
#define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
#define BVME_IRQ_SCCA_RX (IRQ_USER+12)
#define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
/* Address control registers */
#define BVME_ACR_A32VBA 0xff400003
#define BVME_ACR_A32MSK 0xff410003
#define BVME_ACR_A24VBA 0xff420003
#define BVME_ACR_A24MSK 0xff430003
#define BVME_ACR_A16VBA 0xff440003
#define BVME_ACR_A32LBA 0xff450003
#define BVME_ACR_A24LBA 0xff460003
#define BVME_ACR_ADDRCTL 0xff470003
#define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
#define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
#define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
#define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
#define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
#define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
#define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
#define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
#endif

7
include/asm-m68k/byteorder.h
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@@ -1,7 +0,0 @@
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/swab.h>
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */

11
include/asm-m68k/cache.h
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@@ -1,11 +0,0 @@
/*
* include/asm-m68k/cache.h
*/
#ifndef __ARCH_M68K_CACHE_H
#define __ARCH_M68K_CACHE_H
/* bytes per L1 cache line */
#define L1_CACHE_SHIFT 4
#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
#endif

14
include/asm-m68k/cachectl.h
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@@ -1,14 +0,0 @@
#ifndef _M68K_CACHECTL_H
#define _M68K_CACHECTL_H
/* Definitions for the cacheflush system call. */
#define FLUSH_SCOPE_LINE 1 /* Flush a cache line */
#define FLUSH_SCOPE_PAGE 2 /* Flush a page */
#define FLUSH_SCOPE_ALL 3 /* Flush the whole cache -- superuser only */
#define FLUSH_CACHE_DATA 1 /* Writeback and flush data cache */
#define FLUSH_CACHE_INSN 2 /* Flush instruction cache */
#define FLUSH_CACHE_BOTH 3 /* Flush both caches */
#endif /* _M68K_CACHECTL_H */

156
include/asm-m68k/cacheflush.h
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@@ -1,156 +0,0 @@
#ifndef _M68K_CACHEFLUSH_H
#define _M68K_CACHEFLUSH_H
#include <linux/mm.h>
/* cache code */
#define FLUSH_I_AND_D (0x00000808)
#define FLUSH_I (0x00000008)
/*
* Cache handling functions
*/
static inline void flush_icache(void)
{
if (CPU_IS_040_OR_060)
asm volatile ( "nop\n"
" .chip 68040\n"
" cpusha %bc\n"
" .chip 68k");
else {
unsigned long tmp;
asm volatile ( "movec %%cacr,%0\n"
" or.w %1,%0\n"
" movec %0,%%cacr"
: "=&d" (tmp)
: "id" (FLUSH_I));
}
}
/*
* invalidate the cache for the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_clear(unsigned long paddr, int len);
/*
* push any dirty cache in the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_push(unsigned long paddr, int len);
/*
* push and invalidate pages in the specified user virtual
* memory range.
*/
extern void cache_push_v(unsigned long vaddr, int len);
/* This is needed whenever the virtual mapping of the current
process changes. */
#define __flush_cache_all() \
({ \
if (CPU_IS_040_OR_060) \
__asm__ __volatile__("nop\n\t" \
".chip 68040\n\t" \
"cpusha %dc\n\t" \
".chip 68k"); \
else { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
"movec %0,%%cacr" \
: "=&d" (_tmp) \
: "di" (FLUSH_I_AND_D)); \
} \
})
#define __flush_cache_030() \
({ \
if (CPU_IS_020_OR_030) { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
"movec %0,%%cacr" \
: "=&d" (_tmp) \
: "di" (FLUSH_I_AND_D)); \
} \
})
#define flush_cache_all() __flush_cache_all()
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
static inline void flush_cache_mm(struct mm_struct *mm)
{
if (mm == current->mm)
__flush_cache_030();
}
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
/* flush_cache_range/flush_cache_page must be macros to avoid
a dependency on linux/mm.h, which includes this file... */
static inline void flush_cache_range(struct vm_area_struct *vma,
unsigned long start,
unsigned long end)
{
if (vma->vm_mm == current->mm)
__flush_cache_030();
}
static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
{
if (vma->vm_mm == current->mm)
__flush_cache_030();
}
/* Push the page at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
static inline void __flush_page_to_ram(void *vaddr)
{
if (CPU_IS_040_OR_060) {
__asm__ __volatile__("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (__pa(vaddr)));
} else {
unsigned long _tmp;
__asm__ __volatile__("movec %%cacr,%0\n\t"
"orw %1,%0\n\t"
"movec %0,%%cacr"
: "=&d" (_tmp)
: "di" (FLUSH_I));
}
}
#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len);
extern void flush_icache_range(unsigned long address, unsigned long endaddr);
static inline void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
flush_cache_page(vma, vaddr, page_to_pfn(page));
memcpy(dst, src, len);
flush_icache_user_range(vma, page, vaddr, len);
}
static inline void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
flush_cache_page(vma, vaddr, page_to_pfn(page));
memcpy(dst, src, len);
}
#endif /* _M68K_CACHEFLUSH_H */

148
include/asm-m68k/checksum.h
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@@ -1,148 +0,0 @@
#ifndef _M68K_CHECKSUM_H
#define _M68K_CHECKSUM_H
#include <linux/in6.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
__wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* the same as csum_partial, but copies from src while it
* checksums
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
extern __wsum csum_partial_copy_from_user(const void __user *src,
void *dst,
int len, __wsum sum,
int *csum_err);
extern __wsum csum_partial_copy_nocheck(const void *src,
void *dst, int len,
__wsum sum);
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
*/
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
unsigned int sum = 0;
unsigned long tmp;
__asm__ ("subqw #1,%2\n"
"1:\t"
"movel %1@+,%3\n\t"
"addxl %3,%0\n\t"
"dbra %2,1b\n\t"
"movel %0,%3\n\t"
"swap %3\n\t"
"addxw %3,%0\n\t"
"clrw %3\n\t"
"addxw %3,%0\n\t"
: "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
: "0" (sum), "1" (iph), "2" (ihl)
: "memory");
return (__force __sum16)~sum;
}
/*
* Fold a partial checksum
*/
static inline __sum16 csum_fold(__wsum sum)
{
unsigned int tmp = (__force u32)sum;
__asm__("swap %1\n\t"
"addw %1, %0\n\t"
"clrw %1\n\t"
"addxw %1, %0"
: "=&d" (sum), "=&d" (tmp)
: "0" (sum), "1" (tmp));
return (__force __sum16)~sum;
}
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
__asm__ ("addl %2,%0\n\t"
"addxl %3,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=d" (saddr)
: "g" (daddr), "1" (saddr), "d" (len + proto),
"0" (sum));
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __sum16
csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold (csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ __sum16
csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
__u32 len, unsigned short proto, __wsum sum)
{
register unsigned long tmp;
__asm__("addl %2@,%0\n\t"
"movel %2@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(12),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@,%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(12),%1\n\t"
"addxl %1,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=&d" (tmp)
: "a" (saddr), "a" (daddr), "d" (len + proto),
"0" (sum));
return csum_fold(sum);
}
#endif /* _M68K_CHECKSUM_H */

53
include/asm-m68k/contregs.h
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@@ -1,53 +0,0 @@
#ifndef _M68K_CONTREGS_H
#define _M68K_CONTREGS_H
/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
* space. These are for the mmu's context register, etc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* 3=sun3
4=sun4 (as in sun4 sysmaint student book)
c=sun4c (according to davem) */
#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
#define AC_SYNC_ERR 0x60000000 /* c fault type */
#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
#define AC_M_CXR 0x0200 /* shv Context Register */
#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
#define AC_M_RESET 0x0700 /* hv Reset Reg */
#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
#define AC_M_ITR 0x1300 /* hv Index Tag Register */
#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
#endif /* _M68K_CONTREGS_H */

6
include/asm-m68k/cputime.h
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@@ -1,6 +0,0 @@
#ifndef __M68K_CPUTIME_H
#define __M68K_CPUTIME_H
#include <asm-generic/cputime.h>
#endif /* __M68K_CPUTIME_H */

6
include/asm-m68k/current.h
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@@ -1,6 +0,0 @@
#ifndef _M68K_CURRENT_H
#define _M68K_CURRENT_H
register struct task_struct *current __asm__("%a2");
#endif /* !(_M68K_CURRENT_H) */

57
include/asm-m68k/delay.h
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@@ -1,57 +0,0 @@
#ifndef _M68K_DELAY_H
#define _M68K_DELAY_H
#include <asm/param.h>
/*
* Copyright (C) 1994 Hamish Macdonald
*
* Delay routines, using a pre-computed "loops_per_jiffy" value.
*/
static inline void __delay(unsigned long loops)
{
__asm__ __volatile__ ("1: subql #1,%0; jcc 1b"
: "=d" (loops) : "0" (loops));
}
extern void __bad_udelay(void);
/*
* Use only for very small delays ( < 1 msec). Should probably use a
* lookup table, really, as the multiplications take much too long with
* short delays. This is a "reasonable" implementation, though (and the
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
static inline void __const_udelay(unsigned long xloops)
{
unsigned long tmp;
__asm__ ("mulul %2,%0:%1"
: "=d" (xloops), "=d" (tmp)
: "d" (xloops), "1" (loops_per_jiffy));
__delay(xloops * HZ);
}
static inline void __udelay(unsigned long usecs)
{
__const_udelay(usecs * 4295); /* 2**32 / 1000000 */
}
#define udelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 4295)) : \
__udelay(n))
static inline unsigned long muldiv(unsigned long a, unsigned long b,
unsigned long c)
{
unsigned long tmp;
__asm__ ("mulul %2,%0:%1; divul %3,%0:%1"
: "=d" (tmp), "=d" (a)
: "d" (b), "d" (c), "1" (a));
return a;
}
#endif /* defined(_M68K_DELAY_H) */

7
include/asm-m68k/device.h
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@@ -1,7 +0,0 @@
/*
* Arch specific extensions to struct device
*
* This file is released under the GPLv2
*/
#include <asm-generic/device.h>

28
include/asm-m68k/div64.h
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@@ -1,28 +0,0 @@
#ifndef _M68K_DIV64_H
#define _M68K_DIV64_H
#include <linux/types.h>
/* n = n / base; return rem; */
#define do_div(n, base) ({ \
union { \
unsigned long n32[2]; \
unsigned long long n64; \
} __n; \
unsigned long __rem, __upper; \
\
__n.n64 = (n); \
if ((__upper = __n.n32[0])) { \
asm ("divul.l %2,%1:%0" \
: "=d" (__n.n32[0]), "=d" (__upper) \
: "d" (base), "0" (__n.n32[0])); \
} \
asm ("divu.l %2,%1:%0" \
: "=d" (__n.n32[1]), "=d" (__rem) \
: "d" (base), "1" (__upper), "0" (__n.n32[1])); \
(n) = __n.n64; \
__rem; \
})
#endif /* _M68K_DIV64_H */

112
include/asm-m68k/dma-mapping.h
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@@ -1,112 +0,0 @@
#ifndef _M68K_DMA_MAPPING_H
#define _M68K_DMA_MAPPING_H
#include <asm/cache.h>
struct scatterlist;
#ifndef CONFIG_MMU_SUN3
static inline int dma_supported(struct device *dev, u64 mask)
{
return 1;
}
static inline int dma_set_mask(struct device *dev, u64 mask)
{
return 0;
}
static inline int dma_get_cache_alignment(void)
{
return 1 << L1_CACHE_SHIFT;
}
static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 0;
}
extern void *dma_alloc_coherent(struct device *, size_t,
dma_addr_t *, gfp_t);
extern void dma_free_coherent(struct device *, size_t,
void *, dma_addr_t);
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *handle, gfp_t flag)
{
return dma_alloc_coherent(dev, size, handle, flag);
}
static inline void dma_free_noncoherent(struct device *dev, size_t size,
void *addr, dma_addr_t handle)
{
dma_free_coherent(dev, size, addr, handle);
}
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction dir)
{
/* we use coherent allocation, so not much to do here. */
}
extern dma_addr_t dma_map_single(struct device *, void *, size_t,
enum dma_data_direction);
static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
size_t size, enum dma_data_direction dir)
{
}
extern dma_addr_t dma_map_page(struct device *, struct page *,
unsigned long, size_t size,
enum dma_data_direction);
static inline void dma_unmap_page(struct device *dev, dma_addr_t address,
size_t size, enum dma_data_direction dir)
{
}
extern int dma_map_sg(struct device *, struct scatterlist *, int,
enum dma_data_direction);
static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction dir)
{
}
extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
enum dma_data_direction);
extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
enum dma_data_direction);
static inline void dma_sync_single_range_for_device(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
}
static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
size_t size, enum dma_data_direction dir)
{
}
static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
}
static inline void dma_sync_single_range_for_cpu(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
}
static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
{
return 0;
}
#else
#include <asm-generic/dma-mapping-broken.h>
#endif
#endif /* _M68K_DMA_MAPPING_H */

16
include/asm-m68k/dma.h
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@@ -1,16 +0,0 @@
#ifndef _M68K_DMA_H
#define _M68K_DMA_H 1
/* it's useless on the m68k, but unfortunately needed by the new
bootmem allocator (but this should do it for this) */
#define MAX_DMA_ADDRESS PAGE_OFFSET
#define MAX_DMA_CHANNELS 8
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#define isa_dma_bridge_buggy (0)
#endif /* _M68K_DMA_H */

35
include/asm-m68k/dsp56k.h
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@@ -1,35 +0,0 @@
/*
* linux/include/asm-m68k/dsp56k.h - defines and declarations for
* DSP56k device driver
*
* Copyright (C) 1996,1997 Fredrik Noring, lars brinkhoff & Tomas Berndtsson
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/* Used for uploading DSP binary code */
struct dsp56k_upload {
int len;
char __user *bin;
};
/* For the DSP host flags */
struct dsp56k_host_flags {
int dir; /* Bit field. 1 = write output bit, 0 = do nothing.
* 0x0000 means reading only, 0x0011 means
* writing the bits stored in `out' on HF0 and HF1.
* Note that HF2 and HF3 can only be read.
*/
int out; /* Bit field like above. */
int status; /* Host register's current state is returned */
};
/* ioctl command codes */
#define DSP56K_UPLOAD 1 /* Upload DSP binary program */
#define DSP56K_SET_TX_WSIZE 2 /* Host transmit word size (1-4) */
#define DSP56K_SET_RX_WSIZE 3 /* Host receive word size (1-4) */
#define DSP56K_HOST_FLAGS 4 /* Host flag registers */
#define DSP56K_HOST_CMD 5 /* Trig Host Command (0-31) */

240
include/asm-m68k/dvma.h
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@@ -1,240 +0,0 @@
/*
* include/asm-m68k/dma.h
*
* Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
*
* Hacked to fit Sun3x needs by Thomas Bogendoerfer
*/
#ifndef __M68K_DVMA_H
#define __M68K_DVMA_H
#define DVMA_PAGE_SHIFT 13
#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
extern void dvma_init(void);
extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
int len);
#define dvma_malloc(x) dvma_malloc_align(x, 0)
#define dvma_map(x, y) dvma_map_align(x, y, 0)
#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
extern unsigned long dvma_map_align(unsigned long kaddr, int len,
int align);
extern void *dvma_malloc_align(unsigned long len, unsigned long align);
extern void dvma_unmap(void *baddr);
extern void dvma_free(void *vaddr);
#ifdef CONFIG_SUN3
/* sun3 dvma page support */
/* memory and pmegs potentially reserved for dvma */
#define DVMA_PMEG_START 10
#define DVMA_PMEG_END 16
#define DVMA_START 0xf00000
#define DVMA_END 0xfe0000
#define DVMA_SIZE (DVMA_END-DVMA_START)
#define IOMMU_TOTAL_ENTRIES 128
#define IOMMU_ENTRIES 120
/* empirical kludge -- dvma regions only seem to work right on 0x10000
byte boundaries */
#define DVMA_REGION_SIZE 0x10000
#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
~(DVMA_REGION_SIZE-1))
/* virt <-> phys conversions */
#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
#define dvma_vtob(x) dvma_vtop(x)
#define dvma_btov(x) dvma_ptov(x)
static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
int len)
{
return 0;
}
#else /* Sun3x */
/* sun3x dvma page support */
#define DVMA_START 0x0
#define DVMA_END 0xf00000
#define DVMA_SIZE (DVMA_END-DVMA_START)
#define IOMMU_TOTAL_ENTRIES 2048
/* the prom takes the top meg */
#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
#define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
/* everything below this line is specific to dma used for the onboard
ESP scsi on sun3x */
/* Structure to describe the current status of DMA registers on the Sparc */
struct sparc_dma_registers {
__volatile__ unsigned long cond_reg; /* DMA condition register */
__volatile__ unsigned long st_addr; /* Start address of this transfer */
__volatile__ unsigned long cnt; /* How many bytes to transfer */
__volatile__ unsigned long dma_test; /* DMA test register */
};
/* DVMA chip revisions */
enum dvma_rev {
dvmarev0,
dvmaesc1,
dvmarev1,
dvmarev2,
dvmarev3,
dvmarevplus,
dvmahme
};
#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
/* Linux DMA information structure, filled during probe. */
struct Linux_SBus_DMA {
struct Linux_SBus_DMA *next;
struct linux_sbus_device *SBus_dev;
struct sparc_dma_registers *regs;
/* Status, misc info */
int node; /* Prom node for this DMA device */
int running; /* Are we doing DMA now? */
int allocated; /* Are we "owned" by anyone yet? */
/* Transfer information. */
unsigned long addr; /* Start address of current transfer */
int nbytes; /* Size of current transfer */
int realbytes; /* For splitting up large transfers, etc. */
/* DMA revision */
enum dvma_rev revision;
};
extern struct Linux_SBus_DMA *dma_chain;
/* Broken hardware... */
#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
/* Fields in the cond_reg register */
/* First, the version identification bits */
#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
#define DMA_VERS0 0x00000000 /* Sunray DMA version */
#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
#define DMA_VERS1 0x80000000 /* DMA rev 1 */
#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
/* Values describing the burst-size property from the PROM */
#define DMA_BURST1 0x01
#define DMA_BURST2 0x02
#define DMA_BURST4 0x04
#define DMA_BURST8 0x08
#define DMA_BURST16 0x10
#define DMA_BURST32 0x20
#define DMA_BURST64 0x40
#define DMA_BURSTBITS 0x7f
/* Determine highest possible final transfer address given a base */
#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
/* Yes, I hack a lot of elisp in my spare time... */
#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
#define DMA_BEGINDMA_W(regs) \
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
#define DMA_BEGINDMA_R(regs) \
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
/* For certain DMA chips, we need to disable ints upon irq entry
* and turn them back on when we are done. So in any ESP interrupt
* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
* when leaving the handler. You have been warned...
*/
#define DMA_IRQ_ENTRY(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
} while (0)
#define DMA_IRQ_EXIT(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
} while(0)
/* Reset the friggin' thing... */
#define DMA_RESET(dma) do { \
struct sparc_dma_registers *regs = dma->regs; \
/* Let the current FIFO drain itself */ \
sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
/* Reset the logic */ \
regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
__delay(400); /* let the bits set ;) */ \
regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
/* Enable FAST transfers if available */ \
if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
dma->running = 0; \
} while(0)
#endif /* !CONFIG_SUN3 */
#endif /* !(__M68K_DVMA_H) */

119
include/asm-m68k/elf.h
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@@ -1,119 +0,0 @@
#ifndef __ASMm68k_ELF_H
#define __ASMm68k_ELF_H
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
/*
* 68k ELF relocation types
*/
#define R_68K_NONE 0
#define R_68K_32 1
#define R_68K_16 2
#define R_68K_8 3
#define R_68K_PC32 4
#define R_68K_PC16 5
#define R_68K_PC8 6
#define R_68K_GOT32 7
#define R_68K_GOT16 8
#define R_68K_GOT8 9
#define R_68K_GOT32O 10
#define R_68K_GOT16O 11
#define R_68K_GOT8O 12
#define R_68K_PLT32 13
#define R_68K_PLT16 14
#define R_68K_PLT8 15
#define R_68K_PLT32O 16
#define R_68K_PLT16O 17
#define R_68K_PLT8O 18
#define R_68K_COPY 19
#define R_68K_GLOB_DAT 20
#define R_68K_JMP_SLOT 21
#define R_68K_RELATIVE 22
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_m68kfp_struct elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_68K)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
#define ELF_ARCH EM_68K
/* For SVR4/m68k the function pointer to be registered with `atexit' is
passed in %a1. Although my copy of the ABI has no such statement, it
is actually used on ASV. */
#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
#define USE_ELF_CORE_DUMP
#ifndef CONFIG_SUN3
#define ELF_EXEC_PAGESIZE 4096
#else
#define ELF_EXEC_PAGESIZE 8192
#endif
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#ifndef CONFIG_SUN3
#define ELF_ET_DYN_BASE 0xD0000000UL
#else
#define ELF_ET_DYN_BASE 0x0D800000UL
#endif
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
/* Bleech. */ \
pr_reg[0] = regs->d1; \
pr_reg[1] = regs->d2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d4; \
pr_reg[4] = regs->d5; \
pr_reg[7] = regs->a0; \
pr_reg[8] = regs->a1; \
pr_reg[9] = regs->a2; \
pr_reg[14] = regs->d0; \
pr_reg[15] = rdusp(); \
pr_reg[16] = regs->orig_d0; \
pr_reg[17] = regs->sr; \
pr_reg[18] = regs->pc; \
pr_reg[19] = (regs->format << 12) | regs->vector; \
{ \
struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
pr_reg[5] = sw->d6; \
pr_reg[6] = sw->d7; \
pr_reg[10] = sw->a3; \
pr_reg[11] = sw->a4; \
pr_reg[12] = sw->a5; \
pr_reg[13] = sw->a6; \
}
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif

6
include/asm-m68k/emergency-restart.h
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@@ -1,6 +0,0 @@
#ifndef _ASM_EMERGENCY_RESTART_H
#define _ASM_EMERGENCY_RESTART_H
#include <asm-generic/emergency-restart.h>
#endif /* _ASM_EMERGENCY_RESTART_H */

137
include/asm-m68k/entry.h
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@@ -1,137 +0,0 @@
#ifndef __M68K_ENTRY_H
#define __M68K_ENTRY_H
#include <asm/setup.h>
#include <asm/page.h>
/*
* Stack layout in 'ret_from_exception':
*
* This allows access to the syscall arguments in registers d1-d5
*
* 0(sp) - d1
* 4(sp) - d2
* 8(sp) - d3
* C(sp) - d4
* 10(sp) - d5
* 14(sp) - a0
* 18(sp) - a1
* 1C(sp) - a2
* 20(sp) - d0
* 24(sp) - orig_d0
* 28(sp) - stack adjustment
* 2C(sp) - sr
* 2E(sp) - pc
* 32(sp) - format & vector
*/
/*
* 97/05/14 Andreas: Register %a2 is now set to the current task throughout
* the whole kernel.
*/
/* the following macro is used when enabling interrupts */
#if defined(MACH_ATARI_ONLY)
/* block out HSYNC on the atari */
#define ALLOWINT (~0x400)
#define MAX_NOINT_IPL 3
#else
/* portable version */
#define ALLOWINT (~0x700)
#define MAX_NOINT_IPL 0
#endif /* machine compilation types */
#ifdef __ASSEMBLY__
#define curptr a2
LFLUSH_I_AND_D = 0x00000808
LSIGTRAP = 5
/* process bits for task_struct.ptrace */
PT_TRACESYS_OFF = 3
PT_TRACESYS_BIT = 1
PT_PTRACED_OFF = 3
PT_PTRACED_BIT = 0
PT_DTRACE_OFF = 3
PT_DTRACE_BIT = 2
#define SAVE_ALL_INT save_all_int
#define SAVE_ALL_SYS save_all_sys
#define RESTORE_ALL restore_all
/*
* This defines the normal kernel pt-regs layout.
*
* regs a3-a6 and d6-d7 are preserved by C code
* the kernel doesn't mess with usp unless it needs to
*/
/*
* a -1 in the orig_d0 field signifies
* that the stack frame is NOT for syscall
*/
.macro save_all_int
clrl %sp@- | stk_adj
pea -1:w | orig d0
movel %d0,%sp@- | d0
moveml %d1-%d5/%a0-%a1/%curptr,%sp@-
.endm
.macro save_all_sys
clrl %sp@- | stk_adj
movel %d0,%sp@- | orig d0
movel %d0,%sp@- | d0
moveml %d1-%d5/%a0-%a1/%curptr,%sp@-
.endm
.macro restore_all
moveml %sp@+,%a0-%a1/%curptr/%d1-%d5
movel %sp@+,%d0
addql #4,%sp | orig d0
addl %sp@+,%sp | stk adj
rte
.endm
#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
#define SAVE_SWITCH_STACK save_switch_stack
#define RESTORE_SWITCH_STACK restore_switch_stack
#define GET_CURRENT(tmp) get_current tmp
.macro save_switch_stack
moveml %a3-%a6/%d6-%d7,%sp@-
.endm
.macro restore_switch_stack
moveml %sp@+,%a3-%a6/%d6-%d7
.endm
.macro get_current reg=%d0
movel %sp,\reg
andw #-THREAD_SIZE,\reg
movel \reg,%curptr
movel %curptr@,%curptr
.endm
#else /* C source */
#define STR(X) STR1(X)
#define STR1(X) #X
#define PT_OFF_ORIG_D0 0x24
#define PT_OFF_FORMATVEC 0x32
#define PT_OFF_SR 0x2C
#define SAVE_ALL_INT \
"clrl %%sp@-;" /* stk_adj */ \
"pea -1:w;" /* orig d0 = -1 */ \
"movel %%d0,%%sp@-;" /* d0 */ \
"moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
#define GET_CURRENT(tmp) \
"movel %%sp,"#tmp"\n\t" \
"andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
"movel "#tmp",%%a2\n\t" \
"movel %%a2@,%%a2"
#endif
#endif /* __M68K_ENTRY_H */

6
include/asm-m68k/errno.h
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@@ -1,6 +0,0 @@
#ifndef _M68K_ERRNO_H
#define _M68K_ERRNO_H
#include <asm-generic/errno.h>
#endif /* _M68K_ERRNO_H */

34
include/asm-m68k/fb.h
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@@ -1,34 +0,0 @@
#ifndef _ASM_FB_H_
#define _ASM_FB_H_
#include <linux/fb.h>
#include <linux/fs.h>
#include <asm/page.h>
#include <asm/setup.h>
#ifdef CONFIG_SUN3
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
{
pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
}
#else
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
{
if (CPU_IS_020_OR_030)
pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
if (CPU_IS_040_OR_060) {
pgprot_val(vma->vm_page_prot) &= _CACHEMASK040;
/* Use no-cache mode, serialized */
pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
}
}
#endif /* CONFIG_SUN3 */
static inline int fb_is_primary_device(struct fb_info *info)
{
return 0;
}
#endif /* _ASM_FB_H_ */

330
include/asm-m68k/fbio.h
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@@ -1,330 +0,0 @@
#ifndef __LINUX_FBIO_H
#define __LINUX_FBIO_H
#include <linux/compiler.h>
#include <linux/types.h>
/* Constants used for fbio SunOS compatibility */
/* (C) 1996 Miguel de Icaza */
/* Frame buffer types */
#define FBTYPE_NOTYPE -1
#define FBTYPE_SUN1BW 0 /* mono */
#define FBTYPE_SUN1COLOR 1
#define FBTYPE_SUN2BW 2
#define FBTYPE_SUN2COLOR 3
#define FBTYPE_SUN2GP 4
#define FBTYPE_SUN5COLOR 5
#define FBTYPE_SUN3COLOR 6
#define FBTYPE_MEMCOLOR 7
#define FBTYPE_SUN4COLOR 8
#define FBTYPE_NOTSUN1 9
#define FBTYPE_NOTSUN2 10
#define FBTYPE_NOTSUN3 11
#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
#define FBTYPE_SUNROP_COLOR 13
#define FBTYPE_SUNFB_VIDEO 14
#define FBTYPE_SUNGIFB 15
#define FBTYPE_SUNGPLAS 16
#define FBTYPE_SUNGP3 17
#define FBTYPE_SUNGT 18
#define FBTYPE_SUNLEO 19 /* zx Leo card */
#define FBTYPE_MDICOLOR 20 /* cg14 */
#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
/* Does not seem to be listed in the Sun file either */
#define FBTYPE_CREATOR 22
#define FBTYPE_PCI_IGA1682 23
#define FBTYPE_P9100COLOR 24
#define FBTYPE_PCI_GENERIC 1000
#define FBTYPE_PCI_MACH64 1001
/* fbio ioctls */
/* Returned by FBIOGTYPE */
struct fbtype {
int fb_type; /* fb type, see above */
int fb_height; /* pixels */
int fb_width; /* pixels */
int fb_depth;
int fb_cmsize; /* color map entries */
int fb_size; /* fb size in bytes */
};
#define FBIOGTYPE _IOR('F', 0, struct fbtype)
struct fbcmap {
int index; /* first element (0 origin) */
int count;
unsigned char __user *red;
unsigned char __user *green;
unsigned char __user *blue;
};
#ifdef __KERNEL__
#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
#else
#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
#endif
/* # of device specific values */
#define FB_ATTR_NDEVSPECIFIC 8
/* # of possible emulations */
#define FB_ATTR_NEMUTYPES 4
struct fbsattr {
int flags;
int emu_type; /* -1 if none */
int dev_specific[FB_ATTR_NDEVSPECIFIC];
};
struct fbgattr {
int real_type; /* real frame buffer type */
int owner; /* unknown */
struct fbtype fbtype; /* real frame buffer fbtype */
struct fbsattr sattr;
int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
};
#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
#define FBIOSVIDEO _IOW('F', 7, int)
#define FBIOGVIDEO _IOR('F', 8, int)
struct fbcursor {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
char __user *image; /* cursor image bits */
char __user *mask; /* cursor mask bits */
};
/* set/get cursor attributes/shape */
#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
/* set/get cursor position */
#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
/* get max cursor size */
#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
/* wid manipulation */
struct fb_wid_alloc {
#define FB_WID_SHARED_8 0
#define FB_WID_SHARED_24 1
#define FB_WID_DBL_8 2
#define FB_WID_DBL_24 3
__u32 wa_type;
__s32 wa_index; /* Set on return */
__u32 wa_count;
};
struct fb_wid_item {
__u32 wi_type;
__s32 wi_index;
__u32 wi_attrs;
__u32 wi_values[32];
};
struct fb_wid_list {
__u32 wl_flags;
__u32 wl_count;
struct fb_wid_item *wl_list;
};
#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
/* Creator ioctls */
#define FFB_IOCTL ('F'<<8)
#define FFB_SYS_INFO (FFB_IOCTL|80)
#define FFB_CLUTREAD (FFB_IOCTL|81)
#define FFB_CLUTPOST (FFB_IOCTL|82)
#define FFB_SETDIAGMODE (FFB_IOCTL|83)
#define FFB_GETMONITORID (FFB_IOCTL|84)
#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
#define FFB_SETSERVER (FFB_IOCTL|87)
#define FFB_SETOVCTL (FFB_IOCTL|88)
#define FFB_GETOVCTL (FFB_IOCTL|89)
#define FFB_GETSAXNUM (FFB_IOCTL|90)
#define FFB_FBDEBUG (FFB_IOCTL|91)
/* Cg14 ioctls */
#define MDI_IOCTL ('M'<<8)
#define MDI_RESET (MDI_IOCTL|1)
#define MDI_GET_CFGINFO (MDI_IOCTL|2)
#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
# define MDI_32_PIX 32
# define MDI_16_PIX 16
# define MDI_8_PIX 8
struct mdi_cfginfo {
int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
int mdi_type; /* FBTYPE name */
int mdi_height; /* height */
int mdi_width; /* widht */
int mdi_size; /* available ram */
int mdi_mode; /* 8bpp, 16bpp or 32bpp */
int mdi_pixfreq; /* pixel clock (from PROM) */
};
/* SparcLinux specific ioctl for the MDI, should be replaced for
* the SET_XLUT/SET_CLUTn ioctls instead
*/
#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
/* leo & ffb ioctls */
struct fb_clut_alloc {
__u32 clutid; /* Set on return */
__u32 flag;
__u32 index;
};
struct fb_clut {
#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
char * red;
char * green;
char * blue;
};
struct fb_clut32 {
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
__u32 red;
__u32 green;
__u32 blue;
};
#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
#ifdef __KERNEL__
/* Addresses on the fd of a cgsix that are mappable */
#define CG6_FBC 0x70000000
#define CG6_TEC 0x70001000
#define CG6_BTREGS 0x70002000
#define CG6_FHC 0x70004000
#define CG6_THC 0x70005000
#define CG6_ROM 0x70006000
#define CG6_RAM 0x70016000
#define CG6_DHC 0x80000000
#define CG3_MMAP_OFFSET 0x4000000
/* Addresses on the fd of a tcx that are mappable */
#define TCX_RAM8BIT 0x00000000
#define TCX_RAM24BIT 0x01000000
#define TCX_UNK3 0x10000000
#define TCX_UNK4 0x20000000
#define TCX_CONTROLPLANE 0x28000000
#define TCX_UNK6 0x30000000
#define TCX_UNK7 0x38000000
#define TCX_TEC 0x70000000
#define TCX_BTREGS 0x70002000
#define TCX_THC 0x70004000
#define TCX_DHC 0x70008000
#define TCX_ALT 0x7000a000
#define TCX_SYNC 0x7000e000
#define TCX_UNK2 0x70010000
/* CG14 definitions */
/* Offsets into the OBIO space: */
#define CG14_REGS 0 /* registers */
#define CG14_CURSORREGS 0x1000 /* cursor registers */
#define CG14_DACREGS 0x2000 /* DAC registers */
#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
#define CG14_CLUT1 0x4000 /* Color Look Up Table */
#define CG14_CLUT2 0x5000 /* Color Look Up Table */
#define CG14_CLUT3 0x6000 /* Color Look Up Table */
#define CG14_AUTO 0xf000
#endif /* KERNEL */
/* These are exported to userland for applications to use */
/* Mappable offsets for the cg14: control registers */
#define MDI_DIRECT_MAP 0x10000000
#define MDI_CTLREG_MAP 0x20000000
#define MDI_CURSOR_MAP 0x30000000
#define MDI_SHDW_VRT_MAP 0x40000000
/* Mappable offsets for the cg14: frame buffer resolutions */
/* 32 bits */
#define MDI_CHUNKY_XBGR_MAP 0x50000000
#define MDI_CHUNKY_BGR_MAP 0x60000000
/* 16 bits */
#define MDI_PLANAR_X16_MAP 0x70000000
#define MDI_PLANAR_C16_MAP 0x80000000
/* 8 bit is done as CG3 MMAP offset */
/* 32 bits, planar */
#define MDI_PLANAR_X32_MAP 0x90000000
#define MDI_PLANAR_B32_MAP 0xa0000000
#define MDI_PLANAR_G32_MAP 0xb0000000
#define MDI_PLANAR_R32_MAP 0xc0000000
/* Mappable offsets on leo */
#define LEO_SS0_MAP 0x00000000
#define LEO_LC_SS0_USR_MAP 0x00800000
#define LEO_LD_SS0_MAP 0x00801000
#define LEO_LX_CURSOR_MAP 0x00802000
#define LEO_SS1_MAP 0x00803000
#define LEO_LC_SS1_USR_MAP 0x01003000
#define LEO_LD_SS1_MAP 0x01004000
#define LEO_UNK_MAP 0x01005000
#define LEO_LX_KRN_MAP 0x01006000
#define LEO_LC_SS0_KRN_MAP 0x01007000
#define LEO_LC_SS1_KRN_MAP 0x01008000
#define LEO_LD_GBL_MAP 0x01009000
#define LEO_UNK2_MAP 0x0100a000
#ifdef __KERNEL__
struct fbcmap32 {
int index; /* first element (0 origin) */
int count;
u32 red;
u32 green;
u32 blue;
};
#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
struct fbcursor32 {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap32 cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
u32 image; /* cursor image bits */
u32 mask; /* cursor mask bits */
};
#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
#endif
#endif /* __LINUX_FBIO_H */

11
include/asm-m68k/fcntl.h
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@@ -1,11 +0,0 @@
#ifndef _M68K_FCNTL_H
#define _M68K_FCNTL_H
#define O_DIRECTORY 040000 /* must be a directory */
#define O_NOFOLLOW 0100000 /* don't follow links */
#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
#define O_LARGEFILE 0400000
#include <asm-generic/fcntl.h>
#endif /* _M68K_FCNTL_H */

254
include/asm-m68k/floppy.h
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@@ -1,254 +0,0 @@
/*
* Implementation independent bits of the Floppy driver.
*
* much of this file is derived from what was originally the Q40 floppy driver.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999, 2000, 2001
*
* Sun3x support added 2/4/2000 Sam Creasey (sammy@sammy.net)
*
*/
#include <asm/io.h>
#include <linux/vmalloc.h>
asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id);
/* constants... */
#undef MAX_DMA_ADDRESS
#define MAX_DMA_ADDRESS 0x00 /* nothing like that */
/*
* Again, the CMOS information doesn't work on m68k..
*/
#define FLOPPY0_TYPE (MACH_IS_Q40 ? 6 : 4)
#define FLOPPY1_TYPE 0
/* basically PC init + set use_virtual_dma */
#define FDC1 m68k_floppy_init()
#define N_FDC 1
#define N_DRIVE 8
/* vdma globals adapted from asm-i386/floppy.h */
static int virtual_dma_count=0;
static int virtual_dma_residue=0;
static char *virtual_dma_addr=NULL;
static int virtual_dma_mode=0;
static int doing_pdma=0;
#include <asm/sun3xflop.h>
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
static __inline__ unsigned char fd_inb(int port)
{
if(MACH_IS_Q40)
return inb_p(port);
else if(MACH_IS_SUN3X)
return sun3x_82072_fd_inb(port);
return 0;
}
static __inline__ void fd_outb(unsigned char value, int port)
{
if(MACH_IS_Q40)
outb_p(value, port);
else if(MACH_IS_SUN3X)
sun3x_82072_fd_outb(value, port);
}
static int fd_request_irq(void)
{
if(MACH_IS_Q40)
return request_irq(FLOPPY_IRQ, floppy_hardint,
IRQF_DISABLED, "floppy", floppy_hardint);
else if(MACH_IS_SUN3X)
return sun3xflop_request_irq();
return -ENXIO;
}
static void fd_free_irq(void)
{
if(MACH_IS_Q40)
free_irq(FLOPPY_IRQ, floppy_hardint);
}
#define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy")
#define fd_get_dma_residue() vdma_get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) vdma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) vdma_dma_setup(addr, size, mode, io)
#define fd_enable_irq() /* nothing... */
#define fd_disable_irq() /* nothing... */
#define fd_free_dma() /* nothing */
/* No 64k boundary crossing problems on Q40 - no DMA at all */
#define CROSS_64KB(a,s) (0)
#define DMA_MODE_READ 0x44 /* i386 look-alike */
#define DMA_MODE_WRITE 0x48
static int m68k_floppy_init(void)
{
use_virtual_dma =1;
can_use_virtual_dma = 1;
if (MACH_IS_Q40)
return 0x3f0;
else if(MACH_IS_SUN3X)
return sun3xflop_init();
else
return -1;
}
static int vdma_request_dma(unsigned int dmanr, const char * device_id)
{
return 0;
}
static int vdma_get_dma_residue(unsigned int dummy)
{
return virtual_dma_count + virtual_dma_residue;
}
static unsigned long vdma_mem_alloc(unsigned long size)
{
return (unsigned long) vmalloc(size);
}
static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
{
vfree((void *)addr);
}
#define fd_dma_mem_free(addr,size) _fd_dma_mem_free(addr, size)
/* choose_dma_mode ???*/
static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
{
doing_pdma = 1;
virtual_dma_port = (MACH_IS_Q40 ? io : 0);
virtual_dma_mode = (mode == DMA_MODE_WRITE);
virtual_dma_addr = addr;
virtual_dma_count = size;
virtual_dma_residue = 0;
return 0;
}
static void fd_disable_dma(void)
{
doing_pdma = 0;
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
}
/* this is the only truly Q40 specific function */
asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id)
{
register unsigned char st;
#undef TRACE_FLPY_INT
#define NO_FLOPPY_ASSEMBLER
#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
#endif
if(!doing_pdma) {
floppy_interrupt(irq, dev_id);
return IRQ_HANDLED;
}
#ifdef TRACE_FLPY_INT
if(!calls)
bytes = virtual_dma_count;
#endif
{
register int lcount;
register char *lptr;
/* serve 1st byte fast: */
st=1;
for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
st=inb(virtual_dma_port+4) & 0xa0 ;
if(st != 0xa0)
break;
if(virtual_dma_mode)
outb_p(*lptr, virtual_dma_port+5);
else
*lptr = inb_p(virtual_dma_port+5);
}
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
st = inb(virtual_dma_port+4);
}
#ifdef TRACE_FLPY_INT
calls++;
#endif
if(st == 0x20)
return IRQ_HANDLED;
if(!(st & 0x20)) {
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
#ifdef TRACE_FLPY_INT
printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
dma_wait=0;
#endif
doing_pdma = 0;
floppy_interrupt(irq, dev_id);
return IRQ_HANDLED;
}
#ifdef TRACE_FLPY_INT
if(!virtual_dma_count)
dma_wait++;
#endif
return IRQ_HANDLED;
}
#define EXTRA_FLOPPY_PARAMS

21
include/asm-m68k/fpu.h
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@@ -1,21 +0,0 @@
#ifndef __M68K_FPU_H
#define __M68K_FPU_H
/*
* MAX floating point unit state size (FSAVE/FRESTORE)
*/
#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
#define FPSTATESIZE (216)
#elif defined(CONFIG_M68040)
#define FPSTATESIZE (96)
#elif defined(CONFIG_M68KFPU_EMU)
#define FPSTATESIZE (28)
#elif defined(CONFIG_M68060)
#define FPSTATESIZE (12)
#else
#define FPSTATESIZE (0)
#endif
#endif /* __M68K_FPU_H */

6
include/asm-m68k/futex.h
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@@ -1,6 +0,0 @@
#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H
#include <asm-generic/futex.h>
#endif

16
include/asm-m68k/hardirq.h
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@@ -1,16 +0,0 @@
#ifndef __M68K_HARDIRQ_H
#define __M68K_HARDIRQ_H
#include <linux/threads.h>
#include <linux/cache.h>
/* entry.S is sensitive to the offsets of these fields */
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
#define HARDIRQ_BITS 8
#endif

25
include/asm-m68k/hp300hw.h
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@@ -1,25 +0,0 @@
#ifndef _M68K_HP300HW_H
#define _M68K_HP300HW_H
extern unsigned long hp300_model;
/* This information was taken from NetBSD */
#define HP_320 (0) /* 16MHz 68020+HP MMU+16K external cache */
#define HP_330 (1) /* 16MHz 68020+68851 MMU */
#define HP_340 (2) /* 16MHz 68030 */
#define HP_345 (3) /* 50MHz 68030+32K external cache */
#define HP_350 (4) /* 25MHz 68020+HP MMU+32K external cache */
#define HP_360 (5) /* 25MHz 68030 */
#define HP_370 (6) /* 33MHz 68030+64K external cache */
#define HP_375 (7) /* 50MHz 68030+32K external cache */
#define HP_380 (8) /* 25MHz 68040 */
#define HP_385 (9) /* 33MHz 68040 */
#define HP_400 (10) /* 50MHz 68030+32K external cache */
#define HP_425T (11) /* 25MHz 68040 - model 425t */
#define HP_425S (12) /* 25MHz 68040 - model 425s */
#define HP_425E (13) /* 25MHz 68040 - model 425e */
#define HP_433T (14) /* 33MHz 68040 - model 433t */
#define HP_433S (15) /* 33MHz 68040 - model 433s */
#endif /* _M68K_HP300HW_H */

6
include/asm-m68k/hw_irq.h
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@@ -1,6 +0,0 @@
#ifndef __ASM_M68K_HW_IRQ_H
#define __ASM_M68K_HW_IRQ_H
/* Dummy include. */
#endif

15
include/asm-m68k/hwtest.h
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@@ -1,15 +0,0 @@
/* Routines to test for presence/absence of hardware registers:
* see arch/m68k/mm/hwtest.c.
* -- PMM <pmaydell@chiark.greenend.org.uk> 05/1998
*
* Removed __init from decls. We might want them in modules, and
* the code is tiny anyway. 16/5/98 pb
*/
#ifndef __ASM_HWTEST_H
#define __ASM_HWTEST_H
extern int hwreg_present(volatile void *regp);
extern int hwreg_write(volatile void *regp, unsigned short val);
#endif

130
include/asm-m68k/ide.h
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@@ -1,130 +0,0 @@
/*
* linux/include/asm-m68k/ide.h
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*/
/* Copyright(c) 1996 Kars de Jong */
/* Based on the ide driver from 1.2.13pl8 */
/*
* Credits (alphabetical):
*
* - Bjoern Brauel
* - Kars de Jong
* - Torsten Ebeling
* - Dwight Engen
* - Thorsten Floeck
* - Roman Hodek
* - Guenther Kelleter
* - Chris Lawrence
* - Michael Rausch
* - Christian Sauer
* - Michael Schmitz
* - Jes Soerensen
* - Michael Thurm
* - Geert Uytterhoeven
*/
#ifndef _M68K_IDE_H
#define _M68K_IDE_H
#ifdef __KERNEL__
#include <asm/setup.h>
#include <asm/io.h>
#include <asm/irq.h>
#ifdef CONFIG_ATARI
#include <linux/interrupt.h>
#include <asm/atari_stdma.h>
#endif
#ifdef CONFIG_MAC
#include <asm/macints.h>
#endif
/*
* Get rid of defs from io.h - ide has its private and conflicting versions
* Since so far no single m68k platform uses ISA/PCI I/O space for IDE, we
* always use the `raw' MMIO versions
*/
#undef inb
#undef inw
#undef insw
#undef inl
#undef insl
#undef outb
#undef outw
#undef outsw
#undef outl
#undef outsl
#undef readb
#undef readw
#undef readl
#undef writeb
#undef writew
#undef writel
#define inb in_8
#define inw in_be16
#define insw(port, addr, n) raw_insw((u16 *)port, addr, n)
#define inl in_be32
#define insl(port, addr, n) raw_insl((u32 *)port, addr, n)
#define outb(val, port) out_8(port, val)
#define outw(val, port) out_be16(port, val)
#define outsw(port, addr, n) raw_outsw((u16 *)port, addr, n)
#define outl(val, port) out_be32(port, val)
#define outsl(port, addr, n) raw_outsl((u32 *)port, addr, n)
#define readb in_8
#define readw in_be16
#define __ide_mm_insw(port, addr, n) raw_insw((u16 *)port, addr, n)
#define readl in_be32
#define __ide_mm_insl(port, addr, n) raw_insl((u32 *)port, addr, n)
#define writeb(val, port) out_8(port, val)
#define writew(val, port) out_be16(port, val)
#define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n)
#define writel(val, port) out_be32(port, val)
#define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n)
#if defined(CONFIG_ATARI) || defined(CONFIG_Q40)
#define insw_swapw(port, addr, n) raw_insw_swapw((u16 *)port, addr, n)
#define outsw_swapw(port, addr, n) raw_outsw_swapw((u16 *)port, addr, n)
#endif
#ifdef CONFIG_BLK_DEV_FALCON_IDE
#define IDE_ARCH_LOCK
extern int falconide_intr_lock;
static __inline__ void ide_release_lock (void)
{
if (MACH_IS_ATARI) {
if (falconide_intr_lock == 0) {
printk("ide_release_lock: bug\n");
return;
}
falconide_intr_lock = 0;
stdma_release();
}
}
static __inline__ void
ide_get_lock(irq_handler_t handler, void *data)
{
if (MACH_IS_ATARI) {
if (falconide_intr_lock == 0) {
if (in_interrupt() > 0)
panic( "Falcon IDE hasn't ST-DMA lock in interrupt" );
stdma_lock(handler, data);
falconide_intr_lock = 1;
}
}
}
#endif /* CONFIG_BLK_DEV_FALCON_IDE */
#define IDE_ARCH_ACK_INTR
#define ide_ack_intr(hwif) ((hwif)->ack_intr ? (hwif)->ack_intr(hwif) : 1)
#endif /* __KERNEL__ */
#endif /* _M68K_IDE_H */

27
include/asm-m68k/idprom.h
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@@ -1,27 +0,0 @@
#ifndef _M68K_IDPROM_H
#define _M68K_IDPROM_H
/*
* idprom.h: Macros and defines for idprom routines
*
* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
*/
#include <linux/types.h>
struct idprom {
u8 id_format; /* Format identifier (always 0x01) */
u8 id_machtype; /* Machine type */
u8 id_ethaddr[6]; /* Hardware ethernet address */
s32 id_date; /* Date of manufacture */
u32 id_sernum:24; /* Unique serial number */
u8 id_cksum; /* Checksum - xor of the data bytes */
u8 reserved[16];
};
extern struct idprom *idprom;
extern void idprom_init(void);
/* Sun3: in control space */
#define SUN3_IDPROM_BASE 0x00000000
#endif /* !(_M68K_IDPROM_H) */

48
include/asm-m68k/intersil.h
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@@ -1,48 +0,0 @@
#ifndef _SUN3_INTERSIL_H
#define _SUN3_INTERSIL_H
/* bits 0 and 1 */
#define INTERSIL_FREQ_32K 0x00
#define INTERSIL_FREQ_1M 0x01
#define INTERSIL_FREQ_2M 0x02
#define INTERSIL_FREQ_4M 0x03
/* bit 2 */
#define INTERSIL_12H_MODE 0x00
#define INTERSIL_24H_MODE 0x04
/* bit 3 */
#define INTERSIL_STOP 0x00
#define INTERSIL_RUN 0x08
/* bit 4 */
#define INTERSIL_INT_ENABLE 0x10
#define INTERSIL_INT_DISABLE 0x00
/* bit 5 */
#define INTERSIL_MODE_NORMAL 0x00
#define INTERSIL_MODE_TEST 0x20
#define INTERSIL_HZ_100_MASK 0x02
struct intersil_dt {
unsigned char csec;
unsigned char hour;
unsigned char minute;
unsigned char second;
unsigned char month;
unsigned char day;
unsigned char year;
unsigned char weekday;
};
struct intersil_7170 {
struct intersil_dt counter;
struct intersil_dt alarm;
unsigned char int_reg;
unsigned char cmd_reg;
};
extern volatile char* clock_va;
#define intersil_clock ((volatile struct intersil_7170 *) clock_va)
#define intersil_clear() (void)intersil_clock->int_reg
#endif

369
include/asm-m68k/io.h
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@@ -1,369 +0,0 @@
/*
* linux/include/asm-m68k/io.h
*
* 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
* IO access
* - added Q40 support
* - added skeleton for GG-II and Amiga PCMCIA
* 2/3/01 RZ: - moved a few more defs into raw_io.h
*
* inX/outX should not be used by any driver unless it does
* ISA access. Other drivers should use function defined in raw_io.h
* or define its own macros on top of these.
*
* inX(),outX() are for ISA I/O
* isa_readX(),isa_writeX() are for ISA memory
*/
#ifndef _IO_H
#define _IO_H
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <asm/raw_io.h>
#include <asm/virtconvert.h>
#include <asm-generic/iomap.h>
#ifdef CONFIG_ATARI
#include <asm/atarihw.h>
#endif
/*
* IO/MEM definitions for various ISA bridges
*/
#ifdef CONFIG_Q40
#define q40_isa_io_base 0xff400000
#define q40_isa_mem_base 0xff800000
#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
#define MULTI_ISA 0
#endif /* Q40 */
/* GG-II Zorro to ISA bridge */
#ifdef CONFIG_GG2
extern unsigned long gg2_isa_base;
#define GG2_ISA_IO_B(ioaddr) (gg2_isa_base+1+((unsigned long)(ioaddr)*4))
#define GG2_ISA_IO_W(ioaddr) (gg2_isa_base+ ((unsigned long)(ioaddr)*4))
#define GG2_ISA_MEM_B(madr) (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff))
#define GG2_ISA_MEM_W(madr) (gg2_isa_base+ (((unsigned long)(madr)*4) & 0xfffff))
#ifndef MULTI_ISA
#define MULTI_ISA 0
#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
#endif /* GG2 */
#ifdef CONFIG_AMIGA_PCMCIA
#include <asm/amigayle.h>
#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
#ifndef MULTI_ISA
#define MULTI_ISA 0
#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
#endif /* AMIGA_PCMCIA */
#ifdef CONFIG_ISA
#if MULTI_ISA == 0
#undef MULTI_ISA
#endif
#define ISA_TYPE_Q40 (1)
#define ISA_TYPE_GG2 (2)
#define ISA_TYPE_AG (3)
#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
#define ISA_TYPE ISA_TYPE_Q40
#define ISA_SEX 0
#endif
#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
#define ISA_TYPE ISA_TYPE_AG
#define ISA_SEX 1
#endif
#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
#define ISA_TYPE ISA_TYPE_GG2
#define ISA_SEX 0
#endif
#ifdef MULTI_ISA
extern int isa_type;
extern int isa_sex;
#define ISA_TYPE isa_type
#define ISA_SEX isa_sex
#endif
/*
* define inline addr translation functions. Normally only one variant will
* be compiled in so the case statement will be optimised away
*/
static inline u8 __iomem *isa_itb(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr);
#endif
#ifdef CONFIG_GG2
case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_IO_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
static inline u16 __iomem *isa_itw(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr);
#endif
#ifdef CONFIG_GG2
case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_IO_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
static inline u32 __iomem *isa_itl(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr);
#endif
default: return 0; /* avoid warnings, just in case */
}
}
static inline u8 __iomem *isa_mtb(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_GG2
case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u8 __iomem *)addr;
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
static inline u16 __iomem *isa_mtw(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_GG2
case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u16 __iomem *)addr;
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
#define isa_inb(port) in_8(isa_itb(port))
#define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
#define isa_outb(val,port) out_8(isa_itb(port),(val))
#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
#define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
#define isa_readw(p) \
(ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
: in_le16(isa_mtw((unsigned long)(p))))
#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
#define isa_writew(val,p) \
(ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
: out_le16(isa_mtw((unsigned long)(p)),(val)))
static inline void isa_delay(void)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: isa_outb(0,0x80); break;
#endif
#ifdef CONFIG_GG2
case ISA_TYPE_GG2: break;
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: break;
#endif
default: break; /* avoid warnings */
}
}
#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_insw(port, buf, nr) \
(ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
#define isa_outsw(port, buf, nr) \
(ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
#define isa_insl(port, buf, nr) \
(ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \
raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
#define isa_outsl(port, buf, nr) \
(ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
#define inb isa_inb
#define inb_p isa_inb_p
#define outb isa_outb
#define outb_p isa_outb_p
#define inw isa_inw
#define inw_p isa_inw_p
#define outw isa_outw
#define outw_p isa_outw_p
#define inl isa_inl
#define inl_p isa_inl_p
#define outl isa_outl
#define outl_p isa_outl_p
#define insb isa_insb
#define insw isa_insw
#define insl isa_insl
#define outsb isa_outsb
#define outsw isa_outsw
#define outsl isa_outsl
#define readb isa_readb
#define readw isa_readw
#define writeb isa_writeb
#define writew isa_writew
#else /* CONFIG_ISA */
/*
* We need to define dummy functions for GENERIC_IOMAP support.
*/
#define inb(port) 0xff
#define inb_p(port) 0xff
#define outb(val,port) ((void)0)
#define outb_p(val,port) ((void)0)
#define inw(port) 0xffff
#define outw(val,port) ((void)0)
#define inl(port) 0xffffffffUL
#define outl(val,port) ((void)0)
#define insb(port,buf,nr) ((void)0)
#define outsb(port,buf,nr) ((void)0)
#define insw(port,buf,nr) ((void)0)
#define outsw(port,buf,nr) ((void)0)
#define insl(port,buf,nr) ((void)0)
#define outsl(port,buf,nr) ((void)0)
/*
* These should be valid on any ioremap()ed region
*/
#define readb(addr) in_8(addr)
#define writeb(val,addr) out_8((addr),(val))
#define readw(addr) in_le16(addr)
#define writew(val,addr) out_le16((addr),(val))
#endif /* CONFIG_ISA */
#define readl(addr) in_le32(addr)
#define writel(val,addr) out_le32((addr),(val))
#define mmiowb()
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
__builtin_memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
__builtin_memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
__builtin_memcpy((void __force *) dst, src, count);
}
#ifndef CONFIG_SUN3
#define IO_SPACE_LIMIT 0xffff
#else
#define IO_SPACE_LIMIT 0x0fffffff
#endif
#endif /* __KERNEL__ */
#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
#endif /* _IO_H */

1
include/asm-m68k/ioctl.h
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@@ -1 +0,0 @@
#include <asm-generic/ioctl.h>

84
include/asm-m68k/ioctls.h
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@@ -1,84 +0,0 @@
#ifndef __ARCH_M68K_IOCTLS_H__
#define __ARCH_M68K_IOCTLS_H__
#include <asm/ioctl.h>
/* 0x54 is just a magic number to make these relatively unique ('T') */
#define TCGETS 0x5401
#define TCSETS 0x5402
#define TCSETSW 0x5403
#define TCSETSF 0x5404
#define TCGETA 0x5405
#define TCSETA 0x5406
#define TCSETAW 0x5407
#define TCSETAF 0x5408
#define TCSBRK 0x5409
#define TCXONC 0x540A
#define TCFLSH 0x540B
#define TIOCEXCL 0x540C
#define TIOCNXCL 0x540D
#define TIOCSCTTY 0x540E
#define TIOCGPGRP 0x540F
#define TIOCSPGRP 0x5410
#define TIOCOUTQ 0x5411
#define TIOCSTI 0x5412
#define TIOCGWINSZ 0x5413
#define TIOCSWINSZ 0x5414
#define TIOCMGET 0x5415
#define TIOCMBIS 0x5416
#define TIOCMBIC 0x5417
#define TIOCMSET 0x5418
#define TIOCGSOFTCAR 0x5419
#define TIOCSSOFTCAR 0x541A
#define FIONREAD 0x541B
#define TIOCINQ FIONREAD
#define TIOCLINUX 0x541C
#define TIOCCONS 0x541D
#define TIOCGSERIAL 0x541E
#define TIOCSSERIAL 0x541F
#define TIOCPKT 0x5420
#define FIONBIO 0x5421
#define TIOCNOTTY 0x5422
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID 0x5429 /* Return the session ID of FD */
#define TCGETS2 _IOR('T',0x2A, struct termios2)
#define TCSETS2 _IOW('T',0x2B, struct termios2)
#define TCSETSW2 _IOW('T',0x2C, struct termios2)
#define TCSETSF2 _IOW('T',0x2D, struct termios2)
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
#define FIOCLEX 0x5451
#define FIOASYNC 0x5452
#define TIOCSERCONFIG 0x5453
#define TIOCSERGWILD 0x5454
#define TIOCSERSWILD 0x5455
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
#define TIOCSERGETLSR 0x5459 /* Get line status register */
#define TIOCSERGETMULTI 0x545A /* Get multiport config */
#define TIOCSERSETMULTI 0x545B /* Set multiport config */
#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
#define FIOQSIZE 0x545E
/* Used for packet mode */
#define TIOCPKT_DATA 0
#define TIOCPKT_FLUSHREAD 1
#define TIOCPKT_FLUSHWRITE 2
#define TIOCPKT_STOP 4
#define TIOCPKT_START 8
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
#endif /* __ARCH_M68K_IOCTLS_H__ */

29
include/asm-m68k/ipcbuf.h
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@@ -1,29 +0,0 @@
#ifndef __m68k_IPCBUF_H__
#define __m68k_IPCBUF_H__
/*
* The user_ipc_perm structure for m68k architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
*
* Pad space is left for:
* - 32-bit mode_t and seq
* - 2 miscellaneous 32-bit values
*/
struct ipc64_perm
{
__kernel_key_t key;
__kernel_uid32_t uid;
__kernel_gid32_t gid;
__kernel_uid32_t cuid;
__kernel_gid32_t cgid;
__kernel_mode_t mode;
unsigned short __pad1;
unsigned short seq;
unsigned short __pad2;
unsigned long __unused1;
unsigned long __unused2;
};
#endif /* __m68k_IPCBUF_H__ */

125
include/asm-m68k/irq.h
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@@ -1,125 +0,0 @@
#ifndef _M68K_IRQ_H_
#define _M68K_IRQ_H_
#include <linux/linkage.h>
#include <linux/hardirq.h>
#include <linux/spinlock_types.h>
/*
* This should be the same as the max(NUM_X_SOURCES) for all the
* different m68k hosts compiled into the kernel.
* Currently the Atari has 72 and the Amiga 24, but if both are
* supported in the kernel it is better to make room for 72.
*/
#if defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
#define NR_IRQS 200
#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
#define NR_IRQS 72
#elif defined(CONFIG_Q40)
#define NR_IRQS 43
#elif defined(CONFIG_AMIGA)
#define NR_IRQS 32
#elif defined(CONFIG_APOLLO)
#define NR_IRQS 24
#elif defined(CONFIG_HP300)
#define NR_IRQS 8
#else
#define NR_IRQS 0
#endif
/*
* The hardirq mask has to be large enough to have
* space for potentially all IRQ sources in the system
* nesting on a single CPU:
*/
#if (1 << HARDIRQ_BITS) < NR_IRQS
# error HARDIRQ_BITS is too low!
#endif
/*
* Interrupt source definitions
* General interrupt sources are the level 1-7.
* Adding an interrupt service routine for one of these sources
* results in the addition of that routine to a chain of routines.
* Each one is called in succession. Each individual interrupt
* service routine should determine if the device associated with
* that routine requires service.
*/
#define IRQ_SPURIOUS 0
#define IRQ_AUTO_1 1 /* level 1 interrupt */
#define IRQ_AUTO_2 2 /* level 2 interrupt */
#define IRQ_AUTO_3 3 /* level 3 interrupt */
#define IRQ_AUTO_4 4 /* level 4 interrupt */
#define IRQ_AUTO_5 5 /* level 5 interrupt */
#define IRQ_AUTO_6 6 /* level 6 interrupt */
#define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
#define IRQ_USER 8
extern unsigned int irq_canonicalize(unsigned int irq);
struct pt_regs;
/*
* various flags for request_irq() - the Amiga now uses the standard
* mechanism like all other architectures - IRQF_DISABLED and
* IRQF_SHARED are your friends.
*/
#ifndef MACH_AMIGA_ONLY
#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */
#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */
#define IRQ_FLG_FAST (0x0004)
#define IRQ_FLG_SLOW (0x0008)
#define IRQ_FLG_STD (0x8000) /* internally used */
#endif
/*
* This structure is used to chain together the ISRs for a particular
* interrupt source (if it supports chaining).
*/
typedef struct irq_node {
int (*handler)(int, void *);
void *dev_id;
struct irq_node *next;
unsigned long flags;
const char *devname;
} irq_node_t;
/*
* This structure has only 4 elements for speed reasons
*/
struct irq_handler {
int (*handler)(int, void *);
unsigned long flags;
void *dev_id;
const char *devname;
};
struct irq_controller {
const char *name;
spinlock_t lock;
int (*startup)(unsigned int irq);
void (*shutdown)(unsigned int irq);
void (*enable)(unsigned int irq);
void (*disable)(unsigned int irq);
};
extern int m68k_irq_startup(unsigned int);
extern void m68k_irq_shutdown(unsigned int);
/*
* This function returns a new irq_node_t
*/
extern irq_node_t *new_irq_node(void);
extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, struct pt_regs *));
extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt,
void (*handler)(unsigned int, struct pt_regs *));
extern void m68k_setup_irq_controller(struct irq_controller *, unsigned int, unsigned int);
asmlinkage void m68k_handle_int(unsigned int);
asmlinkage void __m68k_handle_int(unsigned int, struct pt_regs *);
#endif /* _M68K_IRQ_H_ */

1
include/asm-m68k/irq_regs.h
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@@ -1 +0,0 @@
#include <asm-generic/irq_regs.h>

1
include/asm-m68k/kdebug.h
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@@ -1 +0,0 @@
#include <asm-generic/kdebug.h>

21
include/asm-m68k/kmap_types.h
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@@ -1,21 +0,0 @@
#ifndef __ASM_M68K_KMAP_TYPES_H
#define __ASM_M68K_KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_SUNRPC_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BIO_SRC_IRQ,
KM_BIO_DST_IRQ,
KM_PTE0,
KM_PTE1,
KM_IRQ0,
KM_IRQ1,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_TYPE_NR
};
#endif /* __ASM_M68K_KMAP_TYPES_H */

7
include/asm-m68k/linkage.h
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@@ -1,7 +0,0 @@
#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
#define __ALIGN .align 4
#define __ALIGN_STR ".align 4"
#endif

6
include/asm-m68k/local.h
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@@ -1,6 +0,0 @@
#ifndef _ASM_M68K_LOCAL_H
#define _ASM_M68K_LOCAL_H
#include <asm-generic/local.h>
#endif /* _ASM_M68K_LOCAL_H */

27
include/asm-m68k/mac_asc.h
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@@ -1,27 +0,0 @@
/*
* Apple Sound Chip
*/
#ifndef __ASM_MAC_ASC_H
#define __ASM_MAC_ASC_H
/*
* ASC offsets and controls
*/
#define ASC_BUF_BASE 0x00 /* RAM buffer offset */
#define ASC_BUF_SIZE 0x800
#define ASC_CONTROL 0x800
#define ASC_CONTROL_OFF 0x00
#define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte))
#define ASC_ENABLE 0x801
#define ASC_ENABLE_SAMPLE 0x02
#define ASC_MODE 0x802
#define ASC_MODE_SAMPLE 0x02
#define ASC_VOLUME 0x806
#define ASC_CHAN 0x807 /* ??? */
#endif

32
include/asm-m68k/mac_baboon.h
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@@ -1,32 +0,0 @@
/*
* Definitions for the "Baboon" custom IC on the PowerBook 190.
*/
#define BABOON_BASE (0x50F1A000) /* same as IDE controller base */
#ifndef __ASSEMBLY__
struct baboon {
char pad1[208]; /* generic IDE registers, not used here */
short mb_control; /* Control register:
* bit 5 : slot 2 power control
* bit 6 : slot 1 power control
*/
char pad2[2];
short mb_status; /* (0xD4) media bay status register:
*
* bit 0: ????
* bit 1: IDE interrupt active?
* bit 2: bay status, 0 = full, 1 = empty
* bit 3: ????
*/
char pad3[2]; /* (0xD6) not used */
short mb_ifr; /* (0xD8) media bay interrupt flags register:
*
* bit 0: ????
* bit 1: IDE controller interrupt
* bit 2: media bay status change interrupt
*/
};
#endif /* __ASSEMBLY **/

162
include/asm-m68k/mac_iop.h
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@@ -1,162 +0,0 @@
/*
* I/O Processor (IOP) defines and structures, mostly snagged from A/UX
* header files.
*
* The original header from which this was taken is copyrighted. I've done some
* rewriting (in fact my changes make this a bit more readable, IMHO) but some
* more should be done.
*/
/*
* This is the base address of the IOPs. Use this as the address of
* a "struct iop" (see below) to see where the actual registers fall.
*/
#define SCC_IOP_BASE_IIFX (0x50F04000)
#define ISM_IOP_BASE_IIFX (0x50F12000)
#define SCC_IOP_BASE_QUADRA (0x50F0C000)
#define ISM_IOP_BASE_QUADRA (0x50F1E000)
/* IOP status/control register bits: */
#define IOP_BYPASS 0x01 /* bypass-mode hardware access */
#define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */
#define IOP_RUN 0x04 /* set to 0 to reset IOP chip */
#define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */
#define IOP_INT0 0x10 /* intr priority from IOP to host */
#define IOP_INT1 0x20 /* intr priority from IOP to host */
#define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */
#define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */
#define NUM_IOPS 2
#define NUM_IOP_CHAN 7
#define NUM_IOP_MSGS NUM_IOP_CHAN*8
#define IOP_MSG_LEN 32
/* IOP reference numbers, used by the globally-visible iop_xxx functions */
#define IOP_NUM_SCC 0
#define IOP_NUM_ISM 1
/* IOP channel states */
#define IOP_MSG_IDLE 0 /* idle */
#define IOP_MSG_NEW 1 /* new message sent */
#define IOP_MSG_RCVD 2 /* message received; processing */
#define IOP_MSG_COMPLETE 3 /* message processing complete */
/* IOP message status codes */
#define IOP_MSGSTATUS_UNUSED 0 /* Unusued message structure */
#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */
#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */
#define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */
/* IOP memory addresses of the members of the mac_iop_kernel structure. */
#define IOP_ADDR_MAX_SEND_CHAN 0x0200
#define IOP_ADDR_SEND_STATE 0x0201
#define IOP_ADDR_PATCH_CTRL 0x021F
#define IOP_ADDR_SEND_MSG 0x0220
#define IOP_ADDR_MAX_RECV_CHAN 0x0300
#define IOP_ADDR_RECV_STATE 0x0301
#define IOP_ADDR_ALIVE 0x031F
#define IOP_ADDR_RECV_MSG 0x0320
#ifndef __ASSEMBLY__
/*
* IOP Control registers, staggered because in usual Apple style they were
* too lazy to decode the A0 bit. This structure is assumed to begin at
* one of the xxx_IOP_BASE addresses given above.
*/
struct mac_iop {
__u8 ram_addr_hi; /* shared RAM address hi byte */
__u8 pad0;
__u8 ram_addr_lo; /* shared RAM address lo byte */
__u8 pad1;
__u8 status_ctrl; /* status/control register */
__u8 pad2[3];
__u8 ram_data; /* RAM data byte at ramhi/lo */
__u8 pad3[23];
/* Bypass-mode hardware access registers */
union {
struct { /* SCC registers */
__u8 sccb_cmd; /* SCC B command reg */
__u8 pad4;
__u8 scca_cmd; /* SCC A command reg */
__u8 pad5;
__u8 sccb_data; /* SCC B data */
__u8 pad6;
__u8 scca_data; /* SCC A data */
} scc_regs;
struct { /* ISM registers */
__u8 wdata; /* write a data byte */
__u8 pad7;
__u8 wmark; /* write a mark byte */
__u8 pad8;
__u8 wcrc; /* write 2-byte crc to disk */
__u8 pad9;
__u8 wparams; /* write the param regs */
__u8 pad10;
__u8 wphase; /* write the phase states & dirs */
__u8 pad11;
__u8 wsetup; /* write the setup register */
__u8 pad12;
__u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */
__u8 pad13;
__u8 wones; /* mode reg: 1's set bits, 0's are x */
__u8 pad14;
__u8 rdata; /* read a data byte */
__u8 pad15;
__u8 rmark; /* read a mark byte */
__u8 pad16;
__u8 rerror; /* read the error register */
__u8 pad17;
__u8 rparams; /* read the param regs */
__u8 pad18;
__u8 rphase; /* read the phase states & dirs */
__u8 pad19;
__u8 rsetup; /* read the setup register */
__u8 pad20;
__u8 rmode; /* read the mode register */
__u8 pad21;
__u8 rhandshake; /* read the handshake register */
} ism_regs;
} b;
};
/* This structure is used to track IOP messages in the Linux kernel */
struct iop_msg {
struct iop_msg *next; /* next message in queue or NULL */
uint iop_num; /* IOP number */
uint channel; /* channel number */
void *caller_priv; /* caller private data */
int status; /* status of this message */
__u8 message[IOP_MSG_LEN]; /* the message being sent/received */
__u8 reply[IOP_MSG_LEN]; /* the reply to the message */
void (*handler)(struct iop_msg *);
/* function to call when reply recvd */
};
extern int iop_scc_present,iop_ism_present;
extern int iop_listen(uint, uint,
void (*handler)(struct iop_msg *),
const char *);
extern int iop_send_message(uint, uint, void *, uint, __u8 *,
void (*)(struct iop_msg *));
extern void iop_complete_message(struct iop_msg *);
extern void iop_upload_code(uint, __u8 *, uint, __u16);
extern void iop_download_code(uint, __u8 *, uint, __u16);
extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16);
#endif /* __ASSEMBLY__ */

23
include/asm-m68k/mac_mouse.h
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@@ -1,23 +0,0 @@
#ifndef _ASM_MAC_MOUSE_H
#define _ASM_MAC_MOUSE_H
/*
* linux/include/asm-m68k/mac_mouse.h
* header file for Macintosh ADB mouse driver
* 27-10-97 Michael Schmitz
* copied from:
* header file for Atari Mouse driver
* by Robert de Vries (robert@and.nl) on 19Jul93
*/
struct mouse_status {
char buttons;
short dx;
short dy;
int ready;
int active;
wait_queue_head_t wait;
struct fasync_struct *fasyncptr;
};
#endif

94
include/asm-m68k/mac_oss.h
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@@ -1,94 +0,0 @@
/*
* OSS
*
* This is used in place of VIA2 on the IIfx.
*/
#define OSS_BASE (0x50f1a000)
/*
* Interrupt level offsets for mac_oss->irq_level
*/
#define OSS_NUBUS0 0
#define OSS_NUBUS1 1
#define OSS_NUBUS2 2
#define OSS_NUBUS3 3
#define OSS_NUBUS4 4
#define OSS_NUBUS5 5
#define OSS_IOPISM 6
#define OSS_IOPSCC 7
#define OSS_SOUND 8
#define OSS_SCSI 9
#define OSS_60HZ 10
#define OSS_VIA1 11
#define OSS_UNUSED1 12
#define OSS_UNUSED2 13
#define OSS_PARITY 14
#define OSS_UNUSED3 15
#define OSS_NUM_SOURCES 16
/*
* Pending interrupt bits in mac_oss->irq_pending
*/
#define OSS_IP_NUBUS0 0x0001
#define OSS_IP_NUBUS1 0x0002
#define OSS_IP_NUBUS2 0x0004
#define OSS_IP_NUBUS3 0x0008
#define OSS_IP_NUBUS4 0x0010
#define OSS_IP_NUBUS5 0x0020
#define OSS_IP_IOPISM 0x0040
#define OSS_IP_IOPSCC 0x0080
#define OSS_IP_SOUND 0x0100
#define OSS_IP_SCSI 0x0200
#define OSS_IP_60HZ 0x0400
#define OSS_IP_VIA1 0x0800
#define OSS_IP_UNUSED1 0x1000
#define OSS_IP_UNUSED2 0x2000
#define OSS_IP_PARITY 0x4000
#define OSS_IP_UNUSED3 0x8000
#define OSS_IP_NUBUS (OSS_IP_NUBUS0|OSS_IP_NUBUS1|OSS_IP_NUBUS2|OSS_IP_NUBUS3|OSS_IP_NUBUS4|OSS_IP_NUBUS5)
/*
* Rom Control Register
*/
#define OSS_POWEROFF 0x80
/*
* OSS Interrupt levels for various sub-systems
*
* This mapping is layed out with two things in mind: first, we try to keep
* things on their own levels to avoid having to do double-dispatches. Second,
* the levels match as closely as possible the alternate IRQ mapping mode (aka
* "A/UX mode") available on some VIA machines.
*/
#define OSS_IRQLEV_DISABLED 0
#define OSS_IRQLEV_IOPISM 1 /* ADB? */
#define OSS_IRQLEV_SCSI IRQ_AUTO_2
#define OSS_IRQLEV_NUBUS IRQ_AUTO_3 /* keep this on its own level */
#define OSS_IRQLEV_IOPSCC IRQ_AUTO_4 /* matches VIA alternate mapping */
#define OSS_IRQLEV_SOUND IRQ_AUTO_5 /* matches VIA alternate mapping */
#define OSS_IRQLEV_60HZ 6 /* matches VIA alternate mapping */
#define OSS_IRQLEV_VIA1 IRQ_AUTO_6 /* matches VIA alternate mapping */
#define OSS_IRQLEV_PARITY 7 /* matches VIA alternate mapping */
#ifndef __ASSEMBLY__
struct mac_oss {
__u8 irq_level[0x10]; /* [0x000-0x00f] Interrupt levels */
__u8 padding0[0x1F2]; /* [0x010-0x201] IO space filler */
__u16 irq_pending; /* [0x202-0x203] pending interrupts bits */
__u8 rom_ctrl; /* [0x204-0x204] ROM cntl reg (for poweroff) */
__u8 padding1[0x2]; /* [0x205-0x206] currently unused by A/UX */
__u8 ack_60hz; /* [0x207-0x207] 60 Hz ack. */
};
extern volatile struct mac_oss *oss;
extern int oss_present;
#endif /* __ASSEMBLY__ */

248
include/asm-m68k/mac_psc.h
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@@ -1,248 +0,0 @@
/*
* Apple Peripheral System Controller (PSC)
*
* The PSC is used on the AV Macs to control IO functions not handled
* by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
* channels.
*
* The first seven DMA channels appear to be "one-shot" and are actually
* sets of two channels; one member is active while the other is being
* configured, and then you flip the active member and start all over again.
* The one-shot channels are grouped together and are:
*
* 1. SCSI
* 2. Ethernet Read
* 3. Ethernet Write
* 4. Floppy Disk Controller
* 5. SCC Channel A Receive
* 6. SCC Channel B Receive
* 7. SCC Channel A Transmit
*
* The remaining two channels are handled somewhat differently. They appear
* to be closely tied and share one set of registers. They also seem to run
* continuously, although how you keep the buffer filled in this scenario is
* not understood as there seems to be only one input and one output buffer
* pointer.
*
* Much of this was extrapolated from what was known about the Ethernet
* registers and subsequently confirmed using MacsBug (ie by pinging the
* machine with easy-to-find patterns and looking for them in the DMA
* buffers, or by sending a file over the serial ports and finding the
* file in the buffers.)
*
* 1999-05-25 (jmt)
*/
#define PSC_BASE (0x50F31000)
/*
* The IER/IFR registers work like the VIA, except that it has 4
* of them each on different interrupt levels, and each register
* set only seems to handle four interrupts instead of seven.
*
* To access a particular set of registers, add 0xn0 to the base
* where n = 3,4,5 or 6.
*/
#define pIFRbase 0x100
#define pIERbase 0x104
/*
* One-shot DMA control registers
*/
#define PSC_MYSTERY 0x804
#define PSC_CTL_BASE 0xC00
#define PSC_SCSI_CTL 0xC00
#define PSC_ENETRD_CTL 0xC10
#define PSC_ENETWR_CTL 0xC20
#define PSC_FDC_CTL 0xC30
#define PSC_SCCA_CTL 0xC40
#define PSC_SCCB_CTL 0xC50
#define PSC_SCCATX_CTL 0xC60
/*
* DMA channels. Add +0x10 for the second channel in the set.
* You're supposed to use one channel while the other runs and
* then flip channels and do the whole thing again.
*/
#define PSC_ADDR_BASE 0x1000
#define PSC_LEN_BASE 0x1004
#define PSC_CMD_BASE 0x1008
#define PSC_SET0 0x00
#define PSC_SET1 0x10
#define PSC_SCSI_ADDR 0x1000 /* confirmed */
#define PSC_SCSI_LEN 0x1004 /* confirmed */
#define PSC_SCSI_CMD 0x1008 /* confirmed */
#define PSC_ENETRD_ADDR 0x1020 /* confirmed */
#define PSC_ENETRD_LEN 0x1024 /* confirmed */
#define PSC_ENETRD_CMD 0x1028 /* confirmed */
#define PSC_ENETWR_ADDR 0x1040 /* confirmed */
#define PSC_ENETWR_LEN 0x1044 /* confirmed */
#define PSC_ENETWR_CMD 0x1048 /* confirmed */
#define PSC_FDC_ADDR 0x1060 /* strongly suspected */
#define PSC_FDC_LEN 0x1064 /* strongly suspected */
#define PSC_FDC_CMD 0x1068 /* strongly suspected */
#define PSC_SCCA_ADDR 0x1080 /* confirmed */
#define PSC_SCCA_LEN 0x1084 /* confirmed */
#define PSC_SCCA_CMD 0x1088 /* confirmed */
#define PSC_SCCB_ADDR 0x10A0 /* confirmed */
#define PSC_SCCB_LEN 0x10A4 /* confirmed */
#define PSC_SCCB_CMD 0x10A8 /* confirmed */
#define PSC_SCCATX_ADDR 0x10C0 /* confirmed */
#define PSC_SCCATX_LEN 0x10C4 /* confirmed */
#define PSC_SCCATX_CMD 0x10C8 /* confirmed */
/*
* Free-running DMA registers. The only part known for sure are the bits in
* the control register, the buffer addresses and the buffer length. Everything
* else is anybody's guess.
*
* These registers seem to be mirrored every thirty-two bytes up until offset
* 0x300. It's safe to assume then that a new set of registers starts there.
*/
#define PSC_SND_CTL 0x200 /*
* [ 16-bit ]
* Sound (Singer?) control register.
*
* bit 0 : ????
* bit 1 : ????
* bit 2 : Set to one to enable sound
* output. Possibly a mute flag.
* bit 3 : ????
* bit 4 : ????
* bit 5 : ????
* bit 6 : Set to one to enable pass-thru
* audio. In this mode the audio data
* seems to appear in both the input
* buffer and the output buffer.
* bit 7 : Set to one to activate the
* sound input DMA or zero to
* disable it.
* bit 8 : Set to one to activate the
* sound output DMA or zero to
* disable it.
* bit 9 : \
* bit 11 : |
* These two bits control the sample
* rate. Usually set to binary 10 and
* MacOS 8.0 says I'm at 48 KHz. Using
* a binary value of 01 makes things
* sound about 1/2 speed (24 KHz?) and
* binary 00 is slower still (22 KHz?)
*
* Setting this to 0x0000 is a good way to
* kill all DMA at boot time so that the
* PSC won't overwrite the kernel image
* with sound data.
*/
/*
* 0x0202 - 0x0203 is unused. Writing there
* seems to clobber the control register.
*/
#define PSC_SND_SOURCE 0x204 /*
* [ 32-bit ]
* Controls input source and volume:
*
* bits 12-15 : input source volume, 0 - F
* bits 16-19 : unknown, always 0x5
* bits 20-23 : input source selection:
* 0x3 = CD Audio
* 0x4 = External Audio
*
* The volume is definitely not the general
* output volume as it doesn't affect the
* alert sound volume.
*/
#define PSC_SND_STATUS1 0x208 /*
* [ 32-bit ]
* Appears to be a read-only status register.
* The usual value is 0x00400002.
*/
#define PSC_SND_HUH3 0x20C /*
* [ 16-bit ]
* Unknown 16-bit value, always 0x0000.
*/
#define PSC_SND_BITS2GO 0x20E /*
* [ 16-bit ]
* Counts down to zero from some constant
* value. The value appears to be the
* number of _bits_ remaining before the
* buffer is full, which would make sense
* since Apple's docs say the sound DMA
* channels are 1 bit wide.
*/
#define PSC_SND_INADDR 0x210 /*
* [ 32-bit ]
* Address of the sound input DMA buffer
*/
#define PSC_SND_OUTADDR 0x214 /*
* [ 32-bit ]
* Address of the sound output DMA buffer
*/
#define PSC_SND_LEN 0x218 /*
* [ 16-bit ]
* Length of both buffers in eight-byte units.
*/
#define PSC_SND_HUH4 0x21A /*
* [ 16-bit ]
* Unknown, always 0x0000.
*/
#define PSC_SND_STATUS2 0x21C /*
* [ 16-bit ]
* Appears to e a read-only status register.
* The usual value is 0x0200.
*/
#define PSC_SND_HUH5 0x21E /*
* [ 16-bit ]
* Unknown, always 0x0000.
*/
#ifndef __ASSEMBLY__
extern volatile __u8 *psc;
extern int psc_present;
/*
* Access functions
*/
static inline void psc_write_byte(int offset, __u8 data)
{
*((volatile __u8 *)(psc + offset)) = data;
}
static inline void psc_write_word(int offset, __u16 data)
{
*((volatile __u16 *)(psc + offset)) = data;
}
static inline void psc_write_long(int offset, __u32 data)
{
*((volatile __u32 *)(psc + offset)) = data;
}
static inline u8 psc_read_byte(int offset)
{
return *((volatile __u8 *)(psc + offset));
}
static inline u16 psc_read_word(int offset)
{
return *((volatile __u16 *)(psc + offset));
}
static inline u32 psc_read_long(int offset)
{
return *((volatile __u32 *)(psc + offset));
}
#endif /* __ASSEMBLY__ */

267
include/asm-m68k/mac_via.h
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/*
* 6522 Versatile Interface Adapter (VIA)
*
* There are two of these on the Mac II. Some IRQ's are vectored
* via them as are assorted bits and bobs - eg rtc, adb. The picture
* is a bit incomplete as the Mac documentation doesn't cover this well
*/
#ifndef _ASM_MAC_VIA_H_
#define _ASM_MAC_VIA_H_
/*
* Base addresses for the VIAs. There are two in every machine,
* although on some machines the second is an RBV or an OSS.
* The OSS is different enough that it's handled separately.
*
* Do not use these values directly; use the via1 and via2 variables
* instead (and don't forget to check rbv_present when using via2!)
*/
#define VIA1_BASE (0x50F00000)
#define VIA2_BASE (0x50F02000)
#define RBV_BASE (0x50F26000)
/*
* Not all of these are true post MacII I think.
* CSA: probably the ones CHRP marks as 'unused' change purposes
* when the IWM becomes the SWIM.
* http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
* ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
*
* also, http://developer.apple.com/technotes/hw/hw_09.html claims the
* following changes for IIfx:
* VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
* Also, "All of the functionality of VIA2 has been moved to other chips".
*/
#define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
* [CHRP] SCC WREQ: Reflects the state of the
* Wait/Request pins from the SCC.
* [Macintosh Family Hardware]
* as CHRP on SE/30,II,IIx,IIcx,IIci.
* on IIfx, "0 means an active request"
*/
#define VIA1A_vRev8 0x40 /* Revision 8 board ???
* [CHRP] En WaitReqB: Lets the WaitReq_L
* signal from port B of the SCC appear on
* the PA7 input pin. Output.
* [Macintosh Family] On the SE/30, this
* is the bit to flip screen buffers.
* 0=alternate, 1=main.
* on II,IIx,IIcx,IIci,IIfx this is a bit
* for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
*/
#define VIA1A_vHeadSel 0x20 /* Head select for IWM.
* [CHRP] unused.
* [Macintosh Family] "Floppy disk
* state-control line SEL" on all but IIfx
*/
#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
* this bit enables the "Overlay" address
* map in the address decoders as it is on
* reset for mapping the ROM over the reset
* vector. 1=use overlay map.
* On the IIci,IIfx it is another bit of the
* CPU ID: 0=normal IIci, 1=IIci with parity
* feature or IIfx.
* [CHRP] En WaitReqA: Lets the WaitReq_L
* signal from port A of the SCC appear
* on the PA7 input pin (CHRP). Output.
* [MkLinux] "Drive Select"
* (with 0x20 being 'disk head select')
*/
#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
* 1: select the external serial clock to
* drive the SCC's /RTxCA pin.
* 0: Select the 3.6864MHz clock to drive
* the SCC cell.
* [Macintosh Family] Correct on all but IIfx
*/
/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
* on Macs which had the PWM sound hardware. Reserved on newer models.
* On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
* bit 2: 1=IIci, 0=IIfx
* bit 1: 1 on both IIci and IIfx.
* MkLinux sez bit 0 is 'burnin flag' in this case.
* CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
* inputs, these bits will read 0.
*/
#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
/* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
* CHRP offers no info. */
#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
* PWM hardware) 0=enabled.
* Also, on IIci w/parity, shows parity error
* 0=error, 1=OK. */
#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
* On SE/30, vertical sync interrupt enable.
* 0=enabled. This vSync interrupt shows up
* as a slot $E interrupt. */
#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
/* MkLinux defines the following "VIA1 Register B contents where they
* differ from standard VIA1". From the naming scheme, we assume they
* correspond to a VIA work-alike named 'EVR'. */
#define EVRB_XCVR 0x08 /* XCVR_SESSION* */
#define EVRB_FULL 0x10 /* VIA_FULL */
#define EVRB_SYSES 0x20 /* SYS_SESSION */
#define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */
#define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */
#define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */
#define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
/*
* VIA2 A register is the interrupt lines raised off the nubus
* slots.
* The below info is from 'Macintosh Family Hardware.'
* MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
* It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and
* defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
* Perhaps OSS uses vRAM1 and vRAM2 for ADB.
*/
#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
/* RAM size bits decoded as follows:
* bit1 bit0 size of ICs in bank A
* 0 0 256 kbit
* 0 1 1 Mbit
* 1 0 4 Mbit
* 1 1 16 Mbit
*/
/*
* Register B has the fun stuff in it
*/
#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
* timer T1.
* on IIci, parity test: 0=test mode.
* [MkLinux] RBV_PARODD: 1=odd,0=even. */
#define VIA2B_vSndJck 0x40 /* External sound jack status.
* 0=plug is inserted. On SE/30, always 0 */
#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
* on II, AMU/PMMU control.
* if AMU, 0=24bit to 32bit translation
* if PMMU, 1=PMMU is accessing page table.
* on SE/30 tied low.
* on IIx,IIcx,IIfx, unused.
* on IIci/RBV, cache control. 0=flush cache.
*/
#define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
* on SE/30 this signal sent to PDS card. */
#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
* on SE/30 sent to PDS card. */
#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
* on others, 0=disable processor's instruction
* and data caches. */
/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html
* Another example of a valid function that has no ROM support is the use
* of the alternate video page for page-flipping animation. Since there
* is no ROM call to flip pages, it is necessary to go play with the
* right bit in the VIA chip (6522 Versatile Interface Adapter).
* [CSA: don't know which one this is, but it's one of 'em!]
*/
/*
* 6522 registers - see databook.
* CSA: Assignments for VIA1 confirmed from CHRP spec.
*/
/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
/* Note: 15 VIA regs, 8 RBV regs */
#define vBufB 0x0000 /* [VIA/RBV] Register B */
#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
#define vSR 0x1400 /* [VIA only] Shift register. */
#define vACR 0x1600 /* [VIA only] Auxilary control register. */
#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
/* CHRP sez never ever to *write* this.
* Mac family says never to *change* this.
* In fact we need to initialize it once at start. */
#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
/* The RBV only decodes the bottom eight address lines; the VIA doesn't
* decode the bottom eight -- so vBufB | rBufB will always get you BufB */
/* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
* BUT note the values for rIER and rIFR, where the top 8 bits *do* seem
* to matter. In fact *all* of the top 8 bits seem to matter;
* setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
* Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
*/
#define rBufB 0x0000 /* [VIA/RBV] Register B */
#define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
#define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
#define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
#define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
#define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
#define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
#define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
#define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */
/*
* Video monitor parameters, for rMonP:
*/
#define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
#define RBV_MONID 0x38 /* monitor type, as below. */
#define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
/* Supported monitor types: */
#define MON_15BW (1<<3) /* 15" BW portrait. */
#define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */
#define MON_15RGB (5<<3) /* 15" RGB portrait. */
#define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */
#define MON_NONE (7<<3) /* No monitor attached. */
/* To clarify IER manipulations */
#define IER_SET_BIT(b) (0x80 | (1<<(b)) )
#define IER_CLR_BIT(b) (0x7F & (1<<(b)) )
#ifndef __ASSEMBLY__
extern volatile __u8 *via1,*via2;
extern int rbv_present,via_alt_mapping;
static inline int rbv_set_video_bpp(int bpp)
{
char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1;
if (!rbv_present || val<0) return -1;
via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val;
return 0;
}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_MAC_VIA_H_ */

35
include/asm-m68k/machdep.h
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#ifndef _M68K_MACHDEP_H
#define _M68K_MACHDEP_H
#include <linux/seq_file.h>
#include <linux/interrupt.h>
struct pt_regs;
struct mktime;
struct rtc_time;
struct rtc_pll_info;
struct buffer_head;
extern void (*mach_sched_init) (irq_handler_t handler);
/* machine dependent irq functions */
extern void (*mach_init_IRQ) (void);
extern void (*mach_get_model) (char *model);
extern void (*mach_get_hardware_list) (struct seq_file *m);
/* machine dependent timer functions */
extern unsigned long (*mach_gettimeoffset)(void);
extern int (*mach_hwclk)(int, struct rtc_time*);
extern unsigned int (*mach_get_ss)(void);
extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_clock_mmss)(unsigned long);
extern void (*mach_reset)( void );
extern void (*mach_halt)( void );
extern void (*mach_power_off)( void );
extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
extern void (*mach_hd_setup)(char *, int *);
extern long mach_max_dma_address;
extern void (*mach_heartbeat) (int);
extern void (*mach_l2_flush) (int);
extern void (*mach_beep) (unsigned int, unsigned int);
#endif /* _M68K_MACHDEP_H */

85
include/asm-m68k/machines.h
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/*
* machines.h: Defines for taking apart the machine type value in the
* idprom and determining the kind of machine we are on.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Sun3/3x models added by David Monro (davidm@psrg.cs.usyd.edu.au)
*/
#ifndef _SPARC_MACHINES_H
#define _SPARC_MACHINES_H
struct Sun_Machine_Models {
char *name;
unsigned char id_machtype;
};
/* Current number of machines we know about that has an IDPROM
* machtype entry including one entry for the 0x80 OBP machines.
*/
// reduced along with table in arch/m68k/sun3/idprom.c
// sun3 port doesn't need to know about sparc machines.
//#define NUM_SUN_MACHINES 23
#define NUM_SUN_MACHINES 8
/* The machine type in the idprom area looks like this:
*
* ---------------
* | ARCH | MACH |
* ---------------
* 7 4 3 0
*
* The ARCH field determines the architecture line (sun4, sun4c, etc).
* The MACH field determines the machine make within that architecture.
*/
#define SM_ARCH_MASK 0xf0
#define SM_SUN3 0x10
#define SM_SUN4 0x20
#define SM_SUN3X 0x40
#define SM_SUN4C 0x50
#define SM_SUN4M 0x70
#define SM_SUN4M_OBP 0x80
#define SM_TYP_MASK 0x0f
/* Sun3 machines */
#define SM_3_160 0x01 /* Sun 3/160 series */
#define SM_3_50 0x02 /* Sun 3/50 series */
#define SM_3_260 0x03 /* Sun 3/260 series */
#define SM_3_110 0x04 /* Sun 3/110 series */
#define SM_3_60 0x07 /* Sun 3/60 series */
#define SM_3_E 0x08 /* Sun 3/E series */
/* Sun3x machines */
#define SM_3_460 0x01 /* Sun 3/460 (460,470,480) series */
#define SM_3_80 0x02 /* Sun 3/80 series */
/* Sun4 machines */
#define SM_4_260 0x01 /* Sun 4/200 series */
#define SM_4_110 0x02 /* Sun 4/100 series */
#define SM_4_330 0x03 /* Sun 4/300 series */
#define SM_4_470 0x04 /* Sun 4/400 series */
/* Sun4c machines Full Name - PROM NAME */
#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
/* Sun4m machines, these predate the OpenBoot. These values only mean
* something if the value in the ARCH field is SM_SUN4M, if it is
* SM_SUN4M_OBP then you have the following situation:
* 1) You either have a sun4d, a sun4e, or a recently made sun4m.
* 2) You have to consult OpenBoot to determine which machine this is.
*/
#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
/* Sun4d machines -- N/A */
/* Sun4e machines -- N/A */
/* Sun4u machines -- N/A */
#endif /* !(_SPARC_MACHINES_H) */

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include/asm-m68k/machw.h
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/*
** linux/machw.h -- This header defines some macros and pointers for
** the various Macintosh custom hardware registers.
**
** Copyright 1997 by Michael Schmitz
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _ASM_MACHW_H_
#define _ASM_MACHW_H_
/*
* head.S maps the videomem to VIDEOMEMBASE
*/
#define VIDEOMEMBASE 0xf0000000
#define VIDEOMEMSIZE (4096*1024)
#define VIDEOMEMMASK (-4096*1024)
#ifndef __ASSEMBLY__
#include <linux/types.h>
#if 0
/*
** SCC Z8530
*/
#define MAC_SCC_BAS (0x50F04000)
struct MAC_SCC
{
u_char cha_a_ctrl;
u_char char_dummy1;
u_char cha_a_data;
u_char char_dummy2;
u_char cha_b_ctrl;
u_char char_dummy3;
u_char cha_b_data;
};
# define mac_scc ((*(volatile struct SCC*)MAC_SCC_BAS))
#endif
#endif /* __ASSEMBLY__ */
#endif /* linux/machw.h */

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include/asm-m68k/macintosh.h
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#ifndef __ASM_MACINTOSH_H
#define __ASM_MACINTOSH_H
#include <linux/seq_file.h>
#include <linux/interrupt.h>
/*
* Apple Macintoshisms
*/
extern void mac_reset(void);
extern void mac_poweroff(void);
extern void mac_init_IRQ(void);
extern int mac_irq_pending(unsigned int);
/*
* Floppy driver magic hook - probably shouldnt be here
*/
extern void via1_set_head(int);
/*
* Macintosh Table
*/
struct mac_model
{
short ident;
char *name;
char adb_type;
char via_type;
char scsi_type;
char ide_type;
char scc_type;
char ether_type;
char nubus_type;
};
#define MAC_ADB_NONE 0
#define MAC_ADB_II 1
#define MAC_ADB_IISI 2
#define MAC_ADB_CUDA 3
#define MAC_ADB_PB1 4
#define MAC_ADB_PB2 5
#define MAC_ADB_IOP 6
#define MAC_VIA_II 1
#define MAC_VIA_IIci 2
#define MAC_VIA_QUADRA 3
#define MAC_SCSI_NONE 0
#define MAC_SCSI_OLD 1
#define MAC_SCSI_QUADRA 2
#define MAC_SCSI_QUADRA2 3
#define MAC_SCSI_QUADRA3 4
#define MAC_IDE_NONE 0
#define MAC_IDE_QUADRA 1
#define MAC_IDE_PB 2
#define MAC_IDE_BABOON 3
#define MAC_SCC_II 1
#define MAC_SCC_IOP 2
#define MAC_SCC_QUADRA 3
#define MAC_SCC_PSC 4
#define MAC_ETHER_NONE 0
#define MAC_ETHER_SONIC 1
#define MAC_ETHER_MACE 2
#define MAC_NO_NUBUS 0
#define MAC_NUBUS 1
/*
* Gestalt numbers
*/
#define MAC_MODEL_II 6
#define MAC_MODEL_IIX 7
#define MAC_MODEL_IICX 8
#define MAC_MODEL_SE30 9
#define MAC_MODEL_IICI 11
#define MAC_MODEL_IIFX 13 /* And well numbered it is too */
#define MAC_MODEL_IISI 18
#define MAC_MODEL_LC 19
#define MAC_MODEL_Q900 20
#define MAC_MODEL_PB170 21
#define MAC_MODEL_Q700 22
#define MAC_MODEL_CLII 23 /* aka: P200 */
#define MAC_MODEL_PB140 25
#define MAC_MODEL_Q950 26 /* aka: WGS95 */
#define MAC_MODEL_LCIII 27 /* aka: P450 */
#define MAC_MODEL_PB210 29
#define MAC_MODEL_C650 30
#define MAC_MODEL_PB230 32
#define MAC_MODEL_PB180 33
#define MAC_MODEL_PB160 34
#define MAC_MODEL_Q800 35 /* aka: WGS80 */
#define MAC_MODEL_Q650 36
#define MAC_MODEL_LCII 37 /* aka: P400/405/410/430 */
#define MAC_MODEL_PB250 38
#define MAC_MODEL_IIVI 44
#define MAC_MODEL_P600 45 /* aka: P600CD */
#define MAC_MODEL_IIVX 48
#define MAC_MODEL_CCL 49 /* aka: P250 */
#define MAC_MODEL_PB165C 50
#define MAC_MODEL_C610 52 /* aka: WGS60 */
#define MAC_MODEL_Q610 53
#define MAC_MODEL_PB145 54 /* aka: PB145B */
#define MAC_MODEL_P520 56 /* aka: LC520 */
#define MAC_MODEL_C660 60
#define MAC_MODEL_P460 62 /* aka: LCIII+, P466/P467 */
#define MAC_MODEL_PB180C 71
#define MAC_MODEL_PB520 72 /* aka: PB520C, PB540, PB540C, PB550C */
#define MAC_MODEL_PB270C 77
#define MAC_MODEL_Q840 78
#define MAC_MODEL_P550 80 /* aka: LC550, P560 */
#define MAC_MODEL_CCLII 83 /* aka: P275 */
#define MAC_MODEL_PB165 84
#define MAC_MODEL_PB190 85 /* aka: PB190CS */
#define MAC_MODEL_TV 88
#define MAC_MODEL_P475 89 /* aka: LC475, P476 */
#define MAC_MODEL_P475F 90 /* aka: P475 w/ FPU (no LC040) */
#define MAC_MODEL_P575 92 /* aka: LC575, P577/P578 */
#define MAC_MODEL_Q605 94
#define MAC_MODEL_Q605_ACC 95 /* Q605 accelerated to 33 MHz */
#define MAC_MODEL_Q630 98 /* aka: LC630, P630/631/635/636/637/638/640 */
#define MAC_MODEL_P588 99 /* aka: LC580, P580 */
#define MAC_MODEL_PB280 102
#define MAC_MODEL_PB280C 103
#define MAC_MODEL_PB150 115
extern struct mac_model *macintosh_config;
#endif

155
include/asm-m68k/macints.h
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@@ -1,155 +0,0 @@
/*
** macints.h -- Macintosh Linux interrupt handling structs and prototypes
**
** Copyright 1997 by Michael Schmitz
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _ASM_MACINTS_H_
#define _ASM_MACINTS_H_
#include <asm/irq.h>
/* Setting this prints debugging info for unclaimed interrupts */
#define DEBUG_SPURIOUS
/* Setting this prints debugging info on each autovector interrupt */
/* #define DEBUG_IRQS */
/* Setting this prints debugging info on each Nubus interrupt */
/* #define DEBUG_NUBUS_INT */
/* Setting this prints debugging info on irqs as they enabled and disabled. */
/* #define DEBUG_IRQUSE */
/*
* Base IRQ number for all Mac68K interrupt sources. Each source
* has eight indexes (base -> base+7).
*/
#define VIA1_SOURCE_BASE 8
#define VIA2_SOURCE_BASE 16
#define MAC_SCC_SOURCE_BASE 24
#define PSC3_SOURCE_BASE 24
#define PSC4_SOURCE_BASE 32
#define PSC5_SOURCE_BASE 40
#define PSC6_SOURCE_BASE 48
#define NUBUS_SOURCE_BASE 56
#define BABOON_SOURCE_BASE 64
/*
* Maximum IRQ number is BABOON_SOURCE_BASE + 7,
* giving us IRQs up through 71
*/
#define NUM_MAC_SOURCES 72
/*
* clean way to separate IRQ into its source and index
*/
#define IRQ_SRC(irq) (irq >> 3)
#define IRQ_IDX(irq) (irq & 7)
/* VIA1 interrupts */
#define IRQ_VIA1_0 (8) /* one second int. */
#define IRQ_VIA1_1 (9) /* VBlank int. */
#define IRQ_MAC_VBL IRQ_VIA1_1
#define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
#define IRQ_MAC_ADB IRQ_VIA1_2
#define IRQ_MAC_ADB_SR IRQ_VIA1_2
#define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */
#define IRQ_MAC_ADB_SD IRQ_VIA1_3
#define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */
#define IRQ_MAC_ADB_CL IRQ_VIA1_4
#define IRQ_VIA1_5 (13)
#define IRQ_MAC_TIMER_2 IRQ_VIA1_5
#define IRQ_VIA1_6 (14)
#define IRQ_MAC_TIMER_1 IRQ_VIA1_6
#define IRQ_VIA1_7 (15)
/* VIA2/RBV interrupts */
#define IRQ_VIA2_0 (16)
#define IRQ_MAC_SCSIDRQ IRQ_VIA2_0
#define IRQ_VIA2_1 (17)
#define IRQ_MAC_NUBUS IRQ_VIA2_1
#define IRQ_VIA2_2 (18)
#define IRQ_VIA2_3 (19)
#define IRQ_MAC_SCSI IRQ_VIA2_3
#define IRQ_VIA2_4 (20)
#define IRQ_VIA2_5 (21)
#define IRQ_VIA2_6 (22)
#define IRQ_VIA2_7 (23)
/* Level 3 (PSC, AV Macs only) interrupts */
#define IRQ_PSC3_0 (24)
#define IRQ_MAC_MACE IRQ_PSC3_0
#define IRQ_PSC3_1 (25)
#define IRQ_PSC3_2 (26)
#define IRQ_PSC3_3 (27)
/* Level 4 (SCC) interrupts */
#define IRQ_SCC (32)
#define IRQ_SCCA (33)
#define IRQ_SCCB (34)
#if 0 /* FIXME: are there multiple interrupt conditions on the SCC ?? */
/* SCC interrupts */
#define IRQ_SCCB_TX (32)
#define IRQ_SCCB_STAT (33)
#define IRQ_SCCB_RX (34)
#define IRQ_SCCB_SPCOND (35)
#define IRQ_SCCA_TX (36)
#define IRQ_SCCA_STAT (37)
#define IRQ_SCCA_RX (38)
#define IRQ_SCCA_SPCOND (39)
#endif
/* Level 4 (PSC, AV Macs only) interrupts */
#define IRQ_PSC4_0 (32)
#define IRQ_PSC4_1 (33)
#define IRQ_PSC4_2 (34)
#define IRQ_PSC4_3 (35)
#define IRQ_MAC_MACE_DMA IRQ_PSC4_3
/* Level 5 (PSC, AV Macs only) interrupts */
#define IRQ_PSC5_0 (40)
#define IRQ_PSC5_1 (41)
#define IRQ_PSC5_2 (42)
#define IRQ_PSC5_3 (43)
/* Level 6 (PSC, AV Macs only) interrupts */
#define IRQ_PSC6_0 (48)
#define IRQ_PSC6_1 (49)
#define IRQ_PSC6_2 (50)
#define IRQ_PSC6_3 (51)
/* Nubus interrupts (cascaded to VIA2) */
#define IRQ_NUBUS_9 (56)
#define IRQ_NUBUS_A (57)
#define IRQ_NUBUS_B (58)
#define IRQ_NUBUS_C (59)
#define IRQ_NUBUS_D (60)
#define IRQ_NUBUS_E (61)
#define IRQ_NUBUS_F (62)
/* Baboon interrupts (cascaded to nubus slot $C) */
#define IRQ_BABOON_0 (64)
#define IRQ_BABOON_1 (65)
#define IRQ_BABOON_2 (66)
#define IRQ_BABOON_3 (67)
#define SLOT2IRQ(x) (x + 47)
#define IRQ2SLOT(x) (x - 47)
#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
#endif /* asm/macints.h */

315
include/asm-m68k/math-emu.h
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@@ -1,315 +0,0 @@
#ifndef _ASM_M68K_SETUP_H
#define _ASM_M68K_SETUP_H
#include <asm/setup.h>
#include <linux/linkage.h>
/* Status Register bits */
/* accrued exception bits */
#define FPSR_AEXC_INEX 3
#define FPSR_AEXC_DZ 4
#define FPSR_AEXC_UNFL 5
#define FPSR_AEXC_OVFL 6
#define FPSR_AEXC_IOP 7
/* exception status bits */
#define FPSR_EXC_INEX1 8
#define FPSR_EXC_INEX2 9
#define FPSR_EXC_DZ 10
#define FPSR_EXC_UNFL 11
#define FPSR_EXC_OVFL 12
#define FPSR_EXC_OPERR 13
#define FPSR_EXC_SNAN 14
#define FPSR_EXC_BSUN 15
/* quotient byte, assumes big-endian, of course */
#define FPSR_QUOTIENT(fpsr) (*((signed char *) &(fpsr) + 1))
/* condition code bits */
#define FPSR_CC_NAN 24
#define FPSR_CC_INF 25
#define FPSR_CC_Z 26
#define FPSR_CC_NEG 27
/* Control register bits */
/* rounding mode */
#define FPCR_ROUND_RN 0 /* round to nearest/even */
#define FPCR_ROUND_RZ 1 /* round to zero */
#define FPCR_ROUND_RM 2 /* minus infinity */
#define FPCR_ROUND_RP 3 /* plus infinity */
/* rounding precision */
#define FPCR_PRECISION_X 0 /* long double */
#define FPCR_PRECISION_S 1 /* double */
#define FPCR_PRECISION_D 2 /* float */
/* Flags to select the debugging output */
#define PDECODE 0
#define PEXECUTE 1
#define PCONV 2
#define PNORM 3
#define PREGISTER 4
#define PINSTR 5
#define PUNIMPL 6
#define PMOVEM 7
#define PMDECODE (1<<PDECODE)
#define PMEXECUTE (1<<PEXECUTE)
#define PMCONV (1<<PCONV)
#define PMNORM (1<<PNORM)
#define PMREGISTER (1<<PREGISTER)
#define PMINSTR (1<<PINSTR)
#define PMUNIMPL (1<<PUNIMPL)
#define PMMOVEM (1<<PMOVEM)
#ifndef __ASSEMBLY__
#include <linux/kernel.h>
#include <linux/sched.h>
union fp_mant64 {
unsigned long long m64;
unsigned long m32[2];
};
union fp_mant128 {
unsigned long long m64[2];
unsigned long m32[4];
};
/* internal representation of extended fp numbers */
struct fp_ext {
unsigned char lowmant;
unsigned char sign;
unsigned short exp;
union fp_mant64 mant;
};
/* C representation of FPU registers */
/* NOTE: if you change this, you have to change the assembler offsets
below and the size in <asm/fpu.h>, too */
struct fp_data {
struct fp_ext fpreg[8];
unsigned int fpcr;
unsigned int fpsr;
unsigned int fpiar;
unsigned short prec;
unsigned short rnd;
struct fp_ext temp[2];
};
#ifdef FPU_EMU_DEBUG
extern unsigned int fp_debugprint;
#define dprint(bit, fmt, args...) ({ \
if (fp_debugprint & (1 << (bit))) \
printk(fmt, ## args); \
})
#else
#define dprint(bit, fmt, args...)
#endif
#define uprint(str) ({ \
static int __count = 3; \
\
if (__count > 0) { \
printk("You just hit an unimplemented " \
"fpu instruction (%s)\n", str); \
printk("Please report this to ....\n"); \
__count--; \
} \
})
#define FPDATA ((struct fp_data *)current->thread.fp)
#else /* __ASSEMBLY__ */
#define FPDATA %a2
/* offsets from the base register to the floating point data in the task struct */
#define FPD_FPREG (TASK_THREAD+THREAD_FPREG+0)
#define FPD_FPCR (TASK_THREAD+THREAD_FPREG+96)
#define FPD_FPSR (TASK_THREAD+THREAD_FPREG+100)
#define FPD_FPIAR (TASK_THREAD+THREAD_FPREG+104)
#define FPD_PREC (TASK_THREAD+THREAD_FPREG+108)
#define FPD_RND (TASK_THREAD+THREAD_FPREG+110)
#define FPD_TEMPFP1 (TASK_THREAD+THREAD_FPREG+112)
#define FPD_TEMPFP2 (TASK_THREAD+THREAD_FPREG+124)
#define FPD_SIZEOF (TASK_THREAD+THREAD_FPREG+136)
/* offsets on the stack to access saved registers,
* these are only used during instruction decoding
* where we always know how deep we're on the stack.
*/
#define FPS_DO (PT_D0)
#define FPS_D1 (PT_D1)
#define FPS_D2 (PT_D2)
#define FPS_A0 (PT_A0)
#define FPS_A1 (PT_A1)
#define FPS_A2 (PT_A2)
#define FPS_SR (PT_SR)
#define FPS_PC (PT_PC)
#define FPS_EA (PT_PC+6)
#define FPS_PC2 (PT_PC+10)
.macro fp_get_fp_reg
lea (FPD_FPREG,FPDATA,%d0.w*4),%a0
lea (%a0,%d0.w*8),%a0
.endm
/* Macros used to get/put the current program counter.
* 020/030 use a different stack frame then 040/060, for the
* 040/060 the return pc points already to the next location,
* so this only needs to be modified for jump instructions.
*/
.macro fp_get_pc dest
move.l (FPS_PC+4,%sp),\dest
.endm
.macro fp_put_pc src,jump=0
move.l \src,(FPS_PC+4,%sp)
.endm
.macro fp_get_instr_data f,s,dest,label
getuser \f,%sp@(FPS_PC+4)@(0),\dest,\label,%sp@(FPS_PC+4)
addq.l #\s,%sp@(FPS_PC+4)
.endm
.macro fp_get_instr_word dest,label,addr
fp_get_instr_data w,2,\dest,\label,\addr
.endm
.macro fp_get_instr_long dest,label,addr
fp_get_instr_data l,4,\dest,\label,\addr
.endm
/* These macros are used to read from/write to user space
* on error we jump to the fixup section, load the fault
* address into %a0 and jump to the exit.
* (derived from <asm/uaccess.h>)
*/
.macro getuser size,src,dest,label,addr
| printf ,"[\size<%08x]",1,\addr
.Lu1\@: moves\size \src,\dest
.section .fixup,"ax"
.even
.Lu2\@: move.l \addr,%a0
jra \label
.previous
.section __ex_table,"a"
.align 4
.long .Lu1\@,.Lu2\@
.previous
.endm
.macro putuser size,src,dest,label,addr
| printf ,"[\size>%08x]",1,\addr
.Lu1\@: moves\size \src,\dest
.Lu2\@:
.section .fixup,"ax"
.even
.Lu3\@: move.l \addr,%a0
jra \label
.previous
.section __ex_table,"a"
.align 4
.long .Lu1\@,.Lu3\@
.long .Lu2\@,.Lu3\@
.previous
.endm
/* work around binutils idiocy */
old_gas=-1
.irp gas_ident.x .x
old_gas=old_gas+1
.endr
.if !old_gas
.irp m b,w,l
.macro getuser.\m src,dest,label,addr
getuser .\m,\src,\dest,\label,\addr
.endm
.macro putuser.\m src,dest,label,addr
putuser .\m,\src,\dest,\label,\addr
.endm
.endr
.endif
.macro movestack nr,arg1,arg2,arg3,arg4,arg5
.if \nr
movestack (\nr-1),\arg2,\arg3,\arg4,\arg5
move.l \arg1,-(%sp)
.endif
.endm
.macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
#ifdef FPU_EMU_DEBUG
.data
.Lpdata\@:
.string "\string"
.previous
movem.l %d0/%d1/%a0/%a1,-(%sp)
.if \bit+1
#if 0
moveq #\bit,%d0
andw #7,%d0
btst %d0,fp_debugprint+((31-\bit)/8)
#else
btst #\bit,fp_debugprint+((31-\bit)/8)
#endif
jeq .Lpskip\@
.endif
movestack \nr,\arg1,\arg2,\arg3,\arg4,\arg5
pea .Lpdata\@
jsr printk
lea ((\nr+1)*4,%sp),%sp
.Lpskip\@:
movem.l (%sp)+,%d0/%d1/%a0/%a1
#endif
.endm
.macro printx bit,fp
#ifdef FPU_EMU_DEBUG
movem.l %d0/%a0,-(%sp)
lea \fp,%a0
#if 0
moveq #'+',%d0
tst.w (%a0)
jeq .Lx1\@
moveq #'-',%d0
.Lx1\@: printf \bit," %c",1,%d0
move.l (4,%a0),%d0
bclr #31,%d0
jne .Lx2\@
printf \bit,"0."
jra .Lx3\@
.Lx2\@: printf \bit,"1."
.Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8)
move.w (2,%a0),%d0
ext.l %d0
printf \bit,"E%04x",1,%d0
#else
printf \bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8)
#endif
movem.l (%sp)+,%d0/%a0
#endif
.endm
.macro debug instr,args
#ifdef FPU_EMU_DEBUG
\instr \args
#endif
.endm
#endif /* __ASSEMBLY__ */
#endif /* _ASM_M68K_SETUP_H */

26
include/asm-m68k/mc146818rtc.h
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@@ -1,26 +0,0 @@
/*
* Machine dependent access functions for RTC registers.
*/
#ifndef _ASM_MC146818RTC_H
#define _ASM_MC146818RTC_H
#ifdef CONFIG_ATARI
/* RTC in Atari machines */
#include <asm/atarihw.h>
#define RTC_PORT(x) (TT_RTC_BAS + 2*(x))
#define RTC_ALWAYS_BCD 0
#define CMOS_READ(addr) ({ \
atari_outb_p((addr),RTC_PORT(0)); \
atari_inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
atari_outb_p((addr),RTC_PORT(0)); \
atari_outb_p((val),RTC_PORT(1)); \
})
#endif /* CONFIG_ATARI */
#endif /* _ASM_MC146818RTC_H */

13
include/asm-m68k/md.h
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@@ -1,13 +0,0 @@
/*
* md.h: High speed xor_block operation for RAID4/5
*
*/
#ifndef __ASM_MD_H
#define __ASM_MD_H
/* #define HAVE_ARCH_XORBLOCK */
#define MD_XORBLOCK_ALIGNMENT sizeof(long)
#endif /* __ASM_MD_H */

17
include/asm-m68k/mman.h
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@@ -1,17 +0,0 @@
#ifndef __M68K_MMAN_H__
#define __M68K_MMAN_H__
#include <asm-generic/mman.h>
#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
#define MAP_LOCKED 0x2000 /* pages are locked */
#define MAP_NORESERVE 0x4000 /* don't check for reservations */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
#define MCL_CURRENT 1 /* lock all current mappings */
#define MCL_FUTURE 2 /* lock all future mappings */
#endif /* __M68K_MMAN_H__ */

7
include/asm-m68k/mmu.h
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@@ -1,7 +0,0 @@
#ifndef __MMU_H
#define __MMU_H
/* Default "unsigned long" context */
typedef unsigned long mm_context_t;
#endif

154
include/asm-m68k/mmu_context.h
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#ifndef __M68K_MMU_CONTEXT_H
#define __M68K_MMU_CONTEXT_H
#include <asm-generic/mm_hooks.h>
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
#ifndef CONFIG_SUN3
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
static inline int init_new_context(struct task_struct *tsk,
struct mm_struct *mm)
{
mm->context = virt_to_phys(mm->pgd);
return 0;
}
#define destroy_context(mm) do { } while(0)
static inline void switch_mm_0230(struct mm_struct *mm)
{
unsigned long crp[2] = {
0x80000000 | _PAGE_TABLE, mm->context
};
unsigned long tmp;
asm volatile (".chip 68030");
/* flush MC68030/MC68020 caches (they are virtually addressed) */
asm volatile (
"movec %%cacr,%0;"
"orw %1,%0; "
"movec %0,%%cacr"
: "=d" (tmp) : "di" (FLUSH_I_AND_D));
/* Switch the root pointer. For a 030-only kernel,
* avoid flushing the whole ATC, we only need to
* flush the user entries. The 68851 does this by
* itself. Avoid a runtime check here.
*/
asm volatile (
#ifdef CPU_M68030_ONLY
"pmovefd %0,%%crp; "
"pflush #0,#4"
#else
"pmove %0,%%crp"
#endif
: : "m" (crp[0]));
asm volatile (".chip 68k");
}
static inline void switch_mm_0460(struct mm_struct *mm)
{
asm volatile (".chip 68040");
/* flush address translation cache (user entries) */
asm volatile ("pflushan");
/* switch the root pointer */
asm volatile ("movec %0,%%urp" : : "r" (mm->context));
if (CPU_IS_060) {
unsigned long tmp;
/* clear user entries in the branch cache */
asm volatile (
"movec %%cacr,%0; "
"orl %1,%0; "
"movec %0,%%cacr"
: "=d" (tmp): "di" (0x00200000));
}
asm volatile (".chip 68k");
}
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
{
if (prev != next) {
if (CPU_IS_020_OR_030)
switch_mm_0230(next);
else
switch_mm_0460(next);
}
}
#define deactivate_mm(tsk,mm) do { } while (0)
static inline void activate_mm(struct mm_struct *prev_mm,
struct mm_struct *next_mm)
{
next_mm->context = virt_to_phys(next_mm->pgd);
if (CPU_IS_020_OR_030)
switch_mm_0230(next_mm);
else
switch_mm_0460(next_mm);
}
#else /* CONFIG_SUN3 */
#include <asm/sun3mmu.h>
#include <linux/sched.h>
extern unsigned long get_free_context(struct mm_struct *mm);
extern void clear_context(unsigned long context);
/* set the context for a new task to unmapped */
static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
mm->context = SUN3_INVALID_CONTEXT;
return 0;
}
/* find the context given to this process, and if it hasn't already
got one, go get one for it. */
static inline void get_mmu_context(struct mm_struct *mm)
{
if(mm->context == SUN3_INVALID_CONTEXT)
mm->context = get_free_context(mm);
}
/* flush context if allocated... */
static inline void destroy_context(struct mm_struct *mm)
{
if(mm->context != SUN3_INVALID_CONTEXT)
clear_context(mm->context);
}
static inline void activate_context(struct mm_struct *mm)
{
get_mmu_context(mm);
sun3_put_context(mm->context);
}
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
{
activate_context(tsk->mm);
}
#define deactivate_mm(tsk,mm) do { } while (0)
static inline void activate_mm(struct mm_struct *prev_mm,
struct mm_struct *next_mm)
{
activate_context(next_mm);
}
#endif
#endif

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