From e9f2c2aeb5bb354e6df3c9b3dfe051b0d7d7b22c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 30 Jan 2017 20:21:49 +0100 Subject: [PATCH 1/3] ARM: dts: add power controller to the Gemini DTS This adds the Gemini power controller to the SoC DTSI file. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 3876feefc9d9..73409a290f89 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -75,6 +75,12 @@ #interrupt-cells = <2>; }; + power-controller@4b000000 { + compatible = "cortina,gemini-power-controller"; + reg = <0x4b000000 0x100>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + }; + gpio0: gpio@4d000000 { compatible = "cortina,gemini-gpio"; reg = <0x4d000000 0x100>; From 552c804afe9b7d843f5ffae165ca5543f89b5293 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 13 Mar 2017 00:20:45 +0100 Subject: [PATCH 2/3] ARM: dts: augment Gemini GPIO nodes The binding should state "cortina,gemini-gpio", "faraday,ftgpio010" stating the full name of the IP part. Cc: Jonas Jensen Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 73409a290f89..e2bd5fa5fccb 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -82,7 +82,7 @@ }; gpio0: gpio@4d000000 { - compatible = "cortina,gemini-gpio"; + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; reg = <0x4d000000 0x100>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; @@ -92,7 +92,7 @@ }; gpio1: gpio@4e000000 { - compatible = "cortina,gemini-gpio"; + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; reg = <0x4e000000 0x100>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; @@ -102,7 +102,7 @@ }; gpio2: gpio@4f000000 { - compatible = "cortina,gemini-gpio"; + compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; reg = <0x4f000000 0x100>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; From e3aeca1d74366a43d28e8c826ac48064f7287022 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Jan 2017 21:15:15 +0100 Subject: [PATCH 3/3] ARM: dts: add PCI to the Gemini device trees The Cortina Gemini has an internal PCI root bus, add this to the device tree, and add interrupt mapping (swizzling) to the relevant systems device trees. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Cc: Feng-Hsin Chiang Cc: Greentime Hu Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-sq201.dts | 22 ++++++++++++++++ arch/arm/boot/dts/gemini.dtsi | 42 ++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index dae2a70d8fbc..46309e79cc7b 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -92,5 +92,27 @@ read-only; }; }; + + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + }; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index e2bd5fa5fccb..b8d011bdcc76 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -110,5 +110,47 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pci@50000000 { + compatible = "cortina,gemini-pci", "faraday,ftpci100"; + /* + * The first 256 bytes in the IO range is actually used + * to configure the host bridge. + */ + reg = <0x50000000 0x100>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + status = "disabled"; + + bus-range = <0x00 0xff>; + /* PCI ranges mappings */ + ranges = + /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + + /* DMA ranges */ + dma-ranges = + /* 128MiB at 0x00000000-0x07ffffff */ + <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, + /* 64MiB at 0x00000000-0x03ffffff */ + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, + /* 64MiB at 0x00000000-0x03ffffff */ + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; + + /* + * This PCI host bridge variant has a cascaded interrupt + * controller embedded in the host bridge. + */ + pci_intc: interrupt-controller { + interrupt-parent = <&intcon>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; }; };