Commit Graph

47151 Commits

Author SHA1 Message Date
Michal Simek
841d6e8c4e microblaze: entry.S use delay slot for return handlers
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:26:13 +01:00
Michal Simek
8633bebc63 microblaze: Save current task directly
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:25:54 +01:00
Michal Simek
b1d70c62ff microblaze: Simplify entry.S - save/restore r3/r4 - ret_from_trap
There is possible to save r3/r4 at the beggining of user part
before calling handlers and at the end restore it.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:25:30 +01:00
Michal Simek
79bf3a1376 microblaze: PCI early support for noMMU system
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:16:17 +01:00
Michal Simek
1be53e084a microblaze: Fix dma alloc and free coherent dma functions
We have to use consistent code to be able to do coherent dma
function. In consistent code is used cache inhibit page mapping.
Xilinx reported that there is bug in Microblaze for WB and
d-cache_always use option. Microblaze 7.30.a should be first version
where is this bug removed.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:15:48 +01:00
Michal Simek
3a0d7a4dd5 microblaze: Add consistent code
Remove ancient Kconfig option for consistent code.
MMU uses cache inhibit pages.

noMMU uses UNCACHE SHADOW feature where is used double ram size.
For example:
Physical ram is 256MB and cache are setup to cover the same size.
But if you setup in HW that size is 512MB and cache covers 256MB
than you can use adresses from 256-512MB without caches and
correspond with 0-256MB with cache. That's why I am using
dcache base/high addresses to find out uncache area.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:14:43 +01:00
Michal Simek
ae8ee15051 microblaze: pgtable.h: move consistent functions
Consistent functions will be used for noMMU and MMU kernels.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:14:20 +01:00
Michal Simek
b8a84059b5 microblaze: Remove ancient Kconfig option for consistent mapping
We don't use CONSISTENT option from Kconfig that's why I am removing them.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:13:34 +01:00
Michal Simek
cca5613f02 microblaze: Remove VMALLOC_VMADDR
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:13:10 +01:00
Michal Simek
22607a2821 microblaze: Add define for ASM_LOOP
It is default option but both options must be measured.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:12:50 +01:00
Jack Steiner
6f4edd69e4 x86, UV: Clean up UV headers for MMR definitions
Update UV mmr definitions header file. Eliminate definitions no
longer needed. Move 2 definitions from tlb_uv.c into the header
file where they belong.

Signed-off-by: Jack Steiner <steiner@sgi.com>
LKML-Reference: <20100310204458.GA28835@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-11 14:11:26 +01:00
Michal Simek
dcbae4be90 microblaze: Preliminary support for dma drivers
I found several problems for ll_temac driver and on system with WB.
This early fix should fix it. I will clean this patch before I will add
it to mainline

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:10:02 +01:00
Frans Pop
4c912c1a33 microblaze: remove trailing space in messages
Signed-off-by: Frans Pop <elendil@planet.nl>
Cc: microblaze-uclinux@itee.uq.edu.au
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:09:29 +01:00
Michal Simek
e786c6ad2b microblaze: Use generic show_mem()
Remove arch-specific show_mem() in favor of the generic version.
It is based on powerpc patch.
bda2fa5355

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:09:12 +01:00
Michal Simek
137d0795a7 microblaze: Change temp register for cmdline
For copy was used r7 register when CONFIG_CMDLINE_BOOL option
is enabled. But r7 stores pointer to fdt that's why machine_early_init
not detect compiled-in DTB.

I also moved kernel PID setup to have TLB init in one block

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:08:55 +01:00
Michal Simek
d79f3b06a9 microblaze: Preliminary support for dma drivers
I found several problems for ll_temac driver and on system with WB.
This early fix should fix it. I will clean this patch before I will add
it to mainline

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:08:33 +01:00
Michal Simek
407c1da07d microblaze: Move cache function to cache.c
It is better to have init cache handling on one place.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:07:57 +01:00
Michal Simek
7775379057 microblaze: Add support from PREEMPT
This patch add core PREEMPT support for Microblaze.
I tried to trace it via tracers and I was able to see any output.

I also added low level debug functions to see if that code is called.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:07:32 +01:00
Michal Simek
733cc21831 microblaze: Add support for Xilinx PCI host bridge
This patch is based on powerpc patch
64f1650247

We did some cleanups and removed powerpc parts.
There is one new debug early listing function too.

Exclude function is only in Debug options.

We tested in on custom board.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:05:18 +01:00
Michal Simek
a6475c1322 microblaze: Enable PCI, missing files
There are two parts of changes. The first is just enable
PCI in Makefiles and in Kconfig. The second is the rest of
missing files. I didn't want to add it with previous patch
because that patch is too big.

Current Microblaze toolchain has problem with weak symbols
that's why is necessary to apply this changes to be possible
to compile pci support.
Xilinx knows about this problem.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:04:27 +01:00
Michal Simek
d3afa58c20 microblaze: Add core PCI files
Add pci-common.h and pci32.c. Files are based on PPC version.
There are removed ppc specific parts and the code was completely
clean.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:03:22 +01:00
Michal Simek
2ed975b43c microblaze: Add pci-bridge.h
Add pci-bridge.h for Microblaze. It is based on powerpc header file.
My changes:
I removed PPC_ prefix from constants
Removed ppc64 specifis parts

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:01:43 +01:00
Michal Simek
830980a0a8 microblaze: Add pci.h
Add pci.h for microblaze. It is based on powerpc pci.h

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:00:43 +01:00
Michal Simek
2ddafeab6f microblaze: io.h include asm-generic/iomap.h
I need to use generic/iomap.h for PCI that's why is necessary
to include it and fix ioport_{map,unmap} functions.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 14:00:09 +01:00
Michal Simek
c6ba01a4c7 microblaze: Add irq_create_{of_,}mapping functions
Support function for PCI. We don't use any advance mapping mechanism
that's why implementation is simple.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 13:59:28 +01:00
Michal Simek
a84642a339 microblaze: Add {z,}alloc_maybe_bootmem functions
I will need {z,}alloc_maybe_bootmem functions for pci patches

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 13:59:02 +01:00
Michal Simek
2549edd353 microblaze: Implement __dma_sync_page
There is necessary to do some cache handling for dma operations.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 13:58:11 +01:00
Michal Simek
ccfe27d700 microblaze: Support DMA
Add DMA support for Microblaze. There are some part of this new feature:
1. Basic DMA support
2. Enable DMA debug option
3. Setup notifier

Ad 1. dma-mapping come from powerpc and x86 version and it is based on
generic dma-mapping-common.h

Ad 2. DMA support debug features which is used in generic file.
For more information please look at Documentation/DMA-API.txt

Ad 3. notifier is very important to setup dma_ops. Without this part
for example ll_temac driver failed because there are no setup dma operations.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11 13:56:29 +01:00
Dimitri Sivanich
938179b4f8 x86: Improve Intel microcode loader performance
We've noticed that on large SGI UV system configurations,
running microcode.ctl can take very long periods of time.  This
is due to the large number of vmalloc/vfree calls made by the
Intel generic_load_microcode() logic.

By reusing allocated space, the following patch reduces the time
to run microcode.ctl on a 1024 cpu system from approximately 80
seconds down to 1 or 2 seconds.

Signed-off-by: Dimitri Sivanich <sivanich@sgi.com>
Acked-by: Dmitry Adamushko <dmitry.adamushko@gmail.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Bill Davidsen <davidsen@tmr.com>
LKML-Reference: <20100305174203.GA19638@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-11 13:49:06 +01:00
Paul E. McKenney
f56e8a0765 x86/mce: Fix RCU lockdep splats
Create an rcu_dereference_check_mce() that checks for RCU-sched
read side and mce_read_mutex being held on update side.  Replace
uses of rcu_dereference() in arch/x86/kernel/cpu/mcheck/mce.c
with this new macro.

Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: laijs@cn.fujitsu.com
Cc: dipankar@in.ibm.com
Cc: mathieu.desnoyers@polymtl.ca
Cc: josh@joshtriplett.org
Cc: dvhltc@us.ibm.com
Cc: niv@us.ibm.com
Cc: peterz@infradead.org
Cc: rostedt@goodmis.org
Cc: Valdis.Kletnieks@vt.edu
Cc: dhowells@redhat.com
LKML-Reference: <1267830207-9474-3-git-send-email-paulmck@linux.vnet.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-11 13:38:02 +01:00
Grant Likely
acc6a0935e powerpc/52xx: update defconfigs
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-03-10 14:39:50 -07:00
Frederic Weisbecker
5331d7b846 perf: Introduce new perf_fetch_caller_regs() for hot regs snapshot
Events that trigger overflows by interrupting a context can
use get_irq_regs() or task_pt_regs() to retrieve the state
when the event triggered. But this is not the case for some
other class of events like trace events as tracepoints are
executed in the same context than the code that triggered
the event.

It means we need a different api to capture the regs there,
namely we need a hot snapshot to get the most important
informations for perf: the instruction pointer to get the
event origin, the frame pointer for the callchain, the code
segment for user_mode() tests (we always use __KERNEL_CS as
trace events always occur from the kernel) and the eflags
for further purposes.

v2: rename perf_save_regs to perf_fetch_caller_regs as per
Masami's suggestion.

Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Masami Hiramatsu <mhiramat@redhat.com>
Cc: Jason Baron <jbaron@redhat.com>
Cc: Archs <linux-arch@vger.kernel.org>
2010-03-10 14:39:35 +01:00
Frederic Weisbecker
61e67fb9d3 perf/x86-64: Use frame pointer to walk on irq and process stacks
We were using the frame pointer based stack walker on every
contexts in x86-32, but not in x86-64 where we only use the
seven-league boots on the exception stacks.

Use it also on irq and process stacks. This utterly accelerate
the captures.

Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
2010-03-10 14:26:40 +01:00
Ingo Molnar
caa0142d84 perf, x86: Fix the !CONFIG_CPU_SUP_INTEL build
Fix typo. But the modularization here is ugly and should be improved.

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:40:44 +01:00
Ingo Molnar
ba7e4d13fc perf, x86: Add INSTRUCTION_DECODER config flag
The PEBS+LBR decoding magic needs the insn_get_length() infrastructure
to be able to decode x86 instruction length.

So split it out of KPROBES dependency and make it enabled when either
KPROBES or PERF_EVENTS is enabled.

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Masami Hiramatsu <mhiramat@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:34:12 +01:00
Peter Zijlstra
63fb3f9b23 perf, x86: Fix LBR read-out
Don't decrement the TOS twice...

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:39 +01:00
Peter Zijlstra
d80c7502ff perf, x86: Fixup the PEBS handler for Core2 cpus
Pull the core handler in line with the nhm one, also make sure we always
drain the buffer.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:39 +01:00
Peter Zijlstra
7645a24cbd perf, x86: Remove checking_{wr,rd}msr() usage
We don't need checking_{wr,rd}msr() calls, since we should know what cpu
we're running on and not use blindly poke at msrs.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:39 +01:00
Peter Zijlstra
b83a46e7da perf, x86: Don't reset the LBR as frequently
If we reset the LBR on each first counter, simple counter rotation which
first deschedules all counters and then reschedules the new ones will
lead to LBR reset, even though we're still in the same task context.

Reduce this by not flushing on the first counter but only flushing on
different task contexts.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:38 +01:00
Peter Zijlstra
ad0e6cfe2a perf, x86: Fix silly bug in intel_pmu_pebs_{enable,disable}
We need to use the actual cpuc->pebs_enabled value, not a local copy for
the changes to take effect.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:38 +01:00
Peter Zijlstra
12ab854d74 perf, x86: Deal with multiple state bits for pebs-fmt1
Its unclear if the PEBS state record will have only a single bit set, in
case it does not and accumulates bits, deal with that by only processing
each event once.

Also, robustify some of the code.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:38 +01:00
Peter Zijlstra
d329527e47 perf, x86: Reorder intel_pmu_enable_all()
The documentation says we have to enable PEBS before we enable the PMU
proper.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:37 +01:00
Peter Zijlstra
2df202bf75 perf, x86: Fix LBR enable/disable vs cpuc->enabled
We should never call ->enable with the pmu enabled, and we _can_ have
->disable called with the pmu enabled.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:37 +01:00
Peter Zijlstra
4807e3d5dc perf, x86: Fix PEBS enable/disable vs cpuc->enabled
We should never call ->enable with the pmu enabled, and we _can_ have
->disable called with the pmu enabled.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:36 +01:00
Peter Zijlstra
8f4aebd2be perf, x86: Fix pebs drains
I overlooked the perf_disable()/perf_enable() calls in
intel_pmu_handle_irq(), (pointed out by Markus) so we should not
explicitly disable_all/enable_all pebs counters in the drain functions,
these are already disabled and enabling them early is confusing.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:36 +01:00
Peter Zijlstra
cc7f00820b perf, x86: Avoid double disable on throttle vs ioctl(PERF_IOC_DISABLE)
Calling ioctl(PERF_EVENT_IOC_DISABLE) on a thottled counter would result
in a double disable, cure this by using x86_pmu_{start,stop} for
throttle/unthrottle and teach x86_pmu_stop() to check ->active_mask.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:36 +01:00
Peter Zijlstra
a562b1871f perf, x86: Robustify PEBS fixup
It turns out the LBR is massively unreliable on certain CPUs, so code the
fixup a little more defensive to avoid crashing the kernel.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100305154129.042271287@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:35 +01:00
Peter Zijlstra
74846d35b2 perf, x86: Clear the LBRs on init
Some CPUs have errata where the LBR is not cleared on Power-On. So always
clear the LBRs before use.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100305154128.966563424@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:35 +01:00
Peter Zijlstra
3c44780b22 perf, x86: Disable PEBS on clovertown chips
This CPU has just too many handycaps to be really useful.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100305154128.890278662@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:35 +01:00
Peter Zijlstra
3adaebd695 perf, x86: Fix silly bug in data store buffer allocation
Fix up the ds allocation error path, where we could free @buffer before
we used it.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100305154128.813452402@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-10 13:23:34 +01:00