The LS1021A QorIQ development system (QDS) is a high-performance
computing evaluation, development and test platform supporting
the LS1021A processor. The LS1021A QDS is optimized to support
the high-bandwidth DDR3LP/DDR4 memory and a full complement of
high-speed SerDes ports.
For more detail information about the LS1021AQDS, please refer to
the QorIQ LS1021A Development System Reference Manual.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On registration I2C bus drivers attemp to get ids from device tree
aliases, add a missing alias for I2C4 found on iMX6 DualLite/Solo.
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
compatible for fec2 node to be compatible with the old version.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The Colibri standard defines four pins as PWM outputs, two of them (PWM
A and C) are routed to FTM instance 0 and the other two (PWM B and D)
are routed to FTM instance 1. Hence enable both FTM instances for the
Colibri module and mux the four pins accordingly.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add Global Timer support which is part of the private peripherals
of the Cortex-A5 processor. This Global Timer is compatible with the
Cortex-A9 implementation. It's a 64-bit timer and is clocked by the
peripheral clock, which is typically 133 or 166MHz on Vybrid.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock
for generating bit clock when SSI operates in master mode.
Add the extra 'baud' clock so that we can have SSI functional in master mode.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock
for generating bit clock when SSI operates in master mode.
Add the extra 'baud' clock so that we can have SSI functional in master mode.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The i.MX SoC update for 3.19:
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
This driver register pm_power_off with snvs power off function. If
your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use
other pin to do, please disable the driver in dts, otherwise, your
pm_power_off maybe overwrote by this driver.
Signed-off-by: Robin Gong <b38343@freescale.com>
Acked-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which
is originally symbol used for the PowerPC based platforms
and guards lots of code that does not build on ARM.
This breaks allmodconfig, so let's remove it for now, until
either all those drivers are fixed or they use a dependency
on IMX instead.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
With the clock assignment device tree changes, the clocks get
initialized properly but the search for those clocks fails with
errors:
[ 0.000000] i.MX clk 4: register failed with -17
[ 0.000000] i.MX clk 5: register failed with -17
This is because the module can't find those clocks anymore, and
tries to initialize fixed clocks with the same name.
Get the clock modules input clocks from the assigned clocks by
default by using of_clk_get_by_name(). If this function returns
not a valid clock, fall back to the old behaviour and search the
input clock from the device tree's /clocks/$name node.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The LS1021A SoC is a dual-core Cortex-A7 based processor,
this adds the initial support for it.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The ARM clock is a virtual clock feeding the ARM partition of
the SoC. It controls multiple other clocks to ensure the right
sequencing when cpufreq changes the CPU clock rate.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This implements a virtual clock used to abstract away
all the steps needed in order to change the ARM clock,
so we don't have to push all this clock handling into
the cpufreq driver.
While it will be used for i.MX53 at first it is generic
enough to be used on i.MX6 later on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add imx6sx iomux-gpr register field define in "imx6q-iomuxc-gpr.h" header
file, which is not fully define all iomux-gpr registers and fields, only
align with freescale internal tree related GPR macro define.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add the ARM Global Timer as clocksource/scheduler clock option and
use it as default scheduler clock. This leaves the PIT timer for
other users e.g. the secondary Cortex-M4 core. Also, the Global Timer
has double the precission (running at pheripheral clock compared to
IPG clock) and a 64-bit incrementing counter register. We still keep
the PIT timer as an secondary option in case the ARM Global Timer is
not available.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
For LPDDR2 platform, no need to enable weak2P5 in DSM mode,
it can be pulled down to save power(~0.65mW).
And per design team's recommendation, we should disconnect
VDDHIGH and SNVS in DSM mode on i.MX6SL.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3,
we used cpu type to decide how to do these settings in suspend
before which is NOT flexible, take i.MX6SL for example, although
it has LPDDR2 on EVK board, but users can also use DDR3 on other
boards, so it is better to read the DDR type from MMDC then decide
how to do related settings.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The i.MX fixes for 3.18, 2nd round:
- Fix a regression on Vybrid platform which is caused by commit
dc4805c2e7 (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3
driver), and results in a missing configuration on PLL clocks.
- Fix a regression with i.MX defconfig files where CONFIG_SPI option
gets lost accidentally.
ext4_ext_remove_space() can incorrectly free a partial_cluster if
EAGAIN is encountered while truncating or punching. Extent removal
should be retried in this case.
It also fails to free a partial cluster when the punched region begins
at the start of a file on that unaligned cluster and where the entire
file has not been punched. Remove the requirement that all blocks in
the file must have been freed in order to free the partial cluster.
Signed-off-by: Eric Whitney <enwlinux@gmail.com>
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Add some casts and rearrange a few statements for improved readability.
Some code can also be simplified and made more readable if we set
partial_cluster to 0 rather than to a negative value when we can tell
we've hit the left edge of the punched region.
Signed-off-by: Eric Whitney <enwlinux@gmail.com>
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
The fix in commit ad6599ab3a ("ext4: fix premature freeing of
partial clusters split across leaf blocks"), intended to avoid
dereferencing an invalid extent pointer when determining whether a
partial cluster should be freed, wasn't quite good enough. Assure that
at least one extent remains at the start of the leaf once the hole has
been punched. Otherwise, the pointer to the extent to the right of the
hole will be invalid and a partial cluster will be incorrectly freed.
Set partial_cluster to 0 when we can tell we've hit the left edge of
the punched region within the leaf. This prevents incorrect freeing
of a partial cluster when ext4_ext_rm_leaf is called one last time
during extent tree traversal after the punched region has been removed.
Adjust comments to reflect code changes and a correction. Remove a bit
of dead code.
Signed-off-by: Eric Whitney <enwlinux@gmail.com>
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
The partial_cluster variable is not always initialized correctly when
hole punching on bigalloc file systems. Although commit c063449394
("ext4: fix partial cluster handling for bigalloc file systems")
addressed the case where the right edge of the punched region and the
next extent to its right were within the same leaf, it didn't handle
the case where the next extent to its right is in the next leaf. This
causes xfstest generic/300 to fail.
Fix this by replacing the code in c0634493922 with a more general
solution that can continue the search for the first cluster to the
right of the punched region into the next leaf if present. If found,
partial_cluster is initialized to this cluster's negative value.
There's no need to determine if that cluster is actually shared; we
simply record it so its blocks won't be freed in the event it does
happen to be shared.
Also, minimize the burden on non-bigalloc file systems with some minor
code simplification.
Signed-off-by: Eric Whitney <enwlinux@gmail.com>
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13.
This appears to be a copy-paste error because such a register does not exist.
We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock
is the same as the rk3066 spdif clock, so we move it to the common clock branches.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Pull timer fix from Thomas Gleixner:
"A single bugfix for an init order problem in the sun4i subarch
clockevents code"
* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
clockevent: sun4i: Fix race condition in the probe code
Pull vfs fixes from Al Viro:
"Assorted fixes, most in overlayfs land"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
ovl: ovl_dir_fsync() cleanup
ovl: update MAINTAINERS
ovl: pass dentry into ovl_dir_read_merged()
ovl: use lockless_dereference() for upperdentry
ovl: allow filenames with comma
ovl: fix race in private xattr checks
ovl: fix remove/copy-up race
ovl: rename filesystem type to "overlay"
isofs: avoid unused function warning
vfs: fix reference leak in d_prune_aliases()
Hariprasad Shenai says:
====================
RDMA/cxgb4,cxgb4vf,csiostor: Cleanup macros
This series continues to cleanup all the macros/register defines related to
filter, port, VI, queue, RSS, LDST, firmware, etc that are defined in t4fw_api.h
and the affected files.
Will post few more series so that we can cover all the macros so that they all
follow the same style to be consistent.
The patches series is created against 'net-next' tree.
And includes patches on cxgb4, cxgb4vf, iw_cxgb4 and csiostor driver.
We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch cleanups all PCIE, RSS & FW related macros/register defines that are
defined in t4fw_api.h and the affected files.
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch cleanups all port and VI related macros/register defines that are
defined in t4fw_api.h and the affected files.
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch cleanups all queue related macros/register defines that are defined
in t4fw_api.h and the affected files.
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch cleanups PF/VF and LDST related macros/register defines that are
defined in t4fw_api.h and the affected files.
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch cleanups all filter related macros/register defines that are defined
in t4fw_api.h and the affected files.
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The original FDB code submission wasn't correct and the code
wasn't enabled. This removes some dead code (can use the common kernel
code for fdb_del and fdb_dump) and correctly enables the fdb_add
function pointer.
The fdb_add functionality is important to i40e because it is needed
for a workaround to allow bridges to work correctly on the i40e
hardware.
Reported-by: Jiri Pirko <jiri@resnulli.us>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: Greg Rose <gregory.v.rose@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jiri Pirko <jiri@resnulli.us>
Signed-off-by: David S. Miller <davem@davemloft.net>
Only determining if low latency mode is enabled. Failure
indicates adapter has no modes
Signed-off-by: Eliot Blennerhassett <eliot@blennerhassett.gen.nz>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Some cards have a so-called low-latency mode, in which they present
a single multichannel stream with no mixing or samplerate conversion.
In this mode the card can generate an interrupt per internal processing
block (typically 32 or 64 frames)
Signed-off-by: Eliot Blennerhassett <eliot@blennerhassett.gen.nz>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
