Commit Graph

506942 Commits

Author SHA1 Message Date
Wolfram Sang
ea18faf9f6 ARM: mach-prima2: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:05 +02:00
Wolfram Sang
ceb8ef2e20 ARM: mach-omap2: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:04 +02:00
Wolfram Sang
a46ca32ca0 ARM: mach-msm: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:03 +02:00
Wolfram Sang
f2633f8a53 ARM: mach-imx: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:03 +02:00
Wolfram Sang
7246c72de2 ARM: mach-davinci: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:02 +02:00
Wolfram Sang
d155fc759a ARM: common: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:02 +02:00
David Henningsson
8e64820419 ALSA: Update control names documentation
This document was not really up-to-date. Add recent additions to this
standard - based on what the HDA driver currently does, which is some
kind of a de facto standard.

Signed-off-by: David Henningsson <david.henningsson@canonical.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2014-10-20 15:37:36 +02:00
Michal Simek
2329efbbca ARM: zynq: DT: trivial: Fix mc node
sed -i 's/}\ ;/};/g'

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:20:17 +02:00
Michal Simek
6714297b1b ARM: zynq: DT: Add cadence watchdog node
Add the cadence watchdog node to the Zynq devicetree.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:20:16 +02:00
Michal Simek
6c7ba4157b ARM: zynq: DT: Add missing reference for memory-controller
Add missing reference for memory-controller.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:20:09 +02:00
Michal Simek
70472c4328 ARM: zynq: DT: Add missing reference for ADC
Add missing reference for ADC node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:19:17 +02:00
Michal Simek
8abef06b63 ARM: zynq: DT: Add missing address for L2 pl310
By in sync with others node and add also baseaddr
to the node name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:19:10 +02:00
Soren Brinkmann
e8b397754a ARM: zynq: DT: Remove 222 MHz OPP
Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:14:20 +02:00
Soren Brinkmann
b5241fb1ca ARM: zynq: DT: Fix GEM register area size
The size of the GEM's register area is only 0x1000 bytes.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-10-20 15:14:20 +02:00
Chen-Yu Tsai
f49a430c14 ARM: dts: sun9i: Add A80 Optimus Board support
The A80 Optimus Board is was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.

This board has a UART port, a JTAG connector, USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND flash,
4G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
jack, IR receiver, and additional GPIO headers.

This patch adds only basic support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-20 14:52:12 +02:00
Chen-Yu Tsai
4ab328f06e ARM: dts: sunxi: Add Allwinner A80 dtsi
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and
4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core
PowerVR G6230 GPU.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-20 14:52:12 +02:00
Iain Paton
35669b39f1 ARM: sun7i: add support for A20-OLinuXino-Lime2
This adds support for the Olimex A20-OLinuXino-Lime2
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2

Differences to previous Lime boards are 1GB RAM and gigabit ethernet

Signed-off-by: Iain Paton <ipaton0@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:52:11 +02:00
Hans de Goede
f9554fb476 ARM: dts: sun7i: Add Mele M3 board
The Mele M3 is yet another Allwinnner based Android top set box from Mele.

It uses a housing similar to the A2000, but without the USM sata storage slot
at the top.

It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices),
100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:52:11 +02:00
Hans de Goede
1566a6eab7 ARM: dts: sun7i: Add mmc2_pins_a pinctrl definition
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:52:11 +02:00
Hans de Goede
8a5b272fbf ARM: dts: sun7i: Add Banana Pi board
The Banana Pi is an A20 based development board using Raspberry Pi compatible
IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi
and stereo audio out + various expenansion headers:

http://www.lemaker.org/

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:52:11 +02:00
Hans de Goede
46e9fd407f ARM: dts: sun7i: Add uart3_pins_b pinctrl setting
The uart3_pins_a multiplexes the uart3 pins to port G, add a pinctrl entry
for mapping them to port H (as used on the Bananapi).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:52:11 +02:00
Hans de Goede
a99eb770b4 ARM: dts: sun7i: Add spi0_pins_a pinctrl setting
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:52:11 +02:00
Chen-Yu Tsai
2f4bc73445 ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i
The A80 SoC has reset controls matching bus clock gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:51:31 +02:00
Chen-Yu Tsai
19e704e35e Documentation: sunxi: Add A80 datasheet link
We now have initial support for the A80, as well a the datasheet.
Update the documents to reflect this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-20 14:51:30 +02:00
Chen-Yu Tsai
a1a0193bdd devicetree: bindings: Document supported Allwinner sunxi SoCs
This adds a list of supported Allwinner SoC bindings.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-20 14:51:29 +02:00
Chen-Yu Tsai
3d4c2f1ced ARM: sunxi: Introduce Allwinner A80 support
The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC.
While it's processor cores and interconnecting bus are new, it
re-uses many peripherals found in earlier Allwinner SoCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-20 14:51:28 +02:00
Chen-Yu Tsai
bb647665ba devicetree: bindings: Add vendor prefix for Merrii Technology Co., Ltd.
Merrii Technology Co., Ltd. is a Chinese ARM integration developer that
specializes in Allwinner SoC based designs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:51:27 +02:00
Chen-Yu Tsai
d4da889a53 ARM: sunxi: Add debug uart used by sun9i (Allwinner A80)
The uarts on sun9i are still compatible with the dw_8250, but are
located at different addresses.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:48:59 +02:00
Chen-Yu Tsai
0da6e72504 Documentation: sunxi: Update Allwinner SoC documentation (A31/A31s/A23)
Lately we have received documentation for A31 and A31s, in addition to
A23 documentation which was received earlier but not added.

Add these to the README, and update to reflect that A31 and A23 are
supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20 14:45:53 +02:00
Michael Opdenacker
5c43cbdf78 {mv64x60,ppc4xx}_edac,: Remove deprecated IRQF_DISABLED
It's a NOOP since 2.6.35.

Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Link: http://lkml.kernel.org/r/1412159043-7348-1-git-send-email-michael.opdenacker@free-electrons.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-20 14:23:09 +02:00
Borislav Petkov
4cfc3a40f7 EDAC: Sync memory types and names
Make keeping the sync between the mem_types enum and the actual string
names simpler by using designated initializers.

Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-20 14:22:50 +02:00
Aravind Gopalakrishnan
348fec7021 EDAC: Add DDR3 LRDIMM entries to edac_mem_types
F15hM60h adds support for DDR4 and DDR3 LRDIMMs. Add them here.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/1411070218-10258-1-git-send-email-Aravind.Gopalakrishnan@amd.com
[ Boris: improve comments. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-20 14:22:22 +02:00
Aravind Gopalakrishnan
15895a729e x86, amd_nb: Add device IDs to NB tables for F15h M60h
Add F3 and F4 PCI device IDs to amd_nb_misc_ids[] and
amd_nb_link_ids[] respectively.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1411070205-10217-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-20 14:18:45 +02:00
Aravind Gopalakrishnan
4cbbdb51cc pci_ids: Add PCI device IDs for F15h M60h
Add F3, F4 device IDs to be used in amd_nb.c and amd64_edac.c

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: http://lkml.kernel.org/r/1411070195-10177-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-20 14:08:40 +02:00
Kever Yang
89c107a88d clk: rockchip: add npll to source of sclk_gpu
The possible sources for the rk3288-gpu-clock also include the npll,
making it the same list of sources as for uart0.

This patch make a common source for uart0 pll src and sclk_gpu,
so that gpu can get its clock from npll.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 14:00:18 +02:00
Jianqun
8f06f5d392 clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout
Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.

Tested on rk3288 board, suggested by Heiko.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 13:53:56 +02:00
David Henningsson
3abb4f4d0e ALSA: hda - Use "Line Out" name instead of "PCM" when there are other outputs
In case there are speakers or headphones as well, anything that only
covers the line out should not be labelled "PCM". Let's name it
"Line Out" instead for clarity.

Signed-off-by: David Henningsson <david.henningsson@canonical.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2014-10-20 13:38:10 +02:00
David Henningsson
03ad6a8c93 ALSA: hda - Fix "PCM" name being used on one DAC when there are two DACs
In the scenario where there is one "Line Out", one "Speaker" and one
"Headphone", and there are only two DACs, two outputs will share a DAC.
Currently any mixer on such a DAC will get the "PCM" name, which is
misleading. Instead use "Headphone+LO" or "Speaker+LO" to better
specify what the volume actually controls.

[fixed missing slave string additions by tiwai]

Signed-off-by: David Henningsson <david.henningsson@canonical.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2014-10-20 13:37:50 +02:00
Mark Brown
5aa664d633 Merge branch 'fix/sgtl5000' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-sgtl5000
Conflicts:
	Documentation/devicetree/bindings/sound/sgtl5000.txt
2014-10-20 12:36:02 +01:00
Xiubo Li
409851c38c spi: fsl-dspi: remove useless code for dspi driver.
Since we are using regmap framework's internal locks, so the
lock_arg for dspi_regmap_config is redundant here.

This patch just remove it, and then the dspi_regmap_config could
be const type.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:28:35 +01:00
Xiubo Li
e39be3a31b regmap: cache: Sort include headers alphabetically
If the inlcude headers aren't sorted alphabetically, then the
logical choice is to append new ones, however that creates a
lot of potential for conflicts or duplicates because every change
will then add new includes in the same location.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:25:06 +01:00
Xiubo Li
fb70067e4a regmap: cache: Fix possible ZERO_SIZE_PTR pointer dereferencing error.
When all the registers are volatile(unlikely, but logically and mostly
will happen for some 'device' who has very few registers), then the
count will be euqal to 0, then kmalloc() will return ZERO_SIZE_PTR,
which equals to ((void *)16).

So this patch fix this with just doing the zero check before calling
kmalloc(). If the count == 0, so we can make sure that all the registers
are volatile, so no cache is need.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:25:02 +01:00
Xiubo Li
06f9c24e55 regmap: cache: use kmalloc_array instead of kmalloc
This patch fixes checkpatch.pl warning for regmap cache.
WARNING : prefer kmalloc_array over kmalloc with multiply

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:25:02 +01:00
Xiubo Li
fbba43c527 regmap: cache: speed regcache_hw_init() up.
This may speed regcache_hw_init() up for some cases that there
has volatile registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:25:01 +01:00
Xiubo Li
ba3f1c85a6 regmap: cache: fix errno in regcache_hw_init()
When kmalloc() fails, we should return -ENOMEM.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:25:01 +01:00
Xiubo Li
5bd83ed098 regmap: cache: cleanup regcache_hw_init()
Remove the redundant code for regmap cache.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:25:01 +01:00
Fengguang Wu
d0de6ff6b9 spi/atmel: fix simple_return.cocci warnings
drivers/spi/spi-atmel.c:1518:1-4: WARNING: end returns can be simpified and declaration on line 1514 can be dropped

 Simplify a trivial if-return sequence.  Possibly combine with a
 preceding function call.
Generated by: scripts/coccinelle/misc/simple_return.cocci

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:24:18 +01:00
Wenyou Yang
ce0c4caf25 spi/atmel: add support for runtime PM
Drivers should put the device into low power states proactively whenever the
device is not in use. Thus implement support for runtime PM and use the
autosuspend feature to make sure that we can still perform well in case we see
lots of SPI traffic within short period of time.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:24:18 +01:00
Vinod Koul
5398ad6897 spi/atmel: use dmaengine_terminate_all() API
The drivers should use dmaengine_terminate_all() API instead of
accessing the device_control which will be deprecated soon

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:24:18 +01:00
Chanwoo Choi
291d761c16 regulator: Document binding for regulator suspend state for PM state
This patch add regulator suspend state to constraint in dt file. The regulation_
constraints structure already has regulator suspend state field as following.
The regulator suspend state control the state of regulator according to
PM (Power Management) state.
- struct regulator_state state_disk
- struct regulator_state state_mem

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20 12:24:14 +01:00