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3 Commits

Author SHA1 Message Date
Michael Turquette 4a47295144 clk: meson: fractional pll support 
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
 2016-06-22 18:05:47 -07:00
Michael Turquette ec623f2a43 clk: meson8b: clean up pll clocks 
Remove the pll registration function and helpers. Replace unnecessary
configuration struct with static initialization of the desired clock
type.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
 2016-06-22 18:02:28 -07:00
Carlo Caione 7a29a86943 clk: meson: Add support for Meson clock controller 
This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2015-06-05 17:22:08 -07:00