Stephen Boyd
6f7478e3bb
Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next
...
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Converted most Mediatek clock drivers to struct platform_driver
- MediaTek clock drivers can be built as modules
- Mediatek MT8188 SoC clk drivers
- Clock driver for Sunplus SP7021 SoC
- Reimplement Loongson-1 clk driver with DT support
- Clk driver support for Loongson-2 SoCs
- Migrate socfpga clk driver to of_clk_add_hw_provider()
* clk-mediatek: (84 commits)
clk: mediatek: fhctl: Mark local variables static
clk: mediatek: Use right match table, include mod_devicetable
clk: mediatek: Add MT8188 adsp clock support
clk: mediatek: Add MT8188 imp i2c wrapper clock support
clk: mediatek: Add MT8188 wpesys clock support
clk: mediatek: Add MT8188 vppsys1 clock support
clk: mediatek: Add MT8188 vppsys0 clock support
clk: mediatek: Add MT8188 vencsys clock support
clk: mediatek: Add MT8188 vdosys1 clock support
clk: mediatek: Add MT8188 vdosys0 clock support
clk: mediatek: Add MT8188 vdecsys clock support
clk: mediatek: Add MT8188 mfgcfg clock support
clk: mediatek: Add MT8188 ipesys clock support
clk: mediatek: Add MT8188 imgsys clock support
clk: mediatek: Add MT8188 ccusys clock support
clk: mediatek: Add MT8188 camsys clock support
clk: mediatek: Add MT8188 infrastructure clock support
clk: mediatek: Add MT8188 peripheral clock support
clk: mediatek: Add MT8188 topckgen clock support
clk: mediatek: Add MT8188 apmixedsys clock support
...
* clk-sunplus:
clk: Add Sunplus SP7021 clock driver
* clk-loongson:
clk: clk-loongson2: add clock controller driver support
dt-bindings: clock: add loongson-2 boot clock index
MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
MIPS: loongson32: Update the clock initialization
clk: loongson1: Re-implement the clock driver
clk: loongson1: Remove the outdated driver
dt-bindings: clock: Add Loongson-1 clock
* clk-socfpga:
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
2023-04-25 11:50:08 -07:00
Tom Rix
cb9eee590a
clk: mediatek: fhctl: Mark local variables static
...
smatch reports
drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol
'fhctl_offset_v1' was not declared. Should it be static?
drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol
'fhctl_offset_v2' was not declared. Should it be static?
These variables are only used in one file so should be static.
Signed-off-by: Tom Rix <trix@redhat.com >
Link: https://lore.kernel.org/r/20230406010935.1944976-1-trix@redhat.com
Fixes: 8da312d657sboyd@kernel.org >
2023-04-10 16:57:12 -07:00
Stephen Boyd
e0e3aca997
clk: mediatek: Use right match table, include mod_devicetable
...
This is copy/pasta that breaks modular builds. Fix the match table to
use the right pointer, or the right device table type. And while we're
including the header, fix the order to be linux, dt-bindings, and
finally local.
Cc: Garmin.Chang <Garmin.Chang@mediatek.com >
Cc: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Fixes: f42b9e9a430d2f2cefbae4aaa60eaecfa4609f9bbb87c1109clkp@intel.com >
Link: https://lore.kernel.org/oe-kbuild-all/202304011039.UBDX1UOT-lkp@intel.com/
Link: https://lore.kernel.org/oe-kbuild-all/202304020649.QO2HlpD5-lkp@intel.com/
Link: https://lore.kernel.org/oe-kbuild-all/202304021055.WDhQPcoS-lkp@intel.com/
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
Link: https://lore.kernel.org/r/20230404204553.1256263-1-sboyd@kernel.org
2023-04-04 13:47:02 -07:00
Garmin.Chang
0d2f2cefba
clk: mediatek: Add MT8188 adsp clock support
...
Add MT8188 adsp clock controller which provides clock gate
control for Audio DSP.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-20-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
Garmin.Chang
1b5e5299dd
clk: mediatek: Add MT8188 imp i2c wrapper clock support
...
Add MT8188 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-19-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
Garmin.Chang
f42b9e9a43
clk: mediatek: Add MT8188 wpesys clock support
...
Add MT8188 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-18-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
Garmin.Chang
4898e77f47
clk: mediatek: Add MT8188 vppsys1 clock support
...
Add MT8188 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-17-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
Garmin.Chang
eb48cccda0
clk: mediatek: Add MT8188 vppsys0 clock support
...
Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-16-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
Garmin.Chang
bb87c1109c
clk: mediatek: Add MT8188 vencsys clock support
...
Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-15-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
cfa4609f9b
clk: mediatek: Add MT8188 vdosys1 clock support
...
Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-14-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
e4aaa60eae
clk: mediatek: Add MT8188 vdosys0 clock support
...
Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-13-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
7275316389
clk: mediatek: Add MT8188 vdecsys clock support
...
Add MT8188 vdec clock controllers which provide clock gate
control for video decoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-12-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
3e26f30fe4
clk: mediatek: Add MT8188 mfgcfg clock support
...
Add MT8188 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-11-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
49c9abe1c8
clk: mediatek: Add MT8188 ipesys clock support
...
Add MT8188 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-10-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
b281039a7b
clk: mediatek: Add MT8188 imgsys clock support
...
Add MT8188 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-9-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
87d06fa9d2
clk: mediatek: Add MT8188 ccusys clock support
...
Add MT8188 ccusys clock controller which provides clock gate
control in Camera Computing Unit.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-8-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
9b42835684
clk: mediatek: Add MT8188 camsys clock support
...
Add MT8188 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-7-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
fce4c7a228
clk: mediatek: Add MT8188 infrastructure clock support
...
Add MT8188 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-6-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
Garmin.Chang
643c06dc53
clk: mediatek: Add MT8188 peripheral clock support
...
Add MT8188 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-5-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:20 -07:00
Garmin.Chang
6c0d1dc233
clk: mediatek: Add MT8188 topckgen clock support
...
Add MT8188 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-4-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:20 -07:00
Garmin.Chang
28b2bc99fa
clk: mediatek: Add MT8188 apmixedsys clock support
...
Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:20 -07:00
Arnd Bergmann
92717003de
clk: mediatek: mt81xx: Ensure fhctl code is available
...
Just like in commit eddc63094845a5cbe05d4d586e10c4da4a82dc67arnd@arndb.de >
Link: https://lore.kernel.org/r/20230320091353.1918439-1-arnd@kernel.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reported-by: kernel test robot <lkp@intel.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-20 12:25:59 -07:00
Stephen Boyd
eddc630948
clk: mediatek: Ensure fhctl code is available for COMMON_CLK_MT6795
...
Without this select we get linker errors when linking
clk-mt6795-apmixedsys
arm-linux-gnueabi-ld: drivers/clk/mediatek/clk-mt6795-apmixedsys.o: in function `clk_mt6795_apmixed_remove':
clk-mt6795-apmixedsys.c:(.text+0x34): undefined reference to `mtk_clk_unregister_pllfhs'
arm-linux-gnueabi-ld: drivers/clk/mediatek/clk-mt6795-apmixedsys.o: in function `clk_mt6795_apmixed_probe':
clk-mt6795-apmixedsys.c:(.text+0x98): undefined reference to `fhctl_parse_dt'
arm-linux-gnueabi-ld: clk-mt6795-apmixedsys.c:(.text+0xb8): undefined reference to `mtk_clk_register_pllfhs'
arm-linux-gnueabi-ld: clk-mt6795-apmixedsys.c:(.text+0x1c4): undefined reference to `mtk_clk_unregister_pllfhs'
Fixes: f222a1baecangelogioacchino.delregno@collabora.com >
Cc: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
Link: https://lore.kernel.org/r/20230316231118.2579242-1-sboyd@kernel.org
2023-03-17 12:13:42 -07:00
Yang Yingliang
f1d97a37f9
clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt()
...
The device_node pointer returned by of_find_compatible_node() with
refcount incremented, when finish using it, the refcount need be
decreased.
Fixes: d7964de8a8yangyingliang@huawei.com >
Link: https://lore.kernel.org/r/20221229092946.4162345-1-yangyingliang@huawei.com
[sboyd@kernel.org: Also unmap on error]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-14 17:53:11 -07:00
AngeloGioacchino Del Regno
10966457a9
clk: mediatek: mt8135: Convert to simple probe and enable module build
...
Convert the MT8135 clock drivers to platform_driver using the common
simple probe mechanism; special note goes to the introduction of
dummy clocks with ID 0 (where 0 is the first entry of a clock array)
for each clock controller: this was necessary because of a mistake
in the bindings for all MT8135 clock controllers, where the first
clock has ID 1 (hence, array would start from element 1) instead of
zero.
Now that all of the MT8135 clock drivers (including apmixedsys) can
be compiled as modules, change the COMMON_CLK_MT8135 configuration
option to tristate to enable module build.
While at it, also remove the __initconst annotation from all of the
clock arrays as they are not only used during init anymore, but also
during runtime.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-55-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
AngeloGioacchino Del Regno
139e621856
clk: mediatek: mt8135: Join root_clk_alias and top_divs arrays
...
In preparation for converting this driver to the common simple probe
mechanism, join the root_clk_alias and top_divs mtk_fixed_factor
arrays.
This commit brings no functional change.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-54-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
AngeloGioacchino Del Regno
54b7026f01
clk: mediatek: mt8135-apmixedsys: Convert to platform_driver and module
...
Convert apmixedsys clocks to be a platform driver; while at it, also
add necessary error handling to the probe function, add a remove
callback and provide a MODULE_DESCRIPTION().
This driver is now compatible with an eventual module build.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-53-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
AngeloGioacchino Del Regno
f4f9a9c003
clk: mediatek: mt8135: Properly use CLK_IS_CRITICAL flag
...
Instead of calling clk_prepare_enable() for clocks that shall stay
enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that.
Fixes: a8aede7948angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-52-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
AngeloGioacchino Del Regno
aafcf16c9e
clk: mediatek: mt8135: Move apmixedsys to its own file
...
In preparation for migrating mt8135 clocks to the common simple
probe mechanism, move the apmixedsys clocks to a different file.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-51-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
AngeloGioacchino Del Regno
65c9ad77cb
clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate
...
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules
to allow auto-load at boot.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org > # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
AngeloGioacchino Del Regno
9bfa4fb1e0
clk: mediatek: Kconfig: Allow module build for core mt8192 clocks
...
Bootloaders must in a way setup the SoC to boot Linux: this means
that it will be possible to decompress a ramdisk and eventually
insert the core clock driver module from there.
Allow module build for all MT8192 clocks by switching to tristate.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-49-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
124294ff46
clk: mediatek: mt8192: Move apmixedsys clock driver to its own file
...
This is the last man standing in clk-mt8192.c that won't allow us to
use the module_platform_driver() macro, and for *no* good reason.
Move it to clk-mt8192-apmixedsys.c and while at it, also add a
.remove() callback for it.
Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was
just due to them being in the same file and probing different clocks,
and since now there's just one platform_driver struct per file, it
seemed natural to rename the `-simple` variant to just "clk-mt8192".
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
5baf38e06a
clk: mediatek: Split configuration options for MT8186 clock drivers
...
When building clock drivers for MT8186, some may want to build in only
some of them to, for example, get CPUFreq up faster, and some may want
to leave out some clock drivers entirely as a machine may not need the
Warp Engine or the camera ISP (hence, their clock drivers).
Split the various clock drivers in their own configuration options,
keeping MT8186 configuration options consistent with other MediaTek
SoCs.
While at it, also allow building the remaining clock drivers as modules
by switching COMMON_CLK_MT8186 to tristate.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-47-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
6f0d2e07f2
clk: mediatek: Allow building most MT6797 clock drivers as modules
...
Most of the MT6797 clock drivers can be built as modules: change them
to tristate to allow that.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-46-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
cfe2c864f0
clk: mediatek: Allow building most MT6765 clock drivers as modules
...
Most of the MT6765 clock drivers can be built as modules: change them
to tristate to allow that.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-45-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
95ffe65437
clk: mediatek: Allow all MT8183 clocks to be built as modules
...
All MT8183 clocks are platform drivers now! Allow module build for
all of them.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-44-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
a851b17059
clk: mediatek: Allow all MT8167 clocks to be built as modules
...
Almost all MT8167 clocks have been converted to use the common probe
mechanism, moreover, now all of them are platform drivers: allow
building as modules.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-43-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
c8f0ef9973
clk: mediatek: Allow MT7622 clocks to be built as modules
...
Now that all drivers are using the simple probe mechanism change the
MT7622 clock drivers to tristate in Kconfig to allow module build.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-42-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
e55351ac27
clk: mediatek: Allow building MT8192 non-critical clocks as modules
...
Allow building non boot critical clocks for MT8192 SoC as modules by
changing them to tristate.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-41-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
0f471d31e5
clk: mediatek: Split MT8195 clock drivers and allow module build
...
MT8195 clock drivers were encapsulated in one single (and big) Kconfig
option: there's no reason to do that, as it is totally unnecessary to
build in all or none of them.
Split them out: keep boot-critical clocks as bool and allow choosing
non critical clocks as tristate.
As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS
are not for build-time but rather for runtime, as clocks registered
by those have runtime dependencies on either or both VPP and IMGSYS.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-40-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
650fcdf918
clk: mediatek: mt2712: Change Kconfig options to allow module build
...
All of the mt2712 drivers have been converted to platform drivers!
Change the Kconfig options for all MT2712 clocks to tristate to allow
building all clock drivers as modules.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-39-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
a451da86cf
clk: mediatek: Add MODULE_LICENSE() where missing
...
In order to successfully build clock drivers as modules it is required
to declare a module license: add it where missing.
While at it, also change the MODULE_LICENSE text from "GPL v2" to
"GPL" (which means the same) on clk-mt7981-eth.c.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org > # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-38-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
164d240de9
clk: mediatek: Switch to module_platform_driver() where possible
...
Lots of clock drivers have got both .probe() and a .remove() callbacks:
switch from builtin_platform_driver() to module_platform_driver() so
that we actually register the .remove() callback.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org > # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-37-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
c5f34f63e5
clk: mediatek: mt8186-mcu: Migrate to common probe mechanism
...
Convert MT8186 MCUSYS clocks to the common mtk_clk_simple_probe().
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-36-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
1d04e30065
clk: mediatek: mt7986-eth: Migrate to common probe mechanism
...
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also remove __initconst annotations (as these structures
are used also at runtime).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Daniel Golle <daniel@makrotopia.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-35-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
148a39560b
clk: mediatek: mt7986-infracfg: Migrate to common probe mechanism
...
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also use module_platform_driver() instead, as this driver
just gained a .remove() callback during the conversion.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Daniel Golle <daniel@makrotopia.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-34-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
2562dc42ae
clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set critical clock
...
Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Daniel Golle <daniel@makrotopia.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
6b7daeaa7e
clk: mediatek: Propagate struct device with mtk_clk_register_dividers()
...
Propagate struct device for divider clocks registered through clk-mtk
helpers to be able to get runtime PM support for MTK clocks.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Chen-Yu Tsai <wenst@chromium.org > # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-32-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
876d4e21aa
clk: mediatek: mt8516: Allow building clock drivers as modules
...
Now that all MT8516 drivers have been converted to platform driver,
change the configuration options to tristate.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-31-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
b8390192f2
clk: mediatek: mt8516: Convert to platform driver and simple probe
...
Convert the MT8516 clock drivers to be platform drivers and use the
common probe mechanism.
Thanks to the conversion, more error handling was added to the clocks
registration.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-30-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:16 -07:00
