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542 Commits

Author SHA1 Message Date
Bartosz Golaszewski
607c101fe9 phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p 
Add QMP PHY config for sa8775p and add support for the new compatible.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20230411130446.401440-4-brgl@bgdev.pl
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-04-12 21:45:29 +05:30
Dmitry Baryshkov
813a239890 phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl 
The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX
table is empty, so we can drop it completely.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230331151250.4049-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-04-10 20:48:00 +05:30
Dmitry Baryshkov
1db6b0a424 phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes 
All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of
lanes to 2.

Fixes: f839f14e24 ("phy: qcom-qmp: Add sc8180x PCIe support")
Cc: stable@vger.kernel.org # 5.15
Sgned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230331151250.4049-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-04-10 20:48:00 +05:30
David Wronek
868c2a6cee phy: qcom-qmp-ufs: Add SM7150 support 
Add the tables and constants for init sequences for UFS QMP phy found in
SM7150 SoC.

Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230311231733.141806-3-danila@jiaxyga.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-31 19:26:25 +05:30
Rohit Agarwal
92bd868f52 phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY 
The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-31 19:24:24 +05:30
Dmitry Baryshkov
eb01687508 phy: qcom-qmp-combo: use qmp_combo_offsets_v3 instead of _v6 
The qmp_combo_offsets_v3 table is already used for v3 and v4 PHYs. Reuse
it for v6 too, dropping the separate qmp_combo_offsets_v6.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323144726.1614344-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-31 19:19:11 +05:30
Dmitry Baryshkov
4546334fc1 phy: qcom-qmp-combo: fix v3 offsets table 
SM8350 and SM8450 use qmp_combo_offsets_v3 table, which doesn't have
PCS_USB offset. Add the usb3_pcs_usb entry to program correct registers
while setting up sm8350 and sm8450 USB+DP combo PHYs.

Fixes: 05bd18348b ("phy: qcom-qmp-combo: Add config for SM6350")
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323144726.1614344-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-31 19:19:10 +05:30
Uwe Kleine-König
de6862d1bd phy: qualcomm: phy-qcom-ipq806x-sata: Convert to platform remove callback returning void 
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230307115900.2293120-15-u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-20 18:14:57 +05:30
Uwe Kleine-König
e5ce6d9d65 phy: qualcomm: phy-qcom-eusb2-repeater: Convert to platform remove callback returning void 
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230307115900.2293120-14-u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-20 18:14:57 +05:30
Uwe Kleine-König
64299241b4 phy: qualcomm: phy-qcom-apq8064-sata: Convert to platform remove callback returning void 
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230307115900.2293120-13-u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-20 18:14:57 +05:30
Manivannan Sadhasivam
364c748d5e phy: qcom-qmp-pcie: Add RC init sequence for SDX55 
Add PCIe RC init sequence making use of the common init sequence. The RC
mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and
powerdown.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-20 18:14:55 +05:30
Manivannan Sadhasivam
458aa82041 phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 
In preparation for adding RC support, let's split out the EP related init
sequence so that the common sequence could be reused by RC as well.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230308082424.140224-12-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-03-20 18:14:55 +05:30
Neil Armstrong
3584f6392f phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater 
For USB 2.0 compliance, eUSB2 needs a repeater. The PHY needs to
initialize and reset it. So add repeater support

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230208190200.2966723-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-16 18:40:27 +05:30
Abel Vesa
56d77c9a10 phy: qcom: Add QCOM SNPS eUSB2 repeater driver 
PM8550B contains a eUSB2 repeater used for making the eUSB2 from
SM8550 USB 2.0 compliant. This can be modelled SW-wise as a Phy.
So add a new phy driver for it.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208190200.2966723-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-16 18:40:27 +05:30
Vinod Koul
4315eab705 Merge tag 'phy-fixes-6.2' into next 
Merge fixes tag pulled into mainline by Linus into phy/next due to
dependency on amlogic patches
 2023-02-14 19:25:45 +05:30
Vinod Koul
037d05af38 phy: qcom: snps-eusb2: Add missing headers 
The driver was missing to include couple of headers explictly which
causes build to fail on other archs

drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_snps_eusb2_hsphy_write_mask':
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:147:15: error: implicit declaration of function 'readl_relaxed' [-Werror=implicit-function-declaration]
  147 |         reg = readl_relaxed(base + offset);
      |               ^~~~~~~~~~~~~
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:150:9: error: implicit declaration of function 'writel_relaxed' [-Werror=implicit-function-declaration]
  150 |         writel_relaxed(reg, base + offset);
      |         ^~~~~~~~~~~~~~
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_eusb2_default_parameters':
drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:161:42: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
  161 |                                          FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
      |                                          ^~~~~~~~~~

Fix this by adding bitfield.h and iopoll.h explictly

Fixes: 80090810f5 ("phy: qcom: Add QCOM SNPS eUSB2 driver")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-13 21:48:18 +05:30
Abel Vesa
49742e9eda phy: qcom-qmp-combo: Add support for SM8550 
Add SM8550 specific register layout and table configs.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:33:44 +05:30
Abel Vesa
dc55a1231e phy: qcom-qmp: Add v6 DP register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6.
Add the new DP specific offsets in the generic qmp header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208183421.2874423-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:32:43 +05:30
Abel Vesa
39bbf82d8c phy: qcom-qmp: pcs-usb: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB.
Add the new PCS USB specific offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:32:43 +05:30
Abel Vesa
80090810f5 phy: qcom: Add QCOM SNPS eUSB2 driver 
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0.
Add a new driver for it.

The driver is based on a downstream implementation.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:30:31 +05:30
Abel Vesa
269b70e852 phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs 
Add the SM8550 both g4 and g3 configurations. In addition, there is a
new "lane shared" table that needs to be configured for g4, along with
the No-CSR list of resets. The no-CSR allows resetting the PHY without
actually dropping the PHY configuration. The no-CSR needs to be
deasserted only after the PHY has been configured and the PLL has
stabilized.

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:01 +05:30
Abel Vesa
d38360e12f phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:00 +05:30
Abel Vesa
cea3e9435e phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a
dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-7-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:00 +05:30
Abel Vesa
baf172cc04 phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:00 +05:30
Abel Vesa
354fc6c513 phy: qcom-qmp: pcs-pcie: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:00 +05:30
Abel Vesa
5f70540273 phy: qcom-qmp: pcs: Add v6.20 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:00 +05:30
Abel Vesa
efecba3c9f phy: qcom-qmp: pcs: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-3-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:28:00 +05:30
Neil Armstrong
ef14aff107 phy: qcom: com-qmp-combo: add SM8350 & SM8450 support 
Copy the USB tables from the QMP USB3 PHY driver and add the
missing DP tables from downstream to enable USB3/DP on
the SM8350 and SM8450 platforms.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-10 22:25:10 +05:30
Stephen Boyd
d1abd69534 phy: qcom-qmp: Introduce Kconfig symbols for discrete drivers 
Introduce a config option for each QMP PHY driver now that the QMP PHY
mega-driver has been split up into different modules. This allows kernel
configurators to limit the binary size of the kernel by only compiling
in the QMP PHY driver that they need.

Leave the old config QCOM_QMP in place and make it into a menuconfig so
that 'make olddefconfig' continues to work. Furthermore, set the default
of the new Kconfig symbols to be QCOM_QMP so that the transition is
smooth.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20230202215330.2152726-1-swboyd@chromium.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-03 19:21:12 +05:30
Luca Weiss
05bd18348b phy: qcom-qmp-combo: Add config for SM6350 
Add the tables and config for the combo phy found on SM6350.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-2-4d700a90ba16@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-02 18:49:20 +05:30
Abel Vesa
1679bfef90 phy: qcom-qmp-ufs: Add SM8550 support 
Add SM8550 specific register layout and table configs.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-7-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-02 18:33:20 +05:30
Abel Vesa
5b8154ce50 phy: qcom-qmp: pcs-ufs: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-6-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-02 18:33:20 +05:30
Abel Vesa
c9736600a6 phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets
in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-02 18:33:20 +05:30
Abel Vesa
ddf070f6c9 phy: qcom-qmp: qserdes-txrx: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-4-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-02 18:33:20 +05:30
Abel Vesa
2df32d96f2 phy: qcom-qmp: qserdes-com: Add v6 register offsets 
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-3-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-02-02 18:33:19 +05:30
Dmitry Baryshkov
0dcaef53eb phy: qcom-qmp-usb: fix the regs layout table for sdx65 uniphy PHY 
The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout
while the PHY itself uses v5 regs. While there are only minor
differences between v4 and v5 regs and none of them concerns registers
mentions in regs_layout, switch the PHY to use
qmp_v5_usb3phy_regs_layout, to remove possible confusion.

Fixes: 14d98d3bf7 ("phy: qcom-qmp-usb: fix regs layout arrays")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230113212138.421583-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-18 22:54:49 +05:30
Dmitry Baryshkov
c08436c156 phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHY 
The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the
PHY itself uses v5 regs. While there are only minor differences between
v4 and v5 regs and none of them concerns registers mentions in
regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove
possible confusion.

Fixes: bbe207a1ab ("phy: qcom-qmp-pcie: rename regs layout arrays")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230113212138.421583-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-18 22:54:49 +05:30
Dmitry Baryshkov
aa14cff16b phy: qcom-qmp-combo: rework regs layout arrays 
Use symbolic names for the values inside reg layout arrays. New register
names are added following the PCS register layout that is used by the
particular PHY.

Note: ipq8074 tables appear to use a mixture of v2 and v3 registers.
This might need additional fixes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230113212102.421491-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-18 22:54:09 +05:30
Dmitry Baryshkov
34d562babf phy: qcom-qmp-combo: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS reg 
The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from
register layout.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230113212102.421491-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-18 22:54:09 +05:30
Dmitry Baryshkov
6900fdf496 phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsets 
All currently known QMP UFS PHYs have the same offsets for register
sub-regions. Instead of using qmp_ufs_offsets_v5 for older generations
of PHYs, rename the offsets struct instance to remove _v5 suffix.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230113195515.407866-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-18 22:53:00 +05:30
Manivannan Sadhasivam
2a397a23a5 phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC 
UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-13-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
8d0fb02ce5 phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC 
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-12-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
90c64cc05f phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC 
UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-11-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
0d46b98d3a phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers 
SM8350 default init sequence sets some PCS registers to HS G3, thereby
disabling HS G4 mode. This has the effect on MPHY capability negotiation
between the host and the device during link startup and causes the
PA_MAXHSGEAR to G3 irrespective of device max gear.

Due to that, the agreed gear speed determined by the UFS core will become
G3 only and the platform won't run at G4.

So, let's remove setting these registers for SM8350 as like other G4
compatible platforms. One downside of this is that, when the board design
uses non-G4 compatible device, then MPHY will continue to run in the
default mode (G4) even if UFSHCD runs in G3. But this is the case for
other platforms as well.

Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-10-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
692b655160 phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC 
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance. This
also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
f89dcb24e2 phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC 
UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-8-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
0cf7620e8e phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b 
Since now there is support for configuring the HS Rate B mode properly,
let's move the register setting to tbls_hs_b struct for all SoCs.

This allows the PHY to be configured in Rate A initially and then in
Rate B if requested by the UFS driver.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
baf8d17e2c phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode 
Add separate tables_hs_g4 instance to allow the PHY driver to configure the
PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and
PCS register setting in tables_hs_g4 and the UFS driver can request the
Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-6-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:57 +05:30
Manivannan Sadhasivam
69d2f980b6 phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode 
Add separate tables_hs_b instance to allow the PHY driver to configure the
PHY in HS Series B mode. The individual SoC configs need to supply the
serdes register setting in tables_hs_b and the UFS driver can request the
Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:56 +05:30
Manivannan Sadhasivam
c9a7b0ddb5 phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct 
As done for Qcom PCIe PHY driver, let's move the register settings to the
common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY
settings needed for functionalities like HS-G4 in the future by adding one
more instance of the qmp_phy_cfg_tbls.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-01-17 11:54:56 +05:30