Commit Graph

1232 Commits

Author SHA1 Message Date
Linus Torvalds
a99163e9e7 Merge tag 'devicetree-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:

 - Sync dtc to upstream version v1.6.0-51-g183df9e9c2b9 and build host
   fdtoverlay

 - Add kbuild support to build DT overlays (%.dtbo)

 - Drop NULLifying match table in of_match_device().

   In preparation for this, there are several driver cleanups to use
   (of_)?device_get_match_data().

 - Drop pointless wrappers from DT struct device API

 - Convert USB binding schemas to use graph schema and remove old plain
   text graph binding doc

 - Convert spi-nor and v3d GPU bindings to DT schema

 - Tree wide schema fixes for if/then schemas, array size constraints,
   and undocumented compatible strings in examples

 - Handle 'no-map' correctly for already reserved memblock regions

* tag 'devicetree-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (35 commits)
  driver core: platform: Drop of_device_node_put() wrapper
  of: Remove of_dev_{get,put}()
  dt-bindings: usb: Change descibe to describe in usbmisc-imx.txt
  dt-bindings: can: rcar_canfd: Group tuples in pin control properties
  dt-bindings: power: renesas,apmu: Group tuples in cpus properties
  dt-bindings: mtd: spi-nor: Convert to DT schema format
  dt-bindings: Use portable sort for version cmp
  dt-bindings: ethernet-controller: fix fixed-link specification
  dt-bindings: irqchip: Add node name to PRUSS INTC
  dt-bindings: interconnect: Fix the expected number of cells
  dt-bindings: Fix errors in 'if' schemas
  dt-bindings: iommu: renesas,ipmmu-vmsa: Make 'power-domains' conditionally required
  dt-bindings: Fix undocumented compatible strings in examples
  kbuild: Add support to build overlays (%.dtbo)
  scripts: dtc: Remove the unused fdtdump.c file
  scripts: dtc: Build fdtoverlay tool
  scripts/dtc: Update to upstream version v1.6.0-51-g183df9e9c2b9
  scripts: dtc: Fetch fdtoverlay.c from external DTC project
  dt-bindings: thermal: sun8i: Fix misplaced schema keyword in compatible strings
  dt-bindings: iio: dac: Fix AD5686 references
  ...
2021-02-22 10:05:12 -08:00
Stephen Boyd
4d5c4ae329 Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' into clk-next
- PLL support on MStar/SigmaStar ARMv7 SoCs
 - CPU clks for Qualcomm SDX55
 - GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
 - GCC clks for Qualcomm SM8350
 - Video clk fixups on Qualcomm SM8250
 - GPU clks for Qualcomm SDM660/SDM630
 - Improvements for multimedia clks on Qualcomm MSM8998
 - Fix many warnings with W=1 enabled builds under drivers/clk/

* clk-socfpga:
  clk: socfpga: agilex: add clock driver for eASIC N5X platform
  dt-bindings: documentation: add clock bindings information for eASIC N5X

* clk-mstar:
  clk: mstar: msc313-mpll: Fix format specifier
  clk: mstar: Allow MStar clk drivers to be compile tested
  clk: mstar: MStar/SigmaStar MPLL driver
  clk: fixed: add devm helper for clk_hw_register_fixed_factor()
  dt-bindings: clk: mstar msc313 mpll binding description
  dt-bindings: clk: mstar msc313 mpll binding header

* clk-qcom: (42 commits)
  clk: qcom: Add Global Clock controller (GCC) driver for SC7280
  dt-bindings: clock: Add SC7280 GCC clock binding
  clk: qcom: rpmh: Add support for RPMH clocks on SC7280
  dt-bindings: clock: Add RPMHCC bindings for SC7280
  clk: qcom: gcc-sm8350: add gdsc
  dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
  clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
  clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
  clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
  dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
  clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
  clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
  clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
  clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
  clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
  clk: qcom: gdsc: Implement NO_RET_PERIPH flag
  clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
  clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
  clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
  clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical
  ...

* clk-warnings: (27 commits)
  clk: zynq: clkc: Remove various instances of an unused variable 'clk'
  clk: versatile: clk-icst: Fix worthy struct documentation block
  clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
  clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter
  clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param
  clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one
  clk: st: clkgen-pll: Demote unpopulated kernel-doc header
  clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header
  clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'
  clk: socfpga: clk-pll: Remove unused variable 'rc'
  clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used
  clk: bcm: clk-iproc-pll: Demote kernel-doc abuse
  clk: zynqmp: divider: Add missing description for 'max_div'
  clk: spear: Move prototype to accessible header
  clk: qcom: clk-rpm: Remove a bunch of superfluous code
  clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags'
  clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}'
  clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx'
  clk: clk-fixed-mmio: Demote obvious kernel-doc abuse
  clk: qcom: gcc-ipq4019: Remove unused variable 'ret'
  ...
2021-02-16 14:09:24 -08:00
Stephen Boyd
11f83102d8 Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm' into clk-next
- Support crystal load capacitance for Versaclock VC5
 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot

* clk-vc5:
  clk: vc5: Add support for optional load capacitance
  dt-bindings: clk: versaclock5: Add optional load capacitance property

* clk-silabs:
  clk: si570: Skip NVM to RAM recall operation if an optional property is set
  dt-bindings: clock: si570: Add 'silabs,skip-recall' property

* clk-aspeed:
  clk: aspeed: Fix APLL calculate formula from ast2600-A2

* clk-qoriq:
  clk: qoriq: use macros to generate pll_mask

* clk-rohm:
  clk: BD718x7: Do not depend on parent driver data
2021-02-16 14:09:12 -08:00
Stephen Boyd
242d8cf626 Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into clk-next
* clk-mediatek:
  clk: mediatek: mux: Update parent at enable time
  clk: mediatek: mux: Drop unused clock ops
  clk: mediatek: Select all the MT8183 clocks by default

* clk-imx:
  dt-bindings: clock: imx: Switch to my personal address
  MAINTAINERS: Add section for NXP i.MX clock drivers
  clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header
  clk: imx8mn: add clkout1/2 support
  clk: imx8mm: add clkout1/2 support
  clk: imx8mq: add PLL monitor output
  clk: imx: clk-imx31: Remove unused static const table 'uart_clks'
  clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting
  clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems
  clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks

* clk-amlogic:
  clk: meson: axg: Remove MIPI enable clock gate
  clk: meson-axg: remove CLKID_MIPI_ENABLE
  dt-bindings: clock: meson8b: remove non-existing clock macros
  clk: meson: meson8b: remove compatibility code for old .dtbs
  clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
  clk: meson: clk-pll: make "ret" a signed integer
  clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL

* clk-at91:
  clk: at91: Fix the declaration of the clocks
2021-02-16 14:09:08 -08:00
Stephen Boyd
ee6b84a3fc Merge branch 'clk-unused' into clk-next
- Remove efm32 clk driver
 - Remove tango4 clk driver
 - Remove zte zx clk driver
 - Remove sirf prima2/atlast clk drivers
 - Remove u300 clk driver

* clk-unused:
  clk: remove u300 driver
  clk: remove sirf prima2/atlas drivers
  clk: remove zte zx driver
  clk: remove tango4 driver
  clk: Drop unused efm32gg driver
2021-02-16 14:08:51 -08:00
Stephen Boyd
0d7a660bfe Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and 'clk-xilinx' into clk-next
- Convert Xilinx VCU clk driver to a proper clk provider driver
 - Expose Xilinx ZynqMP clk driver to more platforms

* clk-doc:
  linux/clk.h: use correct kernel-doc notation for 2 functions

* clk-renesas: (21 commits)
  clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation
  clk: renesas: r8a779a0: Add RAVB clocks
  clk: renesas: r8a779a0: Add I2C clocks
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H
  clk: renesas: r8a779a0: Add SYS-DMAC clocks
  clk: renesas: r8a779a0: Add SDHI support
  clk: renesas: rcar-gen3: Factor out CPG library
  clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock
  clk: renesas: r8a779a0: Add MSIOF clocks
  clk: renesas: r8a779a0: Add PFC/GPIO clocks
  clk: renesas: r8a779a0: Fix parent of CBFUSA clock
  clk: renesas: r8a779a0: Remove non-existent S2 clock
  clk: renesas: r8a779a0: Add HSCIF support
  clk: renesas: r8a779a0: Add RWDT clocks
  clk: renesas: r8a779a0: Add VSPX clock support
  clk: renesas: r8a779a0: Add VSPD clock support
  clk: renesas: r8a779a0: Add FCPVD clock support
  clk: renesas: r8a77995: Add TMU clocks
  clk: renesas: r8a77990: Add TMU clocks
  clk: renesas: r8a77965: Add TMU clocks
  ...

* clk-allwinner:
  clk: sunxi-ng: Add support for the Allwinner H616 CCU
  clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
  dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
  clk: sunxi-ng: h6: Fix clock divider range on some clocks
  clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header
  clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse
  clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers
  clk: sunxi-ng: h6: Fix CEC clock
  clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset

* clk-rockchip:
  clk: rockchip: fix DPHY gate locations on rk3368
  clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
  clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
  clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
  clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
  clk: rockchip: Demote non-conformant kernel-doc header in half-divider
  clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls
  clk: rockchip: Remove unused/undocumented struct members from clk-cpu
  clk: rockchip: Demote non-conformant kernel-doc headers in main clock code

* clk-xilinx:
  clk: xilinx: move xlnx_vcu clock driver from soc
  soc: xilinx: vcu: fix alignment to open parenthesis
  soc: xilinx: vcu: fix repeated word the in comment
  soc: xilinx: vcu: use bitfields for register definition
  soc: xilinx: vcu: remove calculation of PLL configuration
  soc: xilinx: vcu: make the PLL configurable
  soc: xilinx: vcu: make pll post divider explicit
  soc: xilinx: vcu: implement clock provider for output clocks
  soc: xilinx: vcu: register PLL as fixed rate clock
  soc: xilinx: vcu: implement PLL disable
  soc: xilinx: vcu: add helpers for configuring PLL
  soc: xilinx: vcu: add helper to wait for PLL locked
  soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
  clk: divider: fix initialization with parent_hw
  ARM: dts: vcu: define indexes for output clocks
  clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand
  dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support
  clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
  clk: axi-clkgen: replace ARCH dependencies with driver deps
2021-02-16 14:06:43 -08:00
Taniya Das
87a3d523b3 dt-bindings: clock: Add SC7280 GCC clock binding
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612981579-17391-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14 12:56:55 -08:00
Taniya Das
75a81288db dt-bindings: clock: Add RPMHCC bindings for SC7280
Add bindings and update documentation for clock rpmh driver on SC7280.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612977230-11566-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14 12:56:55 -08:00
AngeloGioacchino Del Regno
e16831bf40 dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM630 and SDM660 SoCs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-10-angelogioacchino.delregno@somainline.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14 12:56:55 -08:00
AngeloGioacchino Del Regno
9502d488b1 dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
Document the multimedia clock controller found on SDM630/660.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-5-angelogioacchino.delregno@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14 12:56:54 -08:00
Daniel Palmer
4f83b5233f dt-bindings: clk: mstar msc313 mpll binding description
Add a binding description for the MStar/SigmaStar MPLL clock block.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-3-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14 12:37:45 -08:00
Dinh Nguyen
2bea59d388 dt-bindings: documentation: add clock bindings information for eASIC N5X
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the eASIC
N5X platform.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210212143059.478554-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-12 13:04:58 -08:00
Saeed Nowshadi
3dff4becef dt-bindings: clock: si570: Add 'silabs,skip-recall' property
Add an optional property so the driver can skip calling the NVM->RAM
recall operation during probe().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Link: https://lore.kernel.org/r/1612496104-3437-2-git-send-email-saeed.nowshadi@xilinx.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11 12:13:50 -08:00
Adam Ford
31e7aa7ed7 dt-bindings: clk: versaclock5: Add optional load capacitance property
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal.  Since XTAL1 and XTAL2 will set to the same value,
update the binding to support a single property called
xtal-load-femtofarads.

Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20210207185140.3653350-1-aford173@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11 12:09:31 -08:00
Fabio Estevam
fb7acfe7b0 dt-bindings: clock: imx: Switch to my personal address
My nxp account will expire soon, so switch to my personal e-mail
address.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210130144558.133534-1-festevam@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09 00:15:21 -08:00
Arnd Bergmann
ee7294ba49 clk: remove u300 driver
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-5-arnd@kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:03 -08:00
Arnd Bergmann
ed0f3e23d1 clk: remove sirf prima2/atlas drivers
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-4-arnd@kernel.org
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:03 -08:00
Arnd Bergmann
bcbe6005eb clk: remove zte zx driver
The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:03 -08:00
Arnd Bergmann
7765f32a8e clk: remove tango4 driver
The tango platform is getting removed, so the driver is no
longer needed.

Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-2-arnd@kernel.org
Acked-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:02 -08:00
Alexandru Ardelean
99da100bac dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support
The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
driver needs to use different PFD & VCO limits.

For ZynqMP, these needs to be selected by using the
'adi,zynqmp-axi-clkgen-2.00.a' string.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-4-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 18:13:13 -08:00
Vinod Koul
a2e8c80845 dt-bindings: clock: Add SM8350 GCC clock bindings
Add device tree bindings for global clock controller on SM8350 SoCs.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127070811.152690-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:03:57 -08:00
Bjorn Andersson
0fadcdfdcf dt-bindings: clock: Add SC8180x GCC binding
Add devicetree binding for the global clock controller found in the
Qualcomm SC8180x platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210126043155.1847823-1-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:54:11 -08:00
Bjorn Andersson
e6c3cc63fa dt-bindings: clock: qcom: rpmhcc: Add sc8180x rpmh clocks
Add Qualcomm SC8180x to the list of compatibles for the RPMHCC binding.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210120223741.1610344-1-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:52:20 -08:00
Manivannan Sadhasivam
ee778e069d dt-bindings: clock: Add Qualcomm A7 PLL binding
Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX55.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118041156.50016-4-manivannan.sadhasivam@linaro.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:46:23 -08:00
Rob Herring
91f93c3839 dt-bindings: Fix undocumented compatible strings in examples
Running 'dt-validate -m' will flag any compatible strings missing a schema.
Fix all the errors found in DT binding examples. Most of these are just
typos.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Avi Fishman <avifishman70@gmail.com>
Cc: Tomer Maimon <tmaimon77@gmail.com>
Cc: Tali Perry <tali.perry1@gmail.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Will Deacon <will@kernel.org>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Wim Van Sebroeck <wim@linux-watchdog.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: Vincent Cheng <vincent.cheng.xh@renesas.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-watchdog@vger.kernel.org
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Daniel Palmer <daniel@thingy.jp>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210202205544.24812-1-robh@kernel.org
2021-02-04 09:07:43 -06:00
Andre Przywara
f8d0e2bae6 dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210127172500.13356-2-andre.przywara@arm.com
2021-01-28 11:14:23 +01:00
Adam Ford
c706121386 dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H
The datasheet for the RZ/G2 Series show the bit for choosing between a crystal
oscillator and an external oscillator is present.  Add the bindings for
r8a774a1 (RZ/G2M), r8a774b1 (RZ/G2N), and r8a774e1 (RZ/G2H)

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201228202221.2327468-1-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12 12:35:13 +01:00
Rob Herring
0499220d6d dt-bindings: Add missing array size constraints
DT properties which can have multiple entries need to specify what the
entries are and define how many entries there can be. In the case of
only a single entry, just 'maxItems: 1' is sufficient.

Add the missing entry constraints. These were found with a modified
meta-schema. Unfortunately, there are a few cases where the size
constraints are not defined such as common bindings, so the meta-schema
can't be part of the normal checks.

Cc: Jens Axboe <axboe@kernel.dk>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210104230253.2805217-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
2021-01-11 17:42:25 -06:00
Linus Torvalds
14571d5f22 Merge tag 'devicetree-fixes-for-5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring:

 - Correct the JSON pointer syntax in binding schemas

 - Drop unnecessary *-supply schema constraints

 - Drop redundant maxItems/items on array schemas

 - Fix various yamllint warnings

 - Fix various missing 'additionalProperties' properties

* tag 'devicetree-fixes-for-5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dt-bindings: Drop redundant maxItems/items
  dt-bindings: net: qcom,ipa: Drop unnecessary type ref on 'memory-region'
  dt-bindings: Drop unnecessary *-supply schemas properties
  dt-bindings/display: abt,y030xx067a: Fix binding
  dt-bindings: clock: imx8qxp-lpcg: eliminate yamllint warnings
  dt-bindings: display: eliminate yamllint warnings
  dt-bindings: media: nokia,smia: eliminate yamllint warnings
  dt-bindings: devapc: add the required property 'additionalProperties'
  dt-bindings: soc: add the required property 'additionalProperties'
  dt-bindings: serial: add the required property 'additionalProperties'
  dt-bindings: xlnx,vcu-settings: fix dt_binding_check warnings
  media: dt-bindings: coda: Add missing 'additionalProperties'
  dt-bindings: Fix JSON pointers
2020-12-24 12:09:48 -08:00
Linus Torvalds
8653b778e4 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
 "The core framework got some nice improvements this time around. We
  gained the ability to get struct clk pointers from a struct clk_hw so
  that clk providers can consume the clks they provide, if they need to
  do something like that. This has been a long missing part of the clk
  provider API that will help us move away from exposing a struct clk
  pointer in the struct clk_hw. Tracepoints are added for the
  clk_set_rate() "range" functions, similar to the tracepoints we
  already have for clk_set_rate() and we added a column to debugfs to
  help developers understand the hardware enable state of clks in case
  firmware or bootloader state is different than what is expected.
  Overall the core changes are mostly improving the clk driver writing
  experience.

  At the driver level, we have the usual collection of driver updates
  and new drivers for new SoCs. This time around the Qualcomm folks
  introduced a good handful of clk drivers for various parts of three or
  four SoCs. The SiFive folks added a new clk driver for their FU740
  SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic
  SoCs had lots of work done after that for various new features. One
  last thing to note in the driver area is that the i.MX driver has
  gained a new binding to support SCU clks after being on the list for
  many months. It uses a two cell binding which is sort of rare in clk
  DT bindings. Beyond that we have the usual set of driver fixes and
  tweaks that come from more testing and finding out that some
  configuration was wrong or that a driver could support being built as
  a module.

  Summary:

  Core:
   - Add some trace points for clk_set_rate() "range" functions
   - Add hardware enable information to clk_summary debugfs
   - Replace clk-provider.h with of_clk.h when possible
   - Add devm variant of clk_notifier_register()
   - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

  New Drivers:
   - Bindings for Canaan K210 SoC clks
   - Support for SiFive FU740 PRCI
   - Camera clks on Qualcomm SC7180 SoCs
   - GCC and RPMh clks on Qualcomm SDX55 SoCs
   - RPMh clks on Qualcomm SM8350 SoCs
   - LPASS clks on Qualcomm SM8250 SoCs

  Updates:
   - DVFS support for AT91 clk driver
   - Update git repo branch for Renesas clock drivers
   - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
   - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
   - Stop using __raw_*() I/O accessors in Renesas clk drivers
   - One more conversion of DT bindings to json-schema
   - Make i.MX clk-gate2 driver more flexible
   - New two cell binding for i.MX SCU clks
   - Drop of_match_ptr() in i.MX8 clk drivers
   - Add arch dependencies for Rockchip clk drivers
   - Fix i2s on Rockchip rk3066
   - Add MIPI DSI clks on Amlogic axg and g12 SoCs
   - Support modular builds of Amlogic clk drivers
   - Fix an Amlogic Video PLL clock dependency
   - Samsung Kconfig dependencies updates for better compile test coverage
   - Refactoring of the Samsung PLL clocks driver
   - Small Tegra driver cleanups
   - Minor fixes to Ingenic and VC5 clk drivers
   - Cleanup patches to remove unused variables and plug memory leaks"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
  dt-binding: clock: Document canaan,k210-clk bindings
  dt-bindings: Add Canaan vendor prefix
  clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
  clk: ingenic: Fix divider calculation with div tables
  clk: sunxi-ng: Make sure divider tables have sentinel
  clk: s2mps11: Fix a resource leak in error handling paths in the probe function
  clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
  clk: si5351: Wait for bit clear after PLL reset
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error
  ...
2020-12-21 10:39:37 -08:00
Stephen Boyd
abe7e32f1d Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk-marvell' into clk-next
- Bindings for Canaan K210 SoC clks

* clk-ingenic:
  clk: ingenic: Fix divider calculation with div tables

* clk-vc5:
  clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"

* clk-cleanup:
  clk: sunxi-ng: Make sure divider tables have sentinel
  clk: s2mps11: Fix a resource leak in error handling paths in the probe function
  clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
  clk: bcm: dvp: drop a variable that is assigned to only

* clk-canaan:
  dt-binding: clock: Document canaan,k210-clk bindings
  dt-bindings: Add Canaan vendor prefix

* clk-marvell:
  clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
2020-12-20 17:18:05 -08:00
Stephen Boyd
b53a1603b4 Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next
- Add some trace points for clk_set_rate() "range" functions
 - DVFS support for AT91 clk driver

* clk-ti:
  clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
  clk: ti: Fix memleak in ti_fapll_synth_setup

* clk-analog:
  clk: axi-clkgen: move the OF table at the bottom of the file
  clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
  dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format

* clk-trace:
  clk: Trace clk_set_rate() "range" functions

* clk-at91:
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error

* clk-silabs:
  clk: si5351: Wait for bit clear after PLL reset
2020-12-20 17:17:51 -08:00
Stephen Boyd
699eda2814 Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-summary' into clk-next
- Support for SiFive FU740 PRCI
 - Add hardware enable information to clk_summary debugfs

* clk-tegra:
  clk: tegra: Fix duplicated SE clock entry
  clk: tegra: bpmp: Clamp clock rates on requests
  clk: tegra: Do not return 0 on failure

* clk-imx: (24 commits)
  clk: imx: scu: remove the calling of device_is_bound
  clk: imx: scu: Make pd_np with static keyword
  clk: imx8mq: drop of_match_ptr from of_device_id table
  clk: imx8mp: drop of_match_ptr from of_device_id table
  clk: imx8mn: drop of_match_ptr from of_device_id table
  clk: imx8mm: drop of_match_ptr from of_device_id table
  clk: imx: gate2: Remove unused variable ret
  clk: imx: gate2: Add locking in is_enabled op
  clk: imx: gate2: Add cgr_mask for more flexible number of control bits
  clk: imx: gate2: Check if clock is enabled against cgr_val
  clk: imx: gate2: Keep the register writing in on place
  clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
  clk: imx: scu: fix build break when compiled as modules
  clk: imx: remove redundant assignment to pointer np
  clk: imx: remove unneeded semicolon
  clk: imx: lpcg: add suspend/resume support
  clk: imx: clk-imx8qxp-lpcg: add runtime pm support
  clk: imx: lpcg: allow lpcg clk to take device pointer
  clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
  clk: imx: scu: add suspend/resume support
  ...

* clk-sifive:
  clk: sifive: Add clock enable and disable ops
  clk: sifive: Fix the wrong bit field shift
  clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
  clk: sifive: Use common name for prci configuration
  clk: sifive: Extract prci core to common base
  dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI

* clk-mediatek:
  clk: mediatek: Make mtk_clk_register_mux() a static function

* clk-summary:
  clk: Add hardware-enable column to clk summary
2020-12-20 17:17:37 -08:00
Stephen Boyd
d240d4c205 Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and 'clk-unused' into clk-next
- Replace clk-provider.h with of_clk.h when possible

* clk-amlogic:
  clk: meson: g12a: add MIPI DSI Host Pixel Clock
  dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings
  clk: meson: enable building as modules
  clk: meson: Kconfig: fix dependency for G12A
  clk: meson: axg: add MIPI DSI Host clock
  clk: meson: axg: add Video Clocks
  dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding
  dt-bindings: clk: axg-clkc: add Video Clocks

* clk-rockchip:
  clk: rockchip: fix i2s gate bits on rk3066 and rk3188
  clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
  clk: rockchip: Remove redundant null check before clk_prepare_enable
  clk: rockchip: Add appropriate arch dependencies

* clk-of:
  xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h>

* clk-freescale:
  clk: fsl-flexspi: new driver
  dt-bindings: clock: document the fsl-flexspi-clk device
  clk: divider: add devm_clk_hw_register_divider_table()
  clk: qoriq: provide constants for the type
  clk: fsl-sai: use devm_clk_hw_register_composite_pdata()
  clk: composite: add devm_clk_hw_register_composite_pdata()
  clk: fsl-sai: fix memory leak
  clk: qoriq: Add platform dependencies

* clk-unused:
  clk: scpi: mark scpi_clk_match as maybe unused
  clk: pwm: drop of_match_ptr from of_device_id table
2020-12-20 17:17:25 -08:00
Stephen Boyd
23cae54f52 Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next
- Camera clks on Qualcomm SC7180 SoCs
 - GCC and RPMh clks on Qualcomm SDX55 SoCs
 - RPMh clks on Qualcomm SM8350 SoCs
 - LPASS clks on Qualcomm SM8250 SoCs
 - Add devm variant of clk_notifier_register()
 - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

* clk-doc:
  clk: fix a kernel-doc markup

* clk-qcom: (27 commits)
  clk: qcom: rpmh: add support for SM8350 rpmh clocks
  dt-bindings: clock: Add RPMHCC bindings for SM8350
  clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
  clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
  clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
  clk: qcom: Add GDSC support for SDX55 GCC
  dt-bindings: clock: Add GDSC in SDX55 GCC
  clk: qcom: Add support for SDX55 RPMh clocks
  dt-bindings: clock: Introduce RPMHCC bindings for SDX55
  clk: qcom: Add SDX55 GCC support
  dt-bindings: clock: Add SDX55 GCC clock bindings
  clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
  clk: qcom: rpmh: Add CE clock on sdm845.
  dt-bindings: clock: Add entry for crypto engine RPMH clock resource
  clk: qcom: dispcc-sm8250: handle MMCX power domain
  clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
  clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
  clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
  clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
  dt-bindings: clock: Add support for LPASS Always ON Controller
  ...

* clk-simplify:
  clk: remove unneeded dead-store initialization

* clk-hw:
  clk: meson: g12: use devm variant to register notifiers
  clk: add devm variant of clk_notifier_register
  clk: meson: g12: drop use of __clk_lookup()
  clk: add api to get clk consumer from clk_hw
  clk: avoid devm_clk_release name clash

* clk-renesas:
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
  clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
  clk: renesas: r8a774c0: Add RPC clocks
  clk: renesas: r8a779a0: Fix R and OSC clocks
  clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
  clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
  clk: renesas: r8a774b1: Add RPC clocks
  clk: renesas: r8a774a1: Add RPC clocks
  clk: renesas: r8a779a0: Add VIN clocks
  clk: renesas: r8a779a0: Add CSI4[0-3] clocks
  MAINTAINERS: Update git repo for Renesas clock drivers
  clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
  clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI

* clk-samsung:
  clk: samsung: Prevent potential endless loop in the PLL ops
  clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
2020-12-20 17:17:01 -08:00
Damien Le Moal
0c797d2c7e dt-binding: clock: Document canaan,k210-clk bindings
Document the device tree bindings of the Canaan Kendryte K210 SoC clock
driver in Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml.
The header file include/dt-bindings/clock/k210-clk.h is modified to
include the complete list of IDs for all clocks of the SoC.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201220085725.19545-3-damien.lemoal@wdc.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-20 10:44:37 -08:00
Zhen Lei
246e18ba72 dt-bindings: clock: imx8qxp-lpcg: eliminate yamllint warnings
Eliminate the following yamllint warnings:
./Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
:32:13:[warning] wrong indentation: expected 14 but found 12 (indentation)
:35:9: [warning] wrong indentation: expected 10 but found 8 (indentation)

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201207045527.1607-2-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
2020-12-18 15:15:20 -06:00
Alexandru Ardelean
bd91abb218 dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format
This change converts the old binding for the AXI clkgen driver to a yaml
format.

As maintainers, added:
 - Lars-Peter Clausen <lars@metafoo.de> - as original author of driver &
   binding
 - Michael Hennerich <michael.hennerich@analog.com> - as supporter of
   Analog Devices drivers

Acked-by: Michael Hennerich <michael.hennerich@analog.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201013143421.84188-1-alexandru.ardelean@analog.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:52:28 -08:00
Linus Torvalds
9805529ec5 Merge tag 'arm-soc-dt-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM device tree updates from Arnd Bergmann:
 "Across all platforms, there is a continued move towards DT schema for
  validating the dts files. As a result there are bug fixes for mistakes
  that are found using these schema, in addition to warnings from the
  dtc compiler.

  As usual, many changes are for adding support for additional on-chip
  and on-board components in the machines we already support.

  The newly supported SoCs for this release are:

   - MStar Infinity2M, a low-end IP camera chip based on a dual-core
     Cortex-A7, otherwise similar to the Infinity chip we already
     support. This is also known as the SigmaStar SSD202D, and we add
     support for the Honestar ssd201htv2 development kit.

   - Nuvoton NPCM730, a Cortex-A9 based Baseboard Management Controller
     (BMC), in the same family as the NPCM750. This gets used in the
     Ampere Altra based "Fii Kudo" server and the Quanta GSJ, both of
     which are added as well.

   - Broadcom BCM4908, a 64-bit home router chip based on Broadcom's own
     Brahma-B53 CPU. Support is also added for the Asus ROG Rapture
     GT-AC5300 high-end WiFi router based on this chip.

   - Mediatek MT8192 is a new SoC based on eight Cortex-A76/A55 cores,
     meant for faster Chromebooks and tablets. It gets added along with
     its reference design.

   - Mediatek MT6779 (Helio P90) is a high-end phone chip from last
     year's generation, also added along with its reference board. This
     one is still based on Cortex-A75/A55.

   - Mediatek MT8167 is a version of the already supported MT8516 chip,
     both based on Cortex-A35. It gets added along with the "Pumpkin"
     single board computer, but is likely to also make its way into
     low-end tablets in the future.

  For the already supported chips, there are a number of new boards.
  Interestingly there are more 32-bit machines added this time than
  64-bit. Here is a brief list of the new boards:

   - Three new Mikrotik router variants based on Marvell Prestera
     98DX3236, a close relative of the more common Armada XP

   - A reference board for the Marvell Armada 382

   - Three new servers using ASpeed baseboard management controllers,
     the actual machines being from Bytedance, Facebook and IBM, and one
     machine using the Nuvoton NPCM750 BMC.

   - The Galaxy Note 10.1 (P4) tablet, using an Exynos 4412.

   - The usual set of 32-bit i.MX industrial/embedded hardware:
       * Protonic WD3 (tractor e-cockpit)
       * Kamstrup OMNIA Flex Concentrator (smart grid platform)
       * Van der Laan LANMCU (food storage)
       * Altesco I6P (vehicle inspection stations)
       * PHYTEC phyBOARD-Segin/phyCORE-i.MX6UL baseboard

   - DH electronics STM32MP157C DHCOM, a PicoITX carrier board for the
     aleady supported DHCOM module

   - Three new Allwinner SoC based single-board computers:
       * NanoPi R1 (H3 based)
       * FriendlyArm ZeroPi (H3 based)
       * Elimo Initium SBC (S3 based)

   - Ouya Game Console based on Nvidia Tegra 3

   - Version 5 of the already supported Zynq Z-Turn MYIR Board

   - LX2162AQDS, a reference platform for NXP Layerscape LX2162A, which
     is a repackaged 16-core LX2160A

   - A series of Kontron i.MX8M Mini baseboard/SoM versions

   - Espressobin Ultra, a new variant of the popular Armada 3700 based
     board,

   - IEI Puzzle-M801, a rackmount network appliance based on Marvell
     Armada 8040

   - Microsoft Lumia 950 XL, a phone

   - HDK855 and HDK865 Hardware development kits for Qualcomm sm8250 and
     sm8150, respectively

   - Three new board variants of the "Trogdor" Chromebook (sc7180)

   - New board variants of the Renesas based "Kingfisher" and "HiHope"
     reference boards

   - Kobol Helios64, an open source NAS appliance based on Rockchips
     RK3399

   - Engicam PX30.Core, a SoM based on Rockchip PX30, along with a few
     carrier boards"

* tag 'arm-soc-dt-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (679 commits)
  arm64: dts: sparx5: Add SGPIO devices
  arm64: dts: sparx5: Add reset support
  dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver
  ARM: mstar: SMP support
  ARM: mstar: Wire up smpctrl for SSD201/SSD202D
  ARM: mstar: Add smp ctrl registers to infinity2m dtsi
  ARM: mstar: Add dts for Honestar ssd201htv2
  ARM: mstar: Add chip level dtsi for SSD202D
  ARM: mstar: Add common dtsi for SSD201/SSD202D
  ARM: mstar: Add infinity2m support
  dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards
  dt-bindings: vendor-prefixes: Add honestar vendor prefix
  dt-bindings: mstar: Add binding details for mstar,smpctrl
  ARM: mstar: Fill in GPIO controller properties for infinity
  ARM: mstar: Add gpio controller to MStar base dtsi
  ARM: zynq: Fix incorrect reference to XM013 instead of XM011
  ARM: zynq: Convert at25 binding to new description on zc770-xm013
  ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
  ARM: zynq: Fix leds subnode name for zc702/zybo-z7
  ARM: zynq: Rename bus to be align with simple-bus yaml
  ...
2020-12-16 16:27:35 -08:00
Zong Li
a00a3f29b2 dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI
Add YAML DT binding documentation for the SiFive FU740 PRCI. The
link of unmatched board as follow, the U740-C000 manual would be present
in the same page later.

    https://www.sifive.com/boards/hifive-unmatched

Passes dt_binding_check.

Signed-off-by: Zong Li <zong.li@sifive.com>
Link: https://lore.kernel.org/r/20201126030043.67390-1-zong.li@sifive.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-15 19:21:49 -08:00
Vinod Koul
eb50f3f42c dt-bindings: clock: Add RPMHCC bindings for SM8350
Add bindings and update documentation for clock rpmh driver on SM8350.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20201208064702.3654324-2-vkoul@kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:44:31 -08:00
Yoshihiro Shimoda
f5c50b1fed dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
Convert Renesas R-Car USB 2.0 clock selector bindings documentation
to json-schema.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1604543524-31482-1-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-12-10 08:34:01 +01:00
Greg Kroah-Hartman
54bf54c859 Merge tag 'phy-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes:

phy-for-5.11

 - New phy drivers:
   - Mediatek MT7621 PCIe PHY (promoted from staging)
   - Ingenic USB phy driver supporting JZ4775 and X2000
   - Intel Keem Bay USB PHY driver
   - Marvell USB HSIC PHY driver supporting MMP3 SoC
   - AXG MIPI D-PHY driver

 - Updates:
   - Conversion to YAML binding for:
	- Broadcom SATA PHY
	- Cadence Sierra PHY bindings
	- STM32 USBC Phy
   - Support for Exynos5433 PCIe PHY
   - Support for Qualcomm SM8250 PCIe QMP PHY
   - Support for Exynos5420 USB2 phy
   - devm_platform_ioremap_resource conversion for bunch of drivers

* tag 'phy-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits)
  drm/mediatek: avoid dereferencing a null hdmi_phy on an error message
  phy: ingenic: depend on HAS_IOMEM
  phy: mediatek: statify mtk_hdmi_phy_driver
  dt-bindings: phy: Convert Broadcom SATA PHY to YAML
  devicetree: phy: rockchip-emmc add output-tapdelay-select
  phy: rockchip-emmc: output tap delay dt property
  PHY: Ingenic: Add USB PHY driver using generic PHY framework.
  dt-bindings: USB: Add bindings for Ingenic JZ4775 and X2000.
  USB: PHY: JZ4770: Remove unnecessary function calls.
  devicetree: phy: rockchip-emmc: pulldown property
  phy: rockchip: set pulldown for strobe line in dts
  phy: renesas: rcar-gen3-usb2: disable runtime pm in case of failure
  phy: mediatek: allow compile-testing the hdmi phy
  phy/rockchip: Make PHY_ROCKCHIP_INNO_HDMI depend on HAS_IOMEM to fix build error
  phy: samsung: Merge Kconfig for Exynos5420 and Exynos5250
  phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro
  phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig
  phy: mediatek: Make PHY_MTK_{XSPHY, TPHY} depend on HAS_IOMEM and OF_ADDRESS to fix build errors
  phy: tegra: xusb: Fix usb_phy device driver field
  phy: amlogic: replace devm_reset_control_array_get()
  ...
2020-12-09 14:26:40 +01:00
Arnd Bergmann
3eaac3aed2 Merge tag 'imx-bindings-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT bindings update for 5.11:

- Quite some patches that update vendor-prefixes.yaml and fsl.yaml to
  document missing board compatibles and add new board compatibles.
- A couple of patches from Dong Aisheng to update imx-scu firmware and
  imx-lpcg clock bindings for new SCU two cells clock support.
- A couple of net bindings update from Ioana Ciornei to complete the
  MAC/PCS/PHY representation on DPAA2 devices.
- Document watchdog compatibles for all i.MX and Layerscape devices.

* tag 'imx-bindings-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (35 commits)
  dt-bindings: arm: fsl: add Protonic WD3 board
  dt-bindings: vendor-prefixes: add "virtual" prefix
  dt-bindings: fsl: add kamstrup flex concentrator to schema
  dt-bindings: arm: fsl: document i.MX7S boards
  dt-bindings: arm: fsl: document SolidRun LX2160A boards
  dt-bindings: arm: fsl: document LS1012A FRWY board
  dt-bindings: arm: fsl: add Van der Laan LANMCU board
  dt-bindings: arm: fsl: add Altesco I6P board
  dt-bindings: vendor-prefixes: Add an entry for Altus-Escon-Company
  dt-bindings: net: add the 10gbase-r connection type
  dt-bindings: net: add the DPAA2 MAC DTS definition
  dt-bindings: fsl: add compatible for LX2162A QDS Board
  dt-bindings: vendor-prefixes: Add an entry for Van der Laan b.v.
  dt-bindings: arm: fsl: document i.MX7D boards
  dt-bindings: arm: fsl: document i.MX6ULL boards
  dt-bindings: arm: fsl: document i.MX6UL boards
  dt-bindings: arm: fsl: document i.MX6SX boards
  dt-bindings: arm: fsl: document i.MX6SL boards
  dt-bindings: arm: fsl: document i.MX6QP boards
  dt-bindings: arm: fsl: document i.MX6Q boards
  ...

Link: https://lore.kernel.org/r/20201202142717.9262-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-08 23:57:15 +01:00
Vinod Koul
2e2639b7ef dt-bindings: clock: Introduce RPMHCC bindings for SDX55
Add compatible for SDX55 RPMHCC and DT include.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201126072844.35370-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 17:00:14 -08:00
Vinod Koul
a13ae5a379 dt-bindings: clock: Add SDX55 GCC clock bindings
Add device tree bindings for global clock controller on SDX55 SoCs.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201126072844.35370-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 16:59:58 -08:00
Michael Walle
e577af82c7 dt-bindings: clock: document the fsl-flexspi-clk device
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201108185113.31377-7-michael@walle.cc
[sboyd@kernel.org: DT bindings aren't drivers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 16:55:08 -08:00
周琰杰 (Zhou Yanjie)
4f6ecfaf3e dt-bindings: USB: Add bindings for Ingenic JZ4775 and X2000.
Move Ingenic USB PHY bindings from Documentation/devicetree/bindings/usb
to Documentation/devicetree/bindings/phy, and add bindings for JZ4775 SoC
and X2000 SoC.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201116141906.11758-3-zhouyanjie@wanyeetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-12-05 13:39:30 +05:30
Marc Kleine-Budde
bdac39a3bd dt-bindings: clock: imx5: fix example
Since commit:

    0e030a373d ("can: flexcan: fix endianess detection")

the fsl,imx53-flexcan isn't compatible with the fsl,p1010-flexcan any more. As
the former accesses the IP core in Little Endian mode and the latter uses Big
Endian mode.

With the conversion of the flexcan DT bindings to yaml, the dt_binding_check
this throws the following error:

Documentation/devicetree/bindings/clock/imx5-clock.example.dt.yaml: can@53fc8000: compatible: 'oneOf' conditional failed, one must be fixed:
	['fsl,imx53-flexcan', 'fsl,p1010-flexcan'] is too long
	Additional items are not allowed ('fsl,p1010-flexcan' was unexpected)
	'fsl,imx53-flexcan' is not one of ['fsl,imx7d-flexcan', 'fsl,imx6ul-flexcan', 'fsl,imx6sx-flexcan']
	'fsl,imx53-flexcan' is not one of ['fsl,ls1028ar1-flexcan']
	'fsl,imx6q-flexcan' was expected
	'fsl,lx2160ar1-flexcan' was expected
	From schema: /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml

The error is fixed by replacing the "fsl,p1010-flexcan" compatible
(which turned out the be incompatible) with "fsl,imx25-flexcan" in the
binding example.

Reported-by: Rob Herring <robh+dt@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20201111213548.1621094-1-mkl@pengutronix.de
[robh: Add "fsl,imx25-flexcan" as fallback]
Signed-off-by: Rob Herring <robh@kernel.org>
2020-11-13 08:49:59 -06:00
Srinivas Kandagatla
7dbe5a7a3f dt-bindings: clock: Add support for LPASS Always ON Controller
Always ON Clock controller is a block inside LPASS which controls
1 Glitch free muxes to LPASS codec Macros.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20201026120221.18984-3-srinivas.kandagatla@linaro.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:34:54 -08:00