Eric Yang 0beb54039d drm/amd/display: update dispclk and dppclk vco frequency ...

Value obtained from DV is not allowing 8k60 CTA mode with DSC to
pass, after checking real value being used in hw, find out that
correct value is 3600, which will allow that mode.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-12-05 16:32:18 -05:00

..

drm

drm/amd/display: update dispclk and dppclk vco frequency

2019-12-05 16:32:18 -05:00

host1x

gpu: host1x: Unconditionally select IOMMU_IOVA

2019-11-01 10:49:17 +01:00

ipu-v3

gpu: ipu-v3: image-convert: only sample into the next tile if necessary

2019-08-19 16:25:30 +02:00

vga

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Makefile

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