Ville Syrjälä 1abc4dc7e2
drm/i915: Parametrize VLV_DDL registers ...
The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.
Note that we now fill out the drain latency for pipe C on CHV which we
didn't do before. The rest of the pipe C watermarks are still untouched
but that will be remedied later by adding a proper cherryview_update_wm()
function.
v2: Add a note about CHV pipe C changes (Paulo)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
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1abc4dc7e2