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linux/arch/riscv/lib
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Samuel Holland d5a7fab785
riscv: Fix Zbb alternative IDs 
Commit 4bf8860760 ("riscv: cpufeature: extend
riscv_cpufeature_patch_func to all ISA extensions") switched ISA
extension alternatives to use the RISCV_ISA_EXT_* macros instead of
CPUFEATURE_*. This was mismerged when applied on top of the Zbb series,
so the Zbb alternatives referenced the wrong errata ID values.

Fixes: 9daca9a5b9 ("Merge patch series "riscv: improve boot time isa extensions handling"")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230212021534.59121-3-samuel@sholland.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
 		2023-02-14 16:10:36 -08:00
..
Makefile RISC-V: add infrastructure to allow different str* implementations 2023-01-31 11:43:23 -08:00
delay.c include/linux/delay.h: replace kernel.h with the necessary inclusions 2021-11-09 10:02:49 -08:00
error-inject.c riscv: Add support for function error injection 2021-01-14 15:09:09 -08:00
memcpy.S riscv: Add KASAN support 2020-01-22 13:09:58 -08:00
memmove.S riscv: Fixed misaligned memory access. Fixed pointer comparison. 2022-03-10 10:24:04 -08:00
memset.S riscv: Add KASAN support 2020-01-22 13:09:58 -08:00
strcmp.S riscv: Fix Zbb alternative IDs 2023-02-14 16:10:36 -08:00
strlen.S riscv: Fix Zbb alternative IDs 2023-02-14 16:10:36 -08:00
strncmp.S riscv: Fix Zbb alternative IDs 2023-02-14 16:10:36 -08:00
tishift.S riscv: Less inefficient gcc tishift helpers (and export their symbols) 2020-01-18 19:13:41 -08:00
uaccess.S riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit 2022-08-10 14:06:31 -07:00