Ville Syrjälä 27e639bf02
drm/i915: Make sure we respect n.max on VLV ...
We limit the maximum n divider value in order to make sure the PLL's
reference inout is at least 19.2 MHz. I assume that is done to satisfy
some hardware requirement.
However we never check whether that calculated limit is below the
maximum supoorted N divider value (7). In practice that is always true
since we only support 100 MHz reference clock, but making the code
safe against higher reference clocks seems like a reasoanble thing to
do.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
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