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Srinivas Pandruvada 5a43b87b3c x86/mce/therm_throt: Mask out read-only and reserved MSR bits 
While writing to MSR IA32_THERM_STATUS/IA32_PKG_THERM_STATUS, avoid
writing 1 to read only and reserved fields because updating some fields
generates exception.

 [ bp: Vertically align for better readability. ]

Fixes: f6656208f0 ("x86/mce/therm_throt: Optimize notifications of thermal throttle")
Reported-by: Dominik Brodowski <linux@dominikbrodowski.net>
Tested-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20191128150824.22413-1-srinivas.pandruvada@linux.intel.com
 		2019-11-29 09:17:52 +01:00
..
Makefile
…
amd.c x86/mce/amd: Make disable_err_thresholding() static 2019-10-01 11:42:59 +02:00
apei.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333 2019-06-05 17:37:06 +02:00
core.c x86/mce: Add Zhaoxin LMCE support 2019-10-01 12:33:33 +02:00
dev-mcelog.c treewide: Add SPDX license identifier for missed files 2019-05-21 10:50:45 +02:00
genpool.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 437 2019-06-05 17:37:17 +02:00
inject.c x86/mce: Do not check return value of debugfs_create functions 2019-06-14 16:04:21 +02:00
intel.c x86/mce: Add Xeon Icelake to list of CPUs that support PPIN 2019-11-01 17:29:36 +01:00
internal.h x86/mce: Add Zhaoxin LMCE support 2019-10-01 12:33:33 +02:00
p5.c
…
severity.c x86/mce: Don't check for the overflow bit on action optional machine checks 2019-08-05 09:34:02 +02:00
therm_throt.c x86/mce/therm_throt: Mask out read-only and reserved MSR bits 2019-11-29 09:17:52 +01:00
threshold.c
…
winchip.c
…