mirror
/
linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
linux/arch/riscv/boot/dts/microchip
History
Conor Dooley 0dec364ffe riscv: dts: microchip: use an mpfs specific l2 compatible 
PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:

mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long

Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3ae ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
 		2022-08-31 16:57:51 +01:00
..
Makefile riscv: dts: microchip: add the sundance polarberry 2022-06-01 15:28:29 -07:00
mpfs-icicle-kit-fabric.dtsi riscv: dts: microchip: make the fabric dtsi board specific 2022-06-01 15:28:11 -07:00
mpfs-icicle-kit.dts riscv: dts: microchip: mpfs: remove bogus card-detect-delay 2022-08-23 22:15:54 +01:00
mpfs-polarberry-fabric.dtsi riscv: dts: microchip: add the sundance polarberry 2022-06-01 15:28:29 -07:00
mpfs-polarberry.dts riscv: dts: microchip: mpfs: remove bogus card-detect-delay 2022-08-23 22:15:54 +01:00
mpfs.dtsi riscv: dts: microchip: use an mpfs specific l2 compatible 2022-08-31 16:57:51 +01:00