Divy Le Ray 480fe1a31c
cxgb3 - TP SRAM update ...
The chip executes microcode present in internal RAM,
whose content is loaded from EEPROM on power cycle.
This patch allows an update of the microcode through PIO
without forcing a power cycle.
Signed-off-by: Divy Le Ray <divy@chelsio.com >
Signed-off-by: Jeff Garzik <jeff@garzik.org >
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2007-07-06 10:23:43 -07:00
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480fe1a31c