3e7bf4685e
Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
||
|---|---|---|
| .. | ||
| andestech,ax45mp-cache.yaml | ||
| baikal,bt1-l2-ctl.yaml | ||
| freescale-l2cache.txt | ||
| l2c2x0.yaml | ||
| marvell,feroceon-cache.txt | ||
| marvell,tauros2-cache.txt | ||
| qcom,llcc.yaml | ||
| sifive,ccache0.yaml | ||
| socionext,uniphier-system-cache.yaml | ||