Chon Ming Lee 65ce4bf5a1 drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2 ...

For DP pll settings, there is only two golden configs.  Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.

v2: Rework on the intel_limit compiler warning. (Jani)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2013-09-04 17:34:58 +02:00

..

drm

drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

2013-09-04 17:34:58 +02:00

host1x

drm/tegra: fix up page flip flags.

2013-09-02 09:47:56 +10:00

vga

vgaarb: Fix VGA decodes changes

2013-09-03 19:17:59 +02:00

Makefile

gpu: host1x: Add host1x driver

2013-04-22 12:32:40 +02:00